[D]

1. D
2. D0
3. D0CPF_INT
4. D0CSF_INT
5. D0EPCTL_MPS_16
6. D0EPCTL_MPS_32
7. D0EPCTL_MPS_64
8. D0EPCTL_MPS_8
9. D0EPCTL_MPS_MASK
10. D0EPCTL_MPS_SHIFT
11. D0FIFO
12. D0FIFOCTR
13. D0FIFOSEL
14. D0I3_END_CMD
15. D0S_PRE
16. D0S_PREP
17. D0S_ZERO
18. D0TIM
19. D0W_CNTRL
20. D0W_DPHYCONTRX
21. D0W_DPHYCONTTX
22. D0_MARK
23. D0_NAF0_MARK
24. D1
25. D10
26. D10_2
27. D10_2_DATA_k
28. D10_MARK
29. D10_NAF10_MARK
30. D11
31. D11A_PHY_HDR_GLENGTH
32. D11A_PHY_HDR_GPARITY
33. D11A_PHY_HDR_GRATE
34. D11A_PHY_HDR_GRES
35. D11A_PHY_HDR_GTAIL
36. D11A_PHY_HDR_LEN_L
37. D11A_PHY_HDR_LEN_R
38. D11A_PHY_HDR_SLENGTH
39. D11A_PHY_HDR_SRATE
40. D11A_PHY_HDR_SRES
41. D11A_PHY_HDR_STAIL
42. D11A_PHY_HDR_TIME
43. D11A_PHY_PREHDR_TIME
44. D11A_PHY_PRE_TIME
45. D11A_PHY_TX_DELAY
46. D11B_PHY_HDR_LEN
47. D11B_PHY_LHDR_TIME
48. D11B_PHY_LPREHDR_TIME
49. D11B_PHY_LPRE_TIME
50. D11B_PHY_SHDR_TIME
51. D11B_PHY_SPREHDR_TIME
52. D11B_PHY_SPRE_TIME
53. D11B_PHY_TX_DELAY
54. D11B_PLCP_SIGNAL_LE
55. D11B_PLCP_SIGNAL_LOCKED
56. D11CONF
57. D11CONF_GE
58. D11CONF_GT
59. D11CONF_HAS
60. D11CONF_IS
61. D11CONF_LE
62. D11CONF_LT
63. D11CONF_MSK
64. D11LCN0BSINITVALS24
65. D11LCN0INITVALS24
66. D11LCN1BSINITVALS24
67. D11LCN1INITVALS24
68. D11LCN2BSINITVALS24
69. D11LCN2INITVALS24
70. D11N0ABSINITVALS16
71. D11N0BSINITVALS16
72. D11N0INITVALS16
73. D11REGOFFS
74. D11REV_GE
75. D11REV_GT
76. D11REV_IS
77. D11REV_LE
78. D11REV_LT
79. D11UCODE_NAMETAG_START
80. D11UCODE_OVERSIGHT16_MIMO
81. D11UCODE_OVERSIGHT16_MIMOSZ
82. D11UCODE_OVERSIGHT24_LCN
83. D11UCODE_OVERSIGHT24_LCNSZ
84. D11UCODE_OVERSIGHT_BOMMAJOR
85. D11UCODE_OVERSIGHT_BOMMINOR
86. D11_BCMA_IOCTL_PHYCLOCKEN
87. D11_BCMA_IOCTL_PHYRESET
88. D11_CURCHANNEL_40
89. D11_CURCHANNEL_5G
90. D11_CURCHANNEL_MAX
91. D11_MARK
92. D11_MAX_KEY_SIZE
93. D11_MAX_SSID_LEN
94. D11_MAX_TX_FRMS
95. D11_NAF11_MARK
96. D11_PHY_HDR_LEN
97. D11_TXH_LEN
98. D12
99. D12_MARK
100. D12_NAF12_MARK
101. D13
102. D13_MARK
103. D13_NAF13_MARK
104. D14
105. D14_MARK
106. D14_NAF14_MARK
107. D15
108. D15_MARK
109. D15_NAF15_MARK
110. D16
111. D16_MARK
112. D17
113. D17_MARK
114. D18
115. D18_MARK
116. D19
117. D19_1610_KBC2
118. D19_MARK
119. D1CPF_INT
120. D1CRTC_CONTROL
121. D1CRTC_STATUS
122. D1CRTC_UPDATE_LOCK
123. D1CSF_INT
124. D1D
125. D1FIFO
126. D1FIFOCTR
127. D1FIFOSEL
128. D1GRPH_INTERRUPT_CONTROL
129. D1GRPH_INTERRUPT_STATUS
130. D1GRPH_PRIMARY_SURFACE_ADDRESS
131. D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
132. D1GRPH_SECONDARY_SURFACE_ADDRESS
133. D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
134. D1MODE_PRIORITY_A_CNT
135. D1MODE_PRIORITY_B_CNT
136. D1MODE_VBLANK_INT_MASK
137. D1MODE_VBLANK_STATUS
138. D1MODE_VLINE_INT_MASK
139. D1MODE_VLINE_STATUS
140. D1S
141. D1SRAM1_CK
142. D1S_PRE
143. D1S_PREP
144. D1S_ZERO
145. D1TIM
146. D1VGA_CONTROL
147. D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK
148. D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT
149. D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK
150. D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT
151. D1VGA_CONTROL__D1VGA_ROTATE_MASK
152. D1VGA_CONTROL__D1VGA_ROTATE__SHIFT
153. D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK
154. D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT
155. D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK
156. D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT
157. D1W_CNTRL
158. D1W_DPHYCONTRX
159. D1_MARK
160. D1_NAF1_MARK
161. D2
162. D20
163. D20_1610_KBC1
164. D20_20
165. D20_MARK
166. D21
167. D21_MARK
168. D22
169. D22_MARK
170. D23
171. D23_MARK
172. D24
173. D24_MARK
174. D25_MARK
175. D26
176. D2620
177. D2633
178. D26_MARK
179. D27_MARK
180. D28_MARK
181. D29_MARK
182. D2C
183. D2CRTC_CONTROL
184. D2CRTC_STATUS
185. D2CRTC_UPDATE_LOCK
186. D2D
187. D2D3_INTF_CTRL0
188. D2D3_INTF_LENGTH
189. D2F1_BASE_CLASS__BASE_CLASS_MASK
190. D2F1_BASE_CLASS__BASE_CLASS__SHIFT
191. D2F1_BIST__BIST_CAP_MASK
192. D2F1_BIST__BIST_CAP__SHIFT
193. D2F1_BIST__BIST_COMP_MASK
194. D2F1_BIST__BIST_COMP__SHIFT
195. D2F1_BIST__BIST_STRT_MASK
196. D2F1_BIST__BIST_STRT__SHIFT
197. D2F1_CACHE_LINE__CACHE_LINE_SIZE_MASK
198. D2F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
199. D2F1_CAP_PTR__CAP_PTR_MASK
200. D2F1_CAP_PTR__CAP_PTR__SHIFT
201. D2F1_COMMAND__AD_STEPPING_MASK
202. D2F1_COMMAND__AD_STEPPING__SHIFT
203. D2F1_COMMAND__BUS_MASTER_EN_MASK
204. D2F1_COMMAND__BUS_MASTER_EN__SHIFT
205. D2F1_COMMAND__FAST_B2B_EN_MASK
206. D2F1_COMMAND__FAST_B2B_EN__SHIFT
207. D2F1_COMMAND__INT_DIS_MASK
208. D2F1_COMMAND__INT_DIS__SHIFT
209. D2F1_COMMAND__IO_ACCESS_EN_MASK
210. D2F1_COMMAND__IO_ACCESS_EN__SHIFT
211. D2F1_COMMAND__MEM_ACCESS_EN_MASK
212. D2F1_COMMAND__MEM_ACCESS_EN__SHIFT
213. D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
214. D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
215. D2F1_COMMAND__PAL_SNOOP_EN_MASK
216. D2F1_COMMAND__PAL_SNOOP_EN__SHIFT
217. D2F1_COMMAND__PARITY_ERROR_RESPONSE_MASK
218. D2F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
219. D2F1_COMMAND__SERR_EN_MASK
220. D2F1_COMMAND__SERR_EN__SHIFT
221. D2F1_COMMAND__SPECIAL_CYCLE_EN_MASK
222. D2F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
223. D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
224. D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
225. D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
226. D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
227. D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
228. D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
229. D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
230. D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
231. D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
232. D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
233. D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
234. D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
235. D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
236. D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
237. D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
238. D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
239. D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
240. D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
241. D2F1_DEVICE_CAP2__LTR_SUPPORTED_MASK
242. D2F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
243. D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
244. D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
245. D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
246. D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
247. D2F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
248. D2F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
249. D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
250. D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
251. D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
252. D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
253. D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
254. D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
255. D2F1_DEVICE_CAP__EXTENDED_TAG_MASK
256. D2F1_DEVICE_CAP__EXTENDED_TAG__SHIFT
257. D2F1_DEVICE_CAP__FLR_CAPABLE_MASK
258. D2F1_DEVICE_CAP__FLR_CAPABLE__SHIFT
259. D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
260. D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
261. D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
262. D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
263. D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
264. D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
265. D2F1_DEVICE_CAP__PHANTOM_FUNC_MASK
266. D2F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
267. D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
268. D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
269. D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
270. D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
271. D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
272. D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
273. D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
274. D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
275. D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
276. D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
277. D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
278. D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
279. D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
280. D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
281. D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
282. D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
283. D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
284. D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
285. D2F1_DEVICE_CNTL2__LTR_EN_MASK
286. D2F1_DEVICE_CNTL2__LTR_EN__SHIFT
287. D2F1_DEVICE_CNTL2__OBFF_EN_MASK
288. D2F1_DEVICE_CNTL2__OBFF_EN__SHIFT
289. D2F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
290. D2F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
291. D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
292. D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
293. D2F1_DEVICE_CNTL__CORR_ERR_EN_MASK
294. D2F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
295. D2F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
296. D2F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
297. D2F1_DEVICE_CNTL__FATAL_ERR_EN_MASK
298. D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
299. D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
300. D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
301. D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
302. D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
303. D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
304. D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
305. D2F1_DEVICE_CNTL__NO_SNOOP_EN_MASK
306. D2F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
307. D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
308. D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
309. D2F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
310. D2F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
311. D2F1_DEVICE_CNTL__USR_REPORT_EN_MASK
312. D2F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
313. D2F1_DEVICE_ID__DEVICE_ID_MASK
314. D2F1_DEVICE_ID__DEVICE_ID__SHIFT
315. D2F1_DEVICE_STATUS2__RESERVED_MASK
316. D2F1_DEVICE_STATUS2__RESERVED__SHIFT
317. D2F1_DEVICE_STATUS__AUX_PWR_MASK
318. D2F1_DEVICE_STATUS__AUX_PWR__SHIFT
319. D2F1_DEVICE_STATUS__CORR_ERR_MASK
320. D2F1_DEVICE_STATUS__CORR_ERR__SHIFT
321. D2F1_DEVICE_STATUS__FATAL_ERR_MASK
322. D2F1_DEVICE_STATUS__FATAL_ERR__SHIFT
323. D2F1_DEVICE_STATUS__NON_FATAL_ERR_MASK
324. D2F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
325. D2F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
326. D2F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
327. D2F1_DEVICE_STATUS__USR_DETECTED_MASK
328. D2F1_DEVICE_STATUS__USR_DETECTED__SHIFT
329. D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
330. D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
331. D2F1_HEADER__DEVICE_TYPE_MASK
332. D2F1_HEADER__DEVICE_TYPE__SHIFT
333. D2F1_HEADER__HEADER_TYPE_MASK
334. D2F1_HEADER__HEADER_TYPE__SHIFT
335. D2F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
336. D2F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
337. D2F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
338. D2F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
339. D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
340. D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
341. D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
342. D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
343. D2F1_IO_BASE_LIMIT__IO_BASE_MASK
344. D2F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
345. D2F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
346. D2F1_IO_BASE_LIMIT__IO_BASE__SHIFT
347. D2F1_IO_BASE_LIMIT__IO_LIMIT_MASK
348. D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
349. D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
350. D2F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
351. D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
352. D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
353. D2F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
354. D2F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
355. D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
356. D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
357. D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
358. D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
359. D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
360. D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
361. D2F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
362. D2F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
363. D2F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
364. D2F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
365. D2F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
366. D2F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
367. D2F1_LATENCY__LATENCY_TIMER_MASK
368. D2F1_LATENCY__LATENCY_TIMER__SHIFT
369. D2F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
370. D2F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
371. D2F1_LINK_CAP2__RESERVED_MASK
372. D2F1_LINK_CAP2__RESERVED__SHIFT
373. D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
374. D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
375. D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
376. D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
377. D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
378. D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
379. D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
380. D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
381. D2F1_LINK_CAP__L0S_EXIT_LATENCY_MASK
382. D2F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
383. D2F1_LINK_CAP__L1_EXIT_LATENCY_MASK
384. D2F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
385. D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
386. D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
387. D2F1_LINK_CAP__LINK_SPEED_MASK
388. D2F1_LINK_CAP__LINK_SPEED__SHIFT
389. D2F1_LINK_CAP__LINK_WIDTH_MASK
390. D2F1_LINK_CAP__LINK_WIDTH__SHIFT
391. D2F1_LINK_CAP__PM_SUPPORT_MASK
392. D2F1_LINK_CAP__PM_SUPPORT__SHIFT
393. D2F1_LINK_CAP__PORT_NUMBER_MASK
394. D2F1_LINK_CAP__PORT_NUMBER__SHIFT
395. D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
396. D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
397. D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
398. D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
399. D2F1_LINK_CNTL2__COMPLIANCE_SOS_MASK
400. D2F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
401. D2F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
402. D2F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
403. D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
404. D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
405. D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
406. D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
407. D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
408. D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
409. D2F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
410. D2F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
411. D2F1_LINK_CNTL2__XMIT_MARGIN_MASK
412. D2F1_LINK_CNTL2__XMIT_MARGIN__SHIFT
413. D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
414. D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
415. D2F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
416. D2F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
417. D2F1_LINK_CNTL__EXTENDED_SYNC_MASK
418. D2F1_LINK_CNTL__EXTENDED_SYNC__SHIFT
419. D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
420. D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
421. D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
422. D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
423. D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
424. D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
425. D2F1_LINK_CNTL__LINK_DIS_MASK
426. D2F1_LINK_CNTL__LINK_DIS__SHIFT
427. D2F1_LINK_CNTL__PM_CONTROL_MASK
428. D2F1_LINK_CNTL__PM_CONTROL__SHIFT
429. D2F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
430. D2F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
431. D2F1_LINK_CNTL__RETRAIN_LINK_MASK
432. D2F1_LINK_CNTL__RETRAIN_LINK__SHIFT
433. D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
434. D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
435. D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
436. D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
437. D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
438. D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
439. D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
440. D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
441. D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
442. D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
443. D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
444. D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
445. D2F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
446. D2F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
447. D2F1_LINK_STATUS__DL_ACTIVE_MASK
448. D2F1_LINK_STATUS__DL_ACTIVE__SHIFT
449. D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
450. D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
451. D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
452. D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
453. D2F1_LINK_STATUS__LINK_TRAINING_MASK
454. D2F1_LINK_STATUS__LINK_TRAINING__SHIFT
455. D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
456. D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
457. D2F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
458. D2F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
459. D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
460. D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
461. D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
462. D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
463. D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
464. D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
465. D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
466. D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
467. D2F1_MSI_CAP_LIST__CAP_ID_MASK
468. D2F1_MSI_CAP_LIST__CAP_ID__SHIFT
469. D2F1_MSI_CAP_LIST__NEXT_PTR_MASK
470. D2F1_MSI_CAP_LIST__NEXT_PTR__SHIFT
471. D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
472. D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
473. D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
474. D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
475. D2F1_MSI_MAP_CAP_LIST__CAP_ID_MASK
476. D2F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
477. D2F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
478. D2F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
479. D2F1_MSI_MAP_CAP__CAP_TYPE_MASK
480. D2F1_MSI_MAP_CAP__CAP_TYPE__SHIFT
481. D2F1_MSI_MAP_CAP__EN_MASK
482. D2F1_MSI_MAP_CAP__EN__SHIFT
483. D2F1_MSI_MAP_CAP__FIXD_MASK
484. D2F1_MSI_MAP_CAP__FIXD__SHIFT
485. D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
486. D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
487. D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
488. D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
489. D2F1_MSI_MSG_CNTL__MSI_64BIT_MASK
490. D2F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
491. D2F1_MSI_MSG_CNTL__MSI_EN_MASK
492. D2F1_MSI_MSG_CNTL__MSI_EN__SHIFT
493. D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
494. D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
495. D2F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
496. D2F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
497. D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
498. D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
499. D2F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
500. D2F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
501. D2F1_MSI_MSG_DATA__MSI_DATA_MASK
502. D2F1_MSI_MSG_DATA__MSI_DATA__SHIFT
503. D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
504. D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
505. D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
506. D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
507. D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
508. D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
509. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
510. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
511. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
512. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
513. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
514. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
515. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
516. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
517. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
518. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
519. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
520. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
521. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
522. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
523. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
524. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
525. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
526. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
527. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
528. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
529. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
530. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
531. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
532. D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
533. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
534. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
535. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
536. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
537. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
538. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
539. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
540. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
541. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
542. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
543. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
544. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
545. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
546. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
547. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
548. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
549. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
550. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
551. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
552. D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
553. D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
554. D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
555. D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
556. D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
557. D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
558. D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
559. D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
560. D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
561. D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
562. D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
563. D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
564. D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
565. D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
566. D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
567. D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
568. D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
569. D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
570. D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
571. D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
572. D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
573. D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
574. D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
575. D2F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK
576. D2F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
577. D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
578. D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
579. D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
580. D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
581. D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
582. D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
583. D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
584. D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
585. D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
586. D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
587. D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
588. D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
589. D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
590. D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
591. D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
592. D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
593. D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
594. D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
595. D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
596. D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
597. D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
598. D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
599. D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
600. D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
601. D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
602. D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
603. D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
604. D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
605. D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
606. D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
607. D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
608. D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
609. D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
610. D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
611. D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
612. D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
613. D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
614. D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
615. D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
616. D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
617. D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
618. D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
619. D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
620. D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
621. D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
622. D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
623. D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
624. D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
625. D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
626. D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
627. D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
628. D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
629. D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
630. D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
631. D2F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK
632. D2F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
633. D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
634. D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
635. D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
636. D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
637. D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
638. D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
639. D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
640. D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
641. D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
642. D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
643. D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
644. D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
645. D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
646. D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
647. D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
648. D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
649. D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
650. D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
651. D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
652. D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
653. D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
654. D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
655. D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
656. D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
657. D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
658. D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
659. D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
660. D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
661. D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
662. D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
663. D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
664. D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
665. D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
666. D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
667. D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
668. D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
669. D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
670. D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
671. D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
672. D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
673. D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
674. D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
675. D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
676. D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
677. D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
678. D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
679. D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
680. D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
681. D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
682. D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
683. D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
684. D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
685. D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
686. D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
687. D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
688. D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
689. D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
690. D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
691. D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
692. D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
693. D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
694. D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
695. D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
696. D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
697. D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
698. D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
699. D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
700. D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
701. D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
702. D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
703. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
704. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
705. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
706. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
707. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
708. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
709. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
710. D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
711. D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
712. D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
713. D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
714. D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
715. D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
716. D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
717. D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
718. D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
719. D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
720. D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
721. D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
722. D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
723. D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
724. D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
725. D2F1_PCIE_CAP_LIST__CAP_ID_MASK
726. D2F1_PCIE_CAP_LIST__CAP_ID__SHIFT
727. D2F1_PCIE_CAP_LIST__NEXT_PTR_MASK
728. D2F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
729. D2F1_PCIE_CAP__DEVICE_TYPE_MASK
730. D2F1_PCIE_CAP__DEVICE_TYPE__SHIFT
731. D2F1_PCIE_CAP__INT_MESSAGE_NUM_MASK
732. D2F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
733. D2F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
734. D2F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
735. D2F1_PCIE_CAP__VERSION_MASK
736. D2F1_PCIE_CAP__VERSION__SHIFT
737. D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
738. D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
739. D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
740. D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
741. D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
742. D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
743. D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
744. D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
745. D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
746. D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
747. D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
748. D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
749. D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
750. D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
751. D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
752. D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
753. D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
754. D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
755. D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
756. D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
757. D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
758. D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
759. D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
760. D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
761. D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
762. D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
763. D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
764. D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
765. D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
766. D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
767. D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
768. D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
769. D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
770. D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
771. D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
772. D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
773. D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
774. D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
775. D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
776. D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
777. D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
778. D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
779. D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
780. D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
781. D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
782. D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
783. D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
784. D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
785. D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
786. D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
787. D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
788. D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
789. D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
790. D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
791. D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
792. D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
793. D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
794. D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
795. D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
796. D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
797. D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
798. D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
799. D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
800. D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
801. D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
802. D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
803. D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
804. D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
805. D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
806. D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
807. D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
808. D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
809. D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
810. D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
811. D2F1_PCIE_FC_CPL__CPLD_CREDITS_MASK
812. D2F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
813. D2F1_PCIE_FC_CPL__CPLH_CREDITS_MASK
814. D2F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
815. D2F1_PCIE_FC_NP__NPD_CREDITS_MASK
816. D2F1_PCIE_FC_NP__NPD_CREDITS__SHIFT
817. D2F1_PCIE_FC_NP__NPH_CREDITS_MASK
818. D2F1_PCIE_FC_NP__NPH_CREDITS__SHIFT
819. D2F1_PCIE_FC_P__PD_CREDITS_MASK
820. D2F1_PCIE_FC_P__PD_CREDITS__SHIFT
821. D2F1_PCIE_FC_P__PH_CREDITS_MASK
822. D2F1_PCIE_FC_P__PH_CREDITS__SHIFT
823. D2F1_PCIE_HDR_LOG0__TLP_HDR_MASK
824. D2F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
825. D2F1_PCIE_HDR_LOG1__TLP_HDR_MASK
826. D2F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
827. D2F1_PCIE_HDR_LOG2__TLP_HDR_MASK
828. D2F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
829. D2F1_PCIE_HDR_LOG3__TLP_HDR_MASK
830. D2F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
831. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
832. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
833. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
834. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
835. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
836. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
837. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
838. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
839. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
840. D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
841. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
842. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
843. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
844. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
845. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
846. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
847. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
848. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
849. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
850. D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
851. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
852. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
853. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
854. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
855. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
856. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
857. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
858. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
859. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
860. D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
861. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
862. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
863. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
864. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
865. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
866. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
867. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
868. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
869. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
870. D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
871. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
872. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
873. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
874. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
875. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
876. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
877. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
878. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
879. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
880. D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
881. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
882. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
883. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
884. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
885. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
886. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
887. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
888. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
889. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
890. D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
891. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
892. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
893. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
894. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
895. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
896. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
897. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
898. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
899. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
900. D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
901. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
902. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
903. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
904. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
905. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
906. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
907. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
908. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
909. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
910. D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
911. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
912. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
913. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
914. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
915. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
916. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
917. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
918. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
919. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
920. D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
921. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
922. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
923. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
924. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
925. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
926. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
927. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
928. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
929. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
930. D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
931. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
932. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
933. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
934. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
935. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
936. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
937. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
938. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
939. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
940. D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
941. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
942. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
943. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
944. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
945. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
946. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
947. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
948. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
949. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
950. D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
951. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
952. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
953. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
954. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
955. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
956. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
957. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
958. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
959. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
960. D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
961. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
962. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
963. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
964. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
965. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
966. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
967. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
968. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
969. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
970. D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
971. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
972. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
973. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
974. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
975. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
976. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
977. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
978. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
979. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
980. D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
981. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
982. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
983. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
984. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
985. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
986. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
987. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
988. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
989. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
990. D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
991. D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
992. D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
993. D2F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
994. D2F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
995. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
996. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
997. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
998. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
999. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
1000. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
1001. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
1002. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
1003. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
1004. D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
1005. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
1006. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
1007. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
1008. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
1009. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
1010. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
1011. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
1012. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
1013. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
1014. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
1015. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
1016. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
1017. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
1018. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
1019. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
1020. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
1021. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
1022. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
1023. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
1024. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
1025. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
1026. D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
1027. D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
1028. D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
1029. D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
1030. D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
1031. D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
1032. D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
1033. D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
1034. D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
1035. D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
1036. D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
1037. D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
1038. D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
1039. D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
1040. D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
1041. D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
1042. D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
1043. D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
1044. D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
1045. D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
1046. D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
1047. D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
1048. D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
1049. D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
1050. D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
1051. D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
1052. D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
1053. D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
1054. D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
1055. D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
1056. D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
1057. D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
1058. D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
1059. D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
1060. D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
1061. D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
1062. D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
1063. D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
1064. D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
1065. D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
1066. D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
1067. D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
1068. D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
1069. D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
1070. D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
1071. D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
1072. D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
1073. D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
1074. D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
1075. D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
1076. D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
1077. D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
1078. D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
1079. D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
1080. D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
1081. D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
1082. D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
1083. D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
1084. D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
1085. D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
1086. D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
1087. D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
1088. D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
1089. D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
1090. D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
1091. D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
1092. D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
1093. D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
1094. D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
1095. D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
1096. D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
1097. D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
1098. D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
1099. D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
1100. D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
1101. D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
1102. D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
1103. D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
1104. D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
1105. D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
1106. D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
1107. D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
1108. D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
1109. D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
1110. D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
1111. D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
1112. D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
1113. D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
1114. D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
1115. D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
1116. D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
1117. D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
1118. D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
1119. D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
1120. D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
1121. D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
1122. D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
1123. D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
1124. D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
1125. D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
1126. D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
1127. D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
1128. D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
1129. D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
1130. D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
1131. D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
1132. D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
1133. D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
1134. D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
1135. D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
1136. D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
1137. D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
1138. D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
1139. D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
1140. D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
1141. D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
1142. D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
1143. D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
1144. D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
1145. D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
1146. D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
1147. D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
1148. D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
1149. D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
1150. D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
1151. D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
1152. D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
1153. D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
1154. D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
1155. D2F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
1156. D2F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
1157. D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
1158. D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
1159. D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
1160. D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
1161. D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
1162. D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
1163. D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
1164. D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
1165. D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
1166. D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
1167. D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
1168. D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
1169. D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
1170. D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
1171. D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
1172. D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
1173. D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
1174. D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
1175. D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
1176. D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
1177. D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
1178. D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
1179. D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
1180. D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
1181. D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
1182. D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
1183. D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
1184. D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
1185. D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
1186. D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
1187. D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
1188. D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
1189. D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
1190. D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
1191. D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
1192. D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
1193. D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
1194. D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
1195. D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
1196. D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
1197. D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
1198. D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
1199. D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
1200. D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
1201. D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
1202. D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
1203. D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
1204. D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
1205. D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
1206. D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
1207. D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
1208. D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
1209. D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
1210. D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
1211. D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
1212. D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
1213. D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
1214. D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
1215. D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
1216. D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
1217. D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
1218. D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
1219. D2F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK
1220. D2F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
1221. D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
1222. D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
1223. D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
1224. D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
1225. D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
1226. D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
1227. D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
1228. D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
1229. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
1230. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
1231. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
1232. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
1233. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
1234. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
1235. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
1236. D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
1237. D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
1238. D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
1239. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
1240. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
1241. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
1242. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
1243. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
1244. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
1245. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
1246. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
1247. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
1248. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
1249. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
1250. D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
1251. D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
1252. D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
1253. D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
1254. D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
1255. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
1256. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
1257. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
1258. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
1259. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
1260. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
1261. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
1262. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
1263. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
1264. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
1265. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
1266. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
1267. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
1268. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
1269. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
1270. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
1271. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
1272. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
1273. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
1274. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
1275. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
1276. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
1277. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
1278. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
1279. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
1280. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
1281. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
1282. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
1283. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
1284. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
1285. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
1286. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
1287. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
1288. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
1289. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
1290. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
1291. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
1292. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
1293. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
1294. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
1295. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
1296. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
1297. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
1298. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
1299. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
1300. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
1301. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
1302. D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
1303. D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
1304. D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
1305. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
1306. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
1307. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
1308. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
1309. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
1310. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
1311. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
1312. D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
1313. D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
1314. D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
1315. D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
1316. D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
1317. D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
1318. D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
1319. D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
1320. D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
1321. D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
1322. D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
1323. D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
1324. D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
1325. D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
1326. D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
1327. D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
1328. D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
1329. D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
1330. D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
1331. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
1332. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
1333. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
1334. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
1335. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
1336. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
1337. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
1338. D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
1339. D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
1340. D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
1341. D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
1342. D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
1343. D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
1344. D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
1345. D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
1346. D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
1347. D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
1348. D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
1349. D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
1350. D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
1351. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
1352. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
1353. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
1354. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
1355. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
1356. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
1357. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
1358. D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
1359. D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
1360. D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
1361. D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
1362. D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
1363. D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
1364. D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
1365. D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
1366. D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
1367. D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
1368. D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
1369. D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
1370. D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
1371. D2F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
1372. D2F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
1373. D2F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
1374. D2F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
1375. D2F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
1376. D2F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
1377. D2F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
1378. D2F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
1379. D2F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
1380. D2F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
1381. D2F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
1382. D2F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
1383. D2F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
1384. D2F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
1385. D2F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
1386. D2F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
1387. D2F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
1388. D2F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
1389. D2F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
1390. D2F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
1391. D2F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
1392. D2F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
1393. D2F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
1394. D2F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
1395. D2F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
1396. D2F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
1397. D2F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
1398. D2F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
1399. D2F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
1400. D2F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
1401. D2F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
1402. D2F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
1403. D2F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
1404. D2F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
1405. D2F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
1406. D2F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
1407. D2F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
1408. D2F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
1409. D2F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
1410. D2F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
1411. D2F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
1412. D2F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
1413. D2F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
1414. D2F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
1415. D2F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
1416. D2F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
1417. D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
1418. D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
1419. D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
1420. D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
1421. D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
1422. D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
1423. D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
1424. D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
1425. D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
1426. D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
1427. D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
1428. D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
1429. D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
1430. D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
1431. D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
1432. D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
1433. D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
1434. D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
1435. D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
1436. D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
1437. D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
1438. D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
1439. D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
1440. D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
1441. D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
1442. D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
1443. D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
1444. D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
1445. D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
1446. D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
1447. D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
1448. D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
1449. D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
1450. D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
1451. D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
1452. D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
1453. D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
1454. D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
1455. D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
1456. D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
1457. D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
1458. D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
1459. D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
1460. D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
1461. D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
1462. D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
1463. D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
1464. D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
1465. D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
1466. D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
1467. D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
1468. D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
1469. D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
1470. D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
1471. D2F1_PCIE_LINK_CNTL3__RESERVED_MASK
1472. D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT
1473. D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
1474. D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
1475. D2F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
1476. D2F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
1477. D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
1478. D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
1479. D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
1480. D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
1481. D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
1482. D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
1483. D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
1484. D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
1485. D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
1486. D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
1487. D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
1488. D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
1489. D2F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
1490. D2F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
1491. D2F1_PCIE_MC_CNTL__MC_ENABLE_MASK
1492. D2F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
1493. D2F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
1494. D2F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
1495. D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
1496. D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
1497. D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
1498. D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
1499. D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
1500. D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
1501. D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
1502. D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
1503. D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
1504. D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
1505. D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
1506. D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
1507. D2F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
1508. D2F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
1509. D2F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
1510. D2F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
1511. D2F1_PCIE_PORT_DATA__PCIE_DATA_MASK
1512. D2F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT
1513. D2F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK
1514. D2F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
1515. D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
1516. D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
1517. D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
1518. D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
1519. D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
1520. D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
1521. D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
1522. D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
1523. D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
1524. D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
1525. D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
1526. D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
1527. D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
1528. D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
1529. D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
1530. D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
1531. D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
1532. D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
1533. D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
1534. D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
1535. D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
1536. D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
1537. D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
1538. D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
1539. D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
1540. D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
1541. D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
1542. D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
1543. D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
1544. D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
1545. D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
1546. D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
1547. D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
1548. D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
1549. D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
1550. D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
1551. D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
1552. D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
1553. D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
1554. D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
1555. D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
1556. D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
1557. D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
1558. D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
1559. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
1560. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
1561. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
1562. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
1563. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
1564. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
1565. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
1566. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
1567. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
1568. D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
1569. D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
1570. D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
1571. D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
1572. D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
1573. D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
1574. D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
1575. D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
1576. D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
1577. D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
1578. D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
1579. D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
1580. D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
1581. D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
1582. D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
1583. D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
1584. D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
1585. D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
1586. D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
1587. D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
1588. D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
1589. D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
1590. D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
1591. D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
1592. D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
1593. D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
1594. D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
1595. D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
1596. D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
1597. D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
1598. D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
1599. D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
1600. D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
1601. D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
1602. D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
1603. D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
1604. D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
1605. D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
1606. D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
1607. D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
1608. D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
1609. D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
1610. D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
1611. D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
1612. D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
1613. D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
1614. D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
1615. D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
1616. D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
1617. D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
1618. D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
1619. D2F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK
1620. D2F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
1621. D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
1622. D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
1623. D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
1624. D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
1625. D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
1626. D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
1627. D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
1628. D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
1629. D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
1630. D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
1631. D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
1632. D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
1633. D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
1634. D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
1635. D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
1636. D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
1637. D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
1638. D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
1639. D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
1640. D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
1641. D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
1642. D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
1643. D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
1644. D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
1645. D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
1646. D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
1647. D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
1648. D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
1649. D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
1650. D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
1651. D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
1652. D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
1653. D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
1654. D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
1655. D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
1656. D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
1657. D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
1658. D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
1659. D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
1660. D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
1661. D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
1662. D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
1663. D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
1664. D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
1665. D2F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
1666. D2F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
1667. D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
1668. D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
1669. D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
1670. D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
1671. D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
1672. D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
1673. D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
1674. D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
1675. D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
1676. D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
1677. D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
1678. D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
1679. D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
1680. D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
1681. D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
1682. D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
1683. D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
1684. D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
1685. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
1686. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
1687. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
1688. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
1689. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
1690. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
1691. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
1692. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
1693. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
1694. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
1695. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
1696. D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
1697. D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
1698. D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
1699. D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
1700. D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
1701. D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
1702. D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
1703. D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
1704. D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
1705. D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
1706. D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
1707. D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
1708. D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
1709. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
1710. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
1711. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
1712. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
1713. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
1714. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
1715. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
1716. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
1717. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
1718. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
1719. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
1720. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
1721. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
1722. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
1723. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
1724. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
1725. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
1726. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
1727. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
1728. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
1729. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
1730. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
1731. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
1732. D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
1733. D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
1734. D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
1735. D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
1736. D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
1737. D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
1738. D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
1739. D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
1740. D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
1741. D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
1742. D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
1743. D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
1744. D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
1745. D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
1746. D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
1747. D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
1748. D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
1749. D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
1750. D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
1751. D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
1752. D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
1753. D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
1754. D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
1755. D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
1756. D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
1757. D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
1758. D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
1759. D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
1760. D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
1761. D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
1762. D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
1763. D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
1764. D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
1765. D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
1766. D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
1767. D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
1768. D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
1769. D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
1770. D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
1771. D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
1772. D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
1773. D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
1774. D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
1775. D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
1776. D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
1777. D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
1778. D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
1779. D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
1780. D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
1781. D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
1782. D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
1783. D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
1784. D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
1785. D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
1786. D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
1787. D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
1788. D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
1789. D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
1790. D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
1791. D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
1792. D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
1793. D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
1794. D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
1795. D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
1796. D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
1797. D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
1798. D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
1799. D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
1800. D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
1801. D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
1802. D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
1803. D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
1804. D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
1805. D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
1806. D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
1807. D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
1808. D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
1809. D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
1810. D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
1811. D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
1812. D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
1813. D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
1814. D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
1815. D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
1816. D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
1817. D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
1818. D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
1819. D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
1820. D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
1821. D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
1822. D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
1823. D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
1824. D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
1825. D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
1826. D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
1827. D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
1828. D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
1829. D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
1830. D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
1831. D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
1832. D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
1833. D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
1834. D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
1835. D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
1836. D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
1837. D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
1838. D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
1839. D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
1840. D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
1841. D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
1842. D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
1843. D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
1844. D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
1845. D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
1846. D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
1847. D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
1848. D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
1849. D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
1850. D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
1851. D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
1852. D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
1853. D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
1854. D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
1855. D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
1856. D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
1857. D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
1858. D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
1859. D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
1860. D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
1861. D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
1862. D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
1863. D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
1864. D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
1865. D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
1866. D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
1867. D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
1868. D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
1869. D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
1870. D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
1871. D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
1872. D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
1873. D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
1874. D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
1875. D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
1876. D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
1877. D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
1878. D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
1879. D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
1880. D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
1881. D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
1882. D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
1883. D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
1884. D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
1885. D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
1886. D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
1887. D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
1888. D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
1889. D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
1890. D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
1891. D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
1892. D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
1893. D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
1894. D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
1895. D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
1896. D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
1897. D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
1898. D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
1899. D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
1900. D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
1901. D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
1902. D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
1903. D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
1904. D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
1905. D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
1906. D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
1907. D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
1908. D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
1909. D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
1910. D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
1911. D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
1912. D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
1913. D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
1914. D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
1915. D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
1916. D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
1917. D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
1918. D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
1919. D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
1920. D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
1921. D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
1922. D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
1923. D2F1_PMI_CAP_LIST__CAP_ID_MASK
1924. D2F1_PMI_CAP_LIST__CAP_ID__SHIFT
1925. D2F1_PMI_CAP_LIST__NEXT_PTR_MASK
1926. D2F1_PMI_CAP_LIST__NEXT_PTR__SHIFT
1927. D2F1_PMI_CAP__AUX_CURRENT_MASK
1928. D2F1_PMI_CAP__AUX_CURRENT__SHIFT
1929. D2F1_PMI_CAP__D1_SUPPORT_MASK
1930. D2F1_PMI_CAP__D1_SUPPORT__SHIFT
1931. D2F1_PMI_CAP__D2_SUPPORT_MASK
1932. D2F1_PMI_CAP__D2_SUPPORT__SHIFT
1933. D2F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
1934. D2F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
1935. D2F1_PMI_CAP__PME_CLOCK_MASK
1936. D2F1_PMI_CAP__PME_CLOCK__SHIFT
1937. D2F1_PMI_CAP__PME_SUPPORT_MASK
1938. D2F1_PMI_CAP__PME_SUPPORT__SHIFT
1939. D2F1_PMI_CAP__VERSION_MASK
1940. D2F1_PMI_CAP__VERSION__SHIFT
1941. D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
1942. D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
1943. D2F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
1944. D2F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
1945. D2F1_PMI_STATUS_CNTL__DATA_SCALE_MASK
1946. D2F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
1947. D2F1_PMI_STATUS_CNTL__DATA_SELECT_MASK
1948. D2F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
1949. D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
1950. D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
1951. D2F1_PMI_STATUS_CNTL__PME_EN_MASK
1952. D2F1_PMI_STATUS_CNTL__PME_EN__SHIFT
1953. D2F1_PMI_STATUS_CNTL__PME_STATUS_MASK
1954. D2F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
1955. D2F1_PMI_STATUS_CNTL__PMI_DATA_MASK
1956. D2F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
1957. D2F1_PMI_STATUS_CNTL__POWER_STATE_MASK
1958. D2F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
1959. D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
1960. D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
1961. D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
1962. D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
1963. D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
1964. D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
1965. D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
1966. D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
1967. D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
1968. D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
1969. D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
1970. D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
1971. D2F1_PROG_INTERFACE__PROG_INTERFACE_MASK
1972. D2F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
1973. D2F1_REVISION_ID__MAJOR_REV_ID_MASK
1974. D2F1_REVISION_ID__MAJOR_REV_ID__SHIFT
1975. D2F1_REVISION_ID__MINOR_REV_ID_MASK
1976. D2F1_REVISION_ID__MINOR_REV_ID__SHIFT
1977. D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
1978. D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
1979. D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
1980. D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
1981. D2F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
1982. D2F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
1983. D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
1984. D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
1985. D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
1986. D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
1987. D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
1988. D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
1989. D2F1_ROOT_STATUS__PME_PENDING_MASK
1990. D2F1_ROOT_STATUS__PME_PENDING__SHIFT
1991. D2F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
1992. D2F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
1993. D2F1_ROOT_STATUS__PME_STATUS_MASK
1994. D2F1_ROOT_STATUS__PME_STATUS__SHIFT
1995. D2F1_SECONDARY_STATUS__CAP_LIST_MASK
1996. D2F1_SECONDARY_STATUS__CAP_LIST__SHIFT
1997. D2F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
1998. D2F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
1999. D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
2000. D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
2001. D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
2002. D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
2003. D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
2004. D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
2005. D2F1_SECONDARY_STATUS__PCI_66_EN_MASK
2006. D2F1_SECONDARY_STATUS__PCI_66_EN__SHIFT
2007. D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
2008. D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
2009. D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
2010. D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
2011. D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
2012. D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
2013. D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
2014. D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
2015. D2F1_SLOT_CAP2__RESERVED_MASK
2016. D2F1_SLOT_CAP2__RESERVED__SHIFT
2017. D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
2018. D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
2019. D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
2020. D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
2021. D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
2022. D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
2023. D2F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
2024. D2F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
2025. D2F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
2026. D2F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
2027. D2F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
2028. D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
2029. D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
2030. D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
2031. D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
2032. D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
2033. D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
2034. D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
2035. D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
2036. D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
2037. D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
2038. D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
2039. D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
2040. D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
2041. D2F1_SLOT_CNTL2__RESERVED_MASK
2042. D2F1_SLOT_CNTL2__RESERVED__SHIFT
2043. D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
2044. D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
2045. D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
2046. D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
2047. D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
2048. D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
2049. D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
2050. D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
2051. D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
2052. D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
2053. D2F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
2054. D2F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
2055. D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
2056. D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
2057. D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
2058. D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
2059. D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
2060. D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
2061. D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
2062. D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
2063. D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
2064. D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
2065. D2F1_SLOT_STATUS2__RESERVED_MASK
2066. D2F1_SLOT_STATUS2__RESERVED__SHIFT
2067. D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
2068. D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
2069. D2F1_SLOT_STATUS__COMMAND_COMPLETED_MASK
2070. D2F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
2071. D2F1_SLOT_STATUS__DL_STATE_CHANGED_MASK
2072. D2F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
2073. D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
2074. D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
2075. D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
2076. D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
2077. D2F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
2078. D2F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
2079. D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
2080. D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
2081. D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
2082. D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
2083. D2F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
2084. D2F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
2085. D2F1_SSID_CAP_LIST__CAP_ID_MASK
2086. D2F1_SSID_CAP_LIST__CAP_ID__SHIFT
2087. D2F1_SSID_CAP_LIST__NEXT_PTR_MASK
2088. D2F1_SSID_CAP_LIST__NEXT_PTR__SHIFT
2089. D2F1_SSID_CAP__SUBSYSTEM_ID_MASK
2090. D2F1_SSID_CAP__SUBSYSTEM_ID__SHIFT
2091. D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
2092. D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
2093. D2F1_STATUS__CAP_LIST_MASK
2094. D2F1_STATUS__CAP_LIST__SHIFT
2095. D2F1_STATUS__DEVSEL_TIMING_MASK
2096. D2F1_STATUS__DEVSEL_TIMING__SHIFT
2097. D2F1_STATUS__FAST_BACK_CAPABLE_MASK
2098. D2F1_STATUS__FAST_BACK_CAPABLE__SHIFT
2099. D2F1_STATUS__INT_STATUS_MASK
2100. D2F1_STATUS__INT_STATUS__SHIFT
2101. D2F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
2102. D2F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
2103. D2F1_STATUS__PARITY_ERROR_DETECTED_MASK
2104. D2F1_STATUS__PARITY_ERROR_DETECTED__SHIFT
2105. D2F1_STATUS__PCI_66_EN_MASK
2106. D2F1_STATUS__PCI_66_EN__SHIFT
2107. D2F1_STATUS__RECEIVED_MASTER_ABORT_MASK
2108. D2F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
2109. D2F1_STATUS__RECEIVED_TARGET_ABORT_MASK
2110. D2F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
2111. D2F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
2112. D2F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
2113. D2F1_STATUS__SIGNAL_TARGET_ABORT_MASK
2114. D2F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
2115. D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
2116. D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
2117. D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
2118. D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
2119. D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
2120. D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
2121. D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
2122. D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
2123. D2F1_SUB_CLASS__SUB_CLASS_MASK
2124. D2F1_SUB_CLASS__SUB_CLASS__SHIFT
2125. D2F1_VENDOR_ID__VENDOR_ID_MASK
2126. D2F1_VENDOR_ID__VENDOR_ID__SHIFT
2127. D2F2_BASE_CLASS__BASE_CLASS_MASK
2128. D2F2_BASE_CLASS__BASE_CLASS__SHIFT
2129. D2F2_BIST__BIST_CAP_MASK
2130. D2F2_BIST__BIST_CAP__SHIFT
2131. D2F2_BIST__BIST_COMP_MASK
2132. D2F2_BIST__BIST_COMP__SHIFT
2133. D2F2_BIST__BIST_STRT_MASK
2134. D2F2_BIST__BIST_STRT__SHIFT
2135. D2F2_CACHE_LINE__CACHE_LINE_SIZE_MASK
2136. D2F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
2137. D2F2_CAP_PTR__CAP_PTR_MASK
2138. D2F2_CAP_PTR__CAP_PTR__SHIFT
2139. D2F2_COMMAND__AD_STEPPING_MASK
2140. D2F2_COMMAND__AD_STEPPING__SHIFT
2141. D2F2_COMMAND__BUS_MASTER_EN_MASK
2142. D2F2_COMMAND__BUS_MASTER_EN__SHIFT
2143. D2F2_COMMAND__FAST_B2B_EN_MASK
2144. D2F2_COMMAND__FAST_B2B_EN__SHIFT
2145. D2F2_COMMAND__INT_DIS_MASK
2146. D2F2_COMMAND__INT_DIS__SHIFT
2147. D2F2_COMMAND__IO_ACCESS_EN_MASK
2148. D2F2_COMMAND__IO_ACCESS_EN__SHIFT
2149. D2F2_COMMAND__MEM_ACCESS_EN_MASK
2150. D2F2_COMMAND__MEM_ACCESS_EN__SHIFT
2151. D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
2152. D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
2153. D2F2_COMMAND__PAL_SNOOP_EN_MASK
2154. D2F2_COMMAND__PAL_SNOOP_EN__SHIFT
2155. D2F2_COMMAND__PARITY_ERROR_RESPONSE_MASK
2156. D2F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
2157. D2F2_COMMAND__SERR_EN_MASK
2158. D2F2_COMMAND__SERR_EN__SHIFT
2159. D2F2_COMMAND__SPECIAL_CYCLE_EN_MASK
2160. D2F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
2161. D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
2162. D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
2163. D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
2164. D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
2165. D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
2166. D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
2167. D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
2168. D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
2169. D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
2170. D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
2171. D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
2172. D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
2173. D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
2174. D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
2175. D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
2176. D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
2177. D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
2178. D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
2179. D2F2_DEVICE_CAP2__LTR_SUPPORTED_MASK
2180. D2F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
2181. D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
2182. D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
2183. D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
2184. D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
2185. D2F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
2186. D2F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
2187. D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
2188. D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
2189. D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
2190. D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
2191. D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
2192. D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
2193. D2F2_DEVICE_CAP__EXTENDED_TAG_MASK
2194. D2F2_DEVICE_CAP__EXTENDED_TAG__SHIFT
2195. D2F2_DEVICE_CAP__FLR_CAPABLE_MASK
2196. D2F2_DEVICE_CAP__FLR_CAPABLE__SHIFT
2197. D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
2198. D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
2199. D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
2200. D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
2201. D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
2202. D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
2203. D2F2_DEVICE_CAP__PHANTOM_FUNC_MASK
2204. D2F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
2205. D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
2206. D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
2207. D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
2208. D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
2209. D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
2210. D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
2211. D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
2212. D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
2213. D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
2214. D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
2215. D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
2216. D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
2217. D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
2218. D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
2219. D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
2220. D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
2221. D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
2222. D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
2223. D2F2_DEVICE_CNTL2__LTR_EN_MASK
2224. D2F2_DEVICE_CNTL2__LTR_EN__SHIFT
2225. D2F2_DEVICE_CNTL2__OBFF_EN_MASK
2226. D2F2_DEVICE_CNTL2__OBFF_EN__SHIFT
2227. D2F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
2228. D2F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
2229. D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
2230. D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
2231. D2F2_DEVICE_CNTL__CORR_ERR_EN_MASK
2232. D2F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
2233. D2F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
2234. D2F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
2235. D2F2_DEVICE_CNTL__FATAL_ERR_EN_MASK
2236. D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
2237. D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
2238. D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
2239. D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
2240. D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
2241. D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
2242. D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
2243. D2F2_DEVICE_CNTL__NO_SNOOP_EN_MASK
2244. D2F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
2245. D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
2246. D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
2247. D2F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
2248. D2F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
2249. D2F2_DEVICE_CNTL__USR_REPORT_EN_MASK
2250. D2F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
2251. D2F2_DEVICE_ID__DEVICE_ID_MASK
2252. D2F2_DEVICE_ID__DEVICE_ID__SHIFT
2253. D2F2_DEVICE_STATUS2__RESERVED_MASK
2254. D2F2_DEVICE_STATUS2__RESERVED__SHIFT
2255. D2F2_DEVICE_STATUS__AUX_PWR_MASK
2256. D2F2_DEVICE_STATUS__AUX_PWR__SHIFT
2257. D2F2_DEVICE_STATUS__CORR_ERR_MASK
2258. D2F2_DEVICE_STATUS__CORR_ERR__SHIFT
2259. D2F2_DEVICE_STATUS__FATAL_ERR_MASK
2260. D2F2_DEVICE_STATUS__FATAL_ERR__SHIFT
2261. D2F2_DEVICE_STATUS__NON_FATAL_ERR_MASK
2262. D2F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
2263. D2F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
2264. D2F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
2265. D2F2_DEVICE_STATUS__USR_DETECTED_MASK
2266. D2F2_DEVICE_STATUS__USR_DETECTED__SHIFT
2267. D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
2268. D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
2269. D2F2_HEADER__DEVICE_TYPE_MASK
2270. D2F2_HEADER__DEVICE_TYPE__SHIFT
2271. D2F2_HEADER__HEADER_TYPE_MASK
2272. D2F2_HEADER__HEADER_TYPE__SHIFT
2273. D2F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
2274. D2F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
2275. D2F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
2276. D2F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
2277. D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
2278. D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
2279. D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
2280. D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
2281. D2F2_IO_BASE_LIMIT__IO_BASE_MASK
2282. D2F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
2283. D2F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
2284. D2F2_IO_BASE_LIMIT__IO_BASE__SHIFT
2285. D2F2_IO_BASE_LIMIT__IO_LIMIT_MASK
2286. D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
2287. D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
2288. D2F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
2289. D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
2290. D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
2291. D2F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
2292. D2F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
2293. D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
2294. D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
2295. D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
2296. D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
2297. D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
2298. D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
2299. D2F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
2300. D2F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
2301. D2F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
2302. D2F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
2303. D2F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
2304. D2F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
2305. D2F2_LATENCY__LATENCY_TIMER_MASK
2306. D2F2_LATENCY__LATENCY_TIMER__SHIFT
2307. D2F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
2308. D2F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
2309. D2F2_LINK_CAP2__RESERVED_MASK
2310. D2F2_LINK_CAP2__RESERVED__SHIFT
2311. D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
2312. D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
2313. D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
2314. D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
2315. D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
2316. D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
2317. D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
2318. D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
2319. D2F2_LINK_CAP__L0S_EXIT_LATENCY_MASK
2320. D2F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
2321. D2F2_LINK_CAP__L1_EXIT_LATENCY_MASK
2322. D2F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
2323. D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
2324. D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
2325. D2F2_LINK_CAP__LINK_SPEED_MASK
2326. D2F2_LINK_CAP__LINK_SPEED__SHIFT
2327. D2F2_LINK_CAP__LINK_WIDTH_MASK
2328. D2F2_LINK_CAP__LINK_WIDTH__SHIFT
2329. D2F2_LINK_CAP__PM_SUPPORT_MASK
2330. D2F2_LINK_CAP__PM_SUPPORT__SHIFT
2331. D2F2_LINK_CAP__PORT_NUMBER_MASK
2332. D2F2_LINK_CAP__PORT_NUMBER__SHIFT
2333. D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
2334. D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
2335. D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
2336. D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
2337. D2F2_LINK_CNTL2__COMPLIANCE_SOS_MASK
2338. D2F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
2339. D2F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
2340. D2F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
2341. D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
2342. D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
2343. D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
2344. D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
2345. D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
2346. D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
2347. D2F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
2348. D2F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
2349. D2F2_LINK_CNTL2__XMIT_MARGIN_MASK
2350. D2F2_LINK_CNTL2__XMIT_MARGIN__SHIFT
2351. D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
2352. D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
2353. D2F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
2354. D2F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
2355. D2F2_LINK_CNTL__EXTENDED_SYNC_MASK
2356. D2F2_LINK_CNTL__EXTENDED_SYNC__SHIFT
2357. D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
2358. D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
2359. D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
2360. D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
2361. D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
2362. D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
2363. D2F2_LINK_CNTL__LINK_DIS_MASK
2364. D2F2_LINK_CNTL__LINK_DIS__SHIFT
2365. D2F2_LINK_CNTL__PM_CONTROL_MASK
2366. D2F2_LINK_CNTL__PM_CONTROL__SHIFT
2367. D2F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
2368. D2F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
2369. D2F2_LINK_CNTL__RETRAIN_LINK_MASK
2370. D2F2_LINK_CNTL__RETRAIN_LINK__SHIFT
2371. D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
2372. D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
2373. D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
2374. D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
2375. D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
2376. D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
2377. D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
2378. D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
2379. D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
2380. D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
2381. D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
2382. D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
2383. D2F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
2384. D2F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
2385. D2F2_LINK_STATUS__DL_ACTIVE_MASK
2386. D2F2_LINK_STATUS__DL_ACTIVE__SHIFT
2387. D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
2388. D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
2389. D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
2390. D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
2391. D2F2_LINK_STATUS__LINK_TRAINING_MASK
2392. D2F2_LINK_STATUS__LINK_TRAINING__SHIFT
2393. D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
2394. D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
2395. D2F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
2396. D2F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
2397. D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
2398. D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
2399. D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
2400. D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
2401. D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
2402. D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
2403. D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
2404. D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
2405. D2F2_MSI_CAP_LIST__CAP_ID_MASK
2406. D2F2_MSI_CAP_LIST__CAP_ID__SHIFT
2407. D2F2_MSI_CAP_LIST__NEXT_PTR_MASK
2408. D2F2_MSI_CAP_LIST__NEXT_PTR__SHIFT
2409. D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
2410. D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
2411. D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
2412. D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
2413. D2F2_MSI_MAP_CAP_LIST__CAP_ID_MASK
2414. D2F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
2415. D2F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
2416. D2F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
2417. D2F2_MSI_MAP_CAP__CAP_TYPE_MASK
2418. D2F2_MSI_MAP_CAP__CAP_TYPE__SHIFT
2419. D2F2_MSI_MAP_CAP__EN_MASK
2420. D2F2_MSI_MAP_CAP__EN__SHIFT
2421. D2F2_MSI_MAP_CAP__FIXD_MASK
2422. D2F2_MSI_MAP_CAP__FIXD__SHIFT
2423. D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
2424. D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
2425. D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
2426. D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
2427. D2F2_MSI_MSG_CNTL__MSI_64BIT_MASK
2428. D2F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
2429. D2F2_MSI_MSG_CNTL__MSI_EN_MASK
2430. D2F2_MSI_MSG_CNTL__MSI_EN__SHIFT
2431. D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
2432. D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
2433. D2F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
2434. D2F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
2435. D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
2436. D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
2437. D2F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
2438. D2F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
2439. D2F2_MSI_MSG_DATA__MSI_DATA_MASK
2440. D2F2_MSI_MSG_DATA__MSI_DATA__SHIFT
2441. D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
2442. D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
2443. D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
2444. D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
2445. D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
2446. D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
2447. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
2448. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
2449. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
2450. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
2451. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
2452. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
2453. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
2454. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
2455. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
2456. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
2457. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
2458. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
2459. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
2460. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
2461. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
2462. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
2463. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
2464. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
2465. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
2466. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
2467. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
2468. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
2469. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
2470. D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
2471. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
2472. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
2473. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
2474. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
2475. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
2476. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
2477. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
2478. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
2479. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
2480. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
2481. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
2482. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
2483. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
2484. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
2485. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
2486. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
2487. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
2488. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
2489. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
2490. D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
2491. D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
2492. D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
2493. D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
2494. D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
2495. D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
2496. D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
2497. D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
2498. D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
2499. D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
2500. D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
2501. D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
2502. D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
2503. D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
2504. D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
2505. D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
2506. D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
2507. D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
2508. D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
2509. D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
2510. D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
2511. D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
2512. D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
2513. D2F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK
2514. D2F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
2515. D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
2516. D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
2517. D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
2518. D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
2519. D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
2520. D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
2521. D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
2522. D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
2523. D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
2524. D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
2525. D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
2526. D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
2527. D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
2528. D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
2529. D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
2530. D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
2531. D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
2532. D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
2533. D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
2534. D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
2535. D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
2536. D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
2537. D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
2538. D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
2539. D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
2540. D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
2541. D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
2542. D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
2543. D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
2544. D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
2545. D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
2546. D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
2547. D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
2548. D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
2549. D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
2550. D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
2551. D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
2552. D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
2553. D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
2554. D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
2555. D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
2556. D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
2557. D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
2558. D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
2559. D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
2560. D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
2561. D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
2562. D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
2563. D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
2564. D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
2565. D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
2566. D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
2567. D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
2568. D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
2569. D2F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK
2570. D2F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
2571. D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
2572. D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
2573. D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
2574. D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
2575. D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
2576. D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
2577. D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
2578. D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
2579. D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
2580. D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
2581. D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
2582. D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
2583. D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
2584. D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
2585. D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
2586. D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
2587. D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
2588. D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
2589. D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
2590. D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
2591. D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
2592. D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
2593. D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
2594. D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
2595. D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
2596. D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
2597. D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
2598. D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
2599. D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
2600. D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
2601. D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
2602. D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
2603. D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
2604. D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
2605. D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
2606. D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
2607. D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
2608. D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
2609. D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
2610. D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
2611. D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
2612. D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
2613. D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
2614. D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
2615. D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
2616. D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
2617. D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
2618. D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
2619. D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
2620. D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
2621. D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
2622. D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
2623. D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
2624. D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
2625. D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
2626. D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
2627. D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
2628. D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
2629. D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
2630. D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
2631. D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
2632. D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
2633. D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
2634. D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
2635. D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
2636. D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
2637. D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
2638. D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
2639. D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
2640. D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
2641. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
2642. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
2643. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
2644. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
2645. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
2646. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
2647. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
2648. D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
2649. D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
2650. D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
2651. D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
2652. D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
2653. D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
2654. D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
2655. D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
2656. D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
2657. D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
2658. D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
2659. D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
2660. D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
2661. D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
2662. D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
2663. D2F2_PCIE_CAP_LIST__CAP_ID_MASK
2664. D2F2_PCIE_CAP_LIST__CAP_ID__SHIFT
2665. D2F2_PCIE_CAP_LIST__NEXT_PTR_MASK
2666. D2F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
2667. D2F2_PCIE_CAP__DEVICE_TYPE_MASK
2668. D2F2_PCIE_CAP__DEVICE_TYPE__SHIFT
2669. D2F2_PCIE_CAP__INT_MESSAGE_NUM_MASK
2670. D2F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
2671. D2F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
2672. D2F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
2673. D2F2_PCIE_CAP__VERSION_MASK
2674. D2F2_PCIE_CAP__VERSION__SHIFT
2675. D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
2676. D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
2677. D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
2678. D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
2679. D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
2680. D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
2681. D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
2682. D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
2683. D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
2684. D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
2685. D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
2686. D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
2687. D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
2688. D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
2689. D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
2690. D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
2691. D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
2692. D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
2693. D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
2694. D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
2695. D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
2696. D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
2697. D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
2698. D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
2699. D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
2700. D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
2701. D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
2702. D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
2703. D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
2704. D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
2705. D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
2706. D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
2707. D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
2708. D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
2709. D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
2710. D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
2711. D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
2712. D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
2713. D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
2714. D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
2715. D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
2716. D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
2717. D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
2718. D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
2719. D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
2720. D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
2721. D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
2722. D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
2723. D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
2724. D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
2725. D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
2726. D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
2727. D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
2728. D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
2729. D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
2730. D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
2731. D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
2732. D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
2733. D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
2734. D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
2735. D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
2736. D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
2737. D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
2738. D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
2739. D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
2740. D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
2741. D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
2742. D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
2743. D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
2744. D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
2745. D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
2746. D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
2747. D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
2748. D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
2749. D2F2_PCIE_FC_CPL__CPLD_CREDITS_MASK
2750. D2F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
2751. D2F2_PCIE_FC_CPL__CPLH_CREDITS_MASK
2752. D2F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
2753. D2F2_PCIE_FC_NP__NPD_CREDITS_MASK
2754. D2F2_PCIE_FC_NP__NPD_CREDITS__SHIFT
2755. D2F2_PCIE_FC_NP__NPH_CREDITS_MASK
2756. D2F2_PCIE_FC_NP__NPH_CREDITS__SHIFT
2757. D2F2_PCIE_FC_P__PD_CREDITS_MASK
2758. D2F2_PCIE_FC_P__PD_CREDITS__SHIFT
2759. D2F2_PCIE_FC_P__PH_CREDITS_MASK
2760. D2F2_PCIE_FC_P__PH_CREDITS__SHIFT
2761. D2F2_PCIE_HDR_LOG0__TLP_HDR_MASK
2762. D2F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
2763. D2F2_PCIE_HDR_LOG1__TLP_HDR_MASK
2764. D2F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
2765. D2F2_PCIE_HDR_LOG2__TLP_HDR_MASK
2766. D2F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
2767. D2F2_PCIE_HDR_LOG3__TLP_HDR_MASK
2768. D2F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
2769. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2770. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2771. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2772. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2773. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
2774. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
2775. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2776. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2777. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2778. D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2779. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2780. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2781. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2782. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2783. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
2784. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
2785. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2786. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2787. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2788. D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2789. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2790. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2791. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2792. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2793. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
2794. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
2795. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2796. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2797. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2798. D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2799. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2800. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2801. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2802. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2803. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
2804. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
2805. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2806. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2807. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2808. D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2809. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2810. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2811. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2812. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2813. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
2814. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
2815. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2816. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2817. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2818. D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2819. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2820. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2821. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2822. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2823. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
2824. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
2825. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2826. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2827. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2828. D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2829. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2830. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2831. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2832. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2833. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
2834. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
2835. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2836. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2837. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2838. D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2839. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2840. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2841. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2842. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2843. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
2844. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
2845. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2846. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2847. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2848. D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2849. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2850. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2851. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2852. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2853. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
2854. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
2855. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2856. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2857. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2858. D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2859. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2860. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2861. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2862. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2863. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
2864. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
2865. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2866. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2867. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2868. D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2869. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2870. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2871. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2872. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2873. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
2874. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
2875. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2876. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2877. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2878. D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2879. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2880. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2881. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2882. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2883. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
2884. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
2885. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2886. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2887. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2888. D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2889. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2890. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2891. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2892. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2893. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
2894. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
2895. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2896. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2897. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2898. D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2899. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2900. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2901. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2902. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2903. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
2904. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
2905. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2906. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2907. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2908. D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2909. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2910. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2911. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2912. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2913. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
2914. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
2915. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2916. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2917. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2918. D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2919. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
2920. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
2921. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
2922. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
2923. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
2924. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
2925. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
2926. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
2927. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
2928. D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
2929. D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
2930. D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
2931. D2F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
2932. D2F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
2933. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
2934. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
2935. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
2936. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
2937. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
2938. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
2939. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
2940. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
2941. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
2942. D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
2943. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
2944. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
2945. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
2946. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
2947. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
2948. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
2949. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
2950. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
2951. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
2952. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
2953. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
2954. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
2955. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
2956. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
2957. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
2958. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
2959. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
2960. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
2961. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
2962. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
2963. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
2964. D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
2965. D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
2966. D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
2967. D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
2968. D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
2969. D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
2970. D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
2971. D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
2972. D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
2973. D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
2974. D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
2975. D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
2976. D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
2977. D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
2978. D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
2979. D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
2980. D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
2981. D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
2982. D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
2983. D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
2984. D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
2985. D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
2986. D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
2987. D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
2988. D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
2989. D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
2990. D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
2991. D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
2992. D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
2993. D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
2994. D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
2995. D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
2996. D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
2997. D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
2998. D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
2999. D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
3000. D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
3001. D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
3002. D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
3003. D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
3004. D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
3005. D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
3006. D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
3007. D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
3008. D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
3009. D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
3010. D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
3011. D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
3012. D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
3013. D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
3014. D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
3015. D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
3016. D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
3017. D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
3018. D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
3019. D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
3020. D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
3021. D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
3022. D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
3023. D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
3024. D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
3025. D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
3026. D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
3027. D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
3028. D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
3029. D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
3030. D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
3031. D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
3032. D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
3033. D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
3034. D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
3035. D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
3036. D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
3037. D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
3038. D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
3039. D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
3040. D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
3041. D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
3042. D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
3043. D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
3044. D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
3045. D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
3046. D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
3047. D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
3048. D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
3049. D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
3050. D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
3051. D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
3052. D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
3053. D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
3054. D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
3055. D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
3056. D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
3057. D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
3058. D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
3059. D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
3060. D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
3061. D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
3062. D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
3063. D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
3064. D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
3065. D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
3066. D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
3067. D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
3068. D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
3069. D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
3070. D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
3071. D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
3072. D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
3073. D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
3074. D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
3075. D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
3076. D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
3077. D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
3078. D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
3079. D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
3080. D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
3081. D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
3082. D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
3083. D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
3084. D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
3085. D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
3086. D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
3087. D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
3088. D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
3089. D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
3090. D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
3091. D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
3092. D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
3093. D2F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
3094. D2F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
3095. D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
3096. D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
3097. D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
3098. D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
3099. D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
3100. D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
3101. D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
3102. D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
3103. D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
3104. D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
3105. D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
3106. D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
3107. D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
3108. D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
3109. D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
3110. D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
3111. D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
3112. D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
3113. D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
3114. D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
3115. D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
3116. D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
3117. D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
3118. D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
3119. D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
3120. D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
3121. D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
3122. D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
3123. D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
3124. D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
3125. D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
3126. D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
3127. D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
3128. D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
3129. D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
3130. D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
3131. D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
3132. D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
3133. D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
3134. D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
3135. D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
3136. D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
3137. D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
3138. D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
3139. D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
3140. D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
3141. D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
3142. D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
3143. D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
3144. D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
3145. D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
3146. D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
3147. D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
3148. D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
3149. D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
3150. D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
3151. D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
3152. D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
3153. D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
3154. D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
3155. D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
3156. D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
3157. D2F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK
3158. D2F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
3159. D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
3160. D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
3161. D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
3162. D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
3163. D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
3164. D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
3165. D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
3166. D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
3167. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
3168. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
3169. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
3170. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
3171. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
3172. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
3173. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
3174. D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
3175. D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
3176. D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
3177. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
3178. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
3179. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
3180. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
3181. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
3182. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
3183. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
3184. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
3185. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
3186. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
3187. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
3188. D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
3189. D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
3190. D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
3191. D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
3192. D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
3193. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
3194. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
3195. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
3196. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
3197. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
3198. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
3199. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
3200. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
3201. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
3202. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
3203. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
3204. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
3205. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
3206. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
3207. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
3208. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
3209. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
3210. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
3211. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
3212. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
3213. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
3214. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
3215. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
3216. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
3217. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
3218. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
3219. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
3220. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
3221. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
3222. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
3223. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
3224. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
3225. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
3226. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
3227. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
3228. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
3229. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
3230. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
3231. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
3232. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
3233. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
3234. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
3235. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
3236. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
3237. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
3238. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
3239. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
3240. D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
3241. D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
3242. D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
3243. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
3244. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
3245. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
3246. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
3247. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
3248. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
3249. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
3250. D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
3251. D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
3252. D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
3253. D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
3254. D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
3255. D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
3256. D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
3257. D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
3258. D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
3259. D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
3260. D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
3261. D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
3262. D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
3263. D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
3264. D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
3265. D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
3266. D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
3267. D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
3268. D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
3269. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
3270. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
3271. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
3272. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
3273. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
3274. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
3275. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
3276. D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
3277. D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
3278. D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
3279. D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
3280. D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
3281. D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
3282. D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
3283. D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
3284. D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
3285. D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
3286. D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
3287. D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
3288. D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
3289. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
3290. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
3291. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
3292. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
3293. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
3294. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
3295. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
3296. D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
3297. D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
3298. D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
3299. D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
3300. D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
3301. D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
3302. D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
3303. D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
3304. D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
3305. D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
3306. D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
3307. D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
3308. D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
3309. D2F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
3310. D2F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
3311. D2F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
3312. D2F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
3313. D2F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
3314. D2F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
3315. D2F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
3316. D2F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
3317. D2F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
3318. D2F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
3319. D2F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
3320. D2F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
3321. D2F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
3322. D2F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
3323. D2F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
3324. D2F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
3325. D2F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
3326. D2F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
3327. D2F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
3328. D2F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
3329. D2F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
3330. D2F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
3331. D2F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
3332. D2F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
3333. D2F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
3334. D2F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
3335. D2F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
3336. D2F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
3337. D2F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
3338. D2F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
3339. D2F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
3340. D2F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
3341. D2F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
3342. D2F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
3343. D2F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
3344. D2F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
3345. D2F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
3346. D2F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
3347. D2F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
3348. D2F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
3349. D2F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
3350. D2F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
3351. D2F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
3352. D2F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
3353. D2F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
3354. D2F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
3355. D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
3356. D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
3357. D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
3358. D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
3359. D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
3360. D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
3361. D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
3362. D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
3363. D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
3364. D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
3365. D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
3366. D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
3367. D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
3368. D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
3369. D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
3370. D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
3371. D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
3372. D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
3373. D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
3374. D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
3375. D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
3376. D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
3377. D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
3378. D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
3379. D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
3380. D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
3381. D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
3382. D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
3383. D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
3384. D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
3385. D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
3386. D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
3387. D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
3388. D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
3389. D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
3390. D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
3391. D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
3392. D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
3393. D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
3394. D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
3395. D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
3396. D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
3397. D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
3398. D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
3399. D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
3400. D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
3401. D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
3402. D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
3403. D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
3404. D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
3405. D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
3406. D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
3407. D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
3408. D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
3409. D2F2_PCIE_LINK_CNTL3__RESERVED_MASK
3410. D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT
3411. D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
3412. D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
3413. D2F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
3414. D2F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
3415. D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
3416. D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
3417. D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
3418. D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
3419. D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
3420. D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
3421. D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
3422. D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
3423. D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
3424. D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
3425. D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
3426. D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
3427. D2F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
3428. D2F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
3429. D2F2_PCIE_MC_CNTL__MC_ENABLE_MASK
3430. D2F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
3431. D2F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
3432. D2F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
3433. D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
3434. D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
3435. D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
3436. D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
3437. D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
3438. D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
3439. D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
3440. D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
3441. D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
3442. D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
3443. D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
3444. D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
3445. D2F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
3446. D2F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
3447. D2F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
3448. D2F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
3449. D2F2_PCIE_PORT_DATA__PCIE_DATA_MASK
3450. D2F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT
3451. D2F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK
3452. D2F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
3453. D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
3454. D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
3455. D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
3456. D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
3457. D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
3458. D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
3459. D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
3460. D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
3461. D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
3462. D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
3463. D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
3464. D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
3465. D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
3466. D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
3467. D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
3468. D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
3469. D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
3470. D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
3471. D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
3472. D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
3473. D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
3474. D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
3475. D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
3476. D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
3477. D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
3478. D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
3479. D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
3480. D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
3481. D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
3482. D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
3483. D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
3484. D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
3485. D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
3486. D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
3487. D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
3488. D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
3489. D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
3490. D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
3491. D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
3492. D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
3493. D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
3494. D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
3495. D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
3496. D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
3497. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
3498. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
3499. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
3500. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
3501. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
3502. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
3503. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
3504. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
3505. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
3506. D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
3507. D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
3508. D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
3509. D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
3510. D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
3511. D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
3512. D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
3513. D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
3514. D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
3515. D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
3516. D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
3517. D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
3518. D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
3519. D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
3520. D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
3521. D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
3522. D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
3523. D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
3524. D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
3525. D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
3526. D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
3527. D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
3528. D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
3529. D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
3530. D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
3531. D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
3532. D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
3533. D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
3534. D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
3535. D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
3536. D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
3537. D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
3538. D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
3539. D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
3540. D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
3541. D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
3542. D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
3543. D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
3544. D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
3545. D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
3546. D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
3547. D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
3548. D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
3549. D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
3550. D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
3551. D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
3552. D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
3553. D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
3554. D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
3555. D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
3556. D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
3557. D2F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK
3558. D2F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
3559. D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
3560. D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
3561. D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
3562. D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
3563. D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
3564. D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
3565. D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
3566. D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
3567. D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
3568. D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
3569. D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
3570. D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
3571. D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
3572. D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
3573. D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
3574. D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
3575. D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
3576. D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
3577. D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
3578. D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
3579. D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
3580. D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
3581. D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
3582. D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
3583. D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
3584. D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
3585. D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
3586. D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
3587. D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
3588. D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
3589. D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
3590. D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
3591. D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
3592. D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
3593. D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
3594. D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
3595. D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
3596. D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
3597. D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
3598. D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
3599. D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
3600. D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
3601. D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
3602. D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
3603. D2F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
3604. D2F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
3605. D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
3606. D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
3607. D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
3608. D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
3609. D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
3610. D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
3611. D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
3612. D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
3613. D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
3614. D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
3615. D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
3616. D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
3617. D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
3618. D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
3619. D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
3620. D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
3621. D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
3622. D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
3623. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
3624. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
3625. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
3626. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
3627. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
3628. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
3629. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
3630. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
3631. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
3632. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
3633. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
3634. D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
3635. D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
3636. D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
3637. D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
3638. D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
3639. D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
3640. D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
3641. D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
3642. D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
3643. D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
3644. D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
3645. D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
3646. D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
3647. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
3648. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
3649. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
3650. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
3651. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
3652. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
3653. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
3654. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
3655. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
3656. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
3657. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
3658. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
3659. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
3660. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
3661. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
3662. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
3663. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
3664. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
3665. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
3666. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
3667. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
3668. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
3669. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
3670. D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
3671. D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
3672. D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
3673. D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
3674. D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
3675. D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
3676. D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
3677. D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
3678. D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
3679. D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
3680. D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
3681. D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
3682. D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
3683. D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
3684. D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
3685. D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
3686. D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
3687. D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
3688. D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
3689. D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
3690. D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
3691. D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
3692. D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
3693. D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
3694. D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
3695. D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
3696. D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
3697. D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
3698. D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
3699. D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
3700. D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
3701. D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
3702. D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
3703. D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
3704. D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
3705. D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
3706. D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
3707. D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
3708. D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
3709. D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
3710. D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
3711. D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
3712. D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
3713. D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
3714. D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
3715. D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
3716. D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
3717. D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
3718. D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
3719. D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
3720. D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
3721. D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
3722. D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
3723. D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
3724. D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
3725. D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
3726. D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
3727. D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
3728. D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
3729. D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
3730. D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
3731. D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
3732. D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
3733. D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
3734. D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
3735. D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
3736. D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
3737. D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
3738. D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
3739. D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
3740. D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
3741. D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
3742. D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
3743. D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
3744. D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
3745. D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
3746. D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
3747. D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
3748. D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
3749. D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
3750. D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
3751. D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
3752. D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
3753. D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
3754. D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
3755. D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
3756. D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
3757. D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
3758. D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
3759. D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
3760. D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
3761. D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
3762. D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
3763. D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
3764. D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
3765. D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
3766. D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
3767. D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
3768. D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
3769. D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
3770. D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
3771. D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
3772. D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
3773. D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
3774. D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
3775. D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
3776. D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
3777. D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
3778. D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
3779. D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
3780. D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
3781. D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
3782. D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
3783. D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
3784. D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
3785. D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
3786. D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
3787. D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
3788. D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
3789. D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
3790. D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
3791. D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
3792. D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
3793. D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
3794. D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
3795. D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
3796. D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
3797. D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
3798. D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
3799. D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
3800. D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
3801. D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
3802. D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
3803. D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
3804. D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
3805. D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
3806. D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
3807. D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
3808. D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
3809. D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
3810. D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
3811. D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
3812. D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
3813. D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
3814. D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
3815. D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
3816. D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
3817. D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
3818. D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
3819. D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
3820. D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
3821. D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
3822. D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
3823. D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
3824. D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
3825. D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
3826. D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
3827. D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
3828. D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
3829. D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
3830. D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
3831. D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
3832. D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
3833. D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
3834. D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
3835. D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
3836. D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
3837. D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
3838. D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
3839. D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
3840. D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
3841. D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
3842. D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
3843. D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
3844. D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
3845. D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
3846. D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
3847. D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
3848. D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
3849. D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
3850. D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
3851. D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
3852. D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
3853. D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
3854. D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
3855. D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
3856. D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
3857. D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
3858. D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
3859. D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
3860. D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
3861. D2F2_PMI_CAP_LIST__CAP_ID_MASK
3862. D2F2_PMI_CAP_LIST__CAP_ID__SHIFT
3863. D2F2_PMI_CAP_LIST__NEXT_PTR_MASK
3864. D2F2_PMI_CAP_LIST__NEXT_PTR__SHIFT
3865. D2F2_PMI_CAP__AUX_CURRENT_MASK
3866. D2F2_PMI_CAP__AUX_CURRENT__SHIFT
3867. D2F2_PMI_CAP__D1_SUPPORT_MASK
3868. D2F2_PMI_CAP__D1_SUPPORT__SHIFT
3869. D2F2_PMI_CAP__D2_SUPPORT_MASK
3870. D2F2_PMI_CAP__D2_SUPPORT__SHIFT
3871. D2F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
3872. D2F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
3873. D2F2_PMI_CAP__PME_CLOCK_MASK
3874. D2F2_PMI_CAP__PME_CLOCK__SHIFT
3875. D2F2_PMI_CAP__PME_SUPPORT_MASK
3876. D2F2_PMI_CAP__PME_SUPPORT__SHIFT
3877. D2F2_PMI_CAP__VERSION_MASK
3878. D2F2_PMI_CAP__VERSION__SHIFT
3879. D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
3880. D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
3881. D2F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
3882. D2F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
3883. D2F2_PMI_STATUS_CNTL__DATA_SCALE_MASK
3884. D2F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
3885. D2F2_PMI_STATUS_CNTL__DATA_SELECT_MASK
3886. D2F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
3887. D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
3888. D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
3889. D2F2_PMI_STATUS_CNTL__PME_EN_MASK
3890. D2F2_PMI_STATUS_CNTL__PME_EN__SHIFT
3891. D2F2_PMI_STATUS_CNTL__PME_STATUS_MASK
3892. D2F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
3893. D2F2_PMI_STATUS_CNTL__PMI_DATA_MASK
3894. D2F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
3895. D2F2_PMI_STATUS_CNTL__POWER_STATE_MASK
3896. D2F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
3897. D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
3898. D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
3899. D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
3900. D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
3901. D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
3902. D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
3903. D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
3904. D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
3905. D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
3906. D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
3907. D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
3908. D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
3909. D2F2_PROG_INTERFACE__PROG_INTERFACE_MASK
3910. D2F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
3911. D2F2_REVISION_ID__MAJOR_REV_ID_MASK
3912. D2F2_REVISION_ID__MAJOR_REV_ID__SHIFT
3913. D2F2_REVISION_ID__MINOR_REV_ID_MASK
3914. D2F2_REVISION_ID__MINOR_REV_ID__SHIFT
3915. D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
3916. D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
3917. D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
3918. D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
3919. D2F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
3920. D2F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
3921. D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
3922. D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
3923. D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
3924. D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
3925. D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
3926. D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
3927. D2F2_ROOT_STATUS__PME_PENDING_MASK
3928. D2F2_ROOT_STATUS__PME_PENDING__SHIFT
3929. D2F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
3930. D2F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
3931. D2F2_ROOT_STATUS__PME_STATUS_MASK
3932. D2F2_ROOT_STATUS__PME_STATUS__SHIFT
3933. D2F2_SECONDARY_STATUS__CAP_LIST_MASK
3934. D2F2_SECONDARY_STATUS__CAP_LIST__SHIFT
3935. D2F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
3936. D2F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
3937. D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
3938. D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
3939. D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
3940. D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
3941. D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
3942. D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
3943. D2F2_SECONDARY_STATUS__PCI_66_EN_MASK
3944. D2F2_SECONDARY_STATUS__PCI_66_EN__SHIFT
3945. D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
3946. D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
3947. D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
3948. D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
3949. D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
3950. D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
3951. D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
3952. D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
3953. D2F2_SLOT_CAP2__RESERVED_MASK
3954. D2F2_SLOT_CAP2__RESERVED__SHIFT
3955. D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
3956. D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
3957. D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
3958. D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
3959. D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
3960. D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
3961. D2F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
3962. D2F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
3963. D2F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
3964. D2F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
3965. D2F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
3966. D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
3967. D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
3968. D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
3969. D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
3970. D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
3971. D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
3972. D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
3973. D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
3974. D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
3975. D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
3976. D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
3977. D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
3978. D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
3979. D2F2_SLOT_CNTL2__RESERVED_MASK
3980. D2F2_SLOT_CNTL2__RESERVED__SHIFT
3981. D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
3982. D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
3983. D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
3984. D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
3985. D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
3986. D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
3987. D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
3988. D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
3989. D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
3990. D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
3991. D2F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
3992. D2F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
3993. D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
3994. D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
3995. D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
3996. D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
3997. D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
3998. D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
3999. D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
4000. D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
4001. D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
4002. D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
4003. D2F2_SLOT_STATUS2__RESERVED_MASK
4004. D2F2_SLOT_STATUS2__RESERVED__SHIFT
4005. D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
4006. D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
4007. D2F2_SLOT_STATUS__COMMAND_COMPLETED_MASK
4008. D2F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
4009. D2F2_SLOT_STATUS__DL_STATE_CHANGED_MASK
4010. D2F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
4011. D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
4012. D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
4013. D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
4014. D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
4015. D2F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
4016. D2F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
4017. D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
4018. D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
4019. D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
4020. D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
4021. D2F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
4022. D2F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
4023. D2F2_SSID_CAP_LIST__CAP_ID_MASK
4024. D2F2_SSID_CAP_LIST__CAP_ID__SHIFT
4025. D2F2_SSID_CAP_LIST__NEXT_PTR_MASK
4026. D2F2_SSID_CAP_LIST__NEXT_PTR__SHIFT
4027. D2F2_SSID_CAP__SUBSYSTEM_ID_MASK
4028. D2F2_SSID_CAP__SUBSYSTEM_ID__SHIFT
4029. D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
4030. D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
4031. D2F2_STATUS__CAP_LIST_MASK
4032. D2F2_STATUS__CAP_LIST__SHIFT
4033. D2F2_STATUS__DEVSEL_TIMING_MASK
4034. D2F2_STATUS__DEVSEL_TIMING__SHIFT
4035. D2F2_STATUS__FAST_BACK_CAPABLE_MASK
4036. D2F2_STATUS__FAST_BACK_CAPABLE__SHIFT
4037. D2F2_STATUS__INT_STATUS_MASK
4038. D2F2_STATUS__INT_STATUS__SHIFT
4039. D2F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
4040. D2F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
4041. D2F2_STATUS__PARITY_ERROR_DETECTED_MASK
4042. D2F2_STATUS__PARITY_ERROR_DETECTED__SHIFT
4043. D2F2_STATUS__PCI_66_EN_MASK
4044. D2F2_STATUS__PCI_66_EN__SHIFT
4045. D2F2_STATUS__RECEIVED_MASTER_ABORT_MASK
4046. D2F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
4047. D2F2_STATUS__RECEIVED_TARGET_ABORT_MASK
4048. D2F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
4049. D2F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
4050. D2F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
4051. D2F2_STATUS__SIGNAL_TARGET_ABORT_MASK
4052. D2F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
4053. D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
4054. D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
4055. D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
4056. D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
4057. D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
4058. D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
4059. D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
4060. D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
4061. D2F2_SUB_CLASS__SUB_CLASS_MASK
4062. D2F2_SUB_CLASS__SUB_CLASS__SHIFT
4063. D2F2_VENDOR_ID__VENDOR_ID_MASK
4064. D2F2_VENDOR_ID__VENDOR_ID__SHIFT
4065. D2F3_BASE_CLASS__BASE_CLASS_MASK
4066. D2F3_BASE_CLASS__BASE_CLASS__SHIFT
4067. D2F3_BIST__BIST_CAP_MASK
4068. D2F3_BIST__BIST_CAP__SHIFT
4069. D2F3_BIST__BIST_COMP_MASK
4070. D2F3_BIST__BIST_COMP__SHIFT
4071. D2F3_BIST__BIST_STRT_MASK
4072. D2F3_BIST__BIST_STRT__SHIFT
4073. D2F3_CACHE_LINE__CACHE_LINE_SIZE_MASK
4074. D2F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
4075. D2F3_CAP_PTR__CAP_PTR_MASK
4076. D2F3_CAP_PTR__CAP_PTR__SHIFT
4077. D2F3_COMMAND__AD_STEPPING_MASK
4078. D2F3_COMMAND__AD_STEPPING__SHIFT
4079. D2F3_COMMAND__BUS_MASTER_EN_MASK
4080. D2F3_COMMAND__BUS_MASTER_EN__SHIFT
4081. D2F3_COMMAND__FAST_B2B_EN_MASK
4082. D2F3_COMMAND__FAST_B2B_EN__SHIFT
4083. D2F3_COMMAND__INT_DIS_MASK
4084. D2F3_COMMAND__INT_DIS__SHIFT
4085. D2F3_COMMAND__IO_ACCESS_EN_MASK
4086. D2F3_COMMAND__IO_ACCESS_EN__SHIFT
4087. D2F3_COMMAND__MEM_ACCESS_EN_MASK
4088. D2F3_COMMAND__MEM_ACCESS_EN__SHIFT
4089. D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
4090. D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
4091. D2F3_COMMAND__PAL_SNOOP_EN_MASK
4092. D2F3_COMMAND__PAL_SNOOP_EN__SHIFT
4093. D2F3_COMMAND__PARITY_ERROR_RESPONSE_MASK
4094. D2F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
4095. D2F3_COMMAND__SERR_EN_MASK
4096. D2F3_COMMAND__SERR_EN__SHIFT
4097. D2F3_COMMAND__SPECIAL_CYCLE_EN_MASK
4098. D2F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT
4099. D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
4100. D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
4101. D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
4102. D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
4103. D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
4104. D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
4105. D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
4106. D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
4107. D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
4108. D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
4109. D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
4110. D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
4111. D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
4112. D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
4113. D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
4114. D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
4115. D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
4116. D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
4117. D2F3_DEVICE_CAP2__LTR_SUPPORTED_MASK
4118. D2F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
4119. D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
4120. D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
4121. D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
4122. D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
4123. D2F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK
4124. D2F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
4125. D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
4126. D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
4127. D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
4128. D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
4129. D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
4130. D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
4131. D2F3_DEVICE_CAP__EXTENDED_TAG_MASK
4132. D2F3_DEVICE_CAP__EXTENDED_TAG__SHIFT
4133. D2F3_DEVICE_CAP__FLR_CAPABLE_MASK
4134. D2F3_DEVICE_CAP__FLR_CAPABLE__SHIFT
4135. D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
4136. D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
4137. D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
4138. D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
4139. D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
4140. D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
4141. D2F3_DEVICE_CAP__PHANTOM_FUNC_MASK
4142. D2F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT
4143. D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
4144. D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
4145. D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
4146. D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
4147. D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
4148. D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
4149. D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
4150. D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
4151. D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
4152. D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
4153. D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
4154. D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
4155. D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
4156. D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
4157. D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
4158. D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
4159. D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
4160. D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
4161. D2F3_DEVICE_CNTL2__LTR_EN_MASK
4162. D2F3_DEVICE_CNTL2__LTR_EN__SHIFT
4163. D2F3_DEVICE_CNTL2__OBFF_EN_MASK
4164. D2F3_DEVICE_CNTL2__OBFF_EN__SHIFT
4165. D2F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
4166. D2F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
4167. D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
4168. D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
4169. D2F3_DEVICE_CNTL__CORR_ERR_EN_MASK
4170. D2F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT
4171. D2F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
4172. D2F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
4173. D2F3_DEVICE_CNTL__FATAL_ERR_EN_MASK
4174. D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
4175. D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
4176. D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
4177. D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
4178. D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
4179. D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
4180. D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
4181. D2F3_DEVICE_CNTL__NO_SNOOP_EN_MASK
4182. D2F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
4183. D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
4184. D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
4185. D2F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK
4186. D2F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
4187. D2F3_DEVICE_CNTL__USR_REPORT_EN_MASK
4188. D2F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT
4189. D2F3_DEVICE_ID__DEVICE_ID_MASK
4190. D2F3_DEVICE_ID__DEVICE_ID__SHIFT
4191. D2F3_DEVICE_STATUS2__RESERVED_MASK
4192. D2F3_DEVICE_STATUS2__RESERVED__SHIFT
4193. D2F3_DEVICE_STATUS__AUX_PWR_MASK
4194. D2F3_DEVICE_STATUS__AUX_PWR__SHIFT
4195. D2F3_DEVICE_STATUS__CORR_ERR_MASK
4196. D2F3_DEVICE_STATUS__CORR_ERR__SHIFT
4197. D2F3_DEVICE_STATUS__FATAL_ERR_MASK
4198. D2F3_DEVICE_STATUS__FATAL_ERR__SHIFT
4199. D2F3_DEVICE_STATUS__NON_FATAL_ERR_MASK
4200. D2F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
4201. D2F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
4202. D2F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
4203. D2F3_DEVICE_STATUS__USR_DETECTED_MASK
4204. D2F3_DEVICE_STATUS__USR_DETECTED__SHIFT
4205. D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
4206. D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
4207. D2F3_HEADER__DEVICE_TYPE_MASK
4208. D2F3_HEADER__DEVICE_TYPE__SHIFT
4209. D2F3_HEADER__HEADER_TYPE_MASK
4210. D2F3_HEADER__HEADER_TYPE__SHIFT
4211. D2F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK
4212. D2F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
4213. D2F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK
4214. D2F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
4215. D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
4216. D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
4217. D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
4218. D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
4219. D2F3_IO_BASE_LIMIT__IO_BASE_MASK
4220. D2F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
4221. D2F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
4222. D2F3_IO_BASE_LIMIT__IO_BASE__SHIFT
4223. D2F3_IO_BASE_LIMIT__IO_LIMIT_MASK
4224. D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
4225. D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
4226. D2F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT
4227. D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
4228. D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
4229. D2F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK
4230. D2F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
4231. D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
4232. D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
4233. D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
4234. D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
4235. D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
4236. D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
4237. D2F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK
4238. D2F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
4239. D2F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
4240. D2F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
4241. D2F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK
4242. D2F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
4243. D2F3_LATENCY__LATENCY_TIMER_MASK
4244. D2F3_LATENCY__LATENCY_TIMER__SHIFT
4245. D2F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
4246. D2F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
4247. D2F3_LINK_CAP2__RESERVED_MASK
4248. D2F3_LINK_CAP2__RESERVED__SHIFT
4249. D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
4250. D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
4251. D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
4252. D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
4253. D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
4254. D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
4255. D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
4256. D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
4257. D2F3_LINK_CAP__L0S_EXIT_LATENCY_MASK
4258. D2F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
4259. D2F3_LINK_CAP__L1_EXIT_LATENCY_MASK
4260. D2F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT
4261. D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
4262. D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
4263. D2F3_LINK_CAP__LINK_SPEED_MASK
4264. D2F3_LINK_CAP__LINK_SPEED__SHIFT
4265. D2F3_LINK_CAP__LINK_WIDTH_MASK
4266. D2F3_LINK_CAP__LINK_WIDTH__SHIFT
4267. D2F3_LINK_CAP__PM_SUPPORT_MASK
4268. D2F3_LINK_CAP__PM_SUPPORT__SHIFT
4269. D2F3_LINK_CAP__PORT_NUMBER_MASK
4270. D2F3_LINK_CAP__PORT_NUMBER__SHIFT
4271. D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
4272. D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
4273. D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
4274. D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
4275. D2F3_LINK_CNTL2__COMPLIANCE_SOS_MASK
4276. D2F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
4277. D2F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK
4278. D2F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
4279. D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
4280. D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
4281. D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
4282. D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
4283. D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
4284. D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
4285. D2F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK
4286. D2F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
4287. D2F3_LINK_CNTL2__XMIT_MARGIN_MASK
4288. D2F3_LINK_CNTL2__XMIT_MARGIN__SHIFT
4289. D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
4290. D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
4291. D2F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK
4292. D2F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
4293. D2F3_LINK_CNTL__EXTENDED_SYNC_MASK
4294. D2F3_LINK_CNTL__EXTENDED_SYNC__SHIFT
4295. D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
4296. D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
4297. D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
4298. D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
4299. D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
4300. D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
4301. D2F3_LINK_CNTL__LINK_DIS_MASK
4302. D2F3_LINK_CNTL__LINK_DIS__SHIFT
4303. D2F3_LINK_CNTL__PM_CONTROL_MASK
4304. D2F3_LINK_CNTL__PM_CONTROL__SHIFT
4305. D2F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK
4306. D2F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
4307. D2F3_LINK_CNTL__RETRAIN_LINK_MASK
4308. D2F3_LINK_CNTL__RETRAIN_LINK__SHIFT
4309. D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
4310. D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
4311. D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
4312. D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
4313. D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
4314. D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
4315. D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
4316. D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
4317. D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
4318. D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
4319. D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
4320. D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
4321. D2F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK
4322. D2F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
4323. D2F3_LINK_STATUS__DL_ACTIVE_MASK
4324. D2F3_LINK_STATUS__DL_ACTIVE__SHIFT
4325. D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
4326. D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
4327. D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
4328. D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
4329. D2F3_LINK_STATUS__LINK_TRAINING_MASK
4330. D2F3_LINK_STATUS__LINK_TRAINING__SHIFT
4331. D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
4332. D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
4333. D2F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK
4334. D2F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
4335. D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
4336. D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
4337. D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
4338. D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
4339. D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
4340. D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
4341. D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
4342. D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
4343. D2F3_MSI_CAP_LIST__CAP_ID_MASK
4344. D2F3_MSI_CAP_LIST__CAP_ID__SHIFT
4345. D2F3_MSI_CAP_LIST__NEXT_PTR_MASK
4346. D2F3_MSI_CAP_LIST__NEXT_PTR__SHIFT
4347. D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
4348. D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
4349. D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
4350. D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
4351. D2F3_MSI_MAP_CAP_LIST__CAP_ID_MASK
4352. D2F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
4353. D2F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
4354. D2F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
4355. D2F3_MSI_MAP_CAP__CAP_TYPE_MASK
4356. D2F3_MSI_MAP_CAP__CAP_TYPE__SHIFT
4357. D2F3_MSI_MAP_CAP__EN_MASK
4358. D2F3_MSI_MAP_CAP__EN__SHIFT
4359. D2F3_MSI_MAP_CAP__FIXD_MASK
4360. D2F3_MSI_MAP_CAP__FIXD__SHIFT
4361. D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
4362. D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
4363. D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
4364. D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
4365. D2F3_MSI_MSG_CNTL__MSI_64BIT_MASK
4366. D2F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT
4367. D2F3_MSI_MSG_CNTL__MSI_EN_MASK
4368. D2F3_MSI_MSG_CNTL__MSI_EN__SHIFT
4369. D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
4370. D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
4371. D2F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
4372. D2F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
4373. D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
4374. D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
4375. D2F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK
4376. D2F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
4377. D2F3_MSI_MSG_DATA__MSI_DATA_MASK
4378. D2F3_MSI_MSG_DATA__MSI_DATA__SHIFT
4379. D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
4380. D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
4381. D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
4382. D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
4383. D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
4384. D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
4385. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
4386. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
4387. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
4388. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
4389. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
4390. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
4391. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
4392. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
4393. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
4394. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
4395. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
4396. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
4397. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
4398. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
4399. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
4400. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
4401. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
4402. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
4403. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
4404. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
4405. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
4406. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
4407. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
4408. D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
4409. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
4410. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
4411. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
4412. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
4413. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
4414. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
4415. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
4416. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
4417. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
4418. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
4419. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
4420. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
4421. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
4422. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
4423. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
4424. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
4425. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
4426. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
4427. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
4428. D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
4429. D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
4430. D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
4431. D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
4432. D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
4433. D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
4434. D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
4435. D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
4436. D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
4437. D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
4438. D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
4439. D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
4440. D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
4441. D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
4442. D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
4443. D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
4444. D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
4445. D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
4446. D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
4447. D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
4448. D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
4449. D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
4450. D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
4451. D2F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK
4452. D2F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
4453. D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
4454. D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
4455. D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
4456. D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
4457. D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
4458. D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
4459. D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
4460. D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
4461. D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
4462. D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
4463. D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
4464. D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
4465. D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
4466. D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
4467. D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
4468. D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
4469. D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
4470. D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
4471. D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
4472. D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
4473. D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
4474. D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
4475. D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
4476. D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
4477. D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
4478. D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
4479. D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
4480. D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
4481. D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
4482. D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
4483. D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
4484. D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
4485. D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
4486. D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
4487. D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
4488. D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
4489. D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
4490. D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
4491. D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
4492. D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
4493. D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
4494. D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
4495. D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
4496. D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
4497. D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
4498. D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
4499. D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
4500. D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
4501. D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
4502. D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
4503. D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
4504. D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
4505. D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
4506. D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
4507. D2F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK
4508. D2F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
4509. D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
4510. D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
4511. D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
4512. D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
4513. D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
4514. D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
4515. D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
4516. D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
4517. D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
4518. D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
4519. D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
4520. D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
4521. D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
4522. D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
4523. D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
4524. D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
4525. D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
4526. D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
4527. D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
4528. D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
4529. D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
4530. D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
4531. D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
4532. D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
4533. D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
4534. D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
4535. D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
4536. D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
4537. D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
4538. D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
4539. D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
4540. D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
4541. D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
4542. D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
4543. D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
4544. D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
4545. D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
4546. D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
4547. D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
4548. D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
4549. D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
4550. D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
4551. D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
4552. D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
4553. D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
4554. D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
4555. D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
4556. D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
4557. D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
4558. D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
4559. D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
4560. D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
4561. D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
4562. D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
4563. D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
4564. D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
4565. D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
4566. D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
4567. D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
4568. D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
4569. D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
4570. D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
4571. D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
4572. D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
4573. D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
4574. D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
4575. D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
4576. D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
4577. D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
4578. D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
4579. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
4580. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
4581. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
4582. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
4583. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
4584. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
4585. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
4586. D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
4587. D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
4588. D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
4589. D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
4590. D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
4591. D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
4592. D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
4593. D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
4594. D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
4595. D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
4596. D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
4597. D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
4598. D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
4599. D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
4600. D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
4601. D2F3_PCIE_CAP_LIST__CAP_ID_MASK
4602. D2F3_PCIE_CAP_LIST__CAP_ID__SHIFT
4603. D2F3_PCIE_CAP_LIST__NEXT_PTR_MASK
4604. D2F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT
4605. D2F3_PCIE_CAP__DEVICE_TYPE_MASK
4606. D2F3_PCIE_CAP__DEVICE_TYPE__SHIFT
4607. D2F3_PCIE_CAP__INT_MESSAGE_NUM_MASK
4608. D2F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
4609. D2F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK
4610. D2F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
4611. D2F3_PCIE_CAP__VERSION_MASK
4612. D2F3_PCIE_CAP__VERSION__SHIFT
4613. D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
4614. D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
4615. D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
4616. D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
4617. D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
4618. D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
4619. D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
4620. D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
4621. D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
4622. D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
4623. D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
4624. D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
4625. D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
4626. D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
4627. D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
4628. D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
4629. D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
4630. D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
4631. D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
4632. D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
4633. D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
4634. D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
4635. D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
4636. D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
4637. D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
4638. D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
4639. D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
4640. D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
4641. D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
4642. D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
4643. D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
4644. D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
4645. D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
4646. D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
4647. D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
4648. D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
4649. D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
4650. D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
4651. D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
4652. D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
4653. D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
4654. D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
4655. D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
4656. D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
4657. D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
4658. D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
4659. D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
4660. D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
4661. D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
4662. D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
4663. D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
4664. D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
4665. D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
4666. D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
4667. D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
4668. D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
4669. D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
4670. D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
4671. D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
4672. D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
4673. D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
4674. D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
4675. D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
4676. D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
4677. D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
4678. D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
4679. D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
4680. D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
4681. D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
4682. D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
4683. D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
4684. D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
4685. D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
4686. D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
4687. D2F3_PCIE_FC_CPL__CPLD_CREDITS_MASK
4688. D2F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
4689. D2F3_PCIE_FC_CPL__CPLH_CREDITS_MASK
4690. D2F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
4691. D2F3_PCIE_FC_NP__NPD_CREDITS_MASK
4692. D2F3_PCIE_FC_NP__NPD_CREDITS__SHIFT
4693. D2F3_PCIE_FC_NP__NPH_CREDITS_MASK
4694. D2F3_PCIE_FC_NP__NPH_CREDITS__SHIFT
4695. D2F3_PCIE_FC_P__PD_CREDITS_MASK
4696. D2F3_PCIE_FC_P__PD_CREDITS__SHIFT
4697. D2F3_PCIE_FC_P__PH_CREDITS_MASK
4698. D2F3_PCIE_FC_P__PH_CREDITS__SHIFT
4699. D2F3_PCIE_HDR_LOG0__TLP_HDR_MASK
4700. D2F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT
4701. D2F3_PCIE_HDR_LOG1__TLP_HDR_MASK
4702. D2F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT
4703. D2F3_PCIE_HDR_LOG2__TLP_HDR_MASK
4704. D2F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT
4705. D2F3_PCIE_HDR_LOG3__TLP_HDR_MASK
4706. D2F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT
4707. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4708. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4709. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4710. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4711. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
4712. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
4713. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4714. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4715. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4716. D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4717. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4718. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4719. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4720. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4721. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
4722. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
4723. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4724. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4725. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4726. D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4727. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4728. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4729. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4730. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4731. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
4732. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
4733. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4734. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4735. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4736. D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4737. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4738. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4739. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4740. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4741. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
4742. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
4743. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4744. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4745. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4746. D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4747. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4748. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4749. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4750. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4751. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
4752. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
4753. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4754. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4755. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4756. D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4757. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4758. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4759. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4760. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4761. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
4762. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
4763. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4764. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4765. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4766. D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4767. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4768. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4769. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4770. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4771. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
4772. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
4773. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4774. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4775. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4776. D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4777. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4778. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4779. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4780. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4781. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
4782. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
4783. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4784. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4785. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4786. D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4787. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4788. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4789. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4790. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4791. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
4792. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
4793. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4794. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4795. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4796. D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4797. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4798. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4799. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4800. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4801. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
4802. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
4803. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4804. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4805. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4806. D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4807. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4808. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4809. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4810. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4811. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
4812. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
4813. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4814. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4815. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4816. D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4817. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4818. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4819. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4820. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4821. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
4822. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
4823. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4824. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4825. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4826. D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4827. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4828. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4829. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4830. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4831. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
4832. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
4833. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4834. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4835. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4836. D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4837. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4838. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4839. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4840. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4841. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
4842. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
4843. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4844. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4845. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4846. D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4847. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4848. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4849. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4850. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4851. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
4852. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
4853. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4854. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4855. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4856. D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4857. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
4858. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
4859. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
4860. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
4861. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
4862. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
4863. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
4864. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
4865. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
4866. D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
4867. D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
4868. D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
4869. D2F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
4870. D2F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
4871. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
4872. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
4873. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
4874. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
4875. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
4876. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
4877. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
4878. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
4879. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
4880. D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
4881. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
4882. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
4883. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
4884. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
4885. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
4886. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
4887. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
4888. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
4889. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
4890. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
4891. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
4892. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
4893. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
4894. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
4895. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
4896. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
4897. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
4898. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
4899. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
4900. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
4901. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
4902. D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
4903. D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
4904. D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
4905. D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
4906. D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
4907. D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
4908. D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
4909. D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
4910. D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
4911. D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
4912. D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
4913. D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
4914. D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
4915. D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
4916. D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
4917. D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
4918. D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
4919. D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
4920. D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
4921. D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
4922. D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
4923. D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
4924. D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
4925. D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
4926. D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
4927. D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
4928. D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
4929. D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
4930. D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
4931. D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
4932. D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
4933. D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
4934. D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
4935. D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
4936. D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
4937. D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
4938. D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
4939. D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
4940. D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
4941. D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
4942. D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
4943. D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
4944. D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
4945. D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
4946. D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
4947. D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
4948. D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
4949. D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
4950. D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
4951. D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
4952. D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
4953. D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
4954. D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
4955. D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
4956. D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
4957. D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
4958. D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
4959. D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
4960. D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
4961. D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
4962. D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
4963. D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
4964. D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
4965. D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
4966. D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
4967. D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
4968. D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
4969. D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
4970. D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
4971. D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
4972. D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
4973. D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
4974. D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
4975. D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
4976. D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
4977. D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
4978. D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
4979. D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
4980. D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
4981. D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
4982. D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
4983. D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
4984. D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
4985. D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
4986. D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
4987. D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
4988. D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
4989. D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
4990. D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
4991. D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
4992. D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
4993. D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
4994. D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
4995. D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
4996. D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
4997. D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
4998. D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
4999. D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
5000. D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
5001. D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
5002. D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
5003. D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
5004. D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
5005. D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
5006. D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
5007. D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
5008. D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
5009. D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
5010. D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
5011. D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
5012. D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
5013. D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
5014. D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
5015. D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
5016. D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
5017. D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
5018. D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
5019. D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
5020. D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
5021. D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
5022. D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
5023. D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
5024. D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
5025. D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
5026. D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
5027. D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
5028. D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
5029. D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
5030. D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
5031. D2F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
5032. D2F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
5033. D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
5034. D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
5035. D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
5036. D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
5037. D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
5038. D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
5039. D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
5040. D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
5041. D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
5042. D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
5043. D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
5044. D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
5045. D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
5046. D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
5047. D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
5048. D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
5049. D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
5050. D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
5051. D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
5052. D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
5053. D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
5054. D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
5055. D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
5056. D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
5057. D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
5058. D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
5059. D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
5060. D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
5061. D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
5062. D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
5063. D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
5064. D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
5065. D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
5066. D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
5067. D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
5068. D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
5069. D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
5070. D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
5071. D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
5072. D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
5073. D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
5074. D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
5075. D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
5076. D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
5077. D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
5078. D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
5079. D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
5080. D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
5081. D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
5082. D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
5083. D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
5084. D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
5085. D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
5086. D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
5087. D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
5088. D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
5089. D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
5090. D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
5091. D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
5092. D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
5093. D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
5094. D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
5095. D2F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK
5096. D2F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
5097. D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
5098. D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
5099. D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
5100. D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
5101. D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
5102. D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
5103. D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
5104. D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
5105. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
5106. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
5107. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
5108. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
5109. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
5110. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
5111. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
5112. D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
5113. D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
5114. D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
5115. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
5116. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
5117. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
5118. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
5119. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
5120. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
5121. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
5122. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
5123. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
5124. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
5125. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
5126. D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
5127. D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
5128. D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
5129. D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
5130. D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
5131. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
5132. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
5133. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
5134. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
5135. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
5136. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
5137. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
5138. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
5139. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
5140. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
5141. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
5142. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
5143. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
5144. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
5145. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
5146. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
5147. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
5148. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
5149. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
5150. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
5151. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
5152. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
5153. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
5154. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
5155. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
5156. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
5157. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
5158. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
5159. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
5160. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
5161. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
5162. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
5163. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
5164. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
5165. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
5166. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
5167. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
5168. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
5169. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
5170. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
5171. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
5172. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
5173. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
5174. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
5175. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
5176. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
5177. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
5178. D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
5179. D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
5180. D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
5181. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
5182. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
5183. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
5184. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
5185. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
5186. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
5187. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
5188. D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
5189. D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
5190. D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
5191. D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
5192. D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
5193. D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
5194. D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
5195. D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
5196. D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
5197. D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
5198. D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
5199. D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
5200. D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
5201. D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
5202. D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
5203. D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
5204. D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
5205. D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
5206. D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
5207. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
5208. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
5209. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
5210. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
5211. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
5212. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
5213. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
5214. D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
5215. D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
5216. D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
5217. D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
5218. D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
5219. D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
5220. D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
5221. D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
5222. D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
5223. D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
5224. D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
5225. D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
5226. D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
5227. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
5228. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
5229. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
5230. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
5231. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
5232. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
5233. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
5234. D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
5235. D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
5236. D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
5237. D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
5238. D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
5239. D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
5240. D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
5241. D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
5242. D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
5243. D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
5244. D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
5245. D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
5246. D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
5247. D2F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
5248. D2F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
5249. D2F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
5250. D2F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
5251. D2F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
5252. D2F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
5253. D2F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
5254. D2F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
5255. D2F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
5256. D2F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
5257. D2F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
5258. D2F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
5259. D2F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
5260. D2F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
5261. D2F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
5262. D2F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
5263. D2F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
5264. D2F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
5265. D2F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
5266. D2F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
5267. D2F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
5268. D2F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
5269. D2F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
5270. D2F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
5271. D2F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
5272. D2F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
5273. D2F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
5274. D2F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
5275. D2F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
5276. D2F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
5277. D2F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
5278. D2F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
5279. D2F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
5280. D2F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
5281. D2F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
5282. D2F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
5283. D2F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
5284. D2F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
5285. D2F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
5286. D2F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
5287. D2F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
5288. D2F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
5289. D2F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
5290. D2F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
5291. D2F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
5292. D2F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
5293. D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
5294. D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
5295. D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
5296. D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
5297. D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
5298. D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
5299. D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
5300. D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
5301. D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
5302. D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
5303. D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
5304. D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
5305. D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
5306. D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
5307. D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
5308. D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
5309. D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
5310. D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
5311. D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
5312. D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
5313. D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
5314. D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
5315. D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
5316. D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
5317. D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
5318. D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
5319. D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
5320. D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
5321. D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
5322. D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
5323. D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
5324. D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
5325. D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
5326. D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
5327. D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
5328. D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
5329. D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
5330. D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
5331. D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
5332. D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
5333. D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
5334. D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
5335. D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
5336. D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
5337. D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
5338. D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
5339. D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
5340. D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
5341. D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
5342. D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
5343. D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
5344. D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
5345. D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
5346. D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
5347. D2F3_PCIE_LINK_CNTL3__RESERVED_MASK
5348. D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT
5349. D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
5350. D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
5351. D2F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
5352. D2F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
5353. D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
5354. D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
5355. D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
5356. D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
5357. D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
5358. D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
5359. D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
5360. D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
5361. D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
5362. D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
5363. D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
5364. D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
5365. D2F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK
5366. D2F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
5367. D2F3_PCIE_MC_CNTL__MC_ENABLE_MASK
5368. D2F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT
5369. D2F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
5370. D2F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
5371. D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
5372. D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
5373. D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
5374. D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
5375. D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
5376. D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
5377. D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
5378. D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
5379. D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
5380. D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
5381. D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
5382. D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
5383. D2F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
5384. D2F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
5385. D2F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
5386. D2F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
5387. D2F3_PCIE_PORT_DATA__PCIE_DATA_MASK
5388. D2F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT
5389. D2F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK
5390. D2F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
5391. D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
5392. D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
5393. D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
5394. D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
5395. D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
5396. D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
5397. D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
5398. D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
5399. D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
5400. D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
5401. D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
5402. D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
5403. D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
5404. D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
5405. D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
5406. D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
5407. D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
5408. D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
5409. D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
5410. D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
5411. D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
5412. D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
5413. D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
5414. D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
5415. D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
5416. D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
5417. D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
5418. D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
5419. D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
5420. D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
5421. D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
5422. D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
5423. D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
5424. D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
5425. D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
5426. D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
5427. D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
5428. D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
5429. D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
5430. D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
5431. D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
5432. D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
5433. D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
5434. D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
5435. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
5436. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
5437. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
5438. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
5439. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
5440. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
5441. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
5442. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
5443. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
5444. D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
5445. D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
5446. D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
5447. D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
5448. D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
5449. D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
5450. D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
5451. D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
5452. D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
5453. D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
5454. D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
5455. D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
5456. D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
5457. D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
5458. D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
5459. D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
5460. D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
5461. D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
5462. D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
5463. D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
5464. D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
5465. D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
5466. D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
5467. D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
5468. D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
5469. D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
5470. D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
5471. D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
5472. D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
5473. D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
5474. D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
5475. D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
5476. D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
5477. D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
5478. D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
5479. D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
5480. D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
5481. D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
5482. D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
5483. D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
5484. D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
5485. D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
5486. D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
5487. D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
5488. D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
5489. D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
5490. D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
5491. D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
5492. D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
5493. D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
5494. D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
5495. D2F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK
5496. D2F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
5497. D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
5498. D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
5499. D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
5500. D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
5501. D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
5502. D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
5503. D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
5504. D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
5505. D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
5506. D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
5507. D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
5508. D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
5509. D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
5510. D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
5511. D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
5512. D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
5513. D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
5514. D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
5515. D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
5516. D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
5517. D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
5518. D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
5519. D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
5520. D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
5521. D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
5522. D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
5523. D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
5524. D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
5525. D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
5526. D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
5527. D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
5528. D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
5529. D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
5530. D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
5531. D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
5532. D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
5533. D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
5534. D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
5535. D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
5536. D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
5537. D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
5538. D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
5539. D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
5540. D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
5541. D2F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
5542. D2F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
5543. D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
5544. D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
5545. D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
5546. D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
5547. D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
5548. D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
5549. D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
5550. D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
5551. D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
5552. D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
5553. D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
5554. D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
5555. D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
5556. D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
5557. D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
5558. D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
5559. D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
5560. D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
5561. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
5562. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
5563. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
5564. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
5565. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
5566. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
5567. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
5568. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
5569. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
5570. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
5571. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
5572. D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
5573. D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
5574. D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
5575. D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
5576. D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
5577. D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
5578. D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
5579. D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
5580. D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
5581. D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
5582. D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
5583. D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
5584. D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
5585. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
5586. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
5587. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
5588. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
5589. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
5590. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
5591. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
5592. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
5593. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
5594. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
5595. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
5596. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
5597. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
5598. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
5599. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
5600. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
5601. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
5602. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
5603. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
5604. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
5605. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
5606. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
5607. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
5608. D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
5609. D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
5610. D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
5611. D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
5612. D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
5613. D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
5614. D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
5615. D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
5616. D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
5617. D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
5618. D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
5619. D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
5620. D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
5621. D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
5622. D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
5623. D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
5624. D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
5625. D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
5626. D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
5627. D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
5628. D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
5629. D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
5630. D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
5631. D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
5632. D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
5633. D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
5634. D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
5635. D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
5636. D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
5637. D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
5638. D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
5639. D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
5640. D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
5641. D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
5642. D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
5643. D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
5644. D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
5645. D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
5646. D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
5647. D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
5648. D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
5649. D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
5650. D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
5651. D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
5652. D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
5653. D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
5654. D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
5655. D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
5656. D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
5657. D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
5658. D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
5659. D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
5660. D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
5661. D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
5662. D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
5663. D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
5664. D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
5665. D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
5666. D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
5667. D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
5668. D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
5669. D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
5670. D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
5671. D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
5672. D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
5673. D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
5674. D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
5675. D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
5676. D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
5677. D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
5678. D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
5679. D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
5680. D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
5681. D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
5682. D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
5683. D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
5684. D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
5685. D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
5686. D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
5687. D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
5688. D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
5689. D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
5690. D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
5691. D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
5692. D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
5693. D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
5694. D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
5695. D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
5696. D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
5697. D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
5698. D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
5699. D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
5700. D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
5701. D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
5702. D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
5703. D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
5704. D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
5705. D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
5706. D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
5707. D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
5708. D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
5709. D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
5710. D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
5711. D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
5712. D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
5713. D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
5714. D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
5715. D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
5716. D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
5717. D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
5718. D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
5719. D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
5720. D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
5721. D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
5722. D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
5723. D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
5724. D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
5725. D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
5726. D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
5727. D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
5728. D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
5729. D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
5730. D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
5731. D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
5732. D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
5733. D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
5734. D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
5735. D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
5736. D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
5737. D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
5738. D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
5739. D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
5740. D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
5741. D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
5742. D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
5743. D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
5744. D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
5745. D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
5746. D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
5747. D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
5748. D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
5749. D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
5750. D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
5751. D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
5752. D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
5753. D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
5754. D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
5755. D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
5756. D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
5757. D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
5758. D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
5759. D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
5760. D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
5761. D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
5762. D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
5763. D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
5764. D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
5765. D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
5766. D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
5767. D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
5768. D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
5769. D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
5770. D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
5771. D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
5772. D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
5773. D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
5774. D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
5775. D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
5776. D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
5777. D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
5778. D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
5779. D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
5780. D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
5781. D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
5782. D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
5783. D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
5784. D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
5785. D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
5786. D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
5787. D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
5788. D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
5789. D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
5790. D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
5791. D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
5792. D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
5793. D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
5794. D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
5795. D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
5796. D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
5797. D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
5798. D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
5799. D2F3_PMI_CAP_LIST__CAP_ID_MASK
5800. D2F3_PMI_CAP_LIST__CAP_ID__SHIFT
5801. D2F3_PMI_CAP_LIST__NEXT_PTR_MASK
5802. D2F3_PMI_CAP_LIST__NEXT_PTR__SHIFT
5803. D2F3_PMI_CAP__AUX_CURRENT_MASK
5804. D2F3_PMI_CAP__AUX_CURRENT__SHIFT
5805. D2F3_PMI_CAP__D1_SUPPORT_MASK
5806. D2F3_PMI_CAP__D1_SUPPORT__SHIFT
5807. D2F3_PMI_CAP__D2_SUPPORT_MASK
5808. D2F3_PMI_CAP__D2_SUPPORT__SHIFT
5809. D2F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK
5810. D2F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
5811. D2F3_PMI_CAP__PME_CLOCK_MASK
5812. D2F3_PMI_CAP__PME_CLOCK__SHIFT
5813. D2F3_PMI_CAP__PME_SUPPORT_MASK
5814. D2F3_PMI_CAP__PME_SUPPORT__SHIFT
5815. D2F3_PMI_CAP__VERSION_MASK
5816. D2F3_PMI_CAP__VERSION__SHIFT
5817. D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
5818. D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
5819. D2F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
5820. D2F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
5821. D2F3_PMI_STATUS_CNTL__DATA_SCALE_MASK
5822. D2F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
5823. D2F3_PMI_STATUS_CNTL__DATA_SELECT_MASK
5824. D2F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
5825. D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
5826. D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
5827. D2F3_PMI_STATUS_CNTL__PME_EN_MASK
5828. D2F3_PMI_STATUS_CNTL__PME_EN__SHIFT
5829. D2F3_PMI_STATUS_CNTL__PME_STATUS_MASK
5830. D2F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT
5831. D2F3_PMI_STATUS_CNTL__PMI_DATA_MASK
5832. D2F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT
5833. D2F3_PMI_STATUS_CNTL__POWER_STATE_MASK
5834. D2F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT
5835. D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
5836. D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
5837. D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
5838. D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
5839. D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
5840. D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
5841. D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
5842. D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
5843. D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
5844. D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
5845. D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
5846. D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
5847. D2F3_PROG_INTERFACE__PROG_INTERFACE_MASK
5848. D2F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT
5849. D2F3_REVISION_ID__MAJOR_REV_ID_MASK
5850. D2F3_REVISION_ID__MAJOR_REV_ID__SHIFT
5851. D2F3_REVISION_ID__MINOR_REV_ID_MASK
5852. D2F3_REVISION_ID__MINOR_REV_ID__SHIFT
5853. D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
5854. D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
5855. D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
5856. D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
5857. D2F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK
5858. D2F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
5859. D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
5860. D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
5861. D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
5862. D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
5863. D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
5864. D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
5865. D2F3_ROOT_STATUS__PME_PENDING_MASK
5866. D2F3_ROOT_STATUS__PME_PENDING__SHIFT
5867. D2F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK
5868. D2F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
5869. D2F3_ROOT_STATUS__PME_STATUS_MASK
5870. D2F3_ROOT_STATUS__PME_STATUS__SHIFT
5871. D2F3_SECONDARY_STATUS__CAP_LIST_MASK
5872. D2F3_SECONDARY_STATUS__CAP_LIST__SHIFT
5873. D2F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK
5874. D2F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
5875. D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
5876. D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
5877. D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
5878. D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
5879. D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
5880. D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
5881. D2F3_SECONDARY_STATUS__PCI_66_EN_MASK
5882. D2F3_SECONDARY_STATUS__PCI_66_EN__SHIFT
5883. D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
5884. D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
5885. D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
5886. D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
5887. D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
5888. D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
5889. D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
5890. D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
5891. D2F3_SLOT_CAP2__RESERVED_MASK
5892. D2F3_SLOT_CAP2__RESERVED__SHIFT
5893. D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
5894. D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
5895. D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
5896. D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
5897. D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
5898. D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
5899. D2F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK
5900. D2F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
5901. D2F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK
5902. D2F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
5903. D2F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
5904. D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
5905. D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
5906. D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
5907. D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
5908. D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
5909. D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
5910. D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
5911. D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
5912. D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
5913. D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
5914. D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
5915. D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
5916. D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
5917. D2F3_SLOT_CNTL2__RESERVED_MASK
5918. D2F3_SLOT_CNTL2__RESERVED__SHIFT
5919. D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
5920. D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
5921. D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
5922. D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
5923. D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
5924. D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
5925. D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
5926. D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
5927. D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
5928. D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
5929. D2F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
5930. D2F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
5931. D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
5932. D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
5933. D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
5934. D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
5935. D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
5936. D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
5937. D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
5938. D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
5939. D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
5940. D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
5941. D2F3_SLOT_STATUS2__RESERVED_MASK
5942. D2F3_SLOT_STATUS2__RESERVED__SHIFT
5943. D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
5944. D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
5945. D2F3_SLOT_STATUS__COMMAND_COMPLETED_MASK
5946. D2F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
5947. D2F3_SLOT_STATUS__DL_STATE_CHANGED_MASK
5948. D2F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
5949. D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
5950. D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
5951. D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
5952. D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
5953. D2F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK
5954. D2F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
5955. D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
5956. D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
5957. D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
5958. D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
5959. D2F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
5960. D2F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
5961. D2F3_SSID_CAP_LIST__CAP_ID_MASK
5962. D2F3_SSID_CAP_LIST__CAP_ID__SHIFT
5963. D2F3_SSID_CAP_LIST__NEXT_PTR_MASK
5964. D2F3_SSID_CAP_LIST__NEXT_PTR__SHIFT
5965. D2F3_SSID_CAP__SUBSYSTEM_ID_MASK
5966. D2F3_SSID_CAP__SUBSYSTEM_ID__SHIFT
5967. D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
5968. D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
5969. D2F3_STATUS__CAP_LIST_MASK
5970. D2F3_STATUS__CAP_LIST__SHIFT
5971. D2F3_STATUS__DEVSEL_TIMING_MASK
5972. D2F3_STATUS__DEVSEL_TIMING__SHIFT
5973. D2F3_STATUS__FAST_BACK_CAPABLE_MASK
5974. D2F3_STATUS__FAST_BACK_CAPABLE__SHIFT
5975. D2F3_STATUS__INT_STATUS_MASK
5976. D2F3_STATUS__INT_STATUS__SHIFT
5977. D2F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK
5978. D2F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
5979. D2F3_STATUS__PARITY_ERROR_DETECTED_MASK
5980. D2F3_STATUS__PARITY_ERROR_DETECTED__SHIFT
5981. D2F3_STATUS__PCI_66_EN_MASK
5982. D2F3_STATUS__PCI_66_EN__SHIFT
5983. D2F3_STATUS__RECEIVED_MASTER_ABORT_MASK
5984. D2F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT
5985. D2F3_STATUS__RECEIVED_TARGET_ABORT_MASK
5986. D2F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT
5987. D2F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK
5988. D2F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
5989. D2F3_STATUS__SIGNAL_TARGET_ABORT_MASK
5990. D2F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT
5991. D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
5992. D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
5993. D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
5994. D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
5995. D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
5996. D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
5997. D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
5998. D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
5999. D2F3_SUB_CLASS__SUB_CLASS_MASK
6000. D2F3_SUB_CLASS__SUB_CLASS__SHIFT
6001. D2F3_VENDOR_ID__VENDOR_ID_MASK
6002. D2F3_VENDOR_ID__VENDOR_ID__SHIFT
6003. D2F4_BASE_CLASS__BASE_CLASS_MASK
6004. D2F4_BASE_CLASS__BASE_CLASS__SHIFT
6005. D2F4_BIST__BIST_CAP_MASK
6006. D2F4_BIST__BIST_CAP__SHIFT
6007. D2F4_BIST__BIST_COMP_MASK
6008. D2F4_BIST__BIST_COMP__SHIFT
6009. D2F4_BIST__BIST_STRT_MASK
6010. D2F4_BIST__BIST_STRT__SHIFT
6011. D2F4_CACHE_LINE__CACHE_LINE_SIZE_MASK
6012. D2F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
6013. D2F4_CAP_PTR__CAP_PTR_MASK
6014. D2F4_CAP_PTR__CAP_PTR__SHIFT
6015. D2F4_COMMAND__AD_STEPPING_MASK
6016. D2F4_COMMAND__AD_STEPPING__SHIFT
6017. D2F4_COMMAND__BUS_MASTER_EN_MASK
6018. D2F4_COMMAND__BUS_MASTER_EN__SHIFT
6019. D2F4_COMMAND__FAST_B2B_EN_MASK
6020. D2F4_COMMAND__FAST_B2B_EN__SHIFT
6021. D2F4_COMMAND__INT_DIS_MASK
6022. D2F4_COMMAND__INT_DIS__SHIFT
6023. D2F4_COMMAND__IO_ACCESS_EN_MASK
6024. D2F4_COMMAND__IO_ACCESS_EN__SHIFT
6025. D2F4_COMMAND__MEM_ACCESS_EN_MASK
6026. D2F4_COMMAND__MEM_ACCESS_EN__SHIFT
6027. D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
6028. D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
6029. D2F4_COMMAND__PAL_SNOOP_EN_MASK
6030. D2F4_COMMAND__PAL_SNOOP_EN__SHIFT
6031. D2F4_COMMAND__PARITY_ERROR_RESPONSE_MASK
6032. D2F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
6033. D2F4_COMMAND__SERR_EN_MASK
6034. D2F4_COMMAND__SERR_EN__SHIFT
6035. D2F4_COMMAND__SPECIAL_CYCLE_EN_MASK
6036. D2F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT
6037. D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
6038. D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
6039. D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
6040. D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
6041. D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
6042. D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
6043. D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
6044. D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
6045. D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
6046. D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
6047. D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
6048. D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
6049. D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
6050. D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
6051. D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
6052. D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
6053. D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
6054. D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
6055. D2F4_DEVICE_CAP2__LTR_SUPPORTED_MASK
6056. D2F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
6057. D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
6058. D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
6059. D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
6060. D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
6061. D2F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK
6062. D2F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
6063. D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
6064. D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
6065. D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
6066. D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
6067. D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
6068. D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
6069. D2F4_DEVICE_CAP__EXTENDED_TAG_MASK
6070. D2F4_DEVICE_CAP__EXTENDED_TAG__SHIFT
6071. D2F4_DEVICE_CAP__FLR_CAPABLE_MASK
6072. D2F4_DEVICE_CAP__FLR_CAPABLE__SHIFT
6073. D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
6074. D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
6075. D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
6076. D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
6077. D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
6078. D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
6079. D2F4_DEVICE_CAP__PHANTOM_FUNC_MASK
6080. D2F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT
6081. D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
6082. D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
6083. D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
6084. D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
6085. D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
6086. D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
6087. D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
6088. D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
6089. D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
6090. D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
6091. D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
6092. D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
6093. D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
6094. D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
6095. D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
6096. D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
6097. D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
6098. D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
6099. D2F4_DEVICE_CNTL2__LTR_EN_MASK
6100. D2F4_DEVICE_CNTL2__LTR_EN__SHIFT
6101. D2F4_DEVICE_CNTL2__OBFF_EN_MASK
6102. D2F4_DEVICE_CNTL2__OBFF_EN__SHIFT
6103. D2F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
6104. D2F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
6105. D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
6106. D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
6107. D2F4_DEVICE_CNTL__CORR_ERR_EN_MASK
6108. D2F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT
6109. D2F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
6110. D2F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
6111. D2F4_DEVICE_CNTL__FATAL_ERR_EN_MASK
6112. D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
6113. D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
6114. D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
6115. D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
6116. D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
6117. D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
6118. D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
6119. D2F4_DEVICE_CNTL__NO_SNOOP_EN_MASK
6120. D2F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
6121. D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
6122. D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
6123. D2F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK
6124. D2F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
6125. D2F4_DEVICE_CNTL__USR_REPORT_EN_MASK
6126. D2F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT
6127. D2F4_DEVICE_ID__DEVICE_ID_MASK
6128. D2F4_DEVICE_ID__DEVICE_ID__SHIFT
6129. D2F4_DEVICE_STATUS2__RESERVED_MASK
6130. D2F4_DEVICE_STATUS2__RESERVED__SHIFT
6131. D2F4_DEVICE_STATUS__AUX_PWR_MASK
6132. D2F4_DEVICE_STATUS__AUX_PWR__SHIFT
6133. D2F4_DEVICE_STATUS__CORR_ERR_MASK
6134. D2F4_DEVICE_STATUS__CORR_ERR__SHIFT
6135. D2F4_DEVICE_STATUS__FATAL_ERR_MASK
6136. D2F4_DEVICE_STATUS__FATAL_ERR__SHIFT
6137. D2F4_DEVICE_STATUS__NON_FATAL_ERR_MASK
6138. D2F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
6139. D2F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
6140. D2F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
6141. D2F4_DEVICE_STATUS__USR_DETECTED_MASK
6142. D2F4_DEVICE_STATUS__USR_DETECTED__SHIFT
6143. D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
6144. D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
6145. D2F4_HEADER__DEVICE_TYPE_MASK
6146. D2F4_HEADER__DEVICE_TYPE__SHIFT
6147. D2F4_HEADER__HEADER_TYPE_MASK
6148. D2F4_HEADER__HEADER_TYPE__SHIFT
6149. D2F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK
6150. D2F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
6151. D2F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK
6152. D2F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
6153. D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
6154. D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
6155. D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
6156. D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
6157. D2F4_IO_BASE_LIMIT__IO_BASE_MASK
6158. D2F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
6159. D2F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
6160. D2F4_IO_BASE_LIMIT__IO_BASE__SHIFT
6161. D2F4_IO_BASE_LIMIT__IO_LIMIT_MASK
6162. D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
6163. D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
6164. D2F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT
6165. D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
6166. D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
6167. D2F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK
6168. D2F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
6169. D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
6170. D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
6171. D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
6172. D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
6173. D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
6174. D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
6175. D2F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK
6176. D2F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
6177. D2F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
6178. D2F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
6179. D2F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK
6180. D2F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
6181. D2F4_LATENCY__LATENCY_TIMER_MASK
6182. D2F4_LATENCY__LATENCY_TIMER__SHIFT
6183. D2F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
6184. D2F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
6185. D2F4_LINK_CAP2__RESERVED_MASK
6186. D2F4_LINK_CAP2__RESERVED__SHIFT
6187. D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
6188. D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
6189. D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
6190. D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
6191. D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
6192. D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
6193. D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
6194. D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
6195. D2F4_LINK_CAP__L0S_EXIT_LATENCY_MASK
6196. D2F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
6197. D2F4_LINK_CAP__L1_EXIT_LATENCY_MASK
6198. D2F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT
6199. D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
6200. D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
6201. D2F4_LINK_CAP__LINK_SPEED_MASK
6202. D2F4_LINK_CAP__LINK_SPEED__SHIFT
6203. D2F4_LINK_CAP__LINK_WIDTH_MASK
6204. D2F4_LINK_CAP__LINK_WIDTH__SHIFT
6205. D2F4_LINK_CAP__PM_SUPPORT_MASK
6206. D2F4_LINK_CAP__PM_SUPPORT__SHIFT
6207. D2F4_LINK_CAP__PORT_NUMBER_MASK
6208. D2F4_LINK_CAP__PORT_NUMBER__SHIFT
6209. D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
6210. D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
6211. D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
6212. D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
6213. D2F4_LINK_CNTL2__COMPLIANCE_SOS_MASK
6214. D2F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
6215. D2F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK
6216. D2F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
6217. D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
6218. D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
6219. D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
6220. D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
6221. D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
6222. D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
6223. D2F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK
6224. D2F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
6225. D2F4_LINK_CNTL2__XMIT_MARGIN_MASK
6226. D2F4_LINK_CNTL2__XMIT_MARGIN__SHIFT
6227. D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
6228. D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
6229. D2F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK
6230. D2F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
6231. D2F4_LINK_CNTL__EXTENDED_SYNC_MASK
6232. D2F4_LINK_CNTL__EXTENDED_SYNC__SHIFT
6233. D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
6234. D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
6235. D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
6236. D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
6237. D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
6238. D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
6239. D2F4_LINK_CNTL__LINK_DIS_MASK
6240. D2F4_LINK_CNTL__LINK_DIS__SHIFT
6241. D2F4_LINK_CNTL__PM_CONTROL_MASK
6242. D2F4_LINK_CNTL__PM_CONTROL__SHIFT
6243. D2F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK
6244. D2F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
6245. D2F4_LINK_CNTL__RETRAIN_LINK_MASK
6246. D2F4_LINK_CNTL__RETRAIN_LINK__SHIFT
6247. D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
6248. D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
6249. D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
6250. D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
6251. D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
6252. D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
6253. D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
6254. D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
6255. D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
6256. D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
6257. D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
6258. D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
6259. D2F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK
6260. D2F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
6261. D2F4_LINK_STATUS__DL_ACTIVE_MASK
6262. D2F4_LINK_STATUS__DL_ACTIVE__SHIFT
6263. D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
6264. D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
6265. D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
6266. D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
6267. D2F4_LINK_STATUS__LINK_TRAINING_MASK
6268. D2F4_LINK_STATUS__LINK_TRAINING__SHIFT
6269. D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
6270. D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
6271. D2F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK
6272. D2F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
6273. D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
6274. D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
6275. D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
6276. D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
6277. D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
6278. D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
6279. D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
6280. D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
6281. D2F4_MSI_CAP_LIST__CAP_ID_MASK
6282. D2F4_MSI_CAP_LIST__CAP_ID__SHIFT
6283. D2F4_MSI_CAP_LIST__NEXT_PTR_MASK
6284. D2F4_MSI_CAP_LIST__NEXT_PTR__SHIFT
6285. D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
6286. D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
6287. D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
6288. D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
6289. D2F4_MSI_MAP_CAP_LIST__CAP_ID_MASK
6290. D2F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
6291. D2F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
6292. D2F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
6293. D2F4_MSI_MAP_CAP__CAP_TYPE_MASK
6294. D2F4_MSI_MAP_CAP__CAP_TYPE__SHIFT
6295. D2F4_MSI_MAP_CAP__EN_MASK
6296. D2F4_MSI_MAP_CAP__EN__SHIFT
6297. D2F4_MSI_MAP_CAP__FIXD_MASK
6298. D2F4_MSI_MAP_CAP__FIXD__SHIFT
6299. D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
6300. D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
6301. D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
6302. D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
6303. D2F4_MSI_MSG_CNTL__MSI_64BIT_MASK
6304. D2F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT
6305. D2F4_MSI_MSG_CNTL__MSI_EN_MASK
6306. D2F4_MSI_MSG_CNTL__MSI_EN__SHIFT
6307. D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
6308. D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
6309. D2F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
6310. D2F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
6311. D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
6312. D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
6313. D2F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK
6314. D2F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
6315. D2F4_MSI_MSG_DATA__MSI_DATA_MASK
6316. D2F4_MSI_MSG_DATA__MSI_DATA__SHIFT
6317. D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
6318. D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
6319. D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
6320. D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
6321. D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
6322. D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
6323. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
6324. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
6325. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
6326. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
6327. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
6328. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
6329. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
6330. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
6331. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
6332. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
6333. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
6334. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
6335. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
6336. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
6337. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
6338. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
6339. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
6340. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
6341. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
6342. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
6343. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
6344. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
6345. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
6346. D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
6347. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
6348. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
6349. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
6350. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
6351. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
6352. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
6353. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
6354. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
6355. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
6356. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
6357. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
6358. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
6359. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
6360. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
6361. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
6362. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
6363. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
6364. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
6365. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
6366. D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
6367. D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
6368. D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
6369. D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
6370. D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
6371. D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
6372. D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
6373. D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
6374. D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
6375. D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
6376. D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
6377. D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
6378. D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
6379. D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
6380. D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
6381. D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
6382. D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
6383. D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
6384. D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
6385. D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
6386. D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
6387. D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
6388. D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
6389. D2F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK
6390. D2F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
6391. D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
6392. D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
6393. D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
6394. D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
6395. D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
6396. D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
6397. D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
6398. D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
6399. D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
6400. D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
6401. D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
6402. D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
6403. D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
6404. D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
6405. D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
6406. D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
6407. D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
6408. D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
6409. D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
6410. D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
6411. D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
6412. D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
6413. D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
6414. D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
6415. D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
6416. D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
6417. D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
6418. D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
6419. D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
6420. D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
6421. D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
6422. D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
6423. D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
6424. D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
6425. D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
6426. D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
6427. D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
6428. D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
6429. D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
6430. D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
6431. D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
6432. D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
6433. D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
6434. D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
6435. D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
6436. D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
6437. D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
6438. D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
6439. D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
6440. D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
6441. D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
6442. D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
6443. D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
6444. D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
6445. D2F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK
6446. D2F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
6447. D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
6448. D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
6449. D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
6450. D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
6451. D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
6452. D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
6453. D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
6454. D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
6455. D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
6456. D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
6457. D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
6458. D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
6459. D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
6460. D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
6461. D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
6462. D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
6463. D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
6464. D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
6465. D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
6466. D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
6467. D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
6468. D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
6469. D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
6470. D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
6471. D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
6472. D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
6473. D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
6474. D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
6475. D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
6476. D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
6477. D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
6478. D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
6479. D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
6480. D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
6481. D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
6482. D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
6483. D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
6484. D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
6485. D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
6486. D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
6487. D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
6488. D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
6489. D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
6490. D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
6491. D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
6492. D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
6493. D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
6494. D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
6495. D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
6496. D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
6497. D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
6498. D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
6499. D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
6500. D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
6501. D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
6502. D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
6503. D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
6504. D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
6505. D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
6506. D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
6507. D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
6508. D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
6509. D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
6510. D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
6511. D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
6512. D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
6513. D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
6514. D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
6515. D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
6516. D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
6517. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
6518. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
6519. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
6520. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
6521. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
6522. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
6523. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
6524. D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
6525. D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
6526. D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
6527. D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
6528. D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
6529. D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
6530. D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
6531. D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
6532. D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
6533. D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
6534. D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
6535. D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
6536. D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
6537. D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
6538. D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
6539. D2F4_PCIE_CAP_LIST__CAP_ID_MASK
6540. D2F4_PCIE_CAP_LIST__CAP_ID__SHIFT
6541. D2F4_PCIE_CAP_LIST__NEXT_PTR_MASK
6542. D2F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT
6543. D2F4_PCIE_CAP__DEVICE_TYPE_MASK
6544. D2F4_PCIE_CAP__DEVICE_TYPE__SHIFT
6545. D2F4_PCIE_CAP__INT_MESSAGE_NUM_MASK
6546. D2F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
6547. D2F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK
6548. D2F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
6549. D2F4_PCIE_CAP__VERSION_MASK
6550. D2F4_PCIE_CAP__VERSION__SHIFT
6551. D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
6552. D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
6553. D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
6554. D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
6555. D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
6556. D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
6557. D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
6558. D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
6559. D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
6560. D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
6561. D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
6562. D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
6563. D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
6564. D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
6565. D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
6566. D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
6567. D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
6568. D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
6569. D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
6570. D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
6571. D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
6572. D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
6573. D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
6574. D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
6575. D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
6576. D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
6577. D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
6578. D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
6579. D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
6580. D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
6581. D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
6582. D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
6583. D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
6584. D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
6585. D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
6586. D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
6587. D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
6588. D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
6589. D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
6590. D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
6591. D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
6592. D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
6593. D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
6594. D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
6595. D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
6596. D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
6597. D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
6598. D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
6599. D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
6600. D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
6601. D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
6602. D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
6603. D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
6604. D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
6605. D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
6606. D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
6607. D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
6608. D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
6609. D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
6610. D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
6611. D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
6612. D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
6613. D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
6614. D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
6615. D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
6616. D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
6617. D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
6618. D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
6619. D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
6620. D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
6621. D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
6622. D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
6623. D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
6624. D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
6625. D2F4_PCIE_FC_CPL__CPLD_CREDITS_MASK
6626. D2F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
6627. D2F4_PCIE_FC_CPL__CPLH_CREDITS_MASK
6628. D2F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
6629. D2F4_PCIE_FC_NP__NPD_CREDITS_MASK
6630. D2F4_PCIE_FC_NP__NPD_CREDITS__SHIFT
6631. D2F4_PCIE_FC_NP__NPH_CREDITS_MASK
6632. D2F4_PCIE_FC_NP__NPH_CREDITS__SHIFT
6633. D2F4_PCIE_FC_P__PD_CREDITS_MASK
6634. D2F4_PCIE_FC_P__PD_CREDITS__SHIFT
6635. D2F4_PCIE_FC_P__PH_CREDITS_MASK
6636. D2F4_PCIE_FC_P__PH_CREDITS__SHIFT
6637. D2F4_PCIE_HDR_LOG0__TLP_HDR_MASK
6638. D2F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT
6639. D2F4_PCIE_HDR_LOG1__TLP_HDR_MASK
6640. D2F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT
6641. D2F4_PCIE_HDR_LOG2__TLP_HDR_MASK
6642. D2F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT
6643. D2F4_PCIE_HDR_LOG3__TLP_HDR_MASK
6644. D2F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT
6645. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6646. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6647. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6648. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6649. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
6650. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
6651. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6652. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6653. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6654. D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6655. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6656. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6657. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6658. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6659. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
6660. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
6661. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6662. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6663. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6664. D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6665. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6666. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6667. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6668. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6669. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
6670. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
6671. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6672. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6673. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6674. D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6675. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6676. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6677. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6678. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6679. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
6680. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
6681. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6682. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6683. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6684. D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6685. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6686. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6687. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6688. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6689. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
6690. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
6691. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6692. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6693. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6694. D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6695. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6696. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6697. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6698. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6699. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
6700. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
6701. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6702. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6703. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6704. D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6705. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6706. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6707. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6708. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6709. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
6710. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
6711. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6712. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6713. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6714. D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6715. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6716. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6717. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6718. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6719. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
6720. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
6721. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6722. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6723. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6724. D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6725. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6726. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6727. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6728. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6729. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
6730. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
6731. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6732. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6733. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6734. D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6735. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6736. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6737. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6738. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6739. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
6740. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
6741. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6742. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6743. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6744. D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6745. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6746. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6747. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6748. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6749. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
6750. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
6751. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6752. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6753. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6754. D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6755. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6756. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6757. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6758. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6759. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
6760. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
6761. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6762. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6763. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6764. D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6765. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6766. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6767. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6768. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6769. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
6770. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
6771. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6772. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6773. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6774. D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6775. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6776. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6777. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6778. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6779. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
6780. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
6781. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6782. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6783. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6784. D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6785. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6786. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6787. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6788. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6789. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
6790. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
6791. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6792. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6793. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6794. D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6795. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
6796. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
6797. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
6798. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
6799. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
6800. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
6801. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
6802. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
6803. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
6804. D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
6805. D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
6806. D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
6807. D2F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
6808. D2F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
6809. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
6810. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
6811. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
6812. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
6813. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
6814. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
6815. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
6816. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
6817. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
6818. D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
6819. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
6820. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
6821. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
6822. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
6823. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
6824. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
6825. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
6826. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
6827. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
6828. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
6829. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
6830. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
6831. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
6832. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
6833. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
6834. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
6835. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
6836. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
6837. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
6838. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
6839. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
6840. D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
6841. D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
6842. D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
6843. D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
6844. D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
6845. D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
6846. D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
6847. D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
6848. D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
6849. D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
6850. D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
6851. D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
6852. D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
6853. D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
6854. D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
6855. D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
6856. D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
6857. D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
6858. D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
6859. D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
6860. D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
6861. D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
6862. D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
6863. D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
6864. D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
6865. D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
6866. D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
6867. D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
6868. D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
6869. D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
6870. D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
6871. D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
6872. D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
6873. D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
6874. D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
6875. D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
6876. D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
6877. D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
6878. D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
6879. D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
6880. D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
6881. D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
6882. D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
6883. D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
6884. D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
6885. D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
6886. D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
6887. D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
6888. D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
6889. D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
6890. D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
6891. D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
6892. D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
6893. D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
6894. D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
6895. D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
6896. D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
6897. D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
6898. D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
6899. D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
6900. D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
6901. D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
6902. D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
6903. D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
6904. D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
6905. D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
6906. D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
6907. D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
6908. D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
6909. D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
6910. D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
6911. D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
6912. D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
6913. D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
6914. D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
6915. D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
6916. D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
6917. D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
6918. D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
6919. D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
6920. D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
6921. D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
6922. D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
6923. D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
6924. D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
6925. D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
6926. D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
6927. D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
6928. D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
6929. D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
6930. D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
6931. D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
6932. D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
6933. D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
6934. D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
6935. D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
6936. D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
6937. D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
6938. D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
6939. D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
6940. D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
6941. D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
6942. D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
6943. D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
6944. D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
6945. D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
6946. D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
6947. D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
6948. D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
6949. D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
6950. D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
6951. D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
6952. D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
6953. D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
6954. D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
6955. D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
6956. D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
6957. D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
6958. D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
6959. D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
6960. D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
6961. D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
6962. D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
6963. D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
6964. D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
6965. D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
6966. D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
6967. D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
6968. D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
6969. D2F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
6970. D2F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
6971. D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
6972. D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
6973. D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
6974. D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
6975. D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
6976. D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
6977. D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
6978. D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
6979. D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
6980. D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
6981. D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
6982. D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
6983. D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
6984. D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
6985. D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
6986. D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
6987. D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
6988. D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
6989. D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
6990. D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
6991. D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
6992. D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
6993. D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
6994. D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
6995. D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
6996. D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
6997. D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
6998. D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
6999. D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
7000. D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
7001. D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
7002. D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
7003. D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
7004. D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
7005. D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
7006. D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
7007. D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
7008. D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
7009. D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
7010. D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
7011. D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
7012. D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
7013. D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
7014. D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
7015. D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
7016. D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
7017. D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
7018. D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
7019. D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
7020. D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
7021. D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
7022. D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
7023. D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
7024. D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
7025. D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
7026. D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
7027. D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
7028. D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
7029. D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
7030. D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
7031. D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
7032. D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
7033. D2F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK
7034. D2F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
7035. D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
7036. D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
7037. D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
7038. D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
7039. D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
7040. D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
7041. D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
7042. D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
7043. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
7044. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
7045. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
7046. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
7047. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
7048. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
7049. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
7050. D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
7051. D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
7052. D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
7053. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
7054. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
7055. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
7056. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
7057. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
7058. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
7059. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
7060. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
7061. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
7062. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
7063. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
7064. D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
7065. D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
7066. D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
7067. D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
7068. D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
7069. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
7070. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
7071. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
7072. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
7073. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
7074. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
7075. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
7076. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
7077. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
7078. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
7079. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
7080. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
7081. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
7082. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
7083. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
7084. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
7085. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
7086. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
7087. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
7088. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
7089. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
7090. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
7091. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
7092. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
7093. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
7094. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
7095. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
7096. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
7097. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
7098. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
7099. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
7100. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
7101. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
7102. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
7103. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
7104. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
7105. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
7106. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
7107. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
7108. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
7109. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
7110. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
7111. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
7112. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
7113. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
7114. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
7115. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
7116. D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
7117. D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
7118. D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
7119. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
7120. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
7121. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
7122. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
7123. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
7124. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
7125. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
7126. D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
7127. D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
7128. D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
7129. D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
7130. D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
7131. D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
7132. D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
7133. D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
7134. D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
7135. D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
7136. D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
7137. D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
7138. D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
7139. D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
7140. D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
7141. D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
7142. D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
7143. D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
7144. D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
7145. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
7146. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
7147. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
7148. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
7149. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
7150. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
7151. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
7152. D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
7153. D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
7154. D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
7155. D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
7156. D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
7157. D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
7158. D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
7159. D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
7160. D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
7161. D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
7162. D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
7163. D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
7164. D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
7165. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
7166. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
7167. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
7168. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
7169. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
7170. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
7171. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
7172. D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
7173. D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
7174. D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
7175. D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
7176. D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
7177. D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
7178. D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
7179. D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
7180. D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
7181. D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
7182. D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
7183. D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
7184. D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
7185. D2F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
7186. D2F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
7187. D2F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
7188. D2F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
7189. D2F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
7190. D2F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
7191. D2F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
7192. D2F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
7193. D2F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
7194. D2F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
7195. D2F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
7196. D2F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
7197. D2F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
7198. D2F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
7199. D2F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
7200. D2F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
7201. D2F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
7202. D2F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
7203. D2F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
7204. D2F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
7205. D2F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
7206. D2F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
7207. D2F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
7208. D2F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
7209. D2F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
7210. D2F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
7211. D2F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
7212. D2F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
7213. D2F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
7214. D2F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
7215. D2F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
7216. D2F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
7217. D2F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
7218. D2F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
7219. D2F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
7220. D2F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
7221. D2F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
7222. D2F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
7223. D2F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
7224. D2F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
7225. D2F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
7226. D2F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
7227. D2F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
7228. D2F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
7229. D2F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
7230. D2F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
7231. D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
7232. D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
7233. D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
7234. D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
7235. D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
7236. D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
7237. D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
7238. D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
7239. D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
7240. D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
7241. D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
7242. D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
7243. D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
7244. D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
7245. D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
7246. D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
7247. D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
7248. D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
7249. D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
7250. D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
7251. D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
7252. D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
7253. D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
7254. D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
7255. D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
7256. D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
7257. D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
7258. D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
7259. D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
7260. D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
7261. D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
7262. D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
7263. D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
7264. D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
7265. D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
7266. D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
7267. D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
7268. D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
7269. D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
7270. D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
7271. D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
7272. D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
7273. D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
7274. D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
7275. D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
7276. D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
7277. D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
7278. D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
7279. D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
7280. D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
7281. D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
7282. D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
7283. D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
7284. D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
7285. D2F4_PCIE_LINK_CNTL3__RESERVED_MASK
7286. D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT
7287. D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
7288. D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
7289. D2F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
7290. D2F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
7291. D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
7292. D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
7293. D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
7294. D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
7295. D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
7296. D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
7297. D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
7298. D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
7299. D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
7300. D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
7301. D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
7302. D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
7303. D2F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK
7304. D2F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
7305. D2F4_PCIE_MC_CNTL__MC_ENABLE_MASK
7306. D2F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT
7307. D2F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
7308. D2F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
7309. D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
7310. D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
7311. D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
7312. D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
7313. D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
7314. D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
7315. D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
7316. D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
7317. D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
7318. D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
7319. D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
7320. D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
7321. D2F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
7322. D2F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
7323. D2F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
7324. D2F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
7325. D2F4_PCIE_PORT_DATA__PCIE_DATA_MASK
7326. D2F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT
7327. D2F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK
7328. D2F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
7329. D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
7330. D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
7331. D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
7332. D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
7333. D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
7334. D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
7335. D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
7336. D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
7337. D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
7338. D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
7339. D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
7340. D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
7341. D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
7342. D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
7343. D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
7344. D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
7345. D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
7346. D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
7347. D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
7348. D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
7349. D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
7350. D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
7351. D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
7352. D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
7353. D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
7354. D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
7355. D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
7356. D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
7357. D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
7358. D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
7359. D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
7360. D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
7361. D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
7362. D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
7363. D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
7364. D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
7365. D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
7366. D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
7367. D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
7368. D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
7369. D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
7370. D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
7371. D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
7372. D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
7373. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
7374. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
7375. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
7376. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
7377. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
7378. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
7379. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
7380. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
7381. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
7382. D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
7383. D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
7384. D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
7385. D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
7386. D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
7387. D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
7388. D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
7389. D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
7390. D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
7391. D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
7392. D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
7393. D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
7394. D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
7395. D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
7396. D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
7397. D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
7398. D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
7399. D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
7400. D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
7401. D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
7402. D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
7403. D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
7404. D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
7405. D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
7406. D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
7407. D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
7408. D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
7409. D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
7410. D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
7411. D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
7412. D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
7413. D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
7414. D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
7415. D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
7416. D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
7417. D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
7418. D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
7419. D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
7420. D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
7421. D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
7422. D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
7423. D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
7424. D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
7425. D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
7426. D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
7427. D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
7428. D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
7429. D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
7430. D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
7431. D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
7432. D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
7433. D2F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK
7434. D2F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
7435. D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
7436. D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
7437. D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
7438. D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
7439. D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
7440. D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
7441. D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
7442. D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
7443. D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
7444. D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
7445. D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
7446. D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
7447. D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
7448. D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
7449. D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
7450. D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
7451. D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
7452. D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
7453. D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
7454. D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
7455. D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
7456. D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
7457. D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
7458. D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
7459. D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
7460. D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
7461. D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
7462. D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
7463. D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
7464. D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
7465. D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
7466. D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
7467. D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
7468. D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
7469. D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
7470. D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
7471. D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
7472. D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
7473. D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
7474. D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
7475. D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
7476. D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
7477. D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
7478. D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
7479. D2F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
7480. D2F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
7481. D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
7482. D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
7483. D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
7484. D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
7485. D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
7486. D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
7487. D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
7488. D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
7489. D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
7490. D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
7491. D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
7492. D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
7493. D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
7494. D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
7495. D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
7496. D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
7497. D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
7498. D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
7499. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
7500. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
7501. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
7502. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
7503. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
7504. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
7505. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
7506. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
7507. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
7508. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
7509. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
7510. D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
7511. D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
7512. D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
7513. D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
7514. D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
7515. D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
7516. D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
7517. D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
7518. D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
7519. D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
7520. D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
7521. D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
7522. D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
7523. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
7524. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
7525. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
7526. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
7527. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
7528. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
7529. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
7530. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
7531. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
7532. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
7533. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
7534. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
7535. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
7536. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
7537. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
7538. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
7539. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
7540. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
7541. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
7542. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
7543. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
7544. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
7545. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
7546. D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
7547. D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
7548. D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
7549. D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
7550. D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
7551. D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
7552. D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
7553. D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
7554. D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
7555. D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
7556. D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
7557. D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
7558. D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
7559. D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
7560. D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
7561. D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
7562. D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
7563. D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
7564. D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
7565. D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
7566. D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
7567. D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
7568. D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
7569. D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
7570. D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
7571. D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
7572. D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
7573. D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
7574. D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
7575. D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
7576. D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
7577. D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
7578. D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
7579. D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
7580. D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
7581. D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
7582. D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
7583. D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
7584. D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
7585. D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
7586. D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
7587. D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
7588. D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
7589. D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
7590. D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
7591. D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
7592. D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
7593. D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
7594. D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
7595. D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
7596. D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
7597. D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
7598. D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
7599. D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
7600. D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
7601. D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
7602. D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
7603. D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
7604. D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
7605. D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
7606. D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
7607. D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
7608. D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
7609. D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
7610. D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
7611. D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
7612. D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
7613. D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
7614. D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
7615. D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
7616. D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
7617. D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
7618. D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
7619. D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
7620. D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
7621. D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
7622. D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
7623. D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
7624. D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
7625. D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
7626. D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
7627. D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
7628. D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
7629. D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
7630. D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
7631. D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
7632. D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
7633. D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
7634. D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
7635. D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
7636. D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
7637. D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
7638. D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
7639. D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
7640. D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
7641. D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
7642. D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
7643. D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
7644. D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
7645. D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
7646. D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
7647. D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
7648. D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
7649. D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
7650. D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
7651. D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
7652. D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
7653. D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
7654. D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
7655. D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
7656. D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
7657. D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
7658. D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
7659. D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
7660. D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
7661. D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
7662. D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
7663. D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
7664. D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
7665. D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
7666. D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
7667. D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
7668. D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
7669. D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
7670. D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
7671. D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
7672. D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
7673. D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
7674. D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
7675. D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
7676. D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
7677. D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
7678. D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
7679. D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
7680. D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
7681. D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
7682. D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
7683. D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
7684. D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
7685. D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
7686. D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
7687. D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
7688. D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
7689. D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
7690. D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
7691. D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
7692. D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
7693. D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
7694. D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
7695. D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
7696. D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
7697. D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
7698. D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
7699. D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
7700. D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
7701. D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
7702. D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
7703. D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
7704. D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
7705. D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
7706. D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
7707. D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
7708. D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
7709. D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
7710. D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
7711. D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
7712. D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
7713. D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
7714. D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
7715. D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
7716. D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
7717. D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
7718. D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
7719. D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
7720. D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
7721. D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
7722. D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
7723. D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
7724. D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
7725. D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
7726. D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
7727. D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
7728. D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
7729. D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
7730. D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
7731. D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
7732. D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
7733. D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
7734. D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
7735. D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
7736. D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
7737. D2F4_PMI_CAP_LIST__CAP_ID_MASK
7738. D2F4_PMI_CAP_LIST__CAP_ID__SHIFT
7739. D2F4_PMI_CAP_LIST__NEXT_PTR_MASK
7740. D2F4_PMI_CAP_LIST__NEXT_PTR__SHIFT
7741. D2F4_PMI_CAP__AUX_CURRENT_MASK
7742. D2F4_PMI_CAP__AUX_CURRENT__SHIFT
7743. D2F4_PMI_CAP__D1_SUPPORT_MASK
7744. D2F4_PMI_CAP__D1_SUPPORT__SHIFT
7745. D2F4_PMI_CAP__D2_SUPPORT_MASK
7746. D2F4_PMI_CAP__D2_SUPPORT__SHIFT
7747. D2F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK
7748. D2F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
7749. D2F4_PMI_CAP__PME_CLOCK_MASK
7750. D2F4_PMI_CAP__PME_CLOCK__SHIFT
7751. D2F4_PMI_CAP__PME_SUPPORT_MASK
7752. D2F4_PMI_CAP__PME_SUPPORT__SHIFT
7753. D2F4_PMI_CAP__VERSION_MASK
7754. D2F4_PMI_CAP__VERSION__SHIFT
7755. D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
7756. D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
7757. D2F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
7758. D2F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
7759. D2F4_PMI_STATUS_CNTL__DATA_SCALE_MASK
7760. D2F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
7761. D2F4_PMI_STATUS_CNTL__DATA_SELECT_MASK
7762. D2F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
7763. D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
7764. D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
7765. D2F4_PMI_STATUS_CNTL__PME_EN_MASK
7766. D2F4_PMI_STATUS_CNTL__PME_EN__SHIFT
7767. D2F4_PMI_STATUS_CNTL__PME_STATUS_MASK
7768. D2F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT
7769. D2F4_PMI_STATUS_CNTL__PMI_DATA_MASK
7770. D2F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT
7771. D2F4_PMI_STATUS_CNTL__POWER_STATE_MASK
7772. D2F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT
7773. D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
7774. D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
7775. D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
7776. D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
7777. D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
7778. D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
7779. D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
7780. D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
7781. D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
7782. D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
7783. D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
7784. D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
7785. D2F4_PROG_INTERFACE__PROG_INTERFACE_MASK
7786. D2F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT
7787. D2F4_REVISION_ID__MAJOR_REV_ID_MASK
7788. D2F4_REVISION_ID__MAJOR_REV_ID__SHIFT
7789. D2F4_REVISION_ID__MINOR_REV_ID_MASK
7790. D2F4_REVISION_ID__MINOR_REV_ID__SHIFT
7791. D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
7792. D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
7793. D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
7794. D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
7795. D2F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK
7796. D2F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
7797. D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
7798. D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
7799. D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
7800. D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
7801. D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
7802. D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
7803. D2F4_ROOT_STATUS__PME_PENDING_MASK
7804. D2F4_ROOT_STATUS__PME_PENDING__SHIFT
7805. D2F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK
7806. D2F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
7807. D2F4_ROOT_STATUS__PME_STATUS_MASK
7808. D2F4_ROOT_STATUS__PME_STATUS__SHIFT
7809. D2F4_SECONDARY_STATUS__CAP_LIST_MASK
7810. D2F4_SECONDARY_STATUS__CAP_LIST__SHIFT
7811. D2F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK
7812. D2F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
7813. D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
7814. D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
7815. D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
7816. D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
7817. D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
7818. D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
7819. D2F4_SECONDARY_STATUS__PCI_66_EN_MASK
7820. D2F4_SECONDARY_STATUS__PCI_66_EN__SHIFT
7821. D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
7822. D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
7823. D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
7824. D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
7825. D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
7826. D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
7827. D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
7828. D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
7829. D2F4_SLOT_CAP2__RESERVED_MASK
7830. D2F4_SLOT_CAP2__RESERVED__SHIFT
7831. D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
7832. D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
7833. D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
7834. D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
7835. D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
7836. D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
7837. D2F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK
7838. D2F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
7839. D2F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK
7840. D2F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
7841. D2F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
7842. D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
7843. D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
7844. D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
7845. D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
7846. D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
7847. D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
7848. D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
7849. D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
7850. D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
7851. D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
7852. D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
7853. D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
7854. D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
7855. D2F4_SLOT_CNTL2__RESERVED_MASK
7856. D2F4_SLOT_CNTL2__RESERVED__SHIFT
7857. D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
7858. D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
7859. D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
7860. D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
7861. D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
7862. D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
7863. D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
7864. D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
7865. D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
7866. D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
7867. D2F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
7868. D2F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
7869. D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
7870. D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
7871. D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
7872. D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
7873. D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
7874. D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
7875. D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
7876. D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
7877. D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
7878. D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
7879. D2F4_SLOT_STATUS2__RESERVED_MASK
7880. D2F4_SLOT_STATUS2__RESERVED__SHIFT
7881. D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
7882. D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
7883. D2F4_SLOT_STATUS__COMMAND_COMPLETED_MASK
7884. D2F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
7885. D2F4_SLOT_STATUS__DL_STATE_CHANGED_MASK
7886. D2F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
7887. D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
7888. D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
7889. D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
7890. D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
7891. D2F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK
7892. D2F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
7893. D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
7894. D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
7895. D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
7896. D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
7897. D2F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
7898. D2F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
7899. D2F4_SSID_CAP_LIST__CAP_ID_MASK
7900. D2F4_SSID_CAP_LIST__CAP_ID__SHIFT
7901. D2F4_SSID_CAP_LIST__NEXT_PTR_MASK
7902. D2F4_SSID_CAP_LIST__NEXT_PTR__SHIFT
7903. D2F4_SSID_CAP__SUBSYSTEM_ID_MASK
7904. D2F4_SSID_CAP__SUBSYSTEM_ID__SHIFT
7905. D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
7906. D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
7907. D2F4_STATUS__CAP_LIST_MASK
7908. D2F4_STATUS__CAP_LIST__SHIFT
7909. D2F4_STATUS__DEVSEL_TIMING_MASK
7910. D2F4_STATUS__DEVSEL_TIMING__SHIFT
7911. D2F4_STATUS__FAST_BACK_CAPABLE_MASK
7912. D2F4_STATUS__FAST_BACK_CAPABLE__SHIFT
7913. D2F4_STATUS__INT_STATUS_MASK
7914. D2F4_STATUS__INT_STATUS__SHIFT
7915. D2F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK
7916. D2F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
7917. D2F4_STATUS__PARITY_ERROR_DETECTED_MASK
7918. D2F4_STATUS__PARITY_ERROR_DETECTED__SHIFT
7919. D2F4_STATUS__PCI_66_EN_MASK
7920. D2F4_STATUS__PCI_66_EN__SHIFT
7921. D2F4_STATUS__RECEIVED_MASTER_ABORT_MASK
7922. D2F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT
7923. D2F4_STATUS__RECEIVED_TARGET_ABORT_MASK
7924. D2F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT
7925. D2F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK
7926. D2F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
7927. D2F4_STATUS__SIGNAL_TARGET_ABORT_MASK
7928. D2F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT
7929. D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
7930. D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
7931. D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
7932. D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
7933. D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
7934. D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
7935. D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
7936. D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
7937. D2F4_SUB_CLASS__SUB_CLASS_MASK
7938. D2F4_SUB_CLASS__SUB_CLASS__SHIFT
7939. D2F4_VENDOR_ID__VENDOR_ID_MASK
7940. D2F4_VENDOR_ID__VENDOR_ID__SHIFT
7941. D2F5_BASE_CLASS__BASE_CLASS_MASK
7942. D2F5_BASE_CLASS__BASE_CLASS__SHIFT
7943. D2F5_BIST__BIST_CAP_MASK
7944. D2F5_BIST__BIST_CAP__SHIFT
7945. D2F5_BIST__BIST_COMP_MASK
7946. D2F5_BIST__BIST_COMP__SHIFT
7947. D2F5_BIST__BIST_STRT_MASK
7948. D2F5_BIST__BIST_STRT__SHIFT
7949. D2F5_CACHE_LINE__CACHE_LINE_SIZE_MASK
7950. D2F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
7951. D2F5_CAP_PTR__CAP_PTR_MASK
7952. D2F5_CAP_PTR__CAP_PTR__SHIFT
7953. D2F5_COMMAND__AD_STEPPING_MASK
7954. D2F5_COMMAND__AD_STEPPING__SHIFT
7955. D2F5_COMMAND__BUS_MASTER_EN_MASK
7956. D2F5_COMMAND__BUS_MASTER_EN__SHIFT
7957. D2F5_COMMAND__FAST_B2B_EN_MASK
7958. D2F5_COMMAND__FAST_B2B_EN__SHIFT
7959. D2F5_COMMAND__INT_DIS_MASK
7960. D2F5_COMMAND__INT_DIS__SHIFT
7961. D2F5_COMMAND__IO_ACCESS_EN_MASK
7962. D2F5_COMMAND__IO_ACCESS_EN__SHIFT
7963. D2F5_COMMAND__MEM_ACCESS_EN_MASK
7964. D2F5_COMMAND__MEM_ACCESS_EN__SHIFT
7965. D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
7966. D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
7967. D2F5_COMMAND__PAL_SNOOP_EN_MASK
7968. D2F5_COMMAND__PAL_SNOOP_EN__SHIFT
7969. D2F5_COMMAND__PARITY_ERROR_RESPONSE_MASK
7970. D2F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
7971. D2F5_COMMAND__SERR_EN_MASK
7972. D2F5_COMMAND__SERR_EN__SHIFT
7973. D2F5_COMMAND__SPECIAL_CYCLE_EN_MASK
7974. D2F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT
7975. D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
7976. D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
7977. D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
7978. D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
7979. D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
7980. D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
7981. D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
7982. D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
7983. D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
7984. D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
7985. D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
7986. D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
7987. D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
7988. D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
7989. D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
7990. D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
7991. D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
7992. D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
7993. D2F5_DEVICE_CAP2__LTR_SUPPORTED_MASK
7994. D2F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
7995. D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
7996. D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
7997. D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
7998. D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
7999. D2F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK
8000. D2F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
8001. D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
8002. D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
8003. D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
8004. D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
8005. D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
8006. D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
8007. D2F5_DEVICE_CAP__EXTENDED_TAG_MASK
8008. D2F5_DEVICE_CAP__EXTENDED_TAG__SHIFT
8009. D2F5_DEVICE_CAP__FLR_CAPABLE_MASK
8010. D2F5_DEVICE_CAP__FLR_CAPABLE__SHIFT
8011. D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
8012. D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
8013. D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
8014. D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
8015. D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
8016. D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
8017. D2F5_DEVICE_CAP__PHANTOM_FUNC_MASK
8018. D2F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT
8019. D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
8020. D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
8021. D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
8022. D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
8023. D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
8024. D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
8025. D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
8026. D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
8027. D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
8028. D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
8029. D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
8030. D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
8031. D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
8032. D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
8033. D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
8034. D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
8035. D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
8036. D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
8037. D2F5_DEVICE_CNTL2__LTR_EN_MASK
8038. D2F5_DEVICE_CNTL2__LTR_EN__SHIFT
8039. D2F5_DEVICE_CNTL2__OBFF_EN_MASK
8040. D2F5_DEVICE_CNTL2__OBFF_EN__SHIFT
8041. D2F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
8042. D2F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
8043. D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
8044. D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
8045. D2F5_DEVICE_CNTL__CORR_ERR_EN_MASK
8046. D2F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT
8047. D2F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
8048. D2F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
8049. D2F5_DEVICE_CNTL__FATAL_ERR_EN_MASK
8050. D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
8051. D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
8052. D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
8053. D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
8054. D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
8055. D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
8056. D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
8057. D2F5_DEVICE_CNTL__NO_SNOOP_EN_MASK
8058. D2F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
8059. D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
8060. D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
8061. D2F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK
8062. D2F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
8063. D2F5_DEVICE_CNTL__USR_REPORT_EN_MASK
8064. D2F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT
8065. D2F5_DEVICE_ID__DEVICE_ID_MASK
8066. D2F5_DEVICE_ID__DEVICE_ID__SHIFT
8067. D2F5_DEVICE_STATUS2__RESERVED_MASK
8068. D2F5_DEVICE_STATUS2__RESERVED__SHIFT
8069. D2F5_DEVICE_STATUS__AUX_PWR_MASK
8070. D2F5_DEVICE_STATUS__AUX_PWR__SHIFT
8071. D2F5_DEVICE_STATUS__CORR_ERR_MASK
8072. D2F5_DEVICE_STATUS__CORR_ERR__SHIFT
8073. D2F5_DEVICE_STATUS__FATAL_ERR_MASK
8074. D2F5_DEVICE_STATUS__FATAL_ERR__SHIFT
8075. D2F5_DEVICE_STATUS__NON_FATAL_ERR_MASK
8076. D2F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
8077. D2F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
8078. D2F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
8079. D2F5_DEVICE_STATUS__USR_DETECTED_MASK
8080. D2F5_DEVICE_STATUS__USR_DETECTED__SHIFT
8081. D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
8082. D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
8083. D2F5_HEADER__DEVICE_TYPE_MASK
8084. D2F5_HEADER__DEVICE_TYPE__SHIFT
8085. D2F5_HEADER__HEADER_TYPE_MASK
8086. D2F5_HEADER__HEADER_TYPE__SHIFT
8087. D2F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK
8088. D2F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
8089. D2F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK
8090. D2F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
8091. D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
8092. D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
8093. D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
8094. D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
8095. D2F5_IO_BASE_LIMIT__IO_BASE_MASK
8096. D2F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
8097. D2F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
8098. D2F5_IO_BASE_LIMIT__IO_BASE__SHIFT
8099. D2F5_IO_BASE_LIMIT__IO_LIMIT_MASK
8100. D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
8101. D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
8102. D2F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT
8103. D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
8104. D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
8105. D2F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK
8106. D2F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
8107. D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
8108. D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
8109. D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
8110. D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
8111. D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
8112. D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
8113. D2F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK
8114. D2F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
8115. D2F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
8116. D2F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
8117. D2F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK
8118. D2F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
8119. D2F5_LATENCY__LATENCY_TIMER_MASK
8120. D2F5_LATENCY__LATENCY_TIMER__SHIFT
8121. D2F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
8122. D2F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
8123. D2F5_LINK_CAP2__RESERVED_MASK
8124. D2F5_LINK_CAP2__RESERVED__SHIFT
8125. D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
8126. D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
8127. D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
8128. D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
8129. D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
8130. D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
8131. D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
8132. D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
8133. D2F5_LINK_CAP__L0S_EXIT_LATENCY_MASK
8134. D2F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
8135. D2F5_LINK_CAP__L1_EXIT_LATENCY_MASK
8136. D2F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT
8137. D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
8138. D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
8139. D2F5_LINK_CAP__LINK_SPEED_MASK
8140. D2F5_LINK_CAP__LINK_SPEED__SHIFT
8141. D2F5_LINK_CAP__LINK_WIDTH_MASK
8142. D2F5_LINK_CAP__LINK_WIDTH__SHIFT
8143. D2F5_LINK_CAP__PM_SUPPORT_MASK
8144. D2F5_LINK_CAP__PM_SUPPORT__SHIFT
8145. D2F5_LINK_CAP__PORT_NUMBER_MASK
8146. D2F5_LINK_CAP__PORT_NUMBER__SHIFT
8147. D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
8148. D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
8149. D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
8150. D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
8151. D2F5_LINK_CNTL2__COMPLIANCE_SOS_MASK
8152. D2F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
8153. D2F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK
8154. D2F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
8155. D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
8156. D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
8157. D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
8158. D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
8159. D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
8160. D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
8161. D2F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK
8162. D2F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
8163. D2F5_LINK_CNTL2__XMIT_MARGIN_MASK
8164. D2F5_LINK_CNTL2__XMIT_MARGIN__SHIFT
8165. D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
8166. D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
8167. D2F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK
8168. D2F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
8169. D2F5_LINK_CNTL__EXTENDED_SYNC_MASK
8170. D2F5_LINK_CNTL__EXTENDED_SYNC__SHIFT
8171. D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
8172. D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
8173. D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
8174. D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
8175. D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
8176. D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
8177. D2F5_LINK_CNTL__LINK_DIS_MASK
8178. D2F5_LINK_CNTL__LINK_DIS__SHIFT
8179. D2F5_LINK_CNTL__PM_CONTROL_MASK
8180. D2F5_LINK_CNTL__PM_CONTROL__SHIFT
8181. D2F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK
8182. D2F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
8183. D2F5_LINK_CNTL__RETRAIN_LINK_MASK
8184. D2F5_LINK_CNTL__RETRAIN_LINK__SHIFT
8185. D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
8186. D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
8187. D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
8188. D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
8189. D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
8190. D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
8191. D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
8192. D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
8193. D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
8194. D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
8195. D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
8196. D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
8197. D2F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK
8198. D2F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
8199. D2F5_LINK_STATUS__DL_ACTIVE_MASK
8200. D2F5_LINK_STATUS__DL_ACTIVE__SHIFT
8201. D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
8202. D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
8203. D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
8204. D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
8205. D2F5_LINK_STATUS__LINK_TRAINING_MASK
8206. D2F5_LINK_STATUS__LINK_TRAINING__SHIFT
8207. D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
8208. D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
8209. D2F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK
8210. D2F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
8211. D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
8212. D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
8213. D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
8214. D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
8215. D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
8216. D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
8217. D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
8218. D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
8219. D2F5_MSI_CAP_LIST__CAP_ID_MASK
8220. D2F5_MSI_CAP_LIST__CAP_ID__SHIFT
8221. D2F5_MSI_CAP_LIST__NEXT_PTR_MASK
8222. D2F5_MSI_CAP_LIST__NEXT_PTR__SHIFT
8223. D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
8224. D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
8225. D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
8226. D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
8227. D2F5_MSI_MAP_CAP_LIST__CAP_ID_MASK
8228. D2F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
8229. D2F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
8230. D2F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
8231. D2F5_MSI_MAP_CAP__CAP_TYPE_MASK
8232. D2F5_MSI_MAP_CAP__CAP_TYPE__SHIFT
8233. D2F5_MSI_MAP_CAP__EN_MASK
8234. D2F5_MSI_MAP_CAP__EN__SHIFT
8235. D2F5_MSI_MAP_CAP__FIXD_MASK
8236. D2F5_MSI_MAP_CAP__FIXD__SHIFT
8237. D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
8238. D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
8239. D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
8240. D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
8241. D2F5_MSI_MSG_CNTL__MSI_64BIT_MASK
8242. D2F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT
8243. D2F5_MSI_MSG_CNTL__MSI_EN_MASK
8244. D2F5_MSI_MSG_CNTL__MSI_EN__SHIFT
8245. D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
8246. D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
8247. D2F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
8248. D2F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
8249. D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
8250. D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
8251. D2F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK
8252. D2F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
8253. D2F5_MSI_MSG_DATA__MSI_DATA_MASK
8254. D2F5_MSI_MSG_DATA__MSI_DATA__SHIFT
8255. D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
8256. D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
8257. D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
8258. D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
8259. D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
8260. D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
8261. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
8262. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
8263. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
8264. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
8265. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
8266. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
8267. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
8268. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
8269. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
8270. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
8271. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
8272. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
8273. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
8274. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
8275. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
8276. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
8277. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
8278. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
8279. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
8280. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
8281. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
8282. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
8283. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
8284. D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
8285. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
8286. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
8287. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
8288. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
8289. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
8290. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
8291. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
8292. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
8293. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
8294. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
8295. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
8296. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
8297. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
8298. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
8299. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
8300. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
8301. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
8302. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
8303. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
8304. D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
8305. D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
8306. D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
8307. D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
8308. D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
8309. D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
8310. D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
8311. D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
8312. D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
8313. D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
8314. D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
8315. D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
8316. D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
8317. D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
8318. D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
8319. D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
8320. D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
8321. D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
8322. D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
8323. D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
8324. D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
8325. D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
8326. D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
8327. D2F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK
8328. D2F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
8329. D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
8330. D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
8331. D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
8332. D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
8333. D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
8334. D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
8335. D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
8336. D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
8337. D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
8338. D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
8339. D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
8340. D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
8341. D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
8342. D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
8343. D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
8344. D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
8345. D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
8346. D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
8347. D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
8348. D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
8349. D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
8350. D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
8351. D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
8352. D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
8353. D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
8354. D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
8355. D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
8356. D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
8357. D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
8358. D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
8359. D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
8360. D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
8361. D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
8362. D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
8363. D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
8364. D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
8365. D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
8366. D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
8367. D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
8368. D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
8369. D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
8370. D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
8371. D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
8372. D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
8373. D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
8374. D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
8375. D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
8376. D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
8377. D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
8378. D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
8379. D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
8380. D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
8381. D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
8382. D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
8383. D2F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK
8384. D2F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
8385. D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
8386. D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
8387. D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
8388. D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
8389. D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
8390. D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
8391. D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
8392. D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
8393. D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
8394. D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
8395. D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
8396. D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
8397. D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
8398. D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
8399. D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
8400. D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
8401. D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
8402. D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
8403. D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
8404. D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
8405. D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
8406. D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
8407. D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
8408. D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
8409. D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
8410. D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
8411. D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
8412. D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
8413. D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
8414. D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
8415. D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
8416. D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
8417. D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
8418. D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
8419. D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
8420. D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
8421. D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
8422. D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
8423. D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
8424. D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
8425. D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
8426. D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
8427. D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
8428. D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
8429. D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
8430. D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
8431. D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
8432. D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
8433. D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
8434. D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
8435. D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
8436. D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
8437. D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
8438. D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
8439. D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
8440. D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
8441. D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
8442. D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
8443. D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
8444. D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
8445. D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
8446. D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
8447. D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
8448. D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
8449. D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
8450. D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
8451. D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
8452. D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
8453. D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
8454. D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
8455. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
8456. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
8457. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
8458. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
8459. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
8460. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
8461. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
8462. D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
8463. D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
8464. D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
8465. D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
8466. D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
8467. D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
8468. D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
8469. D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
8470. D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
8471. D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
8472. D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
8473. D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
8474. D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
8475. D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
8476. D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
8477. D2F5_PCIE_CAP_LIST__CAP_ID_MASK
8478. D2F5_PCIE_CAP_LIST__CAP_ID__SHIFT
8479. D2F5_PCIE_CAP_LIST__NEXT_PTR_MASK
8480. D2F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT
8481. D2F5_PCIE_CAP__DEVICE_TYPE_MASK
8482. D2F5_PCIE_CAP__DEVICE_TYPE__SHIFT
8483. D2F5_PCIE_CAP__INT_MESSAGE_NUM_MASK
8484. D2F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
8485. D2F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK
8486. D2F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
8487. D2F5_PCIE_CAP__VERSION_MASK
8488. D2F5_PCIE_CAP__VERSION__SHIFT
8489. D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
8490. D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
8491. D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
8492. D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
8493. D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
8494. D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
8495. D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
8496. D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
8497. D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
8498. D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
8499. D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
8500. D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
8501. D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
8502. D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
8503. D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
8504. D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
8505. D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
8506. D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
8507. D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
8508. D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
8509. D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
8510. D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
8511. D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
8512. D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
8513. D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
8514. D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
8515. D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
8516. D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
8517. D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
8518. D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
8519. D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
8520. D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
8521. D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
8522. D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
8523. D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
8524. D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
8525. D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
8526. D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
8527. D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
8528. D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
8529. D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
8530. D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
8531. D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
8532. D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
8533. D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
8534. D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
8535. D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
8536. D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
8537. D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
8538. D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
8539. D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
8540. D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
8541. D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
8542. D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
8543. D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
8544. D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
8545. D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
8546. D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
8547. D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
8548. D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
8549. D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
8550. D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
8551. D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
8552. D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
8553. D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
8554. D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
8555. D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
8556. D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
8557. D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
8558. D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
8559. D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
8560. D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
8561. D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
8562. D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
8563. D2F5_PCIE_FC_CPL__CPLD_CREDITS_MASK
8564. D2F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
8565. D2F5_PCIE_FC_CPL__CPLH_CREDITS_MASK
8566. D2F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
8567. D2F5_PCIE_FC_NP__NPD_CREDITS_MASK
8568. D2F5_PCIE_FC_NP__NPD_CREDITS__SHIFT
8569. D2F5_PCIE_FC_NP__NPH_CREDITS_MASK
8570. D2F5_PCIE_FC_NP__NPH_CREDITS__SHIFT
8571. D2F5_PCIE_FC_P__PD_CREDITS_MASK
8572. D2F5_PCIE_FC_P__PD_CREDITS__SHIFT
8573. D2F5_PCIE_FC_P__PH_CREDITS_MASK
8574. D2F5_PCIE_FC_P__PH_CREDITS__SHIFT
8575. D2F5_PCIE_HDR_LOG0__TLP_HDR_MASK
8576. D2F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT
8577. D2F5_PCIE_HDR_LOG1__TLP_HDR_MASK
8578. D2F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT
8579. D2F5_PCIE_HDR_LOG2__TLP_HDR_MASK
8580. D2F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT
8581. D2F5_PCIE_HDR_LOG3__TLP_HDR_MASK
8582. D2F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT
8583. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8584. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8585. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8586. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8587. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
8588. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
8589. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8590. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8591. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8592. D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8593. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8594. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8595. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8596. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8597. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
8598. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
8599. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8600. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8601. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8602. D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8603. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8604. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8605. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8606. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8607. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
8608. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
8609. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8610. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8611. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8612. D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8613. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8614. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8615. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8616. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8617. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
8618. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
8619. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8620. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8621. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8622. D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8623. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8624. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8625. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8626. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8627. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
8628. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
8629. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8630. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8631. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8632. D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8633. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8634. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8635. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8636. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8637. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
8638. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
8639. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8640. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8641. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8642. D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8643. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8644. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8645. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8646. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8647. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
8648. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
8649. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8650. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8651. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8652. D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8653. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8654. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8655. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8656. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8657. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
8658. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
8659. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8660. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8661. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8662. D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8663. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8664. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8665. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8666. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8667. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
8668. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
8669. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8670. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8671. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8672. D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8673. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8674. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8675. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8676. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8677. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
8678. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
8679. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8680. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8681. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8682. D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8683. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8684. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8685. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8686. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8687. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
8688. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
8689. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8690. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8691. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8692. D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8693. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8694. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8695. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8696. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8697. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
8698. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
8699. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8700. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8701. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8702. D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8703. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8704. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8705. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8706. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8707. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
8708. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
8709. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8710. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8711. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8712. D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8713. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8714. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8715. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8716. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8717. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
8718. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
8719. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8720. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8721. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8722. D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8723. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8724. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8725. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8726. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8727. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
8728. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
8729. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8730. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8731. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8732. D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8733. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
8734. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
8735. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
8736. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
8737. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
8738. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
8739. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
8740. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
8741. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
8742. D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
8743. D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
8744. D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
8745. D2F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
8746. D2F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
8747. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
8748. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
8749. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
8750. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
8751. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
8752. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
8753. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
8754. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
8755. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
8756. D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
8757. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
8758. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
8759. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
8760. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
8761. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
8762. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
8763. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
8764. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
8765. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
8766. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
8767. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
8768. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
8769. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
8770. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
8771. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
8772. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
8773. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
8774. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
8775. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
8776. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
8777. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
8778. D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
8779. D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
8780. D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
8781. D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
8782. D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
8783. D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
8784. D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
8785. D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
8786. D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
8787. D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
8788. D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
8789. D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
8790. D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
8791. D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
8792. D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
8793. D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
8794. D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
8795. D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
8796. D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
8797. D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
8798. D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
8799. D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
8800. D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
8801. D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
8802. D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
8803. D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
8804. D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
8805. D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
8806. D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
8807. D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
8808. D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
8809. D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
8810. D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
8811. D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
8812. D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
8813. D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
8814. D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
8815. D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
8816. D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
8817. D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
8818. D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
8819. D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
8820. D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
8821. D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
8822. D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
8823. D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
8824. D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
8825. D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
8826. D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
8827. D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
8828. D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
8829. D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
8830. D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
8831. D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
8832. D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
8833. D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
8834. D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
8835. D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
8836. D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
8837. D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
8838. D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
8839. D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
8840. D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
8841. D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
8842. D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
8843. D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
8844. D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
8845. D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
8846. D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
8847. D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
8848. D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
8849. D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
8850. D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
8851. D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
8852. D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
8853. D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
8854. D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
8855. D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
8856. D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
8857. D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
8858. D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
8859. D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
8860. D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
8861. D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
8862. D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
8863. D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
8864. D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
8865. D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
8866. D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
8867. D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
8868. D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
8869. D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
8870. D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
8871. D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
8872. D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
8873. D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
8874. D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
8875. D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
8876. D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
8877. D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
8878. D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
8879. D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
8880. D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
8881. D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
8882. D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
8883. D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
8884. D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
8885. D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
8886. D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
8887. D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
8888. D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
8889. D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
8890. D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
8891. D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
8892. D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
8893. D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
8894. D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
8895. D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
8896. D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
8897. D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
8898. D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
8899. D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
8900. D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
8901. D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
8902. D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
8903. D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
8904. D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
8905. D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
8906. D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
8907. D2F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
8908. D2F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
8909. D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
8910. D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
8911. D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
8912. D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
8913. D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
8914. D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
8915. D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
8916. D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
8917. D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
8918. D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
8919. D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
8920. D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
8921. D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
8922. D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
8923. D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
8924. D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
8925. D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
8926. D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
8927. D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
8928. D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
8929. D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
8930. D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
8931. D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
8932. D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
8933. D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
8934. D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
8935. D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
8936. D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
8937. D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
8938. D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
8939. D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
8940. D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
8941. D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
8942. D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
8943. D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
8944. D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
8945. D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
8946. D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
8947. D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
8948. D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
8949. D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
8950. D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
8951. D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
8952. D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
8953. D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
8954. D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
8955. D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
8956. D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
8957. D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
8958. D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
8959. D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
8960. D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
8961. D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
8962. D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
8963. D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
8964. D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
8965. D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
8966. D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
8967. D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
8968. D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
8969. D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
8970. D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
8971. D2F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK
8972. D2F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
8973. D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
8974. D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
8975. D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
8976. D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
8977. D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
8978. D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
8979. D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
8980. D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
8981. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
8982. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
8983. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
8984. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
8985. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
8986. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
8987. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
8988. D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
8989. D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
8990. D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
8991. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
8992. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
8993. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
8994. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
8995. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
8996. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
8997. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
8998. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
8999. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
9000. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
9001. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
9002. D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
9003. D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
9004. D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
9005. D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
9006. D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
9007. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
9008. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
9009. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
9010. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
9011. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
9012. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
9013. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
9014. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
9015. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
9016. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
9017. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
9018. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
9019. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
9020. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
9021. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
9022. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
9023. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
9024. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
9025. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
9026. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
9027. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
9028. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
9029. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
9030. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
9031. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
9032. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
9033. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
9034. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
9035. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
9036. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
9037. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
9038. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
9039. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
9040. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
9041. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
9042. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
9043. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
9044. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
9045. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
9046. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
9047. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
9048. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
9049. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
9050. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
9051. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
9052. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
9053. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
9054. D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
9055. D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
9056. D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
9057. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
9058. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
9059. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
9060. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
9061. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
9062. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
9063. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
9064. D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
9065. D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
9066. D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
9067. D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
9068. D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
9069. D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
9070. D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
9071. D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
9072. D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
9073. D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
9074. D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
9075. D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
9076. D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
9077. D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
9078. D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
9079. D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
9080. D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
9081. D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
9082. D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
9083. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
9084. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
9085. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
9086. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
9087. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
9088. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
9089. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
9090. D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
9091. D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
9092. D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
9093. D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
9094. D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
9095. D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
9096. D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
9097. D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
9098. D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
9099. D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
9100. D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
9101. D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
9102. D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
9103. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
9104. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
9105. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
9106. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
9107. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
9108. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
9109. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
9110. D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
9111. D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
9112. D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
9113. D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
9114. D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
9115. D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
9116. D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
9117. D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
9118. D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
9119. D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
9120. D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
9121. D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
9122. D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
9123. D2F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
9124. D2F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
9125. D2F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
9126. D2F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
9127. D2F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
9128. D2F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
9129. D2F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
9130. D2F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
9131. D2F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
9132. D2F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
9133. D2F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
9134. D2F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
9135. D2F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
9136. D2F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
9137. D2F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
9138. D2F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
9139. D2F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
9140. D2F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
9141. D2F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
9142. D2F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
9143. D2F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
9144. D2F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
9145. D2F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
9146. D2F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
9147. D2F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
9148. D2F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
9149. D2F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
9150. D2F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
9151. D2F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
9152. D2F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
9153. D2F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
9154. D2F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
9155. D2F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
9156. D2F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
9157. D2F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
9158. D2F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
9159. D2F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
9160. D2F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
9161. D2F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
9162. D2F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
9163. D2F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
9164. D2F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
9165. D2F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
9166. D2F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
9167. D2F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
9168. D2F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
9169. D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
9170. D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
9171. D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
9172. D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
9173. D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
9174. D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
9175. D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
9176. D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
9177. D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
9178. D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
9179. D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
9180. D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
9181. D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
9182. D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
9183. D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
9184. D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
9185. D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
9186. D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
9187. D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
9188. D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
9189. D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
9190. D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
9191. D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
9192. D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
9193. D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
9194. D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
9195. D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
9196. D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
9197. D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
9198. D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
9199. D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
9200. D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
9201. D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
9202. D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
9203. D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
9204. D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
9205. D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
9206. D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
9207. D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
9208. D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
9209. D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
9210. D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
9211. D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
9212. D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
9213. D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
9214. D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
9215. D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
9216. D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
9217. D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
9218. D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
9219. D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
9220. D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
9221. D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
9222. D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
9223. D2F5_PCIE_LINK_CNTL3__RESERVED_MASK
9224. D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT
9225. D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
9226. D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
9227. D2F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
9228. D2F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
9229. D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
9230. D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
9231. D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
9232. D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
9233. D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
9234. D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
9235. D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
9236. D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
9237. D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
9238. D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
9239. D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
9240. D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
9241. D2F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK
9242. D2F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
9243. D2F5_PCIE_MC_CNTL__MC_ENABLE_MASK
9244. D2F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT
9245. D2F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
9246. D2F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
9247. D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
9248. D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
9249. D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
9250. D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
9251. D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
9252. D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
9253. D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
9254. D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
9255. D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
9256. D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
9257. D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
9258. D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
9259. D2F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
9260. D2F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
9261. D2F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
9262. D2F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
9263. D2F5_PCIE_PORT_DATA__PCIE_DATA_MASK
9264. D2F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT
9265. D2F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK
9266. D2F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
9267. D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
9268. D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
9269. D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
9270. D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
9271. D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
9272. D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
9273. D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
9274. D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
9275. D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
9276. D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
9277. D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
9278. D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
9279. D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
9280. D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
9281. D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
9282. D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
9283. D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
9284. D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
9285. D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
9286. D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
9287. D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
9288. D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
9289. D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
9290. D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
9291. D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
9292. D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
9293. D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
9294. D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
9295. D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
9296. D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
9297. D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
9298. D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
9299. D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
9300. D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
9301. D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
9302. D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
9303. D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
9304. D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
9305. D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
9306. D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
9307. D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
9308. D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
9309. D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
9310. D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
9311. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
9312. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
9313. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
9314. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
9315. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
9316. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
9317. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
9318. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
9319. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
9320. D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
9321. D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
9322. D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
9323. D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
9324. D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
9325. D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
9326. D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
9327. D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
9328. D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
9329. D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
9330. D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
9331. D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
9332. D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
9333. D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
9334. D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
9335. D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
9336. D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
9337. D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
9338. D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
9339. D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
9340. D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
9341. D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
9342. D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
9343. D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
9344. D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
9345. D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
9346. D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
9347. D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
9348. D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
9349. D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
9350. D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
9351. D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
9352. D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
9353. D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
9354. D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
9355. D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
9356. D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
9357. D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
9358. D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
9359. D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
9360. D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
9361. D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
9362. D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
9363. D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
9364. D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
9365. D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
9366. D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
9367. D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
9368. D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
9369. D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
9370. D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
9371. D2F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK
9372. D2F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
9373. D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
9374. D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
9375. D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
9376. D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
9377. D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
9378. D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
9379. D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
9380. D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
9381. D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
9382. D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
9383. D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
9384. D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
9385. D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
9386. D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
9387. D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
9388. D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
9389. D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
9390. D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
9391. D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
9392. D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
9393. D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
9394. D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
9395. D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
9396. D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
9397. D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
9398. D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
9399. D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
9400. D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
9401. D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
9402. D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
9403. D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
9404. D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
9405. D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
9406. D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
9407. D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
9408. D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
9409. D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
9410. D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
9411. D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
9412. D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
9413. D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
9414. D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
9415. D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
9416. D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
9417. D2F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
9418. D2F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
9419. D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
9420. D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
9421. D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
9422. D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
9423. D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
9424. D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
9425. D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
9426. D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
9427. D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
9428. D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
9429. D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
9430. D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
9431. D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
9432. D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
9433. D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
9434. D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
9435. D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
9436. D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
9437. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
9438. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
9439. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
9440. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
9441. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
9442. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
9443. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
9444. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
9445. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
9446. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
9447. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
9448. D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
9449. D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
9450. D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
9451. D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
9452. D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
9453. D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
9454. D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
9455. D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
9456. D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
9457. D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
9458. D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
9459. D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
9460. D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
9461. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
9462. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
9463. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
9464. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
9465. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
9466. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
9467. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
9468. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
9469. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
9470. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
9471. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
9472. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
9473. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
9474. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
9475. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
9476. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
9477. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
9478. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
9479. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
9480. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
9481. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
9482. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
9483. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
9484. D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
9485. D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
9486. D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
9487. D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
9488. D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
9489. D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
9490. D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
9491. D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
9492. D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
9493. D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
9494. D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
9495. D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
9496. D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
9497. D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
9498. D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
9499. D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
9500. D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
9501. D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
9502. D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
9503. D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
9504. D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
9505. D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
9506. D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
9507. D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
9508. D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
9509. D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
9510. D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
9511. D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
9512. D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
9513. D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
9514. D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
9515. D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
9516. D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
9517. D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
9518. D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
9519. D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
9520. D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
9521. D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
9522. D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
9523. D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
9524. D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
9525. D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
9526. D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
9527. D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
9528. D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
9529. D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
9530. D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
9531. D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
9532. D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
9533. D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
9534. D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
9535. D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
9536. D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
9537. D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
9538. D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
9539. D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
9540. D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
9541. D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
9542. D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
9543. D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
9544. D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
9545. D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
9546. D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
9547. D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
9548. D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
9549. D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
9550. D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
9551. D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
9552. D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
9553. D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
9554. D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
9555. D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
9556. D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
9557. D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
9558. D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
9559. D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
9560. D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
9561. D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
9562. D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
9563. D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
9564. D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
9565. D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
9566. D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
9567. D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
9568. D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
9569. D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
9570. D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
9571. D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
9572. D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
9573. D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
9574. D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
9575. D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
9576. D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
9577. D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
9578. D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
9579. D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
9580. D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
9581. D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
9582. D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
9583. D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
9584. D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
9585. D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
9586. D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
9587. D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
9588. D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
9589. D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
9590. D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
9591. D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
9592. D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
9593. D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
9594. D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
9595. D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
9596. D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
9597. D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
9598. D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
9599. D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
9600. D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
9601. D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
9602. D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
9603. D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
9604. D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
9605. D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
9606. D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
9607. D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
9608. D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
9609. D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
9610. D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
9611. D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
9612. D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
9613. D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
9614. D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
9615. D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
9616. D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
9617. D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
9618. D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
9619. D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
9620. D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
9621. D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
9622. D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
9623. D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
9624. D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
9625. D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
9626. D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
9627. D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
9628. D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
9629. D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
9630. D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
9631. D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
9632. D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
9633. D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
9634. D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
9635. D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
9636. D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
9637. D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
9638. D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
9639. D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
9640. D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
9641. D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
9642. D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
9643. D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
9644. D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
9645. D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
9646. D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
9647. D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
9648. D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
9649. D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
9650. D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
9651. D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
9652. D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
9653. D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
9654. D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
9655. D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
9656. D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
9657. D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
9658. D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
9659. D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
9660. D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
9661. D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
9662. D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
9663. D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
9664. D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
9665. D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
9666. D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
9667. D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
9668. D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
9669. D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
9670. D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
9671. D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
9672. D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
9673. D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
9674. D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
9675. D2F5_PMI_CAP_LIST__CAP_ID_MASK
9676. D2F5_PMI_CAP_LIST__CAP_ID__SHIFT
9677. D2F5_PMI_CAP_LIST__NEXT_PTR_MASK
9678. D2F5_PMI_CAP_LIST__NEXT_PTR__SHIFT
9679. D2F5_PMI_CAP__AUX_CURRENT_MASK
9680. D2F5_PMI_CAP__AUX_CURRENT__SHIFT
9681. D2F5_PMI_CAP__D1_SUPPORT_MASK
9682. D2F5_PMI_CAP__D1_SUPPORT__SHIFT
9683. D2F5_PMI_CAP__D2_SUPPORT_MASK
9684. D2F5_PMI_CAP__D2_SUPPORT__SHIFT
9685. D2F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK
9686. D2F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
9687. D2F5_PMI_CAP__PME_CLOCK_MASK
9688. D2F5_PMI_CAP__PME_CLOCK__SHIFT
9689. D2F5_PMI_CAP__PME_SUPPORT_MASK
9690. D2F5_PMI_CAP__PME_SUPPORT__SHIFT
9691. D2F5_PMI_CAP__VERSION_MASK
9692. D2F5_PMI_CAP__VERSION__SHIFT
9693. D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
9694. D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
9695. D2F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
9696. D2F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
9697. D2F5_PMI_STATUS_CNTL__DATA_SCALE_MASK
9698. D2F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
9699. D2F5_PMI_STATUS_CNTL__DATA_SELECT_MASK
9700. D2F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
9701. D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
9702. D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
9703. D2F5_PMI_STATUS_CNTL__PME_EN_MASK
9704. D2F5_PMI_STATUS_CNTL__PME_EN__SHIFT
9705. D2F5_PMI_STATUS_CNTL__PME_STATUS_MASK
9706. D2F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT
9707. D2F5_PMI_STATUS_CNTL__PMI_DATA_MASK
9708. D2F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT
9709. D2F5_PMI_STATUS_CNTL__POWER_STATE_MASK
9710. D2F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT
9711. D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
9712. D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
9713. D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
9714. D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
9715. D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
9716. D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
9717. D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
9718. D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
9719. D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
9720. D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
9721. D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
9722. D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
9723. D2F5_PROG_INTERFACE__PROG_INTERFACE_MASK
9724. D2F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT
9725. D2F5_REVISION_ID__MAJOR_REV_ID_MASK
9726. D2F5_REVISION_ID__MAJOR_REV_ID__SHIFT
9727. D2F5_REVISION_ID__MINOR_REV_ID_MASK
9728. D2F5_REVISION_ID__MINOR_REV_ID__SHIFT
9729. D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
9730. D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
9731. D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
9732. D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
9733. D2F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK
9734. D2F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
9735. D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
9736. D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
9737. D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
9738. D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
9739. D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
9740. D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
9741. D2F5_ROOT_STATUS__PME_PENDING_MASK
9742. D2F5_ROOT_STATUS__PME_PENDING__SHIFT
9743. D2F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK
9744. D2F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
9745. D2F5_ROOT_STATUS__PME_STATUS_MASK
9746. D2F5_ROOT_STATUS__PME_STATUS__SHIFT
9747. D2F5_SECONDARY_STATUS__CAP_LIST_MASK
9748. D2F5_SECONDARY_STATUS__CAP_LIST__SHIFT
9749. D2F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK
9750. D2F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
9751. D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
9752. D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
9753. D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
9754. D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
9755. D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
9756. D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
9757. D2F5_SECONDARY_STATUS__PCI_66_EN_MASK
9758. D2F5_SECONDARY_STATUS__PCI_66_EN__SHIFT
9759. D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
9760. D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
9761. D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
9762. D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
9763. D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
9764. D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
9765. D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
9766. D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
9767. D2F5_SLOT_CAP2__RESERVED_MASK
9768. D2F5_SLOT_CAP2__RESERVED__SHIFT
9769. D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
9770. D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
9771. D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
9772. D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
9773. D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
9774. D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
9775. D2F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK
9776. D2F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
9777. D2F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK
9778. D2F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
9779. D2F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
9780. D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
9781. D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
9782. D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
9783. D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
9784. D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
9785. D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
9786. D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
9787. D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
9788. D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
9789. D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
9790. D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
9791. D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
9792. D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
9793. D2F5_SLOT_CNTL2__RESERVED_MASK
9794. D2F5_SLOT_CNTL2__RESERVED__SHIFT
9795. D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
9796. D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
9797. D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
9798. D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
9799. D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
9800. D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
9801. D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
9802. D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
9803. D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
9804. D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
9805. D2F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
9806. D2F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
9807. D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
9808. D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
9809. D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
9810. D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
9811. D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
9812. D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
9813. D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
9814. D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
9815. D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
9816. D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
9817. D2F5_SLOT_STATUS2__RESERVED_MASK
9818. D2F5_SLOT_STATUS2__RESERVED__SHIFT
9819. D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
9820. D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
9821. D2F5_SLOT_STATUS__COMMAND_COMPLETED_MASK
9822. D2F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
9823. D2F5_SLOT_STATUS__DL_STATE_CHANGED_MASK
9824. D2F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
9825. D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
9826. D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
9827. D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
9828. D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
9829. D2F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK
9830. D2F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
9831. D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
9832. D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
9833. D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
9834. D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
9835. D2F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
9836. D2F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
9837. D2F5_SSID_CAP_LIST__CAP_ID_MASK
9838. D2F5_SSID_CAP_LIST__CAP_ID__SHIFT
9839. D2F5_SSID_CAP_LIST__NEXT_PTR_MASK
9840. D2F5_SSID_CAP_LIST__NEXT_PTR__SHIFT
9841. D2F5_SSID_CAP__SUBSYSTEM_ID_MASK
9842. D2F5_SSID_CAP__SUBSYSTEM_ID__SHIFT
9843. D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
9844. D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
9845. D2F5_STATUS__CAP_LIST_MASK
9846. D2F5_STATUS__CAP_LIST__SHIFT
9847. D2F5_STATUS__DEVSEL_TIMING_MASK
9848. D2F5_STATUS__DEVSEL_TIMING__SHIFT
9849. D2F5_STATUS__FAST_BACK_CAPABLE_MASK
9850. D2F5_STATUS__FAST_BACK_CAPABLE__SHIFT
9851. D2F5_STATUS__INT_STATUS_MASK
9852. D2F5_STATUS__INT_STATUS__SHIFT
9853. D2F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK
9854. D2F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
9855. D2F5_STATUS__PARITY_ERROR_DETECTED_MASK
9856. D2F5_STATUS__PARITY_ERROR_DETECTED__SHIFT
9857. D2F5_STATUS__PCI_66_EN_MASK
9858. D2F5_STATUS__PCI_66_EN__SHIFT
9859. D2F5_STATUS__RECEIVED_MASTER_ABORT_MASK
9860. D2F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT
9861. D2F5_STATUS__RECEIVED_TARGET_ABORT_MASK
9862. D2F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT
9863. D2F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK
9864. D2F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
9865. D2F5_STATUS__SIGNAL_TARGET_ABORT_MASK
9866. D2F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT
9867. D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
9868. D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
9869. D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
9870. D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
9871. D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
9872. D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
9873. D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
9874. D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
9875. D2F5_SUB_CLASS__SUB_CLASS_MASK
9876. D2F5_SUB_CLASS__SUB_CLASS__SHIFT
9877. D2F5_VENDOR_ID__VENDOR_ID_MASK
9878. D2F5_VENDOR_ID__VENDOR_ID__SHIFT
9879. D2FIFOCTR
9880. D2FIFOSEL
9881. D2GRPH_INTERRUPT_CONTROL
9882. D2GRPH_INTERRUPT_STATUS
9883. D2GRPH_PRIMARY_SURFACE_ADDRESS
9884. D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
9885. D2GRPH_SECONDARY_SURFACE_ADDRESS
9886. D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
9887. D2MODE_PRIORITY_A_CNT
9888. D2MODE_PRIORITY_B_CNT
9889. D2MODE_VBLANK_INT_MASK
9890. D2MODE_VBLANK_STATUS
9891. D2MODE_VLINE_INT_MASK
9892. D2MODE_VLINE_STATUS
9893. D2NET_GPIO_BLUE_LED_BLINK_CTRL
9894. D2NET_GPIO_BLUE_LED_OFF
9895. D2NET_GPIO_RED_LED
9896. D2SRAM1_CK
9897. D2SRAM2_CK
9898. D2SRAM3_CK
9899. D2S_PRE
9900. D2S_PREP
9901. D2S_ZERO
9902. D2VGA_CONTROL
9903. D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK
9904. D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT
9905. D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK
9906. D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT
9907. D2VGA_CONTROL__D2VGA_ROTATE_MASK
9908. D2VGA_CONTROL__D2VGA_ROTATE__SHIFT
9909. D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK
9910. D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT
9911. D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK
9912. D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT
9913. D2W_CNTRL
9914. D2W_DPHYCONTRX
9915. D2_2_MUTE_CH1_ON_CTL_PRE_MASK
9916. D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT
9917. D2_2_MUTE_CH1_ON_CTL_PRE_SFT
9918. D2_2_MUTE_CH2_ON_CTL_PRE_MASK
9919. D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT
9920. D2_2_MUTE_CH2_ON_CTL_PRE_SFT
9921. D2_7XX_KBR4
9922. D2_MARK
9923. D2_MASK
9924. D2_NAF2_MARK
9925. D2bv
9926. D2bvIP
9927. D3
9928. D30_MARK
9929. D31_MARK
9930. D32_AD0_DR0_MARK
9931. D33_AD1_DR1_MARK
9932. D34_AD2_DR2_MARK
9933. D35_AD3_DR3_MARK
9934. D36_AD4_DR4_MARK
9935. D37_AD5_DR5_MARK
9936. D38_AD6_DG0_MARK
9937. D39_AD7_DG1_MARK
9938. D3F1_BASE_CLASS__BASE_CLASS_MASK
9939. D3F1_BASE_CLASS__BASE_CLASS__SHIFT
9940. D3F1_BIST__BIST_CAP_MASK
9941. D3F1_BIST__BIST_CAP__SHIFT
9942. D3F1_BIST__BIST_COMP_MASK
9943. D3F1_BIST__BIST_COMP__SHIFT
9944. D3F1_BIST__BIST_STRT_MASK
9945. D3F1_BIST__BIST_STRT__SHIFT
9946. D3F1_CACHE_LINE__CACHE_LINE_SIZE_MASK
9947. D3F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
9948. D3F1_CAP_PTR__CAP_PTR_MASK
9949. D3F1_CAP_PTR__CAP_PTR__SHIFT
9950. D3F1_COMMAND__AD_STEPPING_MASK
9951. D3F1_COMMAND__AD_STEPPING__SHIFT
9952. D3F1_COMMAND__BUS_MASTER_EN_MASK
9953. D3F1_COMMAND__BUS_MASTER_EN__SHIFT
9954. D3F1_COMMAND__FAST_B2B_EN_MASK
9955. D3F1_COMMAND__FAST_B2B_EN__SHIFT
9956. D3F1_COMMAND__INT_DIS_MASK
9957. D3F1_COMMAND__INT_DIS__SHIFT
9958. D3F1_COMMAND__IO_ACCESS_EN_MASK
9959. D3F1_COMMAND__IO_ACCESS_EN__SHIFT
9960. D3F1_COMMAND__MEM_ACCESS_EN_MASK
9961. D3F1_COMMAND__MEM_ACCESS_EN__SHIFT
9962. D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
9963. D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
9964. D3F1_COMMAND__PAL_SNOOP_EN_MASK
9965. D3F1_COMMAND__PAL_SNOOP_EN__SHIFT
9966. D3F1_COMMAND__PARITY_ERROR_RESPONSE_MASK
9967. D3F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
9968. D3F1_COMMAND__SERR_EN_MASK
9969. D3F1_COMMAND__SERR_EN__SHIFT
9970. D3F1_COMMAND__SPECIAL_CYCLE_EN_MASK
9971. D3F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
9972. D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
9973. D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
9974. D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
9975. D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
9976. D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
9977. D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
9978. D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
9979. D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
9980. D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
9981. D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
9982. D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
9983. D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
9984. D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
9985. D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
9986. D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
9987. D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
9988. D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
9989. D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
9990. D3F1_DEVICE_CAP2__LTR_SUPPORTED_MASK
9991. D3F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
9992. D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
9993. D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
9994. D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
9995. D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
9996. D3F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
9997. D3F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
9998. D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
9999. D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
10000. D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
10001. D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
10002. D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
10003. D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
10004. D3F1_DEVICE_CAP__EXTENDED_TAG_MASK
10005. D3F1_DEVICE_CAP__EXTENDED_TAG__SHIFT
10006. D3F1_DEVICE_CAP__FLR_CAPABLE_MASK
10007. D3F1_DEVICE_CAP__FLR_CAPABLE__SHIFT
10008. D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
10009. D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
10010. D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
10011. D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
10012. D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
10013. D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
10014. D3F1_DEVICE_CAP__PHANTOM_FUNC_MASK
10015. D3F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
10016. D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
10017. D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
10018. D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
10019. D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
10020. D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
10021. D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
10022. D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
10023. D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
10024. D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
10025. D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
10026. D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
10027. D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
10028. D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
10029. D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
10030. D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
10031. D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
10032. D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
10033. D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
10034. D3F1_DEVICE_CNTL2__LTR_EN_MASK
10035. D3F1_DEVICE_CNTL2__LTR_EN__SHIFT
10036. D3F1_DEVICE_CNTL2__OBFF_EN_MASK
10037. D3F1_DEVICE_CNTL2__OBFF_EN__SHIFT
10038. D3F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
10039. D3F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
10040. D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
10041. D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
10042. D3F1_DEVICE_CNTL__CORR_ERR_EN_MASK
10043. D3F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
10044. D3F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
10045. D3F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
10046. D3F1_DEVICE_CNTL__FATAL_ERR_EN_MASK
10047. D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
10048. D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
10049. D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
10050. D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
10051. D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
10052. D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
10053. D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
10054. D3F1_DEVICE_CNTL__NO_SNOOP_EN_MASK
10055. D3F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
10056. D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
10057. D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
10058. D3F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
10059. D3F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
10060. D3F1_DEVICE_CNTL__USR_REPORT_EN_MASK
10061. D3F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
10062. D3F1_DEVICE_ID__DEVICE_ID_MASK
10063. D3F1_DEVICE_ID__DEVICE_ID__SHIFT
10064. D3F1_DEVICE_STATUS2__RESERVED_MASK
10065. D3F1_DEVICE_STATUS2__RESERVED__SHIFT
10066. D3F1_DEVICE_STATUS__AUX_PWR_MASK
10067. D3F1_DEVICE_STATUS__AUX_PWR__SHIFT
10068. D3F1_DEVICE_STATUS__CORR_ERR_MASK
10069. D3F1_DEVICE_STATUS__CORR_ERR__SHIFT
10070. D3F1_DEVICE_STATUS__FATAL_ERR_MASK
10071. D3F1_DEVICE_STATUS__FATAL_ERR__SHIFT
10072. D3F1_DEVICE_STATUS__NON_FATAL_ERR_MASK
10073. D3F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
10074. D3F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
10075. D3F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
10076. D3F1_DEVICE_STATUS__USR_DETECTED_MASK
10077. D3F1_DEVICE_STATUS__USR_DETECTED__SHIFT
10078. D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
10079. D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
10080. D3F1_HEADER__DEVICE_TYPE_MASK
10081. D3F1_HEADER__DEVICE_TYPE__SHIFT
10082. D3F1_HEADER__HEADER_TYPE_MASK
10083. D3F1_HEADER__HEADER_TYPE__SHIFT
10084. D3F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
10085. D3F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
10086. D3F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
10087. D3F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
10088. D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
10089. D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
10090. D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
10091. D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
10092. D3F1_IO_BASE_LIMIT__IO_BASE_MASK
10093. D3F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
10094. D3F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
10095. D3F1_IO_BASE_LIMIT__IO_BASE__SHIFT
10096. D3F1_IO_BASE_LIMIT__IO_LIMIT_MASK
10097. D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
10098. D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
10099. D3F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
10100. D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
10101. D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
10102. D3F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
10103. D3F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
10104. D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
10105. D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
10106. D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
10107. D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
10108. D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
10109. D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
10110. D3F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
10111. D3F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
10112. D3F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
10113. D3F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
10114. D3F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
10115. D3F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
10116. D3F1_LATENCY__LATENCY_TIMER_MASK
10117. D3F1_LATENCY__LATENCY_TIMER__SHIFT
10118. D3F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
10119. D3F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
10120. D3F1_LINK_CAP2__RESERVED_MASK
10121. D3F1_LINK_CAP2__RESERVED__SHIFT
10122. D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
10123. D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
10124. D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
10125. D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
10126. D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
10127. D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
10128. D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
10129. D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
10130. D3F1_LINK_CAP__L0S_EXIT_LATENCY_MASK
10131. D3F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
10132. D3F1_LINK_CAP__L1_EXIT_LATENCY_MASK
10133. D3F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
10134. D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
10135. D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
10136. D3F1_LINK_CAP__LINK_SPEED_MASK
10137. D3F1_LINK_CAP__LINK_SPEED__SHIFT
10138. D3F1_LINK_CAP__LINK_WIDTH_MASK
10139. D3F1_LINK_CAP__LINK_WIDTH__SHIFT
10140. D3F1_LINK_CAP__PM_SUPPORT_MASK
10141. D3F1_LINK_CAP__PM_SUPPORT__SHIFT
10142. D3F1_LINK_CAP__PORT_NUMBER_MASK
10143. D3F1_LINK_CAP__PORT_NUMBER__SHIFT
10144. D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
10145. D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
10146. D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
10147. D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
10148. D3F1_LINK_CNTL2__COMPLIANCE_SOS_MASK
10149. D3F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
10150. D3F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
10151. D3F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
10152. D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
10153. D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
10154. D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
10155. D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
10156. D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
10157. D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
10158. D3F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
10159. D3F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
10160. D3F1_LINK_CNTL2__XMIT_MARGIN_MASK
10161. D3F1_LINK_CNTL2__XMIT_MARGIN__SHIFT
10162. D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
10163. D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
10164. D3F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
10165. D3F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
10166. D3F1_LINK_CNTL__EXTENDED_SYNC_MASK
10167. D3F1_LINK_CNTL__EXTENDED_SYNC__SHIFT
10168. D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
10169. D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
10170. D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
10171. D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
10172. D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
10173. D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
10174. D3F1_LINK_CNTL__LINK_DIS_MASK
10175. D3F1_LINK_CNTL__LINK_DIS__SHIFT
10176. D3F1_LINK_CNTL__PM_CONTROL_MASK
10177. D3F1_LINK_CNTL__PM_CONTROL__SHIFT
10178. D3F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
10179. D3F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
10180. D3F1_LINK_CNTL__RETRAIN_LINK_MASK
10181. D3F1_LINK_CNTL__RETRAIN_LINK__SHIFT
10182. D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
10183. D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
10184. D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
10185. D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
10186. D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
10187. D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
10188. D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
10189. D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
10190. D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
10191. D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
10192. D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
10193. D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
10194. D3F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
10195. D3F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
10196. D3F1_LINK_STATUS__DL_ACTIVE_MASK
10197. D3F1_LINK_STATUS__DL_ACTIVE__SHIFT
10198. D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
10199. D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
10200. D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
10201. D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
10202. D3F1_LINK_STATUS__LINK_TRAINING_MASK
10203. D3F1_LINK_STATUS__LINK_TRAINING__SHIFT
10204. D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
10205. D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
10206. D3F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
10207. D3F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
10208. D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
10209. D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
10210. D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
10211. D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
10212. D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
10213. D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
10214. D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
10215. D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
10216. D3F1_MSI_CAP_LIST__CAP_ID_MASK
10217. D3F1_MSI_CAP_LIST__CAP_ID__SHIFT
10218. D3F1_MSI_CAP_LIST__NEXT_PTR_MASK
10219. D3F1_MSI_CAP_LIST__NEXT_PTR__SHIFT
10220. D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
10221. D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
10222. D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
10223. D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
10224. D3F1_MSI_MAP_CAP_LIST__CAP_ID_MASK
10225. D3F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
10226. D3F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
10227. D3F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
10228. D3F1_MSI_MAP_CAP__CAP_TYPE_MASK
10229. D3F1_MSI_MAP_CAP__CAP_TYPE__SHIFT
10230. D3F1_MSI_MAP_CAP__EN_MASK
10231. D3F1_MSI_MAP_CAP__EN__SHIFT
10232. D3F1_MSI_MAP_CAP__FIXD_MASK
10233. D3F1_MSI_MAP_CAP__FIXD__SHIFT
10234. D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
10235. D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
10236. D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
10237. D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
10238. D3F1_MSI_MSG_CNTL__MSI_64BIT_MASK
10239. D3F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
10240. D3F1_MSI_MSG_CNTL__MSI_EN_MASK
10241. D3F1_MSI_MSG_CNTL__MSI_EN__SHIFT
10242. D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
10243. D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
10244. D3F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
10245. D3F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
10246. D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
10247. D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
10248. D3F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
10249. D3F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
10250. D3F1_MSI_MSG_DATA__MSI_DATA_MASK
10251. D3F1_MSI_MSG_DATA__MSI_DATA__SHIFT
10252. D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
10253. D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
10254. D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
10255. D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
10256. D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
10257. D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
10258. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
10259. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
10260. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
10261. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
10262. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
10263. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
10264. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
10265. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
10266. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
10267. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
10268. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
10269. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
10270. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
10271. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
10272. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
10273. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
10274. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
10275. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
10276. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
10277. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
10278. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
10279. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
10280. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
10281. D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
10282. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
10283. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
10284. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
10285. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
10286. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
10287. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
10288. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
10289. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
10290. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
10291. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
10292. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
10293. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
10294. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
10295. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
10296. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
10297. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
10298. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
10299. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
10300. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
10301. D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
10302. D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
10303. D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
10304. D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
10305. D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
10306. D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
10307. D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
10308. D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
10309. D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
10310. D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
10311. D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
10312. D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
10313. D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
10314. D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
10315. D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
10316. D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
10317. D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
10318. D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
10319. D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
10320. D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
10321. D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
10322. D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
10323. D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
10324. D3F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK
10325. D3F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
10326. D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
10327. D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
10328. D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
10329. D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
10330. D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
10331. D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
10332. D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
10333. D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
10334. D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
10335. D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
10336. D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
10337. D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
10338. D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
10339. D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
10340. D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
10341. D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
10342. D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
10343. D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
10344. D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
10345. D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
10346. D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
10347. D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
10348. D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
10349. D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
10350. D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
10351. D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
10352. D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
10353. D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
10354. D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
10355. D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
10356. D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
10357. D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
10358. D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
10359. D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
10360. D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
10361. D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
10362. D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
10363. D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
10364. D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
10365. D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
10366. D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
10367. D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
10368. D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
10369. D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
10370. D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
10371. D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
10372. D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
10373. D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
10374. D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
10375. D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
10376. D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
10377. D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
10378. D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
10379. D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
10380. D3F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK
10381. D3F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
10382. D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
10383. D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
10384. D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
10385. D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
10386. D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
10387. D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
10388. D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
10389. D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
10390. D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
10391. D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
10392. D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
10393. D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
10394. D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
10395. D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
10396. D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
10397. D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
10398. D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
10399. D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
10400. D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
10401. D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
10402. D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
10403. D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
10404. D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
10405. D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
10406. D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
10407. D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
10408. D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
10409. D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
10410. D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
10411. D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
10412. D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
10413. D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
10414. D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
10415. D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
10416. D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
10417. D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
10418. D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
10419. D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
10420. D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
10421. D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
10422. D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
10423. D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
10424. D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
10425. D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
10426. D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
10427. D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
10428. D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
10429. D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
10430. D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
10431. D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
10432. D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
10433. D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
10434. D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
10435. D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
10436. D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
10437. D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
10438. D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
10439. D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
10440. D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
10441. D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
10442. D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
10443. D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
10444. D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
10445. D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
10446. D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
10447. D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
10448. D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
10449. D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
10450. D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
10451. D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
10452. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
10453. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
10454. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
10455. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
10456. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
10457. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
10458. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
10459. D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
10460. D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
10461. D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
10462. D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
10463. D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
10464. D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
10465. D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
10466. D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
10467. D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
10468. D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
10469. D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
10470. D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
10471. D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
10472. D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
10473. D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
10474. D3F1_PCIE_CAP_LIST__CAP_ID_MASK
10475. D3F1_PCIE_CAP_LIST__CAP_ID__SHIFT
10476. D3F1_PCIE_CAP_LIST__NEXT_PTR_MASK
10477. D3F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
10478. D3F1_PCIE_CAP__DEVICE_TYPE_MASK
10479. D3F1_PCIE_CAP__DEVICE_TYPE__SHIFT
10480. D3F1_PCIE_CAP__INT_MESSAGE_NUM_MASK
10481. D3F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
10482. D3F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
10483. D3F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
10484. D3F1_PCIE_CAP__VERSION_MASK
10485. D3F1_PCIE_CAP__VERSION__SHIFT
10486. D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
10487. D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
10488. D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
10489. D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
10490. D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
10491. D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
10492. D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
10493. D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
10494. D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
10495. D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
10496. D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
10497. D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
10498. D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
10499. D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
10500. D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
10501. D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
10502. D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
10503. D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
10504. D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
10505. D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
10506. D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
10507. D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
10508. D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
10509. D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
10510. D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
10511. D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
10512. D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
10513. D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
10514. D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
10515. D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
10516. D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
10517. D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
10518. D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
10519. D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
10520. D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
10521. D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
10522. D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
10523. D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
10524. D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
10525. D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
10526. D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
10527. D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
10528. D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
10529. D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
10530. D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
10531. D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
10532. D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
10533. D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
10534. D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
10535. D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
10536. D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
10537. D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
10538. D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
10539. D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
10540. D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
10541. D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
10542. D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
10543. D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
10544. D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
10545. D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
10546. D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
10547. D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
10548. D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
10549. D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
10550. D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
10551. D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
10552. D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
10553. D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
10554. D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
10555. D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
10556. D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
10557. D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
10558. D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
10559. D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
10560. D3F1_PCIE_FC_CPL__CPLD_CREDITS_MASK
10561. D3F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
10562. D3F1_PCIE_FC_CPL__CPLH_CREDITS_MASK
10563. D3F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
10564. D3F1_PCIE_FC_NP__NPD_CREDITS_MASK
10565. D3F1_PCIE_FC_NP__NPD_CREDITS__SHIFT
10566. D3F1_PCIE_FC_NP__NPH_CREDITS_MASK
10567. D3F1_PCIE_FC_NP__NPH_CREDITS__SHIFT
10568. D3F1_PCIE_FC_P__PD_CREDITS_MASK
10569. D3F1_PCIE_FC_P__PD_CREDITS__SHIFT
10570. D3F1_PCIE_FC_P__PH_CREDITS_MASK
10571. D3F1_PCIE_FC_P__PH_CREDITS__SHIFT
10572. D3F1_PCIE_HDR_LOG0__TLP_HDR_MASK
10573. D3F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
10574. D3F1_PCIE_HDR_LOG1__TLP_HDR_MASK
10575. D3F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
10576. D3F1_PCIE_HDR_LOG2__TLP_HDR_MASK
10577. D3F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
10578. D3F1_PCIE_HDR_LOG3__TLP_HDR_MASK
10579. D3F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
10580. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10581. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10582. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10583. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10584. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
10585. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
10586. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10587. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10588. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10589. D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10590. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10591. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10592. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10593. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10594. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
10595. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
10596. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10597. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10598. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10599. D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10600. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10601. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10602. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10603. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10604. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
10605. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
10606. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10607. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10608. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10609. D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10610. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10611. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10612. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10613. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10614. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
10615. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
10616. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10617. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10618. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10619. D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10620. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10621. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10622. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10623. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10624. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
10625. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
10626. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10627. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10628. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10629. D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10630. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10631. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10632. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10633. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10634. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
10635. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
10636. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10637. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10638. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10639. D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10640. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10641. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10642. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10643. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10644. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
10645. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
10646. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10647. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10648. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10649. D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10650. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10651. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10652. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10653. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10654. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
10655. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
10656. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10657. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10658. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10659. D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10660. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10661. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10662. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10663. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10664. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
10665. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
10666. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10667. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10668. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10669. D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10670. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10671. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10672. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10673. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10674. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
10675. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
10676. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10677. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10678. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10679. D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10680. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10681. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10682. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10683. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10684. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
10685. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
10686. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10687. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10688. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10689. D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10690. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10691. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10692. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10693. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10694. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
10695. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
10696. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10697. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10698. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10699. D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10700. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10701. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10702. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10703. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10704. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
10705. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
10706. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10707. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10708. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10709. D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10710. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10711. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10712. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10713. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10714. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
10715. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
10716. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10717. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10718. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10719. D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10720. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10721. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10722. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10723. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10724. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
10725. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
10726. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10727. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10728. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10729. D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10730. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
10731. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
10732. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
10733. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
10734. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
10735. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
10736. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
10737. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
10738. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
10739. D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
10740. D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
10741. D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
10742. D3F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
10743. D3F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
10744. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
10745. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
10746. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
10747. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
10748. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
10749. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
10750. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
10751. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
10752. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
10753. D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
10754. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
10755. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
10756. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
10757. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
10758. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
10759. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
10760. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
10761. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
10762. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
10763. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
10764. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
10765. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
10766. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
10767. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
10768. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
10769. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
10770. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
10771. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
10772. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
10773. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
10774. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
10775. D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
10776. D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
10777. D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
10778. D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
10779. D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
10780. D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
10781. D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
10782. D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
10783. D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
10784. D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
10785. D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
10786. D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
10787. D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
10788. D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
10789. D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
10790. D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
10791. D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
10792. D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
10793. D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
10794. D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
10795. D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
10796. D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
10797. D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
10798. D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
10799. D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
10800. D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
10801. D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
10802. D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
10803. D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
10804. D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
10805. D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
10806. D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
10807. D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
10808. D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
10809. D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
10810. D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
10811. D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
10812. D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
10813. D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
10814. D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
10815. D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
10816. D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
10817. D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
10818. D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
10819. D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
10820. D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
10821. D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
10822. D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
10823. D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
10824. D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
10825. D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
10826. D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
10827. D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
10828. D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
10829. D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
10830. D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
10831. D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
10832. D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
10833. D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
10834. D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
10835. D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
10836. D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
10837. D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
10838. D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
10839. D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
10840. D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
10841. D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
10842. D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
10843. D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
10844. D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
10845. D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
10846. D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
10847. D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
10848. D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
10849. D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
10850. D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
10851. D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
10852. D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
10853. D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
10854. D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
10855. D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
10856. D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
10857. D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
10858. D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
10859. D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
10860. D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
10861. D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
10862. D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
10863. D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
10864. D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
10865. D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
10866. D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
10867. D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
10868. D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
10869. D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
10870. D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
10871. D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
10872. D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
10873. D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
10874. D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
10875. D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
10876. D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
10877. D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
10878. D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
10879. D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
10880. D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
10881. D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
10882. D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
10883. D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
10884. D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
10885. D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
10886. D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
10887. D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
10888. D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
10889. D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
10890. D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
10891. D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
10892. D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
10893. D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
10894. D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
10895. D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
10896. D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
10897. D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
10898. D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
10899. D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
10900. D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
10901. D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
10902. D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
10903. D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
10904. D3F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
10905. D3F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
10906. D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
10907. D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
10908. D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
10909. D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
10910. D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
10911. D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
10912. D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
10913. D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
10914. D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
10915. D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
10916. D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
10917. D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
10918. D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
10919. D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
10920. D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
10921. D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
10922. D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
10923. D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
10924. D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
10925. D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
10926. D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
10927. D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
10928. D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
10929. D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
10930. D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
10931. D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
10932. D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
10933. D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
10934. D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
10935. D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
10936. D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
10937. D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
10938. D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
10939. D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
10940. D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
10941. D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
10942. D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
10943. D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
10944. D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
10945. D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
10946. D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
10947. D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
10948. D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
10949. D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
10950. D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
10951. D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
10952. D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
10953. D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
10954. D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
10955. D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
10956. D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
10957. D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
10958. D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
10959. D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
10960. D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
10961. D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
10962. D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
10963. D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
10964. D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
10965. D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
10966. D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
10967. D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
10968. D3F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK
10969. D3F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
10970. D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
10971. D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
10972. D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
10973. D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
10974. D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
10975. D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
10976. D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
10977. D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
10978. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
10979. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
10980. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
10981. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
10982. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
10983. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
10984. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
10985. D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
10986. D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
10987. D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
10988. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
10989. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
10990. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
10991. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
10992. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
10993. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
10994. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
10995. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
10996. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
10997. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
10998. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
10999. D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
11000. D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
11001. D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
11002. D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
11003. D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
11004. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
11005. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
11006. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
11007. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
11008. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
11009. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
11010. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
11011. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
11012. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
11013. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
11014. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
11015. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
11016. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
11017. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
11018. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
11019. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
11020. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
11021. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
11022. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
11023. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
11024. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
11025. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
11026. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
11027. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
11028. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
11029. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
11030. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
11031. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
11032. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
11033. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
11034. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
11035. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
11036. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
11037. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
11038. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
11039. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
11040. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
11041. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
11042. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
11043. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
11044. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
11045. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
11046. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
11047. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
11048. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
11049. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
11050. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
11051. D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
11052. D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
11053. D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
11054. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
11055. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
11056. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
11057. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
11058. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
11059. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
11060. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
11061. D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
11062. D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
11063. D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
11064. D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
11065. D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
11066. D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
11067. D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
11068. D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
11069. D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
11070. D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
11071. D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
11072. D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
11073. D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
11074. D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
11075. D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
11076. D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
11077. D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
11078. D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
11079. D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
11080. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
11081. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
11082. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
11083. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
11084. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
11085. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
11086. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
11087. D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
11088. D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
11089. D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
11090. D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
11091. D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
11092. D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
11093. D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
11094. D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
11095. D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
11096. D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
11097. D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
11098. D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
11099. D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
11100. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
11101. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
11102. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
11103. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
11104. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
11105. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
11106. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
11107. D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
11108. D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
11109. D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
11110. D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
11111. D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
11112. D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
11113. D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
11114. D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
11115. D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
11116. D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
11117. D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
11118. D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
11119. D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
11120. D3F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
11121. D3F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
11122. D3F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
11123. D3F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
11124. D3F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
11125. D3F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
11126. D3F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
11127. D3F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
11128. D3F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
11129. D3F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
11130. D3F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
11131. D3F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
11132. D3F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
11133. D3F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
11134. D3F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
11135. D3F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
11136. D3F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
11137. D3F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
11138. D3F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
11139. D3F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
11140. D3F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
11141. D3F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
11142. D3F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
11143. D3F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
11144. D3F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
11145. D3F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
11146. D3F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
11147. D3F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
11148. D3F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
11149. D3F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
11150. D3F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
11151. D3F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
11152. D3F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
11153. D3F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
11154. D3F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
11155. D3F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
11156. D3F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
11157. D3F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
11158. D3F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
11159. D3F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
11160. D3F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
11161. D3F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
11162. D3F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
11163. D3F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
11164. D3F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
11165. D3F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
11166. D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
11167. D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
11168. D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
11169. D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
11170. D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
11171. D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
11172. D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
11173. D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
11174. D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
11175. D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
11176. D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
11177. D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
11178. D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
11179. D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
11180. D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
11181. D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
11182. D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
11183. D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
11184. D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
11185. D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
11186. D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
11187. D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
11188. D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
11189. D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
11190. D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
11191. D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
11192. D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
11193. D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
11194. D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
11195. D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
11196. D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
11197. D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
11198. D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
11199. D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
11200. D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
11201. D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
11202. D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
11203. D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
11204. D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
11205. D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
11206. D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
11207. D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
11208. D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
11209. D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
11210. D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
11211. D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
11212. D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
11213. D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
11214. D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
11215. D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
11216. D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
11217. D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
11218. D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
11219. D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
11220. D3F1_PCIE_LINK_CNTL3__RESERVED_MASK
11221. D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT
11222. D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
11223. D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
11224. D3F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
11225. D3F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
11226. D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
11227. D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
11228. D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
11229. D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
11230. D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
11231. D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
11232. D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
11233. D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
11234. D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
11235. D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
11236. D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
11237. D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
11238. D3F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
11239. D3F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
11240. D3F1_PCIE_MC_CNTL__MC_ENABLE_MASK
11241. D3F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
11242. D3F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
11243. D3F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
11244. D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
11245. D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
11246. D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
11247. D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
11248. D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
11249. D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
11250. D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
11251. D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
11252. D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
11253. D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
11254. D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
11255. D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
11256. D3F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
11257. D3F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
11258. D3F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
11259. D3F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
11260. D3F1_PCIE_PORT_DATA__PCIE_DATA_MASK
11261. D3F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT
11262. D3F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK
11263. D3F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
11264. D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
11265. D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
11266. D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
11267. D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
11268. D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
11269. D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
11270. D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
11271. D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
11272. D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
11273. D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
11274. D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
11275. D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
11276. D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
11277. D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
11278. D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
11279. D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
11280. D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
11281. D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
11282. D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
11283. D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
11284. D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
11285. D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
11286. D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
11287. D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
11288. D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
11289. D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
11290. D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
11291. D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
11292. D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
11293. D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
11294. D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
11295. D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
11296. D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
11297. D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
11298. D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
11299. D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
11300. D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
11301. D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
11302. D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
11303. D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
11304. D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
11305. D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
11306. D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
11307. D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
11308. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
11309. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
11310. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
11311. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
11312. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
11313. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
11314. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
11315. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
11316. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
11317. D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
11318. D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
11319. D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
11320. D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
11321. D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
11322. D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
11323. D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
11324. D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
11325. D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
11326. D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
11327. D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
11328. D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
11329. D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
11330. D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
11331. D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
11332. D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
11333. D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
11334. D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
11335. D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
11336. D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
11337. D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
11338. D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
11339. D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
11340. D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
11341. D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
11342. D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
11343. D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
11344. D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
11345. D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
11346. D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
11347. D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
11348. D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
11349. D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
11350. D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
11351. D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
11352. D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
11353. D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
11354. D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
11355. D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
11356. D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
11357. D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
11358. D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
11359. D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
11360. D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
11361. D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
11362. D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
11363. D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
11364. D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
11365. D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
11366. D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
11367. D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
11368. D3F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK
11369. D3F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
11370. D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
11371. D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
11372. D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
11373. D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
11374. D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
11375. D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
11376. D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
11377. D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
11378. D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
11379. D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
11380. D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
11381. D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
11382. D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
11383. D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
11384. D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
11385. D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
11386. D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
11387. D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
11388. D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
11389. D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
11390. D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
11391. D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
11392. D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
11393. D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
11394. D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
11395. D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
11396. D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
11397. D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
11398. D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
11399. D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
11400. D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
11401. D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
11402. D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
11403. D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
11404. D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
11405. D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
11406. D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
11407. D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
11408. D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
11409. D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
11410. D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
11411. D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
11412. D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
11413. D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
11414. D3F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
11415. D3F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
11416. D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
11417. D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
11418. D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
11419. D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
11420. D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
11421. D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
11422. D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
11423. D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
11424. D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
11425. D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
11426. D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
11427. D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
11428. D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
11429. D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
11430. D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
11431. D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
11432. D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
11433. D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
11434. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
11435. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
11436. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
11437. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
11438. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
11439. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
11440. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
11441. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
11442. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
11443. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
11444. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
11445. D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
11446. D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
11447. D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
11448. D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
11449. D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
11450. D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
11451. D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
11452. D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
11453. D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
11454. D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
11455. D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
11456. D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
11457. D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
11458. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
11459. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
11460. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
11461. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
11462. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
11463. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
11464. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
11465. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
11466. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
11467. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
11468. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
11469. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
11470. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
11471. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
11472. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
11473. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
11474. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
11475. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
11476. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
11477. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
11478. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
11479. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
11480. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
11481. D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
11482. D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
11483. D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
11484. D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
11485. D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
11486. D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
11487. D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
11488. D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
11489. D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
11490. D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
11491. D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
11492. D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
11493. D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
11494. D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
11495. D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
11496. D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
11497. D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
11498. D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
11499. D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
11500. D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
11501. D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
11502. D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
11503. D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
11504. D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
11505. D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
11506. D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
11507. D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
11508. D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
11509. D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
11510. D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
11511. D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
11512. D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
11513. D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
11514. D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
11515. D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
11516. D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
11517. D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
11518. D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
11519. D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
11520. D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
11521. D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
11522. D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
11523. D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
11524. D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
11525. D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
11526. D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
11527. D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
11528. D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
11529. D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
11530. D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
11531. D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
11532. D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
11533. D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
11534. D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
11535. D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
11536. D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
11537. D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
11538. D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
11539. D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
11540. D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
11541. D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
11542. D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
11543. D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
11544. D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
11545. D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
11546. D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
11547. D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
11548. D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
11549. D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
11550. D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
11551. D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
11552. D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
11553. D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
11554. D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
11555. D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
11556. D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
11557. D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
11558. D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
11559. D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
11560. D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
11561. D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
11562. D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
11563. D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
11564. D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
11565. D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
11566. D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
11567. D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
11568. D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
11569. D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
11570. D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
11571. D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
11572. D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
11573. D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
11574. D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
11575. D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
11576. D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
11577. D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
11578. D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
11579. D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
11580. D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
11581. D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
11582. D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
11583. D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
11584. D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
11585. D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
11586. D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
11587. D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
11588. D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
11589. D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
11590. D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
11591. D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
11592. D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
11593. D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
11594. D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
11595. D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
11596. D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
11597. D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
11598. D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
11599. D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
11600. D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
11601. D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
11602. D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
11603. D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
11604. D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
11605. D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
11606. D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
11607. D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
11608. D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
11609. D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
11610. D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
11611. D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
11612. D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
11613. D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
11614. D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
11615. D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
11616. D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
11617. D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
11618. D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
11619. D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
11620. D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
11621. D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
11622. D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
11623. D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
11624. D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
11625. D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
11626. D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
11627. D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
11628. D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
11629. D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
11630. D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
11631. D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
11632. D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
11633. D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
11634. D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
11635. D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
11636. D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
11637. D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
11638. D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
11639. D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
11640. D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
11641. D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
11642. D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
11643. D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
11644. D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
11645. D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
11646. D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
11647. D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
11648. D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
11649. D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
11650. D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
11651. D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
11652. D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
11653. D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
11654. D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
11655. D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
11656. D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
11657. D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
11658. D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
11659. D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
11660. D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
11661. D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
11662. D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
11663. D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
11664. D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
11665. D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
11666. D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
11667. D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
11668. D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
11669. D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
11670. D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
11671. D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
11672. D3F1_PMI_CAP_LIST__CAP_ID_MASK
11673. D3F1_PMI_CAP_LIST__CAP_ID__SHIFT
11674. D3F1_PMI_CAP_LIST__NEXT_PTR_MASK
11675. D3F1_PMI_CAP_LIST__NEXT_PTR__SHIFT
11676. D3F1_PMI_CAP__AUX_CURRENT_MASK
11677. D3F1_PMI_CAP__AUX_CURRENT__SHIFT
11678. D3F1_PMI_CAP__D1_SUPPORT_MASK
11679. D3F1_PMI_CAP__D1_SUPPORT__SHIFT
11680. D3F1_PMI_CAP__D2_SUPPORT_MASK
11681. D3F1_PMI_CAP__D2_SUPPORT__SHIFT
11682. D3F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
11683. D3F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
11684. D3F1_PMI_CAP__PME_CLOCK_MASK
11685. D3F1_PMI_CAP__PME_CLOCK__SHIFT
11686. D3F1_PMI_CAP__PME_SUPPORT_MASK
11687. D3F1_PMI_CAP__PME_SUPPORT__SHIFT
11688. D3F1_PMI_CAP__VERSION_MASK
11689. D3F1_PMI_CAP__VERSION__SHIFT
11690. D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
11691. D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
11692. D3F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
11693. D3F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
11694. D3F1_PMI_STATUS_CNTL__DATA_SCALE_MASK
11695. D3F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
11696. D3F1_PMI_STATUS_CNTL__DATA_SELECT_MASK
11697. D3F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
11698. D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
11699. D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
11700. D3F1_PMI_STATUS_CNTL__PME_EN_MASK
11701. D3F1_PMI_STATUS_CNTL__PME_EN__SHIFT
11702. D3F1_PMI_STATUS_CNTL__PME_STATUS_MASK
11703. D3F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
11704. D3F1_PMI_STATUS_CNTL__PMI_DATA_MASK
11705. D3F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
11706. D3F1_PMI_STATUS_CNTL__POWER_STATE_MASK
11707. D3F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
11708. D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
11709. D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
11710. D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
11711. D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
11712. D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
11713. D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
11714. D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
11715. D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
11716. D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
11717. D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
11718. D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
11719. D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
11720. D3F1_PROG_INTERFACE__PROG_INTERFACE_MASK
11721. D3F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
11722. D3F1_REVISION_ID__MAJOR_REV_ID_MASK
11723. D3F1_REVISION_ID__MAJOR_REV_ID__SHIFT
11724. D3F1_REVISION_ID__MINOR_REV_ID_MASK
11725. D3F1_REVISION_ID__MINOR_REV_ID__SHIFT
11726. D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
11727. D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
11728. D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
11729. D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
11730. D3F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
11731. D3F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
11732. D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
11733. D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
11734. D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
11735. D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
11736. D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
11737. D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
11738. D3F1_ROOT_STATUS__PME_PENDING_MASK
11739. D3F1_ROOT_STATUS__PME_PENDING__SHIFT
11740. D3F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
11741. D3F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
11742. D3F1_ROOT_STATUS__PME_STATUS_MASK
11743. D3F1_ROOT_STATUS__PME_STATUS__SHIFT
11744. D3F1_SECONDARY_STATUS__CAP_LIST_MASK
11745. D3F1_SECONDARY_STATUS__CAP_LIST__SHIFT
11746. D3F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
11747. D3F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
11748. D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
11749. D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
11750. D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
11751. D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
11752. D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
11753. D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
11754. D3F1_SECONDARY_STATUS__PCI_66_EN_MASK
11755. D3F1_SECONDARY_STATUS__PCI_66_EN__SHIFT
11756. D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
11757. D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
11758. D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
11759. D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
11760. D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
11761. D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
11762. D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
11763. D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
11764. D3F1_SLOT_CAP2__RESERVED_MASK
11765. D3F1_SLOT_CAP2__RESERVED__SHIFT
11766. D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
11767. D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
11768. D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
11769. D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
11770. D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
11771. D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
11772. D3F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
11773. D3F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
11774. D3F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
11775. D3F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
11776. D3F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
11777. D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
11778. D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
11779. D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
11780. D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
11781. D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
11782. D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
11783. D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
11784. D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
11785. D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
11786. D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
11787. D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
11788. D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
11789. D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
11790. D3F1_SLOT_CNTL2__RESERVED_MASK
11791. D3F1_SLOT_CNTL2__RESERVED__SHIFT
11792. D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
11793. D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
11794. D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
11795. D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
11796. D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
11797. D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
11798. D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
11799. D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
11800. D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
11801. D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
11802. D3F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
11803. D3F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
11804. D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
11805. D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
11806. D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
11807. D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
11808. D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
11809. D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
11810. D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
11811. D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
11812. D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
11813. D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
11814. D3F1_SLOT_STATUS2__RESERVED_MASK
11815. D3F1_SLOT_STATUS2__RESERVED__SHIFT
11816. D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
11817. D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
11818. D3F1_SLOT_STATUS__COMMAND_COMPLETED_MASK
11819. D3F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
11820. D3F1_SLOT_STATUS__DL_STATE_CHANGED_MASK
11821. D3F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
11822. D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
11823. D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
11824. D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
11825. D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
11826. D3F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
11827. D3F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
11828. D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
11829. D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
11830. D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
11831. D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
11832. D3F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
11833. D3F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
11834. D3F1_SSID_CAP_LIST__CAP_ID_MASK
11835. D3F1_SSID_CAP_LIST__CAP_ID__SHIFT
11836. D3F1_SSID_CAP_LIST__NEXT_PTR_MASK
11837. D3F1_SSID_CAP_LIST__NEXT_PTR__SHIFT
11838. D3F1_SSID_CAP__SUBSYSTEM_ID_MASK
11839. D3F1_SSID_CAP__SUBSYSTEM_ID__SHIFT
11840. D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
11841. D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
11842. D3F1_STATUS__CAP_LIST_MASK
11843. D3F1_STATUS__CAP_LIST__SHIFT
11844. D3F1_STATUS__DEVSEL_TIMING_MASK
11845. D3F1_STATUS__DEVSEL_TIMING__SHIFT
11846. D3F1_STATUS__FAST_BACK_CAPABLE_MASK
11847. D3F1_STATUS__FAST_BACK_CAPABLE__SHIFT
11848. D3F1_STATUS__INT_STATUS_MASK
11849. D3F1_STATUS__INT_STATUS__SHIFT
11850. D3F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
11851. D3F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
11852. D3F1_STATUS__PARITY_ERROR_DETECTED_MASK
11853. D3F1_STATUS__PARITY_ERROR_DETECTED__SHIFT
11854. D3F1_STATUS__PCI_66_EN_MASK
11855. D3F1_STATUS__PCI_66_EN__SHIFT
11856. D3F1_STATUS__RECEIVED_MASTER_ABORT_MASK
11857. D3F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
11858. D3F1_STATUS__RECEIVED_TARGET_ABORT_MASK
11859. D3F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
11860. D3F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
11861. D3F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
11862. D3F1_STATUS__SIGNAL_TARGET_ABORT_MASK
11863. D3F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
11864. D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
11865. D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
11866. D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
11867. D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
11868. D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
11869. D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
11870. D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
11871. D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
11872. D3F1_SUB_CLASS__SUB_CLASS_MASK
11873. D3F1_SUB_CLASS__SUB_CLASS__SHIFT
11874. D3F1_VENDOR_ID__VENDOR_ID_MASK
11875. D3F1_VENDOR_ID__VENDOR_ID__SHIFT
11876. D3F2_BASE_CLASS__BASE_CLASS_MASK
11877. D3F2_BASE_CLASS__BASE_CLASS__SHIFT
11878. D3F2_BIST__BIST_CAP_MASK
11879. D3F2_BIST__BIST_CAP__SHIFT
11880. D3F2_BIST__BIST_COMP_MASK
11881. D3F2_BIST__BIST_COMP__SHIFT
11882. D3F2_BIST__BIST_STRT_MASK
11883. D3F2_BIST__BIST_STRT__SHIFT
11884. D3F2_CACHE_LINE__CACHE_LINE_SIZE_MASK
11885. D3F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
11886. D3F2_CAP_PTR__CAP_PTR_MASK
11887. D3F2_CAP_PTR__CAP_PTR__SHIFT
11888. D3F2_COMMAND__AD_STEPPING_MASK
11889. D3F2_COMMAND__AD_STEPPING__SHIFT
11890. D3F2_COMMAND__BUS_MASTER_EN_MASK
11891. D3F2_COMMAND__BUS_MASTER_EN__SHIFT
11892. D3F2_COMMAND__FAST_B2B_EN_MASK
11893. D3F2_COMMAND__FAST_B2B_EN__SHIFT
11894. D3F2_COMMAND__INT_DIS_MASK
11895. D3F2_COMMAND__INT_DIS__SHIFT
11896. D3F2_COMMAND__IO_ACCESS_EN_MASK
11897. D3F2_COMMAND__IO_ACCESS_EN__SHIFT
11898. D3F2_COMMAND__MEM_ACCESS_EN_MASK
11899. D3F2_COMMAND__MEM_ACCESS_EN__SHIFT
11900. D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
11901. D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
11902. D3F2_COMMAND__PAL_SNOOP_EN_MASK
11903. D3F2_COMMAND__PAL_SNOOP_EN__SHIFT
11904. D3F2_COMMAND__PARITY_ERROR_RESPONSE_MASK
11905. D3F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
11906. D3F2_COMMAND__SERR_EN_MASK
11907. D3F2_COMMAND__SERR_EN__SHIFT
11908. D3F2_COMMAND__SPECIAL_CYCLE_EN_MASK
11909. D3F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
11910. D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
11911. D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
11912. D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
11913. D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
11914. D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
11915. D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
11916. D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
11917. D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
11918. D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
11919. D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
11920. D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
11921. D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
11922. D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
11923. D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
11924. D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
11925. D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
11926. D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
11927. D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
11928. D3F2_DEVICE_CAP2__LTR_SUPPORTED_MASK
11929. D3F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
11930. D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
11931. D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
11932. D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
11933. D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
11934. D3F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
11935. D3F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
11936. D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
11937. D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
11938. D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
11939. D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
11940. D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
11941. D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
11942. D3F2_DEVICE_CAP__EXTENDED_TAG_MASK
11943. D3F2_DEVICE_CAP__EXTENDED_TAG__SHIFT
11944. D3F2_DEVICE_CAP__FLR_CAPABLE_MASK
11945. D3F2_DEVICE_CAP__FLR_CAPABLE__SHIFT
11946. D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
11947. D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
11948. D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
11949. D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
11950. D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
11951. D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
11952. D3F2_DEVICE_CAP__PHANTOM_FUNC_MASK
11953. D3F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
11954. D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
11955. D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
11956. D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
11957. D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
11958. D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
11959. D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
11960. D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
11961. D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
11962. D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
11963. D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
11964. D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
11965. D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
11966. D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
11967. D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
11968. D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
11969. D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
11970. D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
11971. D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
11972. D3F2_DEVICE_CNTL2__LTR_EN_MASK
11973. D3F2_DEVICE_CNTL2__LTR_EN__SHIFT
11974. D3F2_DEVICE_CNTL2__OBFF_EN_MASK
11975. D3F2_DEVICE_CNTL2__OBFF_EN__SHIFT
11976. D3F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
11977. D3F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
11978. D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
11979. D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
11980. D3F2_DEVICE_CNTL__CORR_ERR_EN_MASK
11981. D3F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
11982. D3F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
11983. D3F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
11984. D3F2_DEVICE_CNTL__FATAL_ERR_EN_MASK
11985. D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
11986. D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
11987. D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
11988. D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
11989. D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
11990. D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
11991. D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
11992. D3F2_DEVICE_CNTL__NO_SNOOP_EN_MASK
11993. D3F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
11994. D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
11995. D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
11996. D3F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
11997. D3F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
11998. D3F2_DEVICE_CNTL__USR_REPORT_EN_MASK
11999. D3F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
12000. D3F2_DEVICE_ID__DEVICE_ID_MASK
12001. D3F2_DEVICE_ID__DEVICE_ID__SHIFT
12002. D3F2_DEVICE_STATUS2__RESERVED_MASK
12003. D3F2_DEVICE_STATUS2__RESERVED__SHIFT
12004. D3F2_DEVICE_STATUS__AUX_PWR_MASK
12005. D3F2_DEVICE_STATUS__AUX_PWR__SHIFT
12006. D3F2_DEVICE_STATUS__CORR_ERR_MASK
12007. D3F2_DEVICE_STATUS__CORR_ERR__SHIFT
12008. D3F2_DEVICE_STATUS__FATAL_ERR_MASK
12009. D3F2_DEVICE_STATUS__FATAL_ERR__SHIFT
12010. D3F2_DEVICE_STATUS__NON_FATAL_ERR_MASK
12011. D3F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
12012. D3F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
12013. D3F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
12014. D3F2_DEVICE_STATUS__USR_DETECTED_MASK
12015. D3F2_DEVICE_STATUS__USR_DETECTED__SHIFT
12016. D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
12017. D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
12018. D3F2_HEADER__DEVICE_TYPE_MASK
12019. D3F2_HEADER__DEVICE_TYPE__SHIFT
12020. D3F2_HEADER__HEADER_TYPE_MASK
12021. D3F2_HEADER__HEADER_TYPE__SHIFT
12022. D3F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
12023. D3F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
12024. D3F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
12025. D3F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
12026. D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
12027. D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
12028. D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
12029. D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
12030. D3F2_IO_BASE_LIMIT__IO_BASE_MASK
12031. D3F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
12032. D3F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
12033. D3F2_IO_BASE_LIMIT__IO_BASE__SHIFT
12034. D3F2_IO_BASE_LIMIT__IO_LIMIT_MASK
12035. D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
12036. D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
12037. D3F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
12038. D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
12039. D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
12040. D3F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
12041. D3F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
12042. D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
12043. D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
12044. D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
12045. D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
12046. D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
12047. D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
12048. D3F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
12049. D3F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
12050. D3F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
12051. D3F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
12052. D3F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
12053. D3F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
12054. D3F2_LATENCY__LATENCY_TIMER_MASK
12055. D3F2_LATENCY__LATENCY_TIMER__SHIFT
12056. D3F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
12057. D3F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
12058. D3F2_LINK_CAP2__RESERVED_MASK
12059. D3F2_LINK_CAP2__RESERVED__SHIFT
12060. D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
12061. D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
12062. D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
12063. D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
12064. D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
12065. D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
12066. D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
12067. D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
12068. D3F2_LINK_CAP__L0S_EXIT_LATENCY_MASK
12069. D3F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
12070. D3F2_LINK_CAP__L1_EXIT_LATENCY_MASK
12071. D3F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
12072. D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
12073. D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
12074. D3F2_LINK_CAP__LINK_SPEED_MASK
12075. D3F2_LINK_CAP__LINK_SPEED__SHIFT
12076. D3F2_LINK_CAP__LINK_WIDTH_MASK
12077. D3F2_LINK_CAP__LINK_WIDTH__SHIFT
12078. D3F2_LINK_CAP__PM_SUPPORT_MASK
12079. D3F2_LINK_CAP__PM_SUPPORT__SHIFT
12080. D3F2_LINK_CAP__PORT_NUMBER_MASK
12081. D3F2_LINK_CAP__PORT_NUMBER__SHIFT
12082. D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
12083. D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
12084. D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
12085. D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
12086. D3F2_LINK_CNTL2__COMPLIANCE_SOS_MASK
12087. D3F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
12088. D3F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
12089. D3F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
12090. D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
12091. D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
12092. D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
12093. D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
12094. D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
12095. D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
12096. D3F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
12097. D3F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
12098. D3F2_LINK_CNTL2__XMIT_MARGIN_MASK
12099. D3F2_LINK_CNTL2__XMIT_MARGIN__SHIFT
12100. D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
12101. D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
12102. D3F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
12103. D3F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
12104. D3F2_LINK_CNTL__EXTENDED_SYNC_MASK
12105. D3F2_LINK_CNTL__EXTENDED_SYNC__SHIFT
12106. D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
12107. D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
12108. D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
12109. D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
12110. D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
12111. D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
12112. D3F2_LINK_CNTL__LINK_DIS_MASK
12113. D3F2_LINK_CNTL__LINK_DIS__SHIFT
12114. D3F2_LINK_CNTL__PM_CONTROL_MASK
12115. D3F2_LINK_CNTL__PM_CONTROL__SHIFT
12116. D3F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
12117. D3F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
12118. D3F2_LINK_CNTL__RETRAIN_LINK_MASK
12119. D3F2_LINK_CNTL__RETRAIN_LINK__SHIFT
12120. D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
12121. D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
12122. D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
12123. D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
12124. D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
12125. D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
12126. D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
12127. D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
12128. D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
12129. D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
12130. D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
12131. D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
12132. D3F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
12133. D3F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
12134. D3F2_LINK_STATUS__DL_ACTIVE_MASK
12135. D3F2_LINK_STATUS__DL_ACTIVE__SHIFT
12136. D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
12137. D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
12138. D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
12139. D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
12140. D3F2_LINK_STATUS__LINK_TRAINING_MASK
12141. D3F2_LINK_STATUS__LINK_TRAINING__SHIFT
12142. D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
12143. D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
12144. D3F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
12145. D3F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
12146. D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
12147. D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
12148. D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
12149. D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
12150. D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
12151. D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
12152. D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
12153. D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
12154. D3F2_MSI_CAP_LIST__CAP_ID_MASK
12155. D3F2_MSI_CAP_LIST__CAP_ID__SHIFT
12156. D3F2_MSI_CAP_LIST__NEXT_PTR_MASK
12157. D3F2_MSI_CAP_LIST__NEXT_PTR__SHIFT
12158. D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
12159. D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
12160. D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
12161. D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
12162. D3F2_MSI_MAP_CAP_LIST__CAP_ID_MASK
12163. D3F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
12164. D3F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
12165. D3F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
12166. D3F2_MSI_MAP_CAP__CAP_TYPE_MASK
12167. D3F2_MSI_MAP_CAP__CAP_TYPE__SHIFT
12168. D3F2_MSI_MAP_CAP__EN_MASK
12169. D3F2_MSI_MAP_CAP__EN__SHIFT
12170. D3F2_MSI_MAP_CAP__FIXD_MASK
12171. D3F2_MSI_MAP_CAP__FIXD__SHIFT
12172. D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
12173. D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
12174. D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
12175. D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
12176. D3F2_MSI_MSG_CNTL__MSI_64BIT_MASK
12177. D3F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
12178. D3F2_MSI_MSG_CNTL__MSI_EN_MASK
12179. D3F2_MSI_MSG_CNTL__MSI_EN__SHIFT
12180. D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
12181. D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
12182. D3F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
12183. D3F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
12184. D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
12185. D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
12186. D3F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
12187. D3F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
12188. D3F2_MSI_MSG_DATA__MSI_DATA_MASK
12189. D3F2_MSI_MSG_DATA__MSI_DATA__SHIFT
12190. D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
12191. D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
12192. D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
12193. D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
12194. D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
12195. D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
12196. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
12197. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
12198. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
12199. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
12200. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
12201. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
12202. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
12203. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
12204. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
12205. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
12206. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
12207. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
12208. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
12209. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
12210. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
12211. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
12212. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
12213. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
12214. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
12215. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
12216. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
12217. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
12218. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
12219. D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
12220. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
12221. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
12222. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
12223. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
12224. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
12225. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
12226. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
12227. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
12228. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
12229. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
12230. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
12231. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
12232. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
12233. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
12234. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
12235. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
12236. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
12237. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
12238. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
12239. D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
12240. D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
12241. D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
12242. D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
12243. D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
12244. D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
12245. D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
12246. D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
12247. D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
12248. D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
12249. D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
12250. D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
12251. D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
12252. D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
12253. D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
12254. D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
12255. D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
12256. D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
12257. D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
12258. D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
12259. D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
12260. D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
12261. D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
12262. D3F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK
12263. D3F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
12264. D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
12265. D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
12266. D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
12267. D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
12268. D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
12269. D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
12270. D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
12271. D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
12272. D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
12273. D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
12274. D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
12275. D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
12276. D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
12277. D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
12278. D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
12279. D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
12280. D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
12281. D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
12282. D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
12283. D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
12284. D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
12285. D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
12286. D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
12287. D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
12288. D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
12289. D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
12290. D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
12291. D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
12292. D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
12293. D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
12294. D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
12295. D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
12296. D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
12297. D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
12298. D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
12299. D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
12300. D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
12301. D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
12302. D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
12303. D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
12304. D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
12305. D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
12306. D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
12307. D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
12308. D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
12309. D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
12310. D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
12311. D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
12312. D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
12313. D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
12314. D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
12315. D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
12316. D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
12317. D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
12318. D3F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK
12319. D3F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
12320. D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
12321. D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
12322. D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
12323. D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
12324. D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
12325. D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
12326. D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
12327. D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
12328. D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
12329. D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
12330. D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
12331. D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
12332. D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
12333. D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
12334. D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
12335. D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
12336. D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
12337. D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
12338. D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
12339. D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
12340. D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
12341. D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
12342. D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
12343. D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
12344. D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
12345. D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
12346. D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
12347. D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
12348. D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
12349. D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
12350. D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
12351. D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
12352. D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
12353. D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
12354. D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
12355. D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
12356. D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
12357. D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
12358. D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
12359. D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
12360. D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
12361. D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
12362. D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
12363. D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
12364. D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
12365. D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
12366. D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
12367. D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
12368. D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
12369. D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
12370. D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
12371. D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
12372. D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
12373. D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
12374. D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
12375. D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
12376. D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
12377. D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
12378. D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
12379. D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
12380. D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
12381. D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
12382. D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
12383. D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
12384. D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
12385. D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
12386. D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
12387. D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
12388. D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
12389. D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
12390. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
12391. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
12392. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
12393. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
12394. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
12395. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
12396. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
12397. D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
12398. D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
12399. D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
12400. D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
12401. D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
12402. D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
12403. D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
12404. D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
12405. D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
12406. D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
12407. D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
12408. D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
12409. D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
12410. D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
12411. D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
12412. D3F2_PCIE_CAP_LIST__CAP_ID_MASK
12413. D3F2_PCIE_CAP_LIST__CAP_ID__SHIFT
12414. D3F2_PCIE_CAP_LIST__NEXT_PTR_MASK
12415. D3F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
12416. D3F2_PCIE_CAP__DEVICE_TYPE_MASK
12417. D3F2_PCIE_CAP__DEVICE_TYPE__SHIFT
12418. D3F2_PCIE_CAP__INT_MESSAGE_NUM_MASK
12419. D3F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
12420. D3F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
12421. D3F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
12422. D3F2_PCIE_CAP__VERSION_MASK
12423. D3F2_PCIE_CAP__VERSION__SHIFT
12424. D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
12425. D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
12426. D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
12427. D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
12428. D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
12429. D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
12430. D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
12431. D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
12432. D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
12433. D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
12434. D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
12435. D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
12436. D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
12437. D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
12438. D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
12439. D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
12440. D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
12441. D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
12442. D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
12443. D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
12444. D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
12445. D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
12446. D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
12447. D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
12448. D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
12449. D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
12450. D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
12451. D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
12452. D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
12453. D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
12454. D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
12455. D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
12456. D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
12457. D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
12458. D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
12459. D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
12460. D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
12461. D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
12462. D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
12463. D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
12464. D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
12465. D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
12466. D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
12467. D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
12468. D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
12469. D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
12470. D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
12471. D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
12472. D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
12473. D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
12474. D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
12475. D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
12476. D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
12477. D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
12478. D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
12479. D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
12480. D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
12481. D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
12482. D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
12483. D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
12484. D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
12485. D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
12486. D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
12487. D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
12488. D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
12489. D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
12490. D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
12491. D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
12492. D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
12493. D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
12494. D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
12495. D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
12496. D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
12497. D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
12498. D3F2_PCIE_FC_CPL__CPLD_CREDITS_MASK
12499. D3F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
12500. D3F2_PCIE_FC_CPL__CPLH_CREDITS_MASK
12501. D3F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
12502. D3F2_PCIE_FC_NP__NPD_CREDITS_MASK
12503. D3F2_PCIE_FC_NP__NPD_CREDITS__SHIFT
12504. D3F2_PCIE_FC_NP__NPH_CREDITS_MASK
12505. D3F2_PCIE_FC_NP__NPH_CREDITS__SHIFT
12506. D3F2_PCIE_FC_P__PD_CREDITS_MASK
12507. D3F2_PCIE_FC_P__PD_CREDITS__SHIFT
12508. D3F2_PCIE_FC_P__PH_CREDITS_MASK
12509. D3F2_PCIE_FC_P__PH_CREDITS__SHIFT
12510. D3F2_PCIE_HDR_LOG0__TLP_HDR_MASK
12511. D3F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
12512. D3F2_PCIE_HDR_LOG1__TLP_HDR_MASK
12513. D3F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
12514. D3F2_PCIE_HDR_LOG2__TLP_HDR_MASK
12515. D3F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
12516. D3F2_PCIE_HDR_LOG3__TLP_HDR_MASK
12517. D3F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
12518. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12519. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12520. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12521. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12522. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
12523. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
12524. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12525. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12526. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12527. D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12528. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12529. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12530. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12531. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12532. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
12533. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
12534. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12535. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12536. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12537. D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12538. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12539. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12540. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12541. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12542. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
12543. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
12544. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12545. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12546. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12547. D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12548. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12549. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12550. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12551. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12552. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
12553. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
12554. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12555. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12556. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12557. D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12558. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12559. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12560. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12561. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12562. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
12563. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
12564. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12565. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12566. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12567. D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12568. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12569. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12570. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12571. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12572. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
12573. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
12574. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12575. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12576. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12577. D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12578. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12579. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12580. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12581. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12582. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
12583. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
12584. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12585. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12586. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12587. D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12588. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12589. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12590. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12591. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12592. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
12593. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
12594. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12595. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12596. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12597. D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12598. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12599. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12600. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12601. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12602. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
12603. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
12604. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12605. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12606. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12607. D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12608. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12609. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12610. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12611. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12612. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
12613. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
12614. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12615. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12616. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12617. D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12618. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12619. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12620. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12621. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12622. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
12623. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
12624. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12625. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12626. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12627. D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12628. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12629. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12630. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12631. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12632. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
12633. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
12634. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12635. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12636. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12637. D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12638. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12639. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12640. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12641. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12642. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
12643. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
12644. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12645. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12646. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12647. D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12648. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12649. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12650. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12651. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12652. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
12653. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
12654. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12655. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12656. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12657. D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12658. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12659. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12660. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12661. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12662. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
12663. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
12664. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12665. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12666. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12667. D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12668. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
12669. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
12670. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
12671. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
12672. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
12673. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
12674. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
12675. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
12676. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
12677. D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
12678. D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
12679. D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
12680. D3F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
12681. D3F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
12682. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
12683. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
12684. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
12685. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
12686. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
12687. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
12688. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
12689. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
12690. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
12691. D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
12692. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
12693. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
12694. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
12695. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
12696. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
12697. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
12698. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
12699. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
12700. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
12701. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
12702. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
12703. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
12704. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
12705. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
12706. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
12707. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
12708. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
12709. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
12710. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
12711. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
12712. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
12713. D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
12714. D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
12715. D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
12716. D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
12717. D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
12718. D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
12719. D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
12720. D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
12721. D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
12722. D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
12723. D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
12724. D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
12725. D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
12726. D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
12727. D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
12728. D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
12729. D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
12730. D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
12731. D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
12732. D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
12733. D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
12734. D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
12735. D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
12736. D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
12737. D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
12738. D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
12739. D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
12740. D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
12741. D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
12742. D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
12743. D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
12744. D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
12745. D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
12746. D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
12747. D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
12748. D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
12749. D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
12750. D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
12751. D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
12752. D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
12753. D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
12754. D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
12755. D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
12756. D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
12757. D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
12758. D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
12759. D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
12760. D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
12761. D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
12762. D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
12763. D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
12764. D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
12765. D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
12766. D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
12767. D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
12768. D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
12769. D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
12770. D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
12771. D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
12772. D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
12773. D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
12774. D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
12775. D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
12776. D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
12777. D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
12778. D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
12779. D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
12780. D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
12781. D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
12782. D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
12783. D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
12784. D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
12785. D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
12786. D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
12787. D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
12788. D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
12789. D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
12790. D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
12791. D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
12792. D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
12793. D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
12794. D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
12795. D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
12796. D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
12797. D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
12798. D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
12799. D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
12800. D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
12801. D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
12802. D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
12803. D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
12804. D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
12805. D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
12806. D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
12807. D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
12808. D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
12809. D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
12810. D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
12811. D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
12812. D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
12813. D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
12814. D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
12815. D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
12816. D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
12817. D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
12818. D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
12819. D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
12820. D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
12821. D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
12822. D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
12823. D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
12824. D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
12825. D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
12826. D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
12827. D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
12828. D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
12829. D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
12830. D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
12831. D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
12832. D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
12833. D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
12834. D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
12835. D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
12836. D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
12837. D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
12838. D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
12839. D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
12840. D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
12841. D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
12842. D3F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
12843. D3F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
12844. D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
12845. D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
12846. D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
12847. D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
12848. D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
12849. D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
12850. D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
12851. D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
12852. D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
12853. D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
12854. D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
12855. D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
12856. D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
12857. D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
12858. D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
12859. D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
12860. D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
12861. D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
12862. D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
12863. D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
12864. D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
12865. D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
12866. D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
12867. D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
12868. D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
12869. D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
12870. D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
12871. D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
12872. D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
12873. D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
12874. D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
12875. D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
12876. D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
12877. D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
12878. D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
12879. D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
12880. D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
12881. D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
12882. D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
12883. D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
12884. D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
12885. D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
12886. D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
12887. D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
12888. D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
12889. D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
12890. D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
12891. D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
12892. D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
12893. D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
12894. D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
12895. D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
12896. D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
12897. D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
12898. D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
12899. D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
12900. D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
12901. D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
12902. D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
12903. D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
12904. D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
12905. D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
12906. D3F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK
12907. D3F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
12908. D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
12909. D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
12910. D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
12911. D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
12912. D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
12913. D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
12914. D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
12915. D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
12916. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
12917. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
12918. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
12919. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
12920. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
12921. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
12922. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
12923. D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
12924. D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
12925. D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
12926. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
12927. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
12928. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
12929. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
12930. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
12931. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
12932. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
12933. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
12934. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
12935. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
12936. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
12937. D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
12938. D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
12939. D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
12940. D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
12941. D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
12942. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
12943. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
12944. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
12945. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
12946. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
12947. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
12948. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
12949. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
12950. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
12951. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
12952. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
12953. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
12954. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
12955. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
12956. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
12957. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
12958. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
12959. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
12960. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
12961. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
12962. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
12963. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
12964. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
12965. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
12966. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
12967. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
12968. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
12969. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
12970. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
12971. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
12972. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
12973. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
12974. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
12975. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
12976. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
12977. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
12978. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
12979. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
12980. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
12981. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
12982. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
12983. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
12984. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
12985. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
12986. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
12987. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
12988. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
12989. D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
12990. D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
12991. D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
12992. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
12993. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
12994. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
12995. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
12996. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
12997. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
12998. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
12999. D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
13000. D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
13001. D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
13002. D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
13003. D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
13004. D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
13005. D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
13006. D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
13007. D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
13008. D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
13009. D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
13010. D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
13011. D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
13012. D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
13013. D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
13014. D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
13015. D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
13016. D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
13017. D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
13018. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
13019. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
13020. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
13021. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
13022. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
13023. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
13024. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
13025. D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
13026. D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
13027. D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
13028. D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
13029. D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
13030. D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
13031. D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
13032. D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
13033. D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
13034. D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
13035. D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
13036. D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
13037. D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
13038. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
13039. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
13040. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
13041. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
13042. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
13043. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
13044. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
13045. D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
13046. D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
13047. D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
13048. D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
13049. D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
13050. D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
13051. D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
13052. D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
13053. D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
13054. D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
13055. D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
13056. D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
13057. D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
13058. D3F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
13059. D3F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
13060. D3F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
13061. D3F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
13062. D3F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
13063. D3F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
13064. D3F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
13065. D3F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
13066. D3F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
13067. D3F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
13068. D3F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
13069. D3F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
13070. D3F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
13071. D3F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
13072. D3F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
13073. D3F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
13074. D3F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
13075. D3F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
13076. D3F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
13077. D3F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
13078. D3F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
13079. D3F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
13080. D3F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
13081. D3F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
13082. D3F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
13083. D3F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
13084. D3F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
13085. D3F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
13086. D3F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
13087. D3F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
13088. D3F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
13089. D3F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
13090. D3F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
13091. D3F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
13092. D3F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
13093. D3F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
13094. D3F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
13095. D3F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
13096. D3F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
13097. D3F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
13098. D3F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
13099. D3F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
13100. D3F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
13101. D3F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
13102. D3F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
13103. D3F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
13104. D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
13105. D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
13106. D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
13107. D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
13108. D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
13109. D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
13110. D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
13111. D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
13112. D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
13113. D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
13114. D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
13115. D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
13116. D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
13117. D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
13118. D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
13119. D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
13120. D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
13121. D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
13122. D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
13123. D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
13124. D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
13125. D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
13126. D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
13127. D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
13128. D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
13129. D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
13130. D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
13131. D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
13132. D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
13133. D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
13134. D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
13135. D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
13136. D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
13137. D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
13138. D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
13139. D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
13140. D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
13141. D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
13142. D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
13143. D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
13144. D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
13145. D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
13146. D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
13147. D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
13148. D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
13149. D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
13150. D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
13151. D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
13152. D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
13153. D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
13154. D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
13155. D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
13156. D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
13157. D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
13158. D3F2_PCIE_LINK_CNTL3__RESERVED_MASK
13159. D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT
13160. D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
13161. D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
13162. D3F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
13163. D3F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
13164. D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
13165. D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
13166. D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
13167. D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
13168. D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
13169. D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
13170. D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
13171. D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
13172. D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
13173. D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
13174. D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
13175. D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
13176. D3F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
13177. D3F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
13178. D3F2_PCIE_MC_CNTL__MC_ENABLE_MASK
13179. D3F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
13180. D3F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
13181. D3F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
13182. D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
13183. D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
13184. D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
13185. D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
13186. D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
13187. D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
13188. D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
13189. D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
13190. D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
13191. D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
13192. D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
13193. D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
13194. D3F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
13195. D3F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
13196. D3F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
13197. D3F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
13198. D3F2_PCIE_PORT_DATA__PCIE_DATA_MASK
13199. D3F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT
13200. D3F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK
13201. D3F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
13202. D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
13203. D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
13204. D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
13205. D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
13206. D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
13207. D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
13208. D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
13209. D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
13210. D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
13211. D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
13212. D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
13213. D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
13214. D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
13215. D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
13216. D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
13217. D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
13218. D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
13219. D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
13220. D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
13221. D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
13222. D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
13223. D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
13224. D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
13225. D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
13226. D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
13227. D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
13228. D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
13229. D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
13230. D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
13231. D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
13232. D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
13233. D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
13234. D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
13235. D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
13236. D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
13237. D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
13238. D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
13239. D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
13240. D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
13241. D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
13242. D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
13243. D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
13244. D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
13245. D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
13246. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
13247. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
13248. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
13249. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
13250. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
13251. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
13252. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
13253. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
13254. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
13255. D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
13256. D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
13257. D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
13258. D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
13259. D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
13260. D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
13261. D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
13262. D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
13263. D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
13264. D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
13265. D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
13266. D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
13267. D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
13268. D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
13269. D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
13270. D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
13271. D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
13272. D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
13273. D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
13274. D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
13275. D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
13276. D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
13277. D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
13278. D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
13279. D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
13280. D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
13281. D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
13282. D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
13283. D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
13284. D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
13285. D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
13286. D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
13287. D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
13288. D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
13289. D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
13290. D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
13291. D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
13292. D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
13293. D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
13294. D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
13295. D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
13296. D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
13297. D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
13298. D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
13299. D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
13300. D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
13301. D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
13302. D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
13303. D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
13304. D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
13305. D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
13306. D3F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK
13307. D3F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
13308. D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
13309. D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
13310. D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
13311. D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
13312. D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
13313. D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
13314. D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
13315. D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
13316. D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
13317. D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
13318. D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
13319. D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
13320. D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
13321. D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
13322. D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
13323. D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
13324. D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
13325. D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
13326. D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
13327. D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
13328. D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
13329. D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
13330. D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
13331. D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
13332. D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
13333. D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
13334. D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
13335. D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
13336. D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
13337. D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
13338. D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
13339. D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
13340. D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
13341. D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
13342. D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
13343. D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
13344. D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
13345. D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
13346. D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
13347. D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
13348. D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
13349. D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
13350. D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
13351. D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
13352. D3F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
13353. D3F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
13354. D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
13355. D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
13356. D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
13357. D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
13358. D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
13359. D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
13360. D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
13361. D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
13362. D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
13363. D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
13364. D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
13365. D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
13366. D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
13367. D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
13368. D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
13369. D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
13370. D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
13371. D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
13372. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
13373. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
13374. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
13375. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
13376. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
13377. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
13378. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
13379. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
13380. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
13381. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
13382. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
13383. D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
13384. D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
13385. D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
13386. D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
13387. D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
13388. D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
13389. D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
13390. D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
13391. D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
13392. D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
13393. D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
13394. D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
13395. D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
13396. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
13397. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
13398. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
13399. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
13400. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
13401. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
13402. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
13403. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
13404. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
13405. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
13406. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
13407. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
13408. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
13409. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
13410. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
13411. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
13412. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
13413. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
13414. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
13415. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
13416. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
13417. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
13418. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
13419. D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
13420. D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
13421. D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
13422. D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
13423. D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
13424. D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
13425. D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
13426. D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
13427. D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
13428. D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
13429. D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
13430. D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
13431. D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
13432. D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
13433. D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
13434. D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
13435. D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
13436. D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
13437. D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
13438. D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
13439. D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
13440. D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
13441. D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
13442. D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
13443. D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
13444. D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
13445. D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
13446. D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
13447. D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
13448. D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
13449. D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
13450. D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
13451. D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
13452. D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
13453. D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
13454. D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
13455. D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
13456. D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
13457. D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
13458. D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
13459. D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
13460. D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
13461. D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
13462. D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
13463. D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
13464. D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
13465. D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
13466. D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
13467. D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
13468. D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
13469. D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
13470. D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
13471. D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
13472. D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
13473. D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
13474. D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
13475. D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
13476. D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
13477. D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
13478. D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
13479. D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
13480. D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
13481. D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
13482. D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
13483. D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
13484. D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
13485. D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
13486. D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
13487. D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
13488. D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
13489. D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
13490. D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
13491. D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
13492. D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
13493. D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
13494. D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
13495. D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
13496. D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
13497. D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
13498. D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
13499. D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
13500. D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
13501. D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
13502. D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
13503. D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
13504. D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
13505. D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
13506. D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
13507. D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
13508. D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
13509. D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
13510. D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
13511. D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
13512. D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
13513. D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
13514. D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
13515. D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
13516. D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
13517. D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
13518. D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
13519. D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
13520. D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
13521. D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
13522. D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
13523. D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
13524. D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
13525. D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
13526. D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
13527. D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
13528. D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
13529. D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
13530. D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
13531. D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
13532. D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
13533. D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
13534. D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
13535. D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
13536. D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
13537. D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
13538. D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
13539. D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
13540. D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
13541. D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
13542. D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
13543. D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
13544. D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
13545. D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
13546. D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
13547. D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
13548. D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
13549. D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
13550. D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
13551. D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
13552. D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
13553. D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
13554. D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
13555. D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
13556. D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
13557. D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
13558. D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
13559. D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
13560. D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
13561. D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
13562. D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
13563. D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
13564. D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
13565. D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
13566. D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
13567. D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
13568. D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
13569. D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
13570. D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
13571. D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
13572. D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
13573. D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
13574. D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
13575. D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
13576. D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
13577. D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
13578. D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
13579. D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
13580. D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
13581. D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
13582. D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
13583. D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
13584. D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
13585. D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
13586. D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
13587. D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
13588. D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
13589. D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
13590. D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
13591. D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
13592. D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
13593. D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
13594. D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
13595. D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
13596. D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
13597. D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
13598. D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
13599. D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
13600. D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
13601. D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
13602. D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
13603. D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
13604. D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
13605. D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
13606. D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
13607. D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
13608. D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
13609. D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
13610. D3F2_PMI_CAP_LIST__CAP_ID_MASK
13611. D3F2_PMI_CAP_LIST__CAP_ID__SHIFT
13612. D3F2_PMI_CAP_LIST__NEXT_PTR_MASK
13613. D3F2_PMI_CAP_LIST__NEXT_PTR__SHIFT
13614. D3F2_PMI_CAP__AUX_CURRENT_MASK
13615. D3F2_PMI_CAP__AUX_CURRENT__SHIFT
13616. D3F2_PMI_CAP__D1_SUPPORT_MASK
13617. D3F2_PMI_CAP__D1_SUPPORT__SHIFT
13618. D3F2_PMI_CAP__D2_SUPPORT_MASK
13619. D3F2_PMI_CAP__D2_SUPPORT__SHIFT
13620. D3F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
13621. D3F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
13622. D3F2_PMI_CAP__PME_CLOCK_MASK
13623. D3F2_PMI_CAP__PME_CLOCK__SHIFT
13624. D3F2_PMI_CAP__PME_SUPPORT_MASK
13625. D3F2_PMI_CAP__PME_SUPPORT__SHIFT
13626. D3F2_PMI_CAP__VERSION_MASK
13627. D3F2_PMI_CAP__VERSION__SHIFT
13628. D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
13629. D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
13630. D3F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
13631. D3F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
13632. D3F2_PMI_STATUS_CNTL__DATA_SCALE_MASK
13633. D3F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
13634. D3F2_PMI_STATUS_CNTL__DATA_SELECT_MASK
13635. D3F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
13636. D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
13637. D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
13638. D3F2_PMI_STATUS_CNTL__PME_EN_MASK
13639. D3F2_PMI_STATUS_CNTL__PME_EN__SHIFT
13640. D3F2_PMI_STATUS_CNTL__PME_STATUS_MASK
13641. D3F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
13642. D3F2_PMI_STATUS_CNTL__PMI_DATA_MASK
13643. D3F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
13644. D3F2_PMI_STATUS_CNTL__POWER_STATE_MASK
13645. D3F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
13646. D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
13647. D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
13648. D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
13649. D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
13650. D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
13651. D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
13652. D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
13653. D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
13654. D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
13655. D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
13656. D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
13657. D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
13658. D3F2_PROG_INTERFACE__PROG_INTERFACE_MASK
13659. D3F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
13660. D3F2_REVISION_ID__MAJOR_REV_ID_MASK
13661. D3F2_REVISION_ID__MAJOR_REV_ID__SHIFT
13662. D3F2_REVISION_ID__MINOR_REV_ID_MASK
13663. D3F2_REVISION_ID__MINOR_REV_ID__SHIFT
13664. D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
13665. D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
13666. D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
13667. D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
13668. D3F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
13669. D3F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
13670. D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
13671. D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
13672. D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
13673. D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
13674. D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
13675. D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
13676. D3F2_ROOT_STATUS__PME_PENDING_MASK
13677. D3F2_ROOT_STATUS__PME_PENDING__SHIFT
13678. D3F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
13679. D3F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
13680. D3F2_ROOT_STATUS__PME_STATUS_MASK
13681. D3F2_ROOT_STATUS__PME_STATUS__SHIFT
13682. D3F2_SECONDARY_STATUS__CAP_LIST_MASK
13683. D3F2_SECONDARY_STATUS__CAP_LIST__SHIFT
13684. D3F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
13685. D3F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
13686. D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
13687. D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
13688. D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
13689. D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
13690. D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
13691. D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
13692. D3F2_SECONDARY_STATUS__PCI_66_EN_MASK
13693. D3F2_SECONDARY_STATUS__PCI_66_EN__SHIFT
13694. D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
13695. D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
13696. D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
13697. D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
13698. D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
13699. D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
13700. D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
13701. D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
13702. D3F2_SLOT_CAP2__RESERVED_MASK
13703. D3F2_SLOT_CAP2__RESERVED__SHIFT
13704. D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
13705. D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
13706. D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
13707. D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
13708. D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
13709. D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
13710. D3F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
13711. D3F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
13712. D3F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
13713. D3F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
13714. D3F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
13715. D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
13716. D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
13717. D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
13718. D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
13719. D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
13720. D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
13721. D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
13722. D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
13723. D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
13724. D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
13725. D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
13726. D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
13727. D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
13728. D3F2_SLOT_CNTL2__RESERVED_MASK
13729. D3F2_SLOT_CNTL2__RESERVED__SHIFT
13730. D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
13731. D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
13732. D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
13733. D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
13734. D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
13735. D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
13736. D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
13737. D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
13738. D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
13739. D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
13740. D3F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
13741. D3F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
13742. D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
13743. D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
13744. D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
13745. D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
13746. D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
13747. D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
13748. D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
13749. D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
13750. D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
13751. D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
13752. D3F2_SLOT_STATUS2__RESERVED_MASK
13753. D3F2_SLOT_STATUS2__RESERVED__SHIFT
13754. D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
13755. D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
13756. D3F2_SLOT_STATUS__COMMAND_COMPLETED_MASK
13757. D3F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
13758. D3F2_SLOT_STATUS__DL_STATE_CHANGED_MASK
13759. D3F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
13760. D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
13761. D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
13762. D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
13763. D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
13764. D3F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
13765. D3F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
13766. D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
13767. D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
13768. D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
13769. D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
13770. D3F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
13771. D3F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
13772. D3F2_SSID_CAP_LIST__CAP_ID_MASK
13773. D3F2_SSID_CAP_LIST__CAP_ID__SHIFT
13774. D3F2_SSID_CAP_LIST__NEXT_PTR_MASK
13775. D3F2_SSID_CAP_LIST__NEXT_PTR__SHIFT
13776. D3F2_SSID_CAP__SUBSYSTEM_ID_MASK
13777. D3F2_SSID_CAP__SUBSYSTEM_ID__SHIFT
13778. D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
13779. D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
13780. D3F2_STATUS__CAP_LIST_MASK
13781. D3F2_STATUS__CAP_LIST__SHIFT
13782. D3F2_STATUS__DEVSEL_TIMING_MASK
13783. D3F2_STATUS__DEVSEL_TIMING__SHIFT
13784. D3F2_STATUS__FAST_BACK_CAPABLE_MASK
13785. D3F2_STATUS__FAST_BACK_CAPABLE__SHIFT
13786. D3F2_STATUS__INT_STATUS_MASK
13787. D3F2_STATUS__INT_STATUS__SHIFT
13788. D3F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
13789. D3F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
13790. D3F2_STATUS__PARITY_ERROR_DETECTED_MASK
13791. D3F2_STATUS__PARITY_ERROR_DETECTED__SHIFT
13792. D3F2_STATUS__PCI_66_EN_MASK
13793. D3F2_STATUS__PCI_66_EN__SHIFT
13794. D3F2_STATUS__RECEIVED_MASTER_ABORT_MASK
13795. D3F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
13796. D3F2_STATUS__RECEIVED_TARGET_ABORT_MASK
13797. D3F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
13798. D3F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
13799. D3F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
13800. D3F2_STATUS__SIGNAL_TARGET_ABORT_MASK
13801. D3F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
13802. D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
13803. D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
13804. D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
13805. D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
13806. D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
13807. D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
13808. D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
13809. D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
13810. D3F2_SUB_CLASS__SUB_CLASS_MASK
13811. D3F2_SUB_CLASS__SUB_CLASS__SHIFT
13812. D3F2_VENDOR_ID__VENDOR_ID_MASK
13813. D3F2_VENDOR_ID__VENDOR_ID__SHIFT
13814. D3F3_BASE_CLASS__BASE_CLASS_MASK
13815. D3F3_BASE_CLASS__BASE_CLASS__SHIFT
13816. D3F3_BIST__BIST_CAP_MASK
13817. D3F3_BIST__BIST_CAP__SHIFT
13818. D3F3_BIST__BIST_COMP_MASK
13819. D3F3_BIST__BIST_COMP__SHIFT
13820. D3F3_BIST__BIST_STRT_MASK
13821. D3F3_BIST__BIST_STRT__SHIFT
13822. D3F3_CACHE_LINE__CACHE_LINE_SIZE_MASK
13823. D3F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
13824. D3F3_CAP_PTR__CAP_PTR_MASK
13825. D3F3_CAP_PTR__CAP_PTR__SHIFT
13826. D3F3_COMMAND__AD_STEPPING_MASK
13827. D3F3_COMMAND__AD_STEPPING__SHIFT
13828. D3F3_COMMAND__BUS_MASTER_EN_MASK
13829. D3F3_COMMAND__BUS_MASTER_EN__SHIFT
13830. D3F3_COMMAND__FAST_B2B_EN_MASK
13831. D3F3_COMMAND__FAST_B2B_EN__SHIFT
13832. D3F3_COMMAND__INT_DIS_MASK
13833. D3F3_COMMAND__INT_DIS__SHIFT
13834. D3F3_COMMAND__IO_ACCESS_EN_MASK
13835. D3F3_COMMAND__IO_ACCESS_EN__SHIFT
13836. D3F3_COMMAND__MEM_ACCESS_EN_MASK
13837. D3F3_COMMAND__MEM_ACCESS_EN__SHIFT
13838. D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
13839. D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
13840. D3F3_COMMAND__PAL_SNOOP_EN_MASK
13841. D3F3_COMMAND__PAL_SNOOP_EN__SHIFT
13842. D3F3_COMMAND__PARITY_ERROR_RESPONSE_MASK
13843. D3F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
13844. D3F3_COMMAND__SERR_EN_MASK
13845. D3F3_COMMAND__SERR_EN__SHIFT
13846. D3F3_COMMAND__SPECIAL_CYCLE_EN_MASK
13847. D3F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT
13848. D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
13849. D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
13850. D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
13851. D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
13852. D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
13853. D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
13854. D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
13855. D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
13856. D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
13857. D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
13858. D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
13859. D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
13860. D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
13861. D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
13862. D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
13863. D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
13864. D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
13865. D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
13866. D3F3_DEVICE_CAP2__LTR_SUPPORTED_MASK
13867. D3F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
13868. D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
13869. D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
13870. D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
13871. D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
13872. D3F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK
13873. D3F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
13874. D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
13875. D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
13876. D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
13877. D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
13878. D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
13879. D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
13880. D3F3_DEVICE_CAP__EXTENDED_TAG_MASK
13881. D3F3_DEVICE_CAP__EXTENDED_TAG__SHIFT
13882. D3F3_DEVICE_CAP__FLR_CAPABLE_MASK
13883. D3F3_DEVICE_CAP__FLR_CAPABLE__SHIFT
13884. D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
13885. D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
13886. D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
13887. D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
13888. D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
13889. D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
13890. D3F3_DEVICE_CAP__PHANTOM_FUNC_MASK
13891. D3F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT
13892. D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
13893. D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
13894. D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
13895. D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
13896. D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
13897. D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
13898. D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
13899. D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
13900. D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
13901. D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
13902. D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
13903. D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
13904. D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
13905. D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
13906. D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
13907. D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
13908. D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
13909. D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
13910. D3F3_DEVICE_CNTL2__LTR_EN_MASK
13911. D3F3_DEVICE_CNTL2__LTR_EN__SHIFT
13912. D3F3_DEVICE_CNTL2__OBFF_EN_MASK
13913. D3F3_DEVICE_CNTL2__OBFF_EN__SHIFT
13914. D3F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
13915. D3F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
13916. D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
13917. D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
13918. D3F3_DEVICE_CNTL__CORR_ERR_EN_MASK
13919. D3F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT
13920. D3F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
13921. D3F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
13922. D3F3_DEVICE_CNTL__FATAL_ERR_EN_MASK
13923. D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
13924. D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
13925. D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
13926. D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
13927. D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
13928. D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
13929. D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
13930. D3F3_DEVICE_CNTL__NO_SNOOP_EN_MASK
13931. D3F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
13932. D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
13933. D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
13934. D3F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK
13935. D3F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
13936. D3F3_DEVICE_CNTL__USR_REPORT_EN_MASK
13937. D3F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT
13938. D3F3_DEVICE_ID__DEVICE_ID_MASK
13939. D3F3_DEVICE_ID__DEVICE_ID__SHIFT
13940. D3F3_DEVICE_STATUS2__RESERVED_MASK
13941. D3F3_DEVICE_STATUS2__RESERVED__SHIFT
13942. D3F3_DEVICE_STATUS__AUX_PWR_MASK
13943. D3F3_DEVICE_STATUS__AUX_PWR__SHIFT
13944. D3F3_DEVICE_STATUS__CORR_ERR_MASK
13945. D3F3_DEVICE_STATUS__CORR_ERR__SHIFT
13946. D3F3_DEVICE_STATUS__FATAL_ERR_MASK
13947. D3F3_DEVICE_STATUS__FATAL_ERR__SHIFT
13948. D3F3_DEVICE_STATUS__NON_FATAL_ERR_MASK
13949. D3F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
13950. D3F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
13951. D3F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
13952. D3F3_DEVICE_STATUS__USR_DETECTED_MASK
13953. D3F3_DEVICE_STATUS__USR_DETECTED__SHIFT
13954. D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
13955. D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
13956. D3F3_HEADER__DEVICE_TYPE_MASK
13957. D3F3_HEADER__DEVICE_TYPE__SHIFT
13958. D3F3_HEADER__HEADER_TYPE_MASK
13959. D3F3_HEADER__HEADER_TYPE__SHIFT
13960. D3F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK
13961. D3F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
13962. D3F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK
13963. D3F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
13964. D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
13965. D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
13966. D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
13967. D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
13968. D3F3_IO_BASE_LIMIT__IO_BASE_MASK
13969. D3F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
13970. D3F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
13971. D3F3_IO_BASE_LIMIT__IO_BASE__SHIFT
13972. D3F3_IO_BASE_LIMIT__IO_LIMIT_MASK
13973. D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
13974. D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
13975. D3F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT
13976. D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
13977. D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
13978. D3F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK
13979. D3F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
13980. D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
13981. D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
13982. D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
13983. D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
13984. D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
13985. D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
13986. D3F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK
13987. D3F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
13988. D3F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
13989. D3F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
13990. D3F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK
13991. D3F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
13992. D3F3_LATENCY__LATENCY_TIMER_MASK
13993. D3F3_LATENCY__LATENCY_TIMER__SHIFT
13994. D3F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
13995. D3F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
13996. D3F3_LINK_CAP2__RESERVED_MASK
13997. D3F3_LINK_CAP2__RESERVED__SHIFT
13998. D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
13999. D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
14000. D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
14001. D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
14002. D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
14003. D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
14004. D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
14005. D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
14006. D3F3_LINK_CAP__L0S_EXIT_LATENCY_MASK
14007. D3F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
14008. D3F3_LINK_CAP__L1_EXIT_LATENCY_MASK
14009. D3F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT
14010. D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
14011. D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
14012. D3F3_LINK_CAP__LINK_SPEED_MASK
14013. D3F3_LINK_CAP__LINK_SPEED__SHIFT
14014. D3F3_LINK_CAP__LINK_WIDTH_MASK
14015. D3F3_LINK_CAP__LINK_WIDTH__SHIFT
14016. D3F3_LINK_CAP__PM_SUPPORT_MASK
14017. D3F3_LINK_CAP__PM_SUPPORT__SHIFT
14018. D3F3_LINK_CAP__PORT_NUMBER_MASK
14019. D3F3_LINK_CAP__PORT_NUMBER__SHIFT
14020. D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
14021. D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
14022. D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
14023. D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
14024. D3F3_LINK_CNTL2__COMPLIANCE_SOS_MASK
14025. D3F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
14026. D3F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK
14027. D3F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
14028. D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
14029. D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
14030. D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
14031. D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
14032. D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
14033. D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
14034. D3F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK
14035. D3F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
14036. D3F3_LINK_CNTL2__XMIT_MARGIN_MASK
14037. D3F3_LINK_CNTL2__XMIT_MARGIN__SHIFT
14038. D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
14039. D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
14040. D3F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK
14041. D3F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
14042. D3F3_LINK_CNTL__EXTENDED_SYNC_MASK
14043. D3F3_LINK_CNTL__EXTENDED_SYNC__SHIFT
14044. D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
14045. D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
14046. D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
14047. D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
14048. D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
14049. D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
14050. D3F3_LINK_CNTL__LINK_DIS_MASK
14051. D3F3_LINK_CNTL__LINK_DIS__SHIFT
14052. D3F3_LINK_CNTL__PM_CONTROL_MASK
14053. D3F3_LINK_CNTL__PM_CONTROL__SHIFT
14054. D3F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK
14055. D3F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
14056. D3F3_LINK_CNTL__RETRAIN_LINK_MASK
14057. D3F3_LINK_CNTL__RETRAIN_LINK__SHIFT
14058. D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
14059. D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
14060. D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
14061. D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
14062. D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
14063. D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
14064. D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
14065. D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
14066. D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
14067. D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
14068. D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
14069. D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
14070. D3F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK
14071. D3F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
14072. D3F3_LINK_STATUS__DL_ACTIVE_MASK
14073. D3F3_LINK_STATUS__DL_ACTIVE__SHIFT
14074. D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
14075. D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
14076. D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
14077. D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
14078. D3F3_LINK_STATUS__LINK_TRAINING_MASK
14079. D3F3_LINK_STATUS__LINK_TRAINING__SHIFT
14080. D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
14081. D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
14082. D3F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK
14083. D3F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
14084. D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
14085. D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
14086. D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
14087. D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
14088. D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
14089. D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
14090. D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
14091. D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
14092. D3F3_MSI_CAP_LIST__CAP_ID_MASK
14093. D3F3_MSI_CAP_LIST__CAP_ID__SHIFT
14094. D3F3_MSI_CAP_LIST__NEXT_PTR_MASK
14095. D3F3_MSI_CAP_LIST__NEXT_PTR__SHIFT
14096. D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
14097. D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
14098. D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
14099. D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
14100. D3F3_MSI_MAP_CAP_LIST__CAP_ID_MASK
14101. D3F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
14102. D3F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
14103. D3F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
14104. D3F3_MSI_MAP_CAP__CAP_TYPE_MASK
14105. D3F3_MSI_MAP_CAP__CAP_TYPE__SHIFT
14106. D3F3_MSI_MAP_CAP__EN_MASK
14107. D3F3_MSI_MAP_CAP__EN__SHIFT
14108. D3F3_MSI_MAP_CAP__FIXD_MASK
14109. D3F3_MSI_MAP_CAP__FIXD__SHIFT
14110. D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
14111. D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
14112. D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
14113. D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
14114. D3F3_MSI_MSG_CNTL__MSI_64BIT_MASK
14115. D3F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT
14116. D3F3_MSI_MSG_CNTL__MSI_EN_MASK
14117. D3F3_MSI_MSG_CNTL__MSI_EN__SHIFT
14118. D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
14119. D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
14120. D3F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
14121. D3F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
14122. D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
14123. D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
14124. D3F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK
14125. D3F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
14126. D3F3_MSI_MSG_DATA__MSI_DATA_MASK
14127. D3F3_MSI_MSG_DATA__MSI_DATA__SHIFT
14128. D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
14129. D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
14130. D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
14131. D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
14132. D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
14133. D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
14134. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
14135. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
14136. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
14137. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
14138. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
14139. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
14140. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
14141. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
14142. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
14143. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
14144. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
14145. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
14146. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
14147. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
14148. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
14149. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
14150. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
14151. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
14152. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
14153. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
14154. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
14155. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
14156. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
14157. D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
14158. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
14159. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
14160. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
14161. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
14162. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
14163. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
14164. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
14165. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
14166. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
14167. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
14168. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
14169. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
14170. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
14171. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
14172. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
14173. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
14174. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
14175. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
14176. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
14177. D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
14178. D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
14179. D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
14180. D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
14181. D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
14182. D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
14183. D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
14184. D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
14185. D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
14186. D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
14187. D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
14188. D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
14189. D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
14190. D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
14191. D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
14192. D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
14193. D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
14194. D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
14195. D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
14196. D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
14197. D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
14198. D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
14199. D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
14200. D3F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK
14201. D3F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
14202. D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
14203. D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
14204. D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
14205. D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
14206. D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
14207. D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
14208. D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
14209. D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
14210. D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
14211. D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
14212. D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
14213. D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
14214. D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
14215. D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
14216. D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
14217. D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
14218. D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
14219. D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
14220. D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
14221. D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
14222. D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
14223. D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
14224. D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
14225. D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
14226. D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
14227. D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
14228. D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
14229. D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
14230. D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
14231. D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
14232. D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
14233. D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
14234. D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
14235. D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
14236. D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
14237. D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
14238. D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
14239. D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
14240. D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
14241. D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
14242. D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
14243. D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
14244. D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
14245. D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
14246. D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
14247. D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
14248. D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
14249. D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
14250. D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
14251. D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
14252. D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
14253. D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
14254. D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
14255. D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
14256. D3F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK
14257. D3F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
14258. D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
14259. D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
14260. D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
14261. D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
14262. D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
14263. D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
14264. D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
14265. D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
14266. D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
14267. D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
14268. D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
14269. D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
14270. D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
14271. D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
14272. D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
14273. D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
14274. D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
14275. D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
14276. D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
14277. D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
14278. D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
14279. D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
14280. D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
14281. D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
14282. D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
14283. D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
14284. D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
14285. D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
14286. D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
14287. D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
14288. D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
14289. D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
14290. D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
14291. D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
14292. D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
14293. D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
14294. D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
14295. D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
14296. D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
14297. D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
14298. D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
14299. D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
14300. D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
14301. D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
14302. D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
14303. D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
14304. D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
14305. D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
14306. D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
14307. D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
14308. D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
14309. D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
14310. D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
14311. D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
14312. D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
14313. D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
14314. D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
14315. D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
14316. D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
14317. D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
14318. D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
14319. D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
14320. D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
14321. D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
14322. D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
14323. D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
14324. D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
14325. D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
14326. D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
14327. D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
14328. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
14329. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
14330. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
14331. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
14332. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
14333. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
14334. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
14335. D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
14336. D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
14337. D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
14338. D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
14339. D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
14340. D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
14341. D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
14342. D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
14343. D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
14344. D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
14345. D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
14346. D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
14347. D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
14348. D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
14349. D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
14350. D3F3_PCIE_CAP_LIST__CAP_ID_MASK
14351. D3F3_PCIE_CAP_LIST__CAP_ID__SHIFT
14352. D3F3_PCIE_CAP_LIST__NEXT_PTR_MASK
14353. D3F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT
14354. D3F3_PCIE_CAP__DEVICE_TYPE_MASK
14355. D3F3_PCIE_CAP__DEVICE_TYPE__SHIFT
14356. D3F3_PCIE_CAP__INT_MESSAGE_NUM_MASK
14357. D3F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
14358. D3F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK
14359. D3F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
14360. D3F3_PCIE_CAP__VERSION_MASK
14361. D3F3_PCIE_CAP__VERSION__SHIFT
14362. D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
14363. D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
14364. D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
14365. D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
14366. D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
14367. D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
14368. D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
14369. D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
14370. D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
14371. D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
14372. D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
14373. D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
14374. D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
14375. D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
14376. D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
14377. D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
14378. D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
14379. D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
14380. D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
14381. D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
14382. D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
14383. D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
14384. D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
14385. D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
14386. D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
14387. D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
14388. D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
14389. D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
14390. D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
14391. D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
14392. D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
14393. D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
14394. D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
14395. D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
14396. D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
14397. D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
14398. D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
14399. D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
14400. D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
14401. D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
14402. D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
14403. D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
14404. D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
14405. D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
14406. D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
14407. D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
14408. D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
14409. D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
14410. D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
14411. D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
14412. D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
14413. D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
14414. D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
14415. D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
14416. D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
14417. D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
14418. D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
14419. D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
14420. D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
14421. D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
14422. D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
14423. D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
14424. D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
14425. D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
14426. D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
14427. D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
14428. D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
14429. D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
14430. D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
14431. D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
14432. D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
14433. D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
14434. D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
14435. D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
14436. D3F3_PCIE_FC_CPL__CPLD_CREDITS_MASK
14437. D3F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
14438. D3F3_PCIE_FC_CPL__CPLH_CREDITS_MASK
14439. D3F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
14440. D3F3_PCIE_FC_NP__NPD_CREDITS_MASK
14441. D3F3_PCIE_FC_NP__NPD_CREDITS__SHIFT
14442. D3F3_PCIE_FC_NP__NPH_CREDITS_MASK
14443. D3F3_PCIE_FC_NP__NPH_CREDITS__SHIFT
14444. D3F3_PCIE_FC_P__PD_CREDITS_MASK
14445. D3F3_PCIE_FC_P__PD_CREDITS__SHIFT
14446. D3F3_PCIE_FC_P__PH_CREDITS_MASK
14447. D3F3_PCIE_FC_P__PH_CREDITS__SHIFT
14448. D3F3_PCIE_HDR_LOG0__TLP_HDR_MASK
14449. D3F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT
14450. D3F3_PCIE_HDR_LOG1__TLP_HDR_MASK
14451. D3F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT
14452. D3F3_PCIE_HDR_LOG2__TLP_HDR_MASK
14453. D3F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT
14454. D3F3_PCIE_HDR_LOG3__TLP_HDR_MASK
14455. D3F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT
14456. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14457. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14458. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14459. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14460. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
14461. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
14462. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14463. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14464. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14465. D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14466. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14467. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14468. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14469. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14470. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
14471. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
14472. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14473. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14474. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14475. D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14476. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14477. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14478. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14479. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14480. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
14481. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
14482. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14483. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14484. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14485. D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14486. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14487. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14488. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14489. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14490. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
14491. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
14492. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14493. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14494. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14495. D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14496. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14497. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14498. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14499. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14500. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
14501. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
14502. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14503. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14504. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14505. D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14506. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14507. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14508. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14509. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14510. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
14511. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
14512. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14513. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14514. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14515. D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14516. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14517. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14518. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14519. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14520. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
14521. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
14522. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14523. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14524. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14525. D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14526. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14527. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14528. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14529. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14530. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
14531. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
14532. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14533. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14534. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14535. D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14536. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14537. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14538. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14539. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14540. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
14541. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
14542. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14543. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14544. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14545. D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14546. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14547. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14548. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14549. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14550. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
14551. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
14552. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14553. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14554. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14555. D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14556. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14557. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14558. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14559. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14560. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
14561. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
14562. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14563. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14564. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14565. D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14566. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14567. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14568. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14569. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14570. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
14571. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
14572. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14573. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14574. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14575. D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14576. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14577. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14578. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14579. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14580. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
14581. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
14582. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14583. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14584. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14585. D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14586. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14587. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14588. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14589. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14590. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
14591. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
14592. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14593. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14594. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14595. D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14596. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14597. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14598. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14599. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14600. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
14601. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
14602. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14603. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14604. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14605. D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14606. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
14607. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
14608. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
14609. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
14610. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
14611. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
14612. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
14613. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
14614. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
14615. D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
14616. D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
14617. D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
14618. D3F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
14619. D3F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
14620. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
14621. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
14622. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
14623. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
14624. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
14625. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
14626. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
14627. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
14628. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
14629. D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
14630. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
14631. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
14632. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
14633. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
14634. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
14635. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
14636. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
14637. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
14638. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
14639. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
14640. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
14641. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
14642. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
14643. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
14644. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
14645. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
14646. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
14647. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
14648. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
14649. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
14650. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
14651. D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
14652. D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
14653. D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
14654. D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
14655. D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
14656. D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
14657. D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
14658. D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
14659. D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
14660. D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
14661. D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
14662. D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
14663. D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
14664. D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
14665. D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
14666. D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
14667. D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
14668. D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
14669. D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
14670. D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
14671. D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
14672. D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
14673. D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
14674. D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
14675. D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
14676. D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
14677. D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
14678. D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
14679. D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
14680. D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
14681. D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
14682. D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
14683. D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
14684. D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
14685. D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
14686. D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
14687. D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
14688. D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
14689. D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
14690. D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
14691. D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
14692. D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
14693. D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
14694. D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
14695. D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
14696. D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
14697. D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
14698. D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
14699. D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
14700. D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
14701. D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
14702. D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
14703. D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
14704. D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
14705. D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
14706. D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
14707. D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
14708. D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
14709. D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
14710. D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
14711. D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
14712. D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
14713. D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
14714. D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
14715. D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
14716. D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
14717. D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
14718. D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
14719. D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
14720. D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
14721. D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
14722. D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
14723. D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
14724. D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
14725. D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
14726. D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
14727. D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
14728. D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
14729. D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
14730. D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
14731. D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
14732. D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
14733. D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
14734. D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
14735. D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
14736. D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
14737. D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
14738. D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
14739. D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
14740. D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
14741. D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
14742. D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
14743. D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
14744. D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
14745. D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
14746. D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
14747. D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
14748. D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
14749. D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
14750. D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
14751. D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
14752. D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
14753. D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
14754. D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
14755. D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
14756. D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
14757. D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
14758. D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
14759. D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
14760. D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
14761. D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
14762. D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
14763. D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
14764. D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
14765. D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
14766. D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
14767. D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
14768. D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
14769. D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
14770. D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
14771. D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
14772. D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
14773. D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
14774. D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
14775. D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
14776. D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
14777. D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
14778. D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
14779. D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
14780. D3F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
14781. D3F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
14782. D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
14783. D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
14784. D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
14785. D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
14786. D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
14787. D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
14788. D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
14789. D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
14790. D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
14791. D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
14792. D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
14793. D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
14794. D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
14795. D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
14796. D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
14797. D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
14798. D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
14799. D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
14800. D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
14801. D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
14802. D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
14803. D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
14804. D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
14805. D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
14806. D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
14807. D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
14808. D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
14809. D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
14810. D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
14811. D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
14812. D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
14813. D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
14814. D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
14815. D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
14816. D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
14817. D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
14818. D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
14819. D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
14820. D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
14821. D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
14822. D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
14823. D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
14824. D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
14825. D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
14826. D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
14827. D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
14828. D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
14829. D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
14830. D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
14831. D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
14832. D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
14833. D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
14834. D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
14835. D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
14836. D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
14837. D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
14838. D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
14839. D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
14840. D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
14841. D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
14842. D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
14843. D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
14844. D3F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK
14845. D3F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
14846. D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
14847. D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
14848. D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
14849. D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
14850. D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
14851. D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
14852. D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
14853. D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
14854. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
14855. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
14856. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
14857. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
14858. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
14859. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
14860. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
14861. D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
14862. D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
14863. D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
14864. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
14865. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
14866. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
14867. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
14868. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
14869. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
14870. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
14871. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
14872. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
14873. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
14874. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
14875. D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
14876. D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
14877. D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
14878. D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
14879. D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
14880. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
14881. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
14882. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
14883. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
14884. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
14885. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
14886. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
14887. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
14888. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
14889. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
14890. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
14891. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
14892. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
14893. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
14894. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
14895. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
14896. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
14897. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
14898. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
14899. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
14900. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
14901. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
14902. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
14903. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
14904. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
14905. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
14906. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
14907. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
14908. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
14909. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
14910. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
14911. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
14912. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
14913. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
14914. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
14915. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
14916. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
14917. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
14918. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
14919. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
14920. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
14921. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
14922. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
14923. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
14924. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
14925. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
14926. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
14927. D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
14928. D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
14929. D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
14930. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
14931. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
14932. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
14933. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
14934. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
14935. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
14936. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
14937. D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
14938. D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
14939. D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
14940. D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
14941. D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
14942. D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
14943. D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
14944. D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
14945. D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
14946. D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
14947. D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
14948. D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
14949. D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
14950. D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
14951. D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
14952. D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
14953. D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
14954. D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
14955. D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
14956. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
14957. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
14958. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
14959. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
14960. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
14961. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
14962. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
14963. D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
14964. D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
14965. D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
14966. D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
14967. D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
14968. D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
14969. D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
14970. D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
14971. D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
14972. D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
14973. D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
14974. D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
14975. D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
14976. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
14977. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
14978. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
14979. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
14980. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
14981. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
14982. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
14983. D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
14984. D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
14985. D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
14986. D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
14987. D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
14988. D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
14989. D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
14990. D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
14991. D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
14992. D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
14993. D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
14994. D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
14995. D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
14996. D3F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
14997. D3F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
14998. D3F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
14999. D3F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
15000. D3F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
15001. D3F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
15002. D3F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
15003. D3F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
15004. D3F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
15005. D3F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
15006. D3F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
15007. D3F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
15008. D3F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
15009. D3F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
15010. D3F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
15011. D3F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
15012. D3F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
15013. D3F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
15014. D3F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
15015. D3F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
15016. D3F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
15017. D3F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
15018. D3F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
15019. D3F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
15020. D3F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
15021. D3F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
15022. D3F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
15023. D3F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
15024. D3F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
15025. D3F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
15026. D3F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
15027. D3F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
15028. D3F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
15029. D3F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
15030. D3F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
15031. D3F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
15032. D3F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
15033. D3F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
15034. D3F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
15035. D3F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
15036. D3F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
15037. D3F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
15038. D3F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
15039. D3F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
15040. D3F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
15041. D3F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
15042. D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
15043. D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
15044. D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
15045. D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
15046. D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
15047. D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
15048. D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
15049. D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
15050. D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
15051. D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
15052. D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
15053. D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
15054. D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
15055. D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
15056. D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
15057. D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
15058. D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
15059. D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
15060. D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
15061. D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
15062. D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
15063. D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
15064. D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
15065. D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
15066. D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
15067. D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
15068. D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
15069. D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
15070. D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
15071. D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
15072. D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
15073. D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
15074. D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
15075. D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
15076. D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
15077. D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
15078. D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
15079. D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
15080. D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
15081. D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
15082. D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
15083. D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
15084. D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
15085. D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
15086. D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
15087. D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
15088. D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
15089. D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
15090. D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
15091. D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
15092. D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
15093. D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
15094. D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
15095. D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
15096. D3F3_PCIE_LINK_CNTL3__RESERVED_MASK
15097. D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT
15098. D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
15099. D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
15100. D3F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
15101. D3F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
15102. D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
15103. D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
15104. D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
15105. D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
15106. D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
15107. D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
15108. D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
15109. D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
15110. D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
15111. D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
15112. D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
15113. D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
15114. D3F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK
15115. D3F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
15116. D3F3_PCIE_MC_CNTL__MC_ENABLE_MASK
15117. D3F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT
15118. D3F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
15119. D3F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
15120. D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
15121. D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
15122. D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
15123. D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
15124. D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
15125. D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
15126. D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
15127. D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
15128. D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
15129. D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
15130. D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
15131. D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
15132. D3F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
15133. D3F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
15134. D3F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
15135. D3F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
15136. D3F3_PCIE_PORT_DATA__PCIE_DATA_MASK
15137. D3F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT
15138. D3F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK
15139. D3F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
15140. D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
15141. D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
15142. D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
15143. D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
15144. D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
15145. D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
15146. D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
15147. D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
15148. D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
15149. D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
15150. D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
15151. D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
15152. D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
15153. D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
15154. D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
15155. D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
15156. D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
15157. D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
15158. D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
15159. D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
15160. D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
15161. D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
15162. D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
15163. D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
15164. D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
15165. D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
15166. D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
15167. D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
15168. D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
15169. D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
15170. D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
15171. D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
15172. D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
15173. D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
15174. D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
15175. D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
15176. D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
15177. D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
15178. D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
15179. D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
15180. D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
15181. D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
15182. D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
15183. D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
15184. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
15185. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
15186. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
15187. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
15188. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
15189. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
15190. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
15191. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
15192. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
15193. D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
15194. D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
15195. D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
15196. D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
15197. D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
15198. D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
15199. D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
15200. D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
15201. D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
15202. D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
15203. D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
15204. D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
15205. D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
15206. D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
15207. D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
15208. D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
15209. D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
15210. D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
15211. D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
15212. D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
15213. D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
15214. D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
15215. D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
15216. D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
15217. D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
15218. D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
15219. D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
15220. D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
15221. D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
15222. D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
15223. D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
15224. D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
15225. D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
15226. D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
15227. D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
15228. D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
15229. D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
15230. D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
15231. D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
15232. D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
15233. D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
15234. D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
15235. D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
15236. D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
15237. D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
15238. D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
15239. D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
15240. D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
15241. D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
15242. D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
15243. D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
15244. D3F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK
15245. D3F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
15246. D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
15247. D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
15248. D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
15249. D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
15250. D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
15251. D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
15252. D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
15253. D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
15254. D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
15255. D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
15256. D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
15257. D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
15258. D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
15259. D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
15260. D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
15261. D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
15262. D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
15263. D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
15264. D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
15265. D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
15266. D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
15267. D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
15268. D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
15269. D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
15270. D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
15271. D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
15272. D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
15273. D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
15274. D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
15275. D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
15276. D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
15277. D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
15278. D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
15279. D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
15280. D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
15281. D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
15282. D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
15283. D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
15284. D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
15285. D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
15286. D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
15287. D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
15288. D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
15289. D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
15290. D3F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
15291. D3F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
15292. D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
15293. D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
15294. D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
15295. D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
15296. D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
15297. D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
15298. D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
15299. D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
15300. D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
15301. D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
15302. D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
15303. D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
15304. D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
15305. D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
15306. D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
15307. D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
15308. D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
15309. D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
15310. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
15311. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
15312. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
15313. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
15314. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
15315. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
15316. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
15317. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
15318. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
15319. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
15320. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
15321. D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
15322. D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
15323. D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
15324. D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
15325. D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
15326. D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
15327. D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
15328. D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
15329. D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
15330. D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
15331. D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
15332. D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
15333. D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
15334. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
15335. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
15336. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
15337. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
15338. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
15339. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
15340. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
15341. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
15342. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
15343. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
15344. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
15345. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
15346. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
15347. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
15348. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
15349. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
15350. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
15351. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
15352. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
15353. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
15354. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
15355. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
15356. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
15357. D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
15358. D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
15359. D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
15360. D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
15361. D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
15362. D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
15363. D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
15364. D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
15365. D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
15366. D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
15367. D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
15368. D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
15369. D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
15370. D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
15371. D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
15372. D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
15373. D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
15374. D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
15375. D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
15376. D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
15377. D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
15378. D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
15379. D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
15380. D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
15381. D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
15382. D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
15383. D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
15384. D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
15385. D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
15386. D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
15387. D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
15388. D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
15389. D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
15390. D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
15391. D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
15392. D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
15393. D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
15394. D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
15395. D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
15396. D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
15397. D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
15398. D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
15399. D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
15400. D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
15401. D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
15402. D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
15403. D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
15404. D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
15405. D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
15406. D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
15407. D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
15408. D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
15409. D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
15410. D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
15411. D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
15412. D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
15413. D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
15414. D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
15415. D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
15416. D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
15417. D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
15418. D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
15419. D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
15420. D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
15421. D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
15422. D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
15423. D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
15424. D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
15425. D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
15426. D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
15427. D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
15428. D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
15429. D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
15430. D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
15431. D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
15432. D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
15433. D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
15434. D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
15435. D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
15436. D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
15437. D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
15438. D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
15439. D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
15440. D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
15441. D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
15442. D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
15443. D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
15444. D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
15445. D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
15446. D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
15447. D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
15448. D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
15449. D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
15450. D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
15451. D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
15452. D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
15453. D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
15454. D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
15455. D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
15456. D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
15457. D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
15458. D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
15459. D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
15460. D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
15461. D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
15462. D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
15463. D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
15464. D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
15465. D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
15466. D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
15467. D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
15468. D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
15469. D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
15470. D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
15471. D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
15472. D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
15473. D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
15474. D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
15475. D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
15476. D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
15477. D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
15478. D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
15479. D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
15480. D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
15481. D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
15482. D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
15483. D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
15484. D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
15485. D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
15486. D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
15487. D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
15488. D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
15489. D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
15490. D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
15491. D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
15492. D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
15493. D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
15494. D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
15495. D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
15496. D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
15497. D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
15498. D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
15499. D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
15500. D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
15501. D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
15502. D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
15503. D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
15504. D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
15505. D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
15506. D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
15507. D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
15508. D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
15509. D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
15510. D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
15511. D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
15512. D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
15513. D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
15514. D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
15515. D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
15516. D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
15517. D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
15518. D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
15519. D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
15520. D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
15521. D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
15522. D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
15523. D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
15524. D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
15525. D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
15526. D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
15527. D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
15528. D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
15529. D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
15530. D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
15531. D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
15532. D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
15533. D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
15534. D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
15535. D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
15536. D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
15537. D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
15538. D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
15539. D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
15540. D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
15541. D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
15542. D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
15543. D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
15544. D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
15545. D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
15546. D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
15547. D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
15548. D3F3_PMI_CAP_LIST__CAP_ID_MASK
15549. D3F3_PMI_CAP_LIST__CAP_ID__SHIFT
15550. D3F3_PMI_CAP_LIST__NEXT_PTR_MASK
15551. D3F3_PMI_CAP_LIST__NEXT_PTR__SHIFT
15552. D3F3_PMI_CAP__AUX_CURRENT_MASK
15553. D3F3_PMI_CAP__AUX_CURRENT__SHIFT
15554. D3F3_PMI_CAP__D1_SUPPORT_MASK
15555. D3F3_PMI_CAP__D1_SUPPORT__SHIFT
15556. D3F3_PMI_CAP__D2_SUPPORT_MASK
15557. D3F3_PMI_CAP__D2_SUPPORT__SHIFT
15558. D3F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK
15559. D3F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
15560. D3F3_PMI_CAP__PME_CLOCK_MASK
15561. D3F3_PMI_CAP__PME_CLOCK__SHIFT
15562. D3F3_PMI_CAP__PME_SUPPORT_MASK
15563. D3F3_PMI_CAP__PME_SUPPORT__SHIFT
15564. D3F3_PMI_CAP__VERSION_MASK
15565. D3F3_PMI_CAP__VERSION__SHIFT
15566. D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
15567. D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
15568. D3F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
15569. D3F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
15570. D3F3_PMI_STATUS_CNTL__DATA_SCALE_MASK
15571. D3F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
15572. D3F3_PMI_STATUS_CNTL__DATA_SELECT_MASK
15573. D3F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
15574. D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
15575. D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
15576. D3F3_PMI_STATUS_CNTL__PME_EN_MASK
15577. D3F3_PMI_STATUS_CNTL__PME_EN__SHIFT
15578. D3F3_PMI_STATUS_CNTL__PME_STATUS_MASK
15579. D3F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT
15580. D3F3_PMI_STATUS_CNTL__PMI_DATA_MASK
15581. D3F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT
15582. D3F3_PMI_STATUS_CNTL__POWER_STATE_MASK
15583. D3F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT
15584. D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
15585. D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
15586. D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
15587. D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
15588. D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
15589. D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
15590. D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
15591. D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
15592. D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
15593. D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
15594. D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
15595. D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
15596. D3F3_PROG_INTERFACE__PROG_INTERFACE_MASK
15597. D3F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT
15598. D3F3_REVISION_ID__MAJOR_REV_ID_MASK
15599. D3F3_REVISION_ID__MAJOR_REV_ID__SHIFT
15600. D3F3_REVISION_ID__MINOR_REV_ID_MASK
15601. D3F3_REVISION_ID__MINOR_REV_ID__SHIFT
15602. D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
15603. D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
15604. D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
15605. D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
15606. D3F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK
15607. D3F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
15608. D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
15609. D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
15610. D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
15611. D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
15612. D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
15613. D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
15614. D3F3_ROOT_STATUS__PME_PENDING_MASK
15615. D3F3_ROOT_STATUS__PME_PENDING__SHIFT
15616. D3F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK
15617. D3F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
15618. D3F3_ROOT_STATUS__PME_STATUS_MASK
15619. D3F3_ROOT_STATUS__PME_STATUS__SHIFT
15620. D3F3_SECONDARY_STATUS__CAP_LIST_MASK
15621. D3F3_SECONDARY_STATUS__CAP_LIST__SHIFT
15622. D3F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK
15623. D3F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
15624. D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
15625. D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
15626. D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
15627. D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
15628. D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
15629. D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
15630. D3F3_SECONDARY_STATUS__PCI_66_EN_MASK
15631. D3F3_SECONDARY_STATUS__PCI_66_EN__SHIFT
15632. D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
15633. D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
15634. D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
15635. D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
15636. D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
15637. D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
15638. D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
15639. D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
15640. D3F3_SLOT_CAP2__RESERVED_MASK
15641. D3F3_SLOT_CAP2__RESERVED__SHIFT
15642. D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
15643. D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
15644. D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
15645. D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
15646. D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
15647. D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
15648. D3F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK
15649. D3F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
15650. D3F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK
15651. D3F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
15652. D3F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
15653. D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
15654. D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
15655. D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
15656. D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
15657. D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
15658. D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
15659. D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
15660. D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
15661. D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
15662. D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
15663. D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
15664. D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
15665. D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
15666. D3F3_SLOT_CNTL2__RESERVED_MASK
15667. D3F3_SLOT_CNTL2__RESERVED__SHIFT
15668. D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
15669. D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
15670. D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
15671. D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
15672. D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
15673. D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
15674. D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
15675. D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
15676. D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
15677. D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
15678. D3F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
15679. D3F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
15680. D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
15681. D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
15682. D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
15683. D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
15684. D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
15685. D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
15686. D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
15687. D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
15688. D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
15689. D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
15690. D3F3_SLOT_STATUS2__RESERVED_MASK
15691. D3F3_SLOT_STATUS2__RESERVED__SHIFT
15692. D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
15693. D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
15694. D3F3_SLOT_STATUS__COMMAND_COMPLETED_MASK
15695. D3F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
15696. D3F3_SLOT_STATUS__DL_STATE_CHANGED_MASK
15697. D3F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
15698. D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
15699. D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
15700. D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
15701. D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
15702. D3F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK
15703. D3F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
15704. D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
15705. D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
15706. D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
15707. D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
15708. D3F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
15709. D3F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
15710. D3F3_SSID_CAP_LIST__CAP_ID_MASK
15711. D3F3_SSID_CAP_LIST__CAP_ID__SHIFT
15712. D3F3_SSID_CAP_LIST__NEXT_PTR_MASK
15713. D3F3_SSID_CAP_LIST__NEXT_PTR__SHIFT
15714. D3F3_SSID_CAP__SUBSYSTEM_ID_MASK
15715. D3F3_SSID_CAP__SUBSYSTEM_ID__SHIFT
15716. D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
15717. D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
15718. D3F3_STATUS__CAP_LIST_MASK
15719. D3F3_STATUS__CAP_LIST__SHIFT
15720. D3F3_STATUS__DEVSEL_TIMING_MASK
15721. D3F3_STATUS__DEVSEL_TIMING__SHIFT
15722. D3F3_STATUS__FAST_BACK_CAPABLE_MASK
15723. D3F3_STATUS__FAST_BACK_CAPABLE__SHIFT
15724. D3F3_STATUS__INT_STATUS_MASK
15725. D3F3_STATUS__INT_STATUS__SHIFT
15726. D3F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK
15727. D3F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
15728. D3F3_STATUS__PARITY_ERROR_DETECTED_MASK
15729. D3F3_STATUS__PARITY_ERROR_DETECTED__SHIFT
15730. D3F3_STATUS__PCI_66_EN_MASK
15731. D3F3_STATUS__PCI_66_EN__SHIFT
15732. D3F3_STATUS__RECEIVED_MASTER_ABORT_MASK
15733. D3F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT
15734. D3F3_STATUS__RECEIVED_TARGET_ABORT_MASK
15735. D3F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT
15736. D3F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK
15737. D3F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
15738. D3F3_STATUS__SIGNAL_TARGET_ABORT_MASK
15739. D3F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT
15740. D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
15741. D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
15742. D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
15743. D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
15744. D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
15745. D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
15746. D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
15747. D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
15748. D3F3_SUB_CLASS__SUB_CLASS_MASK
15749. D3F3_SUB_CLASS__SUB_CLASS__SHIFT
15750. D3F3_VENDOR_ID__VENDOR_ID_MASK
15751. D3F3_VENDOR_ID__VENDOR_ID__SHIFT
15752. D3F4_BASE_CLASS__BASE_CLASS_MASK
15753. D3F4_BASE_CLASS__BASE_CLASS__SHIFT
15754. D3F4_BIST__BIST_CAP_MASK
15755. D3F4_BIST__BIST_CAP__SHIFT
15756. D3F4_BIST__BIST_COMP_MASK
15757. D3F4_BIST__BIST_COMP__SHIFT
15758. D3F4_BIST__BIST_STRT_MASK
15759. D3F4_BIST__BIST_STRT__SHIFT
15760. D3F4_CACHE_LINE__CACHE_LINE_SIZE_MASK
15761. D3F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
15762. D3F4_CAP_PTR__CAP_PTR_MASK
15763. D3F4_CAP_PTR__CAP_PTR__SHIFT
15764. D3F4_COMMAND__AD_STEPPING_MASK
15765. D3F4_COMMAND__AD_STEPPING__SHIFT
15766. D3F4_COMMAND__BUS_MASTER_EN_MASK
15767. D3F4_COMMAND__BUS_MASTER_EN__SHIFT
15768. D3F4_COMMAND__FAST_B2B_EN_MASK
15769. D3F4_COMMAND__FAST_B2B_EN__SHIFT
15770. D3F4_COMMAND__INT_DIS_MASK
15771. D3F4_COMMAND__INT_DIS__SHIFT
15772. D3F4_COMMAND__IO_ACCESS_EN_MASK
15773. D3F4_COMMAND__IO_ACCESS_EN__SHIFT
15774. D3F4_COMMAND__MEM_ACCESS_EN_MASK
15775. D3F4_COMMAND__MEM_ACCESS_EN__SHIFT
15776. D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
15777. D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
15778. D3F4_COMMAND__PAL_SNOOP_EN_MASK
15779. D3F4_COMMAND__PAL_SNOOP_EN__SHIFT
15780. D3F4_COMMAND__PARITY_ERROR_RESPONSE_MASK
15781. D3F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
15782. D3F4_COMMAND__SERR_EN_MASK
15783. D3F4_COMMAND__SERR_EN__SHIFT
15784. D3F4_COMMAND__SPECIAL_CYCLE_EN_MASK
15785. D3F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT
15786. D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
15787. D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
15788. D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
15789. D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
15790. D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
15791. D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
15792. D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
15793. D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
15794. D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
15795. D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
15796. D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
15797. D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
15798. D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
15799. D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
15800. D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
15801. D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
15802. D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
15803. D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
15804. D3F4_DEVICE_CAP2__LTR_SUPPORTED_MASK
15805. D3F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
15806. D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
15807. D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
15808. D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
15809. D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
15810. D3F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK
15811. D3F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
15812. D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
15813. D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
15814. D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
15815. D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
15816. D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
15817. D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
15818. D3F4_DEVICE_CAP__EXTENDED_TAG_MASK
15819. D3F4_DEVICE_CAP__EXTENDED_TAG__SHIFT
15820. D3F4_DEVICE_CAP__FLR_CAPABLE_MASK
15821. D3F4_DEVICE_CAP__FLR_CAPABLE__SHIFT
15822. D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
15823. D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
15824. D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
15825. D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
15826. D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
15827. D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
15828. D3F4_DEVICE_CAP__PHANTOM_FUNC_MASK
15829. D3F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT
15830. D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
15831. D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
15832. D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
15833. D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
15834. D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
15835. D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
15836. D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
15837. D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
15838. D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
15839. D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
15840. D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
15841. D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
15842. D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
15843. D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
15844. D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
15845. D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
15846. D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
15847. D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
15848. D3F4_DEVICE_CNTL2__LTR_EN_MASK
15849. D3F4_DEVICE_CNTL2__LTR_EN__SHIFT
15850. D3F4_DEVICE_CNTL2__OBFF_EN_MASK
15851. D3F4_DEVICE_CNTL2__OBFF_EN__SHIFT
15852. D3F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
15853. D3F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
15854. D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
15855. D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
15856. D3F4_DEVICE_CNTL__CORR_ERR_EN_MASK
15857. D3F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT
15858. D3F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
15859. D3F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
15860. D3F4_DEVICE_CNTL__FATAL_ERR_EN_MASK
15861. D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
15862. D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
15863. D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
15864. D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
15865. D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
15866. D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
15867. D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
15868. D3F4_DEVICE_CNTL__NO_SNOOP_EN_MASK
15869. D3F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
15870. D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
15871. D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
15872. D3F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK
15873. D3F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
15874. D3F4_DEVICE_CNTL__USR_REPORT_EN_MASK
15875. D3F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT
15876. D3F4_DEVICE_ID__DEVICE_ID_MASK
15877. D3F4_DEVICE_ID__DEVICE_ID__SHIFT
15878. D3F4_DEVICE_STATUS2__RESERVED_MASK
15879. D3F4_DEVICE_STATUS2__RESERVED__SHIFT
15880. D3F4_DEVICE_STATUS__AUX_PWR_MASK
15881. D3F4_DEVICE_STATUS__AUX_PWR__SHIFT
15882. D3F4_DEVICE_STATUS__CORR_ERR_MASK
15883. D3F4_DEVICE_STATUS__CORR_ERR__SHIFT
15884. D3F4_DEVICE_STATUS__FATAL_ERR_MASK
15885. D3F4_DEVICE_STATUS__FATAL_ERR__SHIFT
15886. D3F4_DEVICE_STATUS__NON_FATAL_ERR_MASK
15887. D3F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
15888. D3F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
15889. D3F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
15890. D3F4_DEVICE_STATUS__USR_DETECTED_MASK
15891. D3F4_DEVICE_STATUS__USR_DETECTED__SHIFT
15892. D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
15893. D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
15894. D3F4_HEADER__DEVICE_TYPE_MASK
15895. D3F4_HEADER__DEVICE_TYPE__SHIFT
15896. D3F4_HEADER__HEADER_TYPE_MASK
15897. D3F4_HEADER__HEADER_TYPE__SHIFT
15898. D3F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK
15899. D3F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
15900. D3F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK
15901. D3F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
15902. D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
15903. D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
15904. D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
15905. D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
15906. D3F4_IO_BASE_LIMIT__IO_BASE_MASK
15907. D3F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
15908. D3F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
15909. D3F4_IO_BASE_LIMIT__IO_BASE__SHIFT
15910. D3F4_IO_BASE_LIMIT__IO_LIMIT_MASK
15911. D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
15912. D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
15913. D3F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT
15914. D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
15915. D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
15916. D3F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK
15917. D3F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
15918. D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
15919. D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
15920. D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
15921. D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
15922. D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
15923. D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
15924. D3F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK
15925. D3F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
15926. D3F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
15927. D3F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
15928. D3F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK
15929. D3F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
15930. D3F4_LATENCY__LATENCY_TIMER_MASK
15931. D3F4_LATENCY__LATENCY_TIMER__SHIFT
15932. D3F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
15933. D3F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
15934. D3F4_LINK_CAP2__RESERVED_MASK
15935. D3F4_LINK_CAP2__RESERVED__SHIFT
15936. D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
15937. D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
15938. D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
15939. D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
15940. D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
15941. D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
15942. D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
15943. D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
15944. D3F4_LINK_CAP__L0S_EXIT_LATENCY_MASK
15945. D3F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
15946. D3F4_LINK_CAP__L1_EXIT_LATENCY_MASK
15947. D3F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT
15948. D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
15949. D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
15950. D3F4_LINK_CAP__LINK_SPEED_MASK
15951. D3F4_LINK_CAP__LINK_SPEED__SHIFT
15952. D3F4_LINK_CAP__LINK_WIDTH_MASK
15953. D3F4_LINK_CAP__LINK_WIDTH__SHIFT
15954. D3F4_LINK_CAP__PM_SUPPORT_MASK
15955. D3F4_LINK_CAP__PM_SUPPORT__SHIFT
15956. D3F4_LINK_CAP__PORT_NUMBER_MASK
15957. D3F4_LINK_CAP__PORT_NUMBER__SHIFT
15958. D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
15959. D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
15960. D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
15961. D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
15962. D3F4_LINK_CNTL2__COMPLIANCE_SOS_MASK
15963. D3F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
15964. D3F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK
15965. D3F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
15966. D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
15967. D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
15968. D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
15969. D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
15970. D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
15971. D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
15972. D3F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK
15973. D3F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
15974. D3F4_LINK_CNTL2__XMIT_MARGIN_MASK
15975. D3F4_LINK_CNTL2__XMIT_MARGIN__SHIFT
15976. D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
15977. D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
15978. D3F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK
15979. D3F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
15980. D3F4_LINK_CNTL__EXTENDED_SYNC_MASK
15981. D3F4_LINK_CNTL__EXTENDED_SYNC__SHIFT
15982. D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
15983. D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
15984. D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
15985. D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
15986. D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
15987. D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
15988. D3F4_LINK_CNTL__LINK_DIS_MASK
15989. D3F4_LINK_CNTL__LINK_DIS__SHIFT
15990. D3F4_LINK_CNTL__PM_CONTROL_MASK
15991. D3F4_LINK_CNTL__PM_CONTROL__SHIFT
15992. D3F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK
15993. D3F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
15994. D3F4_LINK_CNTL__RETRAIN_LINK_MASK
15995. D3F4_LINK_CNTL__RETRAIN_LINK__SHIFT
15996. D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
15997. D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
15998. D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
15999. D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
16000. D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
16001. D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
16002. D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
16003. D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
16004. D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
16005. D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
16006. D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
16007. D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
16008. D3F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK
16009. D3F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
16010. D3F4_LINK_STATUS__DL_ACTIVE_MASK
16011. D3F4_LINK_STATUS__DL_ACTIVE__SHIFT
16012. D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
16013. D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
16014. D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
16015. D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
16016. D3F4_LINK_STATUS__LINK_TRAINING_MASK
16017. D3F4_LINK_STATUS__LINK_TRAINING__SHIFT
16018. D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
16019. D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
16020. D3F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK
16021. D3F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
16022. D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
16023. D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
16024. D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
16025. D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
16026. D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
16027. D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
16028. D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
16029. D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
16030. D3F4_MSI_CAP_LIST__CAP_ID_MASK
16031. D3F4_MSI_CAP_LIST__CAP_ID__SHIFT
16032. D3F4_MSI_CAP_LIST__NEXT_PTR_MASK
16033. D3F4_MSI_CAP_LIST__NEXT_PTR__SHIFT
16034. D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
16035. D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
16036. D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
16037. D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
16038. D3F4_MSI_MAP_CAP_LIST__CAP_ID_MASK
16039. D3F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
16040. D3F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
16041. D3F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
16042. D3F4_MSI_MAP_CAP__CAP_TYPE_MASK
16043. D3F4_MSI_MAP_CAP__CAP_TYPE__SHIFT
16044. D3F4_MSI_MAP_CAP__EN_MASK
16045. D3F4_MSI_MAP_CAP__EN__SHIFT
16046. D3F4_MSI_MAP_CAP__FIXD_MASK
16047. D3F4_MSI_MAP_CAP__FIXD__SHIFT
16048. D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
16049. D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
16050. D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
16051. D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
16052. D3F4_MSI_MSG_CNTL__MSI_64BIT_MASK
16053. D3F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT
16054. D3F4_MSI_MSG_CNTL__MSI_EN_MASK
16055. D3F4_MSI_MSG_CNTL__MSI_EN__SHIFT
16056. D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
16057. D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
16058. D3F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
16059. D3F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
16060. D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
16061. D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
16062. D3F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK
16063. D3F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
16064. D3F4_MSI_MSG_DATA__MSI_DATA_MASK
16065. D3F4_MSI_MSG_DATA__MSI_DATA__SHIFT
16066. D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
16067. D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
16068. D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
16069. D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
16070. D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
16071. D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
16072. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
16073. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
16074. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
16075. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
16076. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
16077. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
16078. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
16079. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
16080. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
16081. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
16082. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
16083. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
16084. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
16085. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
16086. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
16087. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
16088. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
16089. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
16090. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
16091. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
16092. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
16093. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
16094. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
16095. D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
16096. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
16097. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
16098. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
16099. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
16100. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
16101. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
16102. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
16103. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
16104. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
16105. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
16106. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
16107. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
16108. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
16109. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
16110. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
16111. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
16112. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
16113. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
16114. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
16115. D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
16116. D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
16117. D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
16118. D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
16119. D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
16120. D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
16121. D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
16122. D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
16123. D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
16124. D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
16125. D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
16126. D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
16127. D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
16128. D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
16129. D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
16130. D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
16131. D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
16132. D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
16133. D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
16134. D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
16135. D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
16136. D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
16137. D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
16138. D3F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK
16139. D3F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
16140. D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
16141. D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
16142. D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
16143. D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
16144. D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
16145. D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
16146. D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
16147. D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
16148. D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
16149. D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
16150. D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
16151. D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
16152. D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
16153. D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
16154. D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
16155. D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
16156. D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
16157. D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
16158. D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
16159. D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
16160. D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
16161. D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
16162. D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
16163. D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
16164. D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
16165. D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
16166. D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
16167. D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
16168. D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
16169. D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
16170. D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
16171. D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
16172. D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
16173. D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
16174. D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
16175. D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
16176. D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
16177. D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
16178. D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
16179. D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
16180. D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
16181. D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
16182. D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
16183. D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
16184. D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
16185. D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
16186. D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
16187. D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
16188. D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
16189. D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
16190. D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
16191. D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
16192. D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
16193. D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
16194. D3F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK
16195. D3F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
16196. D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
16197. D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
16198. D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
16199. D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
16200. D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
16201. D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
16202. D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
16203. D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
16204. D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
16205. D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
16206. D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
16207. D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
16208. D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
16209. D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
16210. D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
16211. D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
16212. D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
16213. D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
16214. D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
16215. D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
16216. D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
16217. D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
16218. D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
16219. D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
16220. D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
16221. D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
16222. D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
16223. D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
16224. D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
16225. D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
16226. D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
16227. D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
16228. D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
16229. D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
16230. D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
16231. D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
16232. D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
16233. D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
16234. D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
16235. D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
16236. D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
16237. D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
16238. D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
16239. D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
16240. D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
16241. D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
16242. D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
16243. D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
16244. D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
16245. D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
16246. D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
16247. D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
16248. D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
16249. D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
16250. D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
16251. D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
16252. D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
16253. D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
16254. D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
16255. D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
16256. D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
16257. D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
16258. D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
16259. D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
16260. D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
16261. D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
16262. D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
16263. D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
16264. D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
16265. D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
16266. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
16267. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
16268. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
16269. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
16270. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
16271. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
16272. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
16273. D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
16274. D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
16275. D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
16276. D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
16277. D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
16278. D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
16279. D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
16280. D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
16281. D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
16282. D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
16283. D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
16284. D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
16285. D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
16286. D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
16287. D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
16288. D3F4_PCIE_CAP_LIST__CAP_ID_MASK
16289. D3F4_PCIE_CAP_LIST__CAP_ID__SHIFT
16290. D3F4_PCIE_CAP_LIST__NEXT_PTR_MASK
16291. D3F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT
16292. D3F4_PCIE_CAP__DEVICE_TYPE_MASK
16293. D3F4_PCIE_CAP__DEVICE_TYPE__SHIFT
16294. D3F4_PCIE_CAP__INT_MESSAGE_NUM_MASK
16295. D3F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
16296. D3F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK
16297. D3F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
16298. D3F4_PCIE_CAP__VERSION_MASK
16299. D3F4_PCIE_CAP__VERSION__SHIFT
16300. D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
16301. D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
16302. D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
16303. D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
16304. D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
16305. D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
16306. D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
16307. D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
16308. D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
16309. D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
16310. D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
16311. D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
16312. D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
16313. D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
16314. D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
16315. D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
16316. D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
16317. D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
16318. D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
16319. D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
16320. D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
16321. D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
16322. D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
16323. D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
16324. D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
16325. D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
16326. D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
16327. D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
16328. D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
16329. D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
16330. D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
16331. D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
16332. D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
16333. D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
16334. D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
16335. D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
16336. D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
16337. D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
16338. D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
16339. D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
16340. D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
16341. D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
16342. D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
16343. D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
16344. D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
16345. D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
16346. D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
16347. D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
16348. D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
16349. D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
16350. D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
16351. D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
16352. D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
16353. D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
16354. D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
16355. D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
16356. D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
16357. D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
16358. D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
16359. D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
16360. D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
16361. D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
16362. D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
16363. D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
16364. D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
16365. D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
16366. D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
16367. D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
16368. D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
16369. D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
16370. D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
16371. D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
16372. D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
16373. D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
16374. D3F4_PCIE_FC_CPL__CPLD_CREDITS_MASK
16375. D3F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
16376. D3F4_PCIE_FC_CPL__CPLH_CREDITS_MASK
16377. D3F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
16378. D3F4_PCIE_FC_NP__NPD_CREDITS_MASK
16379. D3F4_PCIE_FC_NP__NPD_CREDITS__SHIFT
16380. D3F4_PCIE_FC_NP__NPH_CREDITS_MASK
16381. D3F4_PCIE_FC_NP__NPH_CREDITS__SHIFT
16382. D3F4_PCIE_FC_P__PD_CREDITS_MASK
16383. D3F4_PCIE_FC_P__PD_CREDITS__SHIFT
16384. D3F4_PCIE_FC_P__PH_CREDITS_MASK
16385. D3F4_PCIE_FC_P__PH_CREDITS__SHIFT
16386. D3F4_PCIE_HDR_LOG0__TLP_HDR_MASK
16387. D3F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT
16388. D3F4_PCIE_HDR_LOG1__TLP_HDR_MASK
16389. D3F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT
16390. D3F4_PCIE_HDR_LOG2__TLP_HDR_MASK
16391. D3F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT
16392. D3F4_PCIE_HDR_LOG3__TLP_HDR_MASK
16393. D3F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT
16394. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16395. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16396. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16397. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16398. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
16399. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
16400. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16401. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16402. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16403. D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16404. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16405. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16406. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16407. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16408. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
16409. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
16410. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16411. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16412. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16413. D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16414. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16415. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16416. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16417. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16418. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
16419. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
16420. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16421. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16422. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16423. D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16424. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16425. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16426. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16427. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16428. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
16429. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
16430. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16431. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16432. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16433. D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16434. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16435. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16436. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16437. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16438. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
16439. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
16440. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16441. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16442. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16443. D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16444. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16445. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16446. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16447. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16448. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
16449. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
16450. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16451. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16452. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16453. D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16454. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16455. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16456. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16457. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16458. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
16459. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
16460. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16461. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16462. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16463. D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16464. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16465. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16466. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16467. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16468. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
16469. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
16470. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16471. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16472. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16473. D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16474. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16475. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16476. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16477. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16478. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
16479. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
16480. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16481. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16482. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16483. D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16484. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16485. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16486. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16487. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16488. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
16489. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
16490. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16491. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16492. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16493. D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16494. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16495. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16496. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16497. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16498. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
16499. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
16500. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16501. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16502. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16503. D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16504. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16505. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16506. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16507. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16508. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
16509. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
16510. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16511. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16512. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16513. D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16514. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16515. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16516. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16517. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16518. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
16519. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
16520. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16521. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16522. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16523. D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16524. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16525. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16526. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16527. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16528. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
16529. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
16530. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16531. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16532. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16533. D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16534. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16535. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16536. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16537. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16538. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
16539. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
16540. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16541. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16542. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16543. D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16544. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
16545. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
16546. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
16547. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
16548. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
16549. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
16550. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
16551. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
16552. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
16553. D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
16554. D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
16555. D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
16556. D3F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
16557. D3F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
16558. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
16559. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
16560. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
16561. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
16562. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
16563. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
16564. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
16565. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
16566. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
16567. D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
16568. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
16569. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
16570. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
16571. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
16572. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
16573. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
16574. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
16575. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
16576. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
16577. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
16578. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
16579. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
16580. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
16581. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
16582. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
16583. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
16584. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
16585. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
16586. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
16587. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
16588. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
16589. D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
16590. D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
16591. D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
16592. D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
16593. D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
16594. D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
16595. D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
16596. D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
16597. D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
16598. D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
16599. D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
16600. D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
16601. D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
16602. D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
16603. D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
16604. D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
16605. D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
16606. D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
16607. D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
16608. D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
16609. D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
16610. D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
16611. D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
16612. D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
16613. D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
16614. D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
16615. D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
16616. D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
16617. D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
16618. D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
16619. D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
16620. D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
16621. D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
16622. D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
16623. D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
16624. D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
16625. D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
16626. D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
16627. D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
16628. D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
16629. D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
16630. D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
16631. D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
16632. D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
16633. D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
16634. D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
16635. D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
16636. D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
16637. D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
16638. D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
16639. D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
16640. D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
16641. D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
16642. D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
16643. D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
16644. D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
16645. D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
16646. D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
16647. D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
16648. D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
16649. D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
16650. D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
16651. D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
16652. D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
16653. D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
16654. D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
16655. D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
16656. D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
16657. D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
16658. D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
16659. D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
16660. D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
16661. D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
16662. D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
16663. D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
16664. D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
16665. D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
16666. D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
16667. D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
16668. D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
16669. D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
16670. D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
16671. D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
16672. D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
16673. D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
16674. D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
16675. D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
16676. D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
16677. D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
16678. D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
16679. D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
16680. D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
16681. D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
16682. D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
16683. D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
16684. D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
16685. D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
16686. D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
16687. D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
16688. D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
16689. D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
16690. D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
16691. D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
16692. D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
16693. D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
16694. D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
16695. D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
16696. D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
16697. D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
16698. D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
16699. D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
16700. D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
16701. D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
16702. D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
16703. D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
16704. D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
16705. D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
16706. D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
16707. D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
16708. D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
16709. D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
16710. D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
16711. D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
16712. D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
16713. D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
16714. D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
16715. D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
16716. D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
16717. D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
16718. D3F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
16719. D3F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
16720. D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
16721. D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
16722. D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
16723. D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
16724. D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
16725. D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
16726. D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
16727. D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
16728. D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
16729. D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
16730. D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
16731. D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
16732. D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
16733. D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
16734. D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
16735. D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
16736. D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
16737. D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
16738. D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
16739. D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
16740. D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
16741. D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
16742. D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
16743. D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
16744. D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
16745. D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
16746. D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
16747. D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
16748. D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
16749. D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
16750. D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
16751. D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
16752. D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
16753. D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
16754. D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
16755. D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
16756. D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
16757. D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
16758. D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
16759. D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
16760. D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
16761. D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
16762. D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
16763. D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
16764. D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
16765. D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
16766. D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
16767. D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
16768. D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
16769. D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
16770. D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
16771. D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
16772. D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
16773. D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
16774. D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
16775. D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
16776. D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
16777. D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
16778. D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
16779. D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
16780. D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
16781. D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
16782. D3F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK
16783. D3F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
16784. D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
16785. D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
16786. D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
16787. D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
16788. D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
16789. D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
16790. D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
16791. D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
16792. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
16793. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
16794. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
16795. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
16796. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
16797. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
16798. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
16799. D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
16800. D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
16801. D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
16802. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
16803. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
16804. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
16805. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
16806. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
16807. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
16808. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
16809. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
16810. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
16811. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
16812. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
16813. D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
16814. D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
16815. D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
16816. D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
16817. D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
16818. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
16819. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
16820. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
16821. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
16822. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
16823. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
16824. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
16825. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
16826. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
16827. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
16828. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
16829. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
16830. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
16831. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
16832. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
16833. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
16834. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
16835. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
16836. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
16837. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
16838. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
16839. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
16840. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
16841. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
16842. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
16843. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
16844. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
16845. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
16846. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
16847. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
16848. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
16849. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
16850. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
16851. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
16852. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
16853. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
16854. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
16855. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
16856. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
16857. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
16858. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
16859. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
16860. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
16861. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
16862. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
16863. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
16864. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
16865. D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
16866. D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
16867. D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
16868. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
16869. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
16870. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
16871. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
16872. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
16873. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
16874. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
16875. D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
16876. D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
16877. D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
16878. D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
16879. D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
16880. D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
16881. D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
16882. D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
16883. D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
16884. D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
16885. D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
16886. D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
16887. D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
16888. D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
16889. D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
16890. D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
16891. D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
16892. D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
16893. D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
16894. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
16895. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
16896. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
16897. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
16898. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
16899. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
16900. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
16901. D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
16902. D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
16903. D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
16904. D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
16905. D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
16906. D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
16907. D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
16908. D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
16909. D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
16910. D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
16911. D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
16912. D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
16913. D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
16914. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
16915. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
16916. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
16917. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
16918. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
16919. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
16920. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
16921. D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
16922. D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
16923. D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
16924. D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
16925. D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
16926. D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
16927. D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
16928. D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
16929. D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
16930. D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
16931. D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
16932. D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
16933. D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
16934. D3F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
16935. D3F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
16936. D3F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
16937. D3F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
16938. D3F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
16939. D3F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
16940. D3F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
16941. D3F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
16942. D3F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
16943. D3F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
16944. D3F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
16945. D3F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
16946. D3F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
16947. D3F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
16948. D3F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
16949. D3F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
16950. D3F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
16951. D3F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
16952. D3F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
16953. D3F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
16954. D3F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
16955. D3F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
16956. D3F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
16957. D3F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
16958. D3F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
16959. D3F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
16960. D3F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
16961. D3F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
16962. D3F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
16963. D3F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
16964. D3F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
16965. D3F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
16966. D3F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
16967. D3F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
16968. D3F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
16969. D3F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
16970. D3F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
16971. D3F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
16972. D3F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
16973. D3F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
16974. D3F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
16975. D3F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
16976. D3F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
16977. D3F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
16978. D3F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
16979. D3F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
16980. D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
16981. D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
16982. D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
16983. D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
16984. D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
16985. D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
16986. D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
16987. D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
16988. D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
16989. D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
16990. D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
16991. D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
16992. D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
16993. D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
16994. D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
16995. D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
16996. D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
16997. D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
16998. D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
16999. D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
17000. D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
17001. D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
17002. D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
17003. D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
17004. D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
17005. D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
17006. D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
17007. D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
17008. D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
17009. D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
17010. D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
17011. D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
17012. D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
17013. D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
17014. D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
17015. D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
17016. D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
17017. D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
17018. D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
17019. D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
17020. D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
17021. D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
17022. D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
17023. D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
17024. D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
17025. D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
17026. D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
17027. D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
17028. D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
17029. D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
17030. D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
17031. D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
17032. D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
17033. D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
17034. D3F4_PCIE_LINK_CNTL3__RESERVED_MASK
17035. D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT
17036. D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
17037. D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
17038. D3F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
17039. D3F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
17040. D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
17041. D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
17042. D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
17043. D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
17044. D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
17045. D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
17046. D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
17047. D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
17048. D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
17049. D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
17050. D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
17051. D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
17052. D3F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK
17053. D3F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
17054. D3F4_PCIE_MC_CNTL__MC_ENABLE_MASK
17055. D3F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT
17056. D3F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
17057. D3F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
17058. D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
17059. D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
17060. D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
17061. D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
17062. D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
17063. D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
17064. D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
17065. D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
17066. D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
17067. D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
17068. D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
17069. D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
17070. D3F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
17071. D3F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
17072. D3F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
17073. D3F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
17074. D3F4_PCIE_PORT_DATA__PCIE_DATA_MASK
17075. D3F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT
17076. D3F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK
17077. D3F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
17078. D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
17079. D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
17080. D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
17081. D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
17082. D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
17083. D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
17084. D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
17085. D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
17086. D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
17087. D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
17088. D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
17089. D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
17090. D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
17091. D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
17092. D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
17093. D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
17094. D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
17095. D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
17096. D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
17097. D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
17098. D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
17099. D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
17100. D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
17101. D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
17102. D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
17103. D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
17104. D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
17105. D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
17106. D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
17107. D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
17108. D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
17109. D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
17110. D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
17111. D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
17112. D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
17113. D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
17114. D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
17115. D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
17116. D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
17117. D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
17118. D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
17119. D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
17120. D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
17121. D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
17122. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
17123. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
17124. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
17125. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
17126. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
17127. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
17128. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
17129. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
17130. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
17131. D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
17132. D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
17133. D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
17134. D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
17135. D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
17136. D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
17137. D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
17138. D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
17139. D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
17140. D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
17141. D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
17142. D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
17143. D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
17144. D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
17145. D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
17146. D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
17147. D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
17148. D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
17149. D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
17150. D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
17151. D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
17152. D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
17153. D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
17154. D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
17155. D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
17156. D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
17157. D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
17158. D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
17159. D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
17160. D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
17161. D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
17162. D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
17163. D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
17164. D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
17165. D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
17166. D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
17167. D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
17168. D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
17169. D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
17170. D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
17171. D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
17172. D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
17173. D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
17174. D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
17175. D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
17176. D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
17177. D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
17178. D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
17179. D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
17180. D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
17181. D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
17182. D3F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK
17183. D3F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
17184. D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
17185. D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
17186. D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
17187. D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
17188. D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
17189. D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
17190. D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
17191. D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
17192. D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
17193. D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
17194. D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
17195. D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
17196. D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
17197. D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
17198. D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
17199. D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
17200. D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
17201. D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
17202. D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
17203. D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
17204. D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
17205. D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
17206. D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
17207. D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
17208. D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
17209. D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
17210. D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
17211. D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
17212. D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
17213. D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
17214. D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
17215. D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
17216. D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
17217. D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
17218. D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
17219. D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
17220. D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
17221. D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
17222. D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
17223. D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
17224. D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
17225. D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
17226. D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
17227. D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
17228. D3F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
17229. D3F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
17230. D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
17231. D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
17232. D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
17233. D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
17234. D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
17235. D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
17236. D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
17237. D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
17238. D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
17239. D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
17240. D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
17241. D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
17242. D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
17243. D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
17244. D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
17245. D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
17246. D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
17247. D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
17248. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
17249. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
17250. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
17251. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
17252. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
17253. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
17254. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
17255. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
17256. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
17257. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
17258. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
17259. D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
17260. D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
17261. D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
17262. D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
17263. D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
17264. D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
17265. D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
17266. D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
17267. D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
17268. D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
17269. D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
17270. D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
17271. D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
17272. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
17273. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
17274. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
17275. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
17276. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
17277. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
17278. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
17279. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
17280. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
17281. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
17282. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
17283. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
17284. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
17285. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
17286. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
17287. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
17288. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
17289. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
17290. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
17291. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
17292. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
17293. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
17294. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
17295. D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
17296. D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
17297. D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
17298. D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
17299. D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
17300. D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
17301. D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
17302. D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
17303. D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
17304. D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
17305. D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
17306. D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
17307. D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
17308. D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
17309. D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
17310. D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
17311. D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
17312. D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
17313. D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
17314. D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
17315. D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
17316. D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
17317. D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
17318. D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
17319. D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
17320. D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
17321. D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
17322. D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
17323. D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
17324. D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
17325. D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
17326. D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
17327. D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
17328. D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
17329. D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
17330. D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
17331. D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
17332. D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
17333. D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
17334. D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
17335. D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
17336. D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
17337. D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
17338. D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
17339. D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
17340. D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
17341. D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
17342. D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
17343. D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
17344. D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
17345. D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
17346. D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
17347. D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
17348. D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
17349. D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
17350. D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
17351. D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
17352. D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
17353. D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
17354. D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
17355. D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
17356. D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
17357. D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
17358. D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
17359. D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
17360. D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
17361. D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
17362. D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
17363. D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
17364. D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
17365. D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
17366. D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
17367. D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
17368. D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
17369. D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
17370. D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
17371. D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
17372. D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
17373. D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
17374. D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
17375. D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
17376. D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
17377. D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
17378. D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
17379. D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
17380. D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
17381. D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
17382. D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
17383. D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
17384. D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
17385. D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
17386. D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
17387. D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
17388. D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
17389. D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
17390. D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
17391. D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
17392. D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
17393. D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
17394. D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
17395. D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
17396. D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
17397. D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
17398. D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
17399. D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
17400. D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
17401. D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
17402. D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
17403. D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
17404. D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
17405. D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
17406. D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
17407. D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
17408. D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
17409. D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
17410. D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
17411. D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
17412. D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
17413. D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
17414. D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
17415. D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
17416. D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
17417. D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
17418. D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
17419. D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
17420. D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
17421. D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
17422. D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
17423. D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
17424. D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
17425. D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
17426. D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
17427. D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
17428. D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
17429. D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
17430. D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
17431. D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
17432. D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
17433. D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
17434. D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
17435. D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
17436. D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
17437. D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
17438. D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
17439. D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
17440. D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
17441. D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
17442. D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
17443. D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
17444. D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
17445. D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
17446. D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
17447. D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
17448. D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
17449. D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
17450. D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
17451. D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
17452. D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
17453. D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
17454. D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
17455. D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
17456. D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
17457. D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
17458. D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
17459. D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
17460. D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
17461. D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
17462. D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
17463. D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
17464. D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
17465. D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
17466. D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
17467. D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
17468. D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
17469. D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
17470. D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
17471. D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
17472. D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
17473. D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
17474. D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
17475. D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
17476. D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
17477. D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
17478. D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
17479. D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
17480. D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
17481. D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
17482. D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
17483. D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
17484. D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
17485. D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
17486. D3F4_PMI_CAP_LIST__CAP_ID_MASK
17487. D3F4_PMI_CAP_LIST__CAP_ID__SHIFT
17488. D3F4_PMI_CAP_LIST__NEXT_PTR_MASK
17489. D3F4_PMI_CAP_LIST__NEXT_PTR__SHIFT
17490. D3F4_PMI_CAP__AUX_CURRENT_MASK
17491. D3F4_PMI_CAP__AUX_CURRENT__SHIFT
17492. D3F4_PMI_CAP__D1_SUPPORT_MASK
17493. D3F4_PMI_CAP__D1_SUPPORT__SHIFT
17494. D3F4_PMI_CAP__D2_SUPPORT_MASK
17495. D3F4_PMI_CAP__D2_SUPPORT__SHIFT
17496. D3F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK
17497. D3F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
17498. D3F4_PMI_CAP__PME_CLOCK_MASK
17499. D3F4_PMI_CAP__PME_CLOCK__SHIFT
17500. D3F4_PMI_CAP__PME_SUPPORT_MASK
17501. D3F4_PMI_CAP__PME_SUPPORT__SHIFT
17502. D3F4_PMI_CAP__VERSION_MASK
17503. D3F4_PMI_CAP__VERSION__SHIFT
17504. D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
17505. D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
17506. D3F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
17507. D3F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
17508. D3F4_PMI_STATUS_CNTL__DATA_SCALE_MASK
17509. D3F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
17510. D3F4_PMI_STATUS_CNTL__DATA_SELECT_MASK
17511. D3F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
17512. D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
17513. D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
17514. D3F4_PMI_STATUS_CNTL__PME_EN_MASK
17515. D3F4_PMI_STATUS_CNTL__PME_EN__SHIFT
17516. D3F4_PMI_STATUS_CNTL__PME_STATUS_MASK
17517. D3F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT
17518. D3F4_PMI_STATUS_CNTL__PMI_DATA_MASK
17519. D3F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT
17520. D3F4_PMI_STATUS_CNTL__POWER_STATE_MASK
17521. D3F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT
17522. D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
17523. D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
17524. D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
17525. D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
17526. D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
17527. D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
17528. D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
17529. D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
17530. D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
17531. D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
17532. D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
17533. D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
17534. D3F4_PROG_INTERFACE__PROG_INTERFACE_MASK
17535. D3F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT
17536. D3F4_REVISION_ID__MAJOR_REV_ID_MASK
17537. D3F4_REVISION_ID__MAJOR_REV_ID__SHIFT
17538. D3F4_REVISION_ID__MINOR_REV_ID_MASK
17539. D3F4_REVISION_ID__MINOR_REV_ID__SHIFT
17540. D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
17541. D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
17542. D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
17543. D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
17544. D3F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK
17545. D3F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
17546. D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
17547. D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
17548. D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
17549. D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
17550. D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
17551. D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
17552. D3F4_ROOT_STATUS__PME_PENDING_MASK
17553. D3F4_ROOT_STATUS__PME_PENDING__SHIFT
17554. D3F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK
17555. D3F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
17556. D3F4_ROOT_STATUS__PME_STATUS_MASK
17557. D3F4_ROOT_STATUS__PME_STATUS__SHIFT
17558. D3F4_SECONDARY_STATUS__CAP_LIST_MASK
17559. D3F4_SECONDARY_STATUS__CAP_LIST__SHIFT
17560. D3F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK
17561. D3F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
17562. D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
17563. D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
17564. D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
17565. D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
17566. D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
17567. D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
17568. D3F4_SECONDARY_STATUS__PCI_66_EN_MASK
17569. D3F4_SECONDARY_STATUS__PCI_66_EN__SHIFT
17570. D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
17571. D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
17572. D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
17573. D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
17574. D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
17575. D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
17576. D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
17577. D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
17578. D3F4_SLOT_CAP2__RESERVED_MASK
17579. D3F4_SLOT_CAP2__RESERVED__SHIFT
17580. D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
17581. D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
17582. D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
17583. D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
17584. D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
17585. D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
17586. D3F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK
17587. D3F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
17588. D3F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK
17589. D3F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
17590. D3F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
17591. D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
17592. D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
17593. D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
17594. D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
17595. D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
17596. D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
17597. D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
17598. D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
17599. D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
17600. D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
17601. D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
17602. D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
17603. D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
17604. D3F4_SLOT_CNTL2__RESERVED_MASK
17605. D3F4_SLOT_CNTL2__RESERVED__SHIFT
17606. D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
17607. D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
17608. D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
17609. D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
17610. D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
17611. D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
17612. D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
17613. D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
17614. D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
17615. D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
17616. D3F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
17617. D3F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
17618. D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
17619. D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
17620. D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
17621. D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
17622. D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
17623. D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
17624. D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
17625. D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
17626. D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
17627. D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
17628. D3F4_SLOT_STATUS2__RESERVED_MASK
17629. D3F4_SLOT_STATUS2__RESERVED__SHIFT
17630. D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
17631. D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
17632. D3F4_SLOT_STATUS__COMMAND_COMPLETED_MASK
17633. D3F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
17634. D3F4_SLOT_STATUS__DL_STATE_CHANGED_MASK
17635. D3F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
17636. D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
17637. D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
17638. D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
17639. D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
17640. D3F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK
17641. D3F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
17642. D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
17643. D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
17644. D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
17645. D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
17646. D3F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
17647. D3F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
17648. D3F4_SSID_CAP_LIST__CAP_ID_MASK
17649. D3F4_SSID_CAP_LIST__CAP_ID__SHIFT
17650. D3F4_SSID_CAP_LIST__NEXT_PTR_MASK
17651. D3F4_SSID_CAP_LIST__NEXT_PTR__SHIFT
17652. D3F4_SSID_CAP__SUBSYSTEM_ID_MASK
17653. D3F4_SSID_CAP__SUBSYSTEM_ID__SHIFT
17654. D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
17655. D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
17656. D3F4_STATUS__CAP_LIST_MASK
17657. D3F4_STATUS__CAP_LIST__SHIFT
17658. D3F4_STATUS__DEVSEL_TIMING_MASK
17659. D3F4_STATUS__DEVSEL_TIMING__SHIFT
17660. D3F4_STATUS__FAST_BACK_CAPABLE_MASK
17661. D3F4_STATUS__FAST_BACK_CAPABLE__SHIFT
17662. D3F4_STATUS__INT_STATUS_MASK
17663. D3F4_STATUS__INT_STATUS__SHIFT
17664. D3F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK
17665. D3F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
17666. D3F4_STATUS__PARITY_ERROR_DETECTED_MASK
17667. D3F4_STATUS__PARITY_ERROR_DETECTED__SHIFT
17668. D3F4_STATUS__PCI_66_EN_MASK
17669. D3F4_STATUS__PCI_66_EN__SHIFT
17670. D3F4_STATUS__RECEIVED_MASTER_ABORT_MASK
17671. D3F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT
17672. D3F4_STATUS__RECEIVED_TARGET_ABORT_MASK
17673. D3F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT
17674. D3F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK
17675. D3F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
17676. D3F4_STATUS__SIGNAL_TARGET_ABORT_MASK
17677. D3F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT
17678. D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
17679. D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
17680. D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
17681. D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
17682. D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
17683. D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
17684. D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
17685. D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
17686. D3F4_SUB_CLASS__SUB_CLASS_MASK
17687. D3F4_SUB_CLASS__SUB_CLASS__SHIFT
17688. D3F4_VENDOR_ID__VENDOR_ID_MASK
17689. D3F4_VENDOR_ID__VENDOR_ID__SHIFT
17690. D3F5_BASE_CLASS__BASE_CLASS_MASK
17691. D3F5_BASE_CLASS__BASE_CLASS__SHIFT
17692. D3F5_BIST__BIST_CAP_MASK
17693. D3F5_BIST__BIST_CAP__SHIFT
17694. D3F5_BIST__BIST_COMP_MASK
17695. D3F5_BIST__BIST_COMP__SHIFT
17696. D3F5_BIST__BIST_STRT_MASK
17697. D3F5_BIST__BIST_STRT__SHIFT
17698. D3F5_CACHE_LINE__CACHE_LINE_SIZE_MASK
17699. D3F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
17700. D3F5_CAP_PTR__CAP_PTR_MASK
17701. D3F5_CAP_PTR__CAP_PTR__SHIFT
17702. D3F5_COMMAND__AD_STEPPING_MASK
17703. D3F5_COMMAND__AD_STEPPING__SHIFT
17704. D3F5_COMMAND__BUS_MASTER_EN_MASK
17705. D3F5_COMMAND__BUS_MASTER_EN__SHIFT
17706. D3F5_COMMAND__FAST_B2B_EN_MASK
17707. D3F5_COMMAND__FAST_B2B_EN__SHIFT
17708. D3F5_COMMAND__INT_DIS_MASK
17709. D3F5_COMMAND__INT_DIS__SHIFT
17710. D3F5_COMMAND__IO_ACCESS_EN_MASK
17711. D3F5_COMMAND__IO_ACCESS_EN__SHIFT
17712. D3F5_COMMAND__MEM_ACCESS_EN_MASK
17713. D3F5_COMMAND__MEM_ACCESS_EN__SHIFT
17714. D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
17715. D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
17716. D3F5_COMMAND__PAL_SNOOP_EN_MASK
17717. D3F5_COMMAND__PAL_SNOOP_EN__SHIFT
17718. D3F5_COMMAND__PARITY_ERROR_RESPONSE_MASK
17719. D3F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
17720. D3F5_COMMAND__SERR_EN_MASK
17721. D3F5_COMMAND__SERR_EN__SHIFT
17722. D3F5_COMMAND__SPECIAL_CYCLE_EN_MASK
17723. D3F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT
17724. D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
17725. D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
17726. D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
17727. D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
17728. D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
17729. D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
17730. D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
17731. D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
17732. D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
17733. D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
17734. D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
17735. D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
17736. D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
17737. D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
17738. D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
17739. D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
17740. D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
17741. D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
17742. D3F5_DEVICE_CAP2__LTR_SUPPORTED_MASK
17743. D3F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
17744. D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
17745. D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
17746. D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
17747. D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
17748. D3F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK
17749. D3F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
17750. D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
17751. D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
17752. D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
17753. D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
17754. D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
17755. D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
17756. D3F5_DEVICE_CAP__EXTENDED_TAG_MASK
17757. D3F5_DEVICE_CAP__EXTENDED_TAG__SHIFT
17758. D3F5_DEVICE_CAP__FLR_CAPABLE_MASK
17759. D3F5_DEVICE_CAP__FLR_CAPABLE__SHIFT
17760. D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
17761. D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
17762. D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
17763. D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
17764. D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
17765. D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
17766. D3F5_DEVICE_CAP__PHANTOM_FUNC_MASK
17767. D3F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT
17768. D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
17769. D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
17770. D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
17771. D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
17772. D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
17773. D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
17774. D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
17775. D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
17776. D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
17777. D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
17778. D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
17779. D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
17780. D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
17781. D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
17782. D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
17783. D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
17784. D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
17785. D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
17786. D3F5_DEVICE_CNTL2__LTR_EN_MASK
17787. D3F5_DEVICE_CNTL2__LTR_EN__SHIFT
17788. D3F5_DEVICE_CNTL2__OBFF_EN_MASK
17789. D3F5_DEVICE_CNTL2__OBFF_EN__SHIFT
17790. D3F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
17791. D3F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
17792. D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
17793. D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
17794. D3F5_DEVICE_CNTL__CORR_ERR_EN_MASK
17795. D3F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT
17796. D3F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
17797. D3F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
17798. D3F5_DEVICE_CNTL__FATAL_ERR_EN_MASK
17799. D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
17800. D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
17801. D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
17802. D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
17803. D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
17804. D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
17805. D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
17806. D3F5_DEVICE_CNTL__NO_SNOOP_EN_MASK
17807. D3F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
17808. D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
17809. D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
17810. D3F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK
17811. D3F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
17812. D3F5_DEVICE_CNTL__USR_REPORT_EN_MASK
17813. D3F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT
17814. D3F5_DEVICE_ID__DEVICE_ID_MASK
17815. D3F5_DEVICE_ID__DEVICE_ID__SHIFT
17816. D3F5_DEVICE_STATUS2__RESERVED_MASK
17817. D3F5_DEVICE_STATUS2__RESERVED__SHIFT
17818. D3F5_DEVICE_STATUS__AUX_PWR_MASK
17819. D3F5_DEVICE_STATUS__AUX_PWR__SHIFT
17820. D3F5_DEVICE_STATUS__CORR_ERR_MASK
17821. D3F5_DEVICE_STATUS__CORR_ERR__SHIFT
17822. D3F5_DEVICE_STATUS__FATAL_ERR_MASK
17823. D3F5_DEVICE_STATUS__FATAL_ERR__SHIFT
17824. D3F5_DEVICE_STATUS__NON_FATAL_ERR_MASK
17825. D3F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
17826. D3F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
17827. D3F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
17828. D3F5_DEVICE_STATUS__USR_DETECTED_MASK
17829. D3F5_DEVICE_STATUS__USR_DETECTED__SHIFT
17830. D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
17831. D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
17832. D3F5_HEADER__DEVICE_TYPE_MASK
17833. D3F5_HEADER__DEVICE_TYPE__SHIFT
17834. D3F5_HEADER__HEADER_TYPE_MASK
17835. D3F5_HEADER__HEADER_TYPE__SHIFT
17836. D3F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK
17837. D3F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
17838. D3F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK
17839. D3F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
17840. D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
17841. D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
17842. D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
17843. D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
17844. D3F5_IO_BASE_LIMIT__IO_BASE_MASK
17845. D3F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
17846. D3F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
17847. D3F5_IO_BASE_LIMIT__IO_BASE__SHIFT
17848. D3F5_IO_BASE_LIMIT__IO_LIMIT_MASK
17849. D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
17850. D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
17851. D3F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT
17852. D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
17853. D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
17854. D3F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK
17855. D3F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
17856. D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
17857. D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
17858. D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
17859. D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
17860. D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
17861. D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
17862. D3F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK
17863. D3F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
17864. D3F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
17865. D3F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
17866. D3F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK
17867. D3F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
17868. D3F5_LATENCY__LATENCY_TIMER_MASK
17869. D3F5_LATENCY__LATENCY_TIMER__SHIFT
17870. D3F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
17871. D3F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
17872. D3F5_LINK_CAP2__RESERVED_MASK
17873. D3F5_LINK_CAP2__RESERVED__SHIFT
17874. D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
17875. D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
17876. D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
17877. D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
17878. D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
17879. D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
17880. D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
17881. D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
17882. D3F5_LINK_CAP__L0S_EXIT_LATENCY_MASK
17883. D3F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
17884. D3F5_LINK_CAP__L1_EXIT_LATENCY_MASK
17885. D3F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT
17886. D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
17887. D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
17888. D3F5_LINK_CAP__LINK_SPEED_MASK
17889. D3F5_LINK_CAP__LINK_SPEED__SHIFT
17890. D3F5_LINK_CAP__LINK_WIDTH_MASK
17891. D3F5_LINK_CAP__LINK_WIDTH__SHIFT
17892. D3F5_LINK_CAP__PM_SUPPORT_MASK
17893. D3F5_LINK_CAP__PM_SUPPORT__SHIFT
17894. D3F5_LINK_CAP__PORT_NUMBER_MASK
17895. D3F5_LINK_CAP__PORT_NUMBER__SHIFT
17896. D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
17897. D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
17898. D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
17899. D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
17900. D3F5_LINK_CNTL2__COMPLIANCE_SOS_MASK
17901. D3F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
17902. D3F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK
17903. D3F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
17904. D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
17905. D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
17906. D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
17907. D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
17908. D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
17909. D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
17910. D3F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK
17911. D3F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
17912. D3F5_LINK_CNTL2__XMIT_MARGIN_MASK
17913. D3F5_LINK_CNTL2__XMIT_MARGIN__SHIFT
17914. D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
17915. D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
17916. D3F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK
17917. D3F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
17918. D3F5_LINK_CNTL__EXTENDED_SYNC_MASK
17919. D3F5_LINK_CNTL__EXTENDED_SYNC__SHIFT
17920. D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
17921. D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
17922. D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
17923. D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
17924. D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
17925. D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
17926. D3F5_LINK_CNTL__LINK_DIS_MASK
17927. D3F5_LINK_CNTL__LINK_DIS__SHIFT
17928. D3F5_LINK_CNTL__PM_CONTROL_MASK
17929. D3F5_LINK_CNTL__PM_CONTROL__SHIFT
17930. D3F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK
17931. D3F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
17932. D3F5_LINK_CNTL__RETRAIN_LINK_MASK
17933. D3F5_LINK_CNTL__RETRAIN_LINK__SHIFT
17934. D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
17935. D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
17936. D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
17937. D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
17938. D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
17939. D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
17940. D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
17941. D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
17942. D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
17943. D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
17944. D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
17945. D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
17946. D3F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK
17947. D3F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
17948. D3F5_LINK_STATUS__DL_ACTIVE_MASK
17949. D3F5_LINK_STATUS__DL_ACTIVE__SHIFT
17950. D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
17951. D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
17952. D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
17953. D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
17954. D3F5_LINK_STATUS__LINK_TRAINING_MASK
17955. D3F5_LINK_STATUS__LINK_TRAINING__SHIFT
17956. D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
17957. D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
17958. D3F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK
17959. D3F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
17960. D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
17961. D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
17962. D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
17963. D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
17964. D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
17965. D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
17966. D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
17967. D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
17968. D3F5_MSI_CAP_LIST__CAP_ID_MASK
17969. D3F5_MSI_CAP_LIST__CAP_ID__SHIFT
17970. D3F5_MSI_CAP_LIST__NEXT_PTR_MASK
17971. D3F5_MSI_CAP_LIST__NEXT_PTR__SHIFT
17972. D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
17973. D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
17974. D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
17975. D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
17976. D3F5_MSI_MAP_CAP_LIST__CAP_ID_MASK
17977. D3F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
17978. D3F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
17979. D3F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
17980. D3F5_MSI_MAP_CAP__CAP_TYPE_MASK
17981. D3F5_MSI_MAP_CAP__CAP_TYPE__SHIFT
17982. D3F5_MSI_MAP_CAP__EN_MASK
17983. D3F5_MSI_MAP_CAP__EN__SHIFT
17984. D3F5_MSI_MAP_CAP__FIXD_MASK
17985. D3F5_MSI_MAP_CAP__FIXD__SHIFT
17986. D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
17987. D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
17988. D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
17989. D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
17990. D3F5_MSI_MSG_CNTL__MSI_64BIT_MASK
17991. D3F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT
17992. D3F5_MSI_MSG_CNTL__MSI_EN_MASK
17993. D3F5_MSI_MSG_CNTL__MSI_EN__SHIFT
17994. D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
17995. D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
17996. D3F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
17997. D3F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
17998. D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
17999. D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
18000. D3F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK
18001. D3F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
18002. D3F5_MSI_MSG_DATA__MSI_DATA_MASK
18003. D3F5_MSI_MSG_DATA__MSI_DATA__SHIFT
18004. D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
18005. D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
18006. D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
18007. D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
18008. D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
18009. D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
18010. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
18011. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
18012. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
18013. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
18014. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
18015. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
18016. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
18017. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
18018. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
18019. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
18020. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
18021. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
18022. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
18023. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
18024. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
18025. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
18026. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
18027. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
18028. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
18029. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
18030. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
18031. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
18032. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
18033. D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
18034. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
18035. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
18036. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
18037. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
18038. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
18039. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
18040. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
18041. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
18042. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
18043. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
18044. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
18045. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
18046. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
18047. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
18048. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
18049. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
18050. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
18051. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
18052. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
18053. D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
18054. D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
18055. D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
18056. D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
18057. D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
18058. D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
18059. D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
18060. D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
18061. D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
18062. D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
18063. D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
18064. D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
18065. D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
18066. D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
18067. D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
18068. D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
18069. D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
18070. D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
18071. D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
18072. D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
18073. D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
18074. D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
18075. D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
18076. D3F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK
18077. D3F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
18078. D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
18079. D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
18080. D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
18081. D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
18082. D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
18083. D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
18084. D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
18085. D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
18086. D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
18087. D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
18088. D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
18089. D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
18090. D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
18091. D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
18092. D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
18093. D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
18094. D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
18095. D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
18096. D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
18097. D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
18098. D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
18099. D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
18100. D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
18101. D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
18102. D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
18103. D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
18104. D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
18105. D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
18106. D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
18107. D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
18108. D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
18109. D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
18110. D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
18111. D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
18112. D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
18113. D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
18114. D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
18115. D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
18116. D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
18117. D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
18118. D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
18119. D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
18120. D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
18121. D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
18122. D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
18123. D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
18124. D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
18125. D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
18126. D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
18127. D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
18128. D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
18129. D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
18130. D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
18131. D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
18132. D3F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK
18133. D3F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
18134. D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
18135. D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
18136. D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
18137. D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
18138. D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
18139. D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
18140. D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
18141. D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
18142. D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
18143. D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
18144. D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
18145. D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
18146. D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
18147. D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
18148. D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
18149. D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
18150. D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
18151. D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
18152. D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
18153. D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
18154. D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
18155. D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
18156. D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
18157. D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
18158. D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
18159. D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
18160. D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
18161. D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
18162. D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
18163. D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
18164. D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
18165. D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
18166. D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
18167. D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
18168. D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
18169. D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
18170. D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
18171. D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
18172. D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
18173. D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
18174. D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
18175. D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
18176. D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
18177. D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
18178. D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
18179. D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
18180. D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
18181. D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
18182. D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
18183. D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
18184. D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
18185. D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
18186. D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
18187. D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
18188. D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
18189. D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
18190. D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
18191. D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
18192. D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
18193. D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
18194. D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
18195. D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
18196. D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
18197. D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
18198. D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
18199. D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
18200. D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
18201. D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
18202. D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
18203. D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
18204. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
18205. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
18206. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
18207. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
18208. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
18209. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
18210. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
18211. D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
18212. D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
18213. D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
18214. D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
18215. D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
18216. D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
18217. D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
18218. D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
18219. D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
18220. D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
18221. D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
18222. D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
18223. D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
18224. D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
18225. D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
18226. D3F5_PCIE_CAP_LIST__CAP_ID_MASK
18227. D3F5_PCIE_CAP_LIST__CAP_ID__SHIFT
18228. D3F5_PCIE_CAP_LIST__NEXT_PTR_MASK
18229. D3F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT
18230. D3F5_PCIE_CAP__DEVICE_TYPE_MASK
18231. D3F5_PCIE_CAP__DEVICE_TYPE__SHIFT
18232. D3F5_PCIE_CAP__INT_MESSAGE_NUM_MASK
18233. D3F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
18234. D3F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK
18235. D3F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
18236. D3F5_PCIE_CAP__VERSION_MASK
18237. D3F5_PCIE_CAP__VERSION__SHIFT
18238. D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
18239. D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
18240. D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
18241. D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
18242. D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
18243. D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
18244. D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
18245. D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
18246. D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
18247. D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
18248. D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
18249. D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
18250. D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
18251. D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
18252. D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
18253. D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
18254. D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
18255. D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
18256. D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
18257. D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
18258. D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
18259. D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
18260. D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
18261. D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
18262. D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
18263. D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
18264. D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
18265. D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
18266. D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
18267. D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
18268. D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
18269. D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
18270. D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
18271. D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
18272. D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
18273. D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
18274. D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
18275. D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
18276. D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
18277. D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
18278. D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
18279. D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
18280. D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
18281. D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
18282. D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
18283. D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
18284. D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
18285. D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
18286. D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
18287. D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
18288. D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
18289. D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
18290. D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
18291. D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
18292. D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
18293. D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
18294. D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
18295. D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
18296. D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
18297. D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
18298. D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
18299. D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
18300. D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
18301. D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
18302. D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
18303. D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
18304. D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
18305. D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
18306. D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
18307. D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
18308. D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
18309. D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
18310. D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
18311. D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
18312. D3F5_PCIE_FC_CPL__CPLD_CREDITS_MASK
18313. D3F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
18314. D3F5_PCIE_FC_CPL__CPLH_CREDITS_MASK
18315. D3F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
18316. D3F5_PCIE_FC_NP__NPD_CREDITS_MASK
18317. D3F5_PCIE_FC_NP__NPD_CREDITS__SHIFT
18318. D3F5_PCIE_FC_NP__NPH_CREDITS_MASK
18319. D3F5_PCIE_FC_NP__NPH_CREDITS__SHIFT
18320. D3F5_PCIE_FC_P__PD_CREDITS_MASK
18321. D3F5_PCIE_FC_P__PD_CREDITS__SHIFT
18322. D3F5_PCIE_FC_P__PH_CREDITS_MASK
18323. D3F5_PCIE_FC_P__PH_CREDITS__SHIFT
18324. D3F5_PCIE_HDR_LOG0__TLP_HDR_MASK
18325. D3F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT
18326. D3F5_PCIE_HDR_LOG1__TLP_HDR_MASK
18327. D3F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT
18328. D3F5_PCIE_HDR_LOG2__TLP_HDR_MASK
18329. D3F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT
18330. D3F5_PCIE_HDR_LOG3__TLP_HDR_MASK
18331. D3F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT
18332. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18333. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18334. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18335. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18336. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
18337. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
18338. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18339. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18340. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18341. D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18342. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18343. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18344. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18345. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18346. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
18347. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
18348. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18349. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18350. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18351. D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18352. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18353. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18354. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18355. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18356. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
18357. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
18358. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18359. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18360. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18361. D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18362. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18363. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18364. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18365. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18366. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
18367. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
18368. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18369. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18370. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18371. D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18372. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18373. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18374. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18375. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18376. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
18377. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
18378. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18379. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18380. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18381. D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18382. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18383. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18384. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18385. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18386. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
18387. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
18388. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18389. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18390. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18391. D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18392. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18393. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18394. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18395. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18396. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
18397. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
18398. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18399. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18400. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18401. D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18402. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18403. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18404. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18405. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18406. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
18407. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
18408. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18409. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18410. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18411. D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18412. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18413. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18414. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18415. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18416. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
18417. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
18418. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18419. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18420. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18421. D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18422. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18423. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18424. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18425. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18426. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
18427. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
18428. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18429. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18430. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18431. D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18432. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18433. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18434. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18435. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18436. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
18437. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
18438. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18439. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18440. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18441. D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18442. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18443. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18444. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18445. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18446. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
18447. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
18448. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18449. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18450. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18451. D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18452. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18453. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18454. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18455. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18456. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
18457. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
18458. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18459. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18460. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18461. D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18462. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18463. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18464. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18465. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18466. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
18467. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
18468. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18469. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18470. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18471. D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18472. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18473. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18474. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18475. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18476. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
18477. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
18478. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18479. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18480. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18481. D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18482. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
18483. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
18484. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
18485. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
18486. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
18487. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
18488. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
18489. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
18490. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
18491. D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
18492. D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
18493. D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
18494. D3F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
18495. D3F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
18496. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
18497. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
18498. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
18499. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
18500. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
18501. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
18502. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
18503. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
18504. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
18505. D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
18506. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
18507. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
18508. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
18509. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
18510. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
18511. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
18512. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
18513. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
18514. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
18515. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
18516. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
18517. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
18518. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
18519. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
18520. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
18521. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
18522. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
18523. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
18524. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
18525. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
18526. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
18527. D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
18528. D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
18529. D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
18530. D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
18531. D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
18532. D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
18533. D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
18534. D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
18535. D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
18536. D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
18537. D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
18538. D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
18539. D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
18540. D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
18541. D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
18542. D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
18543. D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
18544. D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
18545. D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
18546. D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
18547. D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
18548. D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
18549. D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
18550. D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
18551. D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
18552. D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
18553. D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
18554. D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
18555. D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
18556. D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
18557. D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
18558. D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
18559. D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
18560. D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
18561. D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
18562. D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
18563. D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
18564. D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
18565. D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
18566. D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
18567. D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
18568. D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
18569. D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
18570. D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
18571. D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
18572. D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
18573. D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
18574. D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
18575. D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
18576. D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
18577. D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
18578. D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
18579. D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
18580. D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
18581. D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
18582. D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
18583. D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
18584. D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
18585. D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
18586. D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
18587. D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
18588. D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
18589. D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
18590. D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
18591. D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
18592. D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
18593. D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
18594. D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
18595. D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
18596. D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
18597. D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
18598. D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
18599. D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
18600. D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
18601. D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
18602. D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
18603. D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
18604. D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
18605. D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
18606. D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
18607. D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
18608. D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
18609. D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
18610. D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
18611. D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
18612. D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
18613. D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
18614. D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
18615. D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
18616. D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
18617. D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
18618. D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
18619. D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
18620. D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
18621. D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
18622. D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
18623. D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
18624. D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
18625. D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
18626. D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
18627. D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
18628. D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
18629. D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
18630. D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
18631. D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
18632. D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
18633. D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
18634. D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
18635. D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
18636. D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
18637. D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
18638. D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
18639. D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
18640. D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
18641. D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
18642. D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
18643. D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
18644. D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
18645. D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
18646. D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
18647. D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
18648. D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
18649. D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
18650. D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
18651. D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
18652. D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
18653. D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
18654. D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
18655. D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
18656. D3F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
18657. D3F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
18658. D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
18659. D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
18660. D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
18661. D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
18662. D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
18663. D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
18664. D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
18665. D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
18666. D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
18667. D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
18668. D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
18669. D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
18670. D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
18671. D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
18672. D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
18673. D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
18674. D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
18675. D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
18676. D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
18677. D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
18678. D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
18679. D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
18680. D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
18681. D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
18682. D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
18683. D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
18684. D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
18685. D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
18686. D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
18687. D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
18688. D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
18689. D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
18690. D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
18691. D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
18692. D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
18693. D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
18694. D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
18695. D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
18696. D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
18697. D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
18698. D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
18699. D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
18700. D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
18701. D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
18702. D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
18703. D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
18704. D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
18705. D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
18706. D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
18707. D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
18708. D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
18709. D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
18710. D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
18711. D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
18712. D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
18713. D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
18714. D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
18715. D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
18716. D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
18717. D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
18718. D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
18719. D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
18720. D3F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK
18721. D3F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
18722. D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
18723. D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
18724. D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
18725. D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
18726. D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
18727. D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
18728. D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
18729. D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
18730. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
18731. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
18732. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
18733. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
18734. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
18735. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
18736. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
18737. D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
18738. D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
18739. D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
18740. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
18741. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
18742. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
18743. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
18744. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
18745. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
18746. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
18747. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
18748. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
18749. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
18750. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
18751. D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
18752. D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
18753. D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
18754. D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
18755. D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
18756. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
18757. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
18758. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
18759. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
18760. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
18761. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
18762. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
18763. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
18764. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
18765. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
18766. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
18767. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
18768. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
18769. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
18770. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
18771. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
18772. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
18773. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
18774. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
18775. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
18776. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
18777. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
18778. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
18779. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
18780. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
18781. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
18782. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
18783. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
18784. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
18785. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
18786. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
18787. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
18788. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
18789. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
18790. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
18791. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
18792. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
18793. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
18794. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
18795. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
18796. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
18797. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
18798. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
18799. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
18800. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
18801. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
18802. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
18803. D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
18804. D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
18805. D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
18806. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
18807. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
18808. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
18809. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
18810. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
18811. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
18812. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
18813. D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
18814. D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
18815. D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
18816. D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
18817. D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
18818. D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
18819. D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
18820. D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
18821. D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
18822. D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
18823. D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
18824. D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
18825. D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
18826. D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
18827. D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
18828. D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
18829. D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
18830. D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
18831. D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
18832. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
18833. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
18834. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
18835. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
18836. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
18837. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
18838. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
18839. D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
18840. D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
18841. D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
18842. D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
18843. D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
18844. D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
18845. D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
18846. D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
18847. D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
18848. D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
18849. D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
18850. D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
18851. D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
18852. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
18853. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
18854. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
18855. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
18856. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
18857. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
18858. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
18859. D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
18860. D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
18861. D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
18862. D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
18863. D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
18864. D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
18865. D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
18866. D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
18867. D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
18868. D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
18869. D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
18870. D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
18871. D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
18872. D3F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
18873. D3F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
18874. D3F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
18875. D3F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
18876. D3F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
18877. D3F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
18878. D3F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
18879. D3F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
18880. D3F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
18881. D3F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
18882. D3F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
18883. D3F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
18884. D3F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
18885. D3F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
18886. D3F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
18887. D3F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
18888. D3F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
18889. D3F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
18890. D3F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
18891. D3F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
18892. D3F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
18893. D3F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
18894. D3F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
18895. D3F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
18896. D3F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
18897. D3F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
18898. D3F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
18899. D3F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
18900. D3F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
18901. D3F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
18902. D3F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
18903. D3F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
18904. D3F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
18905. D3F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
18906. D3F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
18907. D3F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
18908. D3F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
18909. D3F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
18910. D3F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
18911. D3F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
18912. D3F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
18913. D3F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
18914. D3F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
18915. D3F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
18916. D3F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
18917. D3F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
18918. D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
18919. D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
18920. D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
18921. D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
18922. D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
18923. D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
18924. D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
18925. D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
18926. D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
18927. D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
18928. D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
18929. D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
18930. D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
18931. D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
18932. D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
18933. D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
18934. D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
18935. D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
18936. D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
18937. D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
18938. D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
18939. D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
18940. D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
18941. D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
18942. D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
18943. D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
18944. D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
18945. D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
18946. D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
18947. D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
18948. D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
18949. D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
18950. D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
18951. D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
18952. D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
18953. D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
18954. D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
18955. D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
18956. D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
18957. D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
18958. D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
18959. D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
18960. D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
18961. D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
18962. D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
18963. D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
18964. D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
18965. D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
18966. D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
18967. D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
18968. D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
18969. D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
18970. D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
18971. D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
18972. D3F5_PCIE_LINK_CNTL3__RESERVED_MASK
18973. D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT
18974. D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
18975. D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
18976. D3F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
18977. D3F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
18978. D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
18979. D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
18980. D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
18981. D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
18982. D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
18983. D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
18984. D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
18985. D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
18986. D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
18987. D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
18988. D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
18989. D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
18990. D3F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK
18991. D3F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
18992. D3F5_PCIE_MC_CNTL__MC_ENABLE_MASK
18993. D3F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT
18994. D3F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
18995. D3F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
18996. D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
18997. D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
18998. D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
18999. D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
19000. D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
19001. D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
19002. D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
19003. D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
19004. D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
19005. D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
19006. D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
19007. D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
19008. D3F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
19009. D3F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
19010. D3F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
19011. D3F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
19012. D3F5_PCIE_PORT_DATA__PCIE_DATA_MASK
19013. D3F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT
19014. D3F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK
19015. D3F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
19016. D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
19017. D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
19018. D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
19019. D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
19020. D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
19021. D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
19022. D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
19023. D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
19024. D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
19025. D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
19026. D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
19027. D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
19028. D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
19029. D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
19030. D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
19031. D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
19032. D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
19033. D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
19034. D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
19035. D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
19036. D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
19037. D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
19038. D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
19039. D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
19040. D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
19041. D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
19042. D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
19043. D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
19044. D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
19045. D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
19046. D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
19047. D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
19048. D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
19049. D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
19050. D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
19051. D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
19052. D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
19053. D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
19054. D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
19055. D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
19056. D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
19057. D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
19058. D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
19059. D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
19060. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
19061. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
19062. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
19063. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
19064. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
19065. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
19066. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
19067. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
19068. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
19069. D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
19070. D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
19071. D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
19072. D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
19073. D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
19074. D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
19075. D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
19076. D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
19077. D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
19078. D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
19079. D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
19080. D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
19081. D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
19082. D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
19083. D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
19084. D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
19085. D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
19086. D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
19087. D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
19088. D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
19089. D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
19090. D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
19091. D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
19092. D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
19093. D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
19094. D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
19095. D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
19096. D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
19097. D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
19098. D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
19099. D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
19100. D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
19101. D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
19102. D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
19103. D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
19104. D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
19105. D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
19106. D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
19107. D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
19108. D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
19109. D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
19110. D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
19111. D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
19112. D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
19113. D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
19114. D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
19115. D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
19116. D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
19117. D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
19118. D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
19119. D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
19120. D3F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK
19121. D3F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
19122. D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
19123. D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
19124. D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
19125. D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
19126. D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
19127. D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
19128. D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
19129. D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
19130. D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
19131. D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
19132. D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
19133. D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
19134. D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
19135. D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
19136. D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
19137. D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
19138. D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
19139. D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
19140. D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
19141. D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
19142. D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
19143. D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
19144. D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
19145. D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
19146. D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
19147. D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
19148. D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
19149. D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
19150. D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
19151. D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
19152. D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
19153. D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
19154. D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
19155. D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
19156. D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
19157. D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
19158. D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
19159. D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
19160. D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
19161. D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
19162. D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
19163. D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
19164. D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
19165. D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
19166. D3F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
19167. D3F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
19168. D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
19169. D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
19170. D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
19171. D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
19172. D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
19173. D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
19174. D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
19175. D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
19176. D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
19177. D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
19178. D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
19179. D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
19180. D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
19181. D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
19182. D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
19183. D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
19184. D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
19185. D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
19186. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
19187. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
19188. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
19189. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
19190. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
19191. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
19192. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
19193. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
19194. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
19195. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
19196. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
19197. D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
19198. D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
19199. D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
19200. D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
19201. D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
19202. D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
19203. D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
19204. D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
19205. D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
19206. D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
19207. D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
19208. D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
19209. D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
19210. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
19211. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
19212. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
19213. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
19214. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
19215. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
19216. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
19217. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
19218. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
19219. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
19220. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
19221. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
19222. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
19223. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
19224. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
19225. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
19226. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
19227. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
19228. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
19229. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
19230. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
19231. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
19232. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
19233. D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
19234. D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
19235. D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
19236. D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
19237. D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
19238. D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
19239. D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
19240. D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
19241. D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
19242. D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
19243. D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
19244. D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
19245. D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
19246. D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
19247. D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
19248. D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
19249. D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
19250. D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
19251. D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
19252. D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
19253. D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
19254. D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
19255. D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
19256. D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
19257. D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
19258. D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
19259. D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
19260. D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
19261. D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
19262. D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
19263. D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
19264. D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
19265. D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
19266. D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
19267. D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
19268. D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
19269. D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
19270. D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
19271. D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
19272. D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
19273. D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
19274. D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
19275. D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
19276. D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
19277. D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
19278. D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
19279. D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
19280. D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
19281. D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
19282. D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
19283. D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
19284. D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
19285. D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
19286. D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
19287. D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
19288. D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
19289. D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
19290. D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
19291. D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
19292. D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
19293. D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
19294. D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
19295. D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
19296. D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
19297. D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
19298. D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
19299. D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
19300. D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
19301. D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
19302. D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
19303. D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
19304. D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
19305. D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
19306. D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
19307. D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
19308. D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
19309. D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
19310. D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
19311. D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
19312. D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
19313. D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
19314. D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
19315. D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
19316. D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
19317. D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
19318. D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
19319. D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
19320. D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
19321. D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
19322. D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
19323. D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
19324. D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
19325. D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
19326. D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
19327. D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
19328. D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
19329. D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
19330. D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
19331. D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
19332. D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
19333. D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
19334. D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
19335. D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
19336. D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
19337. D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
19338. D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
19339. D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
19340. D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
19341. D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
19342. D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
19343. D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
19344. D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
19345. D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
19346. D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
19347. D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
19348. D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
19349. D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
19350. D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
19351. D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
19352. D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
19353. D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
19354. D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
19355. D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
19356. D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
19357. D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
19358. D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
19359. D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
19360. D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
19361. D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
19362. D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
19363. D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
19364. D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
19365. D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
19366. D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
19367. D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
19368. D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
19369. D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
19370. D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
19371. D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
19372. D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
19373. D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
19374. D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
19375. D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
19376. D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
19377. D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
19378. D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
19379. D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
19380. D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
19381. D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
19382. D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
19383. D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
19384. D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
19385. D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
19386. D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
19387. D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
19388. D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
19389. D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
19390. D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
19391. D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
19392. D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
19393. D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
19394. D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
19395. D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
19396. D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
19397. D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
19398. D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
19399. D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
19400. D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
19401. D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
19402. D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
19403. D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
19404. D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
19405. D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
19406. D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
19407. D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
19408. D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
19409. D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
19410. D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
19411. D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
19412. D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
19413. D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
19414. D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
19415. D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
19416. D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
19417. D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
19418. D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
19419. D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
19420. D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
19421. D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
19422. D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
19423. D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
19424. D3F5_PMI_CAP_LIST__CAP_ID_MASK
19425. D3F5_PMI_CAP_LIST__CAP_ID__SHIFT
19426. D3F5_PMI_CAP_LIST__NEXT_PTR_MASK
19427. D3F5_PMI_CAP_LIST__NEXT_PTR__SHIFT
19428. D3F5_PMI_CAP__AUX_CURRENT_MASK
19429. D3F5_PMI_CAP__AUX_CURRENT__SHIFT
19430. D3F5_PMI_CAP__D1_SUPPORT_MASK
19431. D3F5_PMI_CAP__D1_SUPPORT__SHIFT
19432. D3F5_PMI_CAP__D2_SUPPORT_MASK
19433. D3F5_PMI_CAP__D2_SUPPORT__SHIFT
19434. D3F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK
19435. D3F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
19436. D3F5_PMI_CAP__PME_CLOCK_MASK
19437. D3F5_PMI_CAP__PME_CLOCK__SHIFT
19438. D3F5_PMI_CAP__PME_SUPPORT_MASK
19439. D3F5_PMI_CAP__PME_SUPPORT__SHIFT
19440. D3F5_PMI_CAP__VERSION_MASK
19441. D3F5_PMI_CAP__VERSION__SHIFT
19442. D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
19443. D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
19444. D3F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
19445. D3F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
19446. D3F5_PMI_STATUS_CNTL__DATA_SCALE_MASK
19447. D3F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
19448. D3F5_PMI_STATUS_CNTL__DATA_SELECT_MASK
19449. D3F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
19450. D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
19451. D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
19452. D3F5_PMI_STATUS_CNTL__PME_EN_MASK
19453. D3F5_PMI_STATUS_CNTL__PME_EN__SHIFT
19454. D3F5_PMI_STATUS_CNTL__PME_STATUS_MASK
19455. D3F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT
19456. D3F5_PMI_STATUS_CNTL__PMI_DATA_MASK
19457. D3F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT
19458. D3F5_PMI_STATUS_CNTL__POWER_STATE_MASK
19459. D3F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT
19460. D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
19461. D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
19462. D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
19463. D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
19464. D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
19465. D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
19466. D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
19467. D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
19468. D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
19469. D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
19470. D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
19471. D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
19472. D3F5_PROG_INTERFACE__PROG_INTERFACE_MASK
19473. D3F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT
19474. D3F5_REVISION_ID__MAJOR_REV_ID_MASK
19475. D3F5_REVISION_ID__MAJOR_REV_ID__SHIFT
19476. D3F5_REVISION_ID__MINOR_REV_ID_MASK
19477. D3F5_REVISION_ID__MINOR_REV_ID__SHIFT
19478. D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
19479. D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
19480. D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
19481. D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
19482. D3F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK
19483. D3F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
19484. D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
19485. D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
19486. D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
19487. D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
19488. D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
19489. D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
19490. D3F5_ROOT_STATUS__PME_PENDING_MASK
19491. D3F5_ROOT_STATUS__PME_PENDING__SHIFT
19492. D3F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK
19493. D3F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
19494. D3F5_ROOT_STATUS__PME_STATUS_MASK
19495. D3F5_ROOT_STATUS__PME_STATUS__SHIFT
19496. D3F5_SECONDARY_STATUS__CAP_LIST_MASK
19497. D3F5_SECONDARY_STATUS__CAP_LIST__SHIFT
19498. D3F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK
19499. D3F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
19500. D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
19501. D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
19502. D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
19503. D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
19504. D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
19505. D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
19506. D3F5_SECONDARY_STATUS__PCI_66_EN_MASK
19507. D3F5_SECONDARY_STATUS__PCI_66_EN__SHIFT
19508. D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
19509. D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
19510. D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
19511. D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
19512. D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
19513. D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
19514. D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
19515. D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
19516. D3F5_SLOT_CAP2__RESERVED_MASK
19517. D3F5_SLOT_CAP2__RESERVED__SHIFT
19518. D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
19519. D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
19520. D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
19521. D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
19522. D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
19523. D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
19524. D3F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK
19525. D3F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
19526. D3F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK
19527. D3F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
19528. D3F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
19529. D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
19530. D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
19531. D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
19532. D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
19533. D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
19534. D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
19535. D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
19536. D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
19537. D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
19538. D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
19539. D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
19540. D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
19541. D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
19542. D3F5_SLOT_CNTL2__RESERVED_MASK
19543. D3F5_SLOT_CNTL2__RESERVED__SHIFT
19544. D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
19545. D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
19546. D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
19547. D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
19548. D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
19549. D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
19550. D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
19551. D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
19552. D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
19553. D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
19554. D3F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
19555. D3F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
19556. D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
19557. D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
19558. D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
19559. D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
19560. D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
19561. D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
19562. D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
19563. D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
19564. D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
19565. D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
19566. D3F5_SLOT_STATUS2__RESERVED_MASK
19567. D3F5_SLOT_STATUS2__RESERVED__SHIFT
19568. D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
19569. D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
19570. D3F5_SLOT_STATUS__COMMAND_COMPLETED_MASK
19571. D3F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
19572. D3F5_SLOT_STATUS__DL_STATE_CHANGED_MASK
19573. D3F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
19574. D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
19575. D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
19576. D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
19577. D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
19578. D3F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK
19579. D3F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
19580. D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
19581. D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
19582. D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
19583. D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
19584. D3F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
19585. D3F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
19586. D3F5_SSID_CAP_LIST__CAP_ID_MASK
19587. D3F5_SSID_CAP_LIST__CAP_ID__SHIFT
19588. D3F5_SSID_CAP_LIST__NEXT_PTR_MASK
19589. D3F5_SSID_CAP_LIST__NEXT_PTR__SHIFT
19590. D3F5_SSID_CAP__SUBSYSTEM_ID_MASK
19591. D3F5_SSID_CAP__SUBSYSTEM_ID__SHIFT
19592. D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
19593. D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
19594. D3F5_STATUS__CAP_LIST_MASK
19595. D3F5_STATUS__CAP_LIST__SHIFT
19596. D3F5_STATUS__DEVSEL_TIMING_MASK
19597. D3F5_STATUS__DEVSEL_TIMING__SHIFT
19598. D3F5_STATUS__FAST_BACK_CAPABLE_MASK
19599. D3F5_STATUS__FAST_BACK_CAPABLE__SHIFT
19600. D3F5_STATUS__INT_STATUS_MASK
19601. D3F5_STATUS__INT_STATUS__SHIFT
19602. D3F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK
19603. D3F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
19604. D3F5_STATUS__PARITY_ERROR_DETECTED_MASK
19605. D3F5_STATUS__PARITY_ERROR_DETECTED__SHIFT
19606. D3F5_STATUS__PCI_66_EN_MASK
19607. D3F5_STATUS__PCI_66_EN__SHIFT
19608. D3F5_STATUS__RECEIVED_MASTER_ABORT_MASK
19609. D3F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT
19610. D3F5_STATUS__RECEIVED_TARGET_ABORT_MASK
19611. D3F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT
19612. D3F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK
19613. D3F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
19614. D3F5_STATUS__SIGNAL_TARGET_ABORT_MASK
19615. D3F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT
19616. D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
19617. D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
19618. D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
19619. D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
19620. D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
19621. D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
19622. D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
19623. D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
19624. D3F5_SUB_CLASS__SUB_CLASS_MASK
19625. D3F5_SUB_CLASS__SUB_CLASS__SHIFT
19626. D3F5_VENDOR_ID__VENDOR_ID_MASK
19627. D3F5_VENDOR_ID__VENDOR_ID__SHIFT
19628. D3FIFOCTR
19629. D3FIFOSEL
19630. D3HOTSequence_e
19631. D3HOT_SEQUENCE_COUNT
19632. D3RS3EN
19633. D3S_PRE
19634. D3S_PREP
19635. D3S_ZERO
19636. D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK
19637. D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT
19638. D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK
19639. D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT
19640. D3VGA_CONTROL__D3VGA_ROTATE_MASK
19641. D3VGA_CONTROL__D3VGA_ROTATE__SHIFT
19642. D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK
19643. D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT
19644. D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK
19645. D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT
19646. D3W_CNTRL
19647. D3W_DPHYCONTRX
19648. D3_7XX_KBC1
19649. D3_CLK_GATED_EN
19650. D3_CONFIG_CMD
19651. D3_DELINK_MODE_EN
19652. D3_MARK
19653. D3_NAF3_MARK
19654. D4
19655. D40_ACTIVATE_EVENTLINE
19656. D40_AD8_DG2_MARK
19657. D40_ALLOC_FREE
19658. D40_ALLOC_LOG_FREE
19659. D40_ALLOC_PHY
19660. D40_CHAN_POS
19661. D40_CHAN_POS_MASK
19662. D40_CHAN_REG_SDCFG
19663. D40_CHAN_REG_SDELT
19664. D40_CHAN_REG_SDLNK
19665. D40_CHAN_REG_SDPTR
19666. D40_CHAN_REG_SSCFG
19667. D40_CHAN_REG_SSELT
19668. D40_CHAN_REG_SSLNK
19669. D40_CHAN_REG_SSPTR
19670. D40_DEACTIVATE_EVENTLINE
19671. D40_DMA_RUN
19672. D40_DMA_STOP
19673. D40_DMA_SUSPENDED
19674. D40_DMA_SUSPEND_REQ
19675. D40_DREG_ACTIVE
19676. D40_DREG_ACTIVO
19677. D40_DREG_CELLID0
19678. D40_DREG_CELLID1
19679. D40_DREG_CELLID2
19680. D40_DREG_CELLID3
19681. D40_DREG_CFSEBS1
19682. D40_DREG_CFSEBS2
19683. D40_DREG_CFSEBS3
19684. D40_DREG_CFSESS1
19685. D40_DREG_CFSESS2
19686. D40_DREG_CFSESS3
19687. D40_DREG_CIDMOD
19688. D40_DREG_CLCEIS1
19689. D40_DREG_CLCEIS2
19690. D40_DREG_CLCEIS3
19691. D40_DREG_CLCEIS4
19692. D40_DREG_CLCEIS5
19693. D40_DREG_CLCICR1
19694. D40_DREG_CLCICR2
19695. D40_DREG_CLCICR3
19696. D40_DREG_CLCICR4
19697. D40_DREG_CLCICR5
19698. D40_DREG_CLCMIS1
19699. D40_DREG_CLCMIS2
19700. D40_DREG_CLCMIS3
19701. D40_DREG_CLCMIS4
19702. D40_DREG_CLCMIS5
19703. D40_DREG_CLCTIS1
19704. D40_DREG_CLCTIS2
19705. D40_DREG_CLCTIS3
19706. D40_DREG_CLCTIS4
19707. D40_DREG_CLCTIS5
19708. D40_DREG_CPCEG1
19709. D40_DREG_CPCEG2
19710. D40_DREG_CPCEG3
19711. D40_DREG_CPCEG4
19712. D40_DREG_CPCEG5
19713. D40_DREG_CPCEIS
19714. D40_DREG_CPCICR
19715. D40_DREG_CPCMIS
19716. D40_DREG_CPCTIS
19717. D40_DREG_CPSEG1
19718. D40_DREG_CPSEG2
19719. D40_DREG_CPSEG3
19720. D40_DREG_CPSEG4
19721. D40_DREG_CPSEG5
19722. D40_DREG_CRCEG1
19723. D40_DREG_CRCEG2
19724. D40_DREG_CRCEG3
19725. D40_DREG_CRCEG4
19726. D40_DREG_CRCEG5
19727. D40_DREG_CRSEG1
19728. D40_DREG_CRSEG2
19729. D40_DREG_CRSEG3
19730. D40_DREG_CRSEG4
19731. D40_DREG_CRSEG5
19732. D40_DREG_EXTCFG
19733. D40_DREG_FSEBS1
19734. D40_DREG_FSEBS2
19735. D40_DREG_FSESS1
19736. D40_DREG_FSESS2
19737. D40_DREG_GCC
19738. D40_DREG_GCC_DST
19739. D40_DREG_GCC_ENA
19740. D40_DREG_GCC_ENABLE_ALL
19741. D40_DREG_GCC_EVTGRP_ENA
19742. D40_DREG_GCC_EVTGRP_POS
19743. D40_DREG_GCC_SRC
19744. D40_DREG_ICFG
19745. D40_DREG_LCEIS0
19746. D40_DREG_LCEIS1
19747. D40_DREG_LCEIS2
19748. D40_DREG_LCEIS3
19749. D40_DREG_LCICR0
19750. D40_DREG_LCICR1
19751. D40_DREG_LCICR2
19752. D40_DREG_LCICR3
19753. D40_DREG_LCLA
19754. D40_DREG_LCMIS0
19755. D40_DREG_LCMIS1
19756. D40_DREG_LCMIS2
19757. D40_DREG_LCMIS3
19758. D40_DREG_LCPA
19759. D40_DREG_LCTIS0
19760. D40_DREG_LCTIS1
19761. D40_DREG_LCTIS2
19762. D40_DREG_LCTIS3
19763. D40_DREG_PCBASE
19764. D40_DREG_PCDELTA
19765. D40_DREG_PCEG1
19766. D40_DREG_PCEG2
19767. D40_DREG_PCEG3
19768. D40_DREG_PCEG4
19769. D40_DREG_PCEIS
19770. D40_DREG_PCICR
19771. D40_DREG_PCMIS
19772. D40_DREG_PCTIS
19773. D40_DREG_PERIPHID0
19774. D40_DREG_PERIPHID1
19775. D40_DREG_PERIPHID2
19776. D40_DREG_PERIPHID3
19777. D40_DREG_PREFOT
19778. D40_DREG_PRMOE
19779. D40_DREG_PRMOO
19780. D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
19781. D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
19782. D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
19783. D40_DREG_PRMO_PCHAN_BASIC
19784. D40_DREG_PRMO_PCHAN_DOUBLE_DST
19785. D40_DREG_PRMO_PCHAN_MODULO
19786. D40_DREG_PRMSE
19787. D40_DREG_PRMSO
19788. D40_DREG_PRSCCIDA
19789. D40_DREG_PRSCCIDB
19790. D40_DREG_PRSME
19791. D40_DREG_PRSMO
19792. D40_DREG_PRTYP
19793. D40_DREG_PSEG1
19794. D40_DREG_PSEG2
19795. D40_DREG_PSEG3
19796. D40_DREG_PSEG4
19797. D40_DREG_RCEG1
19798. D40_DREG_RCEG2
19799. D40_DREG_RCEG3
19800. D40_DREG_RCEG4
19801. D40_DREG_RSEG1
19802. D40_DREG_RSEG2
19803. D40_DREG_RSEG3
19804. D40_DREG_RSEG4
19805. D40_DREG_SCCIDA1
19806. D40_DREG_SCCIDA2
19807. D40_DREG_SCCIDA3
19808. D40_DREG_SCCIDA4
19809. D40_DREG_SCCIDA5
19810. D40_DREG_SCCIDB1
19811. D40_DREG_SCCIDB2
19812. D40_DREG_SCCIDB3
19813. D40_DREG_SCCIDB4
19814. D40_DREG_SCCIDB5
19815. D40_DREG_SCEG1
19816. D40_DREG_SCEG2
19817. D40_DREG_SCEG3
19818. D40_DREG_SCEG4
19819. D40_DREG_SLCEIS1
19820. D40_DREG_SLCEIS2
19821. D40_DREG_SLCEIS3
19822. D40_DREG_SLCEIS4
19823. D40_DREG_SLCICR1
19824. D40_DREG_SLCICR2
19825. D40_DREG_SLCICR3
19826. D40_DREG_SLCICR4
19827. D40_DREG_SLCMIS1
19828. D40_DREG_SLCMIS2
19829. D40_DREG_SLCMIS3
19830. D40_DREG_SLCMIS4
19831. D40_DREG_SLCTIS1
19832. D40_DREG_SLCTIS2
19833. D40_DREG_SLCTIS3
19834. D40_DREG_SLCTIS4
19835. D40_DREG_SPCEIS
19836. D40_DREG_SPCICR
19837. D40_DREG_SPCMIS
19838. D40_DREG_SPCTIS
19839. D40_DREG_SSEG1
19840. D40_DREG_SSEG2
19841. D40_DREG_SSEG3
19842. D40_DREG_SSEG4
19843. D40_DREG_STFU
19844. D40_DREG_TCIDV
19845. D40_DT_FLAGS_BIG_ENDIAN
19846. D40_DT_FLAGS_DIR
19847. D40_DT_FLAGS_FIXED_CHAN
19848. D40_DT_FLAGS_HIGH_PRIO
19849. D40_DT_FLAGS_MODE
19850. D40_EVENTLINE_MASK
19851. D40_EVENTLINE_POS
19852. D40_GROUP_SIZE
19853. D40_LCLA_END
19854. D40_LCLA_LINK_PER_EVENT_GRP
19855. D40_LCPA_CHAN_DST_DELTA
19856. D40_LCPA_CHAN_SIZE
19857. D40_LLI_ALIGN
19858. D40_MAX_LOG_CHAN_PER_PHY
19859. D40_MEMCPY_MAX_CHANS
19860. D40_MEM_LCSP0_ECNT_MASK
19861. D40_MEM_LCSP0_ECNT_POS
19862. D40_MEM_LCSP0_SPTR_MASK
19863. D40_MEM_LCSP0_SPTR_POS
19864. D40_MEM_LCSP1_SCFG_EIM_POS
19865. D40_MEM_LCSP1_SCFG_ESIZE_POS
19866. D40_MEM_LCSP1_SCFG_INCR_MASK
19867. D40_MEM_LCSP1_SCFG_INCR_POS
19868. D40_MEM_LCSP1_SCFG_MST_POS
19869. D40_MEM_LCSP1_SCFG_PSIZE_MASK
19870. D40_MEM_LCSP1_SCFG_PSIZE_POS
19871. D40_MEM_LCSP1_SCFG_TIM_MASK
19872. D40_MEM_LCSP1_SCFG_TIM_POS
19873. D40_MEM_LCSP1_SLOS_MASK
19874. D40_MEM_LCSP1_SLOS_POS
19875. D40_MEM_LCSP1_SPTR_MASK
19876. D40_MEM_LCSP1_SPTR_POS
19877. D40_MEM_LCSP1_STCP_MASK
19878. D40_MEM_LCSP1_STCP_POS
19879. D40_MEM_LCSP2_ECNT_MASK
19880. D40_MEM_LCSP2_ECNT_POS
19881. D40_MEM_LCSP3_DCFG_EIM_POS
19882. D40_MEM_LCSP3_DCFG_ESIZE_POS
19883. D40_MEM_LCSP3_DCFG_INCR_POS
19884. D40_MEM_LCSP3_DCFG_MST_POS
19885. D40_MEM_LCSP3_DCFG_PSIZE_POS
19886. D40_MEM_LCSP3_DCFG_TIM_POS
19887. D40_MEM_LCSP3_DLOS_MASK
19888. D40_MEM_LCSP3_DLOS_POS
19889. D40_MEM_LCSP3_DTCP_MASK
19890. D40_MEM_LCSP3_DTCP_POS
19891. D40_NAME
19892. D40_PHYS_TO_GROUP
19893. D40_PHY_CHAN
19894. D40_ROUND_EVENTLINE
19895. D40_SREG_CFG_EIM_POS
19896. D40_SREG_CFG_ESIZE_POS
19897. D40_SREG_CFG_LBE_POS
19898. D40_SREG_CFG_LOG_GIM_POS
19899. D40_SREG_CFG_LOG_INCR_POS
19900. D40_SREG_CFG_LOG_MFU_POS
19901. D40_SREG_CFG_MST_POS
19902. D40_SREG_CFG_PHY_EVTL_POS
19903. D40_SREG_CFG_PHY_PEN_POS
19904. D40_SREG_CFG_PHY_TM_POS
19905. D40_SREG_CFG_PRI_POS
19906. D40_SREG_CFG_PSIZE_POS
19907. D40_SREG_CFG_TIM_POS
19908. D40_SREG_ELEM_LOG_ECNT_POS
19909. D40_SREG_ELEM_LOG_LIDX_MASK
19910. D40_SREG_ELEM_LOG_LIDX_POS
19911. D40_SREG_ELEM_LOG_LOS_POS
19912. D40_SREG_ELEM_LOG_TCP_POS
19913. D40_SREG_ELEM_PHY_ECNT_MASK
19914. D40_SREG_ELEM_PHY_ECNT_POS
19915. D40_SREG_ELEM_PHY_EIDX_POS
19916. D40_SREG_LNK_PHYS_LNK_MASK
19917. D40_SREG_LNK_PHY_LMP_POS
19918. D40_SREG_LNK_PHY_PRE_POS
19919. D40_SREG_LNK_PHY_TCP_POS
19920. D40_SUSPEND_MAX_IT
19921. D40_SUSPEND_REQ_EVENTLINE
19922. D40_TYPE_TO_EVENT
19923. D40_TYPE_TO_GROUP
19924. D41_AD9_DG3_MARK
19925. D42_AD10_DG4_MARK
19926. D43_AD11_DG5_MARK
19927. D44_AD12_DB0_MARK
19928. D45_AD13_DB1_MARK
19929. D46_AD14_DB2_MARK
19930. D47_AD15_DB3_MARK
19931. D48_AD16_DB4_MARK
19932. D49_AD17_DB5_MARK
19933. D4C
19934. D4M3
19935. D4M4
19936. D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK
19937. D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT
19938. D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK
19939. D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT
19940. D4VGA_CONTROL__D4VGA_ROTATE_MASK
19941. D4VGA_CONTROL__D4VGA_ROTATE__SHIFT
19942. D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK
19943. D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT
19944. D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK
19945. D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT
19946. D4_MARK
19947. D4_NAF4_MARK
19948. D5
19949. D50_AD18_MARK
19950. D51_AD19_MARK
19951. D52_AD20_MARK
19952. D53_AD21_MARK
19953. D54_AD22_MARK
19954. D55_AD23_MARK
19955. D56_AD24_MARK
19956. D57_AD25_MARK
19957. D58_AD26_MARK
19958. D59_AD27_MARK
19959. D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK
19960. D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT
19961. D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK
19962. D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT
19963. D5VGA_CONTROL__D5VGA_ROTATE_MASK
19964. D5VGA_CONTROL__D5VGA_ROTATE__SHIFT
19965. D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK
19966. D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT
19967. D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK
19968. D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT
19969. D5_MARK
19970. D5_NAF5_MARK
19971. D6
19972. D60_AD28_MARK
19973. D61_AD29_MARK
19974. D62_AD30_MARK
19975. D63_AD31_MARK
19976. D64MAXDD
19977. D64MAXRINGSZ
19978. D64RINGALIGN
19979. D64RINGALIGN_BITS
19980. D64_CTRL1_EOF
19981. D64_CTRL1_EOT
19982. D64_CTRL1_IOC
19983. D64_CTRL1_SOF
19984. D64_CTRL2_AE
19985. D64_CTRL2_AE_SHIFT
19986. D64_CTRL2_BC_MASK
19987. D64_CTRL2_PARITY
19988. D64_CTRL_COREFLAGS
19989. D64_CTRL_CORE_MASK
19990. D64_FA_OFF_MASK
19991. D64_FA_SEL_MASK
19992. D64_FA_SEL_RDD
19993. D64_FA_SEL_RDP
19994. D64_FA_SEL_RFD
19995. D64_FA_SEL_RFP
19996. D64_FA_SEL_RSD
19997. D64_FA_SEL_RSP
19998. D64_FA_SEL_SHIFT
19999. D64_FA_SEL_XDD
20000. D64_FA_SEL_XDP
20001. D64_FA_SEL_XFD
20002. D64_FA_SEL_XFP
20003. D64_RC_AE
20004. D64_RC_AE_SHIFT
20005. D64_RC_FM
20006. D64_RC_OC
20007. D64_RC_PD
20008. D64_RC_RE
20009. D64_RC_RO_MASK
20010. D64_RC_RO_SHIFT
20011. D64_RC_SH
20012. D64_RP_LD_MASK
20013. D64_RS0_CD_MASK
20014. D64_RS0_RS_ACTIVE
20015. D64_RS0_RS_DISABLED
20016. D64_RS0_RS_IDLE
20017. D64_RS0_RS_MASK
20018. D64_RS0_RS_SHIFT
20019. D64_RS0_RS_STOPPED
20020. D64_RS0_RS_SUSP
20021. D64_RS1_AD_MASK
20022. D64_RS1_RE_COREE
20023. D64_RS1_RE_DESRE
20024. D64_RS1_RE_DFU
20025. D64_RS1_RE_DPO
20026. D64_RS1_RE_DTE
20027. D64_RS1_RE_MASK
20028. D64_RS1_RE_NOERR
20029. D64_RS1_RE_SHIFT
20030. D64_RX_FRM_STS_DATATYPE
20031. D64_RX_FRM_STS_DSCRCNT
20032. D64_RX_FRM_STS_LEN
20033. D64_RX_FRM_STS_OVFL
20034. D64_XC_AE
20035. D64_XC_AE_SHIFT
20036. D64_XC_FL
20037. D64_XC_LE
20038. D64_XC_PD
20039. D64_XC_SE
20040. D64_XC_XE
20041. D64_XP_LD_MASK
20042. D64_XS0_CD_MASK
20043. D64_XS0_XS_ACTIVE
20044. D64_XS0_XS_DISABLED
20045. D64_XS0_XS_IDLE
20046. D64_XS0_XS_MASK
20047. D64_XS0_XS_SHIFT
20048. D64_XS0_XS_STOPPED
20049. D64_XS0_XS_SUSP
20050. D64_XS1_AD_MASK
20051. D64_XS1_XE_COREE
20052. D64_XS1_XE_DESRE
20053. D64_XS1_XE_DFU
20054. D64_XS1_XE_DPE
20055. D64_XS1_XE_DTE
20056. D64_XS1_XE_MASK
20057. D64_XS1_XE_NOERR
20058. D64_XS1_XE_SHIFT
20059. D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK
20060. D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT
20061. D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK
20062. D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT
20063. D6VGA_CONTROL__D6VGA_ROTATE_MASK
20064. D6VGA_CONTROL__D6VGA_ROTATE__SHIFT
20065. D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK
20066. D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT
20067. D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK
20068. D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT
20069. D6_MARK
20070. D6_NAF6_MARK
20071. D7
20072. D71_BLK_TYPE_AEU
20073. D71_BLK_TYPE_AEU_AES
20074. D71_BLK_TYPE_AEU_DS
20075. D71_BLK_TYPE_AEU_TRUSTED
20076. D71_BLK_TYPE_CU
20077. D71_BLK_TYPE_CU_MERGER
20078. D71_BLK_TYPE_CU_SCALER
20079. D71_BLK_TYPE_CU_SPLITTER
20080. D71_BLK_TYPE_DOU
20081. D71_BLK_TYPE_DOU_BS
20082. D71_BLK_TYPE_DOU_FT_COEFF
20083. D71_BLK_TYPE_DOU_IPS
20084. D71_BLK_TYPE_GCU
20085. D71_BLK_TYPE_GLB_LT_COEFF
20086. D71_BLK_TYPE_GLB_SCL_COEFF
20087. D71_BLK_TYPE_GLB_SC_COEFF
20088. D71_BLK_TYPE_LPU
20089. D71_BLK_TYPE_LPU_LAYER
20090. D71_BLK_TYPE_LPU_TRUSTED
20091. D71_BLK_TYPE_LPU_WB_LAYER
20092. D71_BLK_TYPE_PERIPH
20093. D71_BLK_TYPE_RESERVED
20094. D71_BLOCK_MAX_INPUT
20095. D71_BLOCK_MAX_OUTPUT
20096. D71_BLOCK_OFFSET_PERIPH
20097. D71_BLOCK_SIZE
20098. D71_BS_CONTROL_DEFAULT
20099. D71_BUS_WIDTH_16_BYTES
20100. D71_DEFAULT_PREPRETCH_LINE
20101. D71_LAYER_CONTROL_DEFAULT
20102. D71_MAX_GLB_IT_COEFF
20103. D71_MAX_GLB_SCL_COEFF
20104. D71_MAX_LAYERS_PER_LPU
20105. D71_MAX_PIPELINE
20106. D71_MAX_SC_PER_CU
20107. D71_MG_MAX_MERGED_HSIZE
20108. D71_MG_MAX_MERGED_VSIZE
20109. D71_MG_MIN_MERGED_SIZE
20110. D71_MIN_LINE_SIZE
20111. D71_MIN_VERTICAL_SIZE
20112. D71_PALPHA_DEF_MAP
20113. D71_PIPELINE_MAX_LAYERS
20114. D71_PIPELINE_MAX_SCALERS
20115. D71_SC_ENH_SPLIT_OVERLAP
20116. D71_SC_MAX_DOWNSCALING
20117. D71_SC_MAX_LIN_SIZE
20118. D71_SC_MAX_UPSCALING
20119. D71_SC_MAX_VERTICAL_SIZE
20120. D71_SC_MIN_LIN_SIZE
20121. D71_SC_MIN_VERTICAL_SIZE
20122. D71_SC_SPLIT_OVERLAP
20123. D71_WB_LAYER_CONTROL_DEFAULT
20124. D7ALSEN
20125. D7SIOCRD
20126. D7SIOCTM
20127. D7SIOCWR
20128. D7S_0
20129. D7S_1
20130. D7S_2
20131. D7S_3
20132. D7S_4
20133. D7S_5
20134. D7S_6
20135. D7S_7
20136. D7S_8
20137. D7S_9
20138. D7S_A
20139. D7S_ALARM
20140. D7S_B
20141. D7S_BLANK
20142. D7S_C
20143. D7S_D
20144. D7S_E
20145. D7S_E2
20146. D7S_F
20147. D7S_FLIP
20148. D7S_H
20149. D7S_IOC
20150. D7S_L
20151. D7S_MAX_VAL
20152. D7S_MINOR
20153. D7S_MIN_VAL
20154. D7S_P
20155. D7S_POINT
20156. D7S_SEGA
20157. D7S_SEGABFG
20158. D7S_SEGADG
20159. D7S_SEGB
20160. D7S_SEGBCEF
20161. D7S_SEGC
20162. D7S_SEGCDEG
20163. D7S_SEGD
20164. D7S_SEGE
20165. D7S_SEGF
20166. D7S_SEGG
20167. D7_MARK
20168. D7_NAF7_MARK
20169. D8
20170. D8E
20171. D8_MARK
20172. D8_NAF8_MARK
20173. D9
20174. D9_MARK
20175. D9_NAF9_MARK
20176. DA
20177. DA0
20178. DA0_MARK
20179. DA1
20180. DA1_MARK
20181. DA2
20182. DA280_CHANNEL
20183. DA280_CHIP_ID
20184. DA280_MODE_DISABLE
20185. DA280_MODE_ENABLE
20186. DA280_REG_ACC_X_LSB
20187. DA280_REG_ACC_Y_LSB
20188. DA280_REG_ACC_Z_LSB
20189. DA280_REG_CHIP_ID
20190. DA280_REG_MODE_BW
20191. DA311_CHANNEL
20192. DA311_CHIP_ID
20193. DA311_REG_BANK
20194. DA311_REG_CHIP_ID
20195. DA311_REG_CLICK_CFG
20196. DA311_REG_CLICK_SRC
20197. DA311_REG_CLICK_THS
20198. DA311_REG_CTRL_REG1
20199. DA311_REG_CTRL_REG3
20200. DA311_REG_CTRL_REG4
20201. DA311_REG_CTRL_REG5
20202. DA311_REG_CTRL_REG6
20203. DA311_REG_INT1_CFG
20204. DA311_REG_INT1_DURATION
20205. DA311_REG_INT1_SRC
20206. DA311_REG_INT1_THS
20207. DA311_REG_INT2_CFG
20208. DA311_REG_INT2_DURATION
20209. DA311_REG_INT2_SRC
20210. DA311_REG_INT2_THS
20211. DA311_REG_LDO_REG
20212. DA311_REG_LPF_ABSOLUTE
20213. DA311_REG_OTP_TRIM_OSC
20214. DA311_REG_OTP_TRIM_THERM_H
20215. DA311_REG_OTP_XOFF_H
20216. DA311_REG_OTP_XOFF_L
20217. DA311_REG_OTP_XSO
20218. DA311_REG_OTP_YOFF_H
20219. DA311_REG_OTP_YOFF_L
20220. DA311_REG_OTP_YSO
20221. DA311_REG_OTP_ZOFF_H
20222. DA311_REG_OTP_ZOFF_L
20223. DA311_REG_OTP_ZSO
20224. DA311_REG_OUT_X_H
20225. DA311_REG_OUT_X_L
20226. DA311_REG_OUT_Y_H
20227. DA311_REG_OUT_Y_L
20228. DA311_REG_OUT_Z_H
20229. DA311_REG_OUT_Z_L
20230. DA311_REG_SOFT_RESET
20231. DA311_REG_STATUS_REG
20232. DA311_REG_TEMP_CFG_REG
20233. DA311_REG_TEMP_OFF1
20234. DA311_REG_TEMP_OFF2
20235. DA311_REG_TEMP_OFF3
20236. DA311_REG_TIME_LATENCY
20237. DA311_REG_TIME_LIMIT
20238. DA311_REG_TIME_WINDOW
20239. DA7210_ADC
20240. DA7210_ADC_ALC_EN
20241. DA7210_ADC_EQ1_2
20242. DA7210_ADC_EQ3_4
20243. DA7210_ADC_EQ5
20244. DA7210_ADC_HPF
20245. DA7210_ADC_L_EN
20246. DA7210_ADC_R_EN
20247. DA7210_ALC_ATT
20248. DA7210_ALC_DEL
20249. DA7210_ALC_MAX
20250. DA7210_ALC_MIN
20251. DA7210_ALC_NOIS
20252. DA7210_ALC_REL
20253. DA7210_AUX1_L
20254. DA7210_AUX1_L_EN
20255. DA7210_AUX1_L_VOL
20256. DA7210_AUX1_L_ZC
20257. DA7210_AUX1_MIN_VOL_NS
20258. DA7210_AUX1_R
20259. DA7210_AUX1_R_EN
20260. DA7210_AUX1_R_VOL
20261. DA7210_AUX1_R_ZC
20262. DA7210_AUX2
20263. DA7210_AUX2_EN
20264. DA7210_A_CP_MODE
20265. DA7210_A_HID_UNLOCK
20266. DA7210_A_PLL1
20267. DA7210_A_TEST_UNLOCK
20268. DA7210_BIAS_EN
20269. DA7210_CLKSRC_MCLK
20270. DA7210_CONTROL
20271. DA7210_DAC_EQ1_2
20272. DA7210_DAC_EQ3_4
20273. DA7210_DAC_EQ5
20274. DA7210_DAC_HPF
20275. DA7210_DAC_L
20276. DA7210_DAC_L_EN
20277. DA7210_DAC_L_SRC_DAI_L
20278. DA7210_DAC_R
20279. DA7210_DAC_R_EN
20280. DA7210_DAC_R_SRC_DAI_R
20281. DA7210_DAC_SEL
20282. DA7210_DAI_CFG1
20283. DA7210_DAI_CFG3
20284. DA7210_DAI_EN
20285. DA7210_DAI_FLEN_64BIT
20286. DA7210_DAI_FORMAT_I2SMODE
20287. DA7210_DAI_FORMAT_LEFT_J
20288. DA7210_DAI_FORMAT_RIGHT_J
20289. DA7210_DAI_MODE_MASTER
20290. DA7210_DAI_MODE_SLAVE
20291. DA7210_DAI_OE
20292. DA7210_DAI_OUT_L_SRC
20293. DA7210_DAI_OUT_R_SRC
20294. DA7210_DAI_SRC_SEL
20295. DA7210_DAI_WORD_S16_LE
20296. DA7210_DAI_WORD_S20_3LE
20297. DA7210_DAI_WORD_S24_LE
20298. DA7210_DAI_WORD_S32_LE
20299. DA7210_FORMATS
20300. DA7210_HP_2CAP_MODE
20301. DA7210_HP_CFG
20302. DA7210_HP_L_EN
20303. DA7210_HP_L_VOL
20304. DA7210_HP_L_ZC
20305. DA7210_HP_MODE
20306. DA7210_HP_R_EN
20307. DA7210_HP_R_VOL
20308. DA7210_HP_R_ZC
20309. DA7210_HP_SENSE_EN
20310. DA7210_INMIX_L
20311. DA7210_INMIX_R
20312. DA7210_INPGA_L_VOL
20313. DA7210_INPGA_MIN_VOL_NS
20314. DA7210_INPGA_R_VOL
20315. DA7210_IN_GAIN
20316. DA7210_IN_L_EN
20317. DA7210_IN_R_EN
20318. DA7210_MCLK_DET_EN
20319. DA7210_MCLK_RANGE_10_20_MHZ
20320. DA7210_MCLK_SRM_EN
20321. DA7210_MICBIAS_EN
20322. DA7210_MIC_L
20323. DA7210_MIC_L_EN
20324. DA7210_MIC_R
20325. DA7210_MIC_R_EN
20326. DA7210_NOISE_SUP_EN
20327. DA7210_OUT1_L
20328. DA7210_OUT1_L_EN
20329. DA7210_OUT1_R
20330. DA7210_OUT1_R_EN
20331. DA7210_OUT2
20332. DA7210_OUT2_EN
20333. DA7210_OUT2_OUTMIX_L
20334. DA7210_OUT2_OUTMIX_R
20335. DA7210_OUTMIX_L
20336. DA7210_OUTMIX_R
20337. DA7210_OUT_L_EN
20338. DA7210_OUT_R_EN
20339. DA7210_PAGE_CONTROL
20340. DA7210_PLL
20341. DA7210_PLL_BYP
20342. DA7210_PLL_DIV1
20343. DA7210_PLL_DIV2
20344. DA7210_PLL_DIV3
20345. DA7210_PLL_DIV_L_MASK
20346. DA7210_PLL_EN
20347. DA7210_PLL_FS_11025
20348. DA7210_PLL_FS_12000
20349. DA7210_PLL_FS_16000
20350. DA7210_PLL_FS_22050
20351. DA7210_PLL_FS_24000
20352. DA7210_PLL_FS_32000
20353. DA7210_PLL_FS_44100
20354. DA7210_PLL_FS_48000
20355. DA7210_PLL_FS_8000
20356. DA7210_PLL_FS_88200
20357. DA7210_PLL_FS_96000
20358. DA7210_PLL_FS_MASK
20359. DA7210_RAMP_EN
20360. DA7210_REG_EN
20361. DA7210_SC_MST_EN
20362. DA7210_SOFTMUTE
20363. DA7210_STARTUP1
20364. DA7210_STARTUP2
20365. DA7210_STARTUP3
20366. DA7210_STATUS
20367. DA7210_VERSION
20368. DA7210_VOICE_EN
20369. DA7210_VOICE_F0_25
20370. DA7210_VOICE_F0_MASK
20371. DA7210_ZERO_CROSS
20372. DA7213_ADC_AMP_GAIN_MAX
20373. DA7213_ADC_AMP_GAIN_SHIFT
20374. DA7213_ADC_EN
20375. DA7213_ADC_EN_SHIFT
20376. DA7213_ADC_FILTERS1
20377. DA7213_ADC_L_CTRL
20378. DA7213_ADC_L_GAIN
20379. DA7213_ADC_L_GAIN_STATUS
20380. DA7213_ADC_R_CTRL
20381. DA7213_ADC_R_GAIN
20382. DA7213_ADC_R_GAIN_STATUS
20383. DA7213_ALC_ANA_GAIN_LIMITS
20384. DA7213_ALC_ANA_GAIN_MAX
20385. DA7213_ALC_ANA_GAIN_MAX_SHIFT
20386. DA7213_ALC_ANA_GAIN_MIN_SHIFT
20387. DA7213_ALC_ANTICLIP_CTRL
20388. DA7213_ALC_ANTICLIP_EN_MAX
20389. DA7213_ALC_ANTICLIP_EN_SHIFT
20390. DA7213_ALC_ANTICLIP_LEVEL
20391. DA7213_ALC_ANTICLIP_LEVEL_MAX
20392. DA7213_ALC_ANTICLIP_LEVEL_SHIFT
20393. DA7213_ALC_ATTACK_MAX
20394. DA7213_ALC_ATTACK_SHIFT
20395. DA7213_ALC_ATTEN_GAIN_MAX_MAX
20396. DA7213_ALC_ATTEN_MAX_SHIFT
20397. DA7213_ALC_AUTO_CALIB_EN
20398. DA7213_ALC_AVG_ITERATIONS
20399. DA7213_ALC_CALIB_MODE_MAN
20400. DA7213_ALC_CALIB_OVERFLOW
20401. DA7213_ALC_CIC_OP_CHANNEL_LEFT
20402. DA7213_ALC_CIC_OP_CHANNEL_RIGHT
20403. DA7213_ALC_CIC_OP_LVL_CTRL
20404. DA7213_ALC_CIC_OP_LVL_DATA
20405. DA7213_ALC_CTRL1
20406. DA7213_ALC_CTRL2
20407. DA7213_ALC_CTRL3
20408. DA7213_ALC_DATA_MIDDLE
20409. DA7213_ALC_DATA_TOP
20410. DA7213_ALC_EN_MAX
20411. DA7213_ALC_GAIN_LIMITS
20412. DA7213_ALC_GAIN_MAX_SHIFT
20413. DA7213_ALC_HOLD_MAX
20414. DA7213_ALC_HOLD_SHIFT
20415. DA7213_ALC_INTEG_ATTACK_SHIFT
20416. DA7213_ALC_INTEG_MAX
20417. DA7213_ALC_INTEG_RELEASE_SHIFT
20418. DA7213_ALC_L_EN_SHIFT
20419. DA7213_ALC_NOISE
20420. DA7213_ALC_OFFSET_15_8
20421. DA7213_ALC_OFFSET_19_16
20422. DA7213_ALC_OFFSET_AUTO_M_L
20423. DA7213_ALC_OFFSET_AUTO_M_R
20424. DA7213_ALC_OFFSET_AUTO_U_L
20425. DA7213_ALC_OFFSET_AUTO_U_R
20426. DA7213_ALC_OFFSET_EN
20427. DA7213_ALC_OFFSET_EN_MAX
20428. DA7213_ALC_OFFSET_EN_SHIFT
20429. DA7213_ALC_OFFSET_MAN_M_L
20430. DA7213_ALC_OFFSET_MAN_M_R
20431. DA7213_ALC_OFFSET_MAN_U_L
20432. DA7213_ALC_OFFSET_MAN_U_R
20433. DA7213_ALC_RELEASE_MAX
20434. DA7213_ALC_RELEASE_SHIFT
20435. DA7213_ALC_R_EN_SHIFT
20436. DA7213_ALC_SYNC_MODE
20437. DA7213_ALC_TARGET_MAX
20438. DA7213_ALC_TARGET_MIN
20439. DA7213_ALC_THRESHOLD_MAX
20440. DA7213_ALC_THRESHOLD_SHIFT
20441. DA7213_AMP_EN_SHIFT
20442. DA7213_AUDIO_HPF_CORNER_MAX
20443. DA7213_AUDIO_HPF_CORNER_SHIFT
20444. DA7213_AUX_AMP_GAIN_MAX
20445. DA7213_AUX_AMP_GAIN_SHIFT
20446. DA7213_AUX_L_CTRL
20447. DA7213_AUX_L_GAIN
20448. DA7213_AUX_L_GAIN_STATUS
20449. DA7213_AUX_R_CTRL
20450. DA7213_AUX_R_GAIN
20451. DA7213_AUX_R_GAIN_STATUS
20452. DA7213_BIAS_EN
20453. DA7213_BYTE_MASK
20454. DA7213_BYTE_SHIFT
20455. DA7213_CLKSRC_MCLK
20456. DA7213_CLKSRC_MCLK_SQR
20457. DA7213_CP_CTRL
20458. DA7213_CP_DELAY
20459. DA7213_CP_DETECTOR
20460. DA7213_CP_EN_SHIFT
20461. DA7213_CP_VOL_THRESHOLD1
20462. DA7213_DAC_AMP_GAIN_MAX
20463. DA7213_DAC_AMP_GAIN_SHIFT
20464. DA7213_DAC_EN_SHIFT
20465. DA7213_DAC_EQ_BAND1_SHIFT
20466. DA7213_DAC_EQ_BAND2_SHIFT
20467. DA7213_DAC_EQ_BAND3_SHIFT
20468. DA7213_DAC_EQ_BAND4_SHIFT
20469. DA7213_DAC_EQ_BAND5_SHIFT
20470. DA7213_DAC_EQ_BAND_MAX
20471. DA7213_DAC_EQ_EN_MAX
20472. DA7213_DAC_EQ_EN_SHIFT
20473. DA7213_DAC_FILTERS1
20474. DA7213_DAC_FILTERS2
20475. DA7213_DAC_FILTERS3
20476. DA7213_DAC_FILTERS4
20477. DA7213_DAC_FILTERS5
20478. DA7213_DAC_INV_MAX
20479. DA7213_DAC_L_CTRL
20480. DA7213_DAC_L_GAIN
20481. DA7213_DAC_L_GAIN_STATUS
20482. DA7213_DAC_L_INV_SHIFT
20483. DA7213_DAC_L_MONO_SHIFT
20484. DA7213_DAC_L_SRC_SHIFT
20485. DA7213_DAC_MONO_MAX
20486. DA7213_DAC_NG_CTRL
20487. DA7213_DAC_NG_EN_MAX
20488. DA7213_DAC_NG_EN_SHIFT
20489. DA7213_DAC_NG_OFF_THRESHOLD
20490. DA7213_DAC_NG_ON_THRESHOLD
20491. DA7213_DAC_NG_RAMPDN_RATE_SHIFT
20492. DA7213_DAC_NG_RAMPUP_RATE_SHIFT
20493. DA7213_DAC_NG_RAMP_RATE_MAX
20494. DA7213_DAC_NG_SETUP_TIME
20495. DA7213_DAC_NG_SETUP_TIME_MAX
20496. DA7213_DAC_NG_SETUP_TIME_SHIFT
20497. DA7213_DAC_NG_THRESHOLD_MAX
20498. DA7213_DAC_NG_THRESHOLD_SHIFT
20499. DA7213_DAC_R_CTRL
20500. DA7213_DAC_R_GAIN
20501. DA7213_DAC_R_GAIN_STATUS
20502. DA7213_DAC_R_INV_SHIFT
20503. DA7213_DAC_R_MONO_SHIFT
20504. DA7213_DAC_R_SRC_SHIFT
20505. DA7213_DAC_SOFTMUTE_EN_MAX
20506. DA7213_DAC_SOFTMUTE_EN_SHIFT
20507. DA7213_DAC_SOFTMUTE_RATE_MAX
20508. DA7213_DAC_SOFTMUTE_RATE_SHIFT
20509. DA7213_DAC_SRC_MAX
20510. DA7213_DAI_BCLKS_PER_WCLK_128
20511. DA7213_DAI_BCLKS_PER_WCLK_256
20512. DA7213_DAI_BCLKS_PER_WCLK_32
20513. DA7213_DAI_BCLKS_PER_WCLK_64
20514. DA7213_DAI_BCLKS_PER_WCLK_MASK
20515. DA7213_DAI_CLK_EN_MASK
20516. DA7213_DAI_CLK_MODE
20517. DA7213_DAI_CLK_POL_INV
20518. DA7213_DAI_CLK_POL_MASK
20519. DA7213_DAI_CTRL
20520. DA7213_DAI_EN_SHIFT
20521. DA7213_DAI_FORMAT_DSP
20522. DA7213_DAI_FORMAT_I2S_MODE
20523. DA7213_DAI_FORMAT_LEFT_J
20524. DA7213_DAI_FORMAT_MASK
20525. DA7213_DAI_FORMAT_RIGHT_J
20526. DA7213_DAI_L_SRC_SHIFT
20527. DA7213_DAI_OFFSET
20528. DA7213_DAI_R_SRC_SHIFT
20529. DA7213_DAI_SRC_MAX
20530. DA7213_DAI_WCLK_POL_INV
20531. DA7213_DAI_WCLK_POL_MASK
20532. DA7213_DAI_WORD_LENGTH_MASK
20533. DA7213_DAI_WORD_LENGTH_S16_LE
20534. DA7213_DAI_WORD_LENGTH_S20_LE
20535. DA7213_DAI_WORD_LENGTH_S24_LE
20536. DA7213_DAI_WORD_LENGTH_S32_LE
20537. DA7213_DIG_CTRL
20538. DA7213_DIG_ROUTING_DAC
20539. DA7213_DIG_ROUTING_DAI
20540. DA7213_DMIC_CLK_1_5MHZ
20541. DA7213_DMIC_CLK_3_0MHZ
20542. DA7213_DMIC_CLK_RATE_MASK
20543. DA7213_DMIC_CLK_RATE_SHIFT
20544. DA7213_DMIC_DATA_LFALL_RRISE
20545. DA7213_DMIC_DATA_LRISE_RFALL
20546. DA7213_DMIC_DATA_SEL_MASK
20547. DA7213_DMIC_DATA_SEL_SHIFT
20548. DA7213_DMIC_EN_MAX
20549. DA7213_DMIC_EN_SHIFT
20550. DA7213_DMIC_SAMPLEPHASE_MASK
20551. DA7213_DMIC_SAMPLEPHASE_SHIFT
20552. DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE
20553. DA7213_DMIC_SAMPLE_ON_CLKEDGE
20554. DA7213_FORMATS
20555. DA7213_GAIN_RAMP_CTRL
20556. DA7213_GAIN_RAMP_EN
20557. DA7213_GAIN_RAMP_EN_MAX
20558. DA7213_GAIN_RAMP_EN_SHIFT
20559. DA7213_GAIN_RAMP_RATE_MAX
20560. DA7213_GAIN_RAMP_RATE_SHIFT
20561. DA7213_HPF_EN_MAX
20562. DA7213_HPF_EN_SHIFT
20563. DA7213_HP_AMP_GAIN_MAX
20564. DA7213_HP_AMP_GAIN_SHIFT
20565. DA7213_HP_AMP_OE
20566. DA7213_HP_L_CTRL
20567. DA7213_HP_L_GAIN
20568. DA7213_HP_L_GAIN_STATUS
20569. DA7213_HP_R_CTRL
20570. DA7213_HP_R_GAIN
20571. DA7213_HP_R_GAIN_STATUS
20572. DA7213_INVERT
20573. DA7213_IO_CTRL
20574. DA7213_LDO_CTRL
20575. DA7213_LINE_AMP_GAIN_MAX
20576. DA7213_LINE_AMP_GAIN_SHIFT
20577. DA7213_LINE_AMP_OE
20578. DA7213_LINE_CTRL
20579. DA7213_LINE_GAIN
20580. DA7213_LINE_GAIN_STATUS
20581. DA7213_MICBIAS1_EN_SHIFT
20582. DA7213_MICBIAS1_LEVEL_MASK
20583. DA7213_MICBIAS1_LEVEL_SHIFT
20584. DA7213_MICBIAS2_EN_SHIFT
20585. DA7213_MICBIAS2_LEVEL_MASK
20586. DA7213_MICBIAS2_LEVEL_SHIFT
20587. DA7213_MICBIAS_1_6V
20588. DA7213_MICBIAS_2_2V
20589. DA7213_MICBIAS_2_5V
20590. DA7213_MICBIAS_3_0V
20591. DA7213_MICBIAS_CTRL
20592. DA7213_MIC_1_CTRL
20593. DA7213_MIC_1_GAIN
20594. DA7213_MIC_1_GAIN_STATUS
20595. DA7213_MIC_2_CTRL
20596. DA7213_MIC_2_GAIN
20597. DA7213_MIC_2_GAIN_STATUS
20598. DA7213_MIC_AMP_GAIN_MAX
20599. DA7213_MIC_AMP_GAIN_SHIFT
20600. DA7213_MIC_AMP_IN_SEL_MAX
20601. DA7213_MIC_AMP_IN_SEL_SHIFT
20602. DA7213_MIC_BIAS_OUTPUT_SELECT_2
20603. DA7213_MIC_CONFIG
20604. DA7213_MIXIN_AMP_GAIN_MAX
20605. DA7213_MIXIN_AMP_GAIN_SHIFT
20606. DA7213_MIXIN_L_CTRL
20607. DA7213_MIXIN_L_GAIN
20608. DA7213_MIXIN_L_GAIN_STATUS
20609. DA7213_MIXIN_L_MIX_SELECT_AUX_L_SHIFT
20610. DA7213_MIXIN_L_MIX_SELECT_MAX
20611. DA7213_MIXIN_L_MIX_SELECT_MIC_1
20612. DA7213_MIXIN_L_MIX_SELECT_MIC_1_SHIFT
20613. DA7213_MIXIN_L_MIX_SELECT_MIC_2
20614. DA7213_MIXIN_L_MIX_SELECT_MIC_2_SHIFT
20615. DA7213_MIXIN_L_MIX_SELECT_MIXIN_R_SHIFT
20616. DA7213_MIXIN_L_SELECT
20617. DA7213_MIXIN_MIX_EN
20618. DA7213_MIXIN_R_CTRL
20619. DA7213_MIXIN_R_GAIN
20620. DA7213_MIXIN_R_GAIN_STATUS
20621. DA7213_MIXIN_R_MIX_SELECT_AUX_R_SHIFT
20622. DA7213_MIXIN_R_MIX_SELECT_MAX
20623. DA7213_MIXIN_R_MIX_SELECT_MIC_1
20624. DA7213_MIXIN_R_MIX_SELECT_MIC_1_SHIFT
20625. DA7213_MIXIN_R_MIX_SELECT_MIC_2
20626. DA7213_MIXIN_R_MIX_SELECT_MIC_2_SHIFT
20627. DA7213_MIXIN_R_MIX_SELECT_MIXIN_L_SHIFT
20628. DA7213_MIXIN_R_SELECT
20629. DA7213_MIXOUT_L_CTRL
20630. DA7213_MIXOUT_L_MIX_SELECT_AUX_L_INVERTED_SHIFT
20631. DA7213_MIXOUT_L_MIX_SELECT_AUX_L_SHIFT
20632. DA7213_MIXOUT_L_MIX_SELECT_DAC_L_SHIFT
20633. DA7213_MIXOUT_L_MIX_SELECT_MAX
20634. DA7213_MIXOUT_L_MIX_SELECT_MIXIN_L_INVERTED_SHIFT
20635. DA7213_MIXOUT_L_MIX_SELECT_MIXIN_L_SHIFT
20636. DA7213_MIXOUT_L_MIX_SELECT_MIXIN_R_INVERTED_SHIFT
20637. DA7213_MIXOUT_L_MIX_SELECT_MIXIN_R_SHIFT
20638. DA7213_MIXOUT_L_SELECT
20639. DA7213_MIXOUT_MIX_EN
20640. DA7213_MIXOUT_R_CTRL
20641. DA7213_MIXOUT_R_MIX_SELECT_AUX_R_INVERTED_SHIFT
20642. DA7213_MIXOUT_R_MIX_SELECT_AUX_R_SHIFT
20643. DA7213_MIXOUT_R_MIX_SELECT_DAC_R_SHIFT
20644. DA7213_MIXOUT_R_MIX_SELECT_MAX
20645. DA7213_MIXOUT_R_MIX_SELECT_MIXIN_L_INVERTED_SHIFT
20646. DA7213_MIXOUT_R_MIX_SELECT_MIXIN_L_SHIFT
20647. DA7213_MIXOUT_R_MIX_SELECT_MIXIN_R_INVERTED_SHIFT
20648. DA7213_MIXOUT_R_MIX_SELECT_MIXIN_R_SHIFT
20649. DA7213_MIXOUT_R_SELECT
20650. DA7213_MUTE_EN
20651. DA7213_MUTE_EN_MAX
20652. DA7213_MUTE_EN_SHIFT
20653. DA7213_NO_INVERT
20654. DA7213_PC_COUNT
20655. DA7213_PC_FREERUN_MASK
20656. DA7213_PLL_32K_MODE
20657. DA7213_PLL_CTRL
20658. DA7213_PLL_EN
20659. DA7213_PLL_FRAC_BOT
20660. DA7213_PLL_FRAC_TOP
20661. DA7213_PLL_FREQ_OUT_90316800
20662. DA7213_PLL_FREQ_OUT_94310400
20663. DA7213_PLL_FREQ_OUT_98304000
20664. DA7213_PLL_INDIV_18_TO_36_MHZ
20665. DA7213_PLL_INDIV_18_TO_36_MHZ_VAL
20666. DA7213_PLL_INDIV_36_TO_54_MHZ
20667. DA7213_PLL_INDIV_36_TO_54_MHZ_VAL
20668. DA7213_PLL_INDIV_5_TO_9_MHZ
20669. DA7213_PLL_INDIV_5_TO_9_MHZ_VAL
20670. DA7213_PLL_INDIV_9_TO_18_MHZ
20671. DA7213_PLL_INDIV_9_TO_18_MHZ_VAL
20672. DA7213_PLL_INDIV_MASK
20673. DA7213_PLL_INTEGER
20674. DA7213_PLL_MCLK_SQR_EN
20675. DA7213_PLL_MODE_MASK
20676. DA7213_PLL_SRM_EN
20677. DA7213_PLL_STATUS
20678. DA7213_REFERENCES
20679. DA7213_SR
20680. DA7213_SRM_CHECK_RETRIES
20681. DA7213_SR_11025
20682. DA7213_SR_12000
20683. DA7213_SR_16000
20684. DA7213_SR_22050
20685. DA7213_SR_24000
20686. DA7213_SR_32000
20687. DA7213_SR_44100
20688. DA7213_SR_48000
20689. DA7213_SR_8000
20690. DA7213_SR_88200
20691. DA7213_SR_96000
20692. DA7213_STATUS1
20693. DA7213_SYSCLK_MCLK
20694. DA7213_SYSCLK_PLL
20695. DA7213_SYSCLK_PLL_32KHZ
20696. DA7213_SYSCLK_PLL_SRM
20697. DA7213_SYSTEM_MODES_INPUT
20698. DA7213_SYSTEM_MODES_OUTPUT
20699. DA7213_VMID_EN
20700. DA7213_VOICE_EN_MAX
20701. DA7213_VOICE_EN_SHIFT
20702. DA7213_VOICE_HPF_CORNER_MAX
20703. DA7213_VOICE_HPF_CORNER_SHIFT
20704. DA7213_ZC_EN_MAX
20705. DA7213_ZC_EN_SHIFT
20706. DA7217_DEV_ID
20707. DA7218_2BYTE_MASK
20708. DA7218_2BYTE_SHIFT
20709. DA7218_ADC_1_AAF_EN_MASK
20710. DA7218_ADC_1_AAF_EN_SHIFT
20711. DA7218_ADC_1_CTRL
20712. DA7218_ADC_2_AAF_EN_MASK
20713. DA7218_ADC_2_AAF_EN_SHIFT
20714. DA7218_ADC_2_CTRL
20715. DA7218_ADC_LP_MODE_MASK
20716. DA7218_ADC_LP_MODE_SHIFT
20717. DA7218_ADC_LVLDET_AUTO_EXIT_MASK
20718. DA7218_ADC_LVLDET_AUTO_EXIT_SHIFT
20719. DA7218_ADC_LVLDET_MODE_MASK
20720. DA7218_ADC_LVLDET_MODE_SHIFT
20721. DA7218_ADC_MODE
20722. DA7218_ADC_MODE_MASK
20723. DA7218_ADC_MODE_SHIFT
20724. DA7218_AGS_ANTICLIP_CTRL
20725. DA7218_AGS_ANTICLIP_EN_MASK
20726. DA7218_AGS_ANTICLIP_EN_SHIFT
20727. DA7218_AGS_ATT_MAX
20728. DA7218_AGS_ATT_MAX_MASK
20729. DA7218_AGS_ATT_MAX_MAX
20730. DA7218_AGS_ATT_MAX_SHIFT
20731. DA7218_AGS_ENABLE
20732. DA7218_AGS_ENABLE_CHAN1_SHIFT
20733. DA7218_AGS_ENABLE_CHAN2_SHIFT
20734. DA7218_AGS_ENABLE_MASK
20735. DA7218_AGS_ENABLE_SHIFT
20736. DA7218_AGS_TIMEOUT
20737. DA7218_AGS_TIMEOUT_EN_MASK
20738. DA7218_AGS_TIMEOUT_EN_SHIFT
20739. DA7218_AGS_TRIGGER
20740. DA7218_AGS_TRIGGER_MASK
20741. DA7218_AGS_TRIGGER_MAX
20742. DA7218_AGS_TRIGGER_SHIFT
20743. DA7218_ALC_ANA_GAIN_LIMITS
20744. DA7218_ALC_ANA_GAIN_MAX
20745. DA7218_ALC_ANA_GAIN_MAX_MASK
20746. DA7218_ALC_ANA_GAIN_MAX_SHIFT
20747. DA7218_ALC_ANA_GAIN_MIN
20748. DA7218_ALC_ANA_GAIN_MIN_MASK
20749. DA7218_ALC_ANA_GAIN_MIN_SHIFT
20750. DA7218_ALC_ANTICLIP_CTRL
20751. DA7218_ALC_ANTICLIP_EN_MASK
20752. DA7218_ALC_ANTICLIP_EN_SHIFT
20753. DA7218_ALC_ANTICLIP_STEP_MASK
20754. DA7218_ALC_ANTICLIP_STEP_MAX
20755. DA7218_ALC_ANTICLIP_STEP_SHIFT
20756. DA7218_ALC_ATTACK_MASK
20757. DA7218_ALC_ATTACK_MAX
20758. DA7218_ALC_ATTACK_SHIFT
20759. DA7218_ALC_ATTEN_GAIN_MAX
20760. DA7218_ALC_ATTEN_MAX_MASK
20761. DA7218_ALC_ATTEN_MAX_SHIFT
20762. DA7218_ALC_CALIB_DELAY_MAX
20763. DA7218_ALC_CALIB_DELAY_MIN
20764. DA7218_ALC_CALIB_MAX_TRIES
20765. DA7218_ALC_CHAN1_L_EN_SHIFT
20766. DA7218_ALC_CHAN1_R_EN_SHIFT
20767. DA7218_ALC_CHAN2_L_EN_SHIFT
20768. DA7218_ALC_CHAN2_R_EN_SHIFT
20769. DA7218_ALC_CTRL1
20770. DA7218_ALC_CTRL2
20771. DA7218_ALC_CTRL3
20772. DA7218_ALC_EN_MASK
20773. DA7218_ALC_EN_SHIFT
20774. DA7218_ALC_GAIN_LIMITS
20775. DA7218_ALC_GAIN_MAX_MASK
20776. DA7218_ALC_GAIN_MAX_SHIFT
20777. DA7218_ALC_HOLD_MASK
20778. DA7218_ALC_HOLD_MAX
20779. DA7218_ALC_HOLD_SHIFT
20780. DA7218_ALC_NOISE
20781. DA7218_ALC_NOISE_MASK
20782. DA7218_ALC_NOISE_SHIFT
20783. DA7218_ALC_RELEASE_MASK
20784. DA7218_ALC_RELEASE_MAX
20785. DA7218_ALC_RELEASE_SHIFT
20786. DA7218_ALC_SYNC_MODE_CH1
20787. DA7218_ALC_SYNC_MODE_CH2
20788. DA7218_ALC_SYNC_MODE_MASK
20789. DA7218_ALC_SYNC_MODE_SHIFT
20790. DA7218_ALC_TARGET_MAX
20791. DA7218_ALC_TARGET_MIN
20792. DA7218_ALC_THRESHOLD_MAX
20793. DA7218_ALC_THRESHOLD_MAX_MASK
20794. DA7218_ALC_THRESHOLD_MAX_SHIFT
20795. DA7218_ALC_THRESHOLD_MIN_MASK
20796. DA7218_ALC_THRESHOLD_MIN_SHIFT
20797. DA7218_AUDIO_HPF_CORNER_MAX
20798. DA7218_BEEP_CYCLES_MASK
20799. DA7218_BEEP_CYCLES_SHIFT
20800. DA7218_BEEP_OFF_PER_MASK
20801. DA7218_BEEP_OFF_PER_SHIFT
20802. DA7218_BEEP_ON_OFF_MAX
20803. DA7218_BEEP_ON_PER_MASK
20804. DA7218_BEEP_ON_PER_SHIFT
20805. DA7218_BIAS_EN_MASK
20806. DA7218_BIAS_EN_SHIFT
20807. DA7218_BIQ_CFG_ADDR
20808. DA7218_BIQ_CFG_DATA
20809. DA7218_BIQ_CFG_SIZE
20810. DA7218_BYTE_MASK
20811. DA7218_BYTE_SHIFT
20812. DA7218_CALIB_AUTO_EN_MASK
20813. DA7218_CALIB_AUTO_EN_SHIFT
20814. DA7218_CALIB_CTRL
20815. DA7218_CALIB_OFFSET_AUTO_M_1
20816. DA7218_CALIB_OFFSET_AUTO_M_1_MASK
20817. DA7218_CALIB_OFFSET_AUTO_M_1_SHIFT
20818. DA7218_CALIB_OFFSET_AUTO_M_2
20819. DA7218_CALIB_OFFSET_AUTO_M_2_MASK
20820. DA7218_CALIB_OFFSET_AUTO_M_2_SHIFT
20821. DA7218_CALIB_OFFSET_AUTO_U_1
20822. DA7218_CALIB_OFFSET_AUTO_U_1_MASK
20823. DA7218_CALIB_OFFSET_AUTO_U_1_SHIFT
20824. DA7218_CALIB_OFFSET_AUTO_U_2
20825. DA7218_CALIB_OFFSET_AUTO_U_2_MASK
20826. DA7218_CALIB_OFFSET_AUTO_U_2_SHIFT
20827. DA7218_CALIB_OFFSET_EN_MASK
20828. DA7218_CALIB_OFFSET_EN_SHIFT
20829. DA7218_CALIB_OVERFLOW_MASK
20830. DA7218_CALIB_OVERFLOW_SHIFT
20831. DA7218_CHIP_ID1
20832. DA7218_CHIP_ID1_MASK
20833. DA7218_CHIP_ID1_SHIFT
20834. DA7218_CHIP_ID2
20835. DA7218_CHIP_ID2_MASK
20836. DA7218_CHIP_ID2_SHIFT
20837. DA7218_CHIP_MAJOR_MASK
20838. DA7218_CHIP_MAJOR_SHIFT
20839. DA7218_CHIP_MINOR_MASK
20840. DA7218_CHIP_MINOR_SHIFT
20841. DA7218_CHIP_REVISION
20842. DA7218_CIF_CTRL
20843. DA7218_CIF_I2C_WRITE_MODE_MASK
20844. DA7218_CIF_I2C_WRITE_MODE_SHIFT
20845. DA7218_CIF_REG_SOFT_RESET_MASK
20846. DA7218_CIF_REG_SOFT_RESET_SHIFT
20847. DA7218_CIF_TIMEOUT_CTRL
20848. DA7218_CLKSRC_MCLK
20849. DA7218_CLKSRC_MCLK_SQR
20850. DA7218_CP_CTRL
20851. DA7218_CP_DELAY
20852. DA7218_CP_EN_MASK
20853. DA7218_CP_EN_SHIFT
20854. DA7218_CP_FCONTROL_MASK
20855. DA7218_CP_FCONTROL_MAX
20856. DA7218_CP_FCONTROL_SHIFT
20857. DA7218_CP_MCHANGE_DAC_VOL
20858. DA7218_CP_MCHANGE_LARGEST_VOL
20859. DA7218_CP_MCHANGE_MASK
20860. DA7218_CP_MCHANGE_MAX
20861. DA7218_CP_MCHANGE_REL_MASK
20862. DA7218_CP_MCHANGE_SHIFT
20863. DA7218_CP_MCHANGE_SIG_MAG
20864. DA7218_CP_MOD_MASK
20865. DA7218_CP_MOD_SHIFT
20866. DA7218_CP_SMALL_SWITCH_FREQ_EN_MASK
20867. DA7218_CP_SMALL_SWITCH_FREQ_EN_SHIFT
20868. DA7218_CP_TAU_DELAY_MASK
20869. DA7218_CP_TAU_DELAY_MAX
20870. DA7218_CP_TAU_DELAY_SHIFT
20871. DA7218_CP_THRESH_VDD2_MASK
20872. DA7218_CP_THRESH_VDD2_MAX
20873. DA7218_CP_THRESH_VDD2_SHIFT
20874. DA7218_CP_VOL_THRESHOLD1
20875. DA7218_DAC_MODE_MASK
20876. DA7218_DAC_MODE_SHIFT
20877. DA7218_DAC_NG_CTRL
20878. DA7218_DAC_NG_EN_MASK
20879. DA7218_DAC_NG_EN_SHIFT
20880. DA7218_DAC_NG_OFF_THRESH
20881. DA7218_DAC_NG_OFF_THRESHOLD_MASK
20882. DA7218_DAC_NG_OFF_THRESHOLD_SHIFT
20883. DA7218_DAC_NG_ON_THRESH
20884. DA7218_DAC_NG_ON_THRESHOLD_MASK
20885. DA7218_DAC_NG_ON_THRESHOLD_SHIFT
20886. DA7218_DAC_NG_RAMPDN_RATE_MASK
20887. DA7218_DAC_NG_RAMPDN_RATE_MAX
20888. DA7218_DAC_NG_RAMPDN_RATE_SHIFT
20889. DA7218_DAC_NG_RAMPUP_RATE_MASK
20890. DA7218_DAC_NG_RAMPUP_RATE_MAX
20891. DA7218_DAC_NG_RAMPUP_RATE_SHIFT
20892. DA7218_DAC_NG_SETUP_TIME
20893. DA7218_DAC_NG_SETUP_TIME_MASK
20894. DA7218_DAC_NG_SETUP_TIME_MAX
20895. DA7218_DAC_NG_SETUP_TIME_SHIFT
20896. DA7218_DAC_NG_THRESHOLD_MAX
20897. DA7218_DAI_BCLKS_PER_WCLK_128
20898. DA7218_DAI_BCLKS_PER_WCLK_256
20899. DA7218_DAI_BCLKS_PER_WCLK_32
20900. DA7218_DAI_BCLKS_PER_WCLK_64
20901. DA7218_DAI_BCLKS_PER_WCLK_MASK
20902. DA7218_DAI_BCLKS_PER_WCLK_SHIFT
20903. DA7218_DAI_CH_NUM_MASK
20904. DA7218_DAI_CH_NUM_MAX
20905. DA7218_DAI_CH_NUM_SHIFT
20906. DA7218_DAI_CLK_EN_MASK
20907. DA7218_DAI_CLK_EN_SHIFT
20908. DA7218_DAI_CLK_MODE
20909. DA7218_DAI_CLK_POL_INV
20910. DA7218_DAI_CLK_POL_MASK
20911. DA7218_DAI_CLK_POL_SHIFT
20912. DA7218_DAI_CTRL
20913. DA7218_DAI_EN_MASK
20914. DA7218_DAI_EN_SHIFT
20915. DA7218_DAI_FORMAT_DSP
20916. DA7218_DAI_FORMAT_I2S
20917. DA7218_DAI_FORMAT_LEFT_J
20918. DA7218_DAI_FORMAT_MASK
20919. DA7218_DAI_FORMAT_RIGHT_J
20920. DA7218_DAI_FORMAT_SHIFT
20921. DA7218_DAI_OE_MASK
20922. DA7218_DAI_OE_SHIFT
20923. DA7218_DAI_OFFSET_LOWER
20924. DA7218_DAI_OFFSET_LOWER_MASK
20925. DA7218_DAI_OFFSET_LOWER_SHIFT
20926. DA7218_DAI_OFFSET_UPPER
20927. DA7218_DAI_OFFSET_UPPER_MASK
20928. DA7218_DAI_OFFSET_UPPER_SHIFT
20929. DA7218_DAI_TDM_CH_EN_MASK
20930. DA7218_DAI_TDM_CH_EN_SHIFT
20931. DA7218_DAI_TDM_CTRL
20932. DA7218_DAI_TDM_MAX_SLOTS
20933. DA7218_DAI_TDM_MODE_EN_MASK
20934. DA7218_DAI_TDM_MODE_EN_SHIFT
20935. DA7218_DAI_WCLK_POL_INV
20936. DA7218_DAI_WCLK_POL_MASK
20937. DA7218_DAI_WCLK_POL_SHIFT
20938. DA7218_DAI_WCLK_TRI_STATE_MASK
20939. DA7218_DAI_WCLK_TRI_STATE_SHIFT
20940. DA7218_DAI_WORD_LENGTH_MASK
20941. DA7218_DAI_WORD_LENGTH_S16_LE
20942. DA7218_DAI_WORD_LENGTH_S20_LE
20943. DA7218_DAI_WORD_LENGTH_S24_LE
20944. DA7218_DAI_WORD_LENGTH_S32_LE
20945. DA7218_DAI_WORD_LENGTH_SHIFT
20946. DA7218_DEV_ID
20947. DA7218_DGS_ANTICLIP_LVL_MASK
20948. DA7218_DGS_ANTICLIP_LVL_MAX
20949. DA7218_DGS_ANTICLIP_LVL_SHIFT
20950. DA7218_DGS_ENABLE
20951. DA7218_DGS_ENABLE_L_SHIFT
20952. DA7218_DGS_ENABLE_MASK
20953. DA7218_DGS_ENABLE_R_SHIFT
20954. DA7218_DGS_ENABLE_SHIFT
20955. DA7218_DGS_FALL_COEFF_MASK
20956. DA7218_DGS_FALL_COEFF_MAX
20957. DA7218_DGS_FALL_COEFF_SHIFT
20958. DA7218_DGS_GAIN_CTRL
20959. DA7218_DGS_LEVELS
20960. DA7218_DGS_RAMP_EN_MASK
20961. DA7218_DGS_RAMP_EN_SHIFT
20962. DA7218_DGS_RISE_COEFF_MASK
20963. DA7218_DGS_RISE_COEFF_MAX
20964. DA7218_DGS_RISE_COEFF_SHIFT
20965. DA7218_DGS_RISE_FALL
20966. DA7218_DGS_SIGNAL_LVL_MASK
20967. DA7218_DGS_SIGNAL_LVL_MAX
20968. DA7218_DGS_SIGNAL_LVL_SHIFT
20969. DA7218_DGS_STEPS_MASK
20970. DA7218_DGS_STEPS_MAX
20971. DA7218_DGS_STEPS_SHIFT
20972. DA7218_DGS_SUBR_EN_MASK
20973. DA7218_DGS_SUBR_EN_SHIFT
20974. DA7218_DGS_SYNC_DELAY
20975. DA7218_DGS_SYNC_DELAY2
20976. DA7218_DGS_SYNC_DELAY2_MASK
20977. DA7218_DGS_SYNC_DELAY2_SHIFT
20978. DA7218_DGS_SYNC_DELAY3
20979. DA7218_DGS_SYNC_DELAY3_MASK
20980. DA7218_DGS_SYNC_DELAY3_MAX
20981. DA7218_DGS_SYNC_DELAY3_SHIFT
20982. DA7218_DGS_SYNC_DELAY_MASK
20983. DA7218_DGS_SYNC_DELAY_MAX
20984. DA7218_DGS_SYNC_DELAY_SHIFT
20985. DA7218_DGS_TRIGGER
20986. DA7218_DGS_TRIGGER_LVL_MASK
20987. DA7218_DGS_TRIGGER_LVL_SHIFT
20988. DA7218_DGS_TRIGGER_MAX
20989. DA7218_DMIC_1L_EN_MASK
20990. DA7218_DMIC_1L_EN_SHIFT
20991. DA7218_DMIC_1R_EN_MASK
20992. DA7218_DMIC_1R_EN_SHIFT
20993. DA7218_DMIC_1_CLK_RATE_MASK
20994. DA7218_DMIC_1_CLK_RATE_SHIFT
20995. DA7218_DMIC_1_CTRL
20996. DA7218_DMIC_1_DATA_SEL_MASK
20997. DA7218_DMIC_1_DATA_SEL_SHIFT
20998. DA7218_DMIC_1_SAMPLEPHASE_MASK
20999. DA7218_DMIC_1_SAMPLEPHASE_SHIFT
21000. DA7218_DMIC_2L_EN_MASK
21001. DA7218_DMIC_2L_EN_SHIFT
21002. DA7218_DMIC_2R_EN_MASK
21003. DA7218_DMIC_2R_EN_SHIFT
21004. DA7218_DMIC_2_CLK_RATE_MASK
21005. DA7218_DMIC_2_CLK_RATE_SHIFT
21006. DA7218_DMIC_2_CTRL
21007. DA7218_DMIC_2_DATA_SEL_MASK
21008. DA7218_DMIC_2_DATA_SEL_SHIFT
21009. DA7218_DMIC_2_SAMPLEPHASE_MASK
21010. DA7218_DMIC_2_SAMPLEPHASE_SHIFT
21011. DA7218_DMIC_CLK_1_5MHZ
21012. DA7218_DMIC_CLK_3_0MHZ
21013. DA7218_DMIC_DATA_LFALL_RRISE
21014. DA7218_DMIC_DATA_LRISE_RFALL
21015. DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE
21016. DA7218_DMIC_SAMPLE_ON_CLKEDGE
21017. DA7218_DMIX_CTRLS
21018. DA7218_DMIX_GAIN_MAX
21019. DA7218_DMIX_OUTDAI_1L_INDAI_1L_GAIN
21020. DA7218_DMIX_OUTDAI_1L_INDAI_1R_GAIN
21021. DA7218_DMIX_OUTDAI_1L_INFILT_1L_GAIN
21022. DA7218_DMIX_OUTDAI_1L_INFILT_1R_GAIN
21023. DA7218_DMIX_OUTDAI_1L_INFILT_2L_GAIN
21024. DA7218_DMIX_OUTDAI_1L_INFILT_2R_GAIN
21025. DA7218_DMIX_OUTDAI_1L_TONEGEN_GAIN
21026. DA7218_DMIX_OUTDAI_1R_INDAI_1L_GAIN
21027. DA7218_DMIX_OUTDAI_1R_INDAI_1R_GAIN
21028. DA7218_DMIX_OUTDAI_1R_INFILT_1L_GAIN
21029. DA7218_DMIX_OUTDAI_1R_INFILT_1R_GAIN
21030. DA7218_DMIX_OUTDAI_1R_INFILT_2L_GAIN
21031. DA7218_DMIX_OUTDAI_1R_INFILT_2R_GAIN
21032. DA7218_DMIX_OUTDAI_1R_TONEGEN_GAIN
21033. DA7218_DMIX_OUTDAI_2L_INDAI_1L_GAIN
21034. DA7218_DMIX_OUTDAI_2L_INDAI_1R_GAIN
21035. DA7218_DMIX_OUTDAI_2L_INFILT_1L_GAIN
21036. DA7218_DMIX_OUTDAI_2L_INFILT_1R_GAIN
21037. DA7218_DMIX_OUTDAI_2L_INFILT_2L_GAIN
21038. DA7218_DMIX_OUTDAI_2L_INFILT_2R_GAIN
21039. DA7218_DMIX_OUTDAI_2L_TONEGEN_GAIN
21040. DA7218_DMIX_OUTDAI_2R_INDAI_1L_GAIN
21041. DA7218_DMIX_OUTDAI_2R_INDAI_1R_GAIN
21042. DA7218_DMIX_OUTDAI_2R_INFILT_1L_GAIN
21043. DA7218_DMIX_OUTDAI_2R_INFILT_1R_GAIN
21044. DA7218_DMIX_OUTDAI_2R_INFILT_2L_GAIN
21045. DA7218_DMIX_OUTDAI_2R_INFILT_2R_GAIN
21046. DA7218_DMIX_OUTDAI_2R_TONEGEN_GAIN
21047. DA7218_DMIX_OUTFILT_1L_INDAI_1L_GAIN
21048. DA7218_DMIX_OUTFILT_1L_INDAI_1R_GAIN
21049. DA7218_DMIX_OUTFILT_1L_INFILT_1L_GAIN
21050. DA7218_DMIX_OUTFILT_1L_INFILT_1R_GAIN
21051. DA7218_DMIX_OUTFILT_1L_INFILT_2L_GAIN
21052. DA7218_DMIX_OUTFILT_1L_INFILT_2R_GAIN
21053. DA7218_DMIX_OUTFILT_1L_TONEGEN_GAIN
21054. DA7218_DMIX_OUTFILT_1R_INDAI_1L_GAIN
21055. DA7218_DMIX_OUTFILT_1R_INDAI_1R_GAIN
21056. DA7218_DMIX_OUTFILT_1R_INFILT_1L_GAIN
21057. DA7218_DMIX_OUTFILT_1R_INFILT_1R_GAIN
21058. DA7218_DMIX_OUTFILT_1R_INFILT_2L_GAIN
21059. DA7218_DMIX_OUTFILT_1R_INFILT_2R_GAIN
21060. DA7218_DMIX_OUTFILT_1R_TONEGEN_GAIN
21061. DA7218_DMIX_ROUTES
21062. DA7218_DMIX_SRC_DAIL
21063. DA7218_DMIX_SRC_DAIR
21064. DA7218_DMIX_SRC_INFILT1L
21065. DA7218_DMIX_SRC_INFILT1R
21066. DA7218_DMIX_SRC_INFILT2L
21067. DA7218_DMIX_SRC_INFILT2R
21068. DA7218_DMIX_SRC_TONEGEN
21069. DA7218_DMIX_ST_CTRLS
21070. DA7218_DMIX_ST_ROUTES
21071. DA7218_DMIX_ST_SRC_OUTFILT1L
21072. DA7218_DMIX_ST_SRC_OUTFILT1R
21073. DA7218_DMIX_ST_SRC_SIDETONE
21074. DA7218_DROUTING_OUTDAI_1L
21075. DA7218_DROUTING_OUTDAI_1R
21076. DA7218_DROUTING_OUTDAI_2L
21077. DA7218_DROUTING_OUTDAI_2R
21078. DA7218_DROUTING_OUTFILT_1L
21079. DA7218_DROUTING_OUTFILT_1R
21080. DA7218_DROUTING_ST_OUTFILT_1L
21081. DA7218_DROUTING_ST_OUTFILT_1R
21082. DA7218_DTMF_EN_MASK
21083. DA7218_DTMF_EN_SHIFT
21084. DA7218_DTMF_REG_MASK
21085. DA7218_DTMF_REG_MAX
21086. DA7218_DTMF_REG_SHIFT
21087. DA7218_ENV_TRACK_CTRL
21088. DA7218_EVENT
21089. DA7218_EVENT_MASK
21090. DA7218_EVENT_STATUS
21091. DA7218_FORMATS
21092. DA7218_FREQ1_L_MASK
21093. DA7218_FREQ1_L_SHIFT
21094. DA7218_FREQ1_U_MASK
21095. DA7218_FREQ1_U_SHIFT
21096. DA7218_FREQ2_L_MASK
21097. DA7218_FREQ2_L_SHIFT
21098. DA7218_FREQ2_U_MASK
21099. DA7218_FREQ2_U_SHIFT
21100. DA7218_FREQ_MAX
21101. DA7218_GAIN_RAMP_CTRL
21102. DA7218_GAIN_RAMP_RATE_MASK
21103. DA7218_GAIN_RAMP_RATE_MAX
21104. DA7218_GAIN_RAMP_RATE_SHIFT
21105. DA7218_HPF_AUDIO_EN
21106. DA7218_HPF_DISABLED
21107. DA7218_HPF_MODE_MASK
21108. DA7218_HPF_MODE_MAX
21109. DA7218_HPF_MODE_SHIFT
21110. DA7218_HPF_VOICE_EN
21111. DA7218_HPLDET_COMP_INV_MASK
21112. DA7218_HPLDET_COMP_INV_SHIFT
21113. DA7218_HPLDET_COMP_STS_MASK
21114. DA7218_HPLDET_COMP_STS_SHIFT
21115. DA7218_HPLDET_CTRL
21116. DA7218_HPLDET_DISCHARGE_EN_MASK
21117. DA7218_HPLDET_DISCHARGE_EN_SHIFT
21118. DA7218_HPLDET_HYST_EN_MASK
21119. DA7218_HPLDET_HYST_EN_SHIFT
21120. DA7218_HPLDET_JACK
21121. DA7218_HPLDET_JACK_DEBOUNCE_2
21122. DA7218_HPLDET_JACK_DEBOUNCE_3
21123. DA7218_HPLDET_JACK_DEBOUNCE_4
21124. DA7218_HPLDET_JACK_DEBOUNCE_MASK
21125. DA7218_HPLDET_JACK_DEBOUNCE_OFF
21126. DA7218_HPLDET_JACK_DEBOUNCE_SHIFT
21127. DA7218_HPLDET_JACK_EN_MASK
21128. DA7218_HPLDET_JACK_EN_SHIFT
21129. DA7218_HPLDET_JACK_EVENT_IRQ_MSK_MASK
21130. DA7218_HPLDET_JACK_EVENT_IRQ_MSK_SHIFT
21131. DA7218_HPLDET_JACK_EVENT_MASK
21132. DA7218_HPLDET_JACK_EVENT_SHIFT
21133. DA7218_HPLDET_JACK_RATE_10US
21134. DA7218_HPLDET_JACK_RATE_160US
21135. DA7218_HPLDET_JACK_RATE_20US
21136. DA7218_HPLDET_JACK_RATE_320US
21137. DA7218_HPLDET_JACK_RATE_40US
21138. DA7218_HPLDET_JACK_RATE_5US
21139. DA7218_HPLDET_JACK_RATE_640US
21140. DA7218_HPLDET_JACK_RATE_80US
21141. DA7218_HPLDET_JACK_RATE_MASK
21142. DA7218_HPLDET_JACK_RATE_SHIFT
21143. DA7218_HPLDET_JACK_STS_MASK
21144. DA7218_HPLDET_JACK_STS_SHIFT
21145. DA7218_HPLDET_JACK_THR_84PCT
21146. DA7218_HPLDET_JACK_THR_88PCT
21147. DA7218_HPLDET_JACK_THR_92PCT
21148. DA7218_HPLDET_JACK_THR_96PCT
21149. DA7218_HPLDET_JACK_THR_MASK
21150. DA7218_HPLDET_JACK_THR_SHIFT
21151. DA7218_HPLDET_TEST
21152. DA7218_HPL_AMP_LOAD_DETECT_STATUS_MASK
21153. DA7218_HPL_AMP_LOAD_DETECT_STATUS_SHIFT
21154. DA7218_HPR_AMP_LOAD_DETECT_STATUS_MASK
21155. DA7218_HPR_AMP_LOAD_DETECT_STATUS_SHIFT
21156. DA7218_HP_AMP_DIFF_MODE_EN_MASK
21157. DA7218_HP_AMP_DIFF_MODE_EN_SHIFT
21158. DA7218_HP_AMP_GAIN_MAX
21159. DA7218_HP_AMP_GAIN_MIN
21160. DA7218_HP_AMP_LOAD_DETECT_EN_MASK
21161. DA7218_HP_AMP_LOAD_DETECT_EN_SHIFT
21162. DA7218_HP_AMP_OE_MASK
21163. DA7218_HP_AMP_SINGLE_SUPPLY_EN_MASK
21164. DA7218_HP_AMP_SINGLE_SUPPLY_EN_SHIFT
21165. DA7218_HP_AMP_STEREO_DETECT_EN_MASK
21166. DA7218_HP_AMP_STEREO_DETECT_EN_SHIFT
21167. DA7218_HP_AMP_STEREO_DETECT_STATUS_MASK
21168. DA7218_HP_AMP_STEREO_DETECT_STATUS_SHIFT
21169. DA7218_HP_DIFF_CTRL
21170. DA7218_HP_DIFF_UNLOCK
21171. DA7218_HP_DIFF_UNLOCK_MASK
21172. DA7218_HP_DIFF_UNLOCK_SHIFT
21173. DA7218_HP_DIFF_UNLOCK_VAL
21174. DA7218_HP_L_AMP_EN_MASK
21175. DA7218_HP_L_AMP_EN_SHIFT
21176. DA7218_HP_L_AMP_GAIN_MASK
21177. DA7218_HP_L_AMP_GAIN_SHIFT
21178. DA7218_HP_L_AMP_MIN_GAIN_EN_MASK
21179. DA7218_HP_L_AMP_MIN_GAIN_EN_SHIFT
21180. DA7218_HP_L_AMP_MUTE_EN_MASK
21181. DA7218_HP_L_AMP_MUTE_EN_SHIFT
21182. DA7218_HP_L_AMP_OE_MASK
21183. DA7218_HP_L_AMP_OE_SHIFT
21184. DA7218_HP_L_AMP_RAMP_EN_MASK
21185. DA7218_HP_L_AMP_RAMP_EN_SHIFT
21186. DA7218_HP_L_AMP_ZC_EN_MASK
21187. DA7218_HP_L_AMP_ZC_EN_SHIFT
21188. DA7218_HP_L_CTRL
21189. DA7218_HP_L_GAIN
21190. DA7218_HP_R_AMP_EN_MASK
21191. DA7218_HP_R_AMP_EN_SHIFT
21192. DA7218_HP_R_AMP_GAIN_MASK
21193. DA7218_HP_R_AMP_GAIN_SHIFT
21194. DA7218_HP_R_AMP_MIN_GAIN_EN_MASK
21195. DA7218_HP_R_AMP_MIN_GAIN_EN_SHIFT
21196. DA7218_HP_R_AMP_MUTE_EN_MASK
21197. DA7218_HP_R_AMP_MUTE_EN_SHIFT
21198. DA7218_HP_R_AMP_OE_MASK
21199. DA7218_HP_R_AMP_OE_SHIFT
21200. DA7218_HP_R_AMP_RAMP_EN_MASK
21201. DA7218_HP_R_AMP_RAMP_EN_SHIFT
21202. DA7218_HP_R_AMP_ZC_EN_MASK
21203. DA7218_HP_R_AMP_ZC_EN_SHIFT
21204. DA7218_HP_R_CTRL
21205. DA7218_HP_R_GAIN
21206. DA7218_HP_SNGL_CTRL
21207. DA7218_I2C_TIMEOUT_EN_MASK
21208. DA7218_I2C_TIMEOUT_EN_SHIFT
21209. DA7218_INTEG_ATTACK_MASK
21210. DA7218_INTEG_ATTACK_SHIFT
21211. DA7218_INTEG_MAX
21212. DA7218_INTEG_RELEASE_MASK
21213. DA7218_INTEG_RELEASE_SHIFT
21214. DA7218_INVERT
21215. DA7218_IN_1L_DIGITAL_GAIN_MASK
21216. DA7218_IN_1L_DIGITAL_GAIN_SHIFT
21217. DA7218_IN_1L_FILTER_CTRL
21218. DA7218_IN_1L_FILTER_EN_MASK
21219. DA7218_IN_1L_FILTER_EN_SHIFT
21220. DA7218_IN_1L_GAIN
21221. DA7218_IN_1L_MUTE_EN_MASK
21222. DA7218_IN_1L_MUTE_EN_SHIFT
21223. DA7218_IN_1L_RAMP_EN_MASK
21224. DA7218_IN_1L_RAMP_EN_SHIFT
21225. DA7218_IN_1R_DIGITAL_GAIN_MASK
21226. DA7218_IN_1R_DIGITAL_GAIN_SHIFT
21227. DA7218_IN_1R_FILTER_CTRL
21228. DA7218_IN_1R_FILTER_EN_MASK
21229. DA7218_IN_1R_FILTER_EN_SHIFT
21230. DA7218_IN_1R_GAIN
21231. DA7218_IN_1R_MUTE_EN_MASK
21232. DA7218_IN_1R_MUTE_EN_SHIFT
21233. DA7218_IN_1R_RAMP_EN_MASK
21234. DA7218_IN_1R_RAMP_EN_SHIFT
21235. DA7218_IN_1_AUDIO_HPF_CORNER_MASK
21236. DA7218_IN_1_AUDIO_HPF_CORNER_SHIFT
21237. DA7218_IN_1_HPF_EN_MASK
21238. DA7218_IN_1_HPF_EN_SHIFT
21239. DA7218_IN_1_HPF_FILTER_CTRL
21240. DA7218_IN_1_VOICE_EN_MASK
21241. DA7218_IN_1_VOICE_EN_SHIFT
21242. DA7218_IN_1_VOICE_HPF_CORNER_MASK
21243. DA7218_IN_1_VOICE_HPF_CORNER_SHIFT
21244. DA7218_IN_2L_DIGITAL_GAIN_MASK
21245. DA7218_IN_2L_DIGITAL_GAIN_SHIFT
21246. DA7218_IN_2L_FILTER_CTRL
21247. DA7218_IN_2L_FILTER_EN_MASK
21248. DA7218_IN_2L_FILTER_EN_SHIFT
21249. DA7218_IN_2L_GAIN
21250. DA7218_IN_2L_MUTE_EN_MASK
21251. DA7218_IN_2L_MUTE_EN_SHIFT
21252. DA7218_IN_2L_RAMP_EN_MASK
21253. DA7218_IN_2L_RAMP_EN_SHIFT
21254. DA7218_IN_2R_DIGITAL_GAIN_MASK
21255. DA7218_IN_2R_DIGITAL_GAIN_SHIFT
21256. DA7218_IN_2R_FILTER_CTRL
21257. DA7218_IN_2R_FILTER_EN_MASK
21258. DA7218_IN_2R_FILTER_EN_SHIFT
21259. DA7218_IN_2R_GAIN
21260. DA7218_IN_2R_MUTE_EN_MASK
21261. DA7218_IN_2R_MUTE_EN_SHIFT
21262. DA7218_IN_2R_RAMP_EN_MASK
21263. DA7218_IN_2R_RAMP_EN_SHIFT
21264. DA7218_IN_2_AUDIO_HPF_CORNER_MASK
21265. DA7218_IN_2_AUDIO_HPF_CORNER_SHIFT
21266. DA7218_IN_2_HPF_EN_MASK
21267. DA7218_IN_2_HPF_EN_SHIFT
21268. DA7218_IN_2_HPF_FILTER_CTRL
21269. DA7218_IN_2_VOICE_EN_MASK
21270. DA7218_IN_2_VOICE_EN_SHIFT
21271. DA7218_IN_2_VOICE_HPF_CORNER_MASK
21272. DA7218_IN_2_VOICE_HPF_CORNER_SHIFT
21273. DA7218_IN_DIGITAL_GAIN_MAX
21274. DA7218_IN_VOICE_HPF_CORNER_MAX
21275. DA7218_IO_CTRL
21276. DA7218_IO_VOLTAGE_LEVEL_1_5V_2_5V
21277. DA7218_IO_VOLTAGE_LEVEL_2_5V_3_6V
21278. DA7218_IO_VOLTAGE_LEVEL_MASK
21279. DA7218_IO_VOLTAGE_LEVEL_SHIFT
21280. DA7218_LDO_CTRL
21281. DA7218_LDO_EN_MASK
21282. DA7218_LDO_EN_SHIFT
21283. DA7218_LDO_LEVEL_SELECT_MASK
21284. DA7218_LDO_LEVEL_SELECT_SHIFT
21285. DA7218_LVL_DET_CTRL
21286. DA7218_LVL_DET_EN_CHAN1L_SHIFT
21287. DA7218_LVL_DET_EN_CHAN1R_SHIFT
21288. DA7218_LVL_DET_EN_CHAN2L_SHIFT
21289. DA7218_LVL_DET_EN_CHAN2R_SHIFT
21290. DA7218_LVL_DET_EN_MASK
21291. DA7218_LVL_DET_EN_SHIFT
21292. DA7218_LVL_DET_EVENT_MASK
21293. DA7218_LVL_DET_EVENT_MSK_MASK
21294. DA7218_LVL_DET_EVENT_MSK_SHIFT
21295. DA7218_LVL_DET_EVENT_SHIFT
21296. DA7218_LVL_DET_LEVEL
21297. DA7218_LVL_DET_LEVEL_MASK
21298. DA7218_LVL_DET_LEVEL_MAX
21299. DA7218_LVL_DET_LEVEL_SHIFT
21300. DA7218_MICBIAS_1_2V
21301. DA7218_MICBIAS_1_6V
21302. DA7218_MICBIAS_1_8V
21303. DA7218_MICBIAS_1_EN_MASK
21304. DA7218_MICBIAS_1_EN_SHIFT
21305. DA7218_MICBIAS_1_LEVEL_MASK
21306. DA7218_MICBIAS_1_LEVEL_SHIFT
21307. DA7218_MICBIAS_1_LP_MODE_MASK
21308. DA7218_MICBIAS_1_LP_MODE_SHIFT
21309. DA7218_MICBIAS_2_0V
21310. DA7218_MICBIAS_2_2V
21311. DA7218_MICBIAS_2_4V
21312. DA7218_MICBIAS_2_6V
21313. DA7218_MICBIAS_2_8V
21314. DA7218_MICBIAS_2_EN_MASK
21315. DA7218_MICBIAS_2_EN_SHIFT
21316. DA7218_MICBIAS_2_LEVEL_MASK
21317. DA7218_MICBIAS_2_LEVEL_SHIFT
21318. DA7218_MICBIAS_2_LP_MODE_MASK
21319. DA7218_MICBIAS_2_LP_MODE_SHIFT
21320. DA7218_MICBIAS_3_0V
21321. DA7218_MICBIAS_CTRL
21322. DA7218_MICBIAS_EN
21323. DA7218_MIC_1_AMP_EN_MASK
21324. DA7218_MIC_1_AMP_EN_SHIFT
21325. DA7218_MIC_1_AMP_GAIN_MASK
21326. DA7218_MIC_1_AMP_GAIN_SHIFT
21327. DA7218_MIC_1_AMP_IN_SEL_MASK
21328. DA7218_MIC_1_AMP_IN_SEL_SHIFT
21329. DA7218_MIC_1_AMP_MUTE_EN_MASK
21330. DA7218_MIC_1_AMP_MUTE_EN_SHIFT
21331. DA7218_MIC_1_CTRL
21332. DA7218_MIC_1_GAIN
21333. DA7218_MIC_1_SELECT
21334. DA7218_MIC_2_AMP_EN_MASK
21335. DA7218_MIC_2_AMP_EN_SHIFT
21336. DA7218_MIC_2_AMP_GAIN_MASK
21337. DA7218_MIC_2_AMP_GAIN_SHIFT
21338. DA7218_MIC_2_AMP_IN_SEL_MASK
21339. DA7218_MIC_2_AMP_IN_SEL_SHIFT
21340. DA7218_MIC_2_AMP_MUTE_EN_MASK
21341. DA7218_MIC_2_AMP_MUTE_EN_SHIFT
21342. DA7218_MIC_2_CTRL
21343. DA7218_MIC_2_GAIN
21344. DA7218_MIC_2_SELECT
21345. DA7218_MIC_AMP_GAIN_MAX
21346. DA7218_MIC_AMP_IN_SEL_DIFF
21347. DA7218_MIC_AMP_IN_SEL_SE_N
21348. DA7218_MIC_AMP_IN_SEL_SE_P
21349. DA7218_MIC_LVL_DET_DELAY
21350. DA7218_MIXIN_1_AMP_EN_MASK
21351. DA7218_MIXIN_1_AMP_EN_SHIFT
21352. DA7218_MIXIN_1_AMP_GAIN_MASK
21353. DA7218_MIXIN_1_AMP_GAIN_SHIFT
21354. DA7218_MIXIN_1_AMP_MUTE_EN_MASK
21355. DA7218_MIXIN_1_AMP_MUTE_EN_SHIFT
21356. DA7218_MIXIN_1_AMP_RAMP_EN_MASK
21357. DA7218_MIXIN_1_AMP_RAMP_EN_SHIFT
21358. DA7218_MIXIN_1_AMP_ZC_EN_MASK
21359. DA7218_MIXIN_1_AMP_ZC_EN_SHIFT
21360. DA7218_MIXIN_1_CTRL
21361. DA7218_MIXIN_1_GAIN
21362. DA7218_MIXIN_1_MIX_SEL_MASK
21363. DA7218_MIXIN_1_MIX_SEL_SHIFT
21364. DA7218_MIXIN_2_AMP_EN_MASK
21365. DA7218_MIXIN_2_AMP_EN_SHIFT
21366. DA7218_MIXIN_2_AMP_GAIN_MASK
21367. DA7218_MIXIN_2_AMP_GAIN_SHIFT
21368. DA7218_MIXIN_2_AMP_MUTE_EN_MASK
21369. DA7218_MIXIN_2_AMP_MUTE_EN_SHIFT
21370. DA7218_MIXIN_2_AMP_RAMP_EN_MASK
21371. DA7218_MIXIN_2_AMP_RAMP_EN_SHIFT
21372. DA7218_MIXIN_2_AMP_ZC_EN_MASK
21373. DA7218_MIXIN_2_AMP_ZC_EN_SHIFT
21374. DA7218_MIXIN_2_CTRL
21375. DA7218_MIXIN_2_GAIN
21376. DA7218_MIXIN_2_MIX_SEL_MASK
21377. DA7218_MIXIN_2_MIX_SEL_SHIFT
21378. DA7218_MIXIN_AMP_GAIN_MAX
21379. DA7218_MIXOUT_AMP_GAIN_MAX
21380. DA7218_MIXOUT_AMP_GAIN_MIN
21381. DA7218_MIXOUT_L_AMP_EN_MASK
21382. DA7218_MIXOUT_L_AMP_EN_SHIFT
21383. DA7218_MIXOUT_L_AMP_GAIN_MASK
21384. DA7218_MIXOUT_L_AMP_GAIN_SHIFT
21385. DA7218_MIXOUT_L_CTRL
21386. DA7218_MIXOUT_L_GAIN
21387. DA7218_MIXOUT_R_AMP_EN_MASK
21388. DA7218_MIXOUT_R_AMP_EN_SHIFT
21389. DA7218_MIXOUT_R_AMP_GAIN_MASK
21390. DA7218_MIXOUT_R_AMP_GAIN_SHIFT
21391. DA7218_MIXOUT_R_CTRL
21392. DA7218_MIXOUT_R_GAIN
21393. DA7218_MODE_SUBMIT_MASK
21394. DA7218_MODE_SUBMIT_SHIFT
21395. DA7218_NO_INVERT
21396. DA7218_NUM_SUPPLIES
21397. DA7218_OUTDAI_1L_INDAI_1L_GAIN_MASK
21398. DA7218_OUTDAI_1L_INDAI_1L_GAIN_SHIFT
21399. DA7218_OUTDAI_1L_INDAI_1R_GAIN_MASK
21400. DA7218_OUTDAI_1L_INDAI_1R_GAIN_SHIFT
21401. DA7218_OUTDAI_1L_INFILT_1L_GAIN_MASK
21402. DA7218_OUTDAI_1L_INFILT_1L_GAIN_SHIFT
21403. DA7218_OUTDAI_1L_INFILT_1R_GAIN_MASK
21404. DA7218_OUTDAI_1L_INFILT_1R_GAIN_SHIFT
21405. DA7218_OUTDAI_1L_INFILT_2L_GAIN_MASK
21406. DA7218_OUTDAI_1L_INFILT_2L_GAIN_SHIFT
21407. DA7218_OUTDAI_1L_INFILT_2R_GAIN_MASK
21408. DA7218_OUTDAI_1L_INFILT_2R_GAIN_SHIFT
21409. DA7218_OUTDAI_1L_SRC_MASK
21410. DA7218_OUTDAI_1L_SRC_SHIFT
21411. DA7218_OUTDAI_1L_TONEGEN_GAIN_MASK
21412. DA7218_OUTDAI_1L_TONEGEN_GAIN_SHIFT
21413. DA7218_OUTDAI_1R_INDAI_1L_GAIN_MASK
21414. DA7218_OUTDAI_1R_INDAI_1L_GAIN_SHIFT
21415. DA7218_OUTDAI_1R_INDAI_1R_GAIN_MASK
21416. DA7218_OUTDAI_1R_INDAI_1R_GAIN_SHIFT
21417. DA7218_OUTDAI_1R_INFILT_1L_GAIN_MASK
21418. DA7218_OUTDAI_1R_INFILT_1L_GAIN_SHIFT
21419. DA7218_OUTDAI_1R_INFILT_1R_GAIN_MASK
21420. DA7218_OUTDAI_1R_INFILT_1R_GAIN_SHIFT
21421. DA7218_OUTDAI_1R_INFILT_2L_GAIN_MASK
21422. DA7218_OUTDAI_1R_INFILT_2L_GAIN_SHIFT
21423. DA7218_OUTDAI_1R_INFILT_2R_GAIN_MASK
21424. DA7218_OUTDAI_1R_INFILT_2R_GAIN_SHIFT
21425. DA7218_OUTDAI_1R_SRC_MASK
21426. DA7218_OUTDAI_1R_SRC_SHIFT
21427. DA7218_OUTDAI_1R_TONEGEN_GAIN_MASK
21428. DA7218_OUTDAI_1R_TONEGEN_GAIN_SHIFT
21429. DA7218_OUTDAI_2L_INDAI_1L_GAIN_MASK
21430. DA7218_OUTDAI_2L_INDAI_1L_GAIN_SHIFT
21431. DA7218_OUTDAI_2L_INDAI_1R_GAIN_MASK
21432. DA7218_OUTDAI_2L_INDAI_1R_GAIN_SHIFT
21433. DA7218_OUTDAI_2L_INFILT_1L_GAIN_MASK
21434. DA7218_OUTDAI_2L_INFILT_1L_GAIN_SHIFT
21435. DA7218_OUTDAI_2L_INFILT_1R_GAIN_MASK
21436. DA7218_OUTDAI_2L_INFILT_1R_GAIN_SHIFT
21437. DA7218_OUTDAI_2L_INFILT_2L_GAIN_MASK
21438. DA7218_OUTDAI_2L_INFILT_2L_GAIN_SHIFT
21439. DA7218_OUTDAI_2L_INFILT_2R_GAIN_MASK
21440. DA7218_OUTDAI_2L_INFILT_2R_GAIN_SHIFT
21441. DA7218_OUTDAI_2L_SRC_MASK
21442. DA7218_OUTDAI_2L_SRC_SHIFT
21443. DA7218_OUTDAI_2L_TONEGEN_GAIN_MASK
21444. DA7218_OUTDAI_2L_TONEGEN_GAIN_SHIFT
21445. DA7218_OUTDAI_2R_INDAI_1L_GAIN_MASK
21446. DA7218_OUTDAI_2R_INDAI_1L_GAIN_SHIFT
21447. DA7218_OUTDAI_2R_INDAI_1R_GAIN_MASK
21448. DA7218_OUTDAI_2R_INDAI_1R_GAIN_SHIFT
21449. DA7218_OUTDAI_2R_INFILT_1L_GAIN_MASK
21450. DA7218_OUTDAI_2R_INFILT_1L_GAIN_SHIFT
21451. DA7218_OUTDAI_2R_INFILT_1R_GAIN_MASK
21452. DA7218_OUTDAI_2R_INFILT_1R_GAIN_SHIFT
21453. DA7218_OUTDAI_2R_INFILT_2L_GAIN_MASK
21454. DA7218_OUTDAI_2R_INFILT_2L_GAIN_SHIFT
21455. DA7218_OUTDAI_2R_INFILT_2R_GAIN_MASK
21456. DA7218_OUTDAI_2R_INFILT_2R_GAIN_SHIFT
21457. DA7218_OUTDAI_2R_SRC_MASK
21458. DA7218_OUTDAI_2R_SRC_SHIFT
21459. DA7218_OUTDAI_2R_TONEGEN_GAIN_MASK
21460. DA7218_OUTDAI_2R_TONEGEN_GAIN_SHIFT
21461. DA7218_OUTFILT_1L_INDAI_1L_GAIN_MASK
21462. DA7218_OUTFILT_1L_INDAI_1L_GAIN_SHIFT
21463. DA7218_OUTFILT_1L_INDAI_1R_GAIN_MASK
21464. DA7218_OUTFILT_1L_INDAI_1R_GAIN_SHIFT
21465. DA7218_OUTFILT_1L_INFILT_1L_GAIN_MASK
21466. DA7218_OUTFILT_1L_INFILT_1L_GAIN_SHIFT
21467. DA7218_OUTFILT_1L_INFILT_1R_GAIN_MASK
21468. DA7218_OUTFILT_1L_INFILT_1R_GAIN_SHIFT
21469. DA7218_OUTFILT_1L_INFILT_2L_GAIN_MASK
21470. DA7218_OUTFILT_1L_INFILT_2L_GAIN_SHIFT
21471. DA7218_OUTFILT_1L_INFILT_2R_GAIN_MASK
21472. DA7218_OUTFILT_1L_INFILT_2R_GAIN_SHIFT
21473. DA7218_OUTFILT_1L_SRC_MASK
21474. DA7218_OUTFILT_1L_SRC_SHIFT
21475. DA7218_OUTFILT_1L_TONEGEN_GAIN_MASK
21476. DA7218_OUTFILT_1L_TONEGEN_GAIN_SHIFT
21477. DA7218_OUTFILT_1R_INDAI_1L_GAIN_MASK
21478. DA7218_OUTFILT_1R_INDAI_1L_GAIN_SHIFT
21479. DA7218_OUTFILT_1R_INDAI_1R_GAIN_MASK
21480. DA7218_OUTFILT_1R_INDAI_1R_GAIN_SHIFT
21481. DA7218_OUTFILT_1R_INFILT_1L_GAIN_MASK
21482. DA7218_OUTFILT_1R_INFILT_1L_GAIN_SHIFT
21483. DA7218_OUTFILT_1R_INFILT_1R_GAIN_MASK
21484. DA7218_OUTFILT_1R_INFILT_1R_GAIN_SHIFT
21485. DA7218_OUTFILT_1R_INFILT_2L_GAIN_MASK
21486. DA7218_OUTFILT_1R_INFILT_2L_GAIN_SHIFT
21487. DA7218_OUTFILT_1R_INFILT_2R_GAIN_MASK
21488. DA7218_OUTFILT_1R_INFILT_2R_GAIN_SHIFT
21489. DA7218_OUTFILT_1R_SRC_MASK
21490. DA7218_OUTFILT_1R_SRC_SHIFT
21491. DA7218_OUTFILT_1R_TONEGEN_GAIN_MASK
21492. DA7218_OUTFILT_1R_TONEGEN_GAIN_SHIFT
21493. DA7218_OUTFILT_ST_1L_SRC_MASK
21494. DA7218_OUTFILT_ST_1L_SRC_SHIFT
21495. DA7218_OUTFILT_ST_1R_SRC_MASK
21496. DA7218_OUTFILT_ST_1R_SRC_SHIFT
21497. DA7218_OUT_1L_BIQ_5STAGE_SEL_MASK
21498. DA7218_OUT_1L_BIQ_5STAGE_SEL_SHIFT
21499. DA7218_OUT_1L_DIGITAL_GAIN_MASK
21500. DA7218_OUT_1L_DIGITAL_GAIN_SHIFT
21501. DA7218_OUT_1L_FILTER_CTRL
21502. DA7218_OUT_1L_FILTER_EN_MASK
21503. DA7218_OUT_1L_FILTER_EN_SHIFT
21504. DA7218_OUT_1L_GAIN
21505. DA7218_OUT_1L_MUTE_EN_MASK
21506. DA7218_OUT_1L_MUTE_EN_SHIFT
21507. DA7218_OUT_1L_RAMP_EN_MASK
21508. DA7218_OUT_1L_RAMP_EN_SHIFT
21509. DA7218_OUT_1L_SUBRANGE_EN_MASK
21510. DA7218_OUT_1L_SUBRANGE_EN_SHIFT
21511. DA7218_OUT_1R_BIQ_5STAGE_SEL_MASK
21512. DA7218_OUT_1R_BIQ_5STAGE_SEL_SHIFT
21513. DA7218_OUT_1R_DIGITAL_GAIN_MASK
21514. DA7218_OUT_1R_DIGITAL_GAIN_SHIFT
21515. DA7218_OUT_1R_FILTER_CTRL
21516. DA7218_OUT_1R_FILTER_EN_MASK
21517. DA7218_OUT_1R_FILTER_EN_SHIFT
21518. DA7218_OUT_1R_GAIN
21519. DA7218_OUT_1R_MUTE_EN_MASK
21520. DA7218_OUT_1R_MUTE_EN_SHIFT
21521. DA7218_OUT_1R_RAMP_EN_MASK
21522. DA7218_OUT_1R_RAMP_EN_SHIFT
21523. DA7218_OUT_1R_SUBRANGE_EN_MASK
21524. DA7218_OUT_1R_SUBRANGE_EN_SHIFT
21525. DA7218_OUT_1_AUDIO_HPF_CORNER_MASK
21526. DA7218_OUT_1_AUDIO_HPF_CORNER_SHIFT
21527. DA7218_OUT_1_BIQ_5STAGE_ADDR
21528. DA7218_OUT_1_BIQ_5STAGE_ADDR_MASK
21529. DA7218_OUT_1_BIQ_5STAGE_ADDR_SHIFT
21530. DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE
21531. DA7218_OUT_1_BIQ_5STAGE_CTRL
21532. DA7218_OUT_1_BIQ_5STAGE_DATA
21533. DA7218_OUT_1_BIQ_5STAGE_DATA_MASK
21534. DA7218_OUT_1_BIQ_5STAGE_DATA_SHIFT
21535. DA7218_OUT_1_BIQ_5STAGE_FILTER_EN_MASK
21536. DA7218_OUT_1_BIQ_5STAGE_FILTER_EN_SHIFT
21537. DA7218_OUT_1_BIQ_5STAGE_MUTE_EN_MASK
21538. DA7218_OUT_1_BIQ_5STAGE_MUTE_EN_SHIFT
21539. DA7218_OUT_1_EQ_12_FILTER_CTRL
21540. DA7218_OUT_1_EQ_34_FILTER_CTRL
21541. DA7218_OUT_1_EQ_5_FILTER_CTRL
21542. DA7218_OUT_1_EQ_BAND1_MASK
21543. DA7218_OUT_1_EQ_BAND1_SHIFT
21544. DA7218_OUT_1_EQ_BAND2_MASK
21545. DA7218_OUT_1_EQ_BAND2_SHIFT
21546. DA7218_OUT_1_EQ_BAND3_MASK
21547. DA7218_OUT_1_EQ_BAND3_SHIFT
21548. DA7218_OUT_1_EQ_BAND4_MASK
21549. DA7218_OUT_1_EQ_BAND4_SHIFT
21550. DA7218_OUT_1_EQ_BAND5_MASK
21551. DA7218_OUT_1_EQ_BAND5_SHIFT
21552. DA7218_OUT_1_EQ_EN_MASK
21553. DA7218_OUT_1_EQ_EN_SHIFT
21554. DA7218_OUT_1_HPF_EN_MASK
21555. DA7218_OUT_1_HPF_EN_SHIFT
21556. DA7218_OUT_1_HPF_FILTER_CTRL
21557. DA7218_OUT_1_VOICE_EN_MASK
21558. DA7218_OUT_1_VOICE_EN_SHIFT
21559. DA7218_OUT_1_VOICE_HPF_CORNER_MASK
21560. DA7218_OUT_1_VOICE_HPF_CORNER_SHIFT
21561. DA7218_OUT_BIQ_5STAGE_SEL_MAX
21562. DA7218_OUT_DIGITAL_GAIN_MAX
21563. DA7218_OUT_DIGITAL_GAIN_MIN
21564. DA7218_OUT_EQ_BAND_MAX
21565. DA7218_PC_COUNT
21566. DA7218_PC_FREERUN_MASK
21567. DA7218_PC_FREERUN_SHIFT
21568. DA7218_PC_RESYNC_AUTO_MASK
21569. DA7218_PC_RESYNC_AUTO_SHIFT
21570. DA7218_PLL_CTRL
21571. DA7218_PLL_FBDIV_FRAC_BOT_MASK
21572. DA7218_PLL_FBDIV_FRAC_BOT_SHIFT
21573. DA7218_PLL_FBDIV_FRAC_TOP_MASK
21574. DA7218_PLL_FBDIV_FRAC_TOP_SHIFT
21575. DA7218_PLL_FBDIV_INTEGER_MASK
21576. DA7218_PLL_FBDIV_INTEGER_SHIFT
21577. DA7218_PLL_FRAC_BOT
21578. DA7218_PLL_FRAC_TOP
21579. DA7218_PLL_FREQ_OUT_90316
21580. DA7218_PLL_FREQ_OUT_98304
21581. DA7218_PLL_INDIV_18_TO_36_MHZ
21582. DA7218_PLL_INDIV_18_TO_36_MHZ_VAL
21583. DA7218_PLL_INDIV_2_TO_4_5_MHZ
21584. DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL
21585. DA7218_PLL_INDIV_36_TO_54_MHZ
21586. DA7218_PLL_INDIV_36_TO_54_MHZ_VAL
21587. DA7218_PLL_INDIV_4_5_TO_9_MHZ
21588. DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL
21589. DA7218_PLL_INDIV_9_TO_18_MHZ
21590. DA7218_PLL_INDIV_9_TO_18_MHZ_VAL
21591. DA7218_PLL_INDIV_MASK
21592. DA7218_PLL_INDIV_SHIFT
21593. DA7218_PLL_INTEGER
21594. DA7218_PLL_MCLK_SQR_EN_MASK
21595. DA7218_PLL_MCLK_SQR_EN_SHIFT
21596. DA7218_PLL_MODE_BYPASS
21597. DA7218_PLL_MODE_MASK
21598. DA7218_PLL_MODE_NORMAL
21599. DA7218_PLL_MODE_SHIFT
21600. DA7218_PLL_MODE_SRM
21601. DA7218_PLL_REFOSC_CAL
21602. DA7218_PLL_REFOSC_CAL_CTRL_MASK
21603. DA7218_PLL_REFOSC_CAL_CTRL_SHIFT
21604. DA7218_PLL_REFOSC_CAL_EN_MASK
21605. DA7218_PLL_REFOSC_CAL_EN_SHIFT
21606. DA7218_PLL_REFOSC_CAL_START_MASK
21607. DA7218_PLL_REFOSC_CAL_START_SHIFT
21608. DA7218_PLL_SRM_STATUS_MASK
21609. DA7218_PLL_SRM_STATUS_SHIFT
21610. DA7218_PLL_SRM_STATUS_SRM_LOCK
21611. DA7218_PLL_STATUS
21612. DA7218_REFERENCES
21613. DA7218_REF_OSC_CHECK_DELAY_MAX
21614. DA7218_REF_OSC_CHECK_DELAY_MIN
21615. DA7218_REF_OSC_CHECK_TRIES
21616. DA7218_SC1_BUSY_MASK
21617. DA7218_SC1_BUSY_SHIFT
21618. DA7218_SC2_BUSY_MASK
21619. DA7218_SC2_BUSY_SHIFT
21620. DA7218_SIDETONE_BIQ_3STAGE_ADDR
21621. DA7218_SIDETONE_BIQ_3STAGE_ADDR_MASK
21622. DA7218_SIDETONE_BIQ_3STAGE_ADDR_SHIFT
21623. DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE
21624. DA7218_SIDETONE_BIQ_3STAGE_DATA
21625. DA7218_SIDETONE_BIQ_3STAGE_DATA_MASK
21626. DA7218_SIDETONE_BIQ_3STAGE_DATA_SHIFT
21627. DA7218_SIDETONE_CTRL
21628. DA7218_SIDETONE_FILTER_EN_MASK
21629. DA7218_SIDETONE_FILTER_EN_SHIFT
21630. DA7218_SIDETONE_GAIN
21631. DA7218_SIDETONE_GAIN_MASK
21632. DA7218_SIDETONE_GAIN_SHIFT
21633. DA7218_SIDETONE_IN_SELECT
21634. DA7218_SIDETONE_IN_SELECT_MASK
21635. DA7218_SIDETONE_IN_SELECT_MAX
21636. DA7218_SIDETONE_IN_SELECT_SHIFT
21637. DA7218_SIDETONE_MUTE_EN_MASK
21638. DA7218_SIDETONE_MUTE_EN_SHIFT
21639. DA7218_SOFT_RESET
21640. DA7218_SPARE1
21641. DA7218_SPARE1_MASK
21642. DA7218_SPARE1_SHIFT
21643. DA7218_SR
21644. DA7218_SRM_CHECK_DELAY
21645. DA7218_SRM_CHECK_TRIES
21646. DA7218_SR_11025
21647. DA7218_SR_12000
21648. DA7218_SR_16000
21649. DA7218_SR_22050
21650. DA7218_SR_24000
21651. DA7218_SR_32000
21652. DA7218_SR_44100
21653. DA7218_SR_48000
21654. DA7218_SR_8000
21655. DA7218_SR_88200
21656. DA7218_SR_96000
21657. DA7218_SR_ADC_MASK
21658. DA7218_SR_ADC_SHIFT
21659. DA7218_SR_DAC_MASK
21660. DA7218_SR_DAC_SHIFT
21661. DA7218_START_STOPN_MASK
21662. DA7218_START_STOPN_SHIFT
21663. DA7218_STATUS1
21664. DA7218_STATUS_SPARE1_MASK
21665. DA7218_STATUS_SPARE1_SHIFT
21666. DA7218_SUPPLY_VDD
21667. DA7218_SUPPLY_VDDIO
21668. DA7218_SUPPLY_VDDMIC
21669. DA7218_SWG_SEL_MASK
21670. DA7218_SWG_SEL_MAX
21671. DA7218_SWG_SEL_SHIFT
21672. DA7218_SWITCH_EN_MAX
21673. DA7218_SYSCLK_MCLK
21674. DA7218_SYSCLK_PLL
21675. DA7218_SYSCLK_PLL_SRM
21676. DA7218_SYSTEM_ACTIVE
21677. DA7218_SYSTEM_ACTIVE_MASK
21678. DA7218_SYSTEM_ACTIVE_SHIFT
21679. DA7218_SYSTEM_MODES_INPUT
21680. DA7218_SYSTEM_MODES_OUTPUT
21681. DA7218_SYSTEM_STATUS
21682. DA7218_TONE_GEN_CFG1
21683. DA7218_TONE_GEN_CFG2
21684. DA7218_TONE_GEN_CYCLES
21685. DA7218_TONE_GEN_FREQ1_L
21686. DA7218_TONE_GEN_FREQ1_U
21687. DA7218_TONE_GEN_FREQ2_L
21688. DA7218_TONE_GEN_FREQ2_U
21689. DA7218_TONE_GEN_OFF_PER
21690. DA7218_TONE_GEN_ON_PER
21691. DA7218_VOICE_HPF_CORNER_MAX
21692. DA7219_AAD_ADC_1BIT_RPT_1
21693. DA7219_AAD_ADC_1BIT_RPT_2
21694. DA7219_AAD_ADC_1BIT_RPT_4
21695. DA7219_AAD_ADC_1BIT_RPT_8
21696. DA7219_AAD_BTN_AVG_1
21697. DA7219_AAD_BTN_AVG_2
21698. DA7219_AAD_BTN_AVG_4
21699. DA7219_AAD_BTN_AVG_8
21700. DA7219_AAD_BTN_CFG_100MS
21701. DA7219_AAD_BTN_CFG_10MS
21702. DA7219_AAD_BTN_CFG_200MS
21703. DA7219_AAD_BTN_CFG_2MS
21704. DA7219_AAD_BTN_CFG_500MS
21705. DA7219_AAD_BTN_CFG_50MS
21706. DA7219_AAD_BTN_CFG_5MS
21707. DA7219_AAD_HPTEST_INT_OSC_PATH_DELAY
21708. DA7219_AAD_HPTEST_PERIOD
21709. DA7219_AAD_HPTEST_RAMP_FREQ
21710. DA7219_AAD_HPTEST_RAMP_FREQ_INT_OSC
21711. DA7219_AAD_IRQ_REG_A
21712. DA7219_AAD_IRQ_REG_B
21713. DA7219_AAD_IRQ_REG_MAX
21714. DA7219_AAD_JACK_DET_RATE_128_256MS
21715. DA7219_AAD_JACK_DET_RATE_256_512MS
21716. DA7219_AAD_JACK_DET_RATE_32_64MS
21717. DA7219_AAD_JACK_DET_RATE_64_128MS
21718. DA7219_AAD_JACK_INS_DEB_100MS
21719. DA7219_AAD_JACK_INS_DEB_10MS
21720. DA7219_AAD_JACK_INS_DEB_1S
21721. DA7219_AAD_JACK_INS_DEB_200MS
21722. DA7219_AAD_JACK_INS_DEB_20MS
21723. DA7219_AAD_JACK_INS_DEB_500MS
21724. DA7219_AAD_JACK_INS_DEB_50MS
21725. DA7219_AAD_JACK_INS_DEB_5MS
21726. DA7219_AAD_JACK_REM_DEB_10MS
21727. DA7219_AAD_JACK_REM_DEB_1MS
21728. DA7219_AAD_JACK_REM_DEB_20MS
21729. DA7219_AAD_JACK_REM_DEB_5MS
21730. DA7219_AAD_MAX_BUTTONS
21731. DA7219_AAD_MICBIAS_CHK_DELAY
21732. DA7219_AAD_MICBIAS_CHK_RETRIES
21733. DA7219_AAD_MICBIAS_PULSE_LVL_2_8V
21734. DA7219_AAD_MICBIAS_PULSE_LVL_2_9V
21735. DA7219_AAD_MICBIAS_PULSE_LVL_OFF
21736. DA7219_AAD_MIC_DET_THR_1000_OHMS
21737. DA7219_AAD_MIC_DET_THR_200_OHMS
21738. DA7219_AAD_MIC_DET_THR_500_OHMS
21739. DA7219_AAD_MIC_DET_THR_750_OHMS
21740. DA7219_AAD_REPORT_ALL_MASK
21741. DA7219_ACCDET_CONFIG_1
21742. DA7219_ACCDET_CONFIG_2
21743. DA7219_ACCDET_CONFIG_3
21744. DA7219_ACCDET_CONFIG_4
21745. DA7219_ACCDET_CONFIG_5
21746. DA7219_ACCDET_CONFIG_6
21747. DA7219_ACCDET_CONFIG_7
21748. DA7219_ACCDET_CONFIG_8
21749. DA7219_ACCDET_EN_MASK
21750. DA7219_ACCDET_EN_SHIFT
21751. DA7219_ACCDET_IRQ_EVENT_A
21752. DA7219_ACCDET_IRQ_EVENT_B
21753. DA7219_ACCDET_IRQ_MASK_A
21754. DA7219_ACCDET_IRQ_MASK_B
21755. DA7219_ACCDET_PAUSE_MASK
21756. DA7219_ACCDET_PAUSE_SHIFT
21757. DA7219_ACCDET_STATUS_A
21758. DA7219_ACCDET_STATUS_B
21759. DA7219_ADC_1_BIT_REPEAT_MASK
21760. DA7219_ADC_1_BIT_REPEAT_SHIFT
21761. DA7219_ADC_AUDIO_HPF_CORNER_MASK
21762. DA7219_ADC_AUDIO_HPF_CORNER_SHIFT
21763. DA7219_ADC_FILTERS1
21764. DA7219_ADC_HPF_EN_MASK
21765. DA7219_ADC_HPF_EN_SHIFT
21766. DA7219_ADC_L_BIAS_MASK
21767. DA7219_ADC_L_BIAS_SHIFT
21768. DA7219_ADC_L_CTRL
21769. DA7219_ADC_L_DIGITAL_GAIN_MASK
21770. DA7219_ADC_L_DIGITAL_GAIN_MAX
21771. DA7219_ADC_L_DIGITAL_GAIN_SHIFT
21772. DA7219_ADC_L_DIGITAL_GAIN_STATUS_MASK
21773. DA7219_ADC_L_DIGITAL_GAIN_STATUS_SHIFT
21774. DA7219_ADC_L_EN_MASK
21775. DA7219_ADC_L_EN_SHIFT
21776. DA7219_ADC_L_GAIN
21777. DA7219_ADC_L_GAIN_STATUS
21778. DA7219_ADC_L_MUTE_EN_MASK
21779. DA7219_ADC_L_MUTE_EN_SHIFT
21780. DA7219_ADC_L_RAMP_EN_MASK
21781. DA7219_ADC_L_RAMP_EN_SHIFT
21782. DA7219_ADC_MODE_MASK
21783. DA7219_ADC_MODE_SHIFT
21784. DA7219_ADC_VOICE_EN_MASK
21785. DA7219_ADC_VOICE_EN_SHIFT
21786. DA7219_ADC_VOICE_HPF_CORNER_MASK
21787. DA7219_ADC_VOICE_HPF_CORNER_SHIFT
21788. DA7219_ALC_ANA_GAIN_LIMITS
21789. DA7219_ALC_ANA_GAIN_MAX
21790. DA7219_ALC_ANA_GAIN_MAX_MASK
21791. DA7219_ALC_ANA_GAIN_MAX_SHIFT
21792. DA7219_ALC_ANA_GAIN_MIN
21793. DA7219_ALC_ANA_GAIN_MIN_MASK
21794. DA7219_ALC_ANA_GAIN_MIN_SHIFT
21795. DA7219_ALC_ANTICLIP_CTRL
21796. DA7219_ALC_ANTICLIP_LEVEL
21797. DA7219_ALC_ANTICLIP_LEVEL_MASK
21798. DA7219_ALC_ANTICLIP_LEVEL_SHIFT
21799. DA7219_ALC_ANTICLIP_STEP_MASK
21800. DA7219_ALC_ANTICLIP_STEP_MAX
21801. DA7219_ALC_ANTICLIP_STEP_SHIFT
21802. DA7219_ALC_ANTIPCLIP_EN_MASK
21803. DA7219_ALC_ANTIPCLIP_EN_SHIFT
21804. DA7219_ALC_ATTACK_MASK
21805. DA7219_ALC_ATTACK_MAX
21806. DA7219_ALC_ATTACK_SHIFT
21807. DA7219_ALC_ATTEN_GAIN_MAX
21808. DA7219_ALC_ATTEN_MAX_MASK
21809. DA7219_ALC_ATTEN_MAX_SHIFT
21810. DA7219_ALC_AUTO_CALIB_EN_MASK
21811. DA7219_ALC_AUTO_CALIB_EN_SHIFT
21812. DA7219_ALC_CALIB_OVERFLOW_MASK
21813. DA7219_ALC_CALIB_OVERFLOW_SHIFT
21814. DA7219_ALC_CTRL1
21815. DA7219_ALC_CTRL2
21816. DA7219_ALC_CTRL3
21817. DA7219_ALC_EN_MASK
21818. DA7219_ALC_EN_SHIFT
21819. DA7219_ALC_GAIN_LIMITS
21820. DA7219_ALC_GAIN_MAX_MASK
21821. DA7219_ALC_GAIN_MAX_SHIFT
21822. DA7219_ALC_HOLD_MASK
21823. DA7219_ALC_HOLD_MAX
21824. DA7219_ALC_HOLD_SHIFT
21825. DA7219_ALC_INTEG_ATTACK_MASK
21826. DA7219_ALC_INTEG_ATTACK_SHIFT
21827. DA7219_ALC_INTEG_MAX
21828. DA7219_ALC_INTEG_RELEASE_MASK
21829. DA7219_ALC_INTEG_RELEASE_SHIFT
21830. DA7219_ALC_NOISE
21831. DA7219_ALC_NOISE_MASK
21832. DA7219_ALC_NOISE_SHIFT
21833. DA7219_ALC_OFFSET_AUTO_M_L
21834. DA7219_ALC_OFFSET_AUTO_M_L_MASK
21835. DA7219_ALC_OFFSET_AUTO_M_L_SHIFT
21836. DA7219_ALC_OFFSET_AUTO_U_L
21837. DA7219_ALC_OFFSET_AUTO_U_L_MASK
21838. DA7219_ALC_OFFSET_AUTO_U_L_SHIFT
21839. DA7219_ALC_OFFSET_EN_MASK
21840. DA7219_ALC_OFFSET_EN_SHIFT
21841. DA7219_ALC_RELEASE_MASK
21842. DA7219_ALC_RELEASE_MAX
21843. DA7219_ALC_RELEASE_SHIFT
21844. DA7219_ALC_SYNC_MODE_MASK
21845. DA7219_ALC_SYNC_MODE_SHIFT
21846. DA7219_ALC_TARGET_MAX
21847. DA7219_ALC_TARGET_MIN
21848. DA7219_ALC_THRESHOLD_MAX
21849. DA7219_ALC_THRESHOLD_MAX_MASK
21850. DA7219_ALC_THRESHOLD_MAX_SHIFT
21851. DA7219_ALC_THRESHOLD_MIN_MASK
21852. DA7219_ALC_THRESHOLD_MIN_SHIFT
21853. DA7219_AUDIO_HPF_CORNER_MAX
21854. DA7219_A_D_BUTTON_THRESH_MASK
21855. DA7219_A_D_BUTTON_THRESH_SHIFT
21856. DA7219_BEEP_CYCLES_MASK
21857. DA7219_BEEP_CYCLES_SHIFT
21858. DA7219_BEEP_OFF_PER_MASK
21859. DA7219_BEEP_OFF_PER_SHIFT
21860. DA7219_BEEP_ON_OFF_MAX
21861. DA7219_BEEP_ON_PER_MASK
21862. DA7219_BEEP_ON_PER_SHIFT
21863. DA7219_BIAS_EN_MASK
21864. DA7219_BIAS_EN_SHIFT
21865. DA7219_BUTTON_AVERAGE_MASK
21866. DA7219_BUTTON_AVERAGE_SHIFT
21867. DA7219_BUTTON_CONFIG_MASK
21868. DA7219_BUTTON_CONFIG_SHIFT
21869. DA7219_BUTTON_TYPE_STS_MASK
21870. DA7219_BUTTON_TYPE_STS_SHIFT
21871. DA7219_BYTE_MASK
21872. DA7219_BYTE_SHIFT
21873. DA7219_B_C_BUTTON_THRESH_MASK
21874. DA7219_B_C_BUTTON_THRESH_SHIFT
21875. DA7219_CHIP_ID1
21876. DA7219_CHIP_ID1_MASK
21877. DA7219_CHIP_ID1_SHIFT
21878. DA7219_CHIP_ID2
21879. DA7219_CHIP_ID2_MASK
21880. DA7219_CHIP_ID2_SHIFT
21881. DA7219_CHIP_MAJOR_MASK
21882. DA7219_CHIP_MAJOR_SHIFT
21883. DA7219_CHIP_MINOR_MASK
21884. DA7219_CHIP_MINOR_SHIFT
21885. DA7219_CHIP_REVISION
21886. DA7219_CIF_CTRL
21887. DA7219_CIF_I2C_ADDR_CFG
21888. DA7219_CIF_I2C_ADDR_CFG_MASK
21889. DA7219_CIF_I2C_ADDR_CFG_SHIFT
21890. DA7219_CIF_I2C_WRITE_MODE_MASK
21891. DA7219_CIF_I2C_WRITE_MODE_SHIFT
21892. DA7219_CIF_REG_SOFT_RESET_MASK
21893. DA7219_CIF_REG_SOFT_RESET_SHIFT
21894. DA7219_CIF_TIMEOUT_CTRL
21895. DA7219_CLKSRC_MCLK
21896. DA7219_CLKSRC_MCLK_SQR
21897. DA7219_CP_CTRL
21898. DA7219_CP_DELAY
21899. DA7219_CP_EN_MASK
21900. DA7219_CP_EN_SHIFT
21901. DA7219_CP_MCHANGE_DAC_VOL
21902. DA7219_CP_MCHANGE_LARGEST_VOL
21903. DA7219_CP_MCHANGE_MASK
21904. DA7219_CP_MCHANGE_MAX
21905. DA7219_CP_MCHANGE_REL_MASK
21906. DA7219_CP_MCHANGE_SHIFT
21907. DA7219_CP_MCHANGE_SIG_MAG
21908. DA7219_CP_THRESH_VDD2_MASK
21909. DA7219_CP_THRESH_VDD2_MAX
21910. DA7219_CP_THRESH_VDD2_SHIFT
21911. DA7219_CP_VOL_THRESHOLD1
21912. DA7219_C_MIC_BUTTON_THRESH_MASK
21913. DA7219_C_MIC_BUTTON_THRESH_SHIFT
21914. DA7219_DAC_AUDIO_HPF_CORNER_MASK
21915. DA7219_DAC_AUDIO_HPF_CORNER_SHIFT
21916. DA7219_DAC_DIGITAL_GAIN_0DB
21917. DA7219_DAC_DIGITAL_GAIN_MAX
21918. DA7219_DAC_EQ_BAND1_MASK
21919. DA7219_DAC_EQ_BAND1_SHIFT
21920. DA7219_DAC_EQ_BAND2_MASK
21921. DA7219_DAC_EQ_BAND2_SHIFT
21922. DA7219_DAC_EQ_BAND3_MASK
21923. DA7219_DAC_EQ_BAND3_SHIFT
21924. DA7219_DAC_EQ_BAND4_MASK
21925. DA7219_DAC_EQ_BAND4_SHIFT
21926. DA7219_DAC_EQ_BAND5_MASK
21927. DA7219_DAC_EQ_BAND5_SHIFT
21928. DA7219_DAC_EQ_BAND_MAX
21929. DA7219_DAC_EQ_EN_MASK
21930. DA7219_DAC_EQ_EN_SHIFT
21931. DA7219_DAC_FILTERS1
21932. DA7219_DAC_FILTERS2
21933. DA7219_DAC_FILTERS3
21934. DA7219_DAC_FILTERS4
21935. DA7219_DAC_FILTERS5
21936. DA7219_DAC_HPF_EN_MASK
21937. DA7219_DAC_HPF_EN_SHIFT
21938. DA7219_DAC_L_CTRL
21939. DA7219_DAC_L_DIGITAL_GAIN_MASK
21940. DA7219_DAC_L_DIGITAL_GAIN_SHIFT
21941. DA7219_DAC_L_DIGITAL_GAIN_STATUS_MASK
21942. DA7219_DAC_L_DIGITAL_GAIN_STATUS_SHIFT
21943. DA7219_DAC_L_EN_MASK
21944. DA7219_DAC_L_EN_SHIFT
21945. DA7219_DAC_L_GAIN
21946. DA7219_DAC_L_GAIN_STATUS
21947. DA7219_DAC_L_INV_MASK
21948. DA7219_DAC_L_INV_SHIFT
21949. DA7219_DAC_L_MONO_MASK
21950. DA7219_DAC_L_MONO_SHIFT
21951. DA7219_DAC_L_MUTE_EN_MASK
21952. DA7219_DAC_L_MUTE_EN_SHIFT
21953. DA7219_DAC_L_RAMP_EN_MASK
21954. DA7219_DAC_L_RAMP_EN_SHIFT
21955. DA7219_DAC_L_SRC_MASK
21956. DA7219_DAC_L_SRC_SHIFT
21957. DA7219_DAC_L_SRC_TONEGEN
21958. DA7219_DAC_MODE_MASK
21959. DA7219_DAC_MODE_SHIFT
21960. DA7219_DAC_NG_CTRL
21961. DA7219_DAC_NG_EN_MASK
21962. DA7219_DAC_NG_EN_SHIFT
21963. DA7219_DAC_NG_OFF_THRESH
21964. DA7219_DAC_NG_OFF_THRESHOLD_MASK
21965. DA7219_DAC_NG_OFF_THRESHOLD_SHIFT
21966. DA7219_DAC_NG_ON_THRESH
21967. DA7219_DAC_NG_ON_THRESHOLD_MASK
21968. DA7219_DAC_NG_ON_THRESHOLD_SHIFT
21969. DA7219_DAC_NG_RAMPDN_RATE_MASK
21970. DA7219_DAC_NG_RAMPDN_RATE_SHIFT
21971. DA7219_DAC_NG_RAMPUP_RATE_MASK
21972. DA7219_DAC_NG_RAMPUP_RATE_SHIFT
21973. DA7219_DAC_NG_RAMP_RATE_MAX
21974. DA7219_DAC_NG_SETUP_TIME
21975. DA7219_DAC_NG_SETUP_TIME_MASK
21976. DA7219_DAC_NG_SETUP_TIME_MAX
21977. DA7219_DAC_NG_SETUP_TIME_SHIFT
21978. DA7219_DAC_NG_THRESHOLD_MAX
21979. DA7219_DAC_R_CTRL
21980. DA7219_DAC_R_DIGITAL_GAIN_MASK
21981. DA7219_DAC_R_DIGITAL_GAIN_SHIFT
21982. DA7219_DAC_R_DIGITAL_GAIN_STATUS_MASK
21983. DA7219_DAC_R_DIGITAL_GAIN_STATUS_SHIFT
21984. DA7219_DAC_R_EN_MASK
21985. DA7219_DAC_R_EN_SHIFT
21986. DA7219_DAC_R_GAIN
21987. DA7219_DAC_R_GAIN_STATUS
21988. DA7219_DAC_R_INV_MASK
21989. DA7219_DAC_R_INV_SHIFT
21990. DA7219_DAC_R_MONO_MASK
21991. DA7219_DAC_R_MONO_SHIFT
21992. DA7219_DAC_R_MUTE_EN_MASK
21993. DA7219_DAC_R_MUTE_EN_SHIFT
21994. DA7219_DAC_R_RAMP_EN_MASK
21995. DA7219_DAC_R_RAMP_EN_SHIFT
21996. DA7219_DAC_R_SRC_MASK
21997. DA7219_DAC_R_SRC_SHIFT
21998. DA7219_DAC_R_SRC_TONEGEN
21999. DA7219_DAC_SOFTMUTE_EN_MASK
22000. DA7219_DAC_SOFTMUTE_EN_SHIFT
22001. DA7219_DAC_SOFTMUTE_RATE_MASK
22002. DA7219_DAC_SOFTMUTE_RATE_MAX
22003. DA7219_DAC_SOFTMUTE_RATE_SHIFT
22004. DA7219_DAC_VOICE_EN_MASK
22005. DA7219_DAC_VOICE_EN_SHIFT
22006. DA7219_DAC_VOICE_HPF_CORNER_MASK
22007. DA7219_DAC_VOICE_HPF_CORNER_SHIFT
22008. DA7219_DAI_BCLKS_PER_WCLK_128
22009. DA7219_DAI_BCLKS_PER_WCLK_256
22010. DA7219_DAI_BCLKS_PER_WCLK_32
22011. DA7219_DAI_BCLKS_PER_WCLK_64
22012. DA7219_DAI_BCLKS_PER_WCLK_MASK
22013. DA7219_DAI_BCLKS_PER_WCLK_SHIFT
22014. DA7219_DAI_BCLK_IDX
22015. DA7219_DAI_CH_NUM_MASK
22016. DA7219_DAI_CH_NUM_MAX
22017. DA7219_DAI_CH_NUM_SHIFT
22018. DA7219_DAI_CLK_EN_MASK
22019. DA7219_DAI_CLK_EN_SHIFT
22020. DA7219_DAI_CLK_MODE
22021. DA7219_DAI_CLK_POL_INV
22022. DA7219_DAI_CLK_POL_MASK
22023. DA7219_DAI_CLK_POL_SHIFT
22024. DA7219_DAI_CTRL
22025. DA7219_DAI_EN_MASK
22026. DA7219_DAI_EN_SHIFT
22027. DA7219_DAI_FORMAT_DSP
22028. DA7219_DAI_FORMAT_I2S
22029. DA7219_DAI_FORMAT_LEFT_J
22030. DA7219_DAI_FORMAT_MASK
22031. DA7219_DAI_FORMAT_RIGHT_J
22032. DA7219_DAI_FORMAT_SHIFT
22033. DA7219_DAI_L_SRC_MASK
22034. DA7219_DAI_L_SRC_SHIFT
22035. DA7219_DAI_NUM_CLKS
22036. DA7219_DAI_OE_MASK
22037. DA7219_DAI_OE_SHIFT
22038. DA7219_DAI_OFFSET_LOWER
22039. DA7219_DAI_OFFSET_LOWER_MASK
22040. DA7219_DAI_OFFSET_LOWER_SHIFT
22041. DA7219_DAI_OFFSET_MAX
22042. DA7219_DAI_OFFSET_UPPER
22043. DA7219_DAI_OFFSET_UPPER_MASK
22044. DA7219_DAI_OFFSET_UPPER_SHIFT
22045. DA7219_DAI_R_SRC_MASK
22046. DA7219_DAI_R_SRC_SHIFT
22047. DA7219_DAI_TDM_CH_EN_MASK
22048. DA7219_DAI_TDM_CH_EN_SHIFT
22049. DA7219_DAI_TDM_CTRL
22050. DA7219_DAI_TDM_MAX_SLOTS
22051. DA7219_DAI_TDM_MODE_EN_MASK
22052. DA7219_DAI_TDM_MODE_EN_SHIFT
22053. DA7219_DAI_WCLK_IDX
22054. DA7219_DAI_WCLK_POL_INV
22055. DA7219_DAI_WCLK_POL_MASK
22056. DA7219_DAI_WCLK_POL_SHIFT
22057. DA7219_DAI_WCLK_TRI_STATE_MASK
22058. DA7219_DAI_WCLK_TRI_STATE_SHIFT
22059. DA7219_DAI_WORD_LENGTH_MASK
22060. DA7219_DAI_WORD_LENGTH_S16_LE
22061. DA7219_DAI_WORD_LENGTH_S20_LE
22062. DA7219_DAI_WORD_LENGTH_S24_LE
22063. DA7219_DAI_WORD_LENGTH_S32_LE
22064. DA7219_DAI_WORD_LENGTH_SHIFT
22065. DA7219_DIG_CTRL
22066. DA7219_DIG_ROUTING_DAC
22067. DA7219_DIG_ROUTING_DAI
22068. DA7219_DMIX_ST_CTRLS
22069. DA7219_DMIX_ST_ROUTES
22070. DA7219_DMIX_ST_SRC_OUTFILT1L
22071. DA7219_DMIX_ST_SRC_OUTFILT1L_SHIFT
22072. DA7219_DMIX_ST_SRC_OUTFILT1R
22073. DA7219_DMIX_ST_SRC_OUTFILT1R_SHIFT
22074. DA7219_DMIX_ST_SRC_SIDETONE_SHIFT
22075. DA7219_DROUTING_ST_OUTFILT_1L
22076. DA7219_DROUTING_ST_OUTFILT_1R
22077. DA7219_DTMF_EN_MASK
22078. DA7219_DTMF_EN_SHIFT
22079. DA7219_DTMF_REG_MASK
22080. DA7219_DTMF_REG_MAX
22081. DA7219_DTMF_REG_SHIFT
22082. DA7219_D_B_BUTTON_THRESH_MASK
22083. DA7219_D_B_BUTTON_THRESH_SHIFT
22084. DA7219_E_BUTTON_A_PRESSED_MASK
22085. DA7219_E_BUTTON_A_PRESSED_SHIFT
22086. DA7219_E_BUTTON_A_RELEASED_MASK
22087. DA7219_E_BUTTON_A_RELEASED_SHIFT
22088. DA7219_E_BUTTON_B_PRESSED_MASK
22089. DA7219_E_BUTTON_B_PRESSED_SHIFT
22090. DA7219_E_BUTTON_B_RELEASED_MASK
22091. DA7219_E_BUTTON_B_RELEASED_SHIFT
22092. DA7219_E_BUTTON_C_PRESSED_MASK
22093. DA7219_E_BUTTON_C_PRESSED_SHIFT
22094. DA7219_E_BUTTON_C_RELEASED_MASK
22095. DA7219_E_BUTTON_C_RELEASED_SHIFT
22096. DA7219_E_BUTTON_D_PRESSED_MASK
22097. DA7219_E_BUTTON_D_PRESSED_SHIFT
22098. DA7219_E_BUTTON_D_RELEASED_MASK
22099. DA7219_E_BUTTON_D_RELEASED_SHIFT
22100. DA7219_E_JACK_DETECT_COMPLETE_MASK
22101. DA7219_E_JACK_DETECT_COMPLETE_SHIFT
22102. DA7219_E_JACK_INSERTED_MASK
22103. DA7219_E_JACK_INSERTED_SHIFT
22104. DA7219_E_JACK_REMOVED_MASK
22105. DA7219_E_JACK_REMOVED_SHIFT
22106. DA7219_FORMATS
22107. DA7219_FREQ1_L_MASK
22108. DA7219_FREQ1_L_SHIFT
22109. DA7219_FREQ1_U_MASK
22110. DA7219_FREQ1_U_SHIFT
22111. DA7219_FREQ2_L_MASK
22112. DA7219_FREQ2_L_SHIFT
22113. DA7219_FREQ2_U_MASK
22114. DA7219_FREQ2_U_SHIFT
22115. DA7219_FREQ_MAX
22116. DA7219_GAIN_RAMP_CTRL
22117. DA7219_GAIN_RAMP_RATE_MASK
22118. DA7219_GAIN_RAMP_RATE_MAX
22119. DA7219_GAIN_RAMP_RATE_NOMINAL
22120. DA7219_GAIN_RAMP_RATE_SHIFT
22121. DA7219_GAIN_RAMP_RATE_X8
22122. DA7219_HPF_AUDIO_EN
22123. DA7219_HPF_DISABLED
22124. DA7219_HPF_MODE_MASK
22125. DA7219_HPF_MODE_MAX
22126. DA7219_HPF_MODE_SHIFT
22127. DA7219_HPF_VOICE_EN
22128. DA7219_HPTEST_COMP_MASK
22129. DA7219_HPTEST_COMP_SHIFT
22130. DA7219_HPTEST_EN_MASK
22131. DA7219_HPTEST_EN_SHIFT
22132. DA7219_HPTEST_RES_SEL_1KOHMS
22133. DA7219_HPTEST_RES_SEL_MASK
22134. DA7219_HPTEST_RES_SEL_SHIFT
22135. DA7219_HP_AMP_GAIN_0DB
22136. DA7219_HP_AMP_GAIN_MAX
22137. DA7219_HP_L_AMP_EN_MASK
22138. DA7219_HP_L_AMP_EN_SHIFT
22139. DA7219_HP_L_AMP_GAIN_MASK
22140. DA7219_HP_L_AMP_GAIN_SHIFT
22141. DA7219_HP_L_AMP_GAIN_STATUS_MASK
22142. DA7219_HP_L_AMP_GAIN_STATUS_SHIFT
22143. DA7219_HP_L_AMP_MIN_GAIN_EN_MASK
22144. DA7219_HP_L_AMP_MIN_GAIN_EN_SHIFT
22145. DA7219_HP_L_AMP_MUTE_EN_MASK
22146. DA7219_HP_L_AMP_MUTE_EN_SHIFT
22147. DA7219_HP_L_AMP_OE_MASK
22148. DA7219_HP_L_AMP_OE_SHIFT
22149. DA7219_HP_L_AMP_RAMP_EN_MASK
22150. DA7219_HP_L_AMP_RAMP_EN_SHIFT
22151. DA7219_HP_L_AMP_ZC_EN_MASK
22152. DA7219_HP_L_AMP_ZC_EN_SHIFT
22153. DA7219_HP_L_CTRL
22154. DA7219_HP_L_GAIN
22155. DA7219_HP_L_GAIN_STATUS
22156. DA7219_HP_R_AMP_EN_MASK
22157. DA7219_HP_R_AMP_EN_SHIFT
22158. DA7219_HP_R_AMP_GAIN_MASK
22159. DA7219_HP_R_AMP_GAIN_SHIFT
22160. DA7219_HP_R_AMP_GAIN_STATUS_MASK
22161. DA7219_HP_R_AMP_GAIN_STATUS_SHIFT
22162. DA7219_HP_R_AMP_MIN_GAIN_EN_MASK
22163. DA7219_HP_R_AMP_MIN_GAIN_EN_SHIFT
22164. DA7219_HP_R_AMP_MUTE_EN_MASK
22165. DA7219_HP_R_AMP_MUTE_EN_SHIFT
22166. DA7219_HP_R_AMP_OE_MASK
22167. DA7219_HP_R_AMP_OE_SHIFT
22168. DA7219_HP_R_AMP_RAMP_EN_MASK
22169. DA7219_HP_R_AMP_RAMP_EN_SHIFT
22170. DA7219_HP_R_AMP_ZC_EN_MASK
22171. DA7219_HP_R_AMP_ZC_EN_SHIFT
22172. DA7219_HP_R_CTRL
22173. DA7219_HP_R_GAIN
22174. DA7219_HP_R_GAIN_STATUS
22175. DA7219_I2C_TIMEOUT_EN_MASK
22176. DA7219_I2C_TIMEOUT_EN_SHIFT
22177. DA7219_INVERT
22178. DA7219_IO_CTRL
22179. DA7219_IO_VOLTAGE_LEVEL_1_2V_2_8V
22180. DA7219_IO_VOLTAGE_LEVEL_2_5V_3_6V
22181. DA7219_IO_VOLTAGE_LEVEL_MASK
22182. DA7219_IO_VOLTAGE_LEVEL_SHIFT
22183. DA7219_JACKDET_DEBOUNCE_MASK
22184. DA7219_JACKDET_DEBOUNCE_SHIFT
22185. DA7219_JACKDET_REM_DEB_MASK
22186. DA7219_JACKDET_REM_DEB_SHIFT
22187. DA7219_JACK_DETECT_RATE_MASK
22188. DA7219_JACK_DETECT_RATE_SHIFT
22189. DA7219_JACK_INSERTION_STS_MASK
22190. DA7219_JACK_INSERTION_STS_SHIFT
22191. DA7219_JACK_PIN_ORDER_STS_MASK
22192. DA7219_JACK_PIN_ORDER_STS_SHIFT
22193. DA7219_JACK_TYPE_DET_EN_MASK
22194. DA7219_JACK_TYPE_DET_EN_SHIFT
22195. DA7219_JACK_TYPE_FORCE_MASK
22196. DA7219_JACK_TYPE_FORCE_SHIFT
22197. DA7219_JACK_TYPE_STS_MASK
22198. DA7219_JACK_TYPE_STS_SHIFT
22199. DA7219_MICBIAS1_EN_MASK
22200. DA7219_MICBIAS1_EN_SHIFT
22201. DA7219_MICBIAS1_LEVEL_MASK
22202. DA7219_MICBIAS1_LEVEL_SHIFT
22203. DA7219_MICBIAS_1_6V
22204. DA7219_MICBIAS_1_8V
22205. DA7219_MICBIAS_2_0V
22206. DA7219_MICBIAS_2_2V
22207. DA7219_MICBIAS_2_4V
22208. DA7219_MICBIAS_2_6V
22209. DA7219_MICBIAS_CTRL
22210. DA7219_MICBIAS_UP_STS_MASK
22211. DA7219_MICBIAS_UP_STS_SHIFT
22212. DA7219_MIC_1_AMP_EN_MASK
22213. DA7219_MIC_1_AMP_EN_SHIFT
22214. DA7219_MIC_1_AMP_GAIN_MASK
22215. DA7219_MIC_1_AMP_GAIN_MAX
22216. DA7219_MIC_1_AMP_GAIN_SHIFT
22217. DA7219_MIC_1_AMP_GAIN_STATUS_MASK
22218. DA7219_MIC_1_AMP_GAIN_STATUS_SHIFT
22219. DA7219_MIC_1_AMP_IN_SEL_MASK
22220. DA7219_MIC_1_AMP_IN_SEL_SHIFT
22221. DA7219_MIC_1_AMP_MUTE_EN_MASK
22222. DA7219_MIC_1_AMP_MUTE_EN_SHIFT
22223. DA7219_MIC_1_AMP_RAMP_EN_MASK
22224. DA7219_MIC_1_AMP_RAMP_EN_SHIFT
22225. DA7219_MIC_1_CTRL
22226. DA7219_MIC_1_GAIN
22227. DA7219_MIC_1_GAIN_STATUS
22228. DA7219_MIC_1_SELECT
22229. DA7219_MIC_AMP_IN_SEL_DIFF
22230. DA7219_MIC_AMP_IN_SEL_SE_N
22231. DA7219_MIC_AMP_IN_SEL_SE_P
22232. DA7219_MIC_DET_THRESH_MASK
22233. DA7219_MIC_DET_THRESH_SHIFT
22234. DA7219_MIC_PGA_BASE_DELAY
22235. DA7219_MIC_PGA_OFFSET_DELAY
22236. DA7219_MIN_GAIN_DELAY
22237. DA7219_MIXIN_L_AMP_EN_MASK
22238. DA7219_MIXIN_L_AMP_EN_SHIFT
22239. DA7219_MIXIN_L_AMP_GAIN_MASK
22240. DA7219_MIXIN_L_AMP_GAIN_MAX
22241. DA7219_MIXIN_L_AMP_GAIN_SHIFT
22242. DA7219_MIXIN_L_AMP_GAIN_STATUS_MASK
22243. DA7219_MIXIN_L_AMP_GAIN_STATUS_SHIFT
22244. DA7219_MIXIN_L_AMP_MUTE_EN_MASK
22245. DA7219_MIXIN_L_AMP_MUTE_EN_SHIFT
22246. DA7219_MIXIN_L_AMP_RAMP_EN_MASK
22247. DA7219_MIXIN_L_AMP_RAMP_EN_SHIFT
22248. DA7219_MIXIN_L_AMP_ZC_EN_MASK
22249. DA7219_MIXIN_L_AMP_ZC_EN_SHIFT
22250. DA7219_MIXIN_L_CTRL
22251. DA7219_MIXIN_L_GAIN
22252. DA7219_MIXIN_L_GAIN_STATUS
22253. DA7219_MIXIN_L_MIX_EN_MASK
22254. DA7219_MIXIN_L_MIX_EN_SHIFT
22255. DA7219_MIXIN_L_MIX_SELECT_MASK
22256. DA7219_MIXIN_L_MIX_SELECT_SHIFT
22257. DA7219_MIXIN_L_SELECT
22258. DA7219_MIXOUT_L_AMP_EN_MASK
22259. DA7219_MIXOUT_L_AMP_EN_SHIFT
22260. DA7219_MIXOUT_L_CTRL
22261. DA7219_MIXOUT_L_MIX_SELECT_MASK
22262. DA7219_MIXOUT_L_MIX_SELECT_SHIFT
22263. DA7219_MIXOUT_L_SELECT
22264. DA7219_MIXOUT_R_AMP_EN_MASK
22265. DA7219_MIXOUT_R_AMP_EN_SHIFT
22266. DA7219_MIXOUT_R_CTRL
22267. DA7219_MIXOUT_R_MIX_SELECT_MASK
22268. DA7219_MIXOUT_R_MIX_SELECT_SHIFT
22269. DA7219_MIXOUT_R_SELECT
22270. DA7219_MODE_SUBMIT_MASK
22271. DA7219_MODE_SUBMIT_SHIFT
22272. DA7219_M_BUTTON_A_PRESSED_MASK
22273. DA7219_M_BUTTON_A_PRESSED_SHIFT
22274. DA7219_M_BUTTON_A_RELEASED_MASK
22275. DA7219_M_BUTTON_A_RELEASED_SHIFT
22276. DA7219_M_BUTTON_B_PRESSED_MASK
22277. DA7219_M_BUTTON_B_PRESSED_SHIFT
22278. DA7219_M_BUTTON_B_RELEASED_MASK
22279. DA7219_M_BUTTON_B_RELEASED_SHIFT
22280. DA7219_M_BUTTON_C_PRESSED_MASK
22281. DA7219_M_BUTTON_C_PRESSED_SHIFT
22282. DA7219_M_BUTTON_C_RELEASED_MASK
22283. DA7219_M_BUTTON_C_RELEASED_SHIFT
22284. DA7219_M_BUTTON_D_PRESSED_MASK
22285. DA7219_M_BUTTON_D_PRESSED_SHIFT
22286. DA7219_M_BUTTON_D_RELEASED_MASK
22287. DA7219_M_BUTTON_D_RELEASED_SHIFT
22288. DA7219_M_JACK_DETECT_COMPLETE_MASK
22289. DA7219_M_JACK_DETECT_COMPLETE_SHIFT
22290. DA7219_M_JACK_INSERTED_MASK
22291. DA7219_M_JACK_INSERTED_SHIFT
22292. DA7219_M_JACK_REMOVED_MASK
22293. DA7219_M_JACK_REMOVED_SHIFT
22294. DA7219_NO_INVERT
22295. DA7219_NUM_SUPPLIES
22296. DA7219_OUTFILT_ST_1L_SRC_MASK
22297. DA7219_OUTFILT_ST_1L_SRC_SHIFT
22298. DA7219_OUTFILT_ST_1R_SRC_MASK
22299. DA7219_OUTFILT_ST_1R_SRC_SHIFT
22300. DA7219_OUT_DAC_MUX_ROUTES
22301. DA7219_OUT_DAI_MUX_ROUTES
22302. DA7219_OUT_SRC_MAX
22303. DA7219_PC_COUNT
22304. DA7219_PC_FREERUN_MASK
22305. DA7219_PC_FREERUN_SHIFT
22306. DA7219_PC_RESYNC_AUTO_MASK
22307. DA7219_PC_RESYNC_AUTO_SHIFT
22308. DA7219_PIN_ORDER_DET_EN_MASK
22309. DA7219_PIN_ORDER_DET_EN_SHIFT
22310. DA7219_PIN_ORDER_FORCE_MASK
22311. DA7219_PIN_ORDER_FORCE_SHIFT
22312. DA7219_PLL_CTRL
22313. DA7219_PLL_FBDIV_FRAC_BOT_MASK
22314. DA7219_PLL_FBDIV_FRAC_BOT_SHIFT
22315. DA7219_PLL_FBDIV_FRAC_TOP_MASK
22316. DA7219_PLL_FBDIV_FRAC_TOP_SHIFT
22317. DA7219_PLL_FBDIV_INTEGER_MASK
22318. DA7219_PLL_FBDIV_INTEGER_SHIFT
22319. DA7219_PLL_FRAC_BOT
22320. DA7219_PLL_FRAC_TOP
22321. DA7219_PLL_FREQ_OUT_90316
22322. DA7219_PLL_FREQ_OUT_98304
22323. DA7219_PLL_INDIV_18_TO_36_MHZ
22324. DA7219_PLL_INDIV_18_TO_36_MHZ_VAL
22325. DA7219_PLL_INDIV_2_TO_4_5_MHZ
22326. DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL
22327. DA7219_PLL_INDIV_36_TO_54_MHZ
22328. DA7219_PLL_INDIV_36_TO_54_MHZ_VAL
22329. DA7219_PLL_INDIV_4_5_TO_9_MHZ
22330. DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL
22331. DA7219_PLL_INDIV_9_TO_18_MHZ
22332. DA7219_PLL_INDIV_9_TO_18_MHZ_VAL
22333. DA7219_PLL_INDIV_MASK
22334. DA7219_PLL_INDIV_SHIFT
22335. DA7219_PLL_INTEGER
22336. DA7219_PLL_MCLK_SQR_EN_MASK
22337. DA7219_PLL_MCLK_SQR_EN_SHIFT
22338. DA7219_PLL_MODE_BYPASS
22339. DA7219_PLL_MODE_MASK
22340. DA7219_PLL_MODE_NORMAL
22341. DA7219_PLL_MODE_SHIFT
22342. DA7219_PLL_MODE_SRM
22343. DA7219_PLL_SRM_LOCK
22344. DA7219_PLL_SRM_STATE_MASK
22345. DA7219_PLL_SRM_STATE_SHIFT
22346. DA7219_PLL_SRM_STATUS_MASK
22347. DA7219_PLL_SRM_STATUS_SHIFT
22348. DA7219_PLL_SRM_STS
22349. DA7219_PLL_SRM_STS_MCLK
22350. DA7219_PLL_SRM_STS_SRM_LOCK
22351. DA7219_RATES
22352. DA7219_REFERENCES
22353. DA7219_SC1_BUSY_MASK
22354. DA7219_SC1_BUSY_SHIFT
22355. DA7219_SC2_BUSY_MASK
22356. DA7219_SC2_BUSY_SHIFT
22357. DA7219_SETTLING_DELAY
22358. DA7219_SIDETONE_CTRL
22359. DA7219_SIDETONE_EN_MASK
22360. DA7219_SIDETONE_EN_SHIFT
22361. DA7219_SIDETONE_GAIN
22362. DA7219_SIDETONE_GAIN_MASK
22363. DA7219_SIDETONE_GAIN_MAX
22364. DA7219_SIDETONE_GAIN_SHIFT
22365. DA7219_SIDETONE_MUTE_EN_MASK
22366. DA7219_SIDETONE_MUTE_EN_SHIFT
22367. DA7219_SR
22368. DA7219_SRM_CHECK_RETRIES
22369. DA7219_SR_11025
22370. DA7219_SR_12000
22371. DA7219_SR_16000
22372. DA7219_SR_22050
22373. DA7219_SR_24000
22374. DA7219_SR_24_48
22375. DA7219_SR_24_48_MASK
22376. DA7219_SR_24_48_SHIFT
22377. DA7219_SR_32000
22378. DA7219_SR_44100
22379. DA7219_SR_48000
22380. DA7219_SR_8000
22381. DA7219_SR_88200
22382. DA7219_SR_96000
22383. DA7219_SR_MASK
22384. DA7219_SR_SHIFT
22385. DA7219_START_STOPN_MASK
22386. DA7219_START_STOPN_SHIFT
22387. DA7219_SUPPLY_VDD
22388. DA7219_SUPPLY_VDDIO
22389. DA7219_SUPPLY_VDDMIC
22390. DA7219_SWG_SEL_MASK
22391. DA7219_SWG_SEL_MAX
22392. DA7219_SWG_SEL_SHIFT
22393. DA7219_SWG_SEL_SRAMP
22394. DA7219_SWITCH_EN_MAX
22395. DA7219_SYSCLK_MCLK
22396. DA7219_SYSCLK_PLL
22397. DA7219_SYSCLK_PLL_SRM
22398. DA7219_SYSTEM_ACTIVE
22399. DA7219_SYSTEM_ACTIVE_MASK
22400. DA7219_SYSTEM_ACTIVE_SHIFT
22401. DA7219_SYSTEM_MODES_INPUT
22402. DA7219_SYSTEM_MODES_OUTPUT
22403. DA7219_SYSTEM_STATUS
22404. DA7219_SYS_STAT_CHECK_DELAY
22405. DA7219_SYS_STAT_CHECK_RETRIES
22406. DA7219_TONE_GEN_CFG1
22407. DA7219_TONE_GEN_CFG2
22408. DA7219_TONE_GEN_CYCLES
22409. DA7219_TONE_GEN_FREQ1_L
22410. DA7219_TONE_GEN_FREQ1_U
22411. DA7219_TONE_GEN_FREQ2_L
22412. DA7219_TONE_GEN_FREQ2_U
22413. DA7219_TONE_GEN_GAIN_MASK
22414. DA7219_TONE_GEN_GAIN_MAX
22415. DA7219_TONE_GEN_GAIN_MINUS_15DB
22416. DA7219_TONE_GEN_GAIN_MINUS_9DB
22417. DA7219_TONE_GEN_GAIN_SHIFT
22418. DA7219_TONE_GEN_OFF_PER
22419. DA7219_TONE_GEN_ON_PER
22420. DA7219_VMID_FAST_CHARGE_MASK
22421. DA7219_VMID_FAST_CHARGE_SHIFT
22422. DA7219_VOICE_HPF_CORNER_MAX
22423. DA723X_CP_DIS
22424. DA732X_16_SAMPLES
22425. DA732X_1BYTE
22426. DA732X_1BYTE_SHIFT
22427. DA732X_2BYTES
22428. DA732X_2BYTES_SHIFT
22429. DA732X_3BYTES
22430. DA732X_3BYTES_SHIFT
22431. DA732X_4BYTES
22432. DA732X_4BYTES_SHIFT
22433. DA732X_ADC1L_MUX_SEL_SHIFT
22434. DA732X_ADC1R_MUX_SEL_SHIFT
22435. DA732X_ADC1_TO_AIFA
22436. DA732X_ADC2L_MUX_SEL_SHIFT
22437. DA732X_ADC2R_MUX_SEL_SHIFT
22438. DA732X_ADC2_TO_AIFB
22439. DA732X_ADCA_BB_CLK_EN
22440. DA732X_ADCC_BB_CLK_EN
22441. DA732X_ADCL_EN
22442. DA732X_ADCL_EN_SHIFT
22443. DA732X_ADCL_MUX_MAX
22444. DA732X_ADCL_VOL_SHIFT
22445. DA732X_ADCR_EN
22446. DA732X_ADCR_EN_SHIFT
22447. DA732X_ADCR_MUX_MAX
22448. DA732X_ADCR_VOL_SHIFT
22449. DA732X_ADC_OFF
22450. DA732X_ADC_ON
22451. DA732X_ADC_PD_MASK
22452. DA732X_ADC_RST_MASK
22453. DA732X_ADC_SET_ACT
22454. DA732X_ADC_SET_RST
22455. DA732X_ADC_VOL_DB_INC
22456. DA732X_ADC_VOL_DB_MIN
22457. DA732X_ADC_VOL_VAL_MASK
22458. DA732X_ADC_VOL_VAL_MAX
22459. DA732X_AIF1_CLK_MASK
22460. DA732X_AIFA_TO_DAC1L
22461. DA732X_AIFA_TO_DAC1R
22462. DA732X_AIFB_TO_DAC2L
22463. DA732X_AIFB_TO_DAC2R
22464. DA732X_AIFB_TO_DAC3
22465. DA732X_AIFM_FRAME_64
22466. DA732X_AIFM_SRC_SEL_AIFA
22467. DA732X_AIF_BCLK_INV
22468. DA732X_AIF_CLK_FROM_SRC
22469. DA732X_AIF_DSP_MODE
22470. DA732X_AIF_EN
22471. DA732X_AIF_EN_SHIFT
22472. DA732X_AIF_I2S_MODE
22473. DA732X_AIF_LEFT_J_MODE
22474. DA732X_AIF_MODE_MASK
22475. DA732X_AIF_MODE_SHIFT
22476. DA732X_AIF_RIGHT_J_MODE
22477. DA732X_AIF_SLAVE
22478. DA732X_AIF_TDM_MONO_SHIFT
22479. DA732X_AIF_WCLK_INV
22480. DA732X_AIF_WORD_16
22481. DA732X_AIF_WORD_20
22482. DA732X_AIF_WORD_24
22483. DA732X_AIF_WORD_32
22484. DA732X_AIF_WORD_MASK
22485. DA732X_ALL_TO_DSP
22486. DA732X_AUXL_ZC_EN
22487. DA732X_AUXR_ZC_EN
22488. DA732X_AUX_EN_SHIFT
22489. DA732X_AUX_MUTE_SHIFT
22490. DA732X_AUX_VOL_DB_INC
22491. DA732X_AUX_VOL_DB_MIN
22492. DA732X_AUX_VOL_MASK
22493. DA732X_AUX_VOL_SHIFT
22494. DA732X_AUX_VOL_VAL_MAX
22495. DA732X_BIAS1_HP_DAC_BIAS_100PC
22496. DA732X_BIAS1_HP_DAC_BIAS_150PC
22497. DA732X_BIAS1_HP_DAC_BIAS_50PC
22498. DA732X_BIAS1_HP_DAC_BIAS_75PC
22499. DA732X_BIAS1_HP_DAC_BIAS_MASK
22500. DA732X_BIAS1_HP_OUT_BIAS_100PC
22501. DA732X_BIAS1_HP_OUT_BIAS_125PC
22502. DA732X_BIAS1_HP_OUT_BIAS_150PC
22503. DA732X_BIAS1_HP_OUT_BIAS_175PC
22504. DA732X_BIAS1_HP_OUT_BIAS_200PC
22505. DA732X_BIAS1_HP_OUT_BIAS_250PC
22506. DA732X_BIAS1_HP_OUT_BIAS_300PC
22507. DA732X_BIAS1_HP_OUT_BIAS_350PC
22508. DA732X_BIAS1_HP_OUT_BIAS_MASK
22509. DA732X_BIAS2_LINE2_DAC_BIAS_100PC
22510. DA732X_BIAS2_LINE2_DAC_BIAS_150PC
22511. DA732X_BIAS2_LINE2_DAC_BIAS_50PC
22512. DA732X_BIAS2_LINE2_DAC_BIAS_75PC
22513. DA732X_BIAS2_LINE2_DAC_BIAS_MASK
22514. DA732X_BIAS2_LINE2_OUT_BIAS_100PC
22515. DA732X_BIAS2_LINE2_OUT_BIAS_125PC
22516. DA732X_BIAS2_LINE2_OUT_BIAS_150PC
22517. DA732X_BIAS2_LINE2_OUT_BIAS_175PC
22518. DA732X_BIAS2_LINE2_OUT_BIAS_200PC
22519. DA732X_BIAS2_LINE2_OUT_BIAS_250PC
22520. DA732X_BIAS2_LINE2_OUT_BIAS_300PC
22521. DA732X_BIAS2_LINE2_OUT_BIAS_350PC
22522. DA732X_BIAS2_LINE2_OUT_BIAS_MASK
22523. DA732X_BIAS3_LINE3_DAC_BIAS_100PC
22524. DA732X_BIAS3_LINE3_DAC_BIAS_150PC
22525. DA732X_BIAS3_LINE3_DAC_BIAS_50PC
22526. DA732X_BIAS3_LINE3_DAC_BIAS_75PC
22527. DA732X_BIAS3_LINE3_DAC_BIAS_MASK
22528. DA732X_BIAS3_LINE3_OUT_BIAS_100PC
22529. DA732X_BIAS3_LINE3_OUT_BIAS_125PC
22530. DA732X_BIAS3_LINE3_OUT_BIAS_150PC
22531. DA732X_BIAS3_LINE3_OUT_BIAS_175PC
22532. DA732X_BIAS3_LINE3_OUT_BIAS_200PC
22533. DA732X_BIAS3_LINE3_OUT_BIAS_250PC
22534. DA732X_BIAS3_LINE3_OUT_BIAS_300PC
22535. DA732X_BIAS3_LINE3_OUT_BIAS_350PC
22536. DA732X_BIAS3_LINE3_OUT_BIAS_MASK
22537. DA732X_BIAS4_LINE4_DAC_BIAS_100PC
22538. DA732X_BIAS4_LINE4_DAC_BIAS_150PC
22539. DA732X_BIAS4_LINE4_DAC_BIAS_50PC
22540. DA732X_BIAS4_LINE4_DAC_BIAS_75PC
22541. DA732X_BIAS4_LINE4_DAC_BIAS_MASK
22542. DA732X_BIAS4_LINE4_OUT_BIAS_100PC
22543. DA732X_BIAS4_LINE4_OUT_BIAS_125PC
22544. DA732X_BIAS4_LINE4_OUT_BIAS_150PC
22545. DA732X_BIAS4_LINE4_OUT_BIAS_175PC
22546. DA732X_BIAS4_LINE4_OUT_BIAS_200PC
22547. DA732X_BIAS4_LINE4_OUT_BIAS_250PC
22548. DA732X_BIAS4_LINE4_OUT_BIAS_300PC
22549. DA732X_BIAS4_LINE4_OUT_BIAS_350PC
22550. DA732X_BIAS4_LINE4_OUT_BIAS_MASK
22551. DA732X_BIAS_BOOST_100PC
22552. DA732X_BIAS_BOOST_133PC
22553. DA732X_BIAS_BOOST_50PC
22554. DA732X_BIAS_BOOST_88PC
22555. DA732X_BIAS_BOOST_MASK
22556. DA732X_BIAS_DIS
22557. DA732X_BIAS_EN
22558. DA732X_BYPASS_DSP
22559. DA732X_CLEAR_REG
22560. DA732X_CLK_GENERATION_AIF_A
22561. DA732X_CP_0KHZ
22562. DA732X_CP_125KHZ
22563. DA732X_CP_1MHZ
22564. DA732X_CP_250KHZ
22565. DA732X_CP_500KHZ
22566. DA732X_CP_63KHZ
22567. DA732X_CP_BOOST
22568. DA732X_CP_CLK_DIS
22569. DA732X_CP_CLK_EN
22570. DA732X_CP_CTRL_CPVDD1
22571. DA732X_CP_CTRL_CPVDD2
22572. DA732X_CP_CTRL_CPVDD3
22573. DA732X_CP_CTRL_CPVDD4
22574. DA732X_CP_CTRL_CPVDD5
22575. DA732X_CP_CTRL_CPVDD6
22576. DA732X_CP_CTRL_STANDBY
22577. DA732X_CP_EN
22578. DA732X_CP_MANAGE_MAGNITUDE
22579. DA732X_CP_MODE_MASK
22580. DA732X_DACA_BB_CLK_EN
22581. DA732X_DACA_BB_CLK_SHIFT
22582. DA732X_DACC_BB_CLK_EN
22583. DA732X_DACC_BB_CLK_SHIFT
22584. DA732X_DACE_BB_CLK_EN
22585. DA732X_DACE_BB_CLK_SHIFT
22586. DA732X_DACL_EN
22587. DA732X_DACL_EN_SHIFT
22588. DA732X_DACL_MUTE
22589. DA732X_DACL_MUTE_SHIFT
22590. DA732X_DACL_SDM
22591. DA732X_DACR_EN
22592. DA732X_DACR_EN_SHIFT
22593. DA732X_DACR_MUTE
22594. DA732X_DACR_MUTE_SHIFT
22595. DA732X_DACR_SDM
22596. DA732X_DACS_DIS
22597. DA732X_DAC_EN_MAX
22598. DA732X_DAC_OFFSET_STEP
22599. DA732X_DAC_VOL_DB_INC
22600. DA732X_DAC_VOL_DB_MIN
22601. DA732X_DAC_VOL_SHIFT
22602. DA732X_DAC_VOL_VAL_MASK
22603. DA732X_DAC_VOL_VAL_MAX
22604. DA732X_DAI_ID1
22605. DA732X_DAI_ID2
22606. DA732X_DIGITAL_EN
22607. DA732X_DIGITAL_RESET
22608. DA732X_DISABLE_ALL_CLKS
22609. DA732X_DISABLE_CP
22610. DA732X_DSP12_CLK_EN
22611. DA732X_DSP_CLK_EN
22612. DA732X_DSP_CORE_EN
22613. DA732X_DSP_CORE_RESET
22614. DA732X_DSP_DMA_BUSY
22615. DA732X_DSP_DMA_FREE
22616. DA732X_DSP_DMA_READ
22617. DA732X_DSP_DMA_WRITE
22618. DA732X_DSP_FREQ_12MHZ
22619. DA732X_DSP_FREQ_24MHZ
22620. DA732X_DSP_FREQ_36MHZ
22621. DA732X_DSP_FREQ_48MHZ
22622. DA732X_DSP_FREQ_60MHZ
22623. DA732X_DSP_FREQ_72MHZ
22624. DA732X_DSP_FREQ_84MHZ
22625. DA732X_DSP_FREQ_96MHZ
22626. DA732X_DSP_FREQ_MASK
22627. DA732X_DSP_RW_MASK
22628. DA732X_DSP_TO_AIFA
22629. DA732X_DSP_TO_AIFB
22630. DA732X_DSP_TO_DAC1L
22631. DA732X_DSP_TO_DAC1R
22632. DA732X_DSP_TO_DAC2L
22633. DA732X_DSP_TO_DAC2R
22634. DA732X_DSP_TO_DAC3
22635. DA732X_ENABLE_CP
22636. DA732X_EQ_BAND1_SHIFT
22637. DA732X_EQ_BAND2_SHIFT
22638. DA732X_EQ_BAND3_SHIFT
22639. DA732X_EQ_BAND4_SHIFT
22640. DA732X_EQ_BAND5_SHIFT
22641. DA732X_EQ_BAND_VOL_DB_INC
22642. DA732X_EQ_BAND_VOL_DB_MIN
22643. DA732X_EQ_DIS
22644. DA732X_EQ_EN
22645. DA732X_EQ_EN_MAX
22646. DA732X_EQ_EN_SHIFT
22647. DA732X_EQ_OVERALL_SHIFT
22648. DA732X_EQ_OVERALL_VOL_DB_INC
22649. DA732X_EQ_OVERALL_VOL_DB_MIN
22650. DA732X_EQ_OVERALL_VOL_VAL_MASK
22651. DA732X_EQ_OVERALL_VOL_VAL_MAX
22652. DA732X_EQ_VOL_VAL_MASK
22653. DA732X_EQ_VOL_VAL_MAX
22654. DA732X_FORMATS
22655. DA732X_GAIN_RAMPED
22656. DA732X_HPF_DIS
22657. DA732X_HPF_DISABLED
22658. DA732X_HPF_MASK
22659. DA732X_HPF_MODE_MAX
22660. DA732X_HPF_MODE_SHIFT
22661. DA732X_HPF_MUSIC
22662. DA732X_HPF_MUSIC_EN
22663. DA732X_HPF_MUSIC_MAX
22664. DA732X_HPF_MUSIC_SHIFT
22665. DA732X_HPF_VOICE
22666. DA732X_HPF_VOICE_EN
22667. DA732X_HPF_VOICE_MAX
22668. DA732X_HPF_VOICE_SHIFT
22669. DA732X_HPL_AMP
22670. DA732X_HPL_DAC
22671. DA732X_HPL_ZC_DIS
22672. DA732X_HPL_ZC_EN
22673. DA732X_HPL_ZC_EN_SHIFT
22674. DA732X_HPR_AMP
22675. DA732X_HPR_DAC
22676. DA732X_HPR_ZC_DIS
22677. DA732X_HPR_ZC_EN
22678. DA732X_HPR_ZC_EN_SHIFT
22679. DA732X_HP_AMPS
22680. DA732X_HP_CP_DIS
22681. DA732X_HP_CP_EN
22682. DA732X_HP_CP_PULSESKIP
22683. DA732X_HP_CP_REG
22684. DA732X_HP_DACS
22685. DA732X_HP_DAC_COMPO_SHIFT
22686. DA732X_HP_DAC_OFFSET_DAC_SIGN
22687. DA732X_HP_DAC_OFFSET_TRIM_MASK
22688. DA732X_HP_DAC_OFFSET_TRIM_VAL
22689. DA732X_HP_DAC_OFF_CALIBRATION
22690. DA732X_HP_DAC_OFF_CNTL_COMPO
22691. DA732X_HP_DAC_OFF_CNTL_CONT_MASK
22692. DA732X_HP_DAC_OFF_MASK
22693. DA732X_HP_DAC_OFF_SCALE_STEPS
22694. DA732X_HP_DET_AZ
22695. DA732X_HP_DET_EN
22696. DA732X_HP_DET_IS_0_5UA
22697. DA732X_HP_DET_IS_1UA
22698. DA732X_HP_DET_IS_2UA
22699. DA732X_HP_DET_IS_4UA
22700. DA732X_HP_DET_IS_MASK
22701. DA732X_HP_DET_RS_100KOHM
22702. DA732X_HP_DET_RS_10KOHM
22703. DA732X_HP_DET_RS_1KOHM
22704. DA732X_HP_DET_RS_INFINITE
22705. DA732X_HP_DET_RS_MASK
22706. DA732X_HP_DET_SEL1
22707. DA732X_HP_DIS
22708. DA732X_HP_DRIVER_EN
22709. DA732X_HP_GATE_LOW
22710. DA732X_HP_HIZ_SHIFT
22711. DA732X_HP_LOOP_GAIN_CTRL
22712. DA732X_HP_MUTE_SHIFT
22713. DA732X_HP_OUT_COMP
22714. DA732X_HP_OUT_COMPO
22715. DA732X_HP_OUT_COMPO_SHIFT
22716. DA732X_HP_OUT_DAC_EN
22717. DA732X_HP_OUT_DAC_EN_SHIFT
22718. DA732X_HP_OUT_EN
22719. DA732X_HP_OUT_EN_SHIFT
22720. DA732X_HP_OUT_GNDSEL
22721. DA732X_HP_OUT_HIZ_DIS
22722. DA732X_HP_OUT_HIZ_EN
22723. DA732X_HP_OUT_MUTE
22724. DA732X_HP_OUT_OFFSET_MASK
22725. DA732X_HP_OUT_RESERVED
22726. DA732X_HP_OUT_SIGN
22727. DA732X_HP_OUT_TRIM_VAL
22728. DA732X_HP_VOL_DB_INC
22729. DA732X_HP_VOL_DB_MIN
22730. DA732X_HP_VOL_SHIFT
22731. DA732X_HP_VOL_VAL_MASK
22732. DA732X_HP_VOL_VAL_MAX
22733. DA732X_ID_MAJOR_MASK
22734. DA732X_ID_MINOR_MASK
22735. DA732X_INP_ADC1L_MUX_SEL_AUX1L
22736. DA732X_INP_ADC1L_MUX_SEL_MIC1
22737. DA732X_INP_ADC1R_MUX_SEL_AUX1R
22738. DA732X_INP_ADC1R_MUX_SEL_MASK
22739. DA732X_INP_ADC1R_MUX_SEL_MIC2
22740. DA732X_INP_ADC1R_MUX_SEL_MIC3
22741. DA732X_INP_ADC2L_MUX_SEL_AUX1L
22742. DA732X_INP_ADC2L_MUX_SEL_MICL
22743. DA732X_INP_ADC2R_MUX_SEL_AUX1R
22744. DA732X_INP_ADC2R_MUX_SEL_AUX2
22745. DA732X_INP_ADC2R_MUX_SEL_MASK
22746. DA732X_INP_ADC2R_MUX_SEL_MICR
22747. DA732X_INP_AUX1L_PINBIAS_EN
22748. DA732X_INP_AUX1R_PINBIAS_EN
22749. DA732X_INP_AUX2_PINBIAS_EN
22750. DA732X_INP_MICL_PINBIAS_EN
22751. DA732X_INP_MICR_PINBIAS_EN
22752. DA732X_INVERT
22753. DA732X_LIN2_VOL_DB_INC
22754. DA732X_LIN2_VOL_DB_MIN
22755. DA732X_LIN2_ZC_DIS
22756. DA732X_LIN2_ZC_EN
22757. DA732X_LIN3_VOL_DB_INC
22758. DA732X_LIN3_VOL_DB_MIN
22759. DA732X_LIN3_ZC_DIS
22760. DA732X_LIN3_ZC_EN
22761. DA732X_LIN4_VOL_DB_INC
22762. DA732X_LIN4_VOL_DB_MIN
22763. DA732X_LIN4_ZC_DIS
22764. DA732X_LIN4_ZC_EN
22765. DA732X_LIN_LP_VOL
22766. DA732X_LIN_OUT_EN_SHIFT
22767. DA732X_LOUT_DAC_EN
22768. DA732X_LOUT_DAC_EN_SHIFT
22769. DA732X_LOUT_DAC_OFF
22770. DA732X_LOUT_DIS
22771. DA732X_LOUT_EN
22772. DA732X_LOUT_HIZ_N_DIS
22773. DA732X_LOUT_HIZ_N_EN
22774. DA732X_LOUT_MUTED
22775. DA732X_LOUT_MUTE_SHIFT
22776. DA732X_LOUT_UNMUTED
22777. DA732X_LOUT_VOL_MASK
22778. DA732X_LOUT_VOL_SHIFT
22779. DA732X_LOUT_VOL_VAL_MAX
22780. DA732X_LP_VOL
22781. DA732X_MAX_REG
22782. DA732X_MCLK_10MHZ
22783. DA732X_MCLK_20MHZ
22784. DA732X_MCLK_40MHZ
22785. DA732X_MCLK_54MHZ
22786. DA732X_MCLK_RET_0_10MHZ
22787. DA732X_MCLK_RET_10_20MHZ
22788. DA732X_MCLK_RET_20_40MHZ
22789. DA732X_MCLK_RET_40_54MHZ
22790. DA732X_MCLK_SQR_EN
22791. DA732X_MCLK_VAL_0_10MHZ
22792. DA732X_MCLK_VAL_10_20MHZ
22793. DA732X_MCLK_VAL_20_40MHZ
22794. DA732X_MCLK_VAL_40_54MHZ
22795. DA732X_MIC1_PRE_ZC_EN
22796. DA732X_MIC1_ZC_EN
22797. DA732X_MIC2_PRE_ZC_EN
22798. DA732X_MIC2_ZC_EN
22799. DA732X_MIC3_PRE_ZC_EN
22800. DA732X_MIC3_ZC_EN
22801. DA732X_MICBIAS_EN
22802. DA732X_MICBIAS_EN_SHIFT
22803. DA732X_MICBIAS_VOLTAGE_2V
22804. DA732X_MICBIAS_VOLTAGE_2V05
22805. DA732X_MICBIAS_VOLTAGE_2V1
22806. DA732X_MICBIAS_VOLTAGE_2V15
22807. DA732X_MICBIAS_VOLTAGE_2V2
22808. DA732X_MICBIAS_VOLTAGE_2V25
22809. DA732X_MICBIAS_VOLTAGE_2V3
22810. DA732X_MICBIAS_VOLTAGE_2V35
22811. DA732X_MICBIAS_VOLTAGE_2V4
22812. DA732X_MICBIAS_VOLTAGE_2V45
22813. DA732X_MICBIAS_VOLTAGE_2V5
22814. DA732X_MICBIAS_VOLTAGE_MASK
22815. DA732X_MICBIAS_VOLTAGE_MAX
22816. DA732X_MICBIAS_VOLTAGE_SHIFT
22817. DA732X_MICBOOST_MASK
22818. DA732X_MICBOOST_MAX
22819. DA732X_MICBOOST_MIN
22820. DA732X_MICBOOST_SHIFT
22821. DA732X_MICDET_INP_DEBOUNCE_PRD_16MS
22822. DA732X_MICDET_INP_DEBOUNCE_PRD_32MS
22823. DA732X_MICDET_INP_DEBOUNCE_PRD_64MS
22824. DA732X_MICDET_INP_DEBOUNCE_PRD_8MS
22825. DA732X_MICDET_INP_MICDET_EN
22826. DA732X_MICDET_INP_MICHOOK
22827. DA732X_MICDET_INP_MICRES
22828. DA732X_MIC_EN_SHIFT
22829. DA732X_MIC_MUTE_SHIFT
22830. DA732X_MIC_PRE_VOL_DB_INC
22831. DA732X_MIC_PRE_VOL_DB_MIN
22832. DA732X_MIC_VOL_DB_INC
22833. DA732X_MIC_VOL_DB_MIN
22834. DA732X_MIC_VOL_SHIFT
22835. DA732X_MIC_VOL_VAL_MASK
22836. DA732X_MIC_VOL_VAL_MAX
22837. DA732X_MIC_VOL_VAL_MIN
22838. DA732X_NO_CLK_GENERATION
22839. DA732X_NO_INVERT
22840. DA732X_OUTPUT_OFFSET_STEP
22841. DA732X_OUT_HIZ_DIS
22842. DA732X_OUT_HIZ_EN
22843. DA732X_PC_CLK_EN
22844. DA732X_PC_PULSE_AIFA
22845. DA732X_PC_PULSE_AIFB
22846. DA732X_PC_RESYNC_AUT
22847. DA732X_PC_RESYNC_NOT_AUT
22848. DA732X_PC_SAME
22849. DA732X_PLL_BYPASS
22850. DA732X_PLL_EN
22851. DA732X_PLL_INDIV_MASK
22852. DA732X_PLL_OUT_180634
22853. DA732X_PLL_OUT_196608
22854. DA732X_PLL_OUT_SRM
22855. DA732X_PLL_SRM_EN
22856. DA732X_RATES
22857. DA732X_REFBUFX2_DIS
22858. DA732X_REFBUFX2_EN
22859. DA732X_REG_ADC1_EQ12
22860. DA732X_REG_ADC1_EQ34
22861. DA732X_REG_ADC1_EQ5
22862. DA732X_REG_ADC1_HPF
22863. DA732X_REG_ADC1_PD
22864. DA732X_REG_ADC1_SEL
22865. DA732X_REG_ADC2_EQ12
22866. DA732X_REG_ADC2_EQ34
22867. DA732X_REG_ADC2_EQ5
22868. DA732X_REG_ADC2_HPF
22869. DA732X_REG_ADC2_PD
22870. DA732X_REG_ADC2_SEL
22871. DA732X_REG_AIFA1
22872. DA732X_REG_AIFA2
22873. DA732X_REG_AIFA3
22874. DA732X_REG_AIFB1
22875. DA732X_REG_AIFB2
22876. DA732X_REG_AIFB3
22877. DA732X_REG_AIF_MCLK
22878. DA732X_REG_AUX1L
22879. DA732X_REG_AUX1R
22880. DA732X_REG_BIAS1
22881. DA732X_REG_BIAS2
22882. DA732X_REG_BIAS3
22883. DA732X_REG_BIAS4
22884. DA732X_REG_BIAS_EN
22885. DA732X_REG_BIQ_BYP
22886. DA732X_REG_BROWNOUT
22887. DA732X_REG_CIF_CTRL2
22888. DA732X_REG_CLK_CTRL
22889. DA732X_REG_CLK_DSP
22890. DA732X_REG_CLK_EN1
22891. DA732X_REG_CLK_EN2
22892. DA732X_REG_CLK_EN3
22893. DA732X_REG_CLK_EN4
22894. DA732X_REG_CLK_EN5
22895. DA732X_REG_CP_CTRL1
22896. DA732X_REG_CP_CTRL2
22897. DA732X_REG_CP_CTRL3
22898. DA732X_REG_CP_DET
22899. DA732X_REG_CP_HP1
22900. DA732X_REG_CP_HP2
22901. DA732X_REG_CP_LEVEL_MASK
22902. DA732X_REG_CP_STATUS
22903. DA732X_REG_CP_THRESH1
22904. DA732X_REG_CP_THRESH2
22905. DA732X_REG_CP_THRESH3
22906. DA732X_REG_CP_THRESH4
22907. DA732X_REG_CP_THRESH5
22908. DA732X_REG_CP_THRESH6
22909. DA732X_REG_CP_THRESH7
22910. DA732X_REG_CP_THRESH8
22911. DA732X_REG_DAC1_EQ12
22912. DA732X_REG_DAC1_EQ34
22913. DA732X_REG_DAC1_EQ5
22914. DA732X_REG_DAC1_HPF
22915. DA732X_REG_DAC1_L_VOL
22916. DA732X_REG_DAC1_R_VOL
22917. DA732X_REG_DAC1_SEL
22918. DA732X_REG_DAC1_SOFTMUTE
22919. DA732X_REG_DAC2_EQ12
22920. DA732X_REG_DAC2_EQ34
22921. DA732X_REG_DAC2_EQ5
22922. DA732X_REG_DAC2_HPF
22923. DA732X_REG_DAC2_L_VOL
22924. DA732X_REG_DAC2_R_VOL
22925. DA732X_REG_DAC2_SEL
22926. DA732X_REG_DAC2_SOFTMUTE
22927. DA732X_REG_DAC3_EQ12
22928. DA732X_REG_DAC3_EQ34
22929. DA732X_REG_DAC3_EQ5
22930. DA732X_REG_DAC3_HPF
22931. DA732X_REG_DAC3_SEL
22932. DA732X_REG_DAC3_SOFTMUTE
22933. DA732X_REG_DAC3_VOL
22934. DA732X_REG_DATA_ROUTE
22935. DA732X_REG_DMA_ADDR0
22936. DA732X_REG_DMA_ADDR1
22937. DA732X_REG_DMA_CMD
22938. DA732X_REG_DMA_DATA0
22939. DA732X_REG_DMA_DATA1
22940. DA732X_REG_DMA_DATA2
22941. DA732X_REG_DMA_DATA3
22942. DA732X_REG_DMA_STATUS
22943. DA732X_REG_DSP_CTRL
22944. DA732X_REG_HANDSHAKE
22945. DA732X_REG_HPL
22946. DA732X_REG_HPL_DAC_OFFSET
22947. DA732X_REG_HPL_DAC_OFF_CNTL
22948. DA732X_REG_HPL_OUT_OFFSET
22949. DA732X_REG_HPL_VOL
22950. DA732X_REG_HPR
22951. DA732X_REG_HPR_DAC_OFFSET
22952. DA732X_REG_HPR_DAC_OFF_CNTL
22953. DA732X_REG_HPR_OUT_OFFSET
22954. DA732X_REG_HPR_VOL
22955. DA732X_REG_HP_DET
22956. DA732X_REG_HP_LIN1_GNDSEL
22957. DA732X_REG_ID
22958. DA732X_REG_INP_MUX
22959. DA732X_REG_INP_PINBIAS
22960. DA732X_REG_INP_ZC_EN
22961. DA732X_REG_LIN2
22962. DA732X_REG_LIN3
22963. DA732X_REG_LIN4
22964. DA732X_REG_MBOX0
22965. DA732X_REG_MBOX1
22966. DA732X_REG_MBOX2
22967. DA732X_REG_MBOX_STATUS
22968. DA732X_REG_MIC1
22969. DA732X_REG_MIC1_PRE
22970. DA732X_REG_MIC2
22971. DA732X_REG_MIC2_PRE
22972. DA732X_REG_MIC3
22973. DA732X_REG_MIC3_PRE
22974. DA732X_REG_MICBIAS1
22975. DA732X_REG_MICBIAS2
22976. DA732X_REG_MICDET
22977. DA732X_REG_OUT_ZC_EN
22978. DA732X_REG_PC_CTRL
22979. DA732X_REG_PLL_CTRL
22980. DA732X_REG_PLL_DIV_HI
22981. DA732X_REG_PLL_DIV_LO
22982. DA732X_REG_PLL_DIV_MID
22983. DA732X_REG_REF1
22984. DA732X_REG_SPARE1_IN
22985. DA732X_REG_SPARE1_OUT
22986. DA732X_REG_SPARE2_OUT
22987. DA732X_REG_STATUS
22988. DA732X_REG_STATUS_EXT
22989. DA732X_REG_UNLOCK
22990. DA732X_RESET_ADCS
22991. DA732X_SEL_DSP_DMA_DIS
22992. DA732X_SEL_DSP_DMA_MASK
22993. DA732X_SEL_DSP_DMA_PMEM
22994. DA732X_SEL_DSP_DMA_XMEM
22995. DA732X_SEL_DSP_DMA_YMEM
22996. DA732X_SIF_VDD_SEL_AIFA_VDD2
22997. DA732X_SIF_VDD_SEL_AIFB_VDD2
22998. DA732X_SIF_VDD_SEL_CIFA_VDD2
22999. DA732X_SOFTMUTE_EN
23000. DA732X_SOFTMUTE_MASK
23001. DA732X_SOFTMUTE_SHIFT
23002. DA732X_SR1_MASK
23003. DA732X_SR2_MASK
23004. DA732X_SRCCLK_MCLK
23005. DA732X_SRCCLK_PLL
23006. DA732X_SR_11_025KHZ
23007. DA732X_SR_12KHZ
23008. DA732X_SR_16KHZ
23009. DA732X_SR_22_05KHZ
23010. DA732X_SR_24KHZ
23011. DA732X_SR_32KHZ
23012. DA732X_SR_44_1KHZ
23013. DA732X_SR_48KHZ
23014. DA732X_SR_88_1KHZ
23015. DA732X_SR_8KHZ
23016. DA732X_SR_96KHZ
23017. DA732X_STARTUP_DELAY
23018. DA732X_STATUS_BO_STATUS
23019. DA732X_STATUS_EXT_CLEAR
23020. DA732X_STATUS_EXT_DSP
23021. DA732X_STATUS_HPDET_OUT
23022. DA732X_STATUS_INP_MIXDET_1
23023. DA732X_STATUS_INP_MIXDET_2
23024. DA732X_STATUS_PLL_LOCK
23025. DA732X_STATUS_PLL_MCLK_DET
23026. DA732X_SWITCH_MAX
23027. DA732X_SYS3_CLK_EN
23028. DA732X_U8_MASK
23029. DA732X_UART_CLK_EN
23030. DA732X_VMID_FASTCHG
23031. DA732X_VMID_FASTDISCHG
23032. DA732X_WAIT_FOR_STABILIZATION
23033. DA830_ACLKR0
23034. DA830_ACLKR1
23035. DA830_ACLKR2
23036. DA830_ACLKX0
23037. DA830_ACLKX1
23038. DA830_ACLKX2
23039. DA830_AFSR0
23040. DA830_AFSR1
23041. DA830_AFSR2
23042. DA830_AFSX0
23043. DA830_AFSX1
23044. DA830_AFSX2
23045. DA830_AHCLKR0
23046. DA830_AHCLKR1
23047. DA830_AHCLKR2
23048. DA830_AHCLKX0
23049. DA830_AHCLKX1
23050. DA830_AHCLKX2
23051. DA830_AMUTE0
23052. DA830_AMUTE1
23053. DA830_AMUTE2
23054. DA830_AXR0_0
23055. DA830_AXR0_1
23056. DA830_AXR0_10
23057. DA830_AXR0_11
23058. DA830_AXR0_12
23059. DA830_AXR0_13
23060. DA830_AXR0_14
23061. DA830_AXR0_15
23062. DA830_AXR0_2
23063. DA830_AXR0_3
23064. DA830_AXR0_4
23065. DA830_AXR0_5
23066. DA830_AXR0_6
23067. DA830_AXR0_7
23068. DA830_AXR0_8
23069. DA830_AXR0_9
23070. DA830_AXR1_0
23071. DA830_AXR1_1
23072. DA830_AXR1_10
23073. DA830_AXR1_11
23074. DA830_AXR1_2
23075. DA830_AXR1_3
23076. DA830_AXR1_4
23077. DA830_AXR1_5
23078. DA830_AXR1_6
23079. DA830_AXR1_7
23080. DA830_AXR1_8
23081. DA830_AXR1_9
23082. DA830_AXR2_0
23083. DA830_AXR2_1
23084. DA830_AXR2_2
23085. DA830_AXR2_3
23086. DA830_CMP12_0
23087. DA830_CMP12_1
23088. DA830_CMP12_2
23089. DA830_CMP12_3
23090. DA830_CMP12_4
23091. DA830_CMP12_5
23092. DA830_CMP12_6
23093. DA830_CMP12_7
23094. DA830_ECAP0_APWM0
23095. DA830_ECAP1_APWM1
23096. DA830_ECAP2_APWM2
23097. DA830_EHRPWMGLUETZ
23098. DA830_EMA_A_0
23099. DA830_EMA_A_1
23100. DA830_EMA_A_10
23101. DA830_EMA_A_11
23102. DA830_EMA_A_12
23103. DA830_EMA_A_2
23104. DA830_EMA_A_3
23105. DA830_EMA_A_4
23106. DA830_EMA_A_5
23107. DA830_EMA_A_6
23108. DA830_EMA_A_7
23109. DA830_EMA_A_8
23110. DA830_EMA_A_9
23111. DA830_EMA_BA_0
23112. DA830_EMA_BA_1
23113. DA830_EMA_CLK
23114. DA830_EMA_D_0
23115. DA830_EMA_D_1
23116. DA830_EMA_D_10
23117. DA830_EMA_D_11
23118. DA830_EMA_D_12
23119. DA830_EMA_D_13
23120. DA830_EMA_D_14
23121. DA830_EMA_D_15
23122. DA830_EMA_D_2
23123. DA830_EMA_D_3
23124. DA830_EMA_D_4
23125. DA830_EMA_D_5
23126. DA830_EMA_D_6
23127. DA830_EMA_D_7
23128. DA830_EMA_D_8
23129. DA830_EMA_D_9
23130. DA830_EMA_SDCKE
23131. DA830_EMA_WAIT_0
23132. DA830_EMB_A_0
23133. DA830_EMB_A_1
23134. DA830_EMB_A_10
23135. DA830_EMB_A_11
23136. DA830_EMB_A_12
23137. DA830_EMB_A_2
23138. DA830_EMB_A_3
23139. DA830_EMB_A_4
23140. DA830_EMB_A_5
23141. DA830_EMB_A_6
23142. DA830_EMB_A_7
23143. DA830_EMB_A_8
23144. DA830_EMB_A_9
23145. DA830_EMB_BA_0
23146. DA830_EMB_BA_1
23147. DA830_EMB_CLK
23148. DA830_EMB_CLK_GLUE
23149. DA830_EMB_D_0
23150. DA830_EMB_D_1
23151. DA830_EMB_D_10
23152. DA830_EMB_D_11
23153. DA830_EMB_D_12
23154. DA830_EMB_D_13
23155. DA830_EMB_D_14
23156. DA830_EMB_D_15
23157. DA830_EMB_D_16
23158. DA830_EMB_D_17
23159. DA830_EMB_D_18
23160. DA830_EMB_D_19
23161. DA830_EMB_D_2
23162. DA830_EMB_D_20
23163. DA830_EMB_D_21
23164. DA830_EMB_D_22
23165. DA830_EMB_D_23
23166. DA830_EMB_D_24
23167. DA830_EMB_D_25
23168. DA830_EMB_D_26
23169. DA830_EMB_D_27
23170. DA830_EMB_D_28
23171. DA830_EMB_D_29
23172. DA830_EMB_D_3
23173. DA830_EMB_D_30
23174. DA830_EMB_D_31
23175. DA830_EMB_D_4
23176. DA830_EMB_D_5
23177. DA830_EMB_D_6
23178. DA830_EMB_D_7
23179. DA830_EMB_D_8
23180. DA830_EMB_D_9
23181. DA830_EMB_SDCKE
23182. DA830_EMU_0
23183. DA830_EPWM0A
23184. DA830_EPWM0B
23185. DA830_EPWM1A
23186. DA830_EPWM1B
23187. DA830_EPWM2A
23188. DA830_EPWM2B
23189. DA830_EPWMSYNC0
23190. DA830_EPWMSYNCI
23191. DA830_EQEP0A
23192. DA830_EQEP0B
23193. DA830_EQEP0I
23194. DA830_EQEP0S
23195. DA830_EQEP1A
23196. DA830_EQEP1B
23197. DA830_EQEP1I
23198. DA830_EQEP1S
23199. DA830_EVM_PHY_ID
23200. DA830_GPIO0_0
23201. DA830_GPIO0_1
23202. DA830_GPIO0_10
23203. DA830_GPIO0_11
23204. DA830_GPIO0_12
23205. DA830_GPIO0_13
23206. DA830_GPIO0_14
23207. DA830_GPIO0_15
23208. DA830_GPIO0_2
23209. DA830_GPIO0_3
23210. DA830_GPIO0_4
23211. DA830_GPIO0_5
23212. DA830_GPIO0_6
23213. DA830_GPIO0_7
23214. DA830_GPIO0_8
23215. DA830_GPIO0_9
23216. DA830_GPIO1_0
23217. DA830_GPIO1_1
23218. DA830_GPIO1_10
23219. DA830_GPIO1_11
23220. DA830_GPIO1_12
23221. DA830_GPIO1_13
23222. DA830_GPIO1_14
23223. DA830_GPIO1_15
23224. DA830_GPIO1_2
23225. DA830_GPIO1_3
23226. DA830_GPIO1_4
23227. DA830_GPIO1_5
23228. DA830_GPIO1_6
23229. DA830_GPIO1_7
23230. DA830_GPIO1_8
23231. DA830_GPIO1_9
23232. DA830_GPIO2_0
23233. DA830_GPIO2_1
23234. DA830_GPIO2_10
23235. DA830_GPIO2_11
23236. DA830_GPIO2_12
23237. DA830_GPIO2_13
23238. DA830_GPIO2_14
23239. DA830_GPIO2_15
23240. DA830_GPIO2_2
23241. DA830_GPIO2_3
23242. DA830_GPIO2_4
23243. DA830_GPIO2_5
23244. DA830_GPIO2_6
23245. DA830_GPIO2_7
23246. DA830_GPIO2_8
23247. DA830_GPIO2_9
23248. DA830_GPIO3_0
23249. DA830_GPIO3_1
23250. DA830_GPIO3_10
23251. DA830_GPIO3_11
23252. DA830_GPIO3_12
23253. DA830_GPIO3_13
23254. DA830_GPIO3_14
23255. DA830_GPIO3_15
23256. DA830_GPIO3_2
23257. DA830_GPIO3_3
23258. DA830_GPIO3_4
23259. DA830_GPIO3_5
23260. DA830_GPIO3_6
23261. DA830_GPIO3_7
23262. DA830_GPIO3_8
23263. DA830_GPIO3_9
23264. DA830_GPIO4_0
23265. DA830_GPIO4_1
23266. DA830_GPIO4_10
23267. DA830_GPIO4_11
23268. DA830_GPIO4_12
23269. DA830_GPIO4_13
23270. DA830_GPIO4_14
23271. DA830_GPIO4_15
23272. DA830_GPIO4_2
23273. DA830_GPIO4_3
23274. DA830_GPIO4_4
23275. DA830_GPIO4_5
23276. DA830_GPIO4_6
23277. DA830_GPIO4_7
23278. DA830_GPIO4_8
23279. DA830_GPIO4_9
23280. DA830_GPIO5_0
23281. DA830_GPIO5_1
23282. DA830_GPIO5_10
23283. DA830_GPIO5_11
23284. DA830_GPIO5_12
23285. DA830_GPIO5_13
23286. DA830_GPIO5_14
23287. DA830_GPIO5_15
23288. DA830_GPIO5_2
23289. DA830_GPIO5_3
23290. DA830_GPIO5_4
23291. DA830_GPIO5_5
23292. DA830_GPIO5_6
23293. DA830_GPIO5_7
23294. DA830_GPIO5_8
23295. DA830_GPIO5_9
23296. DA830_GPIO6_0
23297. DA830_GPIO6_1
23298. DA830_GPIO6_10
23299. DA830_GPIO6_11
23300. DA830_GPIO6_12
23301. DA830_GPIO6_13
23302. DA830_GPIO6_14
23303. DA830_GPIO6_15
23304. DA830_GPIO6_2
23305. DA830_GPIO6_3
23306. DA830_GPIO6_4
23307. DA830_GPIO6_5
23308. DA830_GPIO6_6
23309. DA830_GPIO6_7
23310. DA830_GPIO6_8
23311. DA830_GPIO6_9
23312. DA830_GPIO7_0
23313. DA830_GPIO7_1
23314. DA830_GPIO7_10
23315. DA830_GPIO7_11
23316. DA830_GPIO7_12
23317. DA830_GPIO7_13
23318. DA830_GPIO7_14
23319. DA830_GPIO7_15
23320. DA830_GPIO7_2
23321. DA830_GPIO7_3
23322. DA830_GPIO7_4
23323. DA830_GPIO7_5
23324. DA830_GPIO7_6
23325. DA830_GPIO7_7
23326. DA830_GPIO7_8
23327. DA830_GPIO7_9
23328. DA830_I2C0_SCL
23329. DA830_I2C0_SDA
23330. DA830_I2C1_SCL
23331. DA830_I2C1_SDA
23332. DA830_LCD_D_0
23333. DA830_LCD_D_1
23334. DA830_LCD_D_10
23335. DA830_LCD_D_11
23336. DA830_LCD_D_12
23337. DA830_LCD_D_13
23338. DA830_LCD_D_14
23339. DA830_LCD_D_15
23340. DA830_LCD_D_2
23341. DA830_LCD_D_3
23342. DA830_LCD_D_4
23343. DA830_LCD_D_5
23344. DA830_LCD_D_6
23345. DA830_LCD_D_7
23346. DA830_LCD_D_8
23347. DA830_LCD_D_9
23348. DA830_LCD_HSYNC
23349. DA830_LCD_MCLK
23350. DA830_LCD_PCLK
23351. DA830_LCD_VSYNC
23352. DA830_LPSC1_EQEP
23353. DA830_LPSC1_McASP1
23354. DA830_LPSC1_McASP2
23355. DA830_MDIO_CLK
23356. DA830_MDIO_D
23357. DA830_MMCSD_CD_PIN
23358. DA830_MMCSD_CLK
23359. DA830_MMCSD_CMD
23360. DA830_MMCSD_DAT_0
23361. DA830_MMCSD_DAT_1
23362. DA830_MMCSD_DAT_2
23363. DA830_MMCSD_DAT_3
23364. DA830_MMCSD_DAT_4
23365. DA830_MMCSD_DAT_5
23366. DA830_MMCSD_DAT_6
23367. DA830_MMCSD_DAT_7
23368. DA830_MMCSD_WP_PIN
23369. DA830_NEMA_CAS
23370. DA830_NEMA_CS_0
23371. DA830_NEMA_CS_2
23372. DA830_NEMA_CS_3
23373. DA830_NEMA_CS_4
23374. DA830_NEMA_CS_5
23375. DA830_NEMA_OE
23376. DA830_NEMA_RAS
23377. DA830_NEMA_WE
23378. DA830_NEMA_WE_DQM_0
23379. DA830_NEMA_WE_DQM_1
23380. DA830_NEMB_CAS
23381. DA830_NEMB_CS_0
23382. DA830_NEMB_RAS
23383. DA830_NEMB_WE
23384. DA830_NEMB_WE_DQM_0
23385. DA830_NEMB_WE_DQM_1
23386. DA830_NEMB_WE_DQM_2
23387. DA830_NEMB_WE_DQM_3
23388. DA830_NLCD_AC_ENB_CS
23389. DA830_NRESETOUT
23390. DA830_NSPI0_ENA
23391. DA830_NSPI0_SCS_0
23392. DA830_NSPI1_ENA
23393. DA830_NSPI1_SCS_0
23394. DA830_NUART0_CTS
23395. DA830_NUART0_RTS
23396. DA830_NUHPI_HAS
23397. DA830_NUHPI_HCS
23398. DA830_NUHPI_HDS1
23399. DA830_NUHPI_HDS2
23400. DA830_NUHPI_HINT
23401. DA830_NUHPI_HRDY
23402. DA830_N_CP_INTC_IRQ
23403. DA830_OBSCLK
23404. DA830_REF_FREQ
23405. DA830_RMII_CRS_DV
23406. DA830_RMII_MHZ_50_CLK
23407. DA830_RMII_RXD_0
23408. DA830_RMII_RXD_1
23409. DA830_RMII_RXER
23410. DA830_RMII_TXD_0
23411. DA830_RMII_TXD_1
23412. DA830_RMII_TXEN
23413. DA830_RTCK
23414. DA830_SPI0_CLK
23415. DA830_SPI0_SIMO_0
23416. DA830_SPI0_SOMI_0
23417. DA830_SPI1_BASE
23418. DA830_SPI1_CLK
23419. DA830_SPI1_SIMO_0
23420. DA830_SPI1_SOMI_0
23421. DA830_TM64P0_IN12
23422. DA830_TM64P0_OUT12
23423. DA830_UART0_RXD
23424. DA830_UART0_TXD
23425. DA830_UART1_RXD
23426. DA830_UART1_TXD
23427. DA830_UART2_RXD
23428. DA830_UART2_TXD
23429. DA830_UHPI_HCNTL0
23430. DA830_UHPI_HCNTL1
23431. DA830_UHPI_HD_0
23432. DA830_UHPI_HD_1
23433. DA830_UHPI_HD_10
23434. DA830_UHPI_HD_11
23435. DA830_UHPI_HD_12
23436. DA830_UHPI_HD_13
23437. DA830_UHPI_HD_14
23438. DA830_UHPI_HD_15
23439. DA830_UHPI_HD_2
23440. DA830_UHPI_HD_3
23441. DA830_UHPI_HD_4
23442. DA830_UHPI_HD_5
23443. DA830_UHPI_HD_6
23444. DA830_UHPI_HD_7
23445. DA830_UHPI_HD_8
23446. DA830_UHPI_HD_9
23447. DA830_UHPI_HHWIL
23448. DA830_UHPI_HRNW
23449. DA830_USB0_DRVVBUS
23450. DA830_USB_REFCLKIN
23451. DA850EVM_SATA_REFCLKPN_RATE
23452. DA850_ACLKR
23453. DA850_ACLKX
23454. DA850_AFSR
23455. DA850_AFSX
23456. DA850_AHCLKR
23457. DA850_AHCLKX
23458. DA850_AMUTE
23459. DA850_AXR_0
23460. DA850_AXR_1
23461. DA850_AXR_10
23462. DA850_AXR_11
23463. DA850_AXR_12
23464. DA850_AXR_13
23465. DA850_AXR_14
23466. DA850_AXR_15
23467. DA850_AXR_2
23468. DA850_AXR_3
23469. DA850_AXR_4
23470. DA850_AXR_5
23471. DA850_AXR_6
23472. DA850_AXR_7
23473. DA850_AXR_8
23474. DA850_AXR_9
23475. DA850_BB_EXPANDER_GPIO_BASE
23476. DA850_EMA_A_0
23477. DA850_EMA_A_1
23478. DA850_EMA_A_10
23479. DA850_EMA_A_11
23480. DA850_EMA_A_12
23481. DA850_EMA_A_13
23482. DA850_EMA_A_14
23483. DA850_EMA_A_15
23484. DA850_EMA_A_16
23485. DA850_EMA_A_17
23486. DA850_EMA_A_18
23487. DA850_EMA_A_19
23488. DA850_EMA_A_2
23489. DA850_EMA_A_20
23490. DA850_EMA_A_21
23491. DA850_EMA_A_22
23492. DA850_EMA_A_23
23493. DA850_EMA_A_3
23494. DA850_EMA_A_4
23495. DA850_EMA_A_5
23496. DA850_EMA_A_6
23497. DA850_EMA_A_7
23498. DA850_EMA_A_8
23499. DA850_EMA_A_9
23500. DA850_EMA_BA_1
23501. DA850_EMA_CLK
23502. DA850_EMA_D_0
23503. DA850_EMA_D_1
23504. DA850_EMA_D_10
23505. DA850_EMA_D_11
23506. DA850_EMA_D_12
23507. DA850_EMA_D_13
23508. DA850_EMA_D_14
23509. DA850_EMA_D_15
23510. DA850_EMA_D_2
23511. DA850_EMA_D_3
23512. DA850_EMA_D_4
23513. DA850_EMA_D_5
23514. DA850_EMA_D_6
23515. DA850_EMA_D_7
23516. DA850_EMA_D_8
23517. DA850_EMA_D_9
23518. DA850_EMA_WAIT_1
23519. DA850_EVM_BB_EXP_DEEP_SLEEP_EN
23520. DA850_EVM_BB_EXP_SW_RST
23521. DA850_EVM_BB_EXP_TP_21
23522. DA850_EVM_BB_EXP_TP_22
23523. DA850_EVM_BB_EXP_TP_23
23524. DA850_EVM_BB_EXP_USER_LED1
23525. DA850_EVM_BB_EXP_USER_LED2
23526. DA850_EVM_BB_EXP_USER_PB1
23527. DA850_EVM_BB_EXP_USER_SW1
23528. DA850_EVM_BB_EXP_USER_SW2
23529. DA850_EVM_BB_EXP_USER_SW3
23530. DA850_EVM_BB_EXP_USER_SW4
23531. DA850_EVM_BB_EXP_USER_SW5
23532. DA850_EVM_BB_EXP_USER_SW6
23533. DA850_EVM_BB_EXP_USER_SW7
23534. DA850_EVM_BB_EXP_USER_SW8
23535. DA850_EVM_PHY_ID
23536. DA850_EVM_UI_EXP_PB1
23537. DA850_EVM_UI_EXP_PB2
23538. DA850_EVM_UI_EXP_PB3
23539. DA850_EVM_UI_EXP_PB4
23540. DA850_EVM_UI_EXP_PB5
23541. DA850_EVM_UI_EXP_PB6
23542. DA850_EVM_UI_EXP_PB7
23543. DA850_EVM_UI_EXP_PB8
23544. DA850_EVM_UI_EXP_SEL_A
23545. DA850_EVM_UI_EXP_SEL_B
23546. DA850_EVM_UI_EXP_SEL_C
23547. DA850_GPIO2_15
23548. DA850_GPIO2_4
23549. DA850_GPIO2_6
23550. DA850_GPIO2_8
23551. DA850_GPIO3_12
23552. DA850_GPIO3_13
23553. DA850_GPIO4_0
23554. DA850_GPIO4_1
23555. DA850_GPIO6_10
23556. DA850_GPIO6_13
23557. DA850_GPIO6_9
23558. DA850_GPIO_KEYS_POLL_MS
23559. DA850_HAWK_MMCSD_CD_PIN
23560. DA850_HAWK_MMCSD_WP_PIN
23561. DA850_I2C0_SCL
23562. DA850_I2C0_SDA
23563. DA850_I2C1_SCL
23564. DA850_I2C1_SDA
23565. DA850_KEYS_DEBOUNCE_MS
23566. DA850_LCD_BL_PIN
23567. DA850_LCD_D_0
23568. DA850_LCD_D_1
23569. DA850_LCD_D_10
23570. DA850_LCD_D_11
23571. DA850_LCD_D_12
23572. DA850_LCD_D_13
23573. DA850_LCD_D_14
23574. DA850_LCD_D_15
23575. DA850_LCD_D_2
23576. DA850_LCD_D_3
23577. DA850_LCD_D_4
23578. DA850_LCD_D_5
23579. DA850_LCD_D_6
23580. DA850_LCD_D_7
23581. DA850_LCD_D_8
23582. DA850_LCD_D_9
23583. DA850_LCD_HSYNC
23584. DA850_LCD_PCLK
23585. DA850_LCD_PWR_PIN
23586. DA850_LCD_VSYNC
23587. DA850_LPSC1_MMC_SD1
23588. DA850_LPSC1_McBSP0
23589. DA850_LPSC1_McBSP1
23590. DA850_LPSC1_SATA
23591. DA850_LPSC1_TPCC1
23592. DA850_LPSC1_TPTC2
23593. DA850_LPSC1_VPIF
23594. DA850_MDIO_CLK
23595. DA850_MDIO_D
23596. DA850_MII_COL
23597. DA850_MII_CRS
23598. DA850_MII_MDIO_CLKEN_PIN
23599. DA850_MII_RXCLK
23600. DA850_MII_RXDV
23601. DA850_MII_RXD_0
23602. DA850_MII_RXD_1
23603. DA850_MII_RXD_2
23604. DA850_MII_RXD_3
23605. DA850_MII_RXER
23606. DA850_MII_TXCLK
23607. DA850_MII_TXD_0
23608. DA850_MII_TXD_1
23609. DA850_MII_TXD_2
23610. DA850_MII_TXD_3
23611. DA850_MII_TXEN
23612. DA850_MMCSD0_CLK
23613. DA850_MMCSD0_CMD
23614. DA850_MMCSD0_DAT_0
23615. DA850_MMCSD0_DAT_1
23616. DA850_MMCSD0_DAT_2
23617. DA850_MMCSD0_DAT_3
23618. DA850_MMCSD1_BASE
23619. DA850_MMCSD1_CLK
23620. DA850_MMCSD1_CMD
23621. DA850_MMCSD1_DAT_0
23622. DA850_MMCSD1_DAT_1
23623. DA850_MMCSD1_DAT_2
23624. DA850_MMCSD1_DAT_3
23625. DA850_MMCSD_CD_PIN
23626. DA850_MMCSD_WP_PIN
23627. DA850_NEMA_CS_2
23628. DA850_NEMA_CS_3
23629. DA850_NEMA_CS_4
23630. DA850_NEMA_OE
23631. DA850_NEMA_WE
23632. DA850_NLCD_AC_ENB_CS
23633. DA850_NUART0_CTS
23634. DA850_NUART0_RTS
23635. DA850_NUART1_CTS
23636. DA850_NUART1_RTS
23637. DA850_NUART2_CTS
23638. DA850_NUART2_RTS
23639. DA850_N_BB_USER_SW
23640. DA850_N_CP_INTC_IRQ
23641. DA850_N_UI_PB
23642. DA850_PLL1_BASE
23643. DA850_PUPD_ENA
23644. DA850_PUPD_SEL
23645. DA850_REF_FREQ
23646. DA850_RMII_CRS_DV
23647. DA850_RMII_MHZ_50_CLK
23648. DA850_RMII_RXD_0
23649. DA850_RMII_RXD_1
23650. DA850_RMII_RXER
23651. DA850_RMII_TXD_0
23652. DA850_RMII_TXD_1
23653. DA850_RMII_TXEN
23654. DA850_RTC_ALARM
23655. DA850_SATA_BASE
23656. DA850_SPI1_BASE
23657. DA850_TIMER64P2_BASE
23658. DA850_TIMER64P3_BASE
23659. DA850_TPCC1_BASE
23660. DA850_TPTC2_BASE
23661. DA850_UART0_RXD
23662. DA850_UART0_TXD
23663. DA850_UART1_RXD
23664. DA850_UART1_TXD
23665. DA850_UART2_RXD
23666. DA850_UART2_TXD
23667. DA850_UI_EXPANDER_N_GPIOS
23668. DA850_USB1_OC_PIN
23669. DA850_USB1_VBUS_PIN
23670. DA850_VPIF_CLKIN0
23671. DA850_VPIF_CLKIN1
23672. DA850_VPIF_CLKIN2
23673. DA850_VPIF_CLKIN3
23674. DA850_VPIF_CLKO2
23675. DA850_VPIF_CLKO3
23676. DA850_VPIF_DIN0
23677. DA850_VPIF_DIN1
23678. DA850_VPIF_DIN10
23679. DA850_VPIF_DIN11
23680. DA850_VPIF_DIN12
23681. DA850_VPIF_DIN13
23682. DA850_VPIF_DIN14
23683. DA850_VPIF_DIN15
23684. DA850_VPIF_DIN2
23685. DA850_VPIF_DIN3
23686. DA850_VPIF_DIN4
23687. DA850_VPIF_DIN5
23688. DA850_VPIF_DIN6
23689. DA850_VPIF_DIN7
23690. DA850_VPIF_DIN8
23691. DA850_VPIF_DIN9
23692. DA850_VPIF_DOUT0
23693. DA850_VPIF_DOUT1
23694. DA850_VPIF_DOUT10
23695. DA850_VPIF_DOUT11
23696. DA850_VPIF_DOUT12
23697. DA850_VPIF_DOUT13
23698. DA850_VPIF_DOUT14
23699. DA850_VPIF_DOUT15
23700. DA850_VPIF_DOUT2
23701. DA850_VPIF_DOUT3
23702. DA850_VPIF_DOUT4
23703. DA850_VPIF_DOUT5
23704. DA850_VPIF_DOUT6
23705. DA850_VPIF_DOUT7
23706. DA850_VPIF_DOUT8
23707. DA850_VPIF_DOUT9
23708. DA8XX_AEMIF_CS2_BASE
23709. DA8XX_AEMIF_CS3_BASE
23710. DA8XX_AEMIF_CTL_BASE
23711. DA8XX_ARM_RAM_BASE
23712. DA8XX_CFGCHIP0_REG
23713. DA8XX_CFGCHIP1_REG
23714. DA8XX_CFGCHIP2_REG
23715. DA8XX_CFGCHIP3_REG
23716. DA8XX_CFGCHIP4_REG
23717. DA8XX_CHIPSIG_REG
23718. DA8XX_CP_INTC_BASE
23719. DA8XX_CP_INTC_SIZE
23720. DA8XX_CP_INTC_VIRT
23721. DA8XX_DDR2_CTL_BASE
23722. DA8XX_DEEPSLEEP_REG
23723. DA8XX_DMA_NUM_CHANNELS
23724. DA8XX_DSP_L1D_RAM_BASE
23725. DA8XX_DSP_L1P_RAM_BASE
23726. DA8XX_DSP_L2_RAM_BASE
23727. DA8XX_EMAC_CPGMACSS_BASE
23728. DA8XX_EMAC_CPGMAC_BASE
23729. DA8XX_EMAC_CPPI_PORT_BASE
23730. DA8XX_EMAC_CTRL_RAM_SIZE
23731. DA8XX_EMAC_CTRL_REG_OFFSET
23732. DA8XX_EMAC_MDIO_BASE
23733. DA8XX_EMAC_MOD_REG_OFFSET
23734. DA8XX_EMAC_RAM_OFFSET
23735. DA8XX_FB_H
23736. DA8XX_FRAME_NOWAIT
23737. DA8XX_FRAME_WAIT
23738. DA8XX_GATE_CLOCK_IS_DIV4P5
23739. DA8XX_GPIO_BASE
23740. DA8XX_HOST1CFG_REG
23741. DA8XX_I2C0_BASE
23742. DA8XX_I2C1_BASE
23743. DA8XX_INTR_DRVVBUS
23744. DA8XX_INTR_RX_MASK
23745. DA8XX_INTR_RX_SHIFT
23746. DA8XX_INTR_TX_MASK
23747. DA8XX_INTR_TX_SHIFT
23748. DA8XX_INTR_USB_MASK
23749. DA8XX_INTR_USB_SHIFT
23750. DA8XX_JTAG_ID_REG
23751. DA8XX_LCD_CNTRL_BASE
23752. DA8XX_LPSC0_AINTC
23753. DA8XX_LPSC0_ARM
23754. DA8XX_LPSC0_ARM_RAM_ROM
23755. DA8XX_LPSC0_EMIF25
23756. DA8XX_LPSC0_GEM
23757. DA8XX_LPSC0_MMC_SD
23758. DA8XX_LPSC0_PRUSS
23759. DA8XX_LPSC0_SCR0_SS
23760. DA8XX_LPSC0_SCR1_SS
23761. DA8XX_LPSC0_SCR2_SS
23762. DA8XX_LPSC0_SECU_MGR
23763. DA8XX_LPSC0_SPI0
23764. DA8XX_LPSC0_TPCC
23765. DA8XX_LPSC0_TPTC0
23766. DA8XX_LPSC0_TPTC1
23767. DA8XX_LPSC0_UART0
23768. DA8XX_LPSC1_CPGMAC
23769. DA8XX_LPSC1_CR_P3_SS
23770. DA8XX_LPSC1_ECAP
23771. DA8XX_LPSC1_EMIF3C
23772. DA8XX_LPSC1_GPIO
23773. DA8XX_LPSC1_I2C
23774. DA8XX_LPSC1_L3_CBA_RAM
23775. DA8XX_LPSC1_LCDC
23776. DA8XX_LPSC1_McASP0
23777. DA8XX_LPSC1_PWM
23778. DA8XX_LPSC1_SCR_P0_SS
23779. DA8XX_LPSC1_SCR_P1_SS
23780. DA8XX_LPSC1_SPI1
23781. DA8XX_LPSC1_UART1
23782. DA8XX_LPSC1_UART2
23783. DA8XX_LPSC1_UHPI
23784. DA8XX_LPSC1_USB11
23785. DA8XX_LPSC1_USB20
23786. DA8XX_MENTOR_CORE_OFFSET
23787. DA8XX_MMCSD0_BASE
23788. DA8XX_MSTPRI0_OFFSET
23789. DA8XX_MSTPRI1_OFFSET
23790. DA8XX_MSTPRI2_OFFSET
23791. DA8XX_MSTPRI_ARM_D
23792. DA8XX_MSTPRI_ARM_I
23793. DA8XX_MSTPRI_EDMA30TC0
23794. DA8XX_MSTPRI_EDMA30TC1
23795. DA8XX_MSTPRI_EDMA31TC0
23796. DA8XX_MSTPRI_EMAC
23797. DA8XX_MSTPRI_LCDC
23798. DA8XX_MSTPRI_PRU0
23799. DA8XX_MSTPRI_PRU1
23800. DA8XX_MSTPRI_SATA
23801. DA8XX_MSTPRI_UHPI
23802. DA8XX_MSTPRI_UPP
23803. DA8XX_MSTPRI_USB0CDMA
23804. DA8XX_MSTPRI_USB0CFG
23805. DA8XX_MSTPRI_USB1
23806. DA8XX_MSTPRI_VPIF_DMA_0
23807. DA8XX_MSTPRI_VPIF_DMA_1
23808. DA8XX_PLL0_BASE
23809. DA8XX_PRUSS_MEM_BASE
23810. DA8XX_PSC0_BASE
23811. DA8XX_PSC1_BASE
23812. DA8XX_PWRDN_REG
23813. DA8XX_RPROC_LOCAL_ADDRESS_MASK
23814. DA8XX_RTC_BASE
23815. DA8XX_SHARED_RAM_BASE
23816. DA8XX_SOFT_RESET_MASK
23817. DA8XX_SPI0_BASE
23818. DA8XX_SYSCFG0_BASE
23819. DA8XX_SYSCFG0_VIRT
23820. DA8XX_SYSCFG1_BASE
23821. DA8XX_SYSCFG1_VIRT
23822. DA8XX_TIMER64P0_BASE
23823. DA8XX_TIMER64P1_BASE
23824. DA8XX_TPCC_BASE
23825. DA8XX_TPTC0_BASE
23826. DA8XX_TPTC1_BASE
23827. DA8XX_UART0_BASE
23828. DA8XX_UART1_BASE
23829. DA8XX_UART2_BASE
23830. DA8XX_USB0_BASE
23831. DA8XX_USB1_BASE
23832. DA8XX_USB_AUTOREQ
23833. DA8XX_USB_CTRL_REG
23834. DA8XX_USB_EMULATION_REG
23835. DA8XX_USB_END_OF_INTR_REG
23836. DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG
23837. DA8XX_USB_INTR_MASK_CLEAR_REG
23838. DA8XX_USB_INTR_MASK_REG
23839. DA8XX_USB_INTR_MASK_SET_REG
23840. DA8XX_USB_INTR_SRC_CLEAR_REG
23841. DA8XX_USB_INTR_SRC_MASKED_REG
23842. DA8XX_USB_INTR_SRC_REG
23843. DA8XX_USB_INTR_SRC_SET_REG
23844. DA8XX_USB_MODE
23845. DA8XX_USB_REVISION_REG
23846. DA8XX_USB_RX_EP_MASK
23847. DA8XX_USB_SRP_FIX_TIME_REG
23848. DA8XX_USB_STAT_REG
23849. DA8XX_USB_TEARDOWN
23850. DA8XX_USB_TX_EP_MASK
23851. DA8XX_VPIF_BASE
23852. DA8XX_WDOG_BASE
23853. DA9030_ADC_AUTO_CONTROL
23854. DA9030_ADC_AUTO_SLEEP_ENABLE
23855. DA9030_ADC_ICH_ENABLE
23856. DA9030_ADC_LDO_INT_ENABLE
23857. DA9030_ADC_MAN_CONTROL
23858. DA9030_ADC_TBATREF_ENABLE
23859. DA9030_ADC_TBAT_ENABLE
23860. DA9030_ADC_VBAT_ENABLE
23861. DA9030_ADC_VBAT_IN_TXON
23862. DA9030_ADC_VCH_ENABLE
23863. DA9030_BUCK
23864. DA9030_BUCK2DVM1
23865. DA9030_BUCK2DVM2
23866. DA9030_CHARGE_CONTROL
23867. DA9030_CHIP_ID
23868. DA9030_CHRG_CHARGER_ENABLE
23869. DA9030_DVC
23870. DA9030_EVENT_A
23871. DA9030_EVENT_ADC_READY
23872. DA9030_EVENT_B
23873. DA9030_EVENT_BUCK2
23874. DA9030_EVENT_C
23875. DA9030_EVENT_CCTO
23876. DA9030_EVENT_CHDET
23877. DA9030_EVENT_CHIOVER
23878. DA9030_EVENT_EXTON
23879. DA9030_EVENT_LDO15
23880. DA9030_EVENT_LDO16
23881. DA9030_EVENT_LDO17
23882. DA9030_EVENT_LDO18
23883. DA9030_EVENT_LDO19
23884. DA9030_EVENT_ONKEY
23885. DA9030_EVENT_PWREN
23886. DA9030_EVENT_SESS_VALID
23887. DA9030_EVENT_SRP_DETECT
23888. DA9030_EVENT_TBAT
23889. DA9030_EVENT_TCTO
23890. DA9030_EVENT_VBATMON
23891. DA9030_EVENT_VBATMON_TXON
23892. DA9030_EVENT_VBUS_4P0
23893. DA9030_EVENT_VBUS_4P4
23894. DA9030_EVENT_WATCHDOG
23895. DA9030_FAULT_LOG
23896. DA9030_FAULT_LOG_OVER_TEMP
23897. DA9030_FAULT_LOG_VBAT_OVER
23898. DA9030_ICHAVERAGE_RES
23899. DA9030_ICHMAX_RES
23900. DA9030_ICHMIN_RES
23901. DA9030_ID_BAT
23902. DA9030_ID_BUCK1
23903. DA9030_ID_BUCK2
23904. DA9030_ID_LDO1
23905. DA9030_ID_LDO10
23906. DA9030_ID_LDO11
23907. DA9030_ID_LDO12
23908. DA9030_ID_LDO13
23909. DA9030_ID_LDO14
23910. DA9030_ID_LDO15
23911. DA9030_ID_LDO16
23912. DA9030_ID_LDO17
23913. DA9030_ID_LDO18
23914. DA9030_ID_LDO19
23915. DA9030_ID_LDO2
23916. DA9030_ID_LDO3
23917. DA9030_ID_LDO4
23918. DA9030_ID_LDO5
23919. DA9030_ID_LDO6
23920. DA9030_ID_LDO7
23921. DA9030_ID_LDO8
23922. DA9030_ID_LDO9
23923. DA9030_ID_LDO_INT
23924. DA9030_ID_LED_1
23925. DA9030_ID_LED_2
23926. DA9030_ID_LED_3
23927. DA9030_ID_LED_4
23928. DA9030_ID_LED_PC
23929. DA9030_ID_VIBRA
23930. DA9030_ID_WLED
23931. DA9030_INVAL
23932. DA9030_IRQ_MASK_A
23933. DA9030_IRQ_MASK_B
23934. DA9030_IRQ_MASK_C
23935. DA9030_LDO
23936. DA9030_LDO1
23937. DA9030_LDO1011
23938. DA9030_LDO1416
23939. DA9030_LDO15
23940. DA9030_LDO17
23941. DA9030_LDO1819
23942. DA9030_LDO23
23943. DA9030_LDO45
23944. DA9030_LDO6
23945. DA9030_LDO78
23946. DA9030_LDO912
23947. DA9030_LDO_UNLOCK
23948. DA9030_LDO_UNLOCK_MASK
23949. DA9030_LED1_CONTROL
23950. DA9030_LED2_CONTROL
23951. DA9030_LED3_CONTROL
23952. DA9030_LED4_CONTROL
23953. DA9030_LEDPC_CONTROL
23954. DA9030_LED_DUTY_1_16
23955. DA9030_LED_DUTY_1_2
23956. DA9030_LED_DUTY_1_4
23957. DA9030_LED_DUTY_1_8
23958. DA9030_LED_OFFSET
23959. DA9030_LED_RATE_052S
23960. DA9030_LED_RATE_ON
23961. DA9030_MAX_BRIGHTNESS
23962. DA9030_MISC_CONTROL_A
23963. DA9030_RCTL11
23964. DA9030_RCTL12
23965. DA9030_RCTL21
23966. DA9030_RCTL22
23967. DA9030_STATUS
23968. DA9030_STATUS_CHDET
23969. DA9030_STATUS_EXTON
23970. DA9030_STATUS_MCLKDET
23971. DA9030_STATUS_ONKEY
23972. DA9030_STATUS_PWREN1
23973. DA9030_STATUS_TBAT
23974. DA9030_STATUS_VBATMON
23975. DA9030_STATUS_VBATMON_TXON
23976. DA9030_SUBDEV
23977. DA9030_SYS_CTRL_A
23978. DA9030_SYS_CTRL_B
23979. DA9030_TBATHIGHN
23980. DA9030_TBATHIGHP
23981. DA9030_TBATLOW
23982. DA9030_TBAT_RES
23983. DA9030_VBATMINTXON_RES
23984. DA9030_VBATMIN_RES
23985. DA9030_VBATMON
23986. DA9030_VBATMONTXON
23987. DA9030_VBAT_RES
23988. DA9030_VCHMAX_RES
23989. DA9030_VCHMIN_RES
23990. DA9030_VIBRA_DUTY_25P
23991. DA9030_VIBRA_DUTY_50P
23992. DA9030_VIBRA_DUTY_75P
23993. DA9030_VIBRA_DUTY_ON
23994. DA9030_VIBRA_FREQ_1HZ
23995. DA9030_VIBRA_FREQ_2HZ
23996. DA9030_VIBRA_FREQ_4HZ
23997. DA9030_VIBRA_FREQ_8HZ
23998. DA9030_VIBRA_MODE_1P3V
23999. DA9030_VIBRA_MODE_2P7V
24000. DA9030_WLED_CONTROL
24001. DA9030_WLED_CP_EN
24002. DA9030_WLED_TRIM
24003. DA9034_ADTV1
24004. DA9034_ADTV2
24005. DA9034_AUTO_CTRL1
24006. DA9034_AUTO_CTRL2
24007. DA9034_AUTO_TSI_EN
24008. DA9034_AVRC
24009. DA9034_CDTV1
24010. DA9034_CDTV2
24011. DA9034_CHIP_ID
24012. DA9034_CVRC
24013. DA9034_DVC
24014. DA9034_EVENT_A
24015. DA9034_EVENT_ADC_AUTO4
24016. DA9034_EVENT_ADC_AUTO5
24017. DA9034_EVENT_ADC_AUTO6
24018. DA9034_EVENT_ADC_MAN
24019. DA9034_EVENT_B
24020. DA9034_EVENT_C
24021. DA9034_EVENT_CHDET
24022. DA9034_EVENT_CH_CCTO
24023. DA9034_EVENT_CH_IOVER
24024. DA9034_EVENT_CH_TCTO
24025. DA9034_EVENT_D
24026. DA9034_EVENT_EXTON
24027. DA9034_EVENT_HEADSET
24028. DA9034_EVENT_HOOKSWITCH
24029. DA9034_EVENT_ONKEY
24030. DA9034_EVENT_OTGCP_IOVER
24031. DA9034_EVENT_PEN_DOWN
24032. DA9034_EVENT_REV_IOVER
24033. DA9034_EVENT_SESS_1P8
24034. DA9034_EVENT_SRP_READY
24035. DA9034_EVENT_TBAT
24036. DA9034_EVENT_TSI_READY
24037. DA9034_EVENT_UART_RX
24038. DA9034_EVENT_UART_TX
24039. DA9034_EVENT_USB_DEV
24040. DA9034_EVENT_VBATMON
24041. DA9034_EVENT_VBUS_3P8
24042. DA9034_EVENT_VBUS_4P55
24043. DA9034_EVENT_WATCHDOG
24044. DA9034_FAULT_LOG
24045. DA9034_ID_BUCK1
24046. DA9034_ID_BUCK2
24047. DA9034_ID_LDO1
24048. DA9034_ID_LDO10
24049. DA9034_ID_LDO11
24050. DA9034_ID_LDO12
24051. DA9034_ID_LDO13
24052. DA9034_ID_LDO14
24053. DA9034_ID_LDO15
24054. DA9034_ID_LDO2
24055. DA9034_ID_LDO3
24056. DA9034_ID_LDO4
24057. DA9034_ID_LDO5
24058. DA9034_ID_LDO6
24059. DA9034_ID_LDO7
24060. DA9034_ID_LDO8
24061. DA9034_ID_LDO9
24062. DA9034_ID_LED_1
24063. DA9034_ID_LED_2
24064. DA9034_ID_TOUCH
24065. DA9034_ID_VIBRA
24066. DA9034_ID_WLED
24067. DA9034_INVAL
24068. DA9034_IRQ_MASK_A
24069. DA9034_IRQ_MASK_B
24070. DA9034_IRQ_MASK_C
24071. DA9034_IRQ_MASK_D
24072. DA9034_LDO
24073. DA9034_LDO1110
24074. DA9034_LDO1312
24075. DA9034_LDO1514
24076. DA9034_LDO643
24077. DA9034_LDO987
24078. DA9034_LDO_ADC_EN
24079. DA9034_LED1_CONTROL
24080. DA9034_LED2_CONTROL
24081. DA9034_LED_OFFSET
24082. DA9034_LED_RAMP
24083. DA9034_MANUAL_CTRL
24084. DA9034_MAX_BRIGHTNESS
24085. DA9034_MDTV1
24086. DA9034_MDTV2
24087. DA9034_MVRC
24088. DA9034_OVER1
24089. DA9034_OVER2
24090. DA9034_OVER3
24091. DA9034_PEN_DETECT
24092. DA9034_SDTV1
24093. DA9034_SDTV2
24094. DA9034_STATUS_A
24095. DA9034_STATUS_B
24096. DA9034_STATUS_CHDET
24097. DA9034_STATUS_EXTON
24098. DA9034_STATUS_HEADSET
24099. DA9034_STATUS_HOOKSWITCH
24100. DA9034_STATUS_MCLKDET
24101. DA9034_STATUS_ONKEY
24102. DA9034_STATUS_PEN_DOWN
24103. DA9034_STATUS_REMCON
24104. DA9034_STATUS_SESS_VALID_1P8
24105. DA9034_STATUS_SRP_READY
24106. DA9034_STATUS_TBAT
24107. DA9034_STATUS_USB_DEV
24108. DA9034_STATUS_VBATMON
24109. DA9034_STATUS_VBUS_VALID_3P8
24110. DA9034_STATUS_VBUS_VALID_4P55
24111. DA9034_SVRC
24112. DA9034_SYS_CTRL_A
24113. DA9034_SYS_CTRL_B
24114. DA9034_TSI_CTRL1
24115. DA9034_TSI_CTRL2
24116. DA9034_TSI_XY_LSB
24117. DA9034_TSI_X_MSB
24118. DA9034_TSI_Y_MSB
24119. DA9034_VCC1
24120. DA9034_VIBRA
24121. DA9034_WLED_BOOST_EN
24122. DA9034_WLED_CONTROL1
24123. DA9034_WLED_CONTROL2
24124. DA9034_WLED_ISET
24125. DA9035_3DTV1
24126. DA9035_3DTV2
24127. DA9035_3VRC
24128. DA9035_AUTOSKIP
24129. DA9035_DVC
24130. DA9035_ID_BUCK3
24131. DA9035_OVER3
24132. DA9035_VCC2
24133. DA903x_DVC
24134. DA903x_LDO
24135. DA9052
24136. DA9052_ACTIVE_HIGH
24137. DA9052_ACTIVE_LOW
24138. DA9052_ADCCONT_AD4ISRCEN
24139. DA9052_ADCCONT_ADCMODE
24140. DA9052_ADCCONT_AUTOAD4EN
24141. DA9052_ADCCONT_AUTOAD5EN
24142. DA9052_ADCCONT_AUTOAD6EN
24143. DA9052_ADCCONT_AUTOVDDEN
24144. DA9052_ADCCONT_COMP1V2EN
24145. DA9052_ADCCONT_TBATISRCEN
24146. DA9052_ADCIN4RES_ADCIN4RES
24147. DA9052_ADCIN4_RES_REG
24148. DA9052_ADCIN5RES_ADCIN5RES
24149. DA9052_ADCIN5_RES_REG
24150. DA9052_ADCIN6RES_ADCIN6RES
24151. DA9052_ADCIN6_RES_REG
24152. DA9052_ADCRESH_ADCRESMSB
24153. DA9052_ADC_CONT_REG
24154. DA9052_ADC_ICH
24155. DA9052_ADC_IN4
24156. DA9052_ADC_IN5
24157. DA9052_ADC_IN6
24158. DA9052_ADC_MAN_MAN_CONV
24159. DA9052_ADC_MAN_MUXSEL_AD4
24160. DA9052_ADC_MAN_MUXSEL_AD5
24161. DA9052_ADC_MAN_MUXSEL_AD6
24162. DA9052_ADC_MAN_MUXSEL_ICH
24163. DA9052_ADC_MAN_MUXSEL_TBAT
24164. DA9052_ADC_MAN_MUXSEL_VBAT
24165. DA9052_ADC_MAN_MUXSEL_VBBAT
24166. DA9052_ADC_MAN_MUXSEL_VDDOUT
24167. DA9052_ADC_MAN_REG
24168. DA9052_ADC_RES_H_REG
24169. DA9052_ADC_RES_LSB
24170. DA9052_ADC_RES_L_REG
24171. DA9052_ADC_TBAT
24172. DA9052_ADC_TJUNC
24173. DA9052_ADC_TSI
24174. DA9052_ADC_TSI_XN
24175. DA9052_ADC_TSI_XP
24176. DA9052_ADC_TSI_YN
24177. DA9052_ADC_TSI_YP
24178. DA9052_ADC_VBAT
24179. DA9052_ADC_VBBAT
24180. DA9052_ADC_VDDOUT
24181. DA9052_ALARMMI_ALARMTYPE
24182. DA9052_ALARMM_I_TICK_TYPE
24183. DA9052_ALARM_D_REG
24184. DA9052_ALARM_H_REG
24185. DA9052_ALARM_MI_REG
24186. DA9052_ALARM_MO_REG
24187. DA9052_ALARM_Y_ALARM_ON
24188. DA9052_ALARM_Y_REG
24189. DA9052_ALARM_Y_TICK_ON
24190. DA9052_AUTO4HIGH_AUTO4HIGH
24191. DA9052_AUTO4LOW_AUTO4LOW
24192. DA9052_AUTO4_HIGH_REG
24193. DA9052_AUTO4_LOW_REG
24194. DA9052_AUTO5HIGH_AUTOHIGH
24195. DA9052_AUTO5LOW_AUTO5LOW
24196. DA9052_AUTO5_HIGH_REG
24197. DA9052_AUTO5_LOW_REG
24198. DA9052_AUTO6HIGH_AUTO6HIGH
24199. DA9052_AUTO6LOW_AUTO6LOW
24200. DA9052_AUTO6_HIGH_REG
24201. DA9052_AUTO6_LOW_REG
24202. DA9052_AVG_SZ
24203. DA9052_BATCHG_ICHGBAT
24204. DA9052_BATCHG_ICHGPRE
24205. DA9052_BATCHG_REG
24206. DA9052_BAT_CUTOFF_VOLT
24207. DA9052_BAT_LOW_CAP
24208. DA9052_BAT_TSH
24209. DA9052_BBATCONT_BCHARGERISET
24210. DA9052_BBATCONT_BCHARGERVSET
24211. DA9052_BBAT_CONT_REG
24212. DA9052_BOOST_BOOSTEN
24213. DA9052_BOOST_BOOSTFRQ
24214. DA9052_BOOST_BOOSTILIM
24215. DA9052_BOOST_EBFAULT
24216. DA9052_BOOST_LED1INEN
24217. DA9052_BOOST_LED2INEN
24218. DA9052_BOOST_LED3INEN
24219. DA9052_BOOST_MBFAULT
24220. DA9052_BOOST_REG
24221. DA9052_BUCKA_BCOREILIM
24222. DA9052_BUCKA_BCOREMODE
24223. DA9052_BUCKA_BPROILIM
24224. DA9052_BUCKA_BPROMODE
24225. DA9052_BUCKA_REG
24226. DA9052_BUCKB_BERIILIM
24227. DA9052_BUCKB_BMEMILIM
24228. DA9052_BUCKB_BMEMMODE
24229. DA9052_BUCKB_BPERIMODE
24230. DA9052_BUCKB_REG
24231. DA9052_BUCKCORE_BCORECONF
24232. DA9052_BUCKCORE_BCOREEN
24233. DA9052_BUCKCORE_REG
24234. DA9052_BUCKCORE_VBCORE
24235. DA9052_BUCKMEM_BMEMCONF
24236. DA9052_BUCKMEM_BMEMEN
24237. DA9052_BUCKMEM_REG
24238. DA9052_BUCKMEM_VBMEM
24239. DA9052_BUCKPERI_BPERICONF
24240. DA9052_BUCKPERI_BPERIEN
24241. DA9052_BUCKPERI_BPERIHS
24242. DA9052_BUCKPERI_REG
24243. DA9052_BUCKPERI_VBPERI
24244. DA9052_BUCKPRO_BPROCONF
24245. DA9052_BUCKPRO_BPROEN
24246. DA9052_BUCKPRO_REG
24247. DA9052_BUCKPRO_VBPRO
24248. DA9052_BUCK_ILIM_MASK_EVEN
24249. DA9052_BUCK_ILIM_MASK_ODD
24250. DA9052_BUCK_PERI_3uV_STEP
24251. DA9052_BUCK_PERI_REG_MAP_UPTO_3uV
24252. DA9052_CHARGER
24253. DA9052_CHGBUCK_CHGBUCKEN
24254. DA9052_CHGBUCK_CHGBUCKLP
24255. DA9052_CHGBUCK_CHGTEMP
24256. DA9052_CHGBUCK_CHGUSBILIM
24257. DA9052_CHGBUCK_ISETBUCK
24258. DA9052_CHGBUCK_REG
24259. DA9052_CHGTIME_CHGTIME
24260. DA9052_CHG_CONT_REG
24261. DA9052_CHG_CONT_TCTR
24262. DA9052_CHG_CONT_VCHG_BAT
24263. DA9052_CHG_LIM_COLS
24264. DA9052_CHG_TIME_REG
24265. DA9052_CHG_USB_ILIM_MASK
24266. DA9052_CONST_3uV
24267. DA9052_CONTROLA_GPIV
24268. DA9052_CONTROLA_PMIFV
24269. DA9052_CONTROLA_PMIV
24270. DA9052_CONTROLA_PMOTYPE
24271. DA9052_CONTROLA_PMOV
24272. DA9052_CONTROLA_PWR1EN
24273. DA9052_CONTROLA_PWREN
24274. DA9052_CONTROLA_SYSEN
24275. DA9052_CONTROLB_ACTDIODE
24276. DA9052_CONTROLB_AUTOBOOT
24277. DA9052_CONTROLB_BBATEN
24278. DA9052_CONTROLB_BUCKMERGE
24279. DA9052_CONTROLB_DEEPSLEEP
24280. DA9052_CONTROLB_OTPREADEN
24281. DA9052_CONTROLB_SHUTDOWN
24282. DA9052_CONTROLC_BLINKDUR
24283. DA9052_CONTROLC_BLINKFRQ
24284. DA9052_CONTROLC_DEBOUNCING
24285. DA9052_CONTROLC_PMFB1PIN
24286. DA9052_CONTROLC_PMFB2PIN
24287. DA9052_CONTROLD_ACCDETEN
24288. DA9052_CONTROLD_GPI1415SD
24289. DA9052_CONTROLD_KEEPACTEN
24290. DA9052_CONTROLD_NONKEYSD
24291. DA9052_CONTROLD_TWDSCALE
24292. DA9052_CONTROLD_WATCHDOG
24293. DA9052_CONTROL_A_REG
24294. DA9052_CONTROL_B_REG
24295. DA9052_CONTROL_B_WRITEMODE
24296. DA9052_CONTROL_C_REG
24297. DA9052_CONTROL_D_REG
24298. DA9052_COUNTS_MONITOR
24299. DA9052_COUNT_D_REG
24300. DA9052_COUNT_H_REG
24301. DA9052_COUNT_MI_REG
24302. DA9052_COUNT_MO_REG
24303. DA9052_COUNT_S_REG
24304. DA9052_COUNT_Y_REG
24305. DA9052_CURRENT_RANGE
24306. DA9052_DCDC
24307. DA9052_DEBOUNCING_OFF
24308. DA9052_DEBOUNCING_ON
24309. DA9052_DEF_TIMEOUT
24310. DA9052_EVENTA_EALRAM
24311. DA9052_EVENTA_ECOMP1V2
24312. DA9052_EVENTA_EDCINDET
24313. DA9052_EVENTA_EDCINREM
24314. DA9052_EVENTA_ESEQRDY
24315. DA9052_EVENTA_EVBUSDET
24316. DA9052_EVENTA_EVBUSREM
24317. DA9052_EVENTA_EVDDLOW
24318. DA9052_EVENTB_EADCEOM
24319. DA9052_EVENTB_ECHGEND
24320. DA9052_EVENTB_EIDFLOAT
24321. DA9052_EVENTB_EIDGND
24322. DA9052_EVENTB_ENONKEY
24323. DA9052_EVENTB_EPENDOWN
24324. DA9052_EVENTB_ETBAT
24325. DA9052_EVENTB_ETSIREADY
24326. DA9052_EVENTC_EGPI0
24327. DA9052_EVENTC_EGPI1
24328. DA9052_EVENTC_EGPI2
24329. DA9052_EVENTC_EGPI3
24330. DA9052_EVENTC_EGPI4
24331. DA9052_EVENTC_EGPI5
24332. DA9052_EVENTC_EGPI6
24333. DA9052_EVENTC_EGPI7
24334. DA9052_EVENTD_EGPI10
24335. DA9052_EVENTD_EGPI11
24336. DA9052_EVENTD_EGPI12
24337. DA9052_EVENTD_EGPI13
24338. DA9052_EVENTD_EGPI14
24339. DA9052_EVENTD_EGPI15
24340. DA9052_EVENTD_EGPI8
24341. DA9052_EVENTD_EGPI9
24342. DA9052_EVENT_A_REG
24343. DA9052_EVENT_B_REG
24344. DA9052_EVENT_C_REG
24345. DA9052_EVENT_D_REG
24346. DA9052_E_PEN_DOWN
24347. DA9052_E_TSI_READY
24348. DA9052_FAULTLOG_KEYSHUT
24349. DA9052_FAULTLOG_NSDSET
24350. DA9052_FAULTLOG_REG
24351. DA9052_FAULTLOG_TEMPOVER
24352. DA9052_FAULTLOG_TWDERROR
24353. DA9052_FAULTLOG_VDDFAULT
24354. DA9052_FAULTLOG_VDDSTART
24355. DA9052_FAULTLOG_WAITSET
24356. DA9052_GET_TIME_RETRIES
24357. DA9052_GPIO_0_1_REG
24358. DA9052_GPIO_10_11_REG
24359. DA9052_GPIO_12_13_REG
24360. DA9052_GPIO_14_15_REG
24361. DA9052_GPIO_2_3_REG
24362. DA9052_GPIO_4_5_REG
24363. DA9052_GPIO_6_7_REG
24364. DA9052_GPIO_8_9_REG
24365. DA9052_GPIO_EVEN_PORT_MODE
24366. DA9052_GPIO_EVEN_PORT_PIN
24367. DA9052_GPIO_EVEN_PORT_TYPE
24368. DA9052_GPIO_EVEN_SHIFT
24369. DA9052_GPIO_MASK_LOWER_NIBBLE
24370. DA9052_GPIO_MASK_UPPER_NIBBLE
24371. DA9052_GPIO_MAX_PORTS_PER_REGISTER
24372. DA9052_GPIO_NIBBLE_SHIFT
24373. DA9052_GPIO_ODD_PORT_MODE
24374. DA9052_GPIO_ODD_PORT_PIN
24375. DA9052_GPIO_ODD_PORT_TYPE
24376. DA9052_GPIO_ODD_SHIFT
24377. DA9052_GPIO_SHIFT_COUNT
24378. DA9052_ICHGAV_ICHGAV
24379. DA9052_ICHGEND_ICHGEND
24380. DA9052_ICHGTHD_ICHGTHD
24381. DA9052_ICHG_AV_REG
24382. DA9052_ICHG_END_REG
24383. DA9052_ICHG_THD_REG
24384. DA9052_ID01_DEFSUPPLY
24385. DA9052_ID01_LDO1STEP
24386. DA9052_ID01_NRESMODE
24387. DA9052_ID01_SYSPRE
24388. DA9052_ID1011_LDO10STEP
24389. DA9052_ID1011_PDDISSTEP
24390. DA9052_ID1213_VMEMSWSTEP
24391. DA9052_ID1213_VPERISWSTEP
24392. DA9052_ID1415_BUCKCORESTEP
24393. DA9052_ID1415_BUCKPROSTEP
24394. DA9052_ID1617_BUCKMEMSTEP
24395. DA9052_ID1617_BUCKPERISTEP
24396. DA9052_ID1819_GPRISE1STEP
24397. DA9052_ID1819_GPRISE2STEP
24398. DA9052_ID2021_GPFALL1STEP
24399. DA9052_ID2021_GPFALL2STEP
24400. DA9052_ID23_LDO2STEP
24401. DA9052_ID23_LDO3STEP
24402. DA9052_ID45_LDO4STEP
24403. DA9052_ID45_LDO5STEP
24404. DA9052_ID67_LDO6STEP
24405. DA9052_ID67_LDO7STEP
24406. DA9052_ID89_LDO8STEP
24407. DA9052_ID89_LDO9STEP
24408. DA9052_ID_0_1_REG
24409. DA9052_ID_10_11_REG
24410. DA9052_ID_12_13_REG
24411. DA9052_ID_14_15_REG
24412. DA9052_ID_16_17_REG
24413. DA9052_ID_18_19_REG
24414. DA9052_ID_20_21_REG
24415. DA9052_ID_2_3_REG
24416. DA9052_ID_4_5_REG
24417. DA9052_ID_6_7_REG
24418. DA9052_ID_8_9_REG
24419. DA9052_ID_BUCK1
24420. DA9052_ID_BUCK2
24421. DA9052_ID_BUCK3
24422. DA9052_ID_BUCK4
24423. DA9052_ID_LDO1
24424. DA9052_ID_LDO10
24425. DA9052_ID_LDO2
24426. DA9052_ID_LDO3
24427. DA9052_ID_LDO4
24428. DA9052_ID_LDO5
24429. DA9052_ID_LDO6
24430. DA9052_ID_LDO7
24431. DA9052_ID_LDO8
24432. DA9052_ID_LDO9
24433. DA9052_INPUT
24434. DA9052_INPUT_CONT_DCIN_SUSP
24435. DA9052_INPUT_CONT_REG
24436. DA9052_INPUT_CONT_TCTR_MODE
24437. DA9052_INPUT_CONT_VBUS_SUSP
24438. DA9052_INTERFACE_CPHA
24439. DA9052_INTERFACE_CPOL
24440. DA9052_INTERFACE_IFBASEADDR
24441. DA9052_INTERFACE_IFTYPE
24442. DA9052_INTERFACE_NCSPOL
24443. DA9052_INTERFACE_REG
24444. DA9052_INTERFACE_RWPOL
24445. DA9052_IRQ_ADC_EOM
24446. DA9052_IRQ_ALARM
24447. DA9052_IRQ_CHGEND
24448. DA9052_IRQ_COMP1V2
24449. DA9052_IRQ_DCIN
24450. DA9052_IRQ_DCINREM
24451. DA9052_IRQ_GPI0
24452. DA9052_IRQ_GPI1
24453. DA9052_IRQ_GPI10
24454. DA9052_IRQ_GPI11
24455. DA9052_IRQ_GPI12
24456. DA9052_IRQ_GPI13
24457. DA9052_IRQ_GPI14
24458. DA9052_IRQ_GPI15
24459. DA9052_IRQ_GPI2
24460. DA9052_IRQ_GPI3
24461. DA9052_IRQ_GPI4
24462. DA9052_IRQ_GPI5
24463. DA9052_IRQ_GPI6
24464. DA9052_IRQ_GPI7
24465. DA9052_IRQ_GPI8
24466. DA9052_IRQ_GPI9
24467. DA9052_IRQ_IDFLOAT
24468. DA9052_IRQ_IDGND
24469. DA9052_IRQ_MASK_A_REG
24470. DA9052_IRQ_MASK_B_REG
24471. DA9052_IRQ_MASK_C_REG
24472. DA9052_IRQ_MASK_D_REG
24473. DA9052_IRQ_MASK_POS_1
24474. DA9052_IRQ_MASK_POS_2
24475. DA9052_IRQ_MASK_POS_3
24476. DA9052_IRQ_MASK_POS_4
24477. DA9052_IRQ_MASK_POS_5
24478. DA9052_IRQ_MASK_POS_6
24479. DA9052_IRQ_MASK_POS_7
24480. DA9052_IRQ_MASK_POS_8
24481. DA9052_IRQ_NONKEY
24482. DA9052_IRQ_PENDOWN
24483. DA9052_IRQ_SEQRDY
24484. DA9052_IRQ_TBAT
24485. DA9052_IRQ_TSIREADY
24486. DA9052_IRQ_VBUS
24487. DA9052_IRQ_VBUSREM
24488. DA9052_IRQ_VDDLOW
24489. DA9052_ISET_ISETDCIN
24490. DA9052_ISET_ISETVBUS
24491. DA9052_ISET_REG
24492. DA9052_ISET_USB_MASK
24493. DA9052_LDO
24494. DA9052_LDO10_LDO10CONF
24495. DA9052_LDO10_LDO10EN
24496. DA9052_LDO10_REG
24497. DA9052_LDO10_VLDO10
24498. DA9052_LDO1_LDO1CONF
24499. DA9052_LDO1_LDO1EN
24500. DA9052_LDO1_REG
24501. DA9052_LDO1_VLDO1
24502. DA9052_LDO2_LDO2CONF
24503. DA9052_LDO2_LDO2EN
24504. DA9052_LDO2_REG
24505. DA9052_LDO2_VLDO2
24506. DA9052_LDO3_LDO3CONF
24507. DA9052_LDO3_LDO3EN
24508. DA9052_LDO3_REG
24509. DA9052_LDO3_VLDO3
24510. DA9052_LDO4_LDO4CONF
24511. DA9052_LDO4_LDO4EN
24512. DA9052_LDO4_REG
24513. DA9052_LDO4_VLDO4
24514. DA9052_LDO5_LDO5CONF
24515. DA9052_LDO5_LDO5EN
24516. DA9052_LDO5_REG
24517. DA9052_LDO5_VLDO5
24518. DA9052_LDO6_LDO6CONF
24519. DA9052_LDO6_LDO6EN
24520. DA9052_LDO6_REG
24521. DA9052_LDO6_VLDO6
24522. DA9052_LDO7_LDO7CONF
24523. DA9052_LDO7_LDO7EN
24524. DA9052_LDO7_REG
24525. DA9052_LDO7_VLDO7
24526. DA9052_LDO8_LDO8CONF
24527. DA9052_LDO8_LDO8EN
24528. DA9052_LDO8_REG
24529. DA9052_LDO8_VLDO8
24530. DA9052_LDO9_LDO9CONF
24531. DA9052_LDO9_LDO9EN
24532. DA9052_LDO9_REG
24533. DA9052_LDO9_VLDO9
24534. DA9052_LED1CONF_LED1CURRENT
24535. DA9052_LED1CONT_REG
24536. DA9052_LED1_CONF_REG
24537. DA9052_LED2CONF_LED2CURRENT
24538. DA9052_LED2CONT_REG
24539. DA9052_LED2_CONF_REG
24540. DA9052_LED3CONF_LED3CURRENT
24541. DA9052_LED3CONT_REG
24542. DA9052_LED3_CONF_REG
24543. DA9052_LEDCONT_LED1EN
24544. DA9052_LEDCONT_LED1RAMP
24545. DA9052_LEDCONT_LED2EN
24546. DA9052_LEDCONT_LED2RAMP
24547. DA9052_LEDCONT_LED3EN
24548. DA9052_LEDCONT_LED3ICONT
24549. DA9052_LEDCONT_LED3RAMP
24550. DA9052_LEDCONT_SELLEDMODE
24551. DA9052_LEDMIN123_LEDMINCURRENT
24552. DA9052_LEDMIN123_REG
24553. DA9052_LED_CONT_4_REG
24554. DA9052_LED_CONT_5_REG
24555. DA9052_LED_CONT_DIM
24556. DA9052_LED_CONT_REG
24557. DA9052_MASK_LOWER_NIBBLE
24558. DA9052_MASK_UPPER_NIBBLE
24559. DA9052_MAX_BRIGHTNESS
24560. DA9052_MAX_REGULATORS
24561. DA9052_MAX_UA
24562. DA9052_MEAN
24563. DA9052_MIN_UA
24564. DA9052_M_NONKEY
24565. DA9052_NIBBLE_SHIFT
24566. DA9052_NOCHARGER
24567. DA9052_NUM_IRQ_REGS
24568. DA9052_OPENDRAIN_OUTPUT
24569. DA9052_OUTPUT_LOWLEVEL
24570. DA9052_OUTPUT_OPENDRAIN
24571. DA9052_OUTPUT_PUSHPULL
24572. DA9052_PAGE0_CON_REG
24573. DA9052_PAGE1_CON_REG
24574. DA9052_PAGE_CONF
24575. DA9052_PARK_REGISTER
24576. DA9052_PDDIS_CHGBBATPD
24577. DA9052_PDDIS_CHGPD
24578. DA9052_PDDIS_GPADCPD
24579. DA9052_PDDIS_GPIOPD
24580. DA9052_PDDIS_HS2WIREPD
24581. DA9052_PDDIS_OUT32KPD
24582. DA9052_PDDIS_PMCONTPD
24583. DA9052_PDDIS_PMIFPD
24584. DA9052_PDDIS_REG
24585. DA9052_PULLDOWN_COREPDDIS
24586. DA9052_PULLDOWN_LDO1PDDIS
24587. DA9052_PULLDOWN_LDO2PDDIS
24588. DA9052_PULLDOWN_LDO5PDDIS
24589. DA9052_PULLDOWN_MEMPDDIS
24590. DA9052_PULLDOWN_PROPDDIS
24591. DA9052_PULLDOWN_REG
24592. DA9052_RESET_REG
24593. DA9052_RESET_RESETEVENT
24594. DA9052_RESET_RESETTIMER
24595. DA9052_RTC_DAY
24596. DA9052_RTC_HOUR
24597. DA9052_RTC_MIN
24598. DA9052_RTC_MONTH
24599. DA9052_RTC_SEC
24600. DA9052_RTC_YEAR
24601. DA9052_SECONDA_SECONDSA
24602. DA9052_SECONDB_SECONDSB
24603. DA9052_SECONDC_SECONDSC
24604. DA9052_SECONDD_SECONDSD
24605. DA9052_SECOND_A_REG
24606. DA9052_SECOND_B_REG
24607. DA9052_SECOND_C_REG
24608. DA9052_SECOND_D_REG
24609. DA9052_SEQA_POWEREND
24610. DA9052_SEQA_SYSTEMEND
24611. DA9052_SEQB_MAXCOUNT
24612. DA9052_SEQB_PARTDOWN
24613. DA9052_SEQSTATUS_SEQPOINTER
24614. DA9052_SEQSTATUS_WAITSTEP
24615. DA9052_SEQTIMER_SEQDUMMY
24616. DA9052_SEQTIMER_SEQTIME
24617. DA9052_SEQ_A_REG
24618. DA9052_SEQ_B_REG
24619. DA9052_SEQ_STATUS_REG
24620. DA9052_SEQ_TIMER_REG
24621. DA9052_SET_HIGH_LVL_OUTPUT
24622. DA9052_STATUSA_DCINDET
24623. DA9052_STATUSA_DCINSEL
24624. DA9052_STATUSA_IDFLOAT
24625. DA9052_STATUSA_IDGND
24626. DA9052_STATUSA_NONKEY
24627. DA9052_STATUSA_VBUSDET
24628. DA9052_STATUSA_VBUSSEL
24629. DA9052_STATUSA_VDATDET
24630. DA9052_STATUSB_CHGATT
24631. DA9052_STATUSB_CHGEND
24632. DA9052_STATUSB_CHGLIM
24633. DA9052_STATUSB_CHGPRE
24634. DA9052_STATUSB_CHGTO
24635. DA9052_STATUSB_COMPDET
24636. DA9052_STATUSB_GPFB2
24637. DA9052_STATUSB_SEQUENCING
24638. DA9052_STATUSC_GPI0
24639. DA9052_STATUSC_GPI1
24640. DA9052_STATUSC_GPI2
24641. DA9052_STATUSC_GPI3
24642. DA9052_STATUSC_GPI4
24643. DA9052_STATUSC_GPI5
24644. DA9052_STATUSC_GPI6
24645. DA9052_STATUSC_GPI7
24646. DA9052_STATUSD_GPI10
24647. DA9052_STATUSD_GPI11
24648. DA9052_STATUSD_GPI12
24649. DA9052_STATUSD_GPI13
24650. DA9052_STATUSD_GPI14
24651. DA9052_STATUSD_GPI15
24652. DA9052_STATUSD_GPI8
24653. DA9052_STATUSD_GPI9
24654. DA9052_STATUS_A_REG
24655. DA9052_STATUS_B_REG
24656. DA9052_STATUS_C_REG
24657. DA9052_STATUS_D_REG
24658. DA9052_SUPPLY_REG
24659. DA9052_SUPPLY_VBCOREGO
24660. DA9052_SUPPLY_VBMEMGO
24661. DA9052_SUPPLY_VBPROGO
24662. DA9052_SUPPLY_VDD_IO1
24663. DA9052_SUPPLY_VLDO2GO
24664. DA9052_SUPPLY_VLDO3GO
24665. DA9052_SUPPLY_VLOCK
24666. DA9052_SUPPLY_VMEMSWEN
24667. DA9052_SUPPLY_VPERISWEN
24668. DA9052_TBATHIGHN_TBATHIGHN
24669. DA9052_TBATHIGHP_TBATHIGHP
24670. DA9052_TBATLOW_TBATLOW
24671. DA9052_TBATRES_TBATRES
24672. DA9052_TBAT_HIGHN_REG
24673. DA9052_TBAT_HIGHP_REG
24674. DA9052_TBAT_LOW_REG
24675. DA9052_TBAT_RES_REG
24676. DA9052_TJUNCRES_TJUNCRES
24677. DA9052_TJUNC_RES_REG
24678. DA9052_TOFFSET_TOFFSET
24679. DA9052_TSICONTA_AUTOTSIEN
24680. DA9052_TSICONTA_PENDETEN
24681. DA9052_TSICONTA_TSIDELAY
24682. DA9052_TSICONTA_TSIMODE
24683. DA9052_TSICONTA_TSISKIP
24684. DA9052_TSICONTB_ADCREF
24685. DA9052_TSICONTB_TSIMAN
24686. DA9052_TSICONTB_TSIMUX_XN
24687. DA9052_TSICONTB_TSIMUX_XP
24688. DA9052_TSICONTB_TSIMUX_YN
24689. DA9052_TSICONTB_TSIMUX_YP
24690. DA9052_TSICONTB_TSISEL0
24691. DA9052_TSICONTB_TSISEL1
24692. DA9052_TSICONTB_TSISEL2
24693. DA9052_TSICONTB_TSISEL3
24694. DA9052_TSILSB_PENDOWN
24695. DA9052_TSILSB_TSIXL
24696. DA9052_TSILSB_TSIXL_BITS
24697. DA9052_TSILSB_TSIXL_SHIFT
24698. DA9052_TSILSB_TSIYL
24699. DA9052_TSILSB_TSIYL_BITS
24700. DA9052_TSILSB_TSIYL_SHIFT
24701. DA9052_TSILSB_TSIZL
24702. DA9052_TSILSB_TSIZL_BITS
24703. DA9052_TSILSB_TSIZL_SHIFT
24704. DA9052_TSIXMSB_TSIXM
24705. DA9052_TSIYMSB_TSIYM
24706. DA9052_TSIZMSB_TSIZM
24707. DA9052_TSI_CONT_A_REG
24708. DA9052_TSI_CONT_B_REG
24709. DA9052_TSI_LSB_REG
24710. DA9052_TSI_X_MSB_REG
24711. DA9052_TSI_Y_MSB_REG
24712. DA9052_TSI_Z_MSB_REG
24713. DA9052_TWDMIN
24714. DA9052_TYPE_WLED1
24715. DA9052_TYPE_WLED2
24716. DA9052_TYPE_WLED3
24717. DA9052_T_OFFSET_REG
24718. DA9052_VC_TBL_REF_SZ
24719. DA9052_VC_TBL_SZ
24720. DA9052_VDDMON_VDDOUTMON
24721. DA9052_VDDRES_VDDOUTRES
24722. DA9052_VDD_MON_REG
24723. DA9052_VDD_RES_REG
24724. DA9052_WAITCONT_DELAYTIME
24725. DA9052_WAITCONT_EN32KOUT
24726. DA9052_WAITCONT_REG
24727. DA9052_WAITCONT_RTCCLOCK
24728. DA9052_WAITCONT_WAITDIR
24729. DA9052_WAITCONT_WAITMODE
24730. DA9052_WLEDS_OFF
24731. DA9052_WLEDS_ON
24732. DA9053_AA
24733. DA9053_BA
24734. DA9053_BB
24735. DA9053_BC
24736. DA9055_ACT_LOW
24737. DA9055_AD1_ISRC_MASK
24738. DA9055_AD1_ISRC_SHIFT
24739. DA9055_ADCIN_DIV
24740. DA9055_ADC_ADCIN1
24741. DA9055_ADC_ADCIN1_DEB_SHIFT
24742. DA9055_ADC_ADCIN2
24743. DA9055_ADC_ADCIN2_DEB_SHIFT
24744. DA9055_ADC_ADCIN3
24745. DA9055_ADC_ADCIN3_DEB_SHIFT
24746. DA9055_ADC_AUTO_AD1_EN_SHIFT
24747. DA9055_ADC_AUTO_AD2_EN_SHIFT
24748. DA9055_ADC_AUTO_AD3_EN_SHIFT
24749. DA9055_ADC_AUTO_VSYS_EN_SHIFT
24750. DA9055_ADC_FILTERS1
24751. DA9055_ADC_ISRC_EN_SHIFT
24752. DA9055_ADC_LSB_MASK
24753. DA9055_ADC_L_CTRL
24754. DA9055_ADC_L_EN
24755. DA9055_ADC_L_GAIN
24756. DA9055_ADC_L_GAIN_STATUS
24757. DA9055_ADC_MAN_CONV
24758. DA9055_ADC_MAN_SHIFT
24759. DA9055_ADC_MODE_1MS
24760. DA9055_ADC_MODE_MASK
24761. DA9055_ADC_MODE_SHIFT
24762. DA9055_ADC_MUX_ADCIN1
24763. DA9055_ADC_MUX_ADCIN2
24764. DA9055_ADC_MUX_ADCIN3
24765. DA9055_ADC_MUX_MASK
24766. DA9055_ADC_MUX_SHIFT
24767. DA9055_ADC_MUX_T_SENSE
24768. DA9055_ADC_MUX_VSYS
24769. DA9055_ADC_RDY_EINT
24770. DA9055_ADC_R_CTRL
24771. DA9055_ADC_R_EN
24772. DA9055_ADC_R_GAIN
24773. DA9055_ADC_R_GAIN_STATUS
24774. DA9055_ADC_STEPS
24775. DA9055_ADC_TJUNC
24776. DA9055_ADC_VAL_BASE
24777. DA9055_ADC_VAL_MASK
24778. DA9055_ADC_VAL_MAX
24779. DA9055_ADC_VAL_SHIFT
24780. DA9055_ADC_VOLT_BASE
24781. DA9055_ADC_VOLT_INC
24782. DA9055_ADC_VSYS
24783. DA9055_ADC_VSYS_VOLT_BASE
24784. DA9055_ADC_VSYS_VOLT_INC
24785. DA9055_AIF_BCLKS_PER_WCLK_128
24786. DA9055_AIF_BCLKS_PER_WCLK_256
24787. DA9055_AIF_BCLKS_PER_WCLK_32
24788. DA9055_AIF_BCLKS_PER_WCLK_64
24789. DA9055_AIF_BCLK_MASK
24790. DA9055_AIF_CLK_EN_MASTER_MODE
24791. DA9055_AIF_CLK_EN_SLAVE_MODE
24792. DA9055_AIF_CLK_MODE
24793. DA9055_AIF_CLK_MODE_MASK
24794. DA9055_AIF_CTRL
24795. DA9055_AIF_FORMAT_DSP
24796. DA9055_AIF_FORMAT_I2S_MODE
24797. DA9055_AIF_FORMAT_LEFT_J
24798. DA9055_AIF_FORMAT_MASK
24799. DA9055_AIF_FORMAT_RIGHT_J
24800. DA9055_AIF_OFFSET
24801. DA9055_AIF_WORD_LENGTH_MASK
24802. DA9055_AIF_WORD_S16_LE
24803. DA9055_AIF_WORD_S20_3LE
24804. DA9055_AIF_WORD_S24_LE
24805. DA9055_AIF_WORD_S32_LE
24806. DA9055_ALARAM_TICK_WAKE
24807. DA9055_ALARM_EINT
24808. DA9055_ALARM_STATUS_BOTH
24809. DA9055_ALARM_STATUS_MASK
24810. DA9055_ALARM_STATUS_NO_ALARM
24811. DA9055_ALARM_STATUS_SHIFT
24812. DA9055_ALARM_STATUS_TICK
24813. DA9055_ALARM_STATUS_TIMER_ALARM
24814. DA9055_ALC_ANA_GAIN_LIMITS
24815. DA9055_ALC_ANTICLIP_CTRL
24816. DA9055_ALC_ANTICLIP_LEVEL
24817. DA9055_ALC_AVG_ITERATIONS
24818. DA9055_ALC_CIC_OP_CHANNEL_LEFT
24819. DA9055_ALC_CIC_OP_CHANNEL_RIGHT
24820. DA9055_ALC_CIC_OP_LVL_CTRL
24821. DA9055_ALC_CIC_OP_LVL_DATA
24822. DA9055_ALC_CTRL1
24823. DA9055_ALC_CTRL2
24824. DA9055_ALC_CTRL3
24825. DA9055_ALC_DATA_MIDDLE
24826. DA9055_ALC_DATA_TOP
24827. DA9055_ALC_GAIN_LIMITS
24828. DA9055_ALC_NOISE
24829. DA9055_ALC_OFFSET_15_8
24830. DA9055_ALC_OFFSET_17_16
24831. DA9055_ALC_OFFSET_OP2M_L
24832. DA9055_ALC_OFFSET_OP2M_R
24833. DA9055_ALC_OFFSET_OP2U_L
24834. DA9055_ALC_OFFSET_OP2U_R
24835. DA9055_ALC_TARGET_MAX
24836. DA9055_ALC_TARGET_MIN
24837. DA9055_AUTO_BOOT_MASK
24838. DA9055_AUTO_BOOT_SHIFT
24839. DA9055_AUX_L_CTRL
24840. DA9055_AUX_L_GAIN
24841. DA9055_AUX_L_GAIN_STATUS
24842. DA9055_AUX_R_CTRL
24843. DA9055_AUX_R_GAIN
24844. DA9055_AUX_R_GAIN_STATUS
24845. DA9055_BCMEM_SL_SLEEP
24846. DA9055_BCMEM_SL_SYNCHRO
24847. DA9055_BCORE_CLK_INV_SHIFT
24848. DA9055_BCORE_CONF_MASK
24849. DA9055_BCORE_CONF_SHIFT
24850. DA9055_BCORE_DEF_SHIFT
24851. DA9055_BCORE_EN_MASK
24852. DA9055_BCORE_EN_SHIFT
24853. DA9055_BCORE_GPI_MASK
24854. DA9055_BCORE_GPI_SHIFT
24855. DA9055_BCORE_ILIM_SHIFT
24856. DA9055_BCORE_MODE_SHIFT
24857. DA9055_BCORE_MON_EN_SHIFT
24858. DA9055_BCORE_PD_DIS_MASK
24859. DA9055_BCORE_PD_DIS_SHIFT
24860. DA9055_BCORE_SL_SLEEP
24861. DA9055_BCORE_SL_SYNCHRO
24862. DA9055_BIAS_EN
24863. DA9055_BMEM_CLK_INV_SHIFT
24864. DA9055_BMEM_CONF_MASK
24865. DA9055_BMEM_CONF_SHIFT
24866. DA9055_BMEM_DEF_SHIFT
24867. DA9055_BMEM_EN_MASK
24868. DA9055_BMEM_EN_SHIFT
24869. DA9055_BMEM_GPI_MASK
24870. DA9055_BMEM_GPI_SHIFT
24871. DA9055_BMEM_ILIM_SHIFT
24872. DA9055_BMEM_MODE_SHIFT
24873. DA9055_BMEM_MON_EN_SHIFT
24874. DA9055_BMEM_PD_DIS_MASK
24875. DA9055_BMEM_PD_DIS_SHIFT
24876. DA9055_BUCK
24877. DA9055_BUCK_MODE_AUTO
24878. DA9055_BUCK_MODE_SLEEP
24879. DA9055_BUCK_MODE_SYNC
24880. DA9055_CIF_CTRL
24881. DA9055_CLKSRC_MCLK
24882. DA9055_COMP1V2_EN_SHIFT
24883. DA9055_COMP1V2_STS
24884. DA9055_CP_CTRL
24885. DA9055_CP_DELAY
24886. DA9055_CP_DETECTOR
24887. DA9055_CP_VOL_THRESHOLD1
24888. DA9055_CRYSTAL_EN
24889. DA9055_DAC_FILTERS1
24890. DA9055_DAC_FILTERS2
24891. DA9055_DAC_FILTERS3
24892. DA9055_DAC_FILTERS4
24893. DA9055_DAC_FILTERS5
24894. DA9055_DAC_L_CTRL
24895. DA9055_DAC_L_GAIN
24896. DA9055_DAC_L_GAIN_STATUS
24897. DA9055_DAC_L_MUTE_EN
24898. DA9055_DAC_NG_CTRL
24899. DA9055_DAC_NG_OFF_THRESHOLD
24900. DA9055_DAC_NG_ON_THRESHOLD
24901. DA9055_DAC_NG_SETUP_TIME
24902. DA9055_DAC_R_CTRL
24903. DA9055_DAC_R_GAIN
24904. DA9055_DAC_R_GAIN_STATUS
24905. DA9055_DAC_R_MUTE_EN
24906. DA9055_DEBOUNCING_MASK
24907. DA9055_DEBOUNCING_SHIFT
24908. DA9055_DEF_TIMEOUT
24909. DA9055_DELAY_MODE_EN
24910. DA9055_DIG_CTRL
24911. DA9055_DIG_ROUTING_AIF
24912. DA9055_DIG_ROUTING_DAC
24913. DA9055_DVC_BUSY_STS
24914. DA9055_ECO_MODE_MASK
24915. DA9055_ECO_MODE_SHIFT
24916. DA9055_EN_32KOUT_BUF
24917. DA9055_EVENTS_B_EINT
24918. DA9055_EVENTS_C_EINT
24919. DA9055_E_COMP1V2_EINT
24920. DA9055_E_GPI0_EINT
24921. DA9055_E_GPI1_EINT
24922. DA9055_E_GPI2_EINT
24923. DA9055_E_GPI_MASK
24924. DA9055_E_GPI_SHIFT
24925. DA9055_E_LDO_LIM_EINT
24926. DA9055_E_NJIG_EINT
24927. DA9055_E_TEMP_EINT
24928. DA9055_E_VDD_MON_EINT
24929. DA9055_E_VDD_WARN_EINT
24930. DA9055_E_WAKE_EINT
24931. DA9055_FORMATS
24932. DA9055_GAIN_RAMPING_EN
24933. DA9055_GAIN_RAMP_CTRL
24934. DA9055_GPI
24935. DA9055_GPI0_STS
24936. DA9055_GPI1_STS
24937. DA9055_GPI2_STS
24938. DA9055_GPIO0_MODE_MASK
24939. DA9055_GPIO0_MODE_SHIFT
24940. DA9055_GPIO0_PIN_MASK
24941. DA9055_GPIO0_PIN_SHIFT
24942. DA9055_GPIO0_PUPD_SHIFT
24943. DA9055_GPIO0_TYPE_MASK
24944. DA9055_GPIO0_TYPE_SHIFT
24945. DA9055_GPIO0_WEN_MASK
24946. DA9055_GPIO0_WEN_SHIFT
24947. DA9055_GPIO1_MODE_MASK
24948. DA9055_GPIO1_MODE_SHIFT
24949. DA9055_GPIO1_PIN_MASK
24950. DA9055_GPIO1_PIN_SHIFT
24951. DA9055_GPIO1_PUPD_SHIFT
24952. DA9055_GPIO1_TYPE_MASK
24953. DA9055_GPIO1_TYPE_SHIFT
24954. DA9055_GPIO1_WEN_MASK
24955. DA9055_GPIO1_WEN_SHIFT
24956. DA9055_GPIO2_MODE_MASK
24957. DA9055_GPIO2_MODE_SHIFT
24958. DA9055_GPIO2_PIN_MASK
24959. DA9055_GPIO2_PIN_SHIFT
24960. DA9055_GPIO2_PUPD_SHIFT
24961. DA9055_GPIO2_TYPE_MASK
24962. DA9055_GPIO2_TYPE_SHIFT
24963. DA9055_GPIO2_WEN_MASK
24964. DA9055_GPIO2_WEN_SHIFT
24965. DA9055_GPIO_PUPD_OPEN_DRAIN
24966. DA9055_GPIO_PUPD_PULL_UP
24967. DA9055_GPI_V_VDDCORE
24968. DA9055_GPI_V_VDD_IO
24969. DA9055_HP_L_AMP_OE
24970. DA9055_HP_L_CTRL
24971. DA9055_HP_L_GAIN
24972. DA9055_HP_L_GAIN_STATUS
24973. DA9055_HP_R_AMP_OE
24974. DA9055_HP_R_CTRL
24975. DA9055_HP_R_GAIN
24976. DA9055_HP_R_GAIN_STATUS
24977. DA9055_ID_BUCK1
24978. DA9055_ID_BUCK2
24979. DA9055_ID_LDO1
24980. DA9055_ID_LDO2
24981. DA9055_ID_LDO3
24982. DA9055_ID_LDO4
24983. DA9055_ID_LDO5
24984. DA9055_ID_LDO6
24985. DA9055_ILIM_500MA
24986. DA9055_ILIM_600MA
24987. DA9055_ILIM_700MA
24988. DA9055_ILIM_800MA
24989. DA9055_ILIM_MASK
24990. DA9055_INPUT
24991. DA9055_IO_CTRL
24992. DA9055_IRQ_ADC_MASK
24993. DA9055_IRQ_ALARM
24994. DA9055_IRQ_ALM_MASK
24995. DA9055_IRQ_BUCK_ILIM_MASK
24996. DA9055_IRQ_GPI0
24997. DA9055_IRQ_HWMON
24998. DA9055_IRQ_NONKEY
24999. DA9055_IRQ_NONKEY_MASK
25000. DA9055_IRQ_REGULATOR
25001. DA9055_IRQ_TICK
25002. DA9055_IRQ_TICK_MASK
25003. DA9055_IRQ_TYPE_ACT_HIGH
25004. DA9055_IRQ_TYPE_ACT_LOW
25005. DA9055_KEY_DELAY_10S
25006. DA9055_KEY_DELAY_4S
25007. DA9055_KEY_DELAY_6S
25008. DA9055_KEY_DELAY_8S
25009. DA9055_KEY_DELAY_MASK
25010. DA9055_KEY_DELAY_SHIFT
25011. DA9055_KEY_RESET_FLG
25012. DA9055_LDO
25013. DA9055_LDO1_DEF_SHIFT
25014. DA9055_LDO1_MON_EN_SHIFT
25015. DA9055_LDO2_DEF_SHIFT
25016. DA9055_LDO2_MON_EN_SHIFT
25017. DA9055_LDO3_DEF_SHIFT
25018. DA9055_LDO3_MON_EN_SHIFT
25019. DA9055_LDO4_DEF_SHIFT
25020. DA9055_LDO4_MON_EN_SHIFT
25021. DA9055_LDO5_BYP_SHIFT
25022. DA9055_LDO5_DEF_SHIFT
25023. DA9055_LDO5_LIM_STS
25024. DA9055_LDO5_MON_EN_SHIFT
25025. DA9055_LDO6_BYP_SHIFT
25026. DA9055_LDO6_DEF_SHIFT
25027. DA9055_LDO6_LIM_STS
25028. DA9055_LDO6_MON_EN_SHIFT
25029. DA9055_LDO_CONF_MASK
25030. DA9055_LDO_CONF_SHIFT
25031. DA9055_LDO_CTRL
25032. DA9055_LDO_EN_MASK
25033. DA9055_LDO_EN_SHIFT
25034. DA9055_LDO_GPI_MASK
25035. DA9055_LDO_GPI_SHIFT
25036. DA9055_LDO_MODE_SHIFT
25037. DA9055_LDO_MODE_SLEEP
25038. DA9055_LDO_MODE_SYNC
25039. DA9055_LDO_PD_DIS_MASK
25040. DA9055_LDO_PD_DIS_SHIFT
25041. DA9055_LDO_SD_SHIFT
25042. DA9055_LDO_SL_NORMAL
25043. DA9055_LDO_SL_SLEEP
25044. DA9055_LINE_AMP_OE
25045. DA9055_LINE_CTRL
25046. DA9055_LINE_GAIN
25047. DA9055_LINE_GAIN_STATUS
25048. DA9055_MAX_REGISTER_CNT
25049. DA9055_MAX_REGULATORS
25050. DA9055_MAX_UA
25051. DA9055_MICBIAS2_EN
25052. DA9055_MICBIAS_1_6V
25053. DA9055_MICBIAS_1_8V
25054. DA9055_MICBIAS_2_1V
25055. DA9055_MICBIAS_2_2V
25056. DA9055_MICBIAS_LEVEL_MASK
25057. DA9055_MIC_BIAS_CTRL
25058. DA9055_MIC_CONFIG
25059. DA9055_MIC_L_CTRL
25060. DA9055_MIC_L_GAIN
25061. DA9055_MIC_L_GAIN_STATUS
25062. DA9055_MIC_L_MUTE_EN
25063. DA9055_MIC_R_CTRL
25064. DA9055_MIC_R_GAIN
25065. DA9055_MIC_R_GAIN_STATUS
25066. DA9055_MIC_R_MUTE_EN
25067. DA9055_MIN_UA
25068. DA9055_MIXIN_L_CTRL
25069. DA9055_MIXIN_L_GAIN
25070. DA9055_MIXIN_L_GAIN_STATUS
25071. DA9055_MIXIN_L_MIX_EN
25072. DA9055_MIXIN_L_SELECT
25073. DA9055_MIXIN_R_CTRL
25074. DA9055_MIXIN_R_GAIN
25075. DA9055_MIXIN_R_GAIN_STATUS
25076. DA9055_MIXIN_R_MIX_EN
25077. DA9055_MIXIN_R_SELECT
25078. DA9055_MIXOUT_L_CTRL
25079. DA9055_MIXOUT_L_MIX_EN
25080. DA9055_MIXOUT_L_SELECT
25081. DA9055_MIXOUT_R_CTRL
25082. DA9055_MIXOUT_R_MIX_EN
25083. DA9055_MIXOUT_R_SELECT
25084. DA9055_MODE_AB
25085. DA9055_MODE_AUTO
25086. DA9055_MODE_MASK
25087. DA9055_MODE_SLEEP
25088. DA9055_MODE_SYNCHRO
25089. DA9055_MON_A10_IDX_LDO1
25090. DA9055_MON_A10_IDX_LDO2
25091. DA9055_MON_A10_IDX_LDO5
25092. DA9055_MON_A10_IDX_LDO6
25093. DA9055_MON_A10_IDX_MASK
25094. DA9055_MON_A10_IDX_NONE
25095. DA9055_MON_A10_IDX_SHIFT
25096. DA9055_MON_A89_IDX_BUCKCORE
25097. DA9055_MON_A89_IDX_LDO3
25098. DA9055_MON_A89_IDX_MASK
25099. DA9055_MON_A89_IDX_NONE
25100. DA9055_MON_A8_IDX_SHIFT
25101. DA9055_MON_A9_IDX_SHIFT
25102. DA9055_MON_DEB_SHIFT
25103. DA9055_MON_MODE_MASK
25104. DA9055_MON_MODE_SHIFT
25105. DA9055_MON_RES_SHIFT
25106. DA9055_MON_THRES_MASK
25107. DA9055_MON_THRES_SHIFT
25108. DA9055_M_ADC_RDY_EINT
25109. DA9055_M_ALARM_EINT
25110. DA9055_M_COMP_1V2_EINT
25111. DA9055_M_GPI0_EINT
25112. DA9055_M_GPI1_EINT
25113. DA9055_M_GPI2_EINT
25114. DA9055_M_LDO_LIM_EINT
25115. DA9055_M_NJIG_EINT
25116. DA9055_M_NONKEY_EINT
25117. DA9055_M_SEQ_RDY_EINT
25118. DA9055_M_TEMP_EINT
25119. DA9055_M_TICK_EINT
25120. DA9055_M_VDD_MON_EINT
25121. DA9055_M_VDD_WARN_EINT
25122. DA9055_M_WAKE_EINT
25123. DA9055_NFAULT_CONF_SHIFT
25124. DA9055_NIRQ_MODE_ACTIVE
25125. DA9055_NIRQ_MODE_IMM
25126. DA9055_NJIG_STS
25127. DA9055_NOKEY_EINT
25128. DA9055_NOKEY_LOCK_MASK
25129. DA9055_NOKEY_LOCK_SHIFT
25130. DA9055_NOKEY_STS
25131. DA9055_NONKEY_PIN_DEDICT
25132. DA9055_NONKEY_PIN_KEY_MODE
25133. DA9055_NONKEY_PIN_MASK
25134. DA9055_NONKEY_PIN_MULTI_FUNC
25135. DA9055_NONKEY_PIN_PORT_MODE
25136. DA9055_NONKEY_PIN_SHIFT
25137. DA9055_NONKEY_SD_SHIFT
25138. DA9055_NRES_MODE_MASK
25139. DA9055_NRES_MODE_SHIFT
25140. DA9055_OTP_APPS_LOCK_SHIFT
25141. DA9055_OTP_APPS_RD_SHIFT
25142. DA9055_OTP_CONF_LOCK_SHIFT
25143. DA9055_OTP_GP_LOCK_SHIFT
25144. DA9055_OTP_GP_RD_SHIFT
25145. DA9055_OTP_TIM_MARGINAL
25146. DA9055_OTP_TIM_NORMAL
25147. DA9055_OTP_WRITE_DIS_SHIFT
25148. DA9055_OUTPUT
25149. DA9055_OUT_CLCK_GATED
25150. DA9055_PAGE_WRITE_MODE
25151. DA9055_PC_COUNT
25152. DA9055_PC_DONE_SHIFT
25153. DA9055_PLL_CTRL
25154. DA9055_PLL_EN
25155. DA9055_PLL_FRAC_BOT
25156. DA9055_PLL_FRAC_TOP
25157. DA9055_PLL_INDIV_10_20_MHZ
25158. DA9055_PLL_INTEGER
25159. DA9055_PLL_SRM_EN
25160. DA9055_PLL_STATUS
25161. DA9055_PM_IF_V_VDDCORE
25162. DA9055_PM_IF_V_VDD_IO
25163. DA9055_PM_I_V_VDDCORE
25164. DA9055_PM_I_V_VDD_IO
25165. DA9055_PM_O_TYPE_OPEN_DRAIN
25166. DA9055_PM_O_TYPE_PUSH_PULL
25167. DA9055_PORT_MASK
25168. DA9055_PORT_SHIFT
25169. DA9055_POR_FLG
25170. DA9055_POWER1_EN_MASK
25171. DA9055_POWER1_EN_SHIFT
25172. DA9055_POWERN_EN_MASK
25173. DA9055_POWERN_EN_SHIFT
25174. DA9055_PUSH_PULL
25175. DA9055_REFERENCES
25176. DA9055_REGUALTOR_SET_A
25177. DA9055_REGUALTOR_SET_B
25178. DA9055_REG_ADCIN1_RES
25179. DA9055_REG_ADCIN2_RES
25180. DA9055_REG_ADCIN3_RES
25181. DA9055_REG_ADC_CONT
25182. DA9055_REG_ADC_MAN
25183. DA9055_REG_ADC_RES_H
25184. DA9055_REG_ADC_RES_L
25185. DA9055_REG_ALARM_D
25186. DA9055_REG_ALARM_H
25187. DA9055_REG_ALARM_MI
25188. DA9055_REG_ALARM_MO
25189. DA9055_REG_ALARM_Y
25190. DA9055_REG_AUTO1_HIGH
25191. DA9055_REG_AUTO1_LOW
25192. DA9055_REG_AUTO2_HIGH
25193. DA9055_REG_AUTO2_LOW
25194. DA9055_REG_AUTO3_HIGH
25195. DA9055_REG_AUTO3_LOW
25196. DA9055_REG_BCORE_CONT
25197. DA9055_REG_BCORE_MODE
25198. DA9055_REG_BMEM_CONT
25199. DA9055_REG_BUCK_LIM
25200. DA9055_REG_CONFIG_A
25201. DA9055_REG_CONFIG_B
25202. DA9055_REG_CONFIG_C
25203. DA9055_REG_CONFIG_D
25204. DA9055_REG_CONFIG_E
25205. DA9055_REG_CONTROL_A
25206. DA9055_REG_CONTROL_B
25207. DA9055_REG_CONTROL_C
25208. DA9055_REG_CONTROL_D
25209. DA9055_REG_CONTROL_E
25210. DA9055_REG_COUNT_D
25211. DA9055_REG_COUNT_H
25212. DA9055_REG_COUNT_MI
25213. DA9055_REG_COUNT_MO
25214. DA9055_REG_COUNT_S
25215. DA9055_REG_COUNT_Y
25216. DA9055_REG_EN_32K
25217. DA9055_REG_EVENT_A
25218. DA9055_REG_EVENT_B
25219. DA9055_REG_EVENT_C
25220. DA9055_REG_FAULT_LOG
25221. DA9055_REG_GPIO0_1
25222. DA9055_REG_GPIO2
25223. DA9055_REG_GPIO_MODE0_2
25224. DA9055_REG_GP_ID_0
25225. DA9055_REG_GP_ID_1
25226. DA9055_REG_GP_ID_10
25227. DA9055_REG_GP_ID_11
25228. DA9055_REG_GP_ID_12
25229. DA9055_REG_GP_ID_13
25230. DA9055_REG_GP_ID_14
25231. DA9055_REG_GP_ID_15
25232. DA9055_REG_GP_ID_16
25233. DA9055_REG_GP_ID_17
25234. DA9055_REG_GP_ID_18
25235. DA9055_REG_GP_ID_19
25236. DA9055_REG_GP_ID_2
25237. DA9055_REG_GP_ID_3
25238. DA9055_REG_GP_ID_4
25239. DA9055_REG_GP_ID_5
25240. DA9055_REG_GP_ID_6
25241. DA9055_REG_GP_ID_7
25242. DA9055_REG_GP_ID_8
25243. DA9055_REG_GP_ID_9
25244. DA9055_REG_INTERFACE
25245. DA9055_REG_IRQ_MASK_A
25246. DA9055_REG_IRQ_MASK_B
25247. DA9055_REG_IRQ_MASK_C
25248. DA9055_REG_LDO1_CONT
25249. DA9055_REG_LDO2_CONT
25250. DA9055_REG_LDO3_CONT
25251. DA9055_REG_LDO4_CONT
25252. DA9055_REG_LDO5_CONT
25253. DA9055_REG_LDO6_CONT
25254. DA9055_REG_OPT_ADDR
25255. DA9055_REG_OPT_COUNT
25256. DA9055_REG_OPT_DATA
25257. DA9055_REG_PAGE_CON
25258. DA9055_REG_PD_DIS
25259. DA9055_REG_SECOND_A
25260. DA9055_REG_SECOND_B
25261. DA9055_REG_SECOND_C
25262. DA9055_REG_SECOND_D
25263. DA9055_REG_STATUS_A
25264. DA9055_REG_STATUS_B
25265. DA9055_REG_TRIM_CLDR
25266. DA9055_REG_T_OFFSET
25267. DA9055_REG_VBCORE_A
25268. DA9055_REG_VBCORE_B
25269. DA9055_REG_VBMEM_A
25270. DA9055_REG_VBMEM_B
25271. DA9055_REG_VLDO1_A
25272. DA9055_REG_VLDO1_B
25273. DA9055_REG_VLDO2_A
25274. DA9055_REG_VLDO2_B
25275. DA9055_REG_VLDO3_A
25276. DA9055_REG_VLDO3_B
25277. DA9055_REG_VLDO4_A
25278. DA9055_REG_VLDO4_B
25279. DA9055_REG_VLDO5_A
25280. DA9055_REG_VLDO5_B
25281. DA9055_REG_VLDO6_A
25282. DA9055_REG_VLDO6_B
25283. DA9055_REG_VSYS_MON
25284. DA9055_REG_VSYS_RES
25285. DA9055_REPEAT_WRITE_MODE
25286. DA9055_RESET_DURATION_0MS
25287. DA9055_RESET_DURATION_1000MS
25288. DA9055_RESET_DURATION_100MS
25289. DA9055_RESET_DURATION_500MS
25290. DA9055_RESET_DURATION_MASK
25291. DA9055_RESET_DURATION_SHIFT
25292. DA9055_RESET_HIGH_VAL_BASE
25293. DA9055_RESET_HIGH_VAL_MASK
25294. DA9055_RESET_HIGH_VAL_MAX
25295. DA9055_RESET_LOW_VAL_BASE
25296. DA9055_RESET_LOW_VAL_MASK
25297. DA9055_RESET_LOW_VAL_MAX
25298. DA9055_RESET_TIMER_VAL_SHIFT
25299. DA9055_RESET_US_HIGH_BASE
25300. DA9055_RESET_US_HIGH_INC
25301. DA9055_RESET_US_HIGH_STEP
25302. DA9055_RESET_US_LOW_BASE
25303. DA9055_RESET_US_LOW_INC
25304. DA9055_RESET_US_LOW_STEP
25305. DA9055_RTC_ALM_DAY
25306. DA9055_RTC_ALM_EN
25307. DA9055_RTC_ALM_HOUR
25308. DA9055_RTC_ALM_MIN
25309. DA9055_RTC_ALM_MONTH
25310. DA9055_RTC_ALM_YEAR
25311. DA9055_RTC_CLOCK_GATED
25312. DA9055_RTC_DAY
25313. DA9055_RTC_EN
25314. DA9055_RTC_HOUR
25315. DA9055_RTC_MIN
25316. DA9055_RTC_MODE_PD
25317. DA9055_RTC_MODE_SD
25318. DA9055_RTC_MODE_SD_SHIFT
25319. DA9055_RTC_MONITOR_EN
25320. DA9055_RTC_MONTH
25321. DA9055_RTC_READ
25322. DA9055_RTC_SEC
25323. DA9055_RTC_TICK_ALM_MASK
25324. DA9055_RTC_TICK_EN
25325. DA9055_RTC_TICK_MIN
25326. DA9055_RTC_TICK_SEC
25327. DA9055_RTC_TICK_TYPE
25328. DA9055_RTC_TICK_TYPE_SHIFT
25329. DA9055_RTC_TICK_WAKE_MASK
25330. DA9055_RTC_TICK_WAKE_SHIFT
25331. DA9055_RTC_YEAR
25332. DA9055_RTC_YEAR_BASE
25333. DA9055_SEL_REG_A
25334. DA9055_SEL_REG_B
25335. DA9055_SEQ_RDY_EINT
25336. DA9055_SHUTDOWN_MASK
25337. DA9055_SHUTDOWN_SHIFT
25338. DA9055_SLEW_RATE_MASK
25339. DA9055_SLEW_RATE_SHIFT
25340. DA9055_SR
25341. DA9055_SR_11025
25342. DA9055_SR_12000
25343. DA9055_SR_16000
25344. DA9055_SR_22050
25345. DA9055_SR_24000
25346. DA9055_SR_32000
25347. DA9055_SR_44100
25348. DA9055_SR_48000
25349. DA9055_SR_8000
25350. DA9055_SR_88200
25351. DA9055_SR_96000
25352. DA9055_STANDBY_MASK
25353. DA9055_STANDBY_SHIFT
25354. DA9055_STARTUP_TIME_0S
25355. DA9055_STARTUP_TIME_0_52S
25356. DA9055_STARTUP_TIME_1S
25357. DA9055_STARTUP_TIME_MASK
25358. DA9055_START_MAX_MASK
25359. DA9055_START_MAX_SHIFT
25360. DA9055_STATUS1
25361. DA9055_SYSTEM_EN_MASK
25362. DA9055_SYSTEM_EN_SHIFT
25363. DA9055_SYSTEM_MODES_INPUT
25364. DA9055_SYSTEM_MODES_OUTPUT
25365. DA9055_TEMP_CRIT_FLG
25366. DA9055_TICK_EINT
25367. DA9055_TRIM_32K_MASK
25368. DA9055_TRIM_32K_SHIFT
25369. DA9055_TRIM_DECREMENT
25370. DA9055_TRIM_INCREMENT
25371. DA9055_TRIM_PPM_BASE
25372. DA9055_TRIM_PPM_INC
25373. DA9055_TRIM_STEPS
25374. DA9055_TRIM_VAL_BASE
25375. DA9055_TWDMIN
25376. DA9055_TWDSCALE_MASK
25377. DA9055_TWDSCALE_SHIFT
25378. DA9055_TWD_ERROR_FLG
25379. DA9055_UVOV_DELAY_MASK
25380. DA9055_UVOV_DELAY_SHIFT
25381. DA9055_VBCORE_GPI_MASK
25382. DA9055_VBCORE_GPI_SHIFT
25383. DA9055_VBCORE_SEL_MASK
25384. DA9055_VBCORE_SEL_SHIFT
25385. DA9055_VBCORE_STEPS
25386. DA9055_VBCORE_VAL_BASE
25387. DA9055_VBCORE_VAL_MASK
25388. DA9055_VBCORE_VAL_MAX
25389. DA9055_VBCORE_VAL_SHIFT
25390. DA9055_VBCORE_VOLT_BASE
25391. DA9055_VBCORE_VOLT_INC
25392. DA9055_VBCORE_VOLT_MIN
25393. DA9055_VBMEM_GPI_MASK
25394. DA9055_VBMEM_GPI_SHIFT
25395. DA9055_VBMEM_SEL_MASK
25396. DA9055_VBMEM_SEL_SHIT
25397. DA9055_VBMEM_SEL_VBMEM_A
25398. DA9055_VBMEM_SEL_VBMEM_B
25399. DA9055_VBMEM_STEPS
25400. DA9055_VBMEM_VAL_BASE
25401. DA9055_VBMEM_VAL_MASK
25402. DA9055_VBMEM_VAL_MAX
25403. DA9055_VBMEM_VAL_SHIFT
25404. DA9055_VBMEM_VOLT_BASE
25405. DA9055_VBMEM_VOLT_INC
25406. DA9055_VBMEM_VOLT_MIN
25407. DA9055_VDD_FAULT_EN_SHIFT
25408. DA9055_VDD_FAULT_FLG
25409. DA9055_VDD_FAULT_STEPS
25410. DA9055_VDD_FAULT_TYPE_ACT_HIGH
25411. DA9055_VDD_FAULT_TYPE_ACT_LOW
25412. DA9055_VDD_FAULT_VAL_BASE
25413. DA9055_VDD_FAULT_VAL_MASK
25414. DA9055_VDD_FAULT_VAL_MAX
25415. DA9055_VDD_FAULT_VAL_SHIFT
25416. DA9055_VDD_FAULT_VOLT_BASE
25417. DA9055_VDD_FAULT_VOLT_INC
25418. DA9055_VDD_HYST_STEPS
25419. DA9055_VDD_HYST_VAL_BASE
25420. DA9055_VDD_HYST_VAL_MASK
25421. DA9055_VDD_HYST_VAL_MAX
25422. DA9055_VDD_HYST_VAL_SHIFT
25423. DA9055_VDD_HYST_VOLT_BASE
25424. DA9055_VDD_HYST_VOLT_INC
25425. DA9055_VDD_HYST_VOLT_MIN
25426. DA9055_VDD_IO
25427. DA9055_VDD_START_FLG
25428. DA9055_VLDO2_VAL_BASE
25429. DA9055_VLDO5_STEPS
25430. DA9055_VLDO6_STEPS
25431. DA9055_VLDO6_VAL_BASE
25432. DA9055_VLDO6_VAL_MASK
25433. DA9055_VLDO6_VAL_MAX
25434. DA9055_VLDO6_VOLT_INC
25435. DA9055_VLDO_GPI_MASK
25436. DA9055_VLDO_GPI_SHIFT
25437. DA9055_VLDO_SEL_MASK
25438. DA9055_VLDO_SEL_SHIFT
25439. DA9055_VLDO_SEL_VLDO_A
25440. DA9055_VLDO_SEL_VLDO_B
25441. DA9055_VLDO_STEPS
25442. DA9055_VLDO_VAL_BASE
25443. DA9055_VLDO_VAL_MASK
25444. DA9055_VLDO_VAL_MAX
25445. DA9055_VLDO_VAL_SHIFT
25446. DA9055_VLDO_VOLT_BASE
25447. DA9055_VLDO_VOLT_INC
25448. DA9055_VLDO_VOLT_MIN
25449. DA9055_VMID_EN
25450. DA9055_VSYS_DIV
25451. DA9055_VSYS_STEPS
25452. DA9055_VSYS_VAL_BASE
25453. DA9055_VSYS_VAL_MASK
25454. DA9055_VSYS_VAL_MAX
25455. DA9055_VSYS_VAL_SHIFT
25456. DA9055_VSYS_VOLT_BASE
25457. DA9055_VSYS_VOLT_INC
25458. DA9055_VSYS_VOLT_MIN
25459. DA9055_V_GPI_MASK
25460. DA9055_V_GPI_SHIFT
25461. DA9055_V_LOCK_MASK
25462. DA9055_V_LOCK_SHIFT
25463. DA9055_WAIT_SHUT_FLG
25464. DA9055_WAKE_STS
25465. DA9055_WAKE_UP_MASK
25466. DA9055_WAKE_UP_SHIFT
25467. DA9055_WATCHDOG_MASK
25468. DA9055_WATCHDOG_SHIFT
25469. DA9061_ID_BUCK1
25470. DA9061_ID_BUCK2
25471. DA9061_ID_BUCK3
25472. DA9061_ID_LDO1
25473. DA9061_ID_LDO2
25474. DA9061_ID_LDO3
25475. DA9061_ID_LDO4
25476. DA9061_IRQ_DVC_RDY
25477. DA9061_IRQ_GPI0
25478. DA9061_IRQ_GPI1
25479. DA9061_IRQ_GPI2
25480. DA9061_IRQ_GPI3
25481. DA9061_IRQ_GPI4
25482. DA9061_IRQ_LDO_LIM
25483. DA9061_IRQ_ONKEY
25484. DA9061_IRQ_SEQ_RDY
25485. DA9061_IRQ_TEMP
25486. DA9061_IRQ_VDD_WARN
25487. DA9061_IRQ_WDG_WARN
25488. DA9061_MAX_REGULATORS
25489. DA9061_NUM_IRQ
25490. DA9062AA_ALARM_D
25491. DA9062AA_ALARM_DAY_MASK
25492. DA9062AA_ALARM_DAY_SHIFT
25493. DA9062AA_ALARM_H
25494. DA9062AA_ALARM_HOUR_MASK
25495. DA9062AA_ALARM_HOUR_SHIFT
25496. DA9062AA_ALARM_MI
25497. DA9062AA_ALARM_MIN_MASK
25498. DA9062AA_ALARM_MIN_SHIFT
25499. DA9062AA_ALARM_MO
25500. DA9062AA_ALARM_MONTH_MASK
25501. DA9062AA_ALARM_MONTH_SHIFT
25502. DA9062AA_ALARM_ON_MASK
25503. DA9062AA_ALARM_ON_SHIFT
25504. DA9062AA_ALARM_S
25505. DA9062AA_ALARM_SEC_MASK
25506. DA9062AA_ALARM_SEC_SHIFT
25507. DA9062AA_ALARM_STATUS_MASK
25508. DA9062AA_ALARM_STATUS_SHIFT
25509. DA9062AA_ALARM_Y
25510. DA9062AA_ALARM_YEAR_MASK
25511. DA9062AA_ALARM_YEAR_SHIFT
25512. DA9062AA_AUTO_BOOT_MASK
25513. DA9062AA_AUTO_BOOT_SHIFT
25514. DA9062AA_BBAT_CONT
25515. DA9062AA_BBAT_DIS_MASK
25516. DA9062AA_BBAT_DIS_SHIFT
25517. DA9062AA_BCHG_ISET_MASK
25518. DA9062AA_BCHG_ISET_SHIFT
25519. DA9062AA_BCHG_VSET_MASK
25520. DA9062AA_BCHG_VSET_SHIFT
25521. DA9062AA_BUCK1_2_MERGE_MASK
25522. DA9062AA_BUCK1_2_MERGE_SHIFT
25523. DA9062AA_BUCK1_AUTO_MASK
25524. DA9062AA_BUCK1_AUTO_SHIFT
25525. DA9062AA_BUCK1_CFG
25526. DA9062AA_BUCK1_CLK_INV_MASK
25527. DA9062AA_BUCK1_CLK_INV_SHIFT
25528. DA9062AA_BUCK1_CONF_MASK
25529. DA9062AA_BUCK1_CONF_SHIFT
25530. DA9062AA_BUCK1_CONT
25531. DA9062AA_BUCK1_EN_MASK
25532. DA9062AA_BUCK1_EN_SHIFT
25533. DA9062AA_BUCK1_GPI_MASK
25534. DA9062AA_BUCK1_GPI_SHIFT
25535. DA9062AA_BUCK1_ILIM_MASK
25536. DA9062AA_BUCK1_ILIM_SHIFT
25537. DA9062AA_BUCK1_MODE_MASK
25538. DA9062AA_BUCK1_MODE_SHIFT
25539. DA9062AA_BUCK1_OD_MASK
25540. DA9062AA_BUCK1_OD_SHIFT
25541. DA9062AA_BUCK1_PD_DIS_MASK
25542. DA9062AA_BUCK1_PD_DIS_SHIFT
25543. DA9062AA_BUCK1_SL_A_MASK
25544. DA9062AA_BUCK1_SL_A_SHIFT
25545. DA9062AA_BUCK1_SL_B_MASK
25546. DA9062AA_BUCK1_SL_B_SHIFT
25547. DA9062AA_BUCK1_STEP_MASK
25548. DA9062AA_BUCK1_STEP_SHIFT
25549. DA9062AA_BUCK2_AUTO_MASK
25550. DA9062AA_BUCK2_AUTO_SHIFT
25551. DA9062AA_BUCK2_CFG
25552. DA9062AA_BUCK2_CONF_MASK
25553. DA9062AA_BUCK2_CONF_SHIFT
25554. DA9062AA_BUCK2_CONT
25555. DA9062AA_BUCK2_EN_MASK
25556. DA9062AA_BUCK2_EN_SHIFT
25557. DA9062AA_BUCK2_GPI_MASK
25558. DA9062AA_BUCK2_GPI_SHIFT
25559. DA9062AA_BUCK2_ILIM_MASK
25560. DA9062AA_BUCK2_ILIM_SHIFT
25561. DA9062AA_BUCK2_MODE_MASK
25562. DA9062AA_BUCK2_MODE_SHIFT
25563. DA9062AA_BUCK2_OD_MASK
25564. DA9062AA_BUCK2_OD_SHIFT
25565. DA9062AA_BUCK2_PD_DIS_MASK
25566. DA9062AA_BUCK2_PD_DIS_SHIFT
25567. DA9062AA_BUCK2_SL_A_MASK
25568. DA9062AA_BUCK2_SL_A_SHIFT
25569. DA9062AA_BUCK2_SL_B_MASK
25570. DA9062AA_BUCK2_SL_B_SHIFT
25571. DA9062AA_BUCK2_STEP_MASK
25572. DA9062AA_BUCK2_STEP_SHIFT
25573. DA9062AA_BUCK3_AUTO_MASK
25574. DA9062AA_BUCK3_AUTO_SHIFT
25575. DA9062AA_BUCK3_CFG
25576. DA9062AA_BUCK3_CLK_INV_MASK
25577. DA9062AA_BUCK3_CLK_INV_SHIFT
25578. DA9062AA_BUCK3_CONF_MASK
25579. DA9062AA_BUCK3_CONF_SHIFT
25580. DA9062AA_BUCK3_CONT
25581. DA9062AA_BUCK3_EN_MASK
25582. DA9062AA_BUCK3_EN_SHIFT
25583. DA9062AA_BUCK3_GPI_MASK
25584. DA9062AA_BUCK3_GPI_SHIFT
25585. DA9062AA_BUCK3_ILIM_MASK
25586. DA9062AA_BUCK3_ILIM_SHIFT
25587. DA9062AA_BUCK3_MODE_MASK
25588. DA9062AA_BUCK3_MODE_SHIFT
25589. DA9062AA_BUCK3_PD_DIS_MASK
25590. DA9062AA_BUCK3_PD_DIS_SHIFT
25591. DA9062AA_BUCK3_SL_A_MASK
25592. DA9062AA_BUCK3_SL_A_SHIFT
25593. DA9062AA_BUCK3_SL_B_MASK
25594. DA9062AA_BUCK3_SL_B_SHIFT
25595. DA9062AA_BUCK3_STEP_MASK
25596. DA9062AA_BUCK3_STEP_SHIFT
25597. DA9062AA_BUCK4_AUTO_MASK
25598. DA9062AA_BUCK4_AUTO_SHIFT
25599. DA9062AA_BUCK4_CFG
25600. DA9062AA_BUCK4_CLK_INV_MASK
25601. DA9062AA_BUCK4_CLK_INV_SHIFT
25602. DA9062AA_BUCK4_CONF_MASK
25603. DA9062AA_BUCK4_CONF_SHIFT
25604. DA9062AA_BUCK4_CONT
25605. DA9062AA_BUCK4_EN_MASK
25606. DA9062AA_BUCK4_EN_SHIFT
25607. DA9062AA_BUCK4_GPI_MASK
25608. DA9062AA_BUCK4_GPI_SHIFT
25609. DA9062AA_BUCK4_ILIM_MASK
25610. DA9062AA_BUCK4_ILIM_SHIFT
25611. DA9062AA_BUCK4_MODE_MASK
25612. DA9062AA_BUCK4_MODE_SHIFT
25613. DA9062AA_BUCK4_PD_DIS_MASK
25614. DA9062AA_BUCK4_PD_DIS_SHIFT
25615. DA9062AA_BUCK4_SL_A_MASK
25616. DA9062AA_BUCK4_SL_A_SHIFT
25617. DA9062AA_BUCK4_SL_B_MASK
25618. DA9062AA_BUCK4_SL_B_SHIFT
25619. DA9062AA_BUCK4_STEP_MASK
25620. DA9062AA_BUCK4_STEP_SHIFT
25621. DA9062AA_BUCK4_VTTR_EN_MASK
25622. DA9062AA_BUCK4_VTTR_EN_SHIFT
25623. DA9062AA_BUCK4_VTT_EN_MASK
25624. DA9062AA_BUCK4_VTT_EN_SHIFT
25625. DA9062AA_BUCK_ACTV_DISCHRG_MASK
25626. DA9062AA_BUCK_ACTV_DISCHRG_SHIFT
25627. DA9062AA_BUCK_ILIM_A
25628. DA9062AA_BUCK_ILIM_B
25629. DA9062AA_BUCK_ILIM_C
25630. DA9062AA_BUCK_SLOWSTART_MASK
25631. DA9062AA_BUCK_SLOWSTART_SHIFT
25632. DA9062AA_CLDR_PAUSE_MASK
25633. DA9062AA_CLDR_PAUSE_SHIFT
25634. DA9062AA_CONFIG_A
25635. DA9062AA_CONFIG_B
25636. DA9062AA_CONFIG_C
25637. DA9062AA_CONFIG_D
25638. DA9062AA_CONFIG_E
25639. DA9062AA_CONFIG_G
25640. DA9062AA_CONFIG_H
25641. DA9062AA_CONFIG_I
25642. DA9062AA_CONFIG_ID
25643. DA9062AA_CONFIG_J
25644. DA9062AA_CONFIG_K
25645. DA9062AA_CONFIG_M
25646. DA9062AA_CONFIG_REV_MASK
25647. DA9062AA_CONFIG_REV_SHIFT
25648. DA9062AA_CONTROL_A
25649. DA9062AA_CONTROL_B
25650. DA9062AA_CONTROL_C
25651. DA9062AA_CONTROL_D
25652. DA9062AA_CONTROL_E
25653. DA9062AA_CONTROL_F
25654. DA9062AA_COUNT_D
25655. DA9062AA_COUNT_DAY_MASK
25656. DA9062AA_COUNT_DAY_SHIFT
25657. DA9062AA_COUNT_H
25658. DA9062AA_COUNT_HOUR_MASK
25659. DA9062AA_COUNT_HOUR_SHIFT
25660. DA9062AA_COUNT_MI
25661. DA9062AA_COUNT_MIN_MASK
25662. DA9062AA_COUNT_MIN_SHIFT
25663. DA9062AA_COUNT_MO
25664. DA9062AA_COUNT_MONTH_MASK
25665. DA9062AA_COUNT_MONTH_SHIFT
25666. DA9062AA_COUNT_S
25667. DA9062AA_COUNT_SEC_MASK
25668. DA9062AA_COUNT_SEC_SHIFT
25669. DA9062AA_COUNT_Y
25670. DA9062AA_COUNT_YEAR_MASK
25671. DA9062AA_COUNT_YEAR_SHIFT
25672. DA9062AA_CRYSTAL_MASK
25673. DA9062AA_CRYSTAL_SHIFT
25674. DA9062AA_CUSTOMER_ID
25675. DA9062AA_CUST_ID_MASK
25676. DA9062AA_CUST_ID_SHIFT
25677. DA9062AA_DEBOUNCING_MASK
25678. DA9062AA_DEBOUNCING_SHIFT
25679. DA9062AA_DEF_SUPPLY_MASK
25680. DA9062AA_DEF_SUPPLY_SHIFT
25681. DA9062AA_DELAY_MODE_MASK
25682. DA9062AA_DELAY_MODE_SHIFT
25683. DA9062AA_DEVICE_ID
25684. DA9062AA_DEV_ID_MASK
25685. DA9062AA_DEV_ID_SHIFT
25686. DA9062AA_DVC_1
25687. DA9062AA_DVC_BUSY_MASK
25688. DA9062AA_DVC_BUSY_SHIFT
25689. DA9062AA_EN32K_STEP_MASK
25690. DA9062AA_EN32K_STEP_SHIFT
25691. DA9062AA_EN_32K
25692. DA9062AA_EN_32KOUT_MASK
25693. DA9062AA_EN_32KOUT_SHIFT
25694. DA9062AA_EVENTS_B_MASK
25695. DA9062AA_EVENTS_B_SHIFT
25696. DA9062AA_EVENTS_C_MASK
25697. DA9062AA_EVENTS_C_SHIFT
25698. DA9062AA_EVENT_A
25699. DA9062AA_EVENT_B
25700. DA9062AA_EVENT_C
25701. DA9062AA_E_ALARM_MASK
25702. DA9062AA_E_ALARM_SHIFT
25703. DA9062AA_E_DVC_RDY_MASK
25704. DA9062AA_E_DVC_RDY_SHIFT
25705. DA9062AA_E_GPI0_MASK
25706. DA9062AA_E_GPI0_SHIFT
25707. DA9062AA_E_GPI1_MASK
25708. DA9062AA_E_GPI1_SHIFT
25709. DA9062AA_E_GPI2_MASK
25710. DA9062AA_E_GPI2_SHIFT
25711. DA9062AA_E_GPI3_MASK
25712. DA9062AA_E_GPI3_SHIFT
25713. DA9062AA_E_GPI4_MASK
25714. DA9062AA_E_GPI4_SHIFT
25715. DA9062AA_E_LDO_LIM_MASK
25716. DA9062AA_E_LDO_LIM_SHIFT
25717. DA9062AA_E_NONKEY_MASK
25718. DA9062AA_E_NONKEY_SHIFT
25719. DA9062AA_E_SEQ_RDY_MASK
25720. DA9062AA_E_SEQ_RDY_SHIFT
25721. DA9062AA_E_TEMP_MASK
25722. DA9062AA_E_TEMP_SHIFT
25723. DA9062AA_E_TICK_MASK
25724. DA9062AA_E_TICK_SHIFT
25725. DA9062AA_E_VDD_WARN_MASK
25726. DA9062AA_E_VDD_WARN_SHIFT
25727. DA9062AA_E_WDG_WARN_MASK
25728. DA9062AA_E_WDG_WARN_SHIFT
25729. DA9062AA_FAULT_LOG
25730. DA9062AA_FORCE_RESET_MASK
25731. DA9062AA_FORCE_RESET_SHIFT
25732. DA9062AA_FREEZE_EN_MASK
25733. DA9062AA_FREEZE_EN_SHIFT
25734. DA9062AA_GPI0_MASK
25735. DA9062AA_GPI0_SHIFT
25736. DA9062AA_GPI1_MASK
25737. DA9062AA_GPI1_SHIFT
25738. DA9062AA_GPI2_MASK
25739. DA9062AA_GPI2_SHIFT
25740. DA9062AA_GPI3_MASK
25741. DA9062AA_GPI3_SHIFT
25742. DA9062AA_GPI4_MASK
25743. DA9062AA_GPI4_SHIFT
25744. DA9062AA_GPIO0_MODE_MASK
25745. DA9062AA_GPIO0_MODE_SHIFT
25746. DA9062AA_GPIO0_OUT_MASK
25747. DA9062AA_GPIO0_OUT_SHIFT
25748. DA9062AA_GPIO0_PIN_MASK
25749. DA9062AA_GPIO0_PIN_SHIFT
25750. DA9062AA_GPIO0_PUPD_MASK
25751. DA9062AA_GPIO0_PUPD_SHIFT
25752. DA9062AA_GPIO0_TYPE_MASK
25753. DA9062AA_GPIO0_TYPE_SHIFT
25754. DA9062AA_GPIO0_WEN_MASK
25755. DA9062AA_GPIO0_WEN_SHIFT
25756. DA9062AA_GPIO0_WKUP_MODE_MASK
25757. DA9062AA_GPIO0_WKUP_MODE_SHIFT
25758. DA9062AA_GPIO1_MODE_MASK
25759. DA9062AA_GPIO1_MODE_SHIFT
25760. DA9062AA_GPIO1_OUT_MASK
25761. DA9062AA_GPIO1_OUT_SHIFT
25762. DA9062AA_GPIO1_PIN_MASK
25763. DA9062AA_GPIO1_PIN_SHIFT
25764. DA9062AA_GPIO1_PUPD_MASK
25765. DA9062AA_GPIO1_PUPD_SHIFT
25766. DA9062AA_GPIO1_TYPE_MASK
25767. DA9062AA_GPIO1_TYPE_SHIFT
25768. DA9062AA_GPIO1_WEN_MASK
25769. DA9062AA_GPIO1_WEN_SHIFT
25770. DA9062AA_GPIO1_WKUP_MODE_MASK
25771. DA9062AA_GPIO1_WKUP_MODE_SHIFT
25772. DA9062AA_GPIO2_MODE_MASK
25773. DA9062AA_GPIO2_MODE_SHIFT
25774. DA9062AA_GPIO2_OUT_MASK
25775. DA9062AA_GPIO2_OUT_SHIFT
25776. DA9062AA_GPIO2_PIN_MASK
25777. DA9062AA_GPIO2_PIN_SHIFT
25778. DA9062AA_GPIO2_PUPD_MASK
25779. DA9062AA_GPIO2_PUPD_SHIFT
25780. DA9062AA_GPIO2_TYPE_MASK
25781. DA9062AA_GPIO2_TYPE_SHIFT
25782. DA9062AA_GPIO2_WEN_MASK
25783. DA9062AA_GPIO2_WEN_SHIFT
25784. DA9062AA_GPIO2_WKUP_MODE_MASK
25785. DA9062AA_GPIO2_WKUP_MODE_SHIFT
25786. DA9062AA_GPIO3_MODE_MASK
25787. DA9062AA_GPIO3_MODE_SHIFT
25788. DA9062AA_GPIO3_OUT_MASK
25789. DA9062AA_GPIO3_OUT_SHIFT
25790. DA9062AA_GPIO3_PIN_MASK
25791. DA9062AA_GPIO3_PIN_SHIFT
25792. DA9062AA_GPIO3_PUPD_MASK
25793. DA9062AA_GPIO3_PUPD_SHIFT
25794. DA9062AA_GPIO3_TYPE_MASK
25795. DA9062AA_GPIO3_TYPE_SHIFT
25796. DA9062AA_GPIO3_WEN_MASK
25797. DA9062AA_GPIO3_WEN_SHIFT
25798. DA9062AA_GPIO3_WKUP_MODE_MASK
25799. DA9062AA_GPIO3_WKUP_MODE_SHIFT
25800. DA9062AA_GPIO4_MODE_MASK
25801. DA9062AA_GPIO4_MODE_SHIFT
25802. DA9062AA_GPIO4_OUT_MASK
25803. DA9062AA_GPIO4_OUT_SHIFT
25804. DA9062AA_GPIO4_PIN_MASK
25805. DA9062AA_GPIO4_PIN_SHIFT
25806. DA9062AA_GPIO4_PUPD_MASK
25807. DA9062AA_GPIO4_PUPD_SHIFT
25808. DA9062AA_GPIO4_TYPE_MASK
25809. DA9062AA_GPIO4_TYPE_SHIFT
25810. DA9062AA_GPIO4_WEN_MASK
25811. DA9062AA_GPIO4_WEN_SHIFT
25812. DA9062AA_GPIO4_WKUP_MODE_MASK
25813. DA9062AA_GPIO4_WKUP_MODE_SHIFT
25814. DA9062AA_GPIO_0_1
25815. DA9062AA_GPIO_2_3
25816. DA9062AA_GPIO_4
25817. DA9062AA_GPIO_MODE0_4
25818. DA9062AA_GPIO_OUT0_2
25819. DA9062AA_GPIO_OUT3_4
25820. DA9062AA_GPIO_WKUP_MODE
25821. DA9062AA_GPI_DIS_MASK
25822. DA9062AA_GPI_DIS_SHIFT
25823. DA9062AA_GPI_V_MASK
25824. DA9062AA_GPI_V_SHIFT
25825. DA9062AA_GP_0_MASK
25826. DA9062AA_GP_0_SHIFT
25827. DA9062AA_GP_10_MASK
25828. DA9062AA_GP_10_SHIFT
25829. DA9062AA_GP_11_MASK
25830. DA9062AA_GP_11_SHIFT
25831. DA9062AA_GP_12_MASK
25832. DA9062AA_GP_12_SHIFT
25833. DA9062AA_GP_13_MASK
25834. DA9062AA_GP_13_SHIFT
25835. DA9062AA_GP_14_MASK
25836. DA9062AA_GP_14_SHIFT
25837. DA9062AA_GP_15_MASK
25838. DA9062AA_GP_15_SHIFT
25839. DA9062AA_GP_16_MASK
25840. DA9062AA_GP_16_SHIFT
25841. DA9062AA_GP_17_MASK
25842. DA9062AA_GP_17_SHIFT
25843. DA9062AA_GP_18_MASK
25844. DA9062AA_GP_18_SHIFT
25845. DA9062AA_GP_19_MASK
25846. DA9062AA_GP_19_SHIFT
25847. DA9062AA_GP_1_MASK
25848. DA9062AA_GP_1_SHIFT
25849. DA9062AA_GP_2_MASK
25850. DA9062AA_GP_2_SHIFT
25851. DA9062AA_GP_3_MASK
25852. DA9062AA_GP_3_SHIFT
25853. DA9062AA_GP_4_MASK
25854. DA9062AA_GP_4_SHIFT
25855. DA9062AA_GP_5_MASK
25856. DA9062AA_GP_5_SHIFT
25857. DA9062AA_GP_6_MASK
25858. DA9062AA_GP_6_SHIFT
25859. DA9062AA_GP_7_MASK
25860. DA9062AA_GP_7_SHIFT
25861. DA9062AA_GP_8_MASK
25862. DA9062AA_GP_8_SHIFT
25863. DA9062AA_GP_9_MASK
25864. DA9062AA_GP_9_SHIFT
25865. DA9062AA_GP_FALL1_STEP_MASK
25866. DA9062AA_GP_FALL1_STEP_SHIFT
25867. DA9062AA_GP_FALL2_STEP_MASK
25868. DA9062AA_GP_FALL2_STEP_SHIFT
25869. DA9062AA_GP_FALL3_STEP_MASK
25870. DA9062AA_GP_FALL3_STEP_SHIFT
25871. DA9062AA_GP_FALL4_STEP_MASK
25872. DA9062AA_GP_FALL4_STEP_SHIFT
25873. DA9062AA_GP_FALL5_STEP_MASK
25874. DA9062AA_GP_FALL5_STEP_SHIFT
25875. DA9062AA_GP_ID_0
25876. DA9062AA_GP_ID_1
25877. DA9062AA_GP_ID_10
25878. DA9062AA_GP_ID_11
25879. DA9062AA_GP_ID_12
25880. DA9062AA_GP_ID_13
25881. DA9062AA_GP_ID_14
25882. DA9062AA_GP_ID_15
25883. DA9062AA_GP_ID_16
25884. DA9062AA_GP_ID_17
25885. DA9062AA_GP_ID_18
25886. DA9062AA_GP_ID_19
25887. DA9062AA_GP_ID_2
25888. DA9062AA_GP_ID_3
25889. DA9062AA_GP_ID_4
25890. DA9062AA_GP_ID_5
25891. DA9062AA_GP_ID_6
25892. DA9062AA_GP_ID_7
25893. DA9062AA_GP_ID_8
25894. DA9062AA_GP_ID_9
25895. DA9062AA_GP_RISE1_STEP_MASK
25896. DA9062AA_GP_RISE1_STEP_SHIFT
25897. DA9062AA_GP_RISE2_STEP_MASK
25898. DA9062AA_GP_RISE2_STEP_SHIFT
25899. DA9062AA_GP_RISE3_STEP_MASK
25900. DA9062AA_GP_RISE3_STEP_SHIFT
25901. DA9062AA_GP_RISE4_STEP_MASK
25902. DA9062AA_GP_RISE4_STEP_SHIFT
25903. DA9062AA_GP_RISE5_STEP_MASK
25904. DA9062AA_GP_RISE5_STEP_SHIFT
25905. DA9062AA_HOST_SD_MODE_MASK
25906. DA9062AA_HOST_SD_MODE_SHIFT
25907. DA9062AA_ID_12_11
25908. DA9062AA_ID_14_13
25909. DA9062AA_ID_16_15
25910. DA9062AA_ID_22_21
25911. DA9062AA_ID_24_23
25912. DA9062AA_ID_26_25
25913. DA9062AA_ID_28_27
25914. DA9062AA_ID_2_1
25915. DA9062AA_ID_30_29
25916. DA9062AA_ID_32_31
25917. DA9062AA_ID_4_3
25918. DA9062AA_IF_BASE_ADDR_MASK
25919. DA9062AA_IF_BASE_ADDR_SHIFT
25920. DA9062AA_IF_RESET_MASK
25921. DA9062AA_IF_RESET_SHIFT
25922. DA9062AA_INTERFACE
25923. DA9062AA_INT_SD_MODE_MASK
25924. DA9062AA_INT_SD_MODE_SHIFT
25925. DA9062AA_IRQ_MASK_A
25926. DA9062AA_IRQ_MASK_B
25927. DA9062AA_IRQ_MASK_C
25928. DA9062AA_IRQ_TYPE_MASK
25929. DA9062AA_IRQ_TYPE_SHIFT
25930. DA9062AA_KEY_DELAY_MASK
25931. DA9062AA_KEY_DELAY_SHIFT
25932. DA9062AA_KEY_RESET_MASK
25933. DA9062AA_KEY_RESET_SHIFT
25934. DA9062AA_KEY_SD_MODE_MASK
25935. DA9062AA_KEY_SD_MODE_SHIFT
25936. DA9062AA_LDO1_AUTO_MASK
25937. DA9062AA_LDO1_AUTO_SHIFT
25938. DA9062AA_LDO1_CONF_MASK
25939. DA9062AA_LDO1_CONF_SHIFT
25940. DA9062AA_LDO1_CONT
25941. DA9062AA_LDO1_EN_MASK
25942. DA9062AA_LDO1_EN_SHIFT
25943. DA9062AA_LDO1_GPI_MASK
25944. DA9062AA_LDO1_GPI_SHIFT
25945. DA9062AA_LDO1_ILIM_MASK
25946. DA9062AA_LDO1_ILIM_SHIFT
25947. DA9062AA_LDO1_PD_DIS_MASK
25948. DA9062AA_LDO1_PD_DIS_SHIFT
25949. DA9062AA_LDO1_SL_A_MASK
25950. DA9062AA_LDO1_SL_A_SHIFT
25951. DA9062AA_LDO1_SL_B_MASK
25952. DA9062AA_LDO1_SL_B_SHIFT
25953. DA9062AA_LDO1_STEP_MASK
25954. DA9062AA_LDO1_STEP_SHIFT
25955. DA9062AA_LDO2_AUTO_MASK
25956. DA9062AA_LDO2_AUTO_SHIFT
25957. DA9062AA_LDO2_CONF_MASK
25958. DA9062AA_LDO2_CONF_SHIFT
25959. DA9062AA_LDO2_CONT
25960. DA9062AA_LDO2_EN_MASK
25961. DA9062AA_LDO2_EN_SHIFT
25962. DA9062AA_LDO2_GPI_MASK
25963. DA9062AA_LDO2_GPI_SHIFT
25964. DA9062AA_LDO2_ILIM_MASK
25965. DA9062AA_LDO2_ILIM_SHIFT
25966. DA9062AA_LDO2_PD_DIS_MASK
25967. DA9062AA_LDO2_PD_DIS_SHIFT
25968. DA9062AA_LDO2_SL_A_MASK
25969. DA9062AA_LDO2_SL_A_SHIFT
25970. DA9062AA_LDO2_SL_B_MASK
25971. DA9062AA_LDO2_SL_B_SHIFT
25972. DA9062AA_LDO2_STEP_MASK
25973. DA9062AA_LDO2_STEP_SHIFT
25974. DA9062AA_LDO3_AUTO_MASK
25975. DA9062AA_LDO3_AUTO_SHIFT
25976. DA9062AA_LDO3_CONF_MASK
25977. DA9062AA_LDO3_CONF_SHIFT
25978. DA9062AA_LDO3_CONT
25979. DA9062AA_LDO3_EN_MASK
25980. DA9062AA_LDO3_EN_SHIFT
25981. DA9062AA_LDO3_GPI_MASK
25982. DA9062AA_LDO3_GPI_SHIFT
25983. DA9062AA_LDO3_ILIM_MASK
25984. DA9062AA_LDO3_ILIM_SHIFT
25985. DA9062AA_LDO3_PD_DIS_MASK
25986. DA9062AA_LDO3_PD_DIS_SHIFT
25987. DA9062AA_LDO3_SL_A_MASK
25988. DA9062AA_LDO3_SL_A_SHIFT
25989. DA9062AA_LDO3_SL_B_MASK
25990. DA9062AA_LDO3_SL_B_SHIFT
25991. DA9062AA_LDO3_STEP_MASK
25992. DA9062AA_LDO3_STEP_SHIFT
25993. DA9062AA_LDO4_AUTO_MASK
25994. DA9062AA_LDO4_AUTO_SHIFT
25995. DA9062AA_LDO4_CONF_MASK
25996. DA9062AA_LDO4_CONF_SHIFT
25997. DA9062AA_LDO4_CONT
25998. DA9062AA_LDO4_EN_MASK
25999. DA9062AA_LDO4_EN_SHIFT
26000. DA9062AA_LDO4_GPI_MASK
26001. DA9062AA_LDO4_GPI_SHIFT
26002. DA9062AA_LDO4_ILIM_MASK
26003. DA9062AA_LDO4_ILIM_SHIFT
26004. DA9062AA_LDO4_PD_DIS_MASK
26005. DA9062AA_LDO4_PD_DIS_SHIFT
26006. DA9062AA_LDO4_SL_A_MASK
26007. DA9062AA_LDO4_SL_A_SHIFT
26008. DA9062AA_LDO4_SL_B_MASK
26009. DA9062AA_LDO4_SL_B_SHIFT
26010. DA9062AA_LDO4_STEP_MASK
26011. DA9062AA_LDO4_STEP_SHIFT
26012. DA9062AA_LDO_SD_MASK
26013. DA9062AA_LDO_SD_SHIFT
26014. DA9062AA_MAX_COUNT_MASK
26015. DA9062AA_MAX_COUNT_SHIFT
26016. DA9062AA_MONITOR_MASK
26017. DA9062AA_MONITOR_SHIFT
26018. DA9062AA_MRC_MASK
26019. DA9062AA_MRC_SHIFT
26020. DA9062AA_M_ALARM_MASK
26021. DA9062AA_M_ALARM_SHIFT
26022. DA9062AA_M_DVC_RDY_MASK
26023. DA9062AA_M_DVC_RDY_SHIFT
26024. DA9062AA_M_GPI0_MASK
26025. DA9062AA_M_GPI0_SHIFT
26026. DA9062AA_M_GPI1_MASK
26027. DA9062AA_M_GPI1_SHIFT
26028. DA9062AA_M_GPI2_MASK
26029. DA9062AA_M_GPI2_SHIFT
26030. DA9062AA_M_GPI3_MASK
26031. DA9062AA_M_GPI3_SHIFT
26032. DA9062AA_M_GPI4_MASK
26033. DA9062AA_M_GPI4_SHIFT
26034. DA9062AA_M_LDO_LIM_MASK
26035. DA9062AA_M_LDO_LIM_SHIFT
26036. DA9062AA_M_NONKEY_MASK
26037. DA9062AA_M_NONKEY_SHIFT
26038. DA9062AA_M_POWER1_EN_MASK
26039. DA9062AA_M_POWER1_EN_SHIFT
26040. DA9062AA_M_POWER_EN_MASK
26041. DA9062AA_M_POWER_EN_SHIFT
26042. DA9062AA_M_SEQ_RDY_MASK
26043. DA9062AA_M_SEQ_RDY_SHIFT
26044. DA9062AA_M_SYSTEM_EN_MASK
26045. DA9062AA_M_SYSTEM_EN_SHIFT
26046. DA9062AA_M_TEMP_MASK
26047. DA9062AA_M_TEMP_SHIFT
26048. DA9062AA_M_TICK_MASK
26049. DA9062AA_M_TICK_SHIFT
26050. DA9062AA_M_VDD_WARN_MASK
26051. DA9062AA_M_VDD_WARN_SHIFT
26052. DA9062AA_M_WDG_WARN_MASK
26053. DA9062AA_M_WDG_WARN_SHIFT
26054. DA9062AA_NFREEZE_MASK
26055. DA9062AA_NFREEZE_SHIFT
26056. DA9062AA_NIRQ_MODE_MASK
26057. DA9062AA_NIRQ_MODE_SHIFT
26058. DA9062AA_NONKEY_LOCK_MASK
26059. DA9062AA_NONKEY_LOCK_SHIFT
26060. DA9062AA_NONKEY_MASK
26061. DA9062AA_NONKEY_PIN_MASK
26062. DA9062AA_NONKEY_PIN_SHIFT
26063. DA9062AA_NONKEY_SHIFT
26064. DA9062AA_NRES_MODE_MASK
26065. DA9062AA_NRES_MODE_SHIFT
26066. DA9062AA_NSHUTDOWN_MASK
26067. DA9062AA_NSHUTDOWN_PU_MASK
26068. DA9062AA_NSHUTDOWN_PU_SHIFT
26069. DA9062AA_NSHUTDOWN_SHIFT
26070. DA9062AA_NXT_SEQ_START_MASK
26071. DA9062AA_NXT_SEQ_START_SHIFT
26072. DA9062AA_OSC_FRQ_MASK
26073. DA9062AA_OSC_FRQ_SHIFT
26074. DA9062AA_OTPREAD_EN_MASK
26075. DA9062AA_OTPREAD_EN_SHIFT
26076. DA9062AA_OUT32K_PAUSE_MASK
26077. DA9062AA_OUT32K_PAUSE_SHIFT
26078. DA9062AA_OUT_CLOCK_MASK
26079. DA9062AA_OUT_CLOCK_SHIFT
26080. DA9062AA_PAGE_CON
26081. DA9062AA_PAGE_MASK
26082. DA9062AA_PAGE_SHIFT
26083. DA9062AA_PART_DOWN_MASK
26084. DA9062AA_PART_DOWN_SHIFT
26085. DA9062AA_PD_DIS
26086. DA9062AA_PD_DIS_STEP_MASK
26087. DA9062AA_PD_DIS_STEP_SHIFT
26088. DA9062AA_PMCONT_DIS_MASK
26089. DA9062AA_PMCONT_DIS_SHIFT
26090. DA9062AA_PMIF_DIS_MASK
26091. DA9062AA_PMIF_DIS_SHIFT
26092. DA9062AA_PM_IF_FMP_MASK
26093. DA9062AA_PM_IF_FMP_SHIFT
26094. DA9062AA_PM_IF_HSM_MASK
26095. DA9062AA_PM_IF_HSM_SHIFT
26096. DA9062AA_PM_IF_V_MASK
26097. DA9062AA_PM_IF_V_SHIFT
26098. DA9062AA_PM_I_V_MASK
26099. DA9062AA_PM_I_V_SHIFT
26100. DA9062AA_PM_O_TYPE_MASK
26101. DA9062AA_PM_O_TYPE_SHIFT
26102. DA9062AA_POR_MASK
26103. DA9062AA_POR_SHIFT
26104. DA9062AA_POWER1_EN_MASK
26105. DA9062AA_POWER1_EN_SHIFT
26106. DA9062AA_POWER_END_MASK
26107. DA9062AA_POWER_END_SHIFT
26108. DA9062AA_POWER_EN_MASK
26109. DA9062AA_POWER_EN_SHIFT
26110. DA9062AA_RESET
26111. DA9062AA_RESET_DURATION_MASK
26112. DA9062AA_RESET_DURATION_SHIFT
26113. DA9062AA_RESET_EVENT_MASK
26114. DA9062AA_RESET_EVENT_SHIFT
26115. DA9062AA_RESET_TIMER_MASK
26116. DA9062AA_RESET_TIMER_SHIFT
26117. DA9062AA_REVERT_MASK
26118. DA9062AA_REVERT_SHIFT
26119. DA9062AA_RTC_CLOCK_MASK
26120. DA9062AA_RTC_CLOCK_SHIFT
26121. DA9062AA_RTC_EN_MASK
26122. DA9062AA_RTC_EN_SHIFT
26123. DA9062AA_RTC_MODE_PD_MASK
26124. DA9062AA_RTC_MODE_PD_SHIFT
26125. DA9062AA_RTC_MODE_SD_MASK
26126. DA9062AA_RTC_MODE_SD_SHIFT
26127. DA9062AA_RTC_READ_MASK
26128. DA9062AA_RTC_READ_SHIFT
26129. DA9062AA_SECONDS_A_MASK
26130. DA9062AA_SECONDS_A_SHIFT
26131. DA9062AA_SECONDS_B_MASK
26132. DA9062AA_SECONDS_B_SHIFT
26133. DA9062AA_SECONDS_C_MASK
26134. DA9062AA_SECONDS_C_SHIFT
26135. DA9062AA_SECONDS_D_MASK
26136. DA9062AA_SECONDS_D_SHIFT
26137. DA9062AA_SECOND_A
26138. DA9062AA_SECOND_B
26139. DA9062AA_SECOND_C
26140. DA9062AA_SECOND_D
26141. DA9062AA_SEQ
26142. DA9062AA_SEQ_A
26143. DA9062AA_SEQ_B
26144. DA9062AA_SEQ_DUMMY_MASK
26145. DA9062AA_SEQ_DUMMY_SHIFT
26146. DA9062AA_SEQ_POINTER_MASK
26147. DA9062AA_SEQ_POINTER_SHIFT
26148. DA9062AA_SEQ_TIMER
26149. DA9062AA_SEQ_TIME_MASK
26150. DA9062AA_SEQ_TIME_SHIFT
26151. DA9062AA_SHUTDOWN_MASK
26152. DA9062AA_SHUTDOWN_SHIFT
26153. DA9062AA_SHUT_DELAY_MASK
26154. DA9062AA_SHUT_DELAY_SHIFT
26155. DA9062AA_SLEW_RATE_MASK
26156. DA9062AA_SLEW_RATE_SHIFT
26157. DA9062AA_STABILISATION_TIME_MASK
26158. DA9062AA_STABILISATION_TIME_SHIFT
26159. DA9062AA_STANDBY_MASK
26160. DA9062AA_STANDBY_SHIFT
26161. DA9062AA_STATUS_A
26162. DA9062AA_STATUS_B
26163. DA9062AA_STATUS_D
26164. DA9062AA_SYSTEM_END_MASK
26165. DA9062AA_SYSTEM_END_SHIFT
26166. DA9062AA_SYSTEM_EN_MASK
26167. DA9062AA_SYSTEM_EN_RD_MASK
26168. DA9062AA_SYSTEM_EN_RD_SHIFT
26169. DA9062AA_SYSTEM_EN_SHIFT
26170. DA9062AA_TEMP_CRIT_MASK
26171. DA9062AA_TEMP_CRIT_SHIFT
26172. DA9062AA_TICK_ON_MASK
26173. DA9062AA_TICK_ON_SHIFT
26174. DA9062AA_TICK_TYPE_MASK
26175. DA9062AA_TICK_TYPE_SHIFT
26176. DA9062AA_TICK_WAKE_MASK
26177. DA9062AA_TICK_WAKE_SHIFT
26178. DA9062AA_TIME_OUT_MASK
26179. DA9062AA_TIME_OUT_SHIFT
26180. DA9062AA_TRIM_CLDR
26181. DA9062AA_TRIM_CLDR_MASK
26182. DA9062AA_TRIM_CLDR_SHIFT
26183. DA9062AA_TWDSCALE_MASK
26184. DA9062AA_TWDSCALE_SHIFT
26185. DA9062AA_TWD_ERROR_MASK
26186. DA9062AA_TWD_ERROR_SHIFT
26187. DA9062AA_TWOWIRE_TO_MASK
26188. DA9062AA_TWOWIRE_TO_SHIFT
26189. DA9062AA_VARIANT_ID
26190. DA9062AA_VBUCK1_A
26191. DA9062AA_VBUCK1_A_MASK
26192. DA9062AA_VBUCK1_A_SHIFT
26193. DA9062AA_VBUCK1_B
26194. DA9062AA_VBUCK1_B_MASK
26195. DA9062AA_VBUCK1_B_SHIFT
26196. DA9062AA_VBUCK1_GPI_MASK
26197. DA9062AA_VBUCK1_GPI_SHIFT
26198. DA9062AA_VBUCK1_SEL_MASK
26199. DA9062AA_VBUCK1_SEL_SHIFT
26200. DA9062AA_VBUCK2_A
26201. DA9062AA_VBUCK2_A_MASK
26202. DA9062AA_VBUCK2_A_SHIFT
26203. DA9062AA_VBUCK2_B
26204. DA9062AA_VBUCK2_B_MASK
26205. DA9062AA_VBUCK2_B_SHIFT
26206. DA9062AA_VBUCK2_GPI_MASK
26207. DA9062AA_VBUCK2_GPI_SHIFT
26208. DA9062AA_VBUCK2_SEL_MASK
26209. DA9062AA_VBUCK2_SEL_SHIFT
26210. DA9062AA_VBUCK3_A
26211. DA9062AA_VBUCK3_A_MASK
26212. DA9062AA_VBUCK3_A_SHIFT
26213. DA9062AA_VBUCK3_B
26214. DA9062AA_VBUCK3_B_MASK
26215. DA9062AA_VBUCK3_B_SHIFT
26216. DA9062AA_VBUCK3_GPI_MASK
26217. DA9062AA_VBUCK3_GPI_SHIFT
26218. DA9062AA_VBUCK3_SEL_MASK
26219. DA9062AA_VBUCK3_SEL_SHIFT
26220. DA9062AA_VBUCK4_A
26221. DA9062AA_VBUCK4_A_MASK
26222. DA9062AA_VBUCK4_A_SHIFT
26223. DA9062AA_VBUCK4_B
26224. DA9062AA_VBUCK4_B_MASK
26225. DA9062AA_VBUCK4_B_SHIFT
26226. DA9062AA_VBUCK4_GPI_MASK
26227. DA9062AA_VBUCK4_GPI_SHIFT
26228. DA9062AA_VBUCK4_SEL_MASK
26229. DA9062AA_VBUCK4_SEL_SHIFT
26230. DA9062AA_VDD_FAULT_ADJ_MASK
26231. DA9062AA_VDD_FAULT_ADJ_SHIFT
26232. DA9062AA_VDD_FAULT_MASK
26233. DA9062AA_VDD_FAULT_SHIFT
26234. DA9062AA_VDD_HYST_ADJ_MASK
26235. DA9062AA_VDD_HYST_ADJ_SHIFT
26236. DA9062AA_VDD_START_MASK
26237. DA9062AA_VDD_START_SHIFT
26238. DA9062AA_VLDO1_A
26239. DA9062AA_VLDO1_A_MASK
26240. DA9062AA_VLDO1_A_SHIFT
26241. DA9062AA_VLDO1_B
26242. DA9062AA_VLDO1_B_MASK
26243. DA9062AA_VLDO1_B_SHIFT
26244. DA9062AA_VLDO1_GPI_MASK
26245. DA9062AA_VLDO1_GPI_SHIFT
26246. DA9062AA_VLDO1_SEL_MASK
26247. DA9062AA_VLDO1_SEL_SHIFT
26248. DA9062AA_VLDO2_A
26249. DA9062AA_VLDO2_A_MASK
26250. DA9062AA_VLDO2_A_SHIFT
26251. DA9062AA_VLDO2_B
26252. DA9062AA_VLDO2_B_MASK
26253. DA9062AA_VLDO2_B_SHIFT
26254. DA9062AA_VLDO2_GPI_MASK
26255. DA9062AA_VLDO2_GPI_SHIFT
26256. DA9062AA_VLDO2_SEL_MASK
26257. DA9062AA_VLDO2_SEL_SHIFT
26258. DA9062AA_VLDO3_A
26259. DA9062AA_VLDO3_A_MASK
26260. DA9062AA_VLDO3_A_SHIFT
26261. DA9062AA_VLDO3_B
26262. DA9062AA_VLDO3_B_MASK
26263. DA9062AA_VLDO3_B_SHIFT
26264. DA9062AA_VLDO3_GPI_MASK
26265. DA9062AA_VLDO3_GPI_SHIFT
26266. DA9062AA_VLDO3_SEL_MASK
26267. DA9062AA_VLDO3_SEL_SHIFT
26268. DA9062AA_VLDO4_A
26269. DA9062AA_VLDO4_A_MASK
26270. DA9062AA_VLDO4_A_SHIFT
26271. DA9062AA_VLDO4_B
26272. DA9062AA_VLDO4_B_MASK
26273. DA9062AA_VLDO4_B_SHIFT
26274. DA9062AA_VLDO4_GPI_MASK
26275. DA9062AA_VLDO4_GPI_SHIFT
26276. DA9062AA_VLDO4_SEL_MASK
26277. DA9062AA_VLDO4_SEL_SHIFT
26278. DA9062AA_VLDO_A_MIN_SEL
26279. DA9062AA_VRC_MASK
26280. DA9062AA_VRC_SHIFT
26281. DA9062AA_V_LOCK_MASK
26282. DA9062AA_V_LOCK_SHIFT
26283. DA9062AA_WAIT
26284. DA9062AA_WAIT_DIR_MASK
26285. DA9062AA_WAIT_DIR_SHIFT
26286. DA9062AA_WAIT_MODE_MASK
26287. DA9062AA_WAIT_MODE_SHIFT
26288. DA9062AA_WAIT_SHUT_MASK
26289. DA9062AA_WAIT_SHUT_SHIFT
26290. DA9062AA_WAIT_STEP_MASK
26291. DA9062AA_WAIT_STEP_SHIFT
26292. DA9062AA_WAIT_TIME_MASK
26293. DA9062AA_WAIT_TIME_SHIFT
26294. DA9062AA_WAKE_UP_MASK
26295. DA9062AA_WAKE_UP_SHIFT
26296. DA9062AA_WATCHDOG_MASK
26297. DA9062AA_WATCHDOG_PD_MASK
26298. DA9062AA_WATCHDOG_PD_SHIFT
26299. DA9062AA_WATCHDOG_SD_MASK
26300. DA9062AA_WATCHDOG_SD_SHIFT
26301. DA9062AA_WATCHDOG_SHIFT
26302. DA9062AA_WDG_MODE_MASK
26303. DA9062AA_WDG_MODE_SHIFT
26304. DA9062AA_WRITE_MODE_MASK
26305. DA9062AA_WRITE_MODE_SHIFT
26306. DA9062AA_nONKEY_SD_MASK
26307. DA9062AA_nONKEY_SD_SHIFT
26308. DA9062_DEFAULT_POLLING_MS_PERIOD
26309. DA9062_I2C_PAGE_SEL_SHIFT
26310. DA9062_ID_BUCK1
26311. DA9062_ID_BUCK2
26312. DA9062_ID_BUCK3
26313. DA9062_ID_BUCK4
26314. DA9062_ID_LDO1
26315. DA9062_ID_LDO2
26316. DA9062_ID_LDO3
26317. DA9062_ID_LDO4
26318. DA9062_IRQ_ALARM
26319. DA9062_IRQ_DVC_RDY
26320. DA9062_IRQ_GPI0
26321. DA9062_IRQ_GPI1
26322. DA9062_IRQ_GPI2
26323. DA9062_IRQ_GPI3
26324. DA9062_IRQ_GPI4
26325. DA9062_IRQ_LDO_LIM
26326. DA9062_IRQ_ONKEY
26327. DA9062_IRQ_SEQ_RDY
26328. DA9062_IRQ_TEMP
26329. DA9062_IRQ_TICK
26330. DA9062_IRQ_VDD_WARN
26331. DA9062_IRQ_WDG_WARN
26332. DA9062_MAX_POLLING_MS_PERIOD
26333. DA9062_MAX_REGULATORS
26334. DA9062_MILLI_CELSIUS
26335. DA9062_MIN_POLLING_MS_PERIOD
26336. DA9062_NUM_IRQ
26337. DA9062_PMIC_DEVICE_ID
26338. DA9062_PMIC_VARIANT_MRC_AA
26339. DA9062_PMIC_VARIANT_VRC_DA9061
26340. DA9062_PMIC_VARIANT_VRC_DA9062
26341. DA9062_REG_EVENT_A_OFFSET
26342. DA9062_REG_EVENT_B_OFFSET
26343. DA9062_REG_EVENT_C_OFFSET
26344. DA9062_RESET_PROTECTION_MS
26345. DA9062_TWDSCALE_DISABLE
26346. DA9062_TWDSCALE_MAX
26347. DA9062_TWDSCALE_MIN
26348. DA9062_WDG_DEFAULT_TIMEOUT
26349. DA9062_WDT_MAX_TIMEOUT
26350. DA9062_WDT_MIN_TIMEOUT
26351. DA9063_ADC_AD1_ISRC_EN
26352. DA9063_ADC_AD2_ISRC_EN
26353. DA9063_ADC_AD3_ISRC_EN
26354. DA9063_ADC_AUTO_AD1_EN
26355. DA9063_ADC_AUTO_AD2_EN
26356. DA9063_ADC_AUTO_AD3_EN
26357. DA9063_ADC_AUTO_VSYS_EN
26358. DA9063_ADC_MAN
26359. DA9063_ADC_MODE
26360. DA9063_ADC_MUX_ADCIN1
26361. DA9063_ADC_MUX_ADCIN2
26362. DA9063_ADC_MUX_ADCIN3
26363. DA9063_ADC_MUX_LDO_G1
26364. DA9063_ADC_MUX_LDO_G2
26365. DA9063_ADC_MUX_LDO_G3
26366. DA9063_ADC_MUX_MASK
26367. DA9063_ADC_MUX_T_SENSE
26368. DA9063_ADC_MUX_VBBAT
26369. DA9063_ADC_MUX_VSYS
26370. DA9063_ADC_RES_L_BITS
26371. DA9063_ADC_RES_L_MASK
26372. DA9063_ADC_RES_M_BITS
26373. DA9063_ADC_RES_M_MASK
26374. DA9063_ADC_VAL_MASK
26375. DA9063_AD_REG_ALARM_D
26376. DA9063_AD_REG_ALARM_H
26377. DA9063_AD_REG_ALARM_MI
26378. DA9063_AD_REG_ALARM_MO
26379. DA9063_AD_REG_ALARM_Y
26380. DA9063_AD_REG_GP_ID_0
26381. DA9063_AD_REG_GP_ID_1
26382. DA9063_AD_REG_GP_ID_10
26383. DA9063_AD_REG_GP_ID_11
26384. DA9063_AD_REG_GP_ID_12
26385. DA9063_AD_REG_GP_ID_13
26386. DA9063_AD_REG_GP_ID_14
26387. DA9063_AD_REG_GP_ID_15
26388. DA9063_AD_REG_GP_ID_16
26389. DA9063_AD_REG_GP_ID_17
26390. DA9063_AD_REG_GP_ID_18
26391. DA9063_AD_REG_GP_ID_19
26392. DA9063_AD_REG_GP_ID_2
26393. DA9063_AD_REG_GP_ID_3
26394. DA9063_AD_REG_GP_ID_4
26395. DA9063_AD_REG_GP_ID_5
26396. DA9063_AD_REG_GP_ID_6
26397. DA9063_AD_REG_GP_ID_7
26398. DA9063_AD_REG_GP_ID_8
26399. DA9063_AD_REG_GP_ID_9
26400. DA9063_AD_REG_MON_REG_1
26401. DA9063_AD_REG_MON_REG_2
26402. DA9063_AD_REG_MON_REG_3
26403. DA9063_AD_REG_MON_REG_4
26404. DA9063_AD_REG_MON_REG_5
26405. DA9063_AD_REG_MON_REG_6
26406. DA9063_AD_REG_SECOND_A
26407. DA9063_AD_REG_SECOND_B
26408. DA9063_AD_REG_SECOND_C
26409. DA9063_AD_REG_SECOND_D
26410. DA9063_AD_REG_TRIM_CLDR
26411. DA9063_ALARM_DAY_MASK
26412. DA9063_ALARM_HOUR_MASK
26413. DA9063_ALARM_MIN_MASK
26414. DA9063_ALARM_MONTH_MASK
26415. DA9063_ALARM_ON
26416. DA9063_ALARM_STATUS_ALARM
26417. DA9063_ALARM_STATUS_TICK
26418. DA9063_ALARM_YEAR_MASK
26419. DA9063_AUTO_BOOT
26420. DA9063_BBAT_DIS
26421. DA9063_BB_ALARM_S_MASK
26422. DA9063_BB_BUCK_SLOWSTART
26423. DA9063_BB_CLDR_PAUSE
26424. DA9063_BB_REG_ALARM_D
26425. DA9063_BB_REG_ALARM_H
26426. DA9063_BB_REG_ALARM_MI
26427. DA9063_BB_REG_ALARM_MO
26428. DA9063_BB_REG_ALARM_S
26429. DA9063_BB_REG_ALARM_Y
26430. DA9063_BB_REG_CONFIG_M
26431. DA9063_BB_REG_CONFIG_N
26432. DA9063_BB_REG_GP_ID_0
26433. DA9063_BB_REG_GP_ID_1
26434. DA9063_BB_REG_GP_ID_10
26435. DA9063_BB_REG_GP_ID_11
26436. DA9063_BB_REG_GP_ID_12
26437. DA9063_BB_REG_GP_ID_13
26438. DA9063_BB_REG_GP_ID_14
26439. DA9063_BB_REG_GP_ID_15
26440. DA9063_BB_REG_GP_ID_16
26441. DA9063_BB_REG_GP_ID_17
26442. DA9063_BB_REG_GP_ID_18
26443. DA9063_BB_REG_GP_ID_19
26444. DA9063_BB_REG_GP_ID_2
26445. DA9063_BB_REG_GP_ID_3
26446. DA9063_BB_REG_GP_ID_4
26447. DA9063_BB_REG_GP_ID_5
26448. DA9063_BB_REG_GP_ID_6
26449. DA9063_BB_REG_GP_ID_7
26450. DA9063_BB_REG_GP_ID_8
26451. DA9063_BB_REG_GP_ID_9
26452. DA9063_BB_REG_MON_REG_1
26453. DA9063_BB_REG_MON_REG_2
26454. DA9063_BB_REG_MON_REG_3
26455. DA9063_BB_REG_MON_REG_4
26456. DA9063_BB_REG_MON_REG_5
26457. DA9063_BB_REG_MON_REG_6
26458. DA9063_BB_REG_SECOND_A
26459. DA9063_BB_REG_SECOND_B
26460. DA9063_BB_REG_SECOND_C
26461. DA9063_BB_REG_SECOND_D
26462. DA9063_BB_REG_TRIM_CLDR
26463. DA9063_BB_RESET_BLINKING
26464. DA9063_BCORE1_ILIM_MASK
26465. DA9063_BCORE1_OD
26466. DA9063_BCORE2_ILIM_MASK
26467. DA9063_BCORE2_OD
26468. DA9063_BCORE_MERGE
26469. DA9063_BIO_ILIM_MASK
26470. DA9063_BLINK_DUR_10MS
26471. DA9063_BLINK_DUR_20MS
26472. DA9063_BLINK_DUR_20MSDBL
26473. DA9063_BLINK_DUR_40MS
26474. DA9063_BLINK_DUR_MASK
26475. DA9063_BLINK_FRQ_0S18
26476. DA9063_BLINK_FRQ_0S18_VDD
26477. DA9063_BLINK_FRQ_1S0
26478. DA9063_BLINK_FRQ_2S0
26479. DA9063_BLINK_FRQ_2S0_VDD
26480. DA9063_BLINK_FRQ_4S0
26481. DA9063_BLINK_FRQ_4S0_VDD
26482. DA9063_BLINK_FRQ_MASK
26483. DA9063_BLINK_FRQ_OFF
26484. DA9063_BMEM_ILIM_MASK
26485. DA9063_BPERI_ILIM_MASK
26486. DA9063_BPRO_ILIM_MASK
26487. DA9063_BPRO_OD
26488. DA9063_BPRO_VTTR_EN
26489. DA9063_BPRO_VTT_EN
26490. DA9063_BUCK
26491. DA9063_BUCK_COMMON_FIELDS
26492. DA9063_BUCK_CONF
26493. DA9063_BUCK_EN
26494. DA9063_BUCK_FB_MASK
26495. DA9063_BUCK_GPI_GPIO1
26496. DA9063_BUCK_GPI_GPIO13
26497. DA9063_BUCK_GPI_GPIO2
26498. DA9063_BUCK_GPI_MASK
26499. DA9063_BUCK_GPI_OFF
26500. DA9063_BUCK_MERGE
26501. DA9063_BUCK_MODE_AUTO
26502. DA9063_BUCK_MODE_MANUAL
26503. DA9063_BUCK_MODE_MASK
26504. DA9063_BUCK_MODE_SLEEP
26505. DA9063_BUCK_MODE_SYNC
26506. DA9063_BUCK_PD_DIS_MASK
26507. DA9063_BUCK_SL
26508. DA9063_CHG_SEL
26509. DA9063_CHIP_VARIANT_SHIFT
26510. DA9063_COMP1V2_EN
26511. DA9063_COMP_1V2
26512. DA9063_CORE_SW_CONF
26513. DA9063_CORE_SW_EN
26514. DA9063_CORE_SW_GPI_GPIO1
26515. DA9063_CORE_SW_GPI_GPIO13
26516. DA9063_CORE_SW_GPI_GPIO2
26517. DA9063_CORE_SW_GPI_MASK
26518. DA9063_CORE_SW_GPI_OFF
26519. DA9063_CORE_SW_INTERNAL
26520. DA9063_COUNT_DAY_MASK
26521. DA9063_COUNT_HOUR_MASK
26522. DA9063_COUNT_MIN_MASK
26523. DA9063_COUNT_MONTH_MASK
26524. DA9063_COUNT_SEC_MASK
26525. DA9063_COUNT_YEAR_MASK
26526. DA9063_CP_EN
26527. DA9063_CP_EN_MODE
26528. DA9063_CRYSTAL
26529. DA9063_DEBOUNCING_0MS1
26530. DA9063_DEBOUNCING_1024MS
26531. DA9063_DEBOUNCING_10MS24
26532. DA9063_DEBOUNCING_1MS
26533. DA9063_DEBOUNCING_256MS
26534. DA9063_DEBOUNCING_512MS
26535. DA9063_DEBOUNCING_51MS2
26536. DA9063_DEBOUNCING_MASK
26537. DA9063_DEBOUNCING_OFF
26538. DA9063_DEF_SUPPLY
26539. DA9063_DELAY_MODE
26540. DA9063_DRVNAME_CORE
26541. DA9063_DRVNAME_HWMON
26542. DA9063_DRVNAME_LEDS
26543. DA9063_DRVNAME_ONKEY
26544. DA9063_DRVNAME_REGULATORS
26545. DA9063_DRVNAME_RTC
26546. DA9063_DRVNAME_VIBRATION
26547. DA9063_DRVNAME_WATCHDOG
26548. DA9063_DVC_BUSY
26549. DA9063_ECO_MODE
26550. DA9063_EVENTS_B
26551. DA9063_EVENTS_C
26552. DA9063_EVENTS_D
26553. DA9063_EVENT_REG_NUM
26554. DA9063_E_ADC_RDY
26555. DA9063_E_ALARM
26556. DA9063_E_COMP_1V2
26557. DA9063_E_DVC_RDY
26558. DA9063_E_GPI0
26559. DA9063_E_GPI1
26560. DA9063_E_GPI10
26561. DA9063_E_GPI11
26562. DA9063_E_GPI12
26563. DA9063_E_GPI13
26564. DA9063_E_GPI14
26565. DA9063_E_GPI15
26566. DA9063_E_GPI2
26567. DA9063_E_GPI3
26568. DA9063_E_GPI4
26569. DA9063_E_GPI5
26570. DA9063_E_GPI6
26571. DA9063_E_GPI7
26572. DA9063_E_GPI8
26573. DA9063_E_GPI9
26574. DA9063_E_LDO_LIM
26575. DA9063_E_NONKEY
26576. DA9063_E_REG_UVOV
26577. DA9063_E_SEQ_RDY
26578. DA9063_E_TEMP
26579. DA9063_E_TICK
26580. DA9063_E_VDD_MON
26581. DA9063_E_VDD_WARN
26582. DA9063_E_WAKE
26583. DA9063_GPADC_PAUSE
26584. DA9063_GPI0
26585. DA9063_GPI1
26586. DA9063_GPI10
26587. DA9063_GPI11
26588. DA9063_GPI12
26589. DA9063_GPI13
26590. DA9063_GPI14
26591. DA9063_GPI15
26592. DA9063_GPI2
26593. DA9063_GPI3
26594. DA9063_GPI4
26595. DA9063_GPI5
26596. DA9063_GPI6
26597. DA9063_GPI7
26598. DA9063_GPI8
26599. DA9063_GPI9
26600. DA9063_GPIO0_MODE
26601. DA9063_GPIO0_NO_WAKEUP
26602. DA9063_GPIO0_PIN_ADCIN1
26603. DA9063_GPIO0_PIN_GPI
26604. DA9063_GPIO0_PIN_GPO
26605. DA9063_GPIO0_PIN_GPO_OD
26606. DA9063_GPIO0_PIN_MASK
26607. DA9063_GPIO0_TYPE
26608. DA9063_GPIO0_TYPE_GPI_ACT_HIGH
26609. DA9063_GPIO0_TYPE_GPI_ACT_LOW
26610. DA9063_GPIO0_TYPE_GPO_VDD_IO1
26611. DA9063_GPIO0_TYPE_GPO_VDD_IO2
26612. DA9063_GPIO10_MODE
26613. DA9063_GPIO10_NO_WAKEUP
26614. DA9063_GPIO10_PIN_GPI
26615. DA9063_GPIO10_PIN_GPI_PWR1_EN
26616. DA9063_GPIO10_PIN_GPO
26617. DA9063_GPIO10_PIN_GPO_OD
26618. DA9063_GPIO10_PIN_MASK
26619. DA9063_GPIO10_TYPE
26620. DA9063_GPIO10_TYPE_GPI_ACT_HIGH
26621. DA9063_GPIO10_TYPE_GPI_ACT_LOW
26622. DA9063_GPIO10_TYPE_GPO_VDD_IO1
26623. DA9063_GPIO10_TYPE_GPO_VDD_IO2
26624. DA9063_GPIO11_MODE
26625. DA9063_GPIO11_MODE_LED_ACT_HIGH
26626. DA9063_GPIO11_MODE_LED_ACT_LOW
26627. DA9063_GPIO11_NO_WAKEUP
26628. DA9063_GPIO11_PIN_GPI
26629. DA9063_GPIO11_PIN_GPO
26630. DA9063_GPIO11_PIN_GPO_OD
26631. DA9063_GPIO11_PIN_GPO_PSS
26632. DA9063_GPIO11_PIN_MASK
26633. DA9063_GPIO11_TYPE
26634. DA9063_GPIO11_TYPE_GPI_ACT_HIGH
26635. DA9063_GPIO11_TYPE_GPI_ACT_LOW
26636. DA9063_GPIO11_TYPE_GPO_VDD_IO1
26637. DA9063_GPIO11_TYPE_GPO_VDD_IO2
26638. DA9063_GPIO12_MODE
26639. DA9063_GPIO12_NO_WAKEUP
26640. DA9063_GPIO12_PIN_GPI
26641. DA9063_GPIO12_PIN_GPO
26642. DA9063_GPIO12_PIN_MASK
26643. DA9063_GPIO12_PIN_NVDDFLT_OUT
26644. DA9063_GPIO12_PIN_VSYSMON_OUT
26645. DA9063_GPIO12_TYPE
26646. DA9063_GPIO12_TYPE_GPI_ACT_HIGH
26647. DA9063_GPIO12_TYPE_GPI_ACT_LOW
26648. DA9063_GPIO12_TYPE_GPO_VDD_IO1
26649. DA9063_GPIO12_TYPE_GPO_VDD_IO2
26650. DA9063_GPIO13_MODE
26651. DA9063_GPIO13_NO_WAKEUP
26652. DA9063_GPIO13_PIN_GPFB1_OUT
26653. DA9063_GPIO13_PIN_GPFB1_OUTOD
26654. DA9063_GPIO13_PIN_GPI
26655. DA9063_GPIO13_PIN_GPO
26656. DA9063_GPIO13_PIN_MASK
26657. DA9063_GPIO13_TYPE
26658. DA9063_GPIO13_TYPE_GPFB1_OUT
26659. DA9063_GPIO13_TYPE_GPFB1_OUTOD
26660. DA9063_GPIO13_TYPE_GPI
26661. DA9063_GPIO13_TYPE_GPO
26662. DA9063_GPIO14_MODE
26663. DA9063_GPIO14_MODE_LED_ACT_HIGH
26664. DA9063_GPIO14_MODE_LED_ACT_LOW
26665. DA9063_GPIO14_NO_WAKEUP
26666. DA9063_GPIO14_PIN_GPI
26667. DA9063_GPIO14_PIN_GPO
26668. DA9063_GPIO14_PIN_GPO_OD
26669. DA9063_GPIO14_PIN_HS2DATA
26670. DA9063_GPIO14_PIN_MASK
26671. DA9063_GPIO14_TYPE
26672. DA9063_GPIO14_TYPE_GPI_ACT_HIGH
26673. DA9063_GPIO14_TYPE_GPI_ACT_LOW
26674. DA9063_GPIO14_TYPE_GPO_VDD_IO1
26675. DA9063_GPIO14_TYPE_GPO_VDD_IO2
26676. DA9063_GPIO15_MODE
26677. DA9063_GPIO15_MODE_LED_ACT_HIGH
26678. DA9063_GPIO15_MODE_LED_ACT_LOW
26679. DA9063_GPIO15_NO_WAKEUP
26680. DA9063_GPIO15_PIN_GPI
26681. DA9063_GPIO15_PIN_GPO
26682. DA9063_GPIO15_PIN_GPO_OD
26683. DA9063_GPIO15_PIN_MASK
26684. DA9063_GPIO15_TYPE
26685. DA9063_GPIO15_TYPE_GPFB1_OUT
26686. DA9063_GPIO15_TYPE_GPFB1_OUTOD
26687. DA9063_GPIO15_TYPE_GPI
26688. DA9063_GPIO15_TYPE_GPO
26689. DA9063_GPIO1_MODE
26690. DA9063_GPIO1_NO_WAKEUP
26691. DA9063_GPIO1_PIN_ADCIN2_COMP
26692. DA9063_GPIO1_PIN_GPI
26693. DA9063_GPIO1_PIN_GPO
26694. DA9063_GPIO1_PIN_GPO_OD
26695. DA9063_GPIO1_PIN_MASK
26696. DA9063_GPIO1_TYPE
26697. DA9063_GPIO1_TYPE_GPI_ACT_HIGH
26698. DA9063_GPIO1_TYPE_GPI_ACT_LOW
26699. DA9063_GPIO1_TYPE_GPO_VDD_IO1
26700. DA9063_GPIO1_TYPE_GPO_VDD_IO2
26701. DA9063_GPIO2_MODE
26702. DA9063_GPIO2_NO_WAKEUP
26703. DA9063_GPIO2_PIN_ADCIN3
26704. DA9063_GPIO2_PIN_GPI
26705. DA9063_GPIO2_PIN_GPO
26706. DA9063_GPIO2_PIN_GPO_PSS
26707. DA9063_GPIO2_PIN_MASK
26708. DA9063_GPIO2_TYPE
26709. DA9063_GPIO2_TYPE_GPI_ACT_HIGH
26710. DA9063_GPIO2_TYPE_GPI_ACT_LOW
26711. DA9063_GPIO2_TYPE_GPO_VDD_IO1
26712. DA9063_GPIO2_TYPE_GPO_VDD_IO2
26713. DA9063_GPIO3_MODE
26714. DA9063_GPIO3_NO_WAKEUP
26715. DA9063_GPIO3_PIN_CORE_SW_G
26716. DA9063_GPIO3_PIN_GPI
26717. DA9063_GPIO3_PIN_GPO
26718. DA9063_GPIO3_PIN_GPO_OD
26719. DA9063_GPIO3_PIN_MASK
26720. DA9063_GPIO3_TYPE
26721. DA9063_GPIO3_TYPE_GPI_ACT_HIGH
26722. DA9063_GPIO3_TYPE_GPI_ACT_LOW
26723. DA9063_GPIO3_TYPE_GPO_VDD_IO1
26724. DA9063_GPIO3_TYPE_GPO_VDD_IO2
26725. DA9063_GPIO4_MODE
26726. DA9063_GPIO4_NO_WAKEUP
26727. DA9063_GPIO4_PIN_CORE_SW_S
26728. DA9063_GPIO4_PIN_GPI
26729. DA9063_GPIO4_PIN_GPO
26730. DA9063_GPIO4_PIN_GPO_OD
26731. DA9063_GPIO4_PIN_MASK
26732. DA9063_GPIO4_TYPE
26733. DA9063_GPIO4_TYPE_GPI_ACT_HIGH
26734. DA9063_GPIO4_TYPE_GPI_ACT_LOW
26735. DA9063_GPIO4_TYPE_GPO_VDD_IO1
26736. DA9063_GPIO4_TYPE_GPO_VDD_IO2
26737. DA9063_GPIO5_MODE
26738. DA9063_GPIO5_NO_WAKEUP
26739. DA9063_GPIO5_PIN_GPI
26740. DA9063_GPIO5_PIN_GPO
26741. DA9063_GPIO5_PIN_GPO_OD
26742. DA9063_GPIO5_PIN_MASK
26743. DA9063_GPIO5_PIN_PERI_SW_G
26744. DA9063_GPIO5_TYPE
26745. DA9063_GPIO5_TYPE_GPI_ACT_HIGH
26746. DA9063_GPIO5_TYPE_GPI_ACT_LOW
26747. DA9063_GPIO5_TYPE_GPO_VDD_IO1
26748. DA9063_GPIO5_TYPE_GPO_VDD_IO2
26749. DA9063_GPIO6_MODE
26750. DA9063_GPIO6_NO_WAKEUP
26751. DA9063_GPIO6_PIN_GPI
26752. DA9063_GPIO6_PIN_GPO
26753. DA9063_GPIO6_PIN_GPO_OD
26754. DA9063_GPIO6_PIN_MASK
26755. DA9063_GPIO6_PIN_PERI_SW_S
26756. DA9063_GPIO6_TYPE
26757. DA9063_GPIO6_TYPE_GPI_ACT_HIGH
26758. DA9063_GPIO6_TYPE_GPI_ACT_LOW
26759. DA9063_GPIO6_TYPE_GPO_VDD_IO1
26760. DA9063_GPIO6_TYPE_GPO_VDD_IO2
26761. DA9063_GPIO7_MODE
26762. DA9063_GPIO7_NO_WAKEUP
26763. DA9063_GPIO7_PIN_GPI
26764. DA9063_GPIO7_PIN_GPO
26765. DA9063_GPIO7_PIN_GPO_PSS
26766. DA9063_GPIO7_PIN_MASK
26767. DA9063_GPIO7_TYPE
26768. DA9063_GPIO7_TYPE_GPI_ACT_HIGH
26769. DA9063_GPIO7_TYPE_GPI_ACT_LOW
26770. DA9063_GPIO7_TYPE_GPO_VDD_IO1
26771. DA9063_GPIO7_TYPE_GPO_VDD_IO2
26772. DA9063_GPIO8_MODE
26773. DA9063_GPIO8_NO_WAKEUP
26774. DA9063_GPIO8_PIN_GPI
26775. DA9063_GPIO8_PIN_GPI_SYS_EN
26776. DA9063_GPIO8_PIN_GPO
26777. DA9063_GPIO8_PIN_GPO_PSS
26778. DA9063_GPIO8_PIN_MASK
26779. DA9063_GPIO8_TYPE
26780. DA9063_GPIO8_TYPE_GPI_ACT_HIGH
26781. DA9063_GPIO8_TYPE_GPI_ACT_LOW
26782. DA9063_GPIO8_TYPE_GPO_VDD_IO1
26783. DA9063_GPIO8_TYPE_GPO_VDD_IO2
26784. DA9063_GPIO9_MODE
26785. DA9063_GPIO9_NO_WAKEUP
26786. DA9063_GPIO9_PIN_GPI
26787. DA9063_GPIO9_PIN_GPI_PWR_EN
26788. DA9063_GPIO9_PIN_GPO
26789. DA9063_GPIO9_PIN_GPO_PSS
26790. DA9063_GPIO9_PIN_MASK
26791. DA9063_GPIO9_TYPE
26792. DA9063_GPIO9_TYPE_GPI_ACT_HIGH
26793. DA9063_GPIO9_TYPE_GPI_ACT_LOW
26794. DA9063_GPIO9_TYPE_GPO_VDD_IO1
26795. DA9063_GPIO9_TYPE_GPO_VDD_IO2
26796. DA9063_GPIO_DIM
26797. DA9063_GPIO_PWM_MASK
26798. DA9063_GPI_DIS
26799. DA9063_HS2WIRE_DIS
26800. DA9063_I2C_PAGE_SEL_SHIFT
26801. DA9063_ID_BCORE1
26802. DA9063_ID_BCORE2
26803. DA9063_ID_BCORES_MERGED
26804. DA9063_ID_BIO
26805. DA9063_ID_BMEM
26806. DA9063_ID_BMEM_BIO_MERGED
26807. DA9063_ID_BPERI
26808. DA9063_ID_BPRO
26809. DA9063_ID_LDO1
26810. DA9063_ID_LDO10
26811. DA9063_ID_LDO11
26812. DA9063_ID_LDO2
26813. DA9063_ID_LDO3
26814. DA9063_ID_LDO4
26815. DA9063_ID_LDO5
26816. DA9063_ID_LDO6
26817. DA9063_ID_LDO7
26818. DA9063_ID_LDO8
26819. DA9063_ID_LDO9
26820. DA9063_IRQ_ADC_RDY
26821. DA9063_IRQ_ALARM
26822. DA9063_IRQ_COMP_1V2
26823. DA9063_IRQ_DVC_RDY
26824. DA9063_IRQ_GPI0
26825. DA9063_IRQ_GPI1
26826. DA9063_IRQ_GPI10
26827. DA9063_IRQ_GPI11
26828. DA9063_IRQ_GPI12
26829. DA9063_IRQ_GPI13
26830. DA9063_IRQ_GPI14
26831. DA9063_IRQ_GPI15
26832. DA9063_IRQ_GPI2
26833. DA9063_IRQ_GPI3
26834. DA9063_IRQ_GPI4
26835. DA9063_IRQ_GPI5
26836. DA9063_IRQ_GPI6
26837. DA9063_IRQ_GPI7
26838. DA9063_IRQ_GPI8
26839. DA9063_IRQ_GPI9
26840. DA9063_IRQ_LDO_LIM
26841. DA9063_IRQ_ONKEY
26842. DA9063_IRQ_REG_UVOV
26843. DA9063_IRQ_SEQ_RDY
26844. DA9063_IRQ_TEMP
26845. DA9063_IRQ_TICK
26846. DA9063_IRQ_VDD_MON
26847. DA9063_IRQ_WAKE
26848. DA9063_IRQ_WARN
26849. DA9063_KEY_RESET
26850. DA9063_LDO
26851. DA9063_LDO11_LIM
26852. DA9063_LDO3_LIM
26853. DA9063_LDO4_LIM
26854. DA9063_LDO7_LIM
26855. DA9063_LDO8_LIM
26856. DA9063_LDO8_MODE_LDO
26857. DA9063_LDO8_MODE_MASK
26858. DA9063_LDO8_MODE_VIBR
26859. DA9063_LDO_CONF
26860. DA9063_LDO_EN
26861. DA9063_LDO_GPI_GPIO1
26862. DA9063_LDO_GPI_GPIO13
26863. DA9063_LDO_GPI_GPIO2
26864. DA9063_LDO_GPI_MASK
26865. DA9063_LDO_GPI_OFF
26866. DA9063_LDO_PD_DIS
26867. DA9063_LDO_SL
26868. DA9063_MERGE_SENSE_GPIO4
26869. DA9063_MERGE_SENSE_GP_FB2
26870. DA9063_MERGE_SENSE_MASK
26871. DA9063_MONITOR
26872. DA9063_MON_A10_IDX_LDO10
26873. DA9063_MON_A10_IDX_LDO6
26874. DA9063_MON_A10_IDX_LDO7
26875. DA9063_MON_A10_IDX_LDO8
26876. DA9063_MON_A10_IDX_LDO9
26877. DA9063_MON_A10_IDX_MASK
26878. DA9063_MON_A10_IDX_NONE
26879. DA9063_MON_A8_IDX_BCORE1
26880. DA9063_MON_A8_IDX_BCORE2
26881. DA9063_MON_A8_IDX_BPRO
26882. DA9063_MON_A8_IDX_LDO11
26883. DA9063_MON_A8_IDX_LDO3
26884. DA9063_MON_A8_IDX_LDO4
26885. DA9063_MON_A8_IDX_MASK
26886. DA9063_MON_A8_IDX_NONE
26887. DA9063_MON_A9_IDX_BIO
26888. DA9063_MON_A9_IDX_BMEM
26889. DA9063_MON_A9_IDX_BPERI
26890. DA9063_MON_A9_IDX_LDO1
26891. DA9063_MON_A9_IDX_LDO2
26892. DA9063_MON_A9_IDX_LDO5
26893. DA9063_MON_A9_IDX_MASK
26894. DA9063_MON_A9_IDX_NONE
26895. DA9063_M_ADC_RDY
26896. DA9063_M_ALARM
26897. DA9063_M_COMP_1V2
26898. DA9063_M_DVC_RDY
26899. DA9063_M_GPI0
26900. DA9063_M_GPI1
26901. DA9063_M_GPI10
26902. DA9063_M_GPI11
26903. DA9063_M_GPI12
26904. DA9063_M_GPI13
26905. DA9063_M_GPI14
26906. DA9063_M_GPI15
26907. DA9063_M_GPI2
26908. DA9063_M_GPI3
26909. DA9063_M_GPI4
26910. DA9063_M_GPI5
26911. DA9063_M_GPI6
26912. DA9063_M_GPI7
26913. DA9063_M_GPI8
26914. DA9063_M_GPI9
26915. DA9063_M_LDO_LIM
26916. DA9063_M_ONKEY
26917. DA9063_M_POWER1_EN
26918. DA9063_M_POWER_EN
26919. DA9063_M_SEQ_RDY
26920. DA9063_M_SYSTEM_EN
26921. DA9063_M_TEMP
26922. DA9063_M_TICK
26923. DA9063_M_UVOV
26924. DA9063_M_VDD_MON
26925. DA9063_M_VDD_WARN
26926. DA9063_M_WAKE
26927. DA9063_NONKEY
26928. DA9063_NONKEY_LOCK
26929. DA9063_NONKEY_PIN_AUTODOWN
26930. DA9063_NONKEY_PIN_AUTOFLPRT
26931. DA9063_NONKEY_PIN_MASK
26932. DA9063_NONKEY_PIN_PORT
26933. DA9063_NONKEY_PIN_SWDOWN
26934. DA9063_NRES_MODE
26935. DA9063_NSHUTDOWN
26936. DA9063_OTPREAD_EN
26937. DA9063_OUT_32K_EN
26938. DA9063_OUT_32K_PAUSE
26939. DA9063_OUT_CLOCK
26940. DA9063_PAGE_REVERT
26941. DA9063_PAGE_WRITE_MODE
26942. DA9063_PEG_PAGE_SHIFT
26943. DA9063_PERI_SW_CONF
26944. DA9063_PERI_SW_EN
26945. DA9063_PERI_SW_GPI_GPIO1
26946. DA9063_PERI_SW_GPI_GPIO13
26947. DA9063_PERI_SW_GPI_GPIO2
26948. DA9063_PERI_SW_GPI_MASK
26949. DA9063_PERI_SW_GPI_OFF
26950. DA9063_PMCONT_DIS
26951. DA9063_PMIF_DIS
26952. DA9063_PM_FB1_PIN
26953. DA9063_PM_FB2_PIN
26954. DA9063_PM_FB3_PIN
26955. DA9063_POR
26956. DA9063_POWER1_EN
26957. DA9063_POWER_EN
26958. DA9063_PWM_CLK_MASK
26959. DA9063_PWM_CLK_PWM1MHZ
26960. DA9063_PWM_CLK_PWM2MHZ
26961. DA9063_REG_ADCIN1_RES
26962. DA9063_REG_ADCIN2_RES
26963. DA9063_REG_ADCIN3_RES
26964. DA9063_REG_ADC_CFG
26965. DA9063_REG_ADC_CONT
26966. DA9063_REG_ADC_MAN
26967. DA9063_REG_ADC_RES_H
26968. DA9063_REG_ADC_RES_L
26969. DA9063_REG_AUTO1_HIGH
26970. DA9063_REG_AUTO1_LOW
26971. DA9063_REG_AUTO2_HIGH
26972. DA9063_REG_AUTO2_LOW
26973. DA9063_REG_AUTO3_HIGH
26974. DA9063_REG_AUTO3_LOW
26975. DA9063_REG_BBAT_CONT
26976. DA9063_REG_BCORE1_CFG
26977. DA9063_REG_BCORE1_CONT
26978. DA9063_REG_BCORE2_CFG
26979. DA9063_REG_BCORE2_CONT
26980. DA9063_REG_BIO_CFG
26981. DA9063_REG_BIO_CONT
26982. DA9063_REG_BMEM_CFG
26983. DA9063_REG_BMEM_CONT
26984. DA9063_REG_BPERI_CFG
26985. DA9063_REG_BPERI_CONT
26986. DA9063_REG_BPRO_CFG
26987. DA9063_REG_BPRO_CONT
26988. DA9063_REG_BUCK_ILIM_A
26989. DA9063_REG_BUCK_ILIM_B
26990. DA9063_REG_BUCK_ILIM_C
26991. DA9063_REG_CHIP_ID
26992. DA9063_REG_CHIP_VARIANT
26993. DA9063_REG_CONFIG_A
26994. DA9063_REG_CONFIG_B
26995. DA9063_REG_CONFIG_C
26996. DA9063_REG_CONFIG_D
26997. DA9063_REG_CONFIG_E
26998. DA9063_REG_CONFIG_F
26999. DA9063_REG_CONFIG_G
27000. DA9063_REG_CONFIG_H
27001. DA9063_REG_CONFIG_I
27002. DA9063_REG_CONFIG_J
27003. DA9063_REG_CONFIG_K
27004. DA9063_REG_CONFIG_L
27005. DA9063_REG_CONTROL_A
27006. DA9063_REG_CONTROL_B
27007. DA9063_REG_CONTROL_C
27008. DA9063_REG_CONTROL_D
27009. DA9063_REG_CONTROL_E
27010. DA9063_REG_CONTROL_F
27011. DA9063_REG_COUNT_D
27012. DA9063_REG_COUNT_H
27013. DA9063_REG_COUNT_MI
27014. DA9063_REG_COUNT_MO
27015. DA9063_REG_COUNT_S
27016. DA9063_REG_COUNT_Y
27017. DA9063_REG_DVC_1
27018. DA9063_REG_DVC_2
27019. DA9063_REG_EN_32K
27020. DA9063_REG_EVENT_A
27021. DA9063_REG_EVENT_A_OFFSET
27022. DA9063_REG_EVENT_B
27023. DA9063_REG_EVENT_B_OFFSET
27024. DA9063_REG_EVENT_C
27025. DA9063_REG_EVENT_C_OFFSET
27026. DA9063_REG_EVENT_D
27027. DA9063_REG_EVENT_D_OFFSET
27028. DA9063_REG_FAULT_LOG
27029. DA9063_REG_GPIO_0_1
27030. DA9063_REG_GPIO_10_11
27031. DA9063_REG_GPIO_12_13
27032. DA9063_REG_GPIO_14_15
27033. DA9063_REG_GPIO_2_3
27034. DA9063_REG_GPIO_4_5
27035. DA9063_REG_GPIO_6_7
27036. DA9063_REG_GPIO_8_9
27037. DA9063_REG_GPIO_MODE0_7
27038. DA9063_REG_GPIO_MODE8_15
27039. DA9063_REG_GPO11_LED
27040. DA9063_REG_GPO14_LED
27041. DA9063_REG_GPO15_LED
27042. DA9063_REG_ID_10_9
27043. DA9063_REG_ID_12_11
27044. DA9063_REG_ID_14_13
27045. DA9063_REG_ID_16_15
27046. DA9063_REG_ID_18_17
27047. DA9063_REG_ID_20_19
27048. DA9063_REG_ID_22_21
27049. DA9063_REG_ID_24_23
27050. DA9063_REG_ID_26_25
27051. DA9063_REG_ID_28_27
27052. DA9063_REG_ID_2_1
27053. DA9063_REG_ID_30_29
27054. DA9063_REG_ID_32_31
27055. DA9063_REG_ID_4_3
27056. DA9063_REG_ID_6_5
27057. DA9063_REG_ID_8_7
27058. DA9063_REG_INTERFACE
27059. DA9063_REG_IRQ_MASK_A
27060. DA9063_REG_IRQ_MASK_B
27061. DA9063_REG_IRQ_MASK_C
27062. DA9063_REG_IRQ_MASK_D
27063. DA9063_REG_LDO10_CONT
27064. DA9063_REG_LDO11_CONT
27065. DA9063_REG_LDO1_CONT
27066. DA9063_REG_LDO2_CONT
27067. DA9063_REG_LDO3_CONT
27068. DA9063_REG_LDO4_CONT
27069. DA9063_REG_LDO5_CONT
27070. DA9063_REG_LDO6_CONT
27071. DA9063_REG_LDO7_CONT
27072. DA9063_REG_LDO8_CONT
27073. DA9063_REG_LDO9_CONT
27074. DA9063_REG_MON_A10_RES
27075. DA9063_REG_MON_A8_RES
27076. DA9063_REG_MON_A9_RES
27077. DA9063_REG_OTP_ADDR
27078. DA9063_REG_OTP_CONT
27079. DA9063_REG_OTP_DATA
27080. DA9063_REG_PAGE0
27081. DA9063_REG_PAGE2
27082. DA9063_REG_PAGE_CON
27083. DA9063_REG_PAGE_MASK
27084. DA9063_REG_PD_DIS
27085. DA9063_REG_RESET
27086. DA9063_REG_SEQ
27087. DA9063_REG_SEQ_A
27088. DA9063_REG_SEQ_B
27089. DA9063_REG_SEQ_TIMER
27090. DA9063_REG_STATUS_A
27091. DA9063_REG_STATUS_B
27092. DA9063_REG_STATUS_C
27093. DA9063_REG_STATUS_D
27094. DA9063_REG_SUPPLIES
27095. DA9063_REG_SWITCH_CONT
27096. DA9063_REG_T_OFFSET
27097. DA9063_REG_VBCORE1_A
27098. DA9063_REG_VBCORE1_B
27099. DA9063_REG_VBCORE2_A
27100. DA9063_REG_VBCORE2_B
27101. DA9063_REG_VBIO_A
27102. DA9063_REG_VBIO_B
27103. DA9063_REG_VBMEM_A
27104. DA9063_REG_VBMEM_B
27105. DA9063_REG_VBPERI_A
27106. DA9063_REG_VBPERI_B
27107. DA9063_REG_VBPRO_A
27108. DA9063_REG_VBPRO_B
27109. DA9063_REG_VLDO10_A
27110. DA9063_REG_VLDO10_B
27111. DA9063_REG_VLDO11_A
27112. DA9063_REG_VLDO11_B
27113. DA9063_REG_VLDO1_A
27114. DA9063_REG_VLDO1_B
27115. DA9063_REG_VLDO2_A
27116. DA9063_REG_VLDO2_B
27117. DA9063_REG_VLDO3_A
27118. DA9063_REG_VLDO3_B
27119. DA9063_REG_VLDO4_A
27120. DA9063_REG_VLDO4_B
27121. DA9063_REG_VLDO5_A
27122. DA9063_REG_VLDO5_B
27123. DA9063_REG_VLDO6_A
27124. DA9063_REG_VLDO6_B
27125. DA9063_REG_VLDO7_A
27126. DA9063_REG_VLDO7_B
27127. DA9063_REG_VLDO8_A
27128. DA9063_REG_VLDO8_B
27129. DA9063_REG_VLDO9_A
27130. DA9063_REG_VLDO9_B
27131. DA9063_REG_VSYS_MON
27132. DA9063_REG_VSYS_RES
27133. DA9063_REG_WAIT
27134. DA9063_REG_WAIT_TIME_MASK
27135. DA9063_REPEAT_WRITE_MODE
27136. DA9063_RESET_PROTECTION_MS
27137. DA9063_RTC_CLOCK
27138. DA9063_RTC_EN
27139. DA9063_RTC_MODE_PD
27140. DA9063_RTC_MODE_SD
27141. DA9063_RTC_READ
27142. DA9063_SHUTDOWN
27143. DA9063_SLEW_RATE_0US5
27144. DA9063_SLEW_RATE_1US
27145. DA9063_SLEW_RATE_3US
27146. DA9063_SLEW_RATE_4US
27147. DA9063_SLEW_RATE_MASK
27148. DA9063_STABILIZ_TIME_MASK
27149. DA9063_STANDBY
27150. DA9063_SWITCH_SR_10MV
27151. DA9063_SWITCH_SR_1MV
27152. DA9063_SWITCH_SR_50MV
27153. DA9063_SWITCH_SR_5MV
27154. DA9063_SWITCH_SR_MASK
27155. DA9063_SYSTEM_EN
27156. DA9063_TEMP_CRIT
27157. DA9063_TICK_ON
27158. DA9063_TICK_TYPE
27159. DA9063_TICK_TYPE_MIN
27160. DA9063_TICK_TYPE_SEC
27161. DA9063_TICK_WAKE
27162. DA9063_TWDSCALE_DISABLE
27163. DA9063_TWDSCALE_MASK
27164. DA9063_TWDSCALE_MAX
27165. DA9063_TWDSCALE_MIN
27166. DA9063_TWD_ERROR
27167. DA9063_VBCORE1_SEL
27168. DA9063_VBCORE2_SEL
27169. DA9063_VBIO_SEL
27170. DA9063_VBMEM_SEL
27171. DA9063_VBPERI_SEL
27172. DA9063_VBPRO_SEL
27173. DA9063_VBUCK_BIAS
27174. DA9063_VBUCK_GPI_GPIO1
27175. DA9063_VBUCK_GPI_GPIO13
27176. DA9063_VBUCK_GPI_GPIO2
27177. DA9063_VBUCK_GPI_MASK
27178. DA9063_VBUCK_GPI_OFF
27179. DA9063_VBUCK_MASK
27180. DA9063_VDD_FAULT
27181. DA9063_VDD_START
27182. DA9063_VIB_SET_MASK
27183. DA9063_VIB_SET_MAX
27184. DA9063_VIB_SET_OFF
27185. DA9063_VLDO10_BIAS
27186. DA9063_VLDO10_MASK
27187. DA9063_VLDO10_SEL
27188. DA9063_VLDO11_BIAS
27189. DA9063_VLDO11_MASK
27190. DA9063_VLDO11_SEL
27191. DA9063_VLDO1_BIAS
27192. DA9063_VLDO1_MASK
27193. DA9063_VLDO1_SEL
27194. DA9063_VLDO2_BIAS
27195. DA9063_VLDO2_MASK
27196. DA9063_VLDO2_SEL
27197. DA9063_VLDO3_BIAS
27198. DA9063_VLDO3_MASK
27199. DA9063_VLDO3_SEL
27200. DA9063_VLDO4_BIAS
27201. DA9063_VLDO4_MASK
27202. DA9063_VLDO4_SEL
27203. DA9063_VLDO5_BIAS
27204. DA9063_VLDO5_MASK
27205. DA9063_VLDO5_SEL
27206. DA9063_VLDO6_BIAS
27207. DA9063_VLDO6_MASK
27208. DA9063_VLDO6_SEL
27209. DA9063_VLDO7_BIAS
27210. DA9063_VLDO7_MASK
27211. DA9063_VLDO7_SEL
27212. DA9063_VLDO8_BIAS
27213. DA9063_VLDO8_MASK
27214. DA9063_VLDO8_SEL
27215. DA9063_VLDO9_BIAS
27216. DA9063_VLDO9_MASK
27217. DA9063_VLDO9_SEL
27218. DA9063_VLDO_GPI_GPIO1
27219. DA9063_VLDO_GPI_GPIO13
27220. DA9063_VLDO_GPI_GPIO2
27221. DA9063_VLDO_GPI_MASK
27222. DA9063_VLDO_GPI_OFF
27223. DA9063_VSYS_VAL_BASE
27224. DA9063_VSYS_VAL_MASK
27225. DA9063_V_LOCK
27226. DA9063_WAIT_SHUT
27227. DA9063_WAIT_TIME_0_US
27228. DA9063_WAIT_TIME_128_MS
27229. DA9063_WAIT_TIME_16_4_MS
27230. DA9063_WAIT_TIME_1_MS
27231. DA9063_WAIT_TIME_1_S
27232. DA9063_WAIT_TIME_256_MS
27233. DA9063_WAIT_TIME_2_1_S
27234. DA9063_WAIT_TIME_2_MS
27235. DA9063_WAIT_TIME_32_8_MS
27236. DA9063_WAIT_TIME_4_1_MS
27237. DA9063_WAIT_TIME_512_MS
27238. DA9063_WAIT_TIME_512_US
27239. DA9063_WAIT_TIME_65_5_MS
27240. DA9063_WAIT_TIME_8_2_MS
27241. DA9063_WAKE
27242. DA9063_WAKE_UP
27243. DA9063_WATCHDOG
27244. DA9063_WATCHDOG_PD
27245. DA9063_WDG_TIMEOUT
27246. DA9063_WDT_MAX_TIMEOUT
27247. DA9063_WDT_MIN_TIMEOUT
27248. DA9150_ADDETAC_CFG_B
27249. DA9150_ADETAC_CFG_A
27250. DA9150_ADETAC_CFG_C
27251. DA9150_ADETAC_CFG_D
27252. DA9150_ADETD_STAT
27253. DA9150_ADETID_CFG_A
27254. DA9150_ADETVB_CFG_A
27255. DA9150_ADETVB_CFG_B
27256. DA9150_ADETVB_CFG_C
27257. DA9150_ADETVB_CFG_D
27258. DA9150_ADET_CMPSTAT
27259. DA9150_ADET_CTRL_A
27260. DA9150_ADET_RID_PT_CHG_H
27261. DA9150_ADET_RID_PT_CHG_L
27262. DA9150_ADP_PRB_COMP_MASK
27263. DA9150_ADP_PRB_COMP_SHIFT
27264. DA9150_ADP_SNS_COMP_MASK
27265. DA9150_ADP_SNS_COMP_SHIFT
27266. DA9150_AID_CR_DIS_MASK
27267. DA9150_AID_CR_DIS_SHIFT
27268. DA9150_AID_DAT_MASK
27269. DA9150_AID_DAT_SHIFT
27270. DA9150_AID_EXT_POL_MASK
27271. DA9150_AID_EXT_POL_SHIFT
27272. DA9150_AID_ID_MASK
27273. DA9150_AID_ID_SHIFT
27274. DA9150_AID_MODE_MASK
27275. DA9150_AID_MODE_SHIFT
27276. DA9150_AID_TRIG_MASK
27277. DA9150_AID_TRIG_SHIFT
27278. DA9150_AID_UNCLAMP_MASK
27279. DA9150_AID_UNCLAMP_SHIFT
27280. DA9150_AID_VB_MASK
27281. DA9150_AID_VB_SHIFT
27282. DA9150_AUX_DATA_0
27283. DA9150_AUX_DATA_1
27284. DA9150_AUX_DATA_2
27285. DA9150_AUX_DATA_3
27286. DA9150_AUX_DAT_0_MASK
27287. DA9150_AUX_DAT_0_SHIFT
27288. DA9150_AUX_DAT_1_MASK
27289. DA9150_AUX_DAT_1_SHIFT
27290. DA9150_AUX_DAT_2_MASK
27291. DA9150_AUX_DAT_2_SHIFT
27292. DA9150_AUX_DAT_3_MASK
27293. DA9150_AUX_DAT_3_SHIFT
27294. DA9150_BIF_CTRL
27295. DA9150_BIF_ISRC_EN_MASK
27296. DA9150_BIF_ISRC_EN_SHIFT
27297. DA9150_BOOTLD_EN_MASK
27298. DA9150_BOOTLD_EN_SHIFT
27299. DA9150_BOOTLD_STAT_MASK
27300. DA9150_BOOTLD_STAT_SHIFT
27301. DA9150_CC_CFG_A
27302. DA9150_CC_CFG_B
27303. DA9150_CC_CFG_MASK
27304. DA9150_CC_CFG_SHIFT
27305. DA9150_CC_ENDLESS_MODE_MASK
27306. DA9150_CC_ENDLESS_MODE_SHIFT
27307. DA9150_CC_EN_MASK
27308. DA9150_CC_EN_SHIFT
27309. DA9150_CC_IAVG_RES_A
27310. DA9150_CC_IAVG_RES_B
27311. DA9150_CC_IAVG_RES_H_MASK
27312. DA9150_CC_IAVG_RES_H_SHIFT
27313. DA9150_CC_IAVG_RES_L_MASK
27314. DA9150_CC_IAVG_RES_L_SHIFT
27315. DA9150_CC_ICHG_RES_A
27316. DA9150_CC_ICHG_RES_B
27317. DA9150_CC_ICHG_RES_H_MASK
27318. DA9150_CC_ICHG_RES_H_SHIFT
27319. DA9150_CC_ICHG_RES_L_MASK
27320. DA9150_CC_ICHG_RES_L_SHIFT
27321. DA9150_CC_OPT_MASK
27322. DA9150_CC_OPT_SHIFT
27323. DA9150_CC_PREAMP_MASK
27324. DA9150_CC_PREAMP_SHIFT
27325. DA9150_CC_TIMEBASE_MASK
27326. DA9150_CC_TIMEBASE_SHIFT
27327. DA9150_CE_LPM_DEB_MASK
27328. DA9150_CE_LPM_DEB_SHIFT
27329. DA9150_CHARGER_IDX
27330. DA9150_CHGBL_DBL_MASK
27331. DA9150_CHGBL_DBL_SHIFT
27332. DA9150_CHGBL_DUR_MASK
27333. DA9150_CHGBL_DUR_SHIFT
27334. DA9150_CHGBL_FLKR_MASK
27335. DA9150_CHGBL_FLKR_SHIFT
27336. DA9150_CHGBL_FRQ_MASK
27337. DA9150_CHGBL_FRQ_SHIFT
27338. DA9150_CHGLED_PIN_MASK
27339. DA9150_CHGLED_PIN_SHIFT
27340. DA9150_CHG_BAT_REMOVED_MASK
27341. DA9150_CHG_BAT_REMOVED_SHIFT
27342. DA9150_CHG_EN_MASK
27343. DA9150_CHG_EN_SHIFT
27344. DA9150_CHG_IAV_H_MASK
27345. DA9150_CHG_IAV_H_SHIFT
27346. DA9150_CHG_IAV_L_MASK
27347. DA9150_CHG_IAV_L_SHIFT
27348. DA9150_CHG_IBAT_MASK
27349. DA9150_CHG_IBAT_SHIFT
27350. DA9150_CHG_IBAT_TRED_MASK
27351. DA9150_CHG_IBAT_TRED_SHIFT
27352. DA9150_CHG_ICOLD_MASK
27353. DA9150_CHG_ICOLD_SHIFT
27354. DA9150_CHG_IEND_MASK
27355. DA9150_CHG_IEND_SHIFT
27356. DA9150_CHG_IEND_STAT_MASK
27357. DA9150_CHG_IEND_STAT_SHIFT
27358. DA9150_CHG_IHOT_MASK
27359. DA9150_CHG_IHOT_SHIFT
27360. DA9150_CHG_IPRE_MASK
27361. DA9150_CHG_IPRE_SHIFT
27362. DA9150_CHG_IWARM_MASK
27363. DA9150_CHG_IWARM_SHIFT
27364. DA9150_CHG_LPM_MASK
27365. DA9150_CHG_LPM_SHIFT
27366. DA9150_CHG_NBLO_MASK
27367. DA9150_CHG_NBLO_SHIFT
27368. DA9150_CHG_STAT_ACT
27369. DA9150_CHG_STAT_BAT
27370. DA9150_CHG_STAT_CC
27371. DA9150_CHG_STAT_CV
27372. DA9150_CHG_STAT_FULL
27373. DA9150_CHG_STAT_MASK
27374. DA9150_CHG_STAT_OFF
27375. DA9150_CHG_STAT_PRE
27376. DA9150_CHG_STAT_SHIFT
27377. DA9150_CHG_STAT_SUSP
27378. DA9150_CHG_STAT_TEMP
27379. DA9150_CHG_STAT_TIME
27380. DA9150_CHG_TCTR_MASK
27381. DA9150_CHG_TCTR_MODE_MASK
27382. DA9150_CHG_TCTR_MODE_SHIFT
27383. DA9150_CHG_TCTR_SHIFT
27384. DA9150_CHG_TCTR_VAL_MASK
27385. DA9150_CHG_TCTR_VAL_SHIFT
27386. DA9150_CHG_TEMP_MASK
27387. DA9150_CHG_TEMP_OVER
27388. DA9150_CHG_TEMP_SHIFT
27389. DA9150_CHG_TEMP_UNDER
27390. DA9150_CHG_TIME_MASK
27391. DA9150_CHG_TIME_SHIFT
27392. DA9150_CHG_TJUNC_CLASS_6
27393. DA9150_CHG_TJUNC_CLASS_MASK
27394. DA9150_CHG_TJUNC_CLASS_SHIFT
27395. DA9150_CHG_TRED_MASK
27396. DA9150_CHG_TRED_SHIFT
27397. DA9150_CHG_VBAT_MASK
27398. DA9150_CHG_VBAT_SHIFT
27399. DA9150_CHG_VCOLD_MASK
27400. DA9150_CHG_VCOLD_SHIFT
27401. DA9150_CHG_VDROP_MASK
27402. DA9150_CHG_VDROP_SHIFT
27403. DA9150_CHG_VFAULT_MASK
27404. DA9150_CHG_VFAULT_SHIFT
27405. DA9150_CHG_VFLOAT_MASK
27406. DA9150_CHG_VFLOAT_SHIFT
27407. DA9150_CHG_VHOT_MASK
27408. DA9150_CHG_VHOT_SHIFT
27409. DA9150_CHG_VWARM_MASK
27410. DA9150_CHG_VWARM_SHIFT
27411. DA9150_CONFIG_A
27412. DA9150_CONFIG_A_SHARED
27413. DA9150_CONFIG_B
27414. DA9150_CONFIG_C
27415. DA9150_CONFIG_D
27416. DA9150_CONFIG_D_SHARED
27417. DA9150_CONFIG_E
27418. DA9150_CONF_DBP_MASK
27419. DA9150_CONF_DBP_SHIFT
27420. DA9150_CONF_GPIOA_MASK
27421. DA9150_CONF_GPIOA_SHIFT
27422. DA9150_CONF_GPIOB_MASK
27423. DA9150_CONF_GPIOB_SHIFT
27424. DA9150_CONF_MODE_MASK
27425. DA9150_CONF_MODE_SHIFT
27426. DA9150_CONF_RPD_MASK
27427. DA9150_CONF_RPD_SHIFT
27428. DA9150_CONF_SRP_MASK
27429. DA9150_CONF_SRP_SHIFT
27430. DA9150_CONTROL_A
27431. DA9150_CONTROL_B
27432. DA9150_CONTROL_C
27433. DA9150_CORE2WIRE_CTRL_A
27434. DA9150_CORE2WIRE_STAT_A
27435. DA9150_COREBTLD_CTRL_A
27436. DA9150_COREBTLD_STAT_A
27437. DA9150_CORE_BASE_ADDR_MASK
27438. DA9150_CORE_BASE_ADDR_SHIFT
27439. DA9150_CORE_CFG_DATA_A
27440. DA9150_CORE_CFG_DATA_B
27441. DA9150_CORE_CFG_DT_A_MASK
27442. DA9150_CORE_CFG_DT_A_SHIFT
27443. DA9150_CORE_CFG_DT_B_MASK
27444. DA9150_CORE_CFG_DT_B_SHIFT
27445. DA9150_CORE_CMD_A
27446. DA9150_CORE_CMD_MASK
27447. DA9150_CORE_CMD_SHIFT
27448. DA9150_CORE_CONFIG_A
27449. DA9150_CORE_CONFIG_B
27450. DA9150_CORE_CONFIG_C
27451. DA9150_CORE_DATA_0_MASK
27452. DA9150_CORE_DATA_0_SHIFT
27453. DA9150_CORE_DATA_1_MASK
27454. DA9150_CORE_DATA_1_SHIFT
27455. DA9150_CORE_DATA_2_MASK
27456. DA9150_CORE_DATA_2_SHIFT
27457. DA9150_CORE_DATA_3_MASK
27458. DA9150_CORE_DATA_3_SHIFT
27459. DA9150_CORE_DATA_A
27460. DA9150_CORE_DATA_B
27461. DA9150_CORE_DATA_C
27462. DA9150_CORE_DATA_D
27463. DA9150_CORE_EN_MASK
27464. DA9150_CORE_EN_SHIFT
27465. DA9150_CORE_LOCKUP_MASK
27466. DA9150_CORE_LOCKUP_SHIFT
27467. DA9150_CORE_MEMMUX_MASK
27468. DA9150_CORE_MEMMUX_SHIFT
27469. DA9150_CORE_RESET_MASK
27470. DA9150_CORE_RESET_SHIFT
27471. DA9150_CORE_STOP_MASK
27472. DA9150_CORE_STOP_SHIFT
27473. DA9150_CORE_SW_SIZE_MASK
27474. DA9150_CORE_SW_SIZE_SHIFT
27475. DA9150_CORE_SW_SRC_MASK
27476. DA9150_CORE_SW_SRC_SHIFT
27477. DA9150_DAT_CLAMP_EXT_MASK
27478. DA9150_DAT_CLAMP_EXT_SHIFT
27479. DA9150_DAT_MODE_MASK
27480. DA9150_DAT_MODE_SHIFT
27481. DA9150_DAT_RPD_EXT_MASK
27482. DA9150_DAT_RPD_EXT_SHIFT
27483. DA9150_DAT_SWP_MASK
27484. DA9150_DAT_SWP_SHIFT
27485. DA9150_DCD_STAT_MASK
27486. DA9150_DCD_STAT_SHIFT
27487. DA9150_DEEP_SLEEP_EN_MASK
27488. DA9150_DEEP_SLEEP_EN_SHIFT
27489. DA9150_DISABLE_DEL_MASK
27490. DA9150_DISABLE_DEL_SHIFT
27491. DA9150_DISABLE_MASK
27492. DA9150_DISABLE_SHIFT
27493. DA9150_DM_COMP_MASK
27494. DA9150_DM_COMP_SHIFT
27495. DA9150_DM_STAT_MASK
27496. DA9150_DM_STAT_SHIFT
27497. DA9150_DP_COMP_MASK
27498. DA9150_DP_COMP_SHIFT
27499. DA9150_DP_STAT_MASK
27500. DA9150_DP_STAT_SHIFT
27501. DA9150_DTYPE_DT_ACA_CHG
27502. DA9150_DTYPE_DT_ACA_DOC
27503. DA9150_DTYPE_DT_ACA_OTG
27504. DA9150_DTYPE_DT_CR4_CHG
27505. DA9150_DTYPE_DT_CR5_CHG
27506. DA9150_DTYPE_DT_DED_CHG
27507. DA9150_DTYPE_DT_NIL
27508. DA9150_DTYPE_DT_NN_ACC
27509. DA9150_DTYPE_DT_NN_CHG
27510. DA9150_DTYPE_DT_PT_CHG
27511. DA9150_DTYPE_DT_USB_CHG
27512. DA9150_DTYPE_DT_USB_OTG
27513. DA9150_DTYPE_DT_USB_STD
27514. DA9150_DTYPE_MASK
27515. DA9150_DTYPE_SHIFT
27516. DA9150_EBS_EN_MASK
27517. DA9150_EBS_EN_SHIFT
27518. DA9150_EBS_STAT_MASK
27519. DA9150_EBS_STAT_SHIFT
27520. DA9150_EVENTS_F_MASK
27521. DA9150_EVENTS_F_SHIFT
27522. DA9150_EVENTS_G_MASK
27523. DA9150_EVENTS_G_SHIFT
27524. DA9150_EVENTS_H_MASK
27525. DA9150_EVENTS_H_SHIFT
27526. DA9150_EVENT_E
27527. DA9150_EVENT_F
27528. DA9150_EVENT_G
27529. DA9150_EVENT_H
27530. DA9150_EXT_FAULT_MASK
27531. DA9150_EXT_FAULT_SHIFT
27532. DA9150_E_ADP_MASK
27533. DA9150_E_ADP_SHIFT
27534. DA9150_E_CHG_MASK
27535. DA9150_E_CHG_SHIFT
27536. DA9150_E_CONF_MASK
27537. DA9150_E_CONF_SHIFT
27538. DA9150_E_DAT_MASK
27539. DA9150_E_DAT_SHIFT
27540. DA9150_E_DTYPE_MASK
27541. DA9150_E_DTYPE_SHIFT
27542. DA9150_E_FG_MASK
27543. DA9150_E_FG_SHIFT
27544. DA9150_E_GPADC_MASK
27545. DA9150_E_GPADC_SHIFT
27546. DA9150_E_GPIOA_MASK
27547. DA9150_E_GPIOA_SHIFT
27548. DA9150_E_GPIOB_MASK
27549. DA9150_E_GPIOB_SHIFT
27550. DA9150_E_GPIOC_MASK
27551. DA9150_E_GPIOC_SHIFT
27552. DA9150_E_GPIOD_MASK
27553. DA9150_E_GPIOD_SHIFT
27554. DA9150_E_GP_MASK
27555. DA9150_E_GP_SHIFT
27556. DA9150_E_ID_MASK
27557. DA9150_E_ID_SHIFT
27558. DA9150_E_SESS_END_MASK
27559. DA9150_E_SESS_END_SHIFT
27560. DA9150_E_SESS_VLD_MASK
27561. DA9150_E_SESS_VLD_SHIFT
27562. DA9150_E_TBAT_MASK
27563. DA9150_E_TBAT_SHIFT
27564. DA9150_E_TCLASS_MASK
27565. DA9150_E_TCLASS_SHIFT
27566. DA9150_E_TJUNC_MASK
27567. DA9150_E_TJUNC_SHIFT
27568. DA9150_E_VBUS_MASK
27569. DA9150_E_VBUS_SHIFT
27570. DA9150_E_VFAULT_MASK
27571. DA9150_E_VFAULT_SHIFT
27572. DA9150_E_WKUP_MASK
27573. DA9150_E_WKUP_SHIFT
27574. DA9150_FAULT_LOG_A
27575. DA9150_FAULT_LOG_B
27576. DA9150_FAULT_PIN_MASK
27577. DA9150_FAULT_PIN_SHIFT
27578. DA9150_FAULT_TYPE_MASK
27579. DA9150_FAULT_TYPE_SHIFT
27580. DA9150_FG_CTRL_A
27581. DA9150_FG_CTRL_B
27582. DA9150_FG_IDX
27583. DA9150_FG_IRQ_HIGH_SOC_MASK
27584. DA9150_FG_IRQ_LOW_SOC_MASK
27585. DA9150_FG_IRQ_SOC_MASK
27586. DA9150_FG_QIF_CODE_MASK
27587. DA9150_FG_QIF_CODE_SHIFT
27588. DA9150_FG_QIF_EN_MASK
27589. DA9150_FG_QIF_EN_SHIFT
27590. DA9150_FG_QIF_VALUE_MASK
27591. DA9150_FG_QIF_VALUE_SHIFT
27592. DA9150_FW_CTRL_A
27593. DA9150_FW_CTRL_B
27594. DA9150_FW_CTRL_C
27595. DA9150_FW_CTRL_D
27596. DA9150_FW_CTRL_E
27597. DA9150_FW_FWDL_BASE_MASK
27598. DA9150_FW_FWDL_BASE_SHIFT
27599. DA9150_FW_FWDL_CRC_MASK
27600. DA9150_FW_FWDL_CRC_SHIFT
27601. DA9150_FW_FWDL_EN_MASK
27602. DA9150_FW_FWDL_EN_SHIFT
27603. DA9150_FW_FWDL_ERR_MASK
27604. DA9150_FW_FWDL_ERR_SHIFT
27605. DA9150_FW_FWDL_SEG_MASK
27606. DA9150_FW_FWDL_SEG_SHIFT
27607. DA9150_FW_FWDL_VALUE_MASK
27608. DA9150_FW_FWDL_VALUE_SHIFT
27609. DA9150_FW_SEAL_MASK
27610. DA9150_FW_SEAL_SHIFT
27611. DA9150_GPADC_CEN_MASK
27612. DA9150_GPADC_CEN_SHIFT
27613. DA9150_GPADC_CHANNEL
27614. DA9150_GPADC_CHANNEL_PROCESSED
27615. DA9150_GPADC_CHANNEL_RAW
27616. DA9150_GPADC_CHANNEL_SCALED
27617. DA9150_GPADC_CHAN_GPIOA
27618. DA9150_GPADC_CHAN_GPIOB
27619. DA9150_GPADC_CHAN_GPIOC
27620. DA9150_GPADC_CHAN_GPIOD
27621. DA9150_GPADC_CHAN_IBUS
27622. DA9150_GPADC_CHAN_TBAT
27623. DA9150_GPADC_CHAN_TJUNC_CORE
27624. DA9150_GPADC_CHAN_TJUNC_OVP
27625. DA9150_GPADC_CHAN_VBAT
27626. DA9150_GPADC_CHAN_VBUS
27627. DA9150_GPADC_CHAN_VSYS
27628. DA9150_GPADC_CMAN
27629. DA9150_GPADC_CMUX_MASK
27630. DA9150_GPADC_CMUX_SHIFT
27631. DA9150_GPADC_CRES_A
27632. DA9150_GPADC_CRES_B
27633. DA9150_GPADC_CRES_H_MASK
27634. DA9150_GPADC_CRES_H_SHIFT
27635. DA9150_GPADC_CRES_L_MASK
27636. DA9150_GPADC_CRES_L_SHIFT
27637. DA9150_GPADC_CRUN_MASK
27638. DA9150_GPADC_CRUN_SHIFT
27639. DA9150_GPADC_EN_MASK
27640. DA9150_GPADC_EN_SHIFT
27641. DA9150_GPADC_HW_CHAN_GPIOA_2V
27642. DA9150_GPADC_HW_CHAN_GPIOA_2V_
27643. DA9150_GPADC_HW_CHAN_GPIOA_6V
27644. DA9150_GPADC_HW_CHAN_GPIOA_6V_
27645. DA9150_GPADC_HW_CHAN_GPIOB_2V
27646. DA9150_GPADC_HW_CHAN_GPIOB_2V_
27647. DA9150_GPADC_HW_CHAN_GPIOB_6V
27648. DA9150_GPADC_HW_CHAN_GPIOB_6V_
27649. DA9150_GPADC_HW_CHAN_GPIOC_2V
27650. DA9150_GPADC_HW_CHAN_GPIOC_2V_
27651. DA9150_GPADC_HW_CHAN_GPIOC_6V
27652. DA9150_GPADC_HW_CHAN_GPIOC_6V_
27653. DA9150_GPADC_HW_CHAN_GPIOD_2V
27654. DA9150_GPADC_HW_CHAN_GPIOD_2V_
27655. DA9150_GPADC_HW_CHAN_GPIOD_6V
27656. DA9150_GPADC_HW_CHAN_GPIOD_6V_
27657. DA9150_GPADC_HW_CHAN_IBUS_SENSE
27658. DA9150_GPADC_HW_CHAN_IBUS_SENSE_
27659. DA9150_GPADC_HW_CHAN_ID
27660. DA9150_GPADC_HW_CHAN_ID_
27661. DA9150_GPADC_HW_CHAN_TBAT
27662. DA9150_GPADC_HW_CHAN_TBAT_
27663. DA9150_GPADC_HW_CHAN_TJUNC_CORE
27664. DA9150_GPADC_HW_CHAN_TJUNC_CORE_
27665. DA9150_GPADC_HW_CHAN_TJUNC_OVP
27666. DA9150_GPADC_HW_CHAN_TJUNC_OVP_
27667. DA9150_GPADC_HW_CHAN_VBAT
27668. DA9150_GPADC_HW_CHAN_VBAT_
27669. DA9150_GPADC_HW_CHAN_VBUS_DIV
27670. DA9150_GPADC_HW_CHAN_VBUS_DIV_
27671. DA9150_GPADC_HW_CHAN_VSYS
27672. DA9150_GPADC_HW_CHAN_VSYS_
27673. DA9150_GPADC_IDX
27674. DA9150_GPADC_MAN
27675. DA9150_GPADC_MUX_MASK
27676. DA9150_GPADC_MUX_SHIFT
27677. DA9150_GPADC_RES_A
27678. DA9150_GPADC_RES_B
27679. DA9150_GPADC_RES_H_MASK
27680. DA9150_GPADC_RES_H_SHIFT
27681. DA9150_GPADC_RES_L_BITS
27682. DA9150_GPADC_RES_L_MASK
27683. DA9150_GPADC_RES_L_SHIFT
27684. DA9150_GPADC_RUN_MASK
27685. DA9150_GPADC_RUN_SHIFT
27686. DA9150_GPIOA_ANAEN_MASK
27687. DA9150_GPIOA_ANAEN_SHIFT
27688. DA9150_GPIOA_CONT_MASK
27689. DA9150_GPIOA_CONT_SHIFT
27690. DA9150_GPIOA_MODE_MASK
27691. DA9150_GPIOA_MODE_SHIFT
27692. DA9150_GPIOA_PIN_GPI
27693. DA9150_GPIOA_PIN_GPO_OD
27694. DA9150_GPIOA_PIN_MASK
27695. DA9150_GPIOA_PIN_SHIFT
27696. DA9150_GPIOA_PUPD_MASK
27697. DA9150_GPIOA_PUPD_SHIFT
27698. DA9150_GPIOA_STAT_MASK
27699. DA9150_GPIOA_STAT_SHIFT
27700. DA9150_GPIOA_TYPE_MASK
27701. DA9150_GPIOA_TYPE_SHIFT
27702. DA9150_GPIOB_ANAEN_MASK
27703. DA9150_GPIOB_ANAEN_SHIFT
27704. DA9150_GPIOB_CONT_MASK
27705. DA9150_GPIOB_CONT_SHIFT
27706. DA9150_GPIOB_MODE_MASK
27707. DA9150_GPIOB_MODE_SHIFT
27708. DA9150_GPIOB_PIN_GPI
27709. DA9150_GPIOB_PIN_GPO_OD
27710. DA9150_GPIOB_PIN_MASK
27711. DA9150_GPIOB_PIN_SHIFT
27712. DA9150_GPIOB_PUPD_MASK
27713. DA9150_GPIOB_PUPD_SHIFT
27714. DA9150_GPIOB_STAT_MASK
27715. DA9150_GPIOB_STAT_SHIFT
27716. DA9150_GPIOB_TYPE_MASK
27717. DA9150_GPIOB_TYPE_SHIFT
27718. DA9150_GPIOC_ANAEN_MASK
27719. DA9150_GPIOC_ANAEN_SHIFT
27720. DA9150_GPIOC_CONT_MASK
27721. DA9150_GPIOC_CONT_SHIFT
27722. DA9150_GPIOC_MODE_MASK
27723. DA9150_GPIOC_MODE_SHIFT
27724. DA9150_GPIOC_PIN_GPI
27725. DA9150_GPIOC_PIN_GPO_OD
27726. DA9150_GPIOC_PIN_MASK
27727. DA9150_GPIOC_PIN_SHIFT
27728. DA9150_GPIOC_PUPD_MASK
27729. DA9150_GPIOC_PUPD_SHIFT
27730. DA9150_GPIOC_STAT_MASK
27731. DA9150_GPIOC_STAT_SHIFT
27732. DA9150_GPIOC_TYPE_MASK
27733. DA9150_GPIOC_TYPE_SHIFT
27734. DA9150_GPIOD_ANAEN_MASK
27735. DA9150_GPIOD_ANAEN_SHIFT
27736. DA9150_GPIOD_CONT_MASK
27737. DA9150_GPIOD_CONT_SHIFT
27738. DA9150_GPIOD_MODE_MASK
27739. DA9150_GPIOD_MODE_SHIFT
27740. DA9150_GPIOD_PIN_GPI
27741. DA9150_GPIOD_PIN_GPO_OD
27742. DA9150_GPIOD_PIN_MASK
27743. DA9150_GPIOD_PIN_SHIFT
27744. DA9150_GPIOD_PUPD_MASK
27745. DA9150_GPIOD_PUPD_SHIFT
27746. DA9150_GPIOD_STAT_MASK
27747. DA9150_GPIOD_STAT_SHIFT
27748. DA9150_GPIOD_TYPE_MASK
27749. DA9150_GPIOD_TYPE_SHIFT
27750. DA9150_GPIO_ANAEN
27751. DA9150_GPIO_ANAEN_MASK
27752. DA9150_GPIO_A_B
27753. DA9150_GPIO_CFG_A
27754. DA9150_GPIO_CFG_B
27755. DA9150_GPIO_CFG_C
27756. DA9150_GPIO_CTRL_A
27757. DA9150_GPIO_CTRL_B
27758. DA9150_GPIO_CTRL_C
27759. DA9150_GPIO_C_D
27760. DA9150_GPIO_MODE_CONT
27761. DA9150_GPIO_PUPD_MASK
27762. DA9150_GPI_DEB_MASK
27763. DA9150_GPI_DEB_SHIFT
27764. DA9150_GPI_LPM_MASK
27765. DA9150_GPI_LPM_SHIFT
27766. DA9150_GPI_V_MASK
27767. DA9150_GPI_V_SHIFT
27768. DA9150_I2C_PAGE_MASK
27769. DA9150_I2C_PAGE_SHIFT
27770. DA9150_ID_COMP_MASK
27771. DA9150_ID_COMP_SHIFT
27772. DA9150_ID_ERR_MASK
27773. DA9150_ID_ERR_SHIFT
27774. DA9150_ID_MODE_MASK
27775. DA9150_ID_MODE_SHIFT
27776. DA9150_IF_BASE_ADDR_MASK
27777. DA9150_IF_BASE_ADDR_SHIFT
27778. DA9150_INTERFACE_SHARED
27779. DA9150_IRQ_ADP
27780. DA9150_IRQ_CHG
27781. DA9150_IRQ_CONF
27782. DA9150_IRQ_DAT
27783. DA9150_IRQ_DTYPE
27784. DA9150_IRQ_FG
27785. DA9150_IRQ_GP
27786. DA9150_IRQ_GPADC
27787. DA9150_IRQ_GPIOA
27788. DA9150_IRQ_GPIOB
27789. DA9150_IRQ_GPIOC
27790. DA9150_IRQ_GPIOD
27791. DA9150_IRQ_ID
27792. DA9150_IRQ_MASK_E
27793. DA9150_IRQ_MASK_F
27794. DA9150_IRQ_MASK_G
27795. DA9150_IRQ_MASK_H
27796. DA9150_IRQ_SESS_END
27797. DA9150_IRQ_SESS_VLD
27798. DA9150_IRQ_TBAT
27799. DA9150_IRQ_TCLASS
27800. DA9150_IRQ_TJUNC
27801. DA9150_IRQ_VBUS
27802. DA9150_IRQ_VFAULT
27803. DA9150_IRQ_WKUP
27804. DA9150_ISET_CDP_MASK
27805. DA9150_ISET_CDP_SHIFT
27806. DA9150_ISET_DCHG_MASK
27807. DA9150_ISET_DCHG_SHIFT
27808. DA9150_ISET_DEF_MASK
27809. DA9150_ISET_DEF_SHIFT
27810. DA9150_ISET_UNIT_MASK
27811. DA9150_ISET_UNIT_SHIFT
27812. DA9150_LFOSC_EXT_MASK
27813. DA9150_LFOSC_EXT_SHIFT
27814. DA9150_LFOSC_STAT_MASK
27815. DA9150_LFOSC_STAT_SHIFT
27816. DA9150_LPM_EN_MASK
27817. DA9150_LPM_EN_SHIFT
27818. DA9150_LPM_MASK
27819. DA9150_LPM_SHIFT
27820. DA9150_M_ADP_MASK
27821. DA9150_M_ADP_SHIFT
27822. DA9150_M_CHG_MASK
27823. DA9150_M_CHG_SHIFT
27824. DA9150_M_CONF_MASK
27825. DA9150_M_CONF_SHIFT
27826. DA9150_M_DAT_MASK
27827. DA9150_M_DAT_SHIFT
27828. DA9150_M_DTYPE_MASK
27829. DA9150_M_DTYPE_SHIFT
27830. DA9150_M_FG_MASK
27831. DA9150_M_FG_SHIFT
27832. DA9150_M_GPADC_MASK
27833. DA9150_M_GPADC_SHIFT
27834. DA9150_M_GPIOA_MASK
27835. DA9150_M_GPIOA_SHIFT
27836. DA9150_M_GPIOB_MASK
27837. DA9150_M_GPIOB_SHIFT
27838. DA9150_M_GPIOC_MASK
27839. DA9150_M_GPIOC_SHIFT
27840. DA9150_M_GPIOD_MASK
27841. DA9150_M_GPIOD_SHIFT
27842. DA9150_M_GP_MASK
27843. DA9150_M_GP_SHIFT
27844. DA9150_M_ID_MASK
27845. DA9150_M_ID_SHIFT
27846. DA9150_M_SESS_END_MASK
27847. DA9150_M_SESS_END_SHIFT
27848. DA9150_M_SESS_VLD_MASK
27849. DA9150_M_SESS_VLD_SHIFT
27850. DA9150_M_TBAT_MASK
27851. DA9150_M_TBAT_SHIFT
27852. DA9150_M_TJUNC_MASK
27853. DA9150_M_TJUNC_SHIFT
27854. DA9150_M_VBUS_MASK
27855. DA9150_M_VBUS_SHIFT
27856. DA9150_M_VFAULT_MASK
27857. DA9150_M_VFAULT_SHIFT
27858. DA9150_M_WKUP_MASK
27859. DA9150_M_WKUP_SHIFT
27860. DA9150_NIRQ_MODE_MASK
27861. DA9150_NIRQ_MODE_SHIFT
27862. DA9150_NIRQ_PIN_MASK
27863. DA9150_NIRQ_PIN_SHIFT
27864. DA9150_NIRQ_PUPD_MASK
27865. DA9150_NIRQ_PUPD_SHIFT
27866. DA9150_NIRQ_TYPE_MASK
27867. DA9150_NIRQ_TYPE_SHIFT
27868. DA9150_NIRQ_VDD_MASK
27869. DA9150_NIRQ_VDD_SHIFT
27870. DA9150_NUM_IRQ_REGS
27871. DA9150_OTG_FAULT_DIS_MASK
27872. DA9150_OTG_FAULT_DIS_SHIFT
27873. DA9150_OTG_FAULT_MASK
27874. DA9150_OTG_FAULT_SHIFT
27875. DA9150_OTP_CONT_SHARED
27876. DA9150_PAGE_CON
27877. DA9150_PAGE_CON_1
27878. DA9150_PAGE_CON_2
27879. DA9150_PAGE_CON_3
27880. DA9150_PAGE_CON_4
27881. DA9150_PAGE_CON_5
27882. DA9150_PAGE_CON_6
27883. DA9150_PAGE_MASK
27884. DA9150_PAGE_SHIFT
27885. DA9150_PCD_STAT_MASK
27886. DA9150_PCD_STAT_SHIFT
27887. DA9150_PC_DONE_MASK
27888. DA9150_PC_DONE_SHIFT
27889. DA9150_PM_DLY_SEL_MASK
27890. DA9150_PM_DLY_SEL_SHIFT
27891. DA9150_PM_IF_FMP_MASK
27892. DA9150_PM_IF_FMP_SHIFT
27893. DA9150_PM_IF_HSM_MASK
27894. DA9150_PM_IF_HSM_SHIFT
27895. DA9150_PM_IF_LPM_MASK
27896. DA9150_PM_IF_LPM_SHIFT
27897. DA9150_PM_IF_V_MASK
27898. DA9150_PM_IF_V_SHIFT
27899. DA9150_PM_MERGE_MASK
27900. DA9150_PM_MERGE_SHIFT
27901. DA9150_PM_OUT_DLY_SEL_MASK
27902. DA9150_PM_OUT_DLY_SEL_SHIFT
27903. DA9150_PM_SPKSUP_DIS_MASK
27904. DA9150_PM_SPKSUP_DIS_SHIFT
27905. DA9150_PM_SR_OFF_MASK
27906. DA9150_PM_SR_OFF_SHIFT
27907. DA9150_PM_TIMEOUT_EN_MASK
27908. DA9150_PM_TIMEOUT_EN_SHIFT
27909. DA9150_POR_FAULT_MASK
27910. DA9150_POR_FAULT_SHIFT
27911. DA9150_PPR_BKCFG_A
27912. DA9150_PPR_BKCFG_B
27913. DA9150_PPR_BKCTRL_A
27914. DA9150_PPR_CHGCTRL_A
27915. DA9150_PPR_CHGCTRL_B
27916. DA9150_PPR_CHGCTRL_C
27917. DA9150_PPR_CHGCTRL_D
27918. DA9150_PPR_CHGCTRL_E
27919. DA9150_PPR_CHGCTRL_F
27920. DA9150_PPR_CHGCTRL_G
27921. DA9150_PPR_CHGCTRL_H
27922. DA9150_PPR_CHGCTRL_I
27923. DA9150_PPR_CHGCTRL_J
27924. DA9150_PPR_CHGCTRL_K
27925. DA9150_PPR_CHGCTRL_L
27926. DA9150_PPR_CHGCTRL_M
27927. DA9150_PPR_TCTR_A
27928. DA9150_PPR_TCTR_B
27929. DA9150_PPR_THYST_A
27930. DA9150_PPR_THYST_B
27931. DA9150_PPR_THYST_C
27932. DA9150_PPR_THYST_D
27933. DA9150_PPR_THYST_E
27934. DA9150_PPR_THYST_F
27935. DA9150_PPR_THYST_G
27936. DA9150_PS_DISABLE_DIRECT_MASK
27937. DA9150_PS_DISABLE_DIRECT_SHIFT
27938. DA9150_PS_WAIT_EN_MASK
27939. DA9150_PS_WAIT_EN_SHIFT
27940. DA9150_PT_CHG_MASK
27941. DA9150_PT_CHG_SHIFT
27942. DA9150_QIF_BYTE_MASK
27943. DA9150_QIF_BYTE_SIZE
27944. DA9150_QIF_CHARGE_LIMIT
27945. DA9150_QIF_CHARGE_LIMIT_SIZE
27946. DA9150_QIF_CODE_MASK
27947. DA9150_QIF_DISCHARGE_LIMIT
27948. DA9150_QIF_DISCHARGE_LIMIT_SIZE
27949. DA9150_QIF_E_FG_STATUS
27950. DA9150_QIF_E_FG_STATUS_SIZE
27951. DA9150_QIF_FCC_MAH
27952. DA9150_QIF_FCC_MAH_SIZE
27953. DA9150_QIF_FW_MAIN_VER
27954. DA9150_QIF_FW_MAIN_VER_SIZE
27955. DA9150_QIF_I2C_ADDR_LSB
27956. DA9150_QIF_IAVG
27957. DA9150_QIF_IAVG_SIZE
27958. DA9150_QIF_LONG_SIZE
27959. DA9150_QIF_MAX_CODES
27960. DA9150_QIF_NTCAVG
27961. DA9150_QIF_NTCAVG_SIZE
27962. DA9150_QIF_READ
27963. DA9150_QIF_SD_GAIN
27964. DA9150_QIF_SD_GAIN_SIZE
27965. DA9150_QIF_SHORT_SIZE
27966. DA9150_QIF_SHUNT_VAL
27967. DA9150_QIF_SHUNT_VAL_SIZE
27968. DA9150_QIF_SOC_PCT
27969. DA9150_QIF_SOC_PCT_SIZE
27970. DA9150_QIF_SYNC
27971. DA9150_QIF_SYNC_RETRIES
27972. DA9150_QIF_SYNC_SIZE
27973. DA9150_QIF_SYNC_TIMEOUT
27974. DA9150_QIF_UAVG
27975. DA9150_QIF_UAVG_SIZE
27976. DA9150_QIF_WRITE
27977. DA9150_REG_PAGE_MASK
27978. DA9150_REG_PAGE_SHIFT
27979. DA9150_RESET_DUR_MASK
27980. DA9150_RESET_DUR_SHIFT
27981. DA9150_RESET_EXT_MASK
27982. DA9150_RESET_EXT_SHIFT
27983. DA9150_RESET_MASK
27984. DA9150_RESET_SHIFT
27985. DA9150_RESET_USRCONF_EN_MASK
27986. DA9150_RESET_USRCONF_EN_SHIFT
27987. DA9150_REVERT_MASK
27988. DA9150_REVERT_SHIFT
27989. DA9150_RID_CONV_MASK
27990. DA9150_RID_CONV_SHIFT
27991. DA9150_RID_MASK
27992. DA9150_RID_PT_CHG_H_MASK
27993. DA9150_RID_PT_CHG_H_SHIFT
27994. DA9150_RID_PT_CHG_L_MASK
27995. DA9150_RID_PT_CHG_L_SHIFT
27996. DA9150_RID_SHIFT
27997. DA9150_SCD_STAT_MASK
27998. DA9150_SCD_STAT_SHIFT
27999. DA9150_SESS_VLD_MASK
28000. DA9150_SESS_VLD_SHIFT
28001. DA9150_SLEEP_STAT_MASK
28002. DA9150_SLEEP_STAT_SHIFT
28003. DA9150_START_FAULT_MASK
28004. DA9150_START_FAULT_SHIFT
28005. DA9150_START_MAX_MASK
28006. DA9150_START_MAX_SHIFT
28007. DA9150_STATUS_A
28008. DA9150_STATUS_B
28009. DA9150_STATUS_C
28010. DA9150_STATUS_D
28011. DA9150_STATUS_E
28012. DA9150_STATUS_F
28013. DA9150_STATUS_G
28014. DA9150_STATUS_H
28015. DA9150_STATUS_I
28016. DA9150_STATUS_J
28017. DA9150_STATUS_K
28018. DA9150_STATUS_L
28019. DA9150_STATUS_N
28020. DA9150_TADP_PRB_MASK
28021. DA9150_TADP_PRB_SHIFT
28022. DA9150_TADP_RISE_MASK
28023. DA9150_TADP_RISE_SHIFT
28024. DA9150_TAUX_CTRL_A
28025. DA9150_TAUX_EN_MASK
28026. DA9150_TAUX_EN_SHIFT
28027. DA9150_TAUX_MOD_MASK
28028. DA9150_TAUX_MOD_SHIFT
28029. DA9150_TAUX_RELOAD_H
28030. DA9150_TAUX_RELOAD_L
28031. DA9150_TAUX_RLD_H_MASK
28032. DA9150_TAUX_RLD_H_SHIFT
28033. DA9150_TAUX_RLD_L_MASK
28034. DA9150_TAUX_RLD_L_SHIFT
28035. DA9150_TAUX_UPDATE_MASK
28036. DA9150_TAUX_UPDATE_SHIFT
28037. DA9150_TAUX_VALUE_H
28038. DA9150_TAUX_VALUE_L
28039. DA9150_TAUX_VAL_H_MASK
28040. DA9150_TAUX_VAL_H_SHIFT
28041. DA9150_TAUX_VAL_L_MASK
28042. DA9150_TAUX_VAL_L_SHIFT
28043. DA9150_TBAT_CTRL_A
28044. DA9150_TBAT_CTRL_B
28045. DA9150_TBAT_EN_MASK
28046. DA9150_TBAT_EN_SHIFT
28047. DA9150_TBAT_H1_MASK
28048. DA9150_TBAT_H1_SHIFT
28049. DA9150_TBAT_H5_MASK
28050. DA9150_TBAT_H5_SHIFT
28051. DA9150_TBAT_HIGH_CURR_MASK
28052. DA9150_TBAT_HIGH_CURR_SHIFT
28053. DA9150_TBAT_RES_A
28054. DA9150_TBAT_RES_B
28055. DA9150_TBAT_RES_DIS_MASK
28056. DA9150_TBAT_RES_DIS_SHIFT
28057. DA9150_TBAT_RES_H_MASK
28058. DA9150_TBAT_RES_H_SHIFT
28059. DA9150_TBAT_RES_L_MASK
28060. DA9150_TBAT_RES_L_SHIFT
28061. DA9150_TBAT_STAT_SW1_MASK
28062. DA9150_TBAT_STAT_SW1_SHIFT
28063. DA9150_TBAT_STAT_SW2_MASK
28064. DA9150_TBAT_STAT_SW2_SHIFT
28065. DA9150_TBAT_SW1_MASK
28066. DA9150_TBAT_SW1_SHIFT
28067. DA9150_TBAT_SW2_MASK
28068. DA9150_TBAT_SW2_SHIFT
28069. DA9150_TBAT_SW_FRC_MASK
28070. DA9150_TBAT_SW_FRC_SHIFT
28071. DA9150_TBAT_T1_MASK
28072. DA9150_TBAT_T1_SHIFT
28073. DA9150_TBAT_T2_MASK
28074. DA9150_TBAT_T2_SHIFT
28075. DA9150_TBAT_T3_MASK
28076. DA9150_TBAT_T3_SHIFT
28077. DA9150_TBAT_T4_MASK
28078. DA9150_TBAT_T4_SHIFT
28079. DA9150_TBAT_T5_MASK
28080. DA9150_TBAT_T5_SHIFT
28081. DA9150_TBAT_TDP_EN_MASK
28082. DA9150_TBAT_TDP_EN_SHIFT
28083. DA9150_TBAT_TQA_EN_MASK
28084. DA9150_TBAT_TQA_EN_SHIFT
28085. DA9150_TEMP_FAULT_MASK
28086. DA9150_TEMP_FAULT_SHIFT
28087. DA9150_TFAULT_STAT_MASK
28088. DA9150_TFAULT_STAT_SHIFT
28089. DA9150_TID_POLL_MASK
28090. DA9150_TID_POLL_SHIFT
28091. DA9150_VBUS_DROP_MASK
28092. DA9150_VBUS_DROP_SHIFT
28093. DA9150_VBUS_DROP_STAT_MASK
28094. DA9150_VBUS_DROP_STAT_SHIFT
28095. DA9150_VBUS_FAULT_DIS_MASK
28096. DA9150_VBUS_FAULT_DIS_SHIFT
28097. DA9150_VBUS_FAULT_MASK
28098. DA9150_VBUS_FAULT_SHIFT
28099. DA9150_VBUS_IMAX_MASK
28100. DA9150_VBUS_IMAX_SHIFT
28101. DA9150_VBUS_IOTG_MASK
28102. DA9150_VBUS_IOTG_SHIFT
28103. DA9150_VBUS_ISET_MASK
28104. DA9150_VBUS_ISET_SHIFT
28105. DA9150_VBUS_ISET_STAT_MASK
28106. DA9150_VBUS_ISET_STAT_SHIFT
28107. DA9150_VBUS_ISO_MASK
28108. DA9150_VBUS_ISO_SHIFT
28109. DA9150_VBUS_LDO_MASK
28110. DA9150_VBUS_LDO_SHIFT
28111. DA9150_VBUS_LPM_MASK
28112. DA9150_VBUS_LPM_SHIFT
28113. DA9150_VBUS_MODE_CHG
28114. DA9150_VBUS_MODE_MASK
28115. DA9150_VBUS_MODE_OTG
28116. DA9150_VBUS_MODE_SHIFT
28117. DA9150_VBUS_OT_MASK
28118. DA9150_VBUS_OT_SHIFT
28119. DA9150_VBUS_PWM_MASK
28120. DA9150_VBUS_PWM_SHIFT
28121. DA9150_VBUS_STAT_CHG
28122. DA9150_VBUS_STAT_MASK
28123. DA9150_VBUS_STAT_OFF
28124. DA9150_VBUS_STAT_SHIFT
28125. DA9150_VBUS_STAT_WAIT
28126. DA9150_VBUS_SUSP_MASK
28127. DA9150_VBUS_SUSP_SHIFT
28128. DA9150_VBUS_TRED_MASK
28129. DA9150_VBUS_TRED_SHIFT
28130. DA9150_VB_MODE_MASK
28131. DA9150_VB_MODE_SHIFT
28132. DA9150_VB_MODE_VB_SESS
28133. DA9150_VDD33_DWN_MASK
28134. DA9150_VDD33_DWN_SHIFT
28135. DA9150_VDD33_EN_MASK
28136. DA9150_VDD33_EN_SHIFT
28137. DA9150_VDD33_LPM_MASK
28138. DA9150_VDD33_LPM_SHIFT
28139. DA9150_VDD33_SLEEP_MASK
28140. DA9150_VDD33_SLEEP_SHIFT
28141. DA9150_VDD33_SL_MASK
28142. DA9150_VDD33_SL_SHIFT
28143. DA9150_VDD33_STAT_MASK
28144. DA9150_VDD33_STAT_SHIFT
28145. DA9150_VDDIO_INT_MASK
28146. DA9150_VDDIO_INT_SHIFT
28147. DA9150_VFAULT_ADJ_MASK
28148. DA9150_VFAULT_ADJ_SHIFT
28149. DA9150_VFAULT_EN_MASK
28150. DA9150_VFAULT_EN_SHIFT
28151. DA9150_VFAULT_HYST_MASK
28152. DA9150_VFAULT_HYST_SHIFT
28153. DA9150_VFAULT_STAT_MASK
28154. DA9150_VFAULT_STAT_SHIFT
28155. DA9150_VSYS_FAULT_MASK
28156. DA9150_VSYS_FAULT_SHIFT
28157. DA9150_VSYS_MIN_MASK
28158. DA9150_VSYS_MIN_SHIFT
28159. DA9150_WAKE_CONT_MASK
28160. DA9150_WAKE_CONT_SHIFT
28161. DA9150_WAKE_DLY_MASK
28162. DA9150_WAKE_DLY_SHIFT
28163. DA9150_WAKE_MODE_MASK
28164. DA9150_WAKE_MODE_SHIFT
28165. DA9150_WAKE_PIN_MASK
28166. DA9150_WAKE_PIN_SHIFT
28167. DA9150_WDT_AUTO_LOCK_MASK
28168. DA9150_WDT_AUTO_LOCK_SHIFT
28169. DA9150_WDT_AUTO_START_MASK
28170. DA9150_WDT_AUTO_START_SHIFT
28171. DA9150_WDT_HLT_NO_CLK_MASK
28172. DA9150_WDT_HLT_NO_CLK_SHIFT
28173. DA9150_WKUP_CE_SEL_MASK
28174. DA9150_WKUP_CE_SEL_SHIFT
28175. DA9150_WKUP_CLK32K_EN_MASK
28176. DA9150_WKUP_CLK32K_EN_SHIFT
28177. DA9150_WKUP_PM_EN_MASK
28178. DA9150_WKUP_PM_EN_SHIFT
28179. DA9150_WKUP_STAT_MASK
28180. DA9150_WKUP_STAT_SHIFT
28181. DA9150_WRITE_MODE_MASK
28182. DA9150_WRITE_MODE_SHIFT
28183. DA9210_BUCK_EN
28184. DA9210_BUCK_GPI_GPIO0
28185. DA9210_BUCK_GPI_GPIO3
28186. DA9210_BUCK_GPI_GPIO4
28187. DA9210_BUCK_GPI_MASK
28188. DA9210_BUCK_GPI_OFF
28189. DA9210_BUCK_GPI_SHIFT
28190. DA9210_BUCK_IALARM
28191. DA9210_BUCK_ILIM_MASK
28192. DA9210_BUCK_ILIM_SHIFT
28193. DA9210_BUCK_MODE_AUTO
28194. DA9210_BUCK_MODE_MANUAL
28195. DA9210_BUCK_MODE_MASK
28196. DA9210_BUCK_MODE_SHIFT
28197. DA9210_BUCK_MODE_SLEEP
28198. DA9210_BUCK_MODE_SYNC
28199. DA9210_BUCK_PD_DIS
28200. DA9210_BUCK_SL
28201. DA9210_DEBOUNCING_MASK
28202. DA9210_DEBOUNCING_SHIFT
28203. DA9210_DVC_CTRL_EN
28204. DA9210_DVC_STEP_SIZE
28205. DA9210_DVC_STEP_SIZE_10MV
28206. DA9210_DVC_STEP_SIZE_20MV
28207. DA9210_E_GPI0
28208. DA9210_E_GPI1
28209. DA9210_E_GPI2
28210. DA9210_E_GPI3
28211. DA9210_E_GPI4
28212. DA9210_E_GPI5
28213. DA9210_E_GPI6
28214. DA9210_E_NPWRGOOD
28215. DA9210_E_OVCURR
28216. DA9210_E_TEMP_CRIT
28217. DA9210_E_TEMP_WARN
28218. DA9210_E_VMAX
28219. DA9210_FREQ_SEL
28220. DA9210_GPI0
28221. DA9210_GPI1
28222. DA9210_GPI2
28223. DA9210_GPI3
28224. DA9210_GPI4
28225. DA9210_GPI5
28226. DA9210_GPI6
28227. DA9210_GPIO0_MODE
28228. DA9210_GPIO0_PIN_GPI
28229. DA9210_GPIO0_PIN_GPO
28230. DA9210_GPIO0_PIN_GPO_OD
28231. DA9210_GPIO0_PIN_MASK
28232. DA9210_GPIO0_PIN_SHIFT
28233. DA9210_GPIO0_TYPE
28234. DA9210_GPIO0_TYPE_GPI
28235. DA9210_GPIO0_TYPE_GPO
28236. DA9210_GPIO1_MODE
28237. DA9210_GPIO1_PIN_GPI
28238. DA9210_GPIO1_PIN_GPO
28239. DA9210_GPIO1_PIN_GPO_OD
28240. DA9210_GPIO1_PIN_MASK
28241. DA9210_GPIO1_PIN_SHIFT
28242. DA9210_GPIO1_PIN_VERROR
28243. DA9210_GPIO1_TYPE_GPI
28244. DA9210_GPIO1_TYPE_GPO
28245. DA9210_GPIO1_TYPE_SHIFT
28246. DA9210_GPIO2_MODE
28247. DA9210_GPIO2_PIN_GPI
28248. DA9210_GPIO2_PIN_GPO
28249. DA9210_GPIO2_PIN_GPO_OD
28250. DA9210_GPIO2_PIN_MASK
28251. DA9210_GPIO2_PIN_SHIFT
28252. DA9210_GPIO2_TYPE
28253. DA9210_GPIO2_TYPE_GPI
28254. DA9210_GPIO2_TYPE_GPO
28255. DA9210_GPIO3_MODE
28256. DA9210_GPIO3_PIN_GPI
28257. DA9210_GPIO3_PIN_GPO
28258. DA9210_GPIO3_PIN_GPO_OD
28259. DA9210_GPIO3_PIN_IERROR
28260. DA9210_GPIO3_PIN_MASK
28261. DA9210_GPIO3_PIN_SHIFT
28262. DA9210_GPIO3_TYPE_GPI
28263. DA9210_GPIO3_TYPE_GPO
28264. DA9210_GPIO3_TYPE_SHIFT
28265. DA9210_GPIO4_MODE
28266. DA9210_GPIO4_PIN_GPI
28267. DA9210_GPIO4_PIN_GPO
28268. DA9210_GPIO4_PIN_GPO_OD
28269. DA9210_GPIO4_PIN_MASK
28270. DA9210_GPIO4_PIN_SHIFT
28271. DA9210_GPIO4_TYPE
28272. DA9210_GPIO4_TYPE_GPI
28273. DA9210_GPIO4_TYPE_GPO
28274. DA9210_GPIO5_MODE
28275. DA9210_GPIO5_PIN_BUCK_CLK
28276. DA9210_GPIO5_PIN_GPI
28277. DA9210_GPIO5_PIN_GPO
28278. DA9210_GPIO5_PIN_GPO_OD
28279. DA9210_GPIO5_PIN_INTERFACE
28280. DA9210_GPIO5_PIN_MASK
28281. DA9210_GPIO5_PIN_SHIFT
28282. DA9210_GPIO5_TYPE_GPI
28283. DA9210_GPIO5_TYPE_GPO
28284. DA9210_GPIO5_TYPE_SHIFT
28285. DA9210_GPIO6_MODE
28286. DA9210_GPIO6_PIN_GPI
28287. DA9210_GPIO6_PIN_GPO
28288. DA9210_GPIO6_PIN_GPO_OD
28289. DA9210_GPIO6_PIN_INTERFACE
28290. DA9210_GPIO6_PIN_MASK
28291. DA9210_GPIO6_PIN_SHIFT
28292. DA9210_GPIO6_TYPE
28293. DA9210_GPIO6_TYPE_GPI
28294. DA9210_GPIO6_TYPE_GPO
28295. DA9210_IF_BASE_ADDR_MASK
28296. DA9210_IF_BASE_ADDR_SHIFT
28297. DA9210_MAX_MV
28298. DA9210_MIN_MV
28299. DA9210_M_GPI0
28300. DA9210_M_GPI1
28301. DA9210_M_GPI2
28302. DA9210_M_GPI3
28303. DA9210_M_GPI4
28304. DA9210_M_GPI5
28305. DA9210_M_GPI6
28306. DA9210_M_NPWRGOOD
28307. DA9210_M_OVCURR
28308. DA9210_M_TEMP_CRIT
28309. DA9210_M_TEMP_WARN
28310. DA9210_M_VMAX
28311. DA9210_PAGE_REVERT
28312. DA9210_PAGE_WRITE_MODE
28313. DA9210_PEG_PAGE_SHIFT
28314. DA9210_PHASE_SEL_MASK
28315. DA9210_PHASE_SEL_SHIFT
28316. DA9210_PWR_DOWN_CTRL_MASK
28317. DA9210_PWR_DOWN_CTRL_SHIFT
28318. DA9210_REG_BUCK_CONF1
28319. DA9210_REG_BUCK_CONF2
28320. DA9210_REG_BUCK_CONT
28321. DA9210_REG_BUCK_ILIM
28322. DA9210_REG_CONFIG_A
28323. DA9210_REG_CONFIG_B
28324. DA9210_REG_CONFIG_C
28325. DA9210_REG_CONFIG_D
28326. DA9210_REG_CONFIG_E
28327. DA9210_REG_CONTROL_A
28328. DA9210_REG_EVENT_A
28329. DA9210_REG_EVENT_B
28330. DA9210_REG_GPIO_0_1
28331. DA9210_REG_GPIO_2_3
28332. DA9210_REG_GPIO_4_5
28333. DA9210_REG_GPIO_6
28334. DA9210_REG_INTERFACE
28335. DA9210_REG_MASK_A
28336. DA9210_REG_MASK_B
28337. DA9210_REG_OPT_ADDR
28338. DA9210_REG_OPT_COUNT
28339. DA9210_REG_OPT_DATA
28340. DA9210_REG_PAGE0
28341. DA9210_REG_PAGE2
28342. DA9210_REG_PAGE_CON
28343. DA9210_REG_PAGE_MASK
28344. DA9210_REG_STATUS_A
28345. DA9210_REG_STATUS_B
28346. DA9210_REG_VBACK_AUTO
28347. DA9210_REG_VBACK_BASE
28348. DA9210_REG_VBACK_DVC
28349. DA9210_REG_VBACK_MAX_DVC_IF
28350. DA9210_REG_VBUCK_A
28351. DA9210_REG_VBUCK_B
28352. DA9210_REPEAT_WRITE_MODE
28353. DA9210_SLEW_RATE_MASK
28354. DA9210_SLEW_RATE_SHIFT
28355. DA9210_STAND_ALONE
28356. DA9210_STARTUP_CTRL_MASK
28357. DA9210_STARTUP_CTRL_SHIFT
28358. DA9210_STEP_MV
28359. DA9210_VBUCK_AUTO_MASK
28360. DA9210_VBUCK_AUTO_SHIFT
28361. DA9210_VBUCK_BASE_MASK
28362. DA9210_VBUCK_BASE_SHIFT
28363. DA9210_VBUCK_BIAS
28364. DA9210_VBUCK_DVC_MASK
28365. DA9210_VBUCK_DVC_SHIFT
28366. DA9210_VBUCK_GPI_GPIO0
28367. DA9210_VBUCK_GPI_GPIO3
28368. DA9210_VBUCK_GPI_GPIO4
28369. DA9210_VBUCK_GPI_MASK
28370. DA9210_VBUCK_GPI_OFF
28371. DA9210_VBUCK_GPI_SHIFT
28372. DA9210_VBUCK_MASK
28373. DA9210_VBUCK_MAX_MASK
28374. DA9210_VBUCK_MAX_SHIFT
28375. DA9210_VBUCK_SEL
28376. DA9210_VBUCK_SEL_A
28377. DA9210_VBUCK_SEL_B
28378. DA9210_VBUCK_SHIFT
28379. DA9210_V_LOCK
28380. DA9211
28381. DA9211_BUCK
28382. DA9211_BUCKA_DOWN_CTRL_MASK
28383. DA9211_BUCKA_DOWN_CTRL_SHIFT
28384. DA9211_BUCKA_EN
28385. DA9211_BUCKA_GPI_GPIO0
28386. DA9211_BUCKA_GPI_GPIO1
28387. DA9211_BUCKA_GPI_GPIO3
28388. DA9211_BUCKA_GPI_MASK
28389. DA9211_BUCKA_GPI_OFF
28390. DA9211_BUCKA_GPI_SHIFT
28391. DA9211_BUCKA_ILIM_MASK
28392. DA9211_BUCKA_ILIM_SHIFT
28393. DA9211_BUCKA_MODE_AUTO
28394. DA9211_BUCKA_MODE_MANUAL
28395. DA9211_BUCKA_MODE_MASK
28396. DA9211_BUCKA_MODE_SHIFT
28397. DA9211_BUCKA_MODE_SLEEP
28398. DA9211_BUCKA_MODE_SYNC
28399. DA9211_BUCKA_PD_DIS
28400. DA9211_BUCKA_UP_CTRL_MASK
28401. DA9211_BUCKA_UP_CTRL_SHIFT
28402. DA9211_BUCKB_DOWN_CTRL_MASK
28403. DA9211_BUCKB_DOWN_CTRL_SHIFT
28404. DA9211_BUCKB_EN
28405. DA9211_BUCKB_GPI_GPIO0
28406. DA9211_BUCKB_GPI_GPIO1
28407. DA9211_BUCKB_GPI_GPIO3
28408. DA9211_BUCKB_GPI_MASK
28409. DA9211_BUCKB_GPI_OFF
28410. DA9211_BUCKB_GPI_SHIFT
28411. DA9211_BUCKB_ILIM_MASK
28412. DA9211_BUCKB_ILIM_SHIFT
28413. DA9211_BUCKB_MODE_AUTO
28414. DA9211_BUCKB_MODE_MANUAL
28415. DA9211_BUCKB_MODE_MASK
28416. DA9211_BUCKB_MODE_SHIFT
28417. DA9211_BUCKB_MODE_SLEEP
28418. DA9211_BUCKB_MODE_SYNC
28419. DA9211_BUCKB_PD_DIS
28420. DA9211_BUCKB_UP_CTRL_MASK
28421. DA9211_BUCKB_UP_CTRL_SHIFT
28422. DA9211_BUCK_MODE_AUTO
28423. DA9211_BUCK_MODE_SLEEP
28424. DA9211_BUCK_MODE_SYNC
28425. DA9211_BUCK_SL
28426. DA9211_DEBOUNCING_MASK
28427. DA9211_DEBOUNCING_SHIFT
28428. DA9211_DEVICE_ID
28429. DA9211_E_GPI0
28430. DA9211_E_GPI1
28431. DA9211_E_GPI2
28432. DA9211_E_GPI3
28433. DA9211_E_GPI4
28434. DA9211_E_OV_CURR_A
28435. DA9211_E_OV_CURR_B
28436. DA9211_E_PWRGOOD_A
28437. DA9211_E_PWRGOOD_B
28438. DA9211_E_TEMP_CRIT
28439. DA9211_E_TEMP_WARN
28440. DA9211_E_UVLO_IO
28441. DA9211_GPI0
28442. DA9211_GPI1
28443. DA9211_GPI2
28444. DA9211_GPI3
28445. DA9211_GPI4
28446. DA9211_GPIO0_MODE
28447. DA9211_GPIO0_PIN_GPI
28448. DA9211_GPIO0_PIN_GPO
28449. DA9211_GPIO0_PIN_GPO_OD
28450. DA9211_GPIO0_PIN_MASK
28451. DA9211_GPIO0_PIN_SHIFT
28452. DA9211_GPIO0_TYPE
28453. DA9211_GPIO0_TYPE_GPI
28454. DA9211_GPIO0_TYPE_GPO
28455. DA9211_GPIO1_MODE
28456. DA9211_GPIO1_PIN_GPI
28457. DA9211_GPIO1_PIN_GPO
28458. DA9211_GPIO1_PIN_GPO_OD
28459. DA9211_GPIO1_PIN_MASK
28460. DA9211_GPIO1_PIN_SHIFT
28461. DA9211_GPIO1_PIN_VERROR
28462. DA9211_GPIO1_TYPE_GPI
28463. DA9211_GPIO1_TYPE_GPO
28464. DA9211_GPIO1_TYPE_SHIFT
28465. DA9211_GPIO2_MODE
28466. DA9211_GPIO2_PIN_GPI
28467. DA9211_GPIO2_PIN_GPO
28468. DA9211_GPIO2_PIN_GPO_OD
28469. DA9211_GPIO2_PIN_MASK
28470. DA9211_GPIO2_PIN_SHIFT
28471. DA9211_GPIO2_TYPE
28472. DA9211_GPIO2_TYPE_GPI
28473. DA9211_GPIO2_TYPE_GPO
28474. DA9211_GPIO3_MODE
28475. DA9211_GPIO3_PIN_GPI
28476. DA9211_GPIO3_PIN_GPO
28477. DA9211_GPIO3_PIN_GPO_OD
28478. DA9211_GPIO3_PIN_IERROR
28479. DA9211_GPIO3_PIN_MASK
28480. DA9211_GPIO3_PIN_SHIFT
28481. DA9211_GPIO3_TYPE_GPI
28482. DA9211_GPIO3_TYPE_GPO
28483. DA9211_GPIO3_TYPE_SHIFT
28484. DA9211_GPIO4_MODE
28485. DA9211_GPIO4_PIN_GPI
28486. DA9211_GPIO4_PIN_GPO
28487. DA9211_GPIO4_PIN_GPO_OD
28488. DA9211_GPIO4_PIN_MASK
28489. DA9211_GPIO4_PIN_SHIFT
28490. DA9211_GPIO4_TYPE
28491. DA9211_GPIO4_TYPE_GPI
28492. DA9211_GPIO4_TYPE_GPO
28493. DA9211_GPIO5_PIN_BUCK_CLK
28494. DA9211_ID_BUCKA
28495. DA9211_ID_BUCKB
28496. DA9211_IF_BASE_ADDR_MASK
28497. DA9211_IF_BASE_ADDR_SHIFT
28498. DA9211_MAX_MV
28499. DA9211_MAX_REGULATORS
28500. DA9211_MIN_MV
28501. DA9211_M_GPI0
28502. DA9211_M_GPI1
28503. DA9211_M_GPI2
28504. DA9211_M_GPI3
28505. DA9211_M_GPI4
28506. DA9211_M_OV_CURR_A
28507. DA9211_M_OV_CURR_B
28508. DA9211_M_PWRGOOD_A
28509. DA9211_M_PWRGOOD_B
28510. DA9211_M_TEMP_CRIT
28511. DA9211_M_TEMP_WARN
28512. DA9211_M_UVLO_IO
28513. DA9211_PAGE_REVERT
28514. DA9211_PAGE_WRITE_MODE
28515. DA9211_PHASE_SEL_A_MASK
28516. DA9211_PHASE_SEL_A_SHIFT
28517. DA9211_PHASE_SEL_B_MASK
28518. DA9211_PHASE_SEL_B_SHIFT
28519. DA9211_PH_SH_EN_A_MASK
28520. DA9211_PH_SH_EN_A_SHIFT
28521. DA9211_PH_SH_EN_B_MASK
28522. DA9211_PH_SH_EN_B_SHIFT
28523. DA9211_REG_BUCKA_CONF
28524. DA9211_REG_BUCKA_CONT
28525. DA9211_REG_BUCKB_CONF
28526. DA9211_REG_BUCKB_CONT
28527. DA9211_REG_BUCK_CONF
28528. DA9211_REG_BUCK_ILIM
28529. DA9211_REG_CONFIG_E
28530. DA9211_REG_CONTROL_A
28531. DA9211_REG_DEVICE_ID
28532. DA9211_REG_EVENT_A
28533. DA9211_REG_EVENT_B
28534. DA9211_REG_GPIO_0_1
28535. DA9211_REG_GPIO_2_3
28536. DA9211_REG_GPIO_4
28537. DA9211_REG_INTERFACE
28538. DA9211_REG_MASK_A
28539. DA9211_REG_MASK_B
28540. DA9211_REG_PAGE0
28541. DA9211_REG_PAGE2
28542. DA9211_REG_PAGE_CON
28543. DA9211_REG_PAGE_MASK
28544. DA9211_REG_PAGE_SHIFT
28545. DA9211_REG_STATUS_A
28546. DA9211_REG_STATUS_B
28547. DA9211_REG_VBACKA_MAX
28548. DA9211_REG_VBACKB_MAX
28549. DA9211_REG_VBUCKA_A
28550. DA9211_REG_VBUCKA_B
28551. DA9211_REG_VBUCKB_A
28552. DA9211_REG_VBUCKB_B
28553. DA9211_REPEAT_WRITE_MODE
28554. DA9211_SLAVE_SEL
28555. DA9211_SLEW_RATE_A_MASK
28556. DA9211_SLEW_RATE_B_MASK
28557. DA9211_SLEW_RATE_B_SHIFT
28558. DA9211_SLEW_RATE_SHIFT
28559. DA9211_STEP_MV
28560. DA9211_VBUCKA_BASE_MASK
28561. DA9211_VBUCKA_BASE_SHIFT
28562. DA9211_VBUCKA_GPI_GPIO1
28563. DA9211_VBUCKA_GPI_GPIO2
28564. DA9211_VBUCKA_GPI_GPIO4
28565. DA9211_VBUCKA_GPI_MASK
28566. DA9211_VBUCKA_GPI_OFF
28567. DA9211_VBUCKA_GPI_SHIFT
28568. DA9211_VBUCKA_SEL
28569. DA9211_VBUCKA_SEL_A
28570. DA9211_VBUCKA_SEL_B
28571. DA9211_VBUCKB_BASE_MASK
28572. DA9211_VBUCKB_BASE_SHIFT
28573. DA9211_VBUCKB_GPI_GPIO1
28574. DA9211_VBUCKB_GPI_GPIO2
28575. DA9211_VBUCKB_GPI_GPIO4
28576. DA9211_VBUCKB_GPI_MASK
28577. DA9211_VBUCKB_GPI_OFF
28578. DA9211_VBUCKB_GPI_SHIFT
28579. DA9211_VBUCKB_SEL
28580. DA9211_VBUCKB_SEL_A
28581. DA9211_VBUCKB_SEL_B
28582. DA9211_VBUCK_BIAS
28583. DA9211_VBUCK_MASK
28584. DA9211_VBUCK_SHIFT
28585. DA9211_V_LOCK
28586. DA9212
28587. DA9213
28588. DA9213_DEVICE_ID
28589. DA9214
28590. DA9215
28591. DA9215_DEVICE_ID
28592. DA9223
28593. DA9224
28594. DA9225
28595. DABRX_ALL
28596. DABRX_BTI
28597. DABRX_HYP
28598. DABRX_KERNEL
28599. DABRX_USER
28600. DAC
28601. DAC02_AO_LSB
28602. DAC02_AO_MSB
28603. DAC0_EXT_REF_BIT
28604. DAC0_REG
28605. DAC0_UNIPOLAR_BIT
28606. DAC1
28607. DAC1064_OPT_GDIV1
28608. DAC1064_OPT_GDIV3
28609. DAC1064_OPT_MDIV1
28610. DAC1064_OPT_MDIV2
28611. DAC1064_OPT_RESERVED
28612. DAC1064_OPT_SCLK_EXT
28613. DAC1064_OPT_SCLK_MASK
28614. DAC1064_OPT_SCLK_PCI
28615. DAC1064_OPT_SCLK_PLL
28616. DAC1064_XSYSPLLM
28617. DAC1064_XSYSPLLN
28618. DAC1064_XSYSPLLP
28619. DAC1064_XSYSPLLSTAT
28620. DAC1064_XVREFCTRL
28621. DAC1064_XVREFCTRL_EXTERNAL
28622. DAC1064_XVREFCTRL_G100_DEFAULT
28623. DAC1064_XVREFCTRL_INTERNAL
28624. DAC1064_calcclock
28625. DAC1064_global_init
28626. DAC1064_global_restore
28627. DAC1064_init_1
28628. DAC1064_init_2
28629. DAC1064_restore_1
28630. DAC1064_restore_2
28631. DAC1064_setmclk
28632. DAC1064_setpclk
28633. DAC12
28634. DAC12_CK
28635. DAC12_K
28636. DAC12_R
28637. DAC1_CLK_SEL
28638. DAC1_ENCODER_CONTROL_PARAMETERS
28639. DAC1_ENCODER_CONTROL_PS_ALLOCATION
28640. DAC1_EXT_REF_BIT
28641. DAC1_REG
28642. DAC1_UNIPOLAR_BIT
28643. DAC2
28644. DAC2OutputControl
28645. DAC2_ADR
28646. DAC2_CMP_EN
28647. DAC2_DATA
28648. DAC2_ENCODER_CONTROL_PARAMETERS
28649. DAC2_ENCODER_CONTROL_PS_ALLOCATION
28650. DAC2_EXPAND_MODE
28651. DAC2_PALETTE_ACCESS_CNTL
28652. DAC3100
28653. DAC3101
28654. DAC31XX_BIT
28655. DAC33_ADJSTEP
28656. DAC33_ADJTHRSHLD
28657. DAC33_AFMT_DSP
28658. DAC33_AFMT_I2S
28659. DAC33_AFMT_LEFT_J
28660. DAC33_AFMT_MASK
28661. DAC33_AFMT_RIGHT_J
28662. DAC33_ANA_VOL_SOFT_STEP_CTRL
28663. DAC33_ASRC_CTRL_A
28664. DAC33_ASRC_CTRL_B
28665. DAC33_ATHR_LSB
28666. DAC33_ATHR_MSB
28667. DAC33_ATM
28668. DAC33_BCLKON
28669. DAC33_CACHEREGNUM
28670. DAC33_CALIB_TIME
28671. DAC33_DACDUAL
28672. DAC33_DACLKSEL_BCLK
28673. DAC33_DACLKSEL_INTSOC
28674. DAC33_DACLKSEL_MASK
28675. DAC33_DACLKSEL_MCLK
28676. DAC33_DACLKSEL_PLL
28677. DAC33_DACLPDNB
28678. DAC33_DACLRNUM
28679. DAC33_DACRATE
28680. DAC33_DACRPDNB
28681. DAC33_DACSRCL_LEFT
28682. DAC33_DACSRCL_MASK
28683. DAC33_DACSRCL_MONOMIX
28684. DAC33_DACSRCL_MUTE
28685. DAC33_DACSRCL_RIGHT
28686. DAC33_DACSRCR_LEFT
28687. DAC33_DACSRCR_MASK
28688. DAC33_DACSRCR_MONOMIX
28689. DAC33_DACSRCR_MUTE
28690. DAC33_DACSRCR_RIGHT
28691. DAC33_DAC_CTRL_A
28692. DAC33_DAC_CTRL_B
28693. DAC33_DAC_CTRL_C
28694. DAC33_DAC_STATUS_FLAGS
28695. DAC33_DATA_DELAY
28696. DAC33_DATA_DELAY_MASK
28697. DAC33_DEEMENL
28698. DAC33_DEEMENR
28699. DAC33_DEVICE_ID_LSB
28700. DAC33_DEVICE_ID_MSB
28701. DAC33_DEVICE_REV_ID
28702. DAC33_DVOLCTRL_LR_INDEPENDENT1
28703. DAC33_DVOLCTRL_LR_INDEPENDENT2
28704. DAC33_DVOLCTRL_LR_LEFT_CONTROL
28705. DAC33_DVOLCTRL_LR_RIGHT_CONTROL
28706. DAC33_DVOLCTRL_MASK
28707. DAC33_DVOLSTEP_MASK
28708. DAC33_DVOLSTEP_SS_DISABLED
28709. DAC33_DVOLSTEP_SS_PER2FS
28710. DAC33_DVOLSTEP_SS_PERFS
28711. DAC33_EFFENL
28712. DAC33_EFFENR
28713. DAC33_EN3D
28714. DAC33_FAUTO
28715. DAC33_FBYPAS
28716. DAC33_FIFOFLUSH
28717. DAC33_FIFO_BYPASS
28718. DAC33_FIFO_CTRL_A
28719. DAC33_FIFO_DEPTH_LSB
28720. DAC33_FIFO_DEPTH_MSB
28721. DAC33_FIFO_IRQ_FLAG
28722. DAC33_FIFO_IRQ_MASK
28723. DAC33_FIFO_IRQ_MODE_A
28724. DAC33_FIFO_IRQ_MODE_B
28725. DAC33_FIFO_IRQ_MODE_EDGE
28726. DAC33_FIFO_IRQ_MODE_FALLING
28727. DAC33_FIFO_IRQ_MODE_LEVEL
28728. DAC33_FIFO_IRQ_MODE_MASK
28729. DAC33_FIFO_IRQ_MODE_RISING
28730. DAC33_FIFO_LAST_MODE
28731. DAC33_FIFO_MODE1
28732. DAC33_FIFO_MODE7
28733. DAC33_FIFO_RPTR_LSB
28734. DAC33_FIFO_RPTR_MSB
28735. DAC33_FIFO_SIZE_16BIT
28736. DAC33_FIFO_SIZE_24BIT
28737. DAC33_FIFO_WPTR_LSB
28738. DAC33_FIFO_WPTR_MSB
28739. DAC33_FLUSH
28740. DAC33_FORMATS
28741. DAC33_I2C_ADDR_AUTOINC
28742. DAC33_IDLE
28743. DAC33_INTPM_AHIGH
28744. DAC33_INTPM_ALOW
28745. DAC33_INTPM_ALOW_OPENDRAIN
28746. DAC33_INTPM_MASK
28747. DAC33_INTPSEL
28748. DAC33_INTP_CTRL_A
28749. DAC33_INTP_CTRL_B
28750. DAC33_INT_OSC_CTRL
28751. DAC33_INT_OSC_CTRL_B
28752. DAC33_INT_OSC_CTRL_C
28753. DAC33_INT_OSC_DAC_RATIO_READ
28754. DAC33_INT_OSC_DAC_RATIO_SET
28755. DAC33_INT_OSC_FREQ_RAT_A
28756. DAC33_INT_OSC_FREQ_RAT_B
28757. DAC33_INT_OSC_FREQ_RAT_READ_A
28758. DAC33_INT_OSC_FREQ_RAT_READ_B
28759. DAC33_INT_OSC_STATUS
28760. DAC33_LDAC_DIG_VOL_CTRL
28761. DAC33_LDAC_PWR_CTRL
28762. DAC33_LINEL_TO_LLO_VOL
28763. DAC33_LINER_TO_RLO_VOL
28764. DAC33_LROUT_GAIN
28765. DAC33_LTHR_LSB
28766. DAC33_LTHR_MSB
28767. DAC33_LTM
28768. DAC33_MAT
28769. DAC33_MLT
28770. DAC33_MNS
28771. DAC33_MODE7_MARGIN
28772. DAC33_MOF
28773. DAC33_MPS
28774. DAC33_MSBCLK
28775. DAC33_MSWCLK
28776. DAC33_MUF
28777. DAC33_MUT
28778. DAC33_NCYCL_16
28779. DAC33_NCYCL_20
28780. DAC33_NCYCL_24
28781. DAC33_NCYCL_32
28782. DAC33_NCYCL_MASK
28783. DAC33_NSAMPLE_LSB
28784. DAC33_NSAMPLE_MSB
28785. DAC33_NSM
28786. DAC33_NUM_SUPPLIES
28787. DAC33_OFM
28788. DAC33_OSCPDNB
28789. DAC33_OSCSTATUS_ADJUSTMENT
28790. DAC33_OSCSTATUS_IDLE_CALIB
28791. DAC33_OSCSTATUS_NORMAL
28792. DAC33_OSCSTATUS_NOT_USED
28793. DAC33_OSC_TRIM
28794. DAC33_OUT_AMP_CM_CTRL
28795. DAC33_OUT_AMP_CTRL
28796. DAC33_OUT_AMP_PWR_CTRL
28797. DAC33_PAGE_SELECT
28798. DAC33_PDNALLB
28799. DAC33_PLAYBACK
28800. DAC33_PLLPDNB
28801. DAC33_PLL_CTRL_A
28802. DAC33_PLL_CTRL_B
28803. DAC33_PLL_CTRL_C
28804. DAC33_PLL_CTRL_D
28805. DAC33_PLL_CTRL_E
28806. DAC33_PREFILL
28807. DAC33_PREFILL_LSB
28808. DAC33_PREFILL_MSB
28809. DAC33_PSM
28810. DAC33_PWR_CTRL
28811. DAC33_RATES
28812. DAC33_RDAC_DIG_VOL_CTRL
28813. DAC33_RDAC_PWR_CTRL
28814. DAC33_REFDIV
28815. DAC33_REFSEL
28816. DAC33_RESYNEN
28817. DAC33_RESYNMUTE
28818. DAC33_SAMPLES_REMAINING_LSB
28819. DAC33_SAMPLES_REMAINING_MSB
28820. DAC33_SER_AUDIOIF_CTRL_A
28821. DAC33_SER_AUDIOIF_CTRL_B
28822. DAC33_SER_AUDIOIF_CTRL_C
28823. DAC33_SOFT_RESET
28824. DAC33_SRCBYP
28825. DAC33_SRCLKDIV
28826. DAC33_SRCLKSEL_BCLK
28827. DAC33_SRCLKSEL_INTSOC
28828. DAC33_SRCLKSEL_MASK
28829. DAC33_SRCLKSEL_MCLK
28830. DAC33_SRCLKSEL_PLL
28831. DAC33_SRCREFDIV
28832. DAC33_SRCREFSEL
28833. DAC33_SRCSETUP
28834. DAC33_SRC_EST_REF_CLK_RATIO_A
28835. DAC33_SRC_EST_REF_CLK_RATIO_B
28836. DAC33_SRC_REF_CLK_RATIO_A
28837. DAC33_SRC_REF_CLK_RATIO_B
28838. DAC33_THRREG
28839. DAC33_UFM
28840. DAC33_UTHR_LSB
28841. DAC33_UTHR_MSB
28842. DAC33_UTM
28843. DAC33_VOLBYPASS
28844. DAC33_VOLCLKEN
28845. DAC33_VOLCLKSEL
28846. DAC33_WIDTH
28847. DAC33_WLEN_16
28848. DAC33_WLEN_20
28849. DAC33_WLEN_24
28850. DAC33_WLEN_32
28851. DAC33_WLEN_MASK
28852. DAC5571_CHANNEL_SELECT
28853. DAC5571_LOADMODE_DIRECT
28854. DAC5571_POWERDOWN
28855. DAC5571_POWERDOWN_FLAG
28856. DAC5571_QUAD_PWRDWN_BITS
28857. DAC5571_SINGLE_PWRDWN_BITS
28858. DAC7612_ADDRESS
28859. DAC7612_RESOLUTION
28860. DAC7612_START
28861. DAC960_BA_CMDMBX_OFFSET
28862. DAC960_BA_CMDSTS_OFFSET
28863. DAC960_BA_ERRSTS_OFFSET
28864. DAC960_BA_ERRSTS_PENDING
28865. DAC960_BA_IDB_CTRL_RESET
28866. DAC960_BA_IDB_GEN_IRQ
28867. DAC960_BA_IDB_HWMBOX_ACK_STS
28868. DAC960_BA_IDB_HWMBOX_EMPTY
28869. DAC960_BA_IDB_HWMBOX_NEW_CMD
28870. DAC960_BA_IDB_INIT_DONE
28871. DAC960_BA_IDB_MMBOX_NEW_CMD
28872. DAC960_BA_IDB_OFFSET
28873. DAC960_BA_IRQMASK_DISABLEW_I2O
28874. DAC960_BA_IRQMASK_DISABLE_IRQ
28875. DAC960_BA_IRQMASK_OFFSET
28876. DAC960_BA_IRQSTS_OFFSET
28877. DAC960_BA_ODB_HWMBOX_ACK_IRQ
28878. DAC960_BA_ODB_HWMBOX_STS_AVAIL
28879. DAC960_BA_ODB_MMBOX_ACK_IRQ
28880. DAC960_BA_ODB_MMBOX_STS_AVAIL
28881. DAC960_BA_ODB_OFFSET
28882. DAC960_BA_ack_hw_mbox_intr
28883. DAC960_BA_ack_hw_mbox_status
28884. DAC960_BA_ack_intr
28885. DAC960_BA_ack_mem_mbox_intr
28886. DAC960_BA_disable_intr
28887. DAC960_BA_enable_intr
28888. DAC960_BA_gen_intr
28889. DAC960_BA_hw_init
28890. DAC960_BA_hw_mbox_is_full
28891. DAC960_BA_hw_mbox_new_cmd
28892. DAC960_BA_hw_mbox_status_available
28893. DAC960_BA_init_in_progress
28894. DAC960_BA_intr_enabled
28895. DAC960_BA_intr_handler
28896. DAC960_BA_mbox_init
28897. DAC960_BA_mem_mbox_new_cmd
28898. DAC960_BA_mem_mbox_status_available
28899. DAC960_BA_mmio_size
28900. DAC960_BA_read_cmd_ident
28901. DAC960_BA_read_cmd_status
28902. DAC960_BA_read_error_status
28903. DAC960_BA_reg_offset
28904. DAC960_BA_reset_ctrl
28905. DAC960_BA_write_cmd_mbox
28906. DAC960_BA_write_hw_mbox
28907. DAC960_GEM_CMDMBX_OFFSET
28908. DAC960_GEM_CMDSTS_OFFSET
28909. DAC960_GEM_ERRSTS_CLEAR_OFFSET
28910. DAC960_GEM_ERRSTS_PENDING
28911. DAC960_GEM_ERRSTS_READ_OFFSET
28912. DAC960_GEM_IDB_CLEAR_OFFSET
28913. DAC960_GEM_IDB_CTRL_RESET
28914. DAC960_GEM_IDB_GEN_IRQ
28915. DAC960_GEM_IDB_HWMBOX_ACK_STS
28916. DAC960_GEM_IDB_HWMBOX_FULL
28917. DAC960_GEM_IDB_HWMBOX_NEW_CMD
28918. DAC960_GEM_IDB_INIT_IN_PROGRESS
28919. DAC960_GEM_IDB_MMBOX_NEW_CMD
28920. DAC960_GEM_IDB_READ_OFFSET
28921. DAC960_GEM_IRQMASK_CLEAR_OFFSET
28922. DAC960_GEM_IRQMASK_HWMBOX_IRQ
28923. DAC960_GEM_IRQMASK_MMBOX_IRQ
28924. DAC960_GEM_IRQMASK_READ_OFFSET
28925. DAC960_GEM_IRQSTS_OFFSET
28926. DAC960_GEM_ODB_CLEAR_OFFSET
28927. DAC960_GEM_ODB_HWMBOX_ACK_IRQ
28928. DAC960_GEM_ODB_HWMBOX_STS_AVAIL
28929. DAC960_GEM_ODB_MMBOX_ACK_IRQ
28930. DAC960_GEM_ODB_MMBOX_STS_AVAIL
28931. DAC960_GEM_ODB_READ_OFFSET
28932. DAC960_GEM_ack_hw_mbox_intr
28933. DAC960_GEM_ack_hw_mbox_status
28934. DAC960_GEM_ack_intr
28935. DAC960_GEM_ack_mem_mbox_intr
28936. DAC960_GEM_disable_intr
28937. DAC960_GEM_enable_intr
28938. DAC960_GEM_gen_intr
28939. DAC960_GEM_hw_init
28940. DAC960_GEM_hw_mbox_is_full
28941. DAC960_GEM_hw_mbox_new_cmd
28942. DAC960_GEM_hw_mbox_status_available
28943. DAC960_GEM_init_in_progress
28944. DAC960_GEM_intr_enabled
28945. DAC960_GEM_intr_handler
28946. DAC960_GEM_mbox_init
28947. DAC960_GEM_mem_mbox_new_cmd
28948. DAC960_GEM_mem_mbox_status_available
28949. DAC960_GEM_mmio_size
28950. DAC960_GEM_read_cmd_ident
28951. DAC960_GEM_read_cmd_status
28952. DAC960_GEM_read_error_status
28953. DAC960_GEM_reg_offset
28954. DAC960_GEM_reset_ctrl
28955. DAC960_GEM_write_cmd_mbox
28956. DAC960_GEM_write_hw_mbox
28957. DAC960_LA_CMDID_OFFSET
28958. DAC960_LA_CMDOP_OFFSET
28959. DAC960_LA_ERRSTS_OFFSET
28960. DAC960_LA_ERRSTS_PENDING
28961. DAC960_LA_IDB_CTRL_RESET
28962. DAC960_LA_IDB_GEN_IRQ
28963. DAC960_LA_IDB_HWMBOX_ACK_STS
28964. DAC960_LA_IDB_HWMBOX_EMPTY
28965. DAC960_LA_IDB_HWMBOX_NEW_CMD
28966. DAC960_LA_IDB_INIT_DONE
28967. DAC960_LA_IDB_MMBOX_NEW_CMD
28968. DAC960_LA_IDB_OFFSET
28969. DAC960_LA_IRQMASK_DISABLE_IRQ
28970. DAC960_LA_IRQMASK_OFFSET
28971. DAC960_LA_MBOX10_OFFSET
28972. DAC960_LA_MBOX11_OFFSET
28973. DAC960_LA_MBOX12_OFFSET
28974. DAC960_LA_MBOX2_OFFSET
28975. DAC960_LA_MBOX3_OFFSET
28976. DAC960_LA_MBOX4_OFFSET
28977. DAC960_LA_MBOX5_OFFSET
28978. DAC960_LA_MBOX6_OFFSET
28979. DAC960_LA_MBOX7_OFFSET
28980. DAC960_LA_MBOX8_OFFSET
28981. DAC960_LA_MBOX9_OFFSET
28982. DAC960_LA_ODB_HWMBOX_ACK_IRQ
28983. DAC960_LA_ODB_HWMBOX_STS_AVAIL
28984. DAC960_LA_ODB_MMBOX_ACK_IRQ
28985. DAC960_LA_ODB_MMBOX_STS_AVAIL
28986. DAC960_LA_ODB_OFFSET
28987. DAC960_LA_STSID_OFFSET
28988. DAC960_LA_STS_OFFSET
28989. DAC960_LA_ack_hw_mbox_intr
28990. DAC960_LA_ack_hw_mbox_status
28991. DAC960_LA_ack_intr
28992. DAC960_LA_ack_mem_mbox_intr
28993. DAC960_LA_disable_intr
28994. DAC960_LA_enable_intr
28995. DAC960_LA_gen_intr
28996. DAC960_LA_hw_init
28997. DAC960_LA_hw_mbox_is_full
28998. DAC960_LA_hw_mbox_new_cmd
28999. DAC960_LA_hw_mbox_status_available
29000. DAC960_LA_init_in_progress
29001. DAC960_LA_intr_enabled
29002. DAC960_LA_intr_handler
29003. DAC960_LA_mbox_init
29004. DAC960_LA_mem_mbox_new_cmd
29005. DAC960_LA_mem_mbox_status_available
29006. DAC960_LA_mmio_size
29007. DAC960_LA_read_error_status
29008. DAC960_LA_read_status
29009. DAC960_LA_read_status_cmd_ident
29010. DAC960_LA_reg_offset
29011. DAC960_LA_reset_ctrl
29012. DAC960_LA_write_cmd_mbox
29013. DAC960_LA_write_hw_mbox
29014. DAC960_LP_CMDMBX_OFFSET
29015. DAC960_LP_CMDSTS_OFFSET
29016. DAC960_LP_ERRSTS_OFFSET
29017. DAC960_LP_ERRSTS_PENDING
29018. DAC960_LP_IDB_CTRL_RESET
29019. DAC960_LP_IDB_GEN_IRQ
29020. DAC960_LP_IDB_HWMBOX_ACK_STS
29021. DAC960_LP_IDB_HWMBOX_FULL
29022. DAC960_LP_IDB_HWMBOX_NEW_CMD
29023. DAC960_LP_IDB_INIT_IN_PROGRESS
29024. DAC960_LP_IDB_MMBOX_NEW_CMD
29025. DAC960_LP_IDB_OFFSET
29026. DAC960_LP_IRQMASK_DISABLE_IRQ
29027. DAC960_LP_IRQMASK_OFFSET
29028. DAC960_LP_IRQSTS_OFFSET
29029. DAC960_LP_ODB_HWMBOX_ACK_IRQ
29030. DAC960_LP_ODB_HWMBOX_STS_AVAIL
29031. DAC960_LP_ODB_MMBOX_ACK_IRQ
29032. DAC960_LP_ODB_MMBOX_STS_AVAIL
29033. DAC960_LP_ODB_OFFSET
29034. DAC960_LP_ack_hw_mbox_intr
29035. DAC960_LP_ack_hw_mbox_status
29036. DAC960_LP_ack_intr
29037. DAC960_LP_ack_mem_mbox_intr
29038. DAC960_LP_disable_intr
29039. DAC960_LP_enable_intr
29040. DAC960_LP_gen_intr
29041. DAC960_LP_hw_init
29042. DAC960_LP_hw_mbox_is_full
29043. DAC960_LP_hw_mbox_new_cmd
29044. DAC960_LP_hw_mbox_status_available
29045. DAC960_LP_init_in_progress
29046. DAC960_LP_intr_enabled
29047. DAC960_LP_intr_handler
29048. DAC960_LP_mbox_init
29049. DAC960_LP_mem_mbox_new_cmd
29050. DAC960_LP_mem_mbox_status_available
29051. DAC960_LP_mmio_size
29052. DAC960_LP_read_cmd_ident
29053. DAC960_LP_read_cmd_status
29054. DAC960_LP_read_error_status
29055. DAC960_LP_reg_offset
29056. DAC960_LP_reset_ctrl
29057. DAC960_LP_write_cmd_mbox
29058. DAC960_LP_write_hw_mbox
29059. DAC960_MAJOR
29060. DAC960_PD_CMDID_OFFSET
29061. DAC960_PD_CMDOP_OFFSET
29062. DAC960_PD_ERRSTS_OFFSET
29063. DAC960_PD_ERRSTS_PENDING
29064. DAC960_PD_IDB_CTRL_RESET
29065. DAC960_PD_IDB_GEN_IRQ
29066. DAC960_PD_IDB_HWMBOX_ACK_STS
29067. DAC960_PD_IDB_HWMBOX_FULL
29068. DAC960_PD_IDB_HWMBOX_NEW_CMD
29069. DAC960_PD_IDB_INIT_IN_PROGRESS
29070. DAC960_PD_IDB_OFFSET
29071. DAC960_PD_IRQEN_OFFSET
29072. DAC960_PD_IRQMASK_ENABLE_IRQ
29073. DAC960_PD_MBOX10_OFFSET
29074. DAC960_PD_MBOX11_OFFSET
29075. DAC960_PD_MBOX12_OFFSET
29076. DAC960_PD_MBOX2_OFFSET
29077. DAC960_PD_MBOX3_OFFSET
29078. DAC960_PD_MBOX4_OFFSET
29079. DAC960_PD_MBOX5_OFFSET
29080. DAC960_PD_MBOX6_OFFSET
29081. DAC960_PD_MBOX7_OFFSET
29082. DAC960_PD_MBOX8_OFFSET
29083. DAC960_PD_MBOX9_OFFSET
29084. DAC960_PD_ODB_HWMBOX_ACK_IRQ
29085. DAC960_PD_ODB_HWMBOX_STS_AVAIL
29086. DAC960_PD_ODB_OFFSET
29087. DAC960_PD_STSID_OFFSET
29088. DAC960_PD_STS_OFFSET
29089. DAC960_PD_ack_hw_mbox_status
29090. DAC960_PD_ack_intr
29091. DAC960_PD_disable_intr
29092. DAC960_PD_enable_intr
29093. DAC960_PD_gen_intr
29094. DAC960_PD_hw_init
29095. DAC960_PD_hw_mbox_is_full
29096. DAC960_PD_hw_mbox_new_cmd
29097. DAC960_PD_hw_mbox_status_available
29098. DAC960_PD_init_in_progress
29099. DAC960_PD_intr_enabled
29100. DAC960_PD_intr_handler
29101. DAC960_PD_mmio_size
29102. DAC960_PD_qcmd
29103. DAC960_PD_read_error_status
29104. DAC960_PD_read_status
29105. DAC960_PD_read_status_cmd_ident
29106. DAC960_PD_reg_offset
29107. DAC960_PD_reset_ctrl
29108. DAC960_PD_write_cmd_mbox
29109. DAC960_PG_CMDID_OFFSET
29110. DAC960_PG_CMDOP_OFFSET
29111. DAC960_PG_ERRSTS_OFFSET
29112. DAC960_PG_ERRSTS_PENDING
29113. DAC960_PG_IDB_CTRL_RESET
29114. DAC960_PG_IDB_GEN_IRQ
29115. DAC960_PG_IDB_HWMBOX_ACK_STS
29116. DAC960_PG_IDB_HWMBOX_FULL
29117. DAC960_PG_IDB_HWMBOX_NEW_CMD
29118. DAC960_PG_IDB_INIT_IN_PROGRESS
29119. DAC960_PG_IDB_MMBOX_NEW_CMD
29120. DAC960_PG_IDB_OFFSET
29121. DAC960_PG_IRQMASK_DISABLE_IRQ
29122. DAC960_PG_IRQMASK_MSI_MASK1
29123. DAC960_PG_IRQMASK_MSI_MASK2
29124. DAC960_PG_IRQMASK_OFFSET
29125. DAC960_PG_MBOX10_OFFSET
29126. DAC960_PG_MBOX11_OFFSET
29127. DAC960_PG_MBOX12_OFFSET
29128. DAC960_PG_MBOX2_OFFSET
29129. DAC960_PG_MBOX3_OFFSET
29130. DAC960_PG_MBOX4_OFFSET
29131. DAC960_PG_MBOX5_OFFSET
29132. DAC960_PG_MBOX6_OFFSET
29133. DAC960_PG_MBOX7_OFFSET
29134. DAC960_PG_MBOX8_OFFSET
29135. DAC960_PG_MBOX9_OFFSET
29136. DAC960_PG_ODB_HWMBOX_ACK_IRQ
29137. DAC960_PG_ODB_HWMBOX_STS_AVAIL
29138. DAC960_PG_ODB_MMBOX_ACK_IRQ
29139. DAC960_PG_ODB_MMBOX_STS_AVAIL
29140. DAC960_PG_ODB_OFFSET
29141. DAC960_PG_STSID_OFFSET
29142. DAC960_PG_STS_OFFSET
29143. DAC960_PG_ack_hw_mbox_intr
29144. DAC960_PG_ack_hw_mbox_status
29145. DAC960_PG_ack_intr
29146. DAC960_PG_ack_mem_mbox_intr
29147. DAC960_PG_disable_intr
29148. DAC960_PG_enable_intr
29149. DAC960_PG_gen_intr
29150. DAC960_PG_hw_init
29151. DAC960_PG_hw_mbox_is_full
29152. DAC960_PG_hw_mbox_new_cmd
29153. DAC960_PG_hw_mbox_status_available
29154. DAC960_PG_init_in_progress
29155. DAC960_PG_intr_enabled
29156. DAC960_PG_intr_handler
29157. DAC960_PG_mbox_init
29158. DAC960_PG_mem_mbox_new_cmd
29159. DAC960_PG_mem_mbox_status_available
29160. DAC960_PG_mmio_size
29161. DAC960_PG_read_error_status
29162. DAC960_PG_read_status
29163. DAC960_PG_read_status_cmd_ident
29164. DAC960_PG_reg_offset
29165. DAC960_PG_reset_ctrl
29166. DAC960_PG_write_cmd_mbox
29167. DAC960_PG_write_hw_mbox
29168. DAC960_P_hw_init
29169. DAC960_P_intr_handler
29170. DAC960_P_qcmd
29171. DAC960_V1_1164P
29172. DAC960_V1_GetEventLogEntry
29173. DAC960_V1_PG
29174. DAC960_V1_PJ
29175. DAC960_V1_PL
29176. DAC960_V1_PR
29177. DAC960_V1_PRL
29178. DAC960_V1_PT
29179. DAC960_V1_PTL0
29180. DAC960_V1_PTL1
29181. DAC960_V1_P_PD_PU
29182. DACADDR
29183. DACALIBRATION1
29184. DACALIBRATION2
29185. DACA_AUTODETECT_INTERRUPT
29186. DACA_AUTODETECT_INT_CONTROL
29187. DACA_AUTO_DETECT_CONTROL
29188. DACA_I2C_ADDR
29189. DACA_REG_AVOL
29190. DACA_REG_GCFG
29191. DACA_REG_SR
29192. DACA_SOFT_RESET
29193. DACA_SOFT_RESET_0
29194. DACA_SOFT_RESET_1
29195. DACA_VOL_MAX
29196. DACB_AUTODETECT_INTERRUPT
29197. DACB_AUTODETECT_INT_CONTROL
29198. DACB_AUTO_DETECT_CONTROL
29199. DACCRSTAT_MAX_TRYS
29200. DACDATA
29201. DACDelay
29202. DACEN
29203. DACEQFILT_EQEN_DISABLE
29204. DACEQFILT_EQEN_ENABLE
29205. DACH
29206. DACInfoFlag
29207. DACK0_B_MARK
29208. DACK0_C_MARK
29209. DACK0_MARK
29210. DACK0_PD_MARK
29211. DACK0_PE_MARK
29212. DACK1_A_MARK
29213. DACK1_B_MARK
29214. DACK1_MARK
29215. DACK1_PD_MARK
29216. DACK1_PE_MARK
29217. DACK2_A_MARK
29218. DACK2_B_MARK
29219. DACK2_C_MARK
29220. DACK2_MARK
29221. DACK3_MARK
29222. DACKA
29223. DACK_DCK_BACKUP_NUM
29224. DACK_MARK
29225. DACK_MSBK_BACKUP_NUM
29226. DACK_PATH_8822C
29227. DACK_POLARITY
29228. DACK_REG_8822C
29229. DACK_RF_8822C
29230. DACK_SN_8822C
29231. DACL
29232. DACL1_2_HPLCOM_VOL
29233. DACL1_2_HPLOUT_VOL
29234. DACL1_2_HPRCOM_VOL
29235. DACL1_2_HPROUT_VOL
29236. DACL1_2_LLOPM_VOL
29237. DACL1_2_MONOLOPM_VOL
29238. DACL1_2_RLOPM_VOL
29239. DACL_CLK_MASK
29240. DACL_CLK_OFF
29241. DACL_CLK_ON
29242. DACL_INIT_MASK
29243. DACL_INIT_OFF
29244. DACL_INIT_ON
29245. DACL_MASK
29246. DACL_OFF
29247. DACL_ON
29248. DACL_PATH_REFV_MASK
29249. DACL_PATH_REFV_OFF
29250. DACL_PATH_REFV_ON
29251. DACL_REFV_MASK
29252. DACL_REFV_OFF
29253. DACL_REFV_ON
29254. DACL_SECINFO
29255. DACL_SELECT
29256. DACL_SELECT_MASK
29257. DACL_UNSELECT
29258. DACMASK
29259. DACMBCEN_MBCEN_DISABLE
29260. DACMBCEN_MBCEN_ENABLE
29261. DACMODE
29262. DACMODE_2X
29263. DACOP
29264. DACR
29265. DACR1_2_HPLCOM_VOL
29266. DACR1_2_HPLOUT_VOL
29267. DACR1_2_HPRCOM_VOL
29268. DACR1_2_HPROUT_VOL
29269. DACR1_2_LLOPM_VOL
29270. DACR1_2_MONOLOPM_VOL
29271. DACR1_2_RLOPM_VOL
29272. DACR32_EL2
29273. DACREG_AC0_I
29274. DACREG_AC1_I
29275. DACREG_ADDR_I
29276. DACREG_BD0_I
29277. DACREG_BD1_I
29278. DACREG_CC_CLKA
29279. DACREG_CC_CLKA_C
29280. DACREG_CC_CLKB
29281. DACREG_CC_CLKB_D
29282. DACREG_CC_I
29283. DACREG_CR0_16BPP
29284. DACREG_CR0_24BPP
29285. DACREG_CR0_8BIT
29286. DACREG_CR0_EN_INDEXED
29287. DACREG_CR0_I
29288. DACREG_CR0_PWDOWN
29289. DACREG_CR1_I
29290. DACREG_DATA_I
29291. DACREG_DIR_ATT
29292. DACREG_DIR_TI
29293. DACREG_ICS_CLK0
29294. DACREG_ICS_CLK0_0
29295. DACREG_ICS_CLK1_A
29296. DACREG_ICS_CMD
29297. DACREG_ICS_CMD_16BPP
29298. DACREG_ICS_CMD_24BPP
29299. DACREG_ICS_CMD_PWDOWN
29300. DACREG_ICS_PLLDATA
29301. DACREG_ICS_PLLRMA
29302. DACREG_ICS_PLLWMA
29303. DACREG_ICS_PLL_CLK0_1_INI
29304. DACREG_ICS_PLL_CLK0_7_INI
29305. DACREG_ICS_PLL_CLK1_B_INI
29306. DACREG_ICS_PLL_CTRL
29307. DACREG_LUT
29308. DACREG_MIR_ATT
29309. DACREG_MIR_TI
29310. DACREG_RMA
29311. DACREG_RMR
29312. DACREG_RMR_I
29313. DACREG_WMA
29314. DACRX
29315. DACR_CLK_MASK
29316. DACR_CLK_OFF
29317. DACR_CLK_ON
29318. DACR_DAE
29319. DACR_DAOE0
29320. DACR_DAOE1
29321. DACR_INIT
29322. DACR_INIT_MASK
29323. DACR_INIT_OFF
29324. DACR_INIT_ON
29325. DACR_MASK
29326. DACR_OFF
29327. DACR_ON
29328. DACR_PATH_REFV_MASK
29329. DACR_PATH_REFV_OFF
29330. DACR_PATH_REFV_ON
29331. DACR_REFV_MASK
29332. DACR_REFV_OFF
29333. DACR_REFV_ON
29334. DACR_SELECT
29335. DACR_SELECT_MASK
29336. DACR_UACCESS_DISABLE
29337. DACR_UACCESS_ENABLE
29338. DACR_UNSELECT
29339. DACSPEED16
29340. DACSPEED24_SD
29341. DACSPEED24_SG
29342. DACSPEED32
29343. DACSPEED8
29344. DACSTATE
29345. DACWX
29346. DAC_0dB
29347. DAC_4BPP_PIX_ORDER
29348. DAC_6_BIT
29349. DAC_8BIT_EN
29350. DAC_8_BIT
29351. DAC_ACTIVE_BIT
29352. DAC_ADR
29353. DAC_ATI68860_B
29354. DAC_ATI68860_C
29355. DAC_ATI68875
29356. DAC_ATT20C408
29357. DAC_ATT20C491
29358. DAC_ATT21C498
29359. DAC_ATT498
29360. DAC_ATTEN_MAX
29361. DAC_ATTEN_MIN
29362. DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK
29363. DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT
29364. DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK
29365. DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT
29366. DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK
29367. DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT
29368. DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK
29369. DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT
29370. DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK
29371. DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT
29372. DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK
29373. DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT
29374. DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK
29375. DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT
29376. DAC_AUTODETECT_INT_CONTROL
29377. DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK
29378. DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT
29379. DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK
29380. DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT
29381. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK
29382. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT
29383. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK
29384. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT
29385. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK
29386. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT
29387. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK
29388. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT
29389. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK
29390. DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT
29391. DAC_AUXG
29392. DAC_AUXG_AUXG
29393. DAC_A_0_7_V
29394. DAC_A_1_1_V
29395. DAC_A_1_3_V
29396. DAC_A_ENABLE
29397. DAC_A_MASK
29398. DAC_BASE
29399. DAC_BCP_MASK
29400. DAC_BCP_NORMAL
29401. DAC_BCP_REVERSAL
29402. DAC_BIT
29403. DAC_BIT_NUM_MASK
29404. DAC_BIT_NUM_MASK_SFT
29405. DAC_BIT_NUM_SFT
29406. DAC_BLANKING
29407. DAC_BLANK_ADJ_0
29408. DAC_BLANK_ADJ_1
29409. DAC_BLANK_ADJ_2
29410. DAC_BLANK_ADJ_MASK
29411. DAC_BLANK_LEVEL
29412. DAC_BROAD_PULSE
29413. DAC_BT476
29414. DAC_BT481
29415. DAC_BUFFER_CLEAR_REG
29416. DAC_BUS_FREE_TIME
29417. DAC_BYTE
29418. DAC_B_0_7_V
29419. DAC_B_1_1_V
29420. DAC_B_1_3_V
29421. DAC_B_ENABLE
29422. DAC_B_MASK
29423. DAC_CFG_HD_HZUVW_OFF_MASK
29424. DAC_CH1
29425. DAC_CH2
29426. DAC_CH8398
29427. DAC_CHARGE_CURRENT_02I
29428. DAC_CHARGE_CURRENT_02I_MASK
29429. DAC_CHARGE_CURRENT_04I
29430. DAC_CHARGE_CURRENT_04I_MASK
29431. DAC_CHARGE_CURRENT_08I
29432. DAC_CHARGE_CURRENT_08I_MASK
29433. DAC_CHARGE_CURRENT_16I
29434. DAC_CHARGE_CURRENT_16I_MASK
29435. DAC_CHARGE_CURRENT_32I
29436. DAC_CHARGE_CURRENT_32I_MASK
29437. DAC_CHARGE_CURRENT_64I
29438. DAC_CHARGE_CURRENT_64I_MASK
29439. DAC_CHARGE_CURRENT_ALL_MASK
29440. DAC_CHARGE_CURRENT_ALL_OFF
29441. DAC_CHARGE_CURRENT_ALL_ON
29442. DAC_CHARGE_CURRENT_I
29443. DAC_CHARGE_CURRENT_I_MASK
29444. DAC_CHARGE_DISCHARGE
29445. DAC_CHARGE_PRECHARGE
29446. DAC_CHARGE_XCHARGE_MASK
29447. DAC_CLK_CTRL
29448. DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK
29449. DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT
29450. DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK
29451. DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT
29452. DAC_CLK_SEL
29453. DAC_CMP_DISABLE
29454. DAC_CMP_EN
29455. DAC_CMP_OUTPUT
29456. DAC_CNTL
29457. DAC_CNTL2
29458. DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK
29459. DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT
29460. DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK
29461. DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT
29462. DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK
29463. DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT
29464. DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK
29465. DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT
29466. DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK
29467. DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT
29468. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK
29469. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT
29470. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK
29471. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT
29472. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK
29473. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK
29474. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT
29475. DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT
29476. DAC_CONTROL0_REG
29477. DAC_CONTROL1_REG
29478. DAC_CONTROL__DAC_DFORCE_EN_MASK
29479. DAC_CONTROL__DAC_DFORCE_EN__SHIFT
29480. DAC_CONTROL__DAC_TV_ENABLE_MASK
29481. DAC_CONTROL__DAC_TV_ENABLE__SHIFT
29482. DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK
29483. DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT
29484. DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK
29485. DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT
29486. DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK
29487. DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT
29488. DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK
29489. DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT
29490. DAC_CRC_EN
29491. DAC_CRC_EN__DAC_CRC_CONT_EN_MASK
29492. DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT
29493. DAC_CRC_EN__DAC_CRC_EN_MASK
29494. DAC_CRC_EN__DAC_CRC_EN__SHIFT
29495. DAC_CRC_SIG1
29496. DAC_CRC_SIG2
29497. DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK
29498. DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT
29499. DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK
29500. DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT
29501. DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK
29502. DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT
29503. DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK
29504. DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT
29505. DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK
29506. DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT
29507. DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK
29508. DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT
29509. DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK
29510. DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT
29511. DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK
29512. DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT
29513. DAC_CSFC
29514. DAC_CSFC_OVRSEL
29515. DAC_CTL_OVERRIDE
29516. DAC_CTRL
29517. DAC_CTRL_ONAUXIN
29518. DAC_CTRL_ONDACL
29519. DAC_CTRL_ONDACR
29520. DAC_CTRL_ONLNIL
29521. DAC_CTRL_ONLNIR
29522. DAC_CTRL_ONLNOL
29523. DAC_CTRL_ONLNOR
29524. DAC_CTRL_ONPADRV
29525. DAC_CYCLIC_STOP_BIT
29526. DAC_C_0_7_V
29527. DAC_C_1_1_V
29528. DAC_C_1_3_V
29529. DAC_C_MASK
29530. DAC_DATA
29531. DAC_DATA_HOLD_TIME
29532. DAC_DATA_SETUP_TIME
29533. DAC_DATA__DAC_DATA_MASK
29534. DAC_DATA__DAC_DATA__SHIFT
29535. DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK
29536. DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT
29537. DAC_DIN_A
29538. DAC_DIN_B
29539. DAC_DONE_BIT
29540. DAC_EMBEDDED_SYNC_CNTL
29541. DAC_ENABLE_BIT
29542. DAC_ENABLE__DAC_ENABLE_MASK
29543. DAC_ENABLE__DAC_ENABLE__SHIFT
29544. DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK
29545. DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT
29546. DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK
29547. DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT
29548. DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK
29549. DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT
29550. DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK
29551. DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT
29552. DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK
29553. DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT
29554. DAC_ENCODER_CONTROL_PARAMETERS
29555. DAC_ENCODER_CONTROL_PS_ALLOCATION
29556. DAC_EN_MASK
29557. DAC_EN_MASK_SFT
29558. DAC_EN_SFT
29559. DAC_EXPAND_MODE
29560. DAC_EXT_CNTL
29561. DAC_EXT_SEL_RS2
29562. DAC_EXT_SEL_RS3
29563. DAC_EXT_UPDATE_ENABLE_BIT
29564. DAC_EXT_UPDATE_FALLING_BIT
29565. DAC_FEA_CON_EN
29566. DAC_FIFO_BITS
29567. DAC_FIFO_REG
29568. DAC_FIFO_SIZE
29569. DAC_FIFO_SIZE_MASK
29570. DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK
29571. DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT
29572. DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK
29573. DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT
29574. DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK
29575. DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT
29576. DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK
29577. DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT
29578. DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK
29579. DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT
29580. DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK
29581. DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT
29582. DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK
29583. DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT
29584. DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK
29585. DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT
29586. DAC_FORCE_BLANK_OFF_EN
29587. DAC_FORCE_DATA_EN
29588. DAC_FORCE_DATA_MASK
29589. DAC_FORCE_DATA_SEL_MASK
29590. DAC_FORCE_DATA_SHIFT
29591. DAC_FORCE_DATA__DAC_FORCE_DATA_MASK
29592. DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT
29593. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK
29594. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT
29595. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK
29596. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT
29597. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK
29598. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT
29599. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK
29600. DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT
29601. DAC_FREF
29602. DAC_FROM_REG
29603. DAC_GAIN_0DB
29604. DAC_GAIN_0P2DB
29605. DAC_GAIN_0P4DB
29606. DAC_GAIN_0P6DB
29607. DAC_GAIN_0P8DB
29608. DAC_GAIN_M0P2DB
29609. DAC_GAIN_M0P4DB
29610. DAC_GAIN_M0P6DB
29611. DAC_HALF
29612. DAC_HIGH_SETUP_TIME
29613. DAC_I2S_LRP_MASK
29614. DAC_I2S_LRP_NORMAL
29615. DAC_I2S_LRP_REVERSAL
29616. DAC_I2S_MODE_MASK
29617. DAC_I2S_MODE_MASTER
29618. DAC_I2S_MODE_SLAVE
29619. DAC_IBMRGB514
29620. DAC_ICC_ADJ
29621. DAC_IMSG174
29622. DAC_INCR
29623. DAC_INDEX
29624. DAC_INIT_CTRL1
29625. DAC_INIT_CTRL2
29626. DAC_INIT_CTRL3
29627. DAC_INTERNAL
29628. DAC_INTR_HIGH_CHAN_BITS
29629. DAC_INTR_PENDING_BIT
29630. DAC_INTR_QEMPTY_BITS
29631. DAC_INTR_SRC_MASK
29632. DAC_Info
29633. DAC_LCD_BRIGHTNESS
29634. DAC_LEFT
29635. DAC_LIMIT
29636. DAC_LINE_MUX
29637. DAC_LLIG
29638. DAC_LLIG_LLIG
29639. DAC_LLOG
29640. DAC_LLOG_LLOG
29641. DAC_LMPG
29642. DAC_LMPG_LMPG
29643. DAC_LOAD_DETECTION_PARAMETERS
29644. DAC_LOAD_DETECTION_PS_ALLOCATION
29645. DAC_LOAD_MISC_YPrPb
29646. DAC_LOW_SETUP_TIME
29647. DAC_LR_SWAP_DIS
29648. DAC_LR_SWAP_EN
29649. DAC_LR_SWAP_MASK
29650. DAC_LSB_REG
29651. DAC_MACRO_CNTL
29652. DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK
29653. DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT
29654. DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK
29655. DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT
29656. DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK
29657. DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT
29658. DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK
29659. DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT
29660. DAC_MASK
29661. DAC_MASK_ALL
29662. DAC_MASK__DAC_MASK_MASK
29663. DAC_MASK__DAC_MASK__SHIFT
29664. DAC_MAX
29665. DAC_MC
29666. DAC_MC_INVL
29667. DAC_MC_INVR
29668. DAC_MC_LMSMIN1
29669. DAC_MC_LMSMIN2
29670. DAC_MC_RMSMIN1
29671. DAC_MC_RMSMIN2
29672. DAC_MIN
29673. DAC_MISC
29674. DAC_MISC_DEEMPEN
29675. DAC_MISC_DINTSEL
29676. DAC_MISC_DITHEN
29677. DAC_MISC_NBITS
29678. DAC_MISC_VCMCAPSEL
29679. DAC_MISTERY_BIT
29680. DAC_MODE_I2S
29681. DAC_MODE_LJM
29682. DAC_MODE_MASK
29683. DAC_MODE_PCM
29684. DAC_MODE_RJM
29685. DAC_MSB_REG
29686. DAC_MU9C1880
29687. DAC_MUTE
29688. DAC_MUX_SELECT
29689. DAC_MUX_SELECT_DACA
29690. DAC_MUX_SELECT_DACB
29691. DAC_NEG_SYNC_LEVEL
29692. DAC_OFF
29693. DAC_OFFSET
29694. DAC_OLC
29695. DAC_OLC_LOLC
29696. DAC_OLC_LSHORT
29697. DAC_OLC_ROLC
29698. DAC_OLC_RSHORT
29699. DAC_ON
29700. DAC_OUTPUT_ENABLE_BIT
29701. DAC_OUTPUT_LEVEL_MASK
29702. DAC_OUTPUT_MASK
29703. DAC_PALETTE2_SNOOP_EN
29704. DAC_PALETTE_ACCESS_CNTL
29705. DAC_PAR
29706. DAC_PDWN
29707. DAC_PIX_DLY_0NS
29708. DAC_PIX_DLY_2NS
29709. DAC_PIX_DLY_4NS
29710. DAC_PIX_DLY_MASK
29711. DAC_PLL_CONFIG_REG
29712. DAC_POS_SYNC_LEVEL
29713. DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK
29714. DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT
29715. DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK
29716. DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT
29717. DAC_POWERDOWN__DAC_POWERDOWN_MASK
29718. DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK
29719. DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT
29720. DAC_POWERDOWN__DAC_POWERDOWN__SHIFT
29721. DAC_POWER_EVENT
29722. DAC_PRECH
29723. DAC_PRECHARGE_CTRL
29724. DAC_PRECH_ONMSTR
29725. DAC_PRECH_PRCHG
29726. DAC_PRECH_PRCHGAUX1
29727. DAC_PRECH_PRCHGLNIL
29728. DAC_PRECH_PRCHGLNIR
29729. DAC_PRECH_PRCHGLNOL
29730. DAC_PRECH_PRCHGLNOR
29731. DAC_PRECH_PRCHGPDRV
29732. DAC_PSEUDO8_16
29733. DAC_PSEUDO8_8
29734. DAC_PWR
29735. DAC_PWR_CNTL__DAC_BG_MODE_MASK
29736. DAC_PWR_CNTL__DAC_BG_MODE__SHIFT
29737. DAC_PWR_CNTL__DAC_PWRCNTL_MASK
29738. DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT
29739. DAC_PWR_CTRL
29740. DAC_PWR_MASK
29741. DAC_PWR_OFF
29742. DAC_PWR_ON
29743. DAC_QUAD
29744. DAC_RANGE_CNTL
29745. DAC_RANGE_CNTL_MASK
29746. DAC_READ
29747. DAC_READ_CMD
29748. DAC_REGS
29749. DAC_RES
29750. DAC_RGB0565_16
29751. DAC_RGB0565_8
29752. DAC_RGB0888_16
29753. DAC_RGB0888_8
29754. DAC_RGB1555_16
29755. DAC_RGB1555_8
29756. DAC_RGB8888_16
29757. DAC_RGB8888_8
29758. DAC_RIGHT
29759. DAC_RLIG
29760. DAC_RLIG_RLIG
29761. DAC_RLOG
29762. DAC_RLOG_RLOG
29763. DAC_RMPG
29764. DAC_RMPG_RMPG
29765. DAC_RST
29766. DAC_RST_DIS
29767. DAC_RST_EN
29768. DAC_RST_MASK
29769. DAC_RST_RESFILZ
29770. DAC_RST_RESMASK
29771. DAC_RST_RSTZ
29772. DAC_RUNNING
29773. DAC_R_INDEX
29774. DAC_R_INDEX__DAC_R_INDEX_MASK
29775. DAC_R_INDEX__DAC_R_INDEX__SHIFT
29776. DAC_SAMPLE_INTERVAL_LOWER_REG
29777. DAC_SAMPLE_INTERVAL_UPPER_REG
29778. DAC_SC15021
29779. DAC_SC15026
29780. DAC_SCL_HIGH_HOLD_TIME
29781. DAC_SCL_LOW_HOLD_TIME
29782. DAC_SELECT
29783. DAC_SELECT_REG
29784. DAC_SKEW_CLKS
29785. DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK
29786. DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT
29787. DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK
29788. DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT
29789. DAC_SPEAKER_VOLUME
29790. DAC_START_HOLD_TIME
29791. DAC_START_REG
29792. DAC_START_SETUP_TIME
29793. DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK
29794. DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT
29795. DAC_STG1700
29796. DAC_STG1702
29797. DAC_STG1703
29798. DAC_STOP_SETUP_TIME
29799. DAC_SW_GATE_BIT
29800. DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK
29801. DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT
29802. DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK
29803. DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT
29804. DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK
29805. DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT
29806. DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK
29807. DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT
29808. DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK
29809. DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT
29810. DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK
29811. DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT
29812. DAC_TO_REG
29813. DAC_TVP3026_A
29814. DAC_TVP3026_B
29815. DAC_TYPE_MASK
29816. DAC_UNDERRUN_BIT
29817. DAC_UPDATE_POLARITY_BIT
29818. DAC_USAGE
29819. DAC_VDL_16BITS
29820. DAC_VDL_20BITS
29821. DAC_VDL_24BITS
29822. DAC_VDL_32BITS
29823. DAC_VDL_MASK
29824. DAC_VGA_ADR_EN
29825. DAC_WAVEFORM_MODE_BIT
29826. DAC_WL_16BITS
29827. DAC_WL_20BITS
29828. DAC_WL_24BITS
29829. DAC_WL_32BITS
29830. DAC_WL_MASK
29831. DAC_WORD
29832. DAC_WRITE_POLARITY_BIT
29833. DAC_W_INDEX
29834. DAC_W_INDEX__DAC_W_INDEX_MASK
29835. DAC_W_INDEX__DAC_W_INDEX__SHIFT
29836. DAC_XGENIOCTRL
29837. DAC_XGENIODATA
29838. DACx_AUTODETECT_ACK
29839. DACx_AUTODETECT_CHECK_MASK
29840. DACx_AUTODETECT_FRAME_TIME_COUNTER
29841. DACx_AUTODETECT_INT_ENABLE
29842. DACx_AUTODETECT_MODE
29843. DACx_AUTODETECT_MODE_CONNECT
29844. DACx_AUTODETECT_MODE_DISCONNECT
29845. DACx_AUTODETECT_MODE_NONE
29846. DAD
29847. DADDI_SCRATCH
29848. DADDI_WAR
29849. DADR0
29850. DADR1
29851. DAD_ABORT
29852. DAD_BEGIN
29853. DAD_PROCESS
29854. DAE
29855. DAEMON
29856. DAFB_BASE
29857. DAFO
29858. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
29859. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
29860. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
29861. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
29862. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
29863. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
29864. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
29865. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
29866. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
29867. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
29868. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
29869. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
29870. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
29871. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
29872. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
29873. DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
29874. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
29875. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
29876. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
29877. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
29878. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
29879. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
29880. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
29881. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
29882. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
29883. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
29884. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
29885. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
29886. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
29887. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
29888. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
29889. DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
29890. DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
29891. DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
29892. DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
29893. DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
29894. DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
29895. DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
29896. DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
29897. DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
29898. DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
29899. DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
29900. DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
29901. DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
29902. DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
29903. DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
29904. DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
29905. DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
29906. DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK
29907. DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT
29908. DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
29909. DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
29910. DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK
29911. DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
29912. DAGB0_CNTL_MISC2__SWAP_CTL_MASK
29913. DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT
29914. DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK
29915. DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
29916. DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK
29917. DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
29918. DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK
29919. DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT
29920. DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
29921. DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
29922. DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK
29923. DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT
29924. DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK
29925. DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT
29926. DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK
29927. DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT
29928. DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK
29929. DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT
29930. DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK
29931. DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT
29932. DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK
29933. DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT
29934. DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK
29935. DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT
29936. DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK
29937. DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT
29938. DAGB0_DAGB_DLY__CLI_MASK
29939. DAGB0_DAGB_DLY__CLI__SHIFT
29940. DAGB0_DAGB_DLY__DLY_MASK
29941. DAGB0_DAGB_DLY__DLY__SHIFT
29942. DAGB0_DAGB_DLY__POS_MASK
29943. DAGB0_DAGB_DLY__POS__SHIFT
29944. DAGB0_FIFO_EMPTY__EMPTY_MASK
29945. DAGB0_FIFO_EMPTY__EMPTY__SHIFT
29946. DAGB0_FIFO_FULL__FULL_MASK
29947. DAGB0_FIFO_FULL__FULL__SHIFT
29948. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
29949. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
29950. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
29951. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
29952. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
29953. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
29954. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
29955. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
29956. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
29957. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
29958. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
29959. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
29960. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
29961. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
29962. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
29963. DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
29964. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
29965. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
29966. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
29967. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
29968. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
29969. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
29970. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
29971. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
29972. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
29973. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
29974. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
29975. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
29976. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
29977. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
29978. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
29979. DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
29980. DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK
29981. DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT
29982. DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK
29983. DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT
29984. DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK
29985. DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
29986. DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
29987. DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
29988. DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK
29989. DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
29990. DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK
29991. DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT
29992. DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK
29993. DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT
29994. DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK
29995. DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
29996. DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
29997. DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
29998. DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK
29999. DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
30000. DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK
30001. DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT
30002. DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK
30003. DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT
30004. DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK
30005. DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
30006. DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
30007. DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
30008. DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK
30009. DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
30010. DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK
30011. DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
30012. DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK
30013. DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT
30014. DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK
30015. DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT
30016. DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
30017. DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
30018. DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
30019. DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
30020. DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
30021. DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
30022. DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
30023. DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
30024. DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
30025. DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
30026. DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
30027. DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
30028. DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK
30029. DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT
30030. DAGB0_RDCLI0__MAX_BW_ENABLE_MASK
30031. DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT
30032. DAGB0_RDCLI0__MAX_BW_MASK
30033. DAGB0_RDCLI0__MAX_BW__SHIFT
30034. DAGB0_RDCLI0__MAX_OSD_MASK
30035. DAGB0_RDCLI0__MAX_OSD__SHIFT
30036. DAGB0_RDCLI0__MIN_BW_ENABLE_MASK
30037. DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT
30038. DAGB0_RDCLI0__MIN_BW_MASK
30039. DAGB0_RDCLI0__MIN_BW__SHIFT
30040. DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK
30041. DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
30042. DAGB0_RDCLI0__URG_HIGH_MASK
30043. DAGB0_RDCLI0__URG_HIGH__SHIFT
30044. DAGB0_RDCLI0__URG_LOW_MASK
30045. DAGB0_RDCLI0__URG_LOW__SHIFT
30046. DAGB0_RDCLI0__VIRT_CHAN_MASK
30047. DAGB0_RDCLI0__VIRT_CHAN__SHIFT
30048. DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK
30049. DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT
30050. DAGB0_RDCLI10__MAX_BW_ENABLE_MASK
30051. DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT
30052. DAGB0_RDCLI10__MAX_BW_MASK
30053. DAGB0_RDCLI10__MAX_BW__SHIFT
30054. DAGB0_RDCLI10__MAX_OSD_MASK
30055. DAGB0_RDCLI10__MAX_OSD__SHIFT
30056. DAGB0_RDCLI10__MIN_BW_ENABLE_MASK
30057. DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT
30058. DAGB0_RDCLI10__MIN_BW_MASK
30059. DAGB0_RDCLI10__MIN_BW__SHIFT
30060. DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK
30061. DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
30062. DAGB0_RDCLI10__URG_HIGH_MASK
30063. DAGB0_RDCLI10__URG_HIGH__SHIFT
30064. DAGB0_RDCLI10__URG_LOW_MASK
30065. DAGB0_RDCLI10__URG_LOW__SHIFT
30066. DAGB0_RDCLI10__VIRT_CHAN_MASK
30067. DAGB0_RDCLI10__VIRT_CHAN__SHIFT
30068. DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK
30069. DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT
30070. DAGB0_RDCLI11__MAX_BW_ENABLE_MASK
30071. DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT
30072. DAGB0_RDCLI11__MAX_BW_MASK
30073. DAGB0_RDCLI11__MAX_BW__SHIFT
30074. DAGB0_RDCLI11__MAX_OSD_MASK
30075. DAGB0_RDCLI11__MAX_OSD__SHIFT
30076. DAGB0_RDCLI11__MIN_BW_ENABLE_MASK
30077. DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT
30078. DAGB0_RDCLI11__MIN_BW_MASK
30079. DAGB0_RDCLI11__MIN_BW__SHIFT
30080. DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK
30081. DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
30082. DAGB0_RDCLI11__URG_HIGH_MASK
30083. DAGB0_RDCLI11__URG_HIGH__SHIFT
30084. DAGB0_RDCLI11__URG_LOW_MASK
30085. DAGB0_RDCLI11__URG_LOW__SHIFT
30086. DAGB0_RDCLI11__VIRT_CHAN_MASK
30087. DAGB0_RDCLI11__VIRT_CHAN__SHIFT
30088. DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK
30089. DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT
30090. DAGB0_RDCLI12__MAX_BW_ENABLE_MASK
30091. DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT
30092. DAGB0_RDCLI12__MAX_BW_MASK
30093. DAGB0_RDCLI12__MAX_BW__SHIFT
30094. DAGB0_RDCLI12__MAX_OSD_MASK
30095. DAGB0_RDCLI12__MAX_OSD__SHIFT
30096. DAGB0_RDCLI12__MIN_BW_ENABLE_MASK
30097. DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT
30098. DAGB0_RDCLI12__MIN_BW_MASK
30099. DAGB0_RDCLI12__MIN_BW__SHIFT
30100. DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK
30101. DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
30102. DAGB0_RDCLI12__URG_HIGH_MASK
30103. DAGB0_RDCLI12__URG_HIGH__SHIFT
30104. DAGB0_RDCLI12__URG_LOW_MASK
30105. DAGB0_RDCLI12__URG_LOW__SHIFT
30106. DAGB0_RDCLI12__VIRT_CHAN_MASK
30107. DAGB0_RDCLI12__VIRT_CHAN__SHIFT
30108. DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK
30109. DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT
30110. DAGB0_RDCLI13__MAX_BW_ENABLE_MASK
30111. DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT
30112. DAGB0_RDCLI13__MAX_BW_MASK
30113. DAGB0_RDCLI13__MAX_BW__SHIFT
30114. DAGB0_RDCLI13__MAX_OSD_MASK
30115. DAGB0_RDCLI13__MAX_OSD__SHIFT
30116. DAGB0_RDCLI13__MIN_BW_ENABLE_MASK
30117. DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT
30118. DAGB0_RDCLI13__MIN_BW_MASK
30119. DAGB0_RDCLI13__MIN_BW__SHIFT
30120. DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK
30121. DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
30122. DAGB0_RDCLI13__URG_HIGH_MASK
30123. DAGB0_RDCLI13__URG_HIGH__SHIFT
30124. DAGB0_RDCLI13__URG_LOW_MASK
30125. DAGB0_RDCLI13__URG_LOW__SHIFT
30126. DAGB0_RDCLI13__VIRT_CHAN_MASK
30127. DAGB0_RDCLI13__VIRT_CHAN__SHIFT
30128. DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK
30129. DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT
30130. DAGB0_RDCLI14__MAX_BW_ENABLE_MASK
30131. DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT
30132. DAGB0_RDCLI14__MAX_BW_MASK
30133. DAGB0_RDCLI14__MAX_BW__SHIFT
30134. DAGB0_RDCLI14__MAX_OSD_MASK
30135. DAGB0_RDCLI14__MAX_OSD__SHIFT
30136. DAGB0_RDCLI14__MIN_BW_ENABLE_MASK
30137. DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT
30138. DAGB0_RDCLI14__MIN_BW_MASK
30139. DAGB0_RDCLI14__MIN_BW__SHIFT
30140. DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK
30141. DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
30142. DAGB0_RDCLI14__URG_HIGH_MASK
30143. DAGB0_RDCLI14__URG_HIGH__SHIFT
30144. DAGB0_RDCLI14__URG_LOW_MASK
30145. DAGB0_RDCLI14__URG_LOW__SHIFT
30146. DAGB0_RDCLI14__VIRT_CHAN_MASK
30147. DAGB0_RDCLI14__VIRT_CHAN__SHIFT
30148. DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK
30149. DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT
30150. DAGB0_RDCLI15__MAX_BW_ENABLE_MASK
30151. DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT
30152. DAGB0_RDCLI15__MAX_BW_MASK
30153. DAGB0_RDCLI15__MAX_BW__SHIFT
30154. DAGB0_RDCLI15__MAX_OSD_MASK
30155. DAGB0_RDCLI15__MAX_OSD__SHIFT
30156. DAGB0_RDCLI15__MIN_BW_ENABLE_MASK
30157. DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT
30158. DAGB0_RDCLI15__MIN_BW_MASK
30159. DAGB0_RDCLI15__MIN_BW__SHIFT
30160. DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK
30161. DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
30162. DAGB0_RDCLI15__URG_HIGH_MASK
30163. DAGB0_RDCLI15__URG_HIGH__SHIFT
30164. DAGB0_RDCLI15__URG_LOW_MASK
30165. DAGB0_RDCLI15__URG_LOW__SHIFT
30166. DAGB0_RDCLI15__VIRT_CHAN_MASK
30167. DAGB0_RDCLI15__VIRT_CHAN__SHIFT
30168. DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK
30169. DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT
30170. DAGB0_RDCLI16__MAX_BW_ENABLE_MASK
30171. DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT
30172. DAGB0_RDCLI16__MAX_BW_MASK
30173. DAGB0_RDCLI16__MAX_BW__SHIFT
30174. DAGB0_RDCLI16__MAX_OSD_MASK
30175. DAGB0_RDCLI16__MAX_OSD__SHIFT
30176. DAGB0_RDCLI16__MIN_BW_ENABLE_MASK
30177. DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT
30178. DAGB0_RDCLI16__MIN_BW_MASK
30179. DAGB0_RDCLI16__MIN_BW__SHIFT
30180. DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK
30181. DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT
30182. DAGB0_RDCLI16__URG_HIGH_MASK
30183. DAGB0_RDCLI16__URG_HIGH__SHIFT
30184. DAGB0_RDCLI16__URG_LOW_MASK
30185. DAGB0_RDCLI16__URG_LOW__SHIFT
30186. DAGB0_RDCLI16__VIRT_CHAN_MASK
30187. DAGB0_RDCLI16__VIRT_CHAN__SHIFT
30188. DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK
30189. DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT
30190. DAGB0_RDCLI17__MAX_BW_ENABLE_MASK
30191. DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT
30192. DAGB0_RDCLI17__MAX_BW_MASK
30193. DAGB0_RDCLI17__MAX_BW__SHIFT
30194. DAGB0_RDCLI17__MAX_OSD_MASK
30195. DAGB0_RDCLI17__MAX_OSD__SHIFT
30196. DAGB0_RDCLI17__MIN_BW_ENABLE_MASK
30197. DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT
30198. DAGB0_RDCLI17__MIN_BW_MASK
30199. DAGB0_RDCLI17__MIN_BW__SHIFT
30200. DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK
30201. DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT
30202. DAGB0_RDCLI17__URG_HIGH_MASK
30203. DAGB0_RDCLI17__URG_HIGH__SHIFT
30204. DAGB0_RDCLI17__URG_LOW_MASK
30205. DAGB0_RDCLI17__URG_LOW__SHIFT
30206. DAGB0_RDCLI17__VIRT_CHAN_MASK
30207. DAGB0_RDCLI17__VIRT_CHAN__SHIFT
30208. DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK
30209. DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT
30210. DAGB0_RDCLI18__MAX_BW_ENABLE_MASK
30211. DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT
30212. DAGB0_RDCLI18__MAX_BW_MASK
30213. DAGB0_RDCLI18__MAX_BW__SHIFT
30214. DAGB0_RDCLI18__MAX_OSD_MASK
30215. DAGB0_RDCLI18__MAX_OSD__SHIFT
30216. DAGB0_RDCLI18__MIN_BW_ENABLE_MASK
30217. DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT
30218. DAGB0_RDCLI18__MIN_BW_MASK
30219. DAGB0_RDCLI18__MIN_BW__SHIFT
30220. DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK
30221. DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT
30222. DAGB0_RDCLI18__URG_HIGH_MASK
30223. DAGB0_RDCLI18__URG_HIGH__SHIFT
30224. DAGB0_RDCLI18__URG_LOW_MASK
30225. DAGB0_RDCLI18__URG_LOW__SHIFT
30226. DAGB0_RDCLI18__VIRT_CHAN_MASK
30227. DAGB0_RDCLI18__VIRT_CHAN__SHIFT
30228. DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK
30229. DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT
30230. DAGB0_RDCLI19__MAX_BW_ENABLE_MASK
30231. DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT
30232. DAGB0_RDCLI19__MAX_BW_MASK
30233. DAGB0_RDCLI19__MAX_BW__SHIFT
30234. DAGB0_RDCLI19__MAX_OSD_MASK
30235. DAGB0_RDCLI19__MAX_OSD__SHIFT
30236. DAGB0_RDCLI19__MIN_BW_ENABLE_MASK
30237. DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT
30238. DAGB0_RDCLI19__MIN_BW_MASK
30239. DAGB0_RDCLI19__MIN_BW__SHIFT
30240. DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK
30241. DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT
30242. DAGB0_RDCLI19__URG_HIGH_MASK
30243. DAGB0_RDCLI19__URG_HIGH__SHIFT
30244. DAGB0_RDCLI19__URG_LOW_MASK
30245. DAGB0_RDCLI19__URG_LOW__SHIFT
30246. DAGB0_RDCLI19__VIRT_CHAN_MASK
30247. DAGB0_RDCLI19__VIRT_CHAN__SHIFT
30248. DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK
30249. DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT
30250. DAGB0_RDCLI1__MAX_BW_ENABLE_MASK
30251. DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT
30252. DAGB0_RDCLI1__MAX_BW_MASK
30253. DAGB0_RDCLI1__MAX_BW__SHIFT
30254. DAGB0_RDCLI1__MAX_OSD_MASK
30255. DAGB0_RDCLI1__MAX_OSD__SHIFT
30256. DAGB0_RDCLI1__MIN_BW_ENABLE_MASK
30257. DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT
30258. DAGB0_RDCLI1__MIN_BW_MASK
30259. DAGB0_RDCLI1__MIN_BW__SHIFT
30260. DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK
30261. DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
30262. DAGB0_RDCLI1__URG_HIGH_MASK
30263. DAGB0_RDCLI1__URG_HIGH__SHIFT
30264. DAGB0_RDCLI1__URG_LOW_MASK
30265. DAGB0_RDCLI1__URG_LOW__SHIFT
30266. DAGB0_RDCLI1__VIRT_CHAN_MASK
30267. DAGB0_RDCLI1__VIRT_CHAN__SHIFT
30268. DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK
30269. DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT
30270. DAGB0_RDCLI20__MAX_BW_ENABLE_MASK
30271. DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT
30272. DAGB0_RDCLI20__MAX_BW_MASK
30273. DAGB0_RDCLI20__MAX_BW__SHIFT
30274. DAGB0_RDCLI20__MAX_OSD_MASK
30275. DAGB0_RDCLI20__MAX_OSD__SHIFT
30276. DAGB0_RDCLI20__MIN_BW_ENABLE_MASK
30277. DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT
30278. DAGB0_RDCLI20__MIN_BW_MASK
30279. DAGB0_RDCLI20__MIN_BW__SHIFT
30280. DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK
30281. DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT
30282. DAGB0_RDCLI20__URG_HIGH_MASK
30283. DAGB0_RDCLI20__URG_HIGH__SHIFT
30284. DAGB0_RDCLI20__URG_LOW_MASK
30285. DAGB0_RDCLI20__URG_LOW__SHIFT
30286. DAGB0_RDCLI20__VIRT_CHAN_MASK
30287. DAGB0_RDCLI20__VIRT_CHAN__SHIFT
30288. DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK
30289. DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT
30290. DAGB0_RDCLI21__MAX_BW_ENABLE_MASK
30291. DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT
30292. DAGB0_RDCLI21__MAX_BW_MASK
30293. DAGB0_RDCLI21__MAX_BW__SHIFT
30294. DAGB0_RDCLI21__MAX_OSD_MASK
30295. DAGB0_RDCLI21__MAX_OSD__SHIFT
30296. DAGB0_RDCLI21__MIN_BW_ENABLE_MASK
30297. DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT
30298. DAGB0_RDCLI21__MIN_BW_MASK
30299. DAGB0_RDCLI21__MIN_BW__SHIFT
30300. DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK
30301. DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT
30302. DAGB0_RDCLI21__URG_HIGH_MASK
30303. DAGB0_RDCLI21__URG_HIGH__SHIFT
30304. DAGB0_RDCLI21__URG_LOW_MASK
30305. DAGB0_RDCLI21__URG_LOW__SHIFT
30306. DAGB0_RDCLI21__VIRT_CHAN_MASK
30307. DAGB0_RDCLI21__VIRT_CHAN__SHIFT
30308. DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK
30309. DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT
30310. DAGB0_RDCLI22__MAX_BW_ENABLE_MASK
30311. DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT
30312. DAGB0_RDCLI22__MAX_BW_MASK
30313. DAGB0_RDCLI22__MAX_BW__SHIFT
30314. DAGB0_RDCLI22__MAX_OSD_MASK
30315. DAGB0_RDCLI22__MAX_OSD__SHIFT
30316. DAGB0_RDCLI22__MIN_BW_ENABLE_MASK
30317. DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT
30318. DAGB0_RDCLI22__MIN_BW_MASK
30319. DAGB0_RDCLI22__MIN_BW__SHIFT
30320. DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK
30321. DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT
30322. DAGB0_RDCLI22__URG_HIGH_MASK
30323. DAGB0_RDCLI22__URG_HIGH__SHIFT
30324. DAGB0_RDCLI22__URG_LOW_MASK
30325. DAGB0_RDCLI22__URG_LOW__SHIFT
30326. DAGB0_RDCLI22__VIRT_CHAN_MASK
30327. DAGB0_RDCLI22__VIRT_CHAN__SHIFT
30328. DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK
30329. DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT
30330. DAGB0_RDCLI23__MAX_BW_ENABLE_MASK
30331. DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT
30332. DAGB0_RDCLI23__MAX_BW_MASK
30333. DAGB0_RDCLI23__MAX_BW__SHIFT
30334. DAGB0_RDCLI23__MAX_OSD_MASK
30335. DAGB0_RDCLI23__MAX_OSD__SHIFT
30336. DAGB0_RDCLI23__MIN_BW_ENABLE_MASK
30337. DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT
30338. DAGB0_RDCLI23__MIN_BW_MASK
30339. DAGB0_RDCLI23__MIN_BW__SHIFT
30340. DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK
30341. DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT
30342. DAGB0_RDCLI23__URG_HIGH_MASK
30343. DAGB0_RDCLI23__URG_HIGH__SHIFT
30344. DAGB0_RDCLI23__URG_LOW_MASK
30345. DAGB0_RDCLI23__URG_LOW__SHIFT
30346. DAGB0_RDCLI23__VIRT_CHAN_MASK
30347. DAGB0_RDCLI23__VIRT_CHAN__SHIFT
30348. DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK
30349. DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT
30350. DAGB0_RDCLI24__MAX_BW_ENABLE_MASK
30351. DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT
30352. DAGB0_RDCLI24__MAX_BW_MASK
30353. DAGB0_RDCLI24__MAX_BW__SHIFT
30354. DAGB0_RDCLI24__MAX_OSD_MASK
30355. DAGB0_RDCLI24__MAX_OSD__SHIFT
30356. DAGB0_RDCLI24__MIN_BW_ENABLE_MASK
30357. DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT
30358. DAGB0_RDCLI24__MIN_BW_MASK
30359. DAGB0_RDCLI24__MIN_BW__SHIFT
30360. DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK
30361. DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT
30362. DAGB0_RDCLI24__URG_HIGH_MASK
30363. DAGB0_RDCLI24__URG_HIGH__SHIFT
30364. DAGB0_RDCLI24__URG_LOW_MASK
30365. DAGB0_RDCLI24__URG_LOW__SHIFT
30366. DAGB0_RDCLI24__VIRT_CHAN_MASK
30367. DAGB0_RDCLI24__VIRT_CHAN__SHIFT
30368. DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK
30369. DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT
30370. DAGB0_RDCLI25__MAX_BW_ENABLE_MASK
30371. DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT
30372. DAGB0_RDCLI25__MAX_BW_MASK
30373. DAGB0_RDCLI25__MAX_BW__SHIFT
30374. DAGB0_RDCLI25__MAX_OSD_MASK
30375. DAGB0_RDCLI25__MAX_OSD__SHIFT
30376. DAGB0_RDCLI25__MIN_BW_ENABLE_MASK
30377. DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT
30378. DAGB0_RDCLI25__MIN_BW_MASK
30379. DAGB0_RDCLI25__MIN_BW__SHIFT
30380. DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK
30381. DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT
30382. DAGB0_RDCLI25__URG_HIGH_MASK
30383. DAGB0_RDCLI25__URG_HIGH__SHIFT
30384. DAGB0_RDCLI25__URG_LOW_MASK
30385. DAGB0_RDCLI25__URG_LOW__SHIFT
30386. DAGB0_RDCLI25__VIRT_CHAN_MASK
30387. DAGB0_RDCLI25__VIRT_CHAN__SHIFT
30388. DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK
30389. DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT
30390. DAGB0_RDCLI26__MAX_BW_ENABLE_MASK
30391. DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT
30392. DAGB0_RDCLI26__MAX_BW_MASK
30393. DAGB0_RDCLI26__MAX_BW__SHIFT
30394. DAGB0_RDCLI26__MAX_OSD_MASK
30395. DAGB0_RDCLI26__MAX_OSD__SHIFT
30396. DAGB0_RDCLI26__MIN_BW_ENABLE_MASK
30397. DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT
30398. DAGB0_RDCLI26__MIN_BW_MASK
30399. DAGB0_RDCLI26__MIN_BW__SHIFT
30400. DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK
30401. DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT
30402. DAGB0_RDCLI26__URG_HIGH_MASK
30403. DAGB0_RDCLI26__URG_HIGH__SHIFT
30404. DAGB0_RDCLI26__URG_LOW_MASK
30405. DAGB0_RDCLI26__URG_LOW__SHIFT
30406. DAGB0_RDCLI26__VIRT_CHAN_MASK
30407. DAGB0_RDCLI26__VIRT_CHAN__SHIFT
30408. DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK
30409. DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT
30410. DAGB0_RDCLI27__MAX_BW_ENABLE_MASK
30411. DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT
30412. DAGB0_RDCLI27__MAX_BW_MASK
30413. DAGB0_RDCLI27__MAX_BW__SHIFT
30414. DAGB0_RDCLI27__MAX_OSD_MASK
30415. DAGB0_RDCLI27__MAX_OSD__SHIFT
30416. DAGB0_RDCLI27__MIN_BW_ENABLE_MASK
30417. DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT
30418. DAGB0_RDCLI27__MIN_BW_MASK
30419. DAGB0_RDCLI27__MIN_BW__SHIFT
30420. DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK
30421. DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT
30422. DAGB0_RDCLI27__URG_HIGH_MASK
30423. DAGB0_RDCLI27__URG_HIGH__SHIFT
30424. DAGB0_RDCLI27__URG_LOW_MASK
30425. DAGB0_RDCLI27__URG_LOW__SHIFT
30426. DAGB0_RDCLI27__VIRT_CHAN_MASK
30427. DAGB0_RDCLI27__VIRT_CHAN__SHIFT
30428. DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK
30429. DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT
30430. DAGB0_RDCLI28__MAX_BW_ENABLE_MASK
30431. DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT
30432. DAGB0_RDCLI28__MAX_BW_MASK
30433. DAGB0_RDCLI28__MAX_BW__SHIFT
30434. DAGB0_RDCLI28__MAX_OSD_MASK
30435. DAGB0_RDCLI28__MAX_OSD__SHIFT
30436. DAGB0_RDCLI28__MIN_BW_ENABLE_MASK
30437. DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT
30438. DAGB0_RDCLI28__MIN_BW_MASK
30439. DAGB0_RDCLI28__MIN_BW__SHIFT
30440. DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK
30441. DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT
30442. DAGB0_RDCLI28__URG_HIGH_MASK
30443. DAGB0_RDCLI28__URG_HIGH__SHIFT
30444. DAGB0_RDCLI28__URG_LOW_MASK
30445. DAGB0_RDCLI28__URG_LOW__SHIFT
30446. DAGB0_RDCLI28__VIRT_CHAN_MASK
30447. DAGB0_RDCLI28__VIRT_CHAN__SHIFT
30448. DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK
30449. DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT
30450. DAGB0_RDCLI29__MAX_BW_ENABLE_MASK
30451. DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT
30452. DAGB0_RDCLI29__MAX_BW_MASK
30453. DAGB0_RDCLI29__MAX_BW__SHIFT
30454. DAGB0_RDCLI29__MAX_OSD_MASK
30455. DAGB0_RDCLI29__MAX_OSD__SHIFT
30456. DAGB0_RDCLI29__MIN_BW_ENABLE_MASK
30457. DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT
30458. DAGB0_RDCLI29__MIN_BW_MASK
30459. DAGB0_RDCLI29__MIN_BW__SHIFT
30460. DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK
30461. DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT
30462. DAGB0_RDCLI29__URG_HIGH_MASK
30463. DAGB0_RDCLI29__URG_HIGH__SHIFT
30464. DAGB0_RDCLI29__URG_LOW_MASK
30465. DAGB0_RDCLI29__URG_LOW__SHIFT
30466. DAGB0_RDCLI29__VIRT_CHAN_MASK
30467. DAGB0_RDCLI29__VIRT_CHAN__SHIFT
30468. DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK
30469. DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT
30470. DAGB0_RDCLI2__MAX_BW_ENABLE_MASK
30471. DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT
30472. DAGB0_RDCLI2__MAX_BW_MASK
30473. DAGB0_RDCLI2__MAX_BW__SHIFT
30474. DAGB0_RDCLI2__MAX_OSD_MASK
30475. DAGB0_RDCLI2__MAX_OSD__SHIFT
30476. DAGB0_RDCLI2__MIN_BW_ENABLE_MASK
30477. DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT
30478. DAGB0_RDCLI2__MIN_BW_MASK
30479. DAGB0_RDCLI2__MIN_BW__SHIFT
30480. DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK
30481. DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
30482. DAGB0_RDCLI2__URG_HIGH_MASK
30483. DAGB0_RDCLI2__URG_HIGH__SHIFT
30484. DAGB0_RDCLI2__URG_LOW_MASK
30485. DAGB0_RDCLI2__URG_LOW__SHIFT
30486. DAGB0_RDCLI2__VIRT_CHAN_MASK
30487. DAGB0_RDCLI2__VIRT_CHAN__SHIFT
30488. DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK
30489. DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT
30490. DAGB0_RDCLI30__MAX_BW_ENABLE_MASK
30491. DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT
30492. DAGB0_RDCLI30__MAX_BW_MASK
30493. DAGB0_RDCLI30__MAX_BW__SHIFT
30494. DAGB0_RDCLI30__MAX_OSD_MASK
30495. DAGB0_RDCLI30__MAX_OSD__SHIFT
30496. DAGB0_RDCLI30__MIN_BW_ENABLE_MASK
30497. DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT
30498. DAGB0_RDCLI30__MIN_BW_MASK
30499. DAGB0_RDCLI30__MIN_BW__SHIFT
30500. DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK
30501. DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT
30502. DAGB0_RDCLI30__URG_HIGH_MASK
30503. DAGB0_RDCLI30__URG_HIGH__SHIFT
30504. DAGB0_RDCLI30__URG_LOW_MASK
30505. DAGB0_RDCLI30__URG_LOW__SHIFT
30506. DAGB0_RDCLI30__VIRT_CHAN_MASK
30507. DAGB0_RDCLI30__VIRT_CHAN__SHIFT
30508. DAGB0_RDCLI31__CHECK_TLB_CREDIT_MASK
30509. DAGB0_RDCLI31__CHECK_TLB_CREDIT__SHIFT
30510. DAGB0_RDCLI31__MAX_BW_ENABLE_MASK
30511. DAGB0_RDCLI31__MAX_BW_ENABLE__SHIFT
30512. DAGB0_RDCLI31__MAX_BW_MASK
30513. DAGB0_RDCLI31__MAX_BW__SHIFT
30514. DAGB0_RDCLI31__MAX_OSD_MASK
30515. DAGB0_RDCLI31__MAX_OSD__SHIFT
30516. DAGB0_RDCLI31__MIN_BW_ENABLE_MASK
30517. DAGB0_RDCLI31__MIN_BW_ENABLE__SHIFT
30518. DAGB0_RDCLI31__MIN_BW_MASK
30519. DAGB0_RDCLI31__MIN_BW__SHIFT
30520. DAGB0_RDCLI31__OSD_LIMITER_ENABLE_MASK
30521. DAGB0_RDCLI31__OSD_LIMITER_ENABLE__SHIFT
30522. DAGB0_RDCLI31__URG_HIGH_MASK
30523. DAGB0_RDCLI31__URG_HIGH__SHIFT
30524. DAGB0_RDCLI31__URG_LOW_MASK
30525. DAGB0_RDCLI31__URG_LOW__SHIFT
30526. DAGB0_RDCLI31__VIRT_CHAN_MASK
30527. DAGB0_RDCLI31__VIRT_CHAN__SHIFT
30528. DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK
30529. DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT
30530. DAGB0_RDCLI3__MAX_BW_ENABLE_MASK
30531. DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT
30532. DAGB0_RDCLI3__MAX_BW_MASK
30533. DAGB0_RDCLI3__MAX_BW__SHIFT
30534. DAGB0_RDCLI3__MAX_OSD_MASK
30535. DAGB0_RDCLI3__MAX_OSD__SHIFT
30536. DAGB0_RDCLI3__MIN_BW_ENABLE_MASK
30537. DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT
30538. DAGB0_RDCLI3__MIN_BW_MASK
30539. DAGB0_RDCLI3__MIN_BW__SHIFT
30540. DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK
30541. DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
30542. DAGB0_RDCLI3__URG_HIGH_MASK
30543. DAGB0_RDCLI3__URG_HIGH__SHIFT
30544. DAGB0_RDCLI3__URG_LOW_MASK
30545. DAGB0_RDCLI3__URG_LOW__SHIFT
30546. DAGB0_RDCLI3__VIRT_CHAN_MASK
30547. DAGB0_RDCLI3__VIRT_CHAN__SHIFT
30548. DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK
30549. DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT
30550. DAGB0_RDCLI4__MAX_BW_ENABLE_MASK
30551. DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT
30552. DAGB0_RDCLI4__MAX_BW_MASK
30553. DAGB0_RDCLI4__MAX_BW__SHIFT
30554. DAGB0_RDCLI4__MAX_OSD_MASK
30555. DAGB0_RDCLI4__MAX_OSD__SHIFT
30556. DAGB0_RDCLI4__MIN_BW_ENABLE_MASK
30557. DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT
30558. DAGB0_RDCLI4__MIN_BW_MASK
30559. DAGB0_RDCLI4__MIN_BW__SHIFT
30560. DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK
30561. DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
30562. DAGB0_RDCLI4__URG_HIGH_MASK
30563. DAGB0_RDCLI4__URG_HIGH__SHIFT
30564. DAGB0_RDCLI4__URG_LOW_MASK
30565. DAGB0_RDCLI4__URG_LOW__SHIFT
30566. DAGB0_RDCLI4__VIRT_CHAN_MASK
30567. DAGB0_RDCLI4__VIRT_CHAN__SHIFT
30568. DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK
30569. DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT
30570. DAGB0_RDCLI5__MAX_BW_ENABLE_MASK
30571. DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT
30572. DAGB0_RDCLI5__MAX_BW_MASK
30573. DAGB0_RDCLI5__MAX_BW__SHIFT
30574. DAGB0_RDCLI5__MAX_OSD_MASK
30575. DAGB0_RDCLI5__MAX_OSD__SHIFT
30576. DAGB0_RDCLI5__MIN_BW_ENABLE_MASK
30577. DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT
30578. DAGB0_RDCLI5__MIN_BW_MASK
30579. DAGB0_RDCLI5__MIN_BW__SHIFT
30580. DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK
30581. DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
30582. DAGB0_RDCLI5__URG_HIGH_MASK
30583. DAGB0_RDCLI5__URG_HIGH__SHIFT
30584. DAGB0_RDCLI5__URG_LOW_MASK
30585. DAGB0_RDCLI5__URG_LOW__SHIFT
30586. DAGB0_RDCLI5__VIRT_CHAN_MASK
30587. DAGB0_RDCLI5__VIRT_CHAN__SHIFT
30588. DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK
30589. DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT
30590. DAGB0_RDCLI6__MAX_BW_ENABLE_MASK
30591. DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT
30592. DAGB0_RDCLI6__MAX_BW_MASK
30593. DAGB0_RDCLI6__MAX_BW__SHIFT
30594. DAGB0_RDCLI6__MAX_OSD_MASK
30595. DAGB0_RDCLI6__MAX_OSD__SHIFT
30596. DAGB0_RDCLI6__MIN_BW_ENABLE_MASK
30597. DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT
30598. DAGB0_RDCLI6__MIN_BW_MASK
30599. DAGB0_RDCLI6__MIN_BW__SHIFT
30600. DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK
30601. DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
30602. DAGB0_RDCLI6__URG_HIGH_MASK
30603. DAGB0_RDCLI6__URG_HIGH__SHIFT
30604. DAGB0_RDCLI6__URG_LOW_MASK
30605. DAGB0_RDCLI6__URG_LOW__SHIFT
30606. DAGB0_RDCLI6__VIRT_CHAN_MASK
30607. DAGB0_RDCLI6__VIRT_CHAN__SHIFT
30608. DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK
30609. DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT
30610. DAGB0_RDCLI7__MAX_BW_ENABLE_MASK
30611. DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT
30612. DAGB0_RDCLI7__MAX_BW_MASK
30613. DAGB0_RDCLI7__MAX_BW__SHIFT
30614. DAGB0_RDCLI7__MAX_OSD_MASK
30615. DAGB0_RDCLI7__MAX_OSD__SHIFT
30616. DAGB0_RDCLI7__MIN_BW_ENABLE_MASK
30617. DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT
30618. DAGB0_RDCLI7__MIN_BW_MASK
30619. DAGB0_RDCLI7__MIN_BW__SHIFT
30620. DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK
30621. DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
30622. DAGB0_RDCLI7__URG_HIGH_MASK
30623. DAGB0_RDCLI7__URG_HIGH__SHIFT
30624. DAGB0_RDCLI7__URG_LOW_MASK
30625. DAGB0_RDCLI7__URG_LOW__SHIFT
30626. DAGB0_RDCLI7__VIRT_CHAN_MASK
30627. DAGB0_RDCLI7__VIRT_CHAN__SHIFT
30628. DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK
30629. DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT
30630. DAGB0_RDCLI8__MAX_BW_ENABLE_MASK
30631. DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT
30632. DAGB0_RDCLI8__MAX_BW_MASK
30633. DAGB0_RDCLI8__MAX_BW__SHIFT
30634. DAGB0_RDCLI8__MAX_OSD_MASK
30635. DAGB0_RDCLI8__MAX_OSD__SHIFT
30636. DAGB0_RDCLI8__MIN_BW_ENABLE_MASK
30637. DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT
30638. DAGB0_RDCLI8__MIN_BW_MASK
30639. DAGB0_RDCLI8__MIN_BW__SHIFT
30640. DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK
30641. DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
30642. DAGB0_RDCLI8__URG_HIGH_MASK
30643. DAGB0_RDCLI8__URG_HIGH__SHIFT
30644. DAGB0_RDCLI8__URG_LOW_MASK
30645. DAGB0_RDCLI8__URG_LOW__SHIFT
30646. DAGB0_RDCLI8__VIRT_CHAN_MASK
30647. DAGB0_RDCLI8__VIRT_CHAN__SHIFT
30648. DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK
30649. DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT
30650. DAGB0_RDCLI9__MAX_BW_ENABLE_MASK
30651. DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT
30652. DAGB0_RDCLI9__MAX_BW_MASK
30653. DAGB0_RDCLI9__MAX_BW__SHIFT
30654. DAGB0_RDCLI9__MAX_OSD_MASK
30655. DAGB0_RDCLI9__MAX_OSD__SHIFT
30656. DAGB0_RDCLI9__MIN_BW_ENABLE_MASK
30657. DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT
30658. DAGB0_RDCLI9__MIN_BW_MASK
30659. DAGB0_RDCLI9__MIN_BW__SHIFT
30660. DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK
30661. DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
30662. DAGB0_RDCLI9__URG_HIGH_MASK
30663. DAGB0_RDCLI9__URG_HIGH__SHIFT
30664. DAGB0_RDCLI9__URG_LOW_MASK
30665. DAGB0_RDCLI9__URG_LOW__SHIFT
30666. DAGB0_RDCLI9__VIRT_CHAN_MASK
30667. DAGB0_RDCLI9__VIRT_CHAN__SHIFT
30668. DAGB0_RDCLI_ASK_PENDING__BUSY_MASK
30669. DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT
30670. DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK
30671. DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
30672. DAGB0_RDCLI_GO_PENDING__BUSY_MASK
30673. DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT
30674. DAGB0_RDCLI_OARB_PENDING__BUSY_MASK
30675. DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT
30676. DAGB0_RDCLI_OSD_PENDING__BUSY_MASK
30677. DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT
30678. DAGB0_RDCLI_TLB_PENDING__BUSY_MASK
30679. DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT
30680. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
30681. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
30682. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
30683. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
30684. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
30685. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
30686. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
30687. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
30688. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
30689. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
30690. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
30691. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
30692. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
30693. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
30694. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
30695. DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
30696. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
30697. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
30698. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
30699. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
30700. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
30701. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
30702. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
30703. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
30704. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
30705. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
30706. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
30707. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
30708. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
30709. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
30710. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
30711. DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
30712. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK
30713. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT
30714. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK
30715. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT
30716. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK
30717. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT
30718. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK
30719. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT
30720. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK
30721. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT
30722. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK
30723. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT
30724. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK
30725. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT
30726. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK
30727. DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT
30728. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK
30729. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT
30730. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK
30731. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT
30732. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK
30733. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT
30734. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK
30735. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT
30736. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK
30737. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT
30738. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK
30739. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT
30740. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK
30741. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT
30742. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK
30743. DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT
30744. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
30745. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
30746. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
30747. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
30748. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
30749. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
30750. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
30751. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
30752. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
30753. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
30754. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
30755. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
30756. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
30757. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
30758. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
30759. DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
30760. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
30761. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
30762. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
30763. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
30764. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
30765. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
30766. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
30767. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
30768. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
30769. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
30770. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
30771. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
30772. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
30773. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
30774. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
30775. DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
30776. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK
30777. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT
30778. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK
30779. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT
30780. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK
30781. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT
30782. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK
30783. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT
30784. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK
30785. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT
30786. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK
30787. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT
30788. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK
30789. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT
30790. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK
30791. DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT
30792. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK
30793. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT
30794. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK
30795. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT
30796. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK
30797. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT
30798. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK
30799. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT
30800. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK
30801. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT
30802. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK
30803. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT
30804. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK
30805. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT
30806. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK
30807. DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT
30808. DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK
30809. DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
30810. DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
30811. DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
30812. DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
30813. DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
30814. DAGB0_RD_ADDR_DAGB__WHOAMI_MASK
30815. DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT
30816. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
30817. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
30818. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
30819. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
30820. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
30821. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
30822. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
30823. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
30824. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
30825. DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
30826. DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
30827. DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
30828. DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
30829. DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
30830. DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
30831. DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
30832. DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
30833. DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
30834. DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
30835. DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
30836. DAGB0_RD_CNTL_MISC__HDP_CID_MASK
30837. DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT
30838. DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK
30839. DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
30840. DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
30841. DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
30842. DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
30843. DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
30844. DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
30845. DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
30846. DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK
30847. DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT
30848. DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
30849. DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
30850. DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
30851. DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
30852. DAGB0_RD_CNTL__IO_LEVEL_MASK
30853. DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
30854. DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
30855. DAGB0_RD_CNTL__IO_LEVEL__SHIFT
30856. DAGB0_RD_CNTL__SCLK_FREQ_MASK
30857. DAGB0_RD_CNTL__SCLK_FREQ__SHIFT
30858. DAGB0_RD_CNTL__SHARE_VC_NUM_MASK
30859. DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT
30860. DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK
30861. DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
30862. DAGB0_RD_CREDITS_FULL__FULL_MASK
30863. DAGB0_RD_CREDITS_FULL__FULL__SHIFT
30864. DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK
30865. DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT
30866. DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK
30867. DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT
30868. DAGB0_RD_GMI_CNTL__LEVEL_MASK
30869. DAGB0_RD_GMI_CNTL__LEVEL__SHIFT
30870. DAGB0_RD_GMI_CNTL__MAX_BURST_MASK
30871. DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT
30872. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
30873. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
30874. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
30875. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
30876. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
30877. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
30878. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
30879. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
30880. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
30881. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
30882. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
30883. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
30884. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
30885. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
30886. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
30887. DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
30888. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
30889. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
30890. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
30891. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
30892. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
30893. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
30894. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
30895. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
30896. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
30897. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
30898. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
30899. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
30900. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
30901. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
30902. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
30903. DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
30904. DAGB0_RD_TLB_CREDIT__TLB0_MASK
30905. DAGB0_RD_TLB_CREDIT__TLB0__SHIFT
30906. DAGB0_RD_TLB_CREDIT__TLB1_MASK
30907. DAGB0_RD_TLB_CREDIT__TLB1__SHIFT
30908. DAGB0_RD_TLB_CREDIT__TLB2_MASK
30909. DAGB0_RD_TLB_CREDIT__TLB2__SHIFT
30910. DAGB0_RD_TLB_CREDIT__TLB3_MASK
30911. DAGB0_RD_TLB_CREDIT__TLB3__SHIFT
30912. DAGB0_RD_TLB_CREDIT__TLB4_MASK
30913. DAGB0_RD_TLB_CREDIT__TLB4__SHIFT
30914. DAGB0_RD_TLB_CREDIT__TLB5_MASK
30915. DAGB0_RD_TLB_CREDIT__TLB5__SHIFT
30916. DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK
30917. DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT
30918. DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
30919. DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
30920. DAGB0_RD_VC0_CNTL__MAX_BW_MASK
30921. DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT
30922. DAGB0_RD_VC0_CNTL__MAX_OSD_MASK
30923. DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT
30924. DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
30925. DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
30926. DAGB0_RD_VC0_CNTL__MIN_BW_MASK
30927. DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT
30928. DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
30929. DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
30930. DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK
30931. DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT
30932. DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK
30933. DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT
30934. DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
30935. DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
30936. DAGB0_RD_VC1_CNTL__MAX_BW_MASK
30937. DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT
30938. DAGB0_RD_VC1_CNTL__MAX_OSD_MASK
30939. DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT
30940. DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
30941. DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
30942. DAGB0_RD_VC1_CNTL__MIN_BW_MASK
30943. DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT
30944. DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
30945. DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
30946. DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK
30947. DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT
30948. DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK
30949. DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT
30950. DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
30951. DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
30952. DAGB0_RD_VC2_CNTL__MAX_BW_MASK
30953. DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT
30954. DAGB0_RD_VC2_CNTL__MAX_OSD_MASK
30955. DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT
30956. DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
30957. DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
30958. DAGB0_RD_VC2_CNTL__MIN_BW_MASK
30959. DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT
30960. DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
30961. DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
30962. DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK
30963. DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT
30964. DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK
30965. DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT
30966. DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
30967. DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
30968. DAGB0_RD_VC3_CNTL__MAX_BW_MASK
30969. DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT
30970. DAGB0_RD_VC3_CNTL__MAX_OSD_MASK
30971. DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT
30972. DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
30973. DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
30974. DAGB0_RD_VC3_CNTL__MIN_BW_MASK
30975. DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT
30976. DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
30977. DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
30978. DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK
30979. DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT
30980. DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK
30981. DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT
30982. DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
30983. DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
30984. DAGB0_RD_VC4_CNTL__MAX_BW_MASK
30985. DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT
30986. DAGB0_RD_VC4_CNTL__MAX_OSD_MASK
30987. DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT
30988. DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
30989. DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
30990. DAGB0_RD_VC4_CNTL__MIN_BW_MASK
30991. DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT
30992. DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
30993. DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
30994. DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK
30995. DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT
30996. DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK
30997. DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT
30998. DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
30999. DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
31000. DAGB0_RD_VC5_CNTL__MAX_BW_MASK
31001. DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT
31002. DAGB0_RD_VC5_CNTL__MAX_OSD_MASK
31003. DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT
31004. DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
31005. DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
31006. DAGB0_RD_VC5_CNTL__MIN_BW_MASK
31007. DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT
31008. DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
31009. DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
31010. DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK
31011. DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT
31012. DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK
31013. DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT
31014. DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
31015. DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
31016. DAGB0_RD_VC6_CNTL__MAX_BW_MASK
31017. DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT
31018. DAGB0_RD_VC6_CNTL__MAX_OSD_MASK
31019. DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT
31020. DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
31021. DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
31022. DAGB0_RD_VC6_CNTL__MIN_BW_MASK
31023. DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT
31024. DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
31025. DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
31026. DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK
31027. DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT
31028. DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK
31029. DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT
31030. DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
31031. DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
31032. DAGB0_RD_VC7_CNTL__MAX_BW_MASK
31033. DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT
31034. DAGB0_RD_VC7_CNTL__MAX_OSD_MASK
31035. DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT
31036. DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
31037. DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
31038. DAGB0_RD_VC7_CNTL__MIN_BW_MASK
31039. DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT
31040. DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
31041. DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
31042. DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK
31043. DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT
31044. DAGB0_RESERVE0__RESERVE_MASK
31045. DAGB0_RESERVE0__RESERVE__SHIFT
31046. DAGB0_RESERVE100__RESERVE_MASK
31047. DAGB0_RESERVE100__RESERVE__SHIFT
31048. DAGB0_RESERVE101__RESERVE_MASK
31049. DAGB0_RESERVE101__RESERVE__SHIFT
31050. DAGB0_RESERVE102__RESERVE_MASK
31051. DAGB0_RESERVE102__RESERVE__SHIFT
31052. DAGB0_RESERVE103__RESERVE_MASK
31053. DAGB0_RESERVE103__RESERVE__SHIFT
31054. DAGB0_RESERVE104__RESERVE_MASK
31055. DAGB0_RESERVE104__RESERVE__SHIFT
31056. DAGB0_RESERVE105__RESERVE_MASK
31057. DAGB0_RESERVE105__RESERVE__SHIFT
31058. DAGB0_RESERVE106__RESERVE_MASK
31059. DAGB0_RESERVE106__RESERVE__SHIFT
31060. DAGB0_RESERVE107__RESERVE_MASK
31061. DAGB0_RESERVE107__RESERVE__SHIFT
31062. DAGB0_RESERVE108__RESERVE_MASK
31063. DAGB0_RESERVE108__RESERVE__SHIFT
31064. DAGB0_RESERVE109__RESERVE_MASK
31065. DAGB0_RESERVE109__RESERVE__SHIFT
31066. DAGB0_RESERVE10__RESERVE_MASK
31067. DAGB0_RESERVE10__RESERVE__SHIFT
31068. DAGB0_RESERVE110__RESERVE_MASK
31069. DAGB0_RESERVE110__RESERVE__SHIFT
31070. DAGB0_RESERVE111__RESERVE_MASK
31071. DAGB0_RESERVE111__RESERVE__SHIFT
31072. DAGB0_RESERVE112__RESERVE_MASK
31073. DAGB0_RESERVE112__RESERVE__SHIFT
31074. DAGB0_RESERVE113__RESERVE_MASK
31075. DAGB0_RESERVE113__RESERVE__SHIFT
31076. DAGB0_RESERVE114__RESERVE_MASK
31077. DAGB0_RESERVE114__RESERVE__SHIFT
31078. DAGB0_RESERVE115__RESERVE_MASK
31079. DAGB0_RESERVE115__RESERVE__SHIFT
31080. DAGB0_RESERVE116__RESERVE_MASK
31081. DAGB0_RESERVE116__RESERVE__SHIFT
31082. DAGB0_RESERVE117__RESERVE_MASK
31083. DAGB0_RESERVE117__RESERVE__SHIFT
31084. DAGB0_RESERVE118__RESERVE_MASK
31085. DAGB0_RESERVE118__RESERVE__SHIFT
31086. DAGB0_RESERVE119__RESERVE_MASK
31087. DAGB0_RESERVE119__RESERVE__SHIFT
31088. DAGB0_RESERVE11__RESERVE_MASK
31089. DAGB0_RESERVE11__RESERVE__SHIFT
31090. DAGB0_RESERVE120__RESERVE_MASK
31091. DAGB0_RESERVE120__RESERVE__SHIFT
31092. DAGB0_RESERVE121__RESERVE_MASK
31093. DAGB0_RESERVE121__RESERVE__SHIFT
31094. DAGB0_RESERVE122__RESERVE_MASK
31095. DAGB0_RESERVE122__RESERVE__SHIFT
31096. DAGB0_RESERVE123__RESERVE_MASK
31097. DAGB0_RESERVE123__RESERVE__SHIFT
31098. DAGB0_RESERVE124__RESERVE_MASK
31099. DAGB0_RESERVE124__RESERVE__SHIFT
31100. DAGB0_RESERVE125__RESERVE_MASK
31101. DAGB0_RESERVE125__RESERVE__SHIFT
31102. DAGB0_RESERVE126__RESERVE_MASK
31103. DAGB0_RESERVE126__RESERVE__SHIFT
31104. DAGB0_RESERVE127__RESERVE_MASK
31105. DAGB0_RESERVE127__RESERVE__SHIFT
31106. DAGB0_RESERVE128__RESERVE_MASK
31107. DAGB0_RESERVE128__RESERVE__SHIFT
31108. DAGB0_RESERVE129__RESERVE_MASK
31109. DAGB0_RESERVE129__RESERVE__SHIFT
31110. DAGB0_RESERVE12__RESERVE_MASK
31111. DAGB0_RESERVE12__RESERVE__SHIFT
31112. DAGB0_RESERVE130__RESERVE_MASK
31113. DAGB0_RESERVE130__RESERVE__SHIFT
31114. DAGB0_RESERVE131__RESERVE_MASK
31115. DAGB0_RESERVE131__RESERVE__SHIFT
31116. DAGB0_RESERVE13__RESERVE_MASK
31117. DAGB0_RESERVE13__RESERVE__SHIFT
31118. DAGB0_RESERVE14__RESERVE_MASK
31119. DAGB0_RESERVE14__RESERVE__SHIFT
31120. DAGB0_RESERVE15__RESERVE_MASK
31121. DAGB0_RESERVE15__RESERVE__SHIFT
31122. DAGB0_RESERVE16__RESERVE_MASK
31123. DAGB0_RESERVE16__RESERVE__SHIFT
31124. DAGB0_RESERVE17__RESERVE_MASK
31125. DAGB0_RESERVE17__RESERVE__SHIFT
31126. DAGB0_RESERVE18__RESERVE_MASK
31127. DAGB0_RESERVE18__RESERVE__SHIFT
31128. DAGB0_RESERVE19__RESERVE_MASK
31129. DAGB0_RESERVE19__RESERVE__SHIFT
31130. DAGB0_RESERVE1__RESERVE_MASK
31131. DAGB0_RESERVE1__RESERVE__SHIFT
31132. DAGB0_RESERVE20__RESERVE_MASK
31133. DAGB0_RESERVE20__RESERVE__SHIFT
31134. DAGB0_RESERVE21__RESERVE_MASK
31135. DAGB0_RESERVE21__RESERVE__SHIFT
31136. DAGB0_RESERVE22__RESERVE_MASK
31137. DAGB0_RESERVE22__RESERVE__SHIFT
31138. DAGB0_RESERVE23__RESERVE_MASK
31139. DAGB0_RESERVE23__RESERVE__SHIFT
31140. DAGB0_RESERVE24__RESERVE_MASK
31141. DAGB0_RESERVE24__RESERVE__SHIFT
31142. DAGB0_RESERVE25__RESERVE_MASK
31143. DAGB0_RESERVE25__RESERVE__SHIFT
31144. DAGB0_RESERVE26__RESERVE_MASK
31145. DAGB0_RESERVE26__RESERVE__SHIFT
31146. DAGB0_RESERVE27__RESERVE_MASK
31147. DAGB0_RESERVE27__RESERVE__SHIFT
31148. DAGB0_RESERVE28__RESERVE_MASK
31149. DAGB0_RESERVE28__RESERVE__SHIFT
31150. DAGB0_RESERVE29__RESERVE_MASK
31151. DAGB0_RESERVE29__RESERVE__SHIFT
31152. DAGB0_RESERVE2__RESERVE_MASK
31153. DAGB0_RESERVE2__RESERVE__SHIFT
31154. DAGB0_RESERVE30__RESERVE_MASK
31155. DAGB0_RESERVE30__RESERVE__SHIFT
31156. DAGB0_RESERVE31__RESERVE_MASK
31157. DAGB0_RESERVE31__RESERVE__SHIFT
31158. DAGB0_RESERVE32__RESERVE_MASK
31159. DAGB0_RESERVE32__RESERVE__SHIFT
31160. DAGB0_RESERVE33__RESERVE_MASK
31161. DAGB0_RESERVE33__RESERVE__SHIFT
31162. DAGB0_RESERVE34__RESERVE_MASK
31163. DAGB0_RESERVE34__RESERVE__SHIFT
31164. DAGB0_RESERVE35__RESERVE_MASK
31165. DAGB0_RESERVE35__RESERVE__SHIFT
31166. DAGB0_RESERVE36__RESERVE_MASK
31167. DAGB0_RESERVE36__RESERVE__SHIFT
31168. DAGB0_RESERVE37__RESERVE_MASK
31169. DAGB0_RESERVE37__RESERVE__SHIFT
31170. DAGB0_RESERVE38__RESERVE_MASK
31171. DAGB0_RESERVE38__RESERVE__SHIFT
31172. DAGB0_RESERVE39__RESERVE_MASK
31173. DAGB0_RESERVE39__RESERVE__SHIFT
31174. DAGB0_RESERVE3__RESERVE_MASK
31175. DAGB0_RESERVE3__RESERVE__SHIFT
31176. DAGB0_RESERVE40__RESERVE_MASK
31177. DAGB0_RESERVE40__RESERVE__SHIFT
31178. DAGB0_RESERVE41__RESERVE_MASK
31179. DAGB0_RESERVE41__RESERVE__SHIFT
31180. DAGB0_RESERVE42__RESERVE_MASK
31181. DAGB0_RESERVE42__RESERVE__SHIFT
31182. DAGB0_RESERVE43__RESERVE_MASK
31183. DAGB0_RESERVE43__RESERVE__SHIFT
31184. DAGB0_RESERVE44__RESERVE_MASK
31185. DAGB0_RESERVE44__RESERVE__SHIFT
31186. DAGB0_RESERVE45__RESERVE_MASK
31187. DAGB0_RESERVE45__RESERVE__SHIFT
31188. DAGB0_RESERVE46__RESERVE_MASK
31189. DAGB0_RESERVE46__RESERVE__SHIFT
31190. DAGB0_RESERVE47__RESERVE_MASK
31191. DAGB0_RESERVE47__RESERVE__SHIFT
31192. DAGB0_RESERVE48__RESERVE_MASK
31193. DAGB0_RESERVE48__RESERVE__SHIFT
31194. DAGB0_RESERVE49__RESERVE_MASK
31195. DAGB0_RESERVE49__RESERVE__SHIFT
31196. DAGB0_RESERVE4__RESERVE_MASK
31197. DAGB0_RESERVE4__RESERVE__SHIFT
31198. DAGB0_RESERVE50__RESERVE_MASK
31199. DAGB0_RESERVE50__RESERVE__SHIFT
31200. DAGB0_RESERVE51__RESERVE_MASK
31201. DAGB0_RESERVE51__RESERVE__SHIFT
31202. DAGB0_RESERVE52__RESERVE_MASK
31203. DAGB0_RESERVE52__RESERVE__SHIFT
31204. DAGB0_RESERVE53__RESERVE_MASK
31205. DAGB0_RESERVE53__RESERVE__SHIFT
31206. DAGB0_RESERVE54__RESERVE_MASK
31207. DAGB0_RESERVE54__RESERVE__SHIFT
31208. DAGB0_RESERVE55__RESERVE_MASK
31209. DAGB0_RESERVE55__RESERVE__SHIFT
31210. DAGB0_RESERVE56__RESERVE_MASK
31211. DAGB0_RESERVE56__RESERVE__SHIFT
31212. DAGB0_RESERVE57__RESERVE_MASK
31213. DAGB0_RESERVE57__RESERVE__SHIFT
31214. DAGB0_RESERVE58__RESERVE_MASK
31215. DAGB0_RESERVE58__RESERVE__SHIFT
31216. DAGB0_RESERVE59__RESERVE_MASK
31217. DAGB0_RESERVE59__RESERVE__SHIFT
31218. DAGB0_RESERVE5__RESERVE_MASK
31219. DAGB0_RESERVE5__RESERVE__SHIFT
31220. DAGB0_RESERVE60__RESERVE_MASK
31221. DAGB0_RESERVE60__RESERVE__SHIFT
31222. DAGB0_RESERVE61__RESERVE_MASK
31223. DAGB0_RESERVE61__RESERVE__SHIFT
31224. DAGB0_RESERVE62__RESERVE_MASK
31225. DAGB0_RESERVE62__RESERVE__SHIFT
31226. DAGB0_RESERVE63__RESERVE_MASK
31227. DAGB0_RESERVE63__RESERVE__SHIFT
31228. DAGB0_RESERVE64__RESERVE_MASK
31229. DAGB0_RESERVE64__RESERVE__SHIFT
31230. DAGB0_RESERVE65__RESERVE_MASK
31231. DAGB0_RESERVE65__RESERVE__SHIFT
31232. DAGB0_RESERVE66__RESERVE_MASK
31233. DAGB0_RESERVE66__RESERVE__SHIFT
31234. DAGB0_RESERVE67__RESERVE_MASK
31235. DAGB0_RESERVE67__RESERVE__SHIFT
31236. DAGB0_RESERVE68__RESERVE_MASK
31237. DAGB0_RESERVE68__RESERVE__SHIFT
31238. DAGB0_RESERVE69__RESERVE_MASK
31239. DAGB0_RESERVE69__RESERVE__SHIFT
31240. DAGB0_RESERVE6__RESERVE_MASK
31241. DAGB0_RESERVE6__RESERVE__SHIFT
31242. DAGB0_RESERVE70__RESERVE_MASK
31243. DAGB0_RESERVE70__RESERVE__SHIFT
31244. DAGB0_RESERVE71__RESERVE_MASK
31245. DAGB0_RESERVE71__RESERVE__SHIFT
31246. DAGB0_RESERVE72__RESERVE_MASK
31247. DAGB0_RESERVE72__RESERVE__SHIFT
31248. DAGB0_RESERVE73__RESERVE_MASK
31249. DAGB0_RESERVE73__RESERVE__SHIFT
31250. DAGB0_RESERVE74__RESERVE_MASK
31251. DAGB0_RESERVE74__RESERVE__SHIFT
31252. DAGB0_RESERVE75__RESERVE_MASK
31253. DAGB0_RESERVE75__RESERVE__SHIFT
31254. DAGB0_RESERVE76__RESERVE_MASK
31255. DAGB0_RESERVE76__RESERVE__SHIFT
31256. DAGB0_RESERVE77__RESERVE_MASK
31257. DAGB0_RESERVE77__RESERVE__SHIFT
31258. DAGB0_RESERVE78__RESERVE_MASK
31259. DAGB0_RESERVE78__RESERVE__SHIFT
31260. DAGB0_RESERVE79__RESERVE_MASK
31261. DAGB0_RESERVE79__RESERVE__SHIFT
31262. DAGB0_RESERVE7__RESERVE_MASK
31263. DAGB0_RESERVE7__RESERVE__SHIFT
31264. DAGB0_RESERVE80__RESERVE_MASK
31265. DAGB0_RESERVE80__RESERVE__SHIFT
31266. DAGB0_RESERVE81__RESERVE_MASK
31267. DAGB0_RESERVE81__RESERVE__SHIFT
31268. DAGB0_RESERVE82__RESERVE_MASK
31269. DAGB0_RESERVE82__RESERVE__SHIFT
31270. DAGB0_RESERVE83__RESERVE_MASK
31271. DAGB0_RESERVE83__RESERVE__SHIFT
31272. DAGB0_RESERVE84__RESERVE_MASK
31273. DAGB0_RESERVE84__RESERVE__SHIFT
31274. DAGB0_RESERVE85__RESERVE_MASK
31275. DAGB0_RESERVE85__RESERVE__SHIFT
31276. DAGB0_RESERVE86__RESERVE_MASK
31277. DAGB0_RESERVE86__RESERVE__SHIFT
31278. DAGB0_RESERVE87__RESERVE_MASK
31279. DAGB0_RESERVE87__RESERVE__SHIFT
31280. DAGB0_RESERVE88__RESERVE_MASK
31281. DAGB0_RESERVE88__RESERVE__SHIFT
31282. DAGB0_RESERVE89__RESERVE_MASK
31283. DAGB0_RESERVE89__RESERVE__SHIFT
31284. DAGB0_RESERVE8__RESERVE_MASK
31285. DAGB0_RESERVE8__RESERVE__SHIFT
31286. DAGB0_RESERVE90__RESERVE_MASK
31287. DAGB0_RESERVE90__RESERVE__SHIFT
31288. DAGB0_RESERVE91__RESERVE_MASK
31289. DAGB0_RESERVE91__RESERVE__SHIFT
31290. DAGB0_RESERVE92__RESERVE_MASK
31291. DAGB0_RESERVE92__RESERVE__SHIFT
31292. DAGB0_RESERVE93__RESERVE_MASK
31293. DAGB0_RESERVE93__RESERVE__SHIFT
31294. DAGB0_RESERVE94__RESERVE_MASK
31295. DAGB0_RESERVE94__RESERVE__SHIFT
31296. DAGB0_RESERVE95__RESERVE_MASK
31297. DAGB0_RESERVE95__RESERVE__SHIFT
31298. DAGB0_RESERVE96__RESERVE_MASK
31299. DAGB0_RESERVE96__RESERVE__SHIFT
31300. DAGB0_RESERVE97__RESERVE_MASK
31301. DAGB0_RESERVE97__RESERVE__SHIFT
31302. DAGB0_RESERVE98__RESERVE_MASK
31303. DAGB0_RESERVE98__RESERVE__SHIFT
31304. DAGB0_RESERVE99__RESERVE_MASK
31305. DAGB0_RESERVE99__RESERVE__SHIFT
31306. DAGB0_RESERVE9__RESERVE_MASK
31307. DAGB0_RESERVE9__RESERVE__SHIFT
31308. DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK
31309. DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT
31310. DAGB0_WRCLI0__MAX_BW_ENABLE_MASK
31311. DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT
31312. DAGB0_WRCLI0__MAX_BW_MASK
31313. DAGB0_WRCLI0__MAX_BW__SHIFT
31314. DAGB0_WRCLI0__MAX_OSD_MASK
31315. DAGB0_WRCLI0__MAX_OSD__SHIFT
31316. DAGB0_WRCLI0__MIN_BW_ENABLE_MASK
31317. DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT
31318. DAGB0_WRCLI0__MIN_BW_MASK
31319. DAGB0_WRCLI0__MIN_BW__SHIFT
31320. DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK
31321. DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
31322. DAGB0_WRCLI0__URG_HIGH_MASK
31323. DAGB0_WRCLI0__URG_HIGH__SHIFT
31324. DAGB0_WRCLI0__URG_LOW_MASK
31325. DAGB0_WRCLI0__URG_LOW__SHIFT
31326. DAGB0_WRCLI0__VIRT_CHAN_MASK
31327. DAGB0_WRCLI0__VIRT_CHAN__SHIFT
31328. DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK
31329. DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT
31330. DAGB0_WRCLI10__MAX_BW_ENABLE_MASK
31331. DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT
31332. DAGB0_WRCLI10__MAX_BW_MASK
31333. DAGB0_WRCLI10__MAX_BW__SHIFT
31334. DAGB0_WRCLI10__MAX_OSD_MASK
31335. DAGB0_WRCLI10__MAX_OSD__SHIFT
31336. DAGB0_WRCLI10__MIN_BW_ENABLE_MASK
31337. DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT
31338. DAGB0_WRCLI10__MIN_BW_MASK
31339. DAGB0_WRCLI10__MIN_BW__SHIFT
31340. DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK
31341. DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
31342. DAGB0_WRCLI10__URG_HIGH_MASK
31343. DAGB0_WRCLI10__URG_HIGH__SHIFT
31344. DAGB0_WRCLI10__URG_LOW_MASK
31345. DAGB0_WRCLI10__URG_LOW__SHIFT
31346. DAGB0_WRCLI10__VIRT_CHAN_MASK
31347. DAGB0_WRCLI10__VIRT_CHAN__SHIFT
31348. DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK
31349. DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT
31350. DAGB0_WRCLI11__MAX_BW_ENABLE_MASK
31351. DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT
31352. DAGB0_WRCLI11__MAX_BW_MASK
31353. DAGB0_WRCLI11__MAX_BW__SHIFT
31354. DAGB0_WRCLI11__MAX_OSD_MASK
31355. DAGB0_WRCLI11__MAX_OSD__SHIFT
31356. DAGB0_WRCLI11__MIN_BW_ENABLE_MASK
31357. DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT
31358. DAGB0_WRCLI11__MIN_BW_MASK
31359. DAGB0_WRCLI11__MIN_BW__SHIFT
31360. DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK
31361. DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
31362. DAGB0_WRCLI11__URG_HIGH_MASK
31363. DAGB0_WRCLI11__URG_HIGH__SHIFT
31364. DAGB0_WRCLI11__URG_LOW_MASK
31365. DAGB0_WRCLI11__URG_LOW__SHIFT
31366. DAGB0_WRCLI11__VIRT_CHAN_MASK
31367. DAGB0_WRCLI11__VIRT_CHAN__SHIFT
31368. DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK
31369. DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT
31370. DAGB0_WRCLI12__MAX_BW_ENABLE_MASK
31371. DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT
31372. DAGB0_WRCLI12__MAX_BW_MASK
31373. DAGB0_WRCLI12__MAX_BW__SHIFT
31374. DAGB0_WRCLI12__MAX_OSD_MASK
31375. DAGB0_WRCLI12__MAX_OSD__SHIFT
31376. DAGB0_WRCLI12__MIN_BW_ENABLE_MASK
31377. DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT
31378. DAGB0_WRCLI12__MIN_BW_MASK
31379. DAGB0_WRCLI12__MIN_BW__SHIFT
31380. DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK
31381. DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
31382. DAGB0_WRCLI12__URG_HIGH_MASK
31383. DAGB0_WRCLI12__URG_HIGH__SHIFT
31384. DAGB0_WRCLI12__URG_LOW_MASK
31385. DAGB0_WRCLI12__URG_LOW__SHIFT
31386. DAGB0_WRCLI12__VIRT_CHAN_MASK
31387. DAGB0_WRCLI12__VIRT_CHAN__SHIFT
31388. DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK
31389. DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT
31390. DAGB0_WRCLI13__MAX_BW_ENABLE_MASK
31391. DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT
31392. DAGB0_WRCLI13__MAX_BW_MASK
31393. DAGB0_WRCLI13__MAX_BW__SHIFT
31394. DAGB0_WRCLI13__MAX_OSD_MASK
31395. DAGB0_WRCLI13__MAX_OSD__SHIFT
31396. DAGB0_WRCLI13__MIN_BW_ENABLE_MASK
31397. DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT
31398. DAGB0_WRCLI13__MIN_BW_MASK
31399. DAGB0_WRCLI13__MIN_BW__SHIFT
31400. DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK
31401. DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
31402. DAGB0_WRCLI13__URG_HIGH_MASK
31403. DAGB0_WRCLI13__URG_HIGH__SHIFT
31404. DAGB0_WRCLI13__URG_LOW_MASK
31405. DAGB0_WRCLI13__URG_LOW__SHIFT
31406. DAGB0_WRCLI13__VIRT_CHAN_MASK
31407. DAGB0_WRCLI13__VIRT_CHAN__SHIFT
31408. DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK
31409. DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT
31410. DAGB0_WRCLI14__MAX_BW_ENABLE_MASK
31411. DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT
31412. DAGB0_WRCLI14__MAX_BW_MASK
31413. DAGB0_WRCLI14__MAX_BW__SHIFT
31414. DAGB0_WRCLI14__MAX_OSD_MASK
31415. DAGB0_WRCLI14__MAX_OSD__SHIFT
31416. DAGB0_WRCLI14__MIN_BW_ENABLE_MASK
31417. DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT
31418. DAGB0_WRCLI14__MIN_BW_MASK
31419. DAGB0_WRCLI14__MIN_BW__SHIFT
31420. DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK
31421. DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
31422. DAGB0_WRCLI14__URG_HIGH_MASK
31423. DAGB0_WRCLI14__URG_HIGH__SHIFT
31424. DAGB0_WRCLI14__URG_LOW_MASK
31425. DAGB0_WRCLI14__URG_LOW__SHIFT
31426. DAGB0_WRCLI14__VIRT_CHAN_MASK
31427. DAGB0_WRCLI14__VIRT_CHAN__SHIFT
31428. DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK
31429. DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT
31430. DAGB0_WRCLI15__MAX_BW_ENABLE_MASK
31431. DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT
31432. DAGB0_WRCLI15__MAX_BW_MASK
31433. DAGB0_WRCLI15__MAX_BW__SHIFT
31434. DAGB0_WRCLI15__MAX_OSD_MASK
31435. DAGB0_WRCLI15__MAX_OSD__SHIFT
31436. DAGB0_WRCLI15__MIN_BW_ENABLE_MASK
31437. DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT
31438. DAGB0_WRCLI15__MIN_BW_MASK
31439. DAGB0_WRCLI15__MIN_BW__SHIFT
31440. DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK
31441. DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
31442. DAGB0_WRCLI15__URG_HIGH_MASK
31443. DAGB0_WRCLI15__URG_HIGH__SHIFT
31444. DAGB0_WRCLI15__URG_LOW_MASK
31445. DAGB0_WRCLI15__URG_LOW__SHIFT
31446. DAGB0_WRCLI15__VIRT_CHAN_MASK
31447. DAGB0_WRCLI15__VIRT_CHAN__SHIFT
31448. DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK
31449. DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT
31450. DAGB0_WRCLI16__MAX_BW_ENABLE_MASK
31451. DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT
31452. DAGB0_WRCLI16__MAX_BW_MASK
31453. DAGB0_WRCLI16__MAX_BW__SHIFT
31454. DAGB0_WRCLI16__MAX_OSD_MASK
31455. DAGB0_WRCLI16__MAX_OSD__SHIFT
31456. DAGB0_WRCLI16__MIN_BW_ENABLE_MASK
31457. DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT
31458. DAGB0_WRCLI16__MIN_BW_MASK
31459. DAGB0_WRCLI16__MIN_BW__SHIFT
31460. DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK
31461. DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT
31462. DAGB0_WRCLI16__URG_HIGH_MASK
31463. DAGB0_WRCLI16__URG_HIGH__SHIFT
31464. DAGB0_WRCLI16__URG_LOW_MASK
31465. DAGB0_WRCLI16__URG_LOW__SHIFT
31466. DAGB0_WRCLI16__VIRT_CHAN_MASK
31467. DAGB0_WRCLI16__VIRT_CHAN__SHIFT
31468. DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK
31469. DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT
31470. DAGB0_WRCLI17__MAX_BW_ENABLE_MASK
31471. DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT
31472. DAGB0_WRCLI17__MAX_BW_MASK
31473. DAGB0_WRCLI17__MAX_BW__SHIFT
31474. DAGB0_WRCLI17__MAX_OSD_MASK
31475. DAGB0_WRCLI17__MAX_OSD__SHIFT
31476. DAGB0_WRCLI17__MIN_BW_ENABLE_MASK
31477. DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT
31478. DAGB0_WRCLI17__MIN_BW_MASK
31479. DAGB0_WRCLI17__MIN_BW__SHIFT
31480. DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK
31481. DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT
31482. DAGB0_WRCLI17__URG_HIGH_MASK
31483. DAGB0_WRCLI17__URG_HIGH__SHIFT
31484. DAGB0_WRCLI17__URG_LOW_MASK
31485. DAGB0_WRCLI17__URG_LOW__SHIFT
31486. DAGB0_WRCLI17__VIRT_CHAN_MASK
31487. DAGB0_WRCLI17__VIRT_CHAN__SHIFT
31488. DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK
31489. DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT
31490. DAGB0_WRCLI18__MAX_BW_ENABLE_MASK
31491. DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT
31492. DAGB0_WRCLI18__MAX_BW_MASK
31493. DAGB0_WRCLI18__MAX_BW__SHIFT
31494. DAGB0_WRCLI18__MAX_OSD_MASK
31495. DAGB0_WRCLI18__MAX_OSD__SHIFT
31496. DAGB0_WRCLI18__MIN_BW_ENABLE_MASK
31497. DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT
31498. DAGB0_WRCLI18__MIN_BW_MASK
31499. DAGB0_WRCLI18__MIN_BW__SHIFT
31500. DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK
31501. DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT
31502. DAGB0_WRCLI18__URG_HIGH_MASK
31503. DAGB0_WRCLI18__URG_HIGH__SHIFT
31504. DAGB0_WRCLI18__URG_LOW_MASK
31505. DAGB0_WRCLI18__URG_LOW__SHIFT
31506. DAGB0_WRCLI18__VIRT_CHAN_MASK
31507. DAGB0_WRCLI18__VIRT_CHAN__SHIFT
31508. DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK
31509. DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT
31510. DAGB0_WRCLI19__MAX_BW_ENABLE_MASK
31511. DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT
31512. DAGB0_WRCLI19__MAX_BW_MASK
31513. DAGB0_WRCLI19__MAX_BW__SHIFT
31514. DAGB0_WRCLI19__MAX_OSD_MASK
31515. DAGB0_WRCLI19__MAX_OSD__SHIFT
31516. DAGB0_WRCLI19__MIN_BW_ENABLE_MASK
31517. DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT
31518. DAGB0_WRCLI19__MIN_BW_MASK
31519. DAGB0_WRCLI19__MIN_BW__SHIFT
31520. DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK
31521. DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT
31522. DAGB0_WRCLI19__URG_HIGH_MASK
31523. DAGB0_WRCLI19__URG_HIGH__SHIFT
31524. DAGB0_WRCLI19__URG_LOW_MASK
31525. DAGB0_WRCLI19__URG_LOW__SHIFT
31526. DAGB0_WRCLI19__VIRT_CHAN_MASK
31527. DAGB0_WRCLI19__VIRT_CHAN__SHIFT
31528. DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK
31529. DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT
31530. DAGB0_WRCLI1__MAX_BW_ENABLE_MASK
31531. DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT
31532. DAGB0_WRCLI1__MAX_BW_MASK
31533. DAGB0_WRCLI1__MAX_BW__SHIFT
31534. DAGB0_WRCLI1__MAX_OSD_MASK
31535. DAGB0_WRCLI1__MAX_OSD__SHIFT
31536. DAGB0_WRCLI1__MIN_BW_ENABLE_MASK
31537. DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT
31538. DAGB0_WRCLI1__MIN_BW_MASK
31539. DAGB0_WRCLI1__MIN_BW__SHIFT
31540. DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK
31541. DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
31542. DAGB0_WRCLI1__URG_HIGH_MASK
31543. DAGB0_WRCLI1__URG_HIGH__SHIFT
31544. DAGB0_WRCLI1__URG_LOW_MASK
31545. DAGB0_WRCLI1__URG_LOW__SHIFT
31546. DAGB0_WRCLI1__VIRT_CHAN_MASK
31547. DAGB0_WRCLI1__VIRT_CHAN__SHIFT
31548. DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK
31549. DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT
31550. DAGB0_WRCLI20__MAX_BW_ENABLE_MASK
31551. DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT
31552. DAGB0_WRCLI20__MAX_BW_MASK
31553. DAGB0_WRCLI20__MAX_BW__SHIFT
31554. DAGB0_WRCLI20__MAX_OSD_MASK
31555. DAGB0_WRCLI20__MAX_OSD__SHIFT
31556. DAGB0_WRCLI20__MIN_BW_ENABLE_MASK
31557. DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT
31558. DAGB0_WRCLI20__MIN_BW_MASK
31559. DAGB0_WRCLI20__MIN_BW__SHIFT
31560. DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK
31561. DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT
31562. DAGB0_WRCLI20__URG_HIGH_MASK
31563. DAGB0_WRCLI20__URG_HIGH__SHIFT
31564. DAGB0_WRCLI20__URG_LOW_MASK
31565. DAGB0_WRCLI20__URG_LOW__SHIFT
31566. DAGB0_WRCLI20__VIRT_CHAN_MASK
31567. DAGB0_WRCLI20__VIRT_CHAN__SHIFT
31568. DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK
31569. DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT
31570. DAGB0_WRCLI21__MAX_BW_ENABLE_MASK
31571. DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT
31572. DAGB0_WRCLI21__MAX_BW_MASK
31573. DAGB0_WRCLI21__MAX_BW__SHIFT
31574. DAGB0_WRCLI21__MAX_OSD_MASK
31575. DAGB0_WRCLI21__MAX_OSD__SHIFT
31576. DAGB0_WRCLI21__MIN_BW_ENABLE_MASK
31577. DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT
31578. DAGB0_WRCLI21__MIN_BW_MASK
31579. DAGB0_WRCLI21__MIN_BW__SHIFT
31580. DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK
31581. DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT
31582. DAGB0_WRCLI21__URG_HIGH_MASK
31583. DAGB0_WRCLI21__URG_HIGH__SHIFT
31584. DAGB0_WRCLI21__URG_LOW_MASK
31585. DAGB0_WRCLI21__URG_LOW__SHIFT
31586. DAGB0_WRCLI21__VIRT_CHAN_MASK
31587. DAGB0_WRCLI21__VIRT_CHAN__SHIFT
31588. DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK
31589. DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT
31590. DAGB0_WRCLI22__MAX_BW_ENABLE_MASK
31591. DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT
31592. DAGB0_WRCLI22__MAX_BW_MASK
31593. DAGB0_WRCLI22__MAX_BW__SHIFT
31594. DAGB0_WRCLI22__MAX_OSD_MASK
31595. DAGB0_WRCLI22__MAX_OSD__SHIFT
31596. DAGB0_WRCLI22__MIN_BW_ENABLE_MASK
31597. DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT
31598. DAGB0_WRCLI22__MIN_BW_MASK
31599. DAGB0_WRCLI22__MIN_BW__SHIFT
31600. DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK
31601. DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT
31602. DAGB0_WRCLI22__URG_HIGH_MASK
31603. DAGB0_WRCLI22__URG_HIGH__SHIFT
31604. DAGB0_WRCLI22__URG_LOW_MASK
31605. DAGB0_WRCLI22__URG_LOW__SHIFT
31606. DAGB0_WRCLI22__VIRT_CHAN_MASK
31607. DAGB0_WRCLI22__VIRT_CHAN__SHIFT
31608. DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK
31609. DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT
31610. DAGB0_WRCLI23__MAX_BW_ENABLE_MASK
31611. DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT
31612. DAGB0_WRCLI23__MAX_BW_MASK
31613. DAGB0_WRCLI23__MAX_BW__SHIFT
31614. DAGB0_WRCLI23__MAX_OSD_MASK
31615. DAGB0_WRCLI23__MAX_OSD__SHIFT
31616. DAGB0_WRCLI23__MIN_BW_ENABLE_MASK
31617. DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT
31618. DAGB0_WRCLI23__MIN_BW_MASK
31619. DAGB0_WRCLI23__MIN_BW__SHIFT
31620. DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK
31621. DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT
31622. DAGB0_WRCLI23__URG_HIGH_MASK
31623. DAGB0_WRCLI23__URG_HIGH__SHIFT
31624. DAGB0_WRCLI23__URG_LOW_MASK
31625. DAGB0_WRCLI23__URG_LOW__SHIFT
31626. DAGB0_WRCLI23__VIRT_CHAN_MASK
31627. DAGB0_WRCLI23__VIRT_CHAN__SHIFT
31628. DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK
31629. DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT
31630. DAGB0_WRCLI24__MAX_BW_ENABLE_MASK
31631. DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT
31632. DAGB0_WRCLI24__MAX_BW_MASK
31633. DAGB0_WRCLI24__MAX_BW__SHIFT
31634. DAGB0_WRCLI24__MAX_OSD_MASK
31635. DAGB0_WRCLI24__MAX_OSD__SHIFT
31636. DAGB0_WRCLI24__MIN_BW_ENABLE_MASK
31637. DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT
31638. DAGB0_WRCLI24__MIN_BW_MASK
31639. DAGB0_WRCLI24__MIN_BW__SHIFT
31640. DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK
31641. DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT
31642. DAGB0_WRCLI24__URG_HIGH_MASK
31643. DAGB0_WRCLI24__URG_HIGH__SHIFT
31644. DAGB0_WRCLI24__URG_LOW_MASK
31645. DAGB0_WRCLI24__URG_LOW__SHIFT
31646. DAGB0_WRCLI24__VIRT_CHAN_MASK
31647. DAGB0_WRCLI24__VIRT_CHAN__SHIFT
31648. DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK
31649. DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT
31650. DAGB0_WRCLI25__MAX_BW_ENABLE_MASK
31651. DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT
31652. DAGB0_WRCLI25__MAX_BW_MASK
31653. DAGB0_WRCLI25__MAX_BW__SHIFT
31654. DAGB0_WRCLI25__MAX_OSD_MASK
31655. DAGB0_WRCLI25__MAX_OSD__SHIFT
31656. DAGB0_WRCLI25__MIN_BW_ENABLE_MASK
31657. DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT
31658. DAGB0_WRCLI25__MIN_BW_MASK
31659. DAGB0_WRCLI25__MIN_BW__SHIFT
31660. DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK
31661. DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT
31662. DAGB0_WRCLI25__URG_HIGH_MASK
31663. DAGB0_WRCLI25__URG_HIGH__SHIFT
31664. DAGB0_WRCLI25__URG_LOW_MASK
31665. DAGB0_WRCLI25__URG_LOW__SHIFT
31666. DAGB0_WRCLI25__VIRT_CHAN_MASK
31667. DAGB0_WRCLI25__VIRT_CHAN__SHIFT
31668. DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK
31669. DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT
31670. DAGB0_WRCLI26__MAX_BW_ENABLE_MASK
31671. DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT
31672. DAGB0_WRCLI26__MAX_BW_MASK
31673. DAGB0_WRCLI26__MAX_BW__SHIFT
31674. DAGB0_WRCLI26__MAX_OSD_MASK
31675. DAGB0_WRCLI26__MAX_OSD__SHIFT
31676. DAGB0_WRCLI26__MIN_BW_ENABLE_MASK
31677. DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT
31678. DAGB0_WRCLI26__MIN_BW_MASK
31679. DAGB0_WRCLI26__MIN_BW__SHIFT
31680. DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK
31681. DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT
31682. DAGB0_WRCLI26__URG_HIGH_MASK
31683. DAGB0_WRCLI26__URG_HIGH__SHIFT
31684. DAGB0_WRCLI26__URG_LOW_MASK
31685. DAGB0_WRCLI26__URG_LOW__SHIFT
31686. DAGB0_WRCLI26__VIRT_CHAN_MASK
31687. DAGB0_WRCLI26__VIRT_CHAN__SHIFT
31688. DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK
31689. DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT
31690. DAGB0_WRCLI27__MAX_BW_ENABLE_MASK
31691. DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT
31692. DAGB0_WRCLI27__MAX_BW_MASK
31693. DAGB0_WRCLI27__MAX_BW__SHIFT
31694. DAGB0_WRCLI27__MAX_OSD_MASK
31695. DAGB0_WRCLI27__MAX_OSD__SHIFT
31696. DAGB0_WRCLI27__MIN_BW_ENABLE_MASK
31697. DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT
31698. DAGB0_WRCLI27__MIN_BW_MASK
31699. DAGB0_WRCLI27__MIN_BW__SHIFT
31700. DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK
31701. DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT
31702. DAGB0_WRCLI27__URG_HIGH_MASK
31703. DAGB0_WRCLI27__URG_HIGH__SHIFT
31704. DAGB0_WRCLI27__URG_LOW_MASK
31705. DAGB0_WRCLI27__URG_LOW__SHIFT
31706. DAGB0_WRCLI27__VIRT_CHAN_MASK
31707. DAGB0_WRCLI27__VIRT_CHAN__SHIFT
31708. DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK
31709. DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT
31710. DAGB0_WRCLI28__MAX_BW_ENABLE_MASK
31711. DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT
31712. DAGB0_WRCLI28__MAX_BW_MASK
31713. DAGB0_WRCLI28__MAX_BW__SHIFT
31714. DAGB0_WRCLI28__MAX_OSD_MASK
31715. DAGB0_WRCLI28__MAX_OSD__SHIFT
31716. DAGB0_WRCLI28__MIN_BW_ENABLE_MASK
31717. DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT
31718. DAGB0_WRCLI28__MIN_BW_MASK
31719. DAGB0_WRCLI28__MIN_BW__SHIFT
31720. DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK
31721. DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT
31722. DAGB0_WRCLI28__URG_HIGH_MASK
31723. DAGB0_WRCLI28__URG_HIGH__SHIFT
31724. DAGB0_WRCLI28__URG_LOW_MASK
31725. DAGB0_WRCLI28__URG_LOW__SHIFT
31726. DAGB0_WRCLI28__VIRT_CHAN_MASK
31727. DAGB0_WRCLI28__VIRT_CHAN__SHIFT
31728. DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK
31729. DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT
31730. DAGB0_WRCLI29__MAX_BW_ENABLE_MASK
31731. DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT
31732. DAGB0_WRCLI29__MAX_BW_MASK
31733. DAGB0_WRCLI29__MAX_BW__SHIFT
31734. DAGB0_WRCLI29__MAX_OSD_MASK
31735. DAGB0_WRCLI29__MAX_OSD__SHIFT
31736. DAGB0_WRCLI29__MIN_BW_ENABLE_MASK
31737. DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT
31738. DAGB0_WRCLI29__MIN_BW_MASK
31739. DAGB0_WRCLI29__MIN_BW__SHIFT
31740. DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK
31741. DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT
31742. DAGB0_WRCLI29__URG_HIGH_MASK
31743. DAGB0_WRCLI29__URG_HIGH__SHIFT
31744. DAGB0_WRCLI29__URG_LOW_MASK
31745. DAGB0_WRCLI29__URG_LOW__SHIFT
31746. DAGB0_WRCLI29__VIRT_CHAN_MASK
31747. DAGB0_WRCLI29__VIRT_CHAN__SHIFT
31748. DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK
31749. DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT
31750. DAGB0_WRCLI2__MAX_BW_ENABLE_MASK
31751. DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT
31752. DAGB0_WRCLI2__MAX_BW_MASK
31753. DAGB0_WRCLI2__MAX_BW__SHIFT
31754. DAGB0_WRCLI2__MAX_OSD_MASK
31755. DAGB0_WRCLI2__MAX_OSD__SHIFT
31756. DAGB0_WRCLI2__MIN_BW_ENABLE_MASK
31757. DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT
31758. DAGB0_WRCLI2__MIN_BW_MASK
31759. DAGB0_WRCLI2__MIN_BW__SHIFT
31760. DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK
31761. DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
31762. DAGB0_WRCLI2__URG_HIGH_MASK
31763. DAGB0_WRCLI2__URG_HIGH__SHIFT
31764. DAGB0_WRCLI2__URG_LOW_MASK
31765. DAGB0_WRCLI2__URG_LOW__SHIFT
31766. DAGB0_WRCLI2__VIRT_CHAN_MASK
31767. DAGB0_WRCLI2__VIRT_CHAN__SHIFT
31768. DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK
31769. DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT
31770. DAGB0_WRCLI30__MAX_BW_ENABLE_MASK
31771. DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT
31772. DAGB0_WRCLI30__MAX_BW_MASK
31773. DAGB0_WRCLI30__MAX_BW__SHIFT
31774. DAGB0_WRCLI30__MAX_OSD_MASK
31775. DAGB0_WRCLI30__MAX_OSD__SHIFT
31776. DAGB0_WRCLI30__MIN_BW_ENABLE_MASK
31777. DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT
31778. DAGB0_WRCLI30__MIN_BW_MASK
31779. DAGB0_WRCLI30__MIN_BW__SHIFT
31780. DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK
31781. DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT
31782. DAGB0_WRCLI30__URG_HIGH_MASK
31783. DAGB0_WRCLI30__URG_HIGH__SHIFT
31784. DAGB0_WRCLI30__URG_LOW_MASK
31785. DAGB0_WRCLI30__URG_LOW__SHIFT
31786. DAGB0_WRCLI30__VIRT_CHAN_MASK
31787. DAGB0_WRCLI30__VIRT_CHAN__SHIFT
31788. DAGB0_WRCLI31__CHECK_TLB_CREDIT_MASK
31789. DAGB0_WRCLI31__CHECK_TLB_CREDIT__SHIFT
31790. DAGB0_WRCLI31__MAX_BW_ENABLE_MASK
31791. DAGB0_WRCLI31__MAX_BW_ENABLE__SHIFT
31792. DAGB0_WRCLI31__MAX_BW_MASK
31793. DAGB0_WRCLI31__MAX_BW__SHIFT
31794. DAGB0_WRCLI31__MAX_OSD_MASK
31795. DAGB0_WRCLI31__MAX_OSD__SHIFT
31796. DAGB0_WRCLI31__MIN_BW_ENABLE_MASK
31797. DAGB0_WRCLI31__MIN_BW_ENABLE__SHIFT
31798. DAGB0_WRCLI31__MIN_BW_MASK
31799. DAGB0_WRCLI31__MIN_BW__SHIFT
31800. DAGB0_WRCLI31__OSD_LIMITER_ENABLE_MASK
31801. DAGB0_WRCLI31__OSD_LIMITER_ENABLE__SHIFT
31802. DAGB0_WRCLI31__URG_HIGH_MASK
31803. DAGB0_WRCLI31__URG_HIGH__SHIFT
31804. DAGB0_WRCLI31__URG_LOW_MASK
31805. DAGB0_WRCLI31__URG_LOW__SHIFT
31806. DAGB0_WRCLI31__VIRT_CHAN_MASK
31807. DAGB0_WRCLI31__VIRT_CHAN__SHIFT
31808. DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK
31809. DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT
31810. DAGB0_WRCLI3__MAX_BW_ENABLE_MASK
31811. DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT
31812. DAGB0_WRCLI3__MAX_BW_MASK
31813. DAGB0_WRCLI3__MAX_BW__SHIFT
31814. DAGB0_WRCLI3__MAX_OSD_MASK
31815. DAGB0_WRCLI3__MAX_OSD__SHIFT
31816. DAGB0_WRCLI3__MIN_BW_ENABLE_MASK
31817. DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT
31818. DAGB0_WRCLI3__MIN_BW_MASK
31819. DAGB0_WRCLI3__MIN_BW__SHIFT
31820. DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK
31821. DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
31822. DAGB0_WRCLI3__URG_HIGH_MASK
31823. DAGB0_WRCLI3__URG_HIGH__SHIFT
31824. DAGB0_WRCLI3__URG_LOW_MASK
31825. DAGB0_WRCLI3__URG_LOW__SHIFT
31826. DAGB0_WRCLI3__VIRT_CHAN_MASK
31827. DAGB0_WRCLI3__VIRT_CHAN__SHIFT
31828. DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK
31829. DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT
31830. DAGB0_WRCLI4__MAX_BW_ENABLE_MASK
31831. DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT
31832. DAGB0_WRCLI4__MAX_BW_MASK
31833. DAGB0_WRCLI4__MAX_BW__SHIFT
31834. DAGB0_WRCLI4__MAX_OSD_MASK
31835. DAGB0_WRCLI4__MAX_OSD__SHIFT
31836. DAGB0_WRCLI4__MIN_BW_ENABLE_MASK
31837. DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT
31838. DAGB0_WRCLI4__MIN_BW_MASK
31839. DAGB0_WRCLI4__MIN_BW__SHIFT
31840. DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK
31841. DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
31842. DAGB0_WRCLI4__URG_HIGH_MASK
31843. DAGB0_WRCLI4__URG_HIGH__SHIFT
31844. DAGB0_WRCLI4__URG_LOW_MASK
31845. DAGB0_WRCLI4__URG_LOW__SHIFT
31846. DAGB0_WRCLI4__VIRT_CHAN_MASK
31847. DAGB0_WRCLI4__VIRT_CHAN__SHIFT
31848. DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK
31849. DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT
31850. DAGB0_WRCLI5__MAX_BW_ENABLE_MASK
31851. DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT
31852. DAGB0_WRCLI5__MAX_BW_MASK
31853. DAGB0_WRCLI5__MAX_BW__SHIFT
31854. DAGB0_WRCLI5__MAX_OSD_MASK
31855. DAGB0_WRCLI5__MAX_OSD__SHIFT
31856. DAGB0_WRCLI5__MIN_BW_ENABLE_MASK
31857. DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT
31858. DAGB0_WRCLI5__MIN_BW_MASK
31859. DAGB0_WRCLI5__MIN_BW__SHIFT
31860. DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK
31861. DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
31862. DAGB0_WRCLI5__URG_HIGH_MASK
31863. DAGB0_WRCLI5__URG_HIGH__SHIFT
31864. DAGB0_WRCLI5__URG_LOW_MASK
31865. DAGB0_WRCLI5__URG_LOW__SHIFT
31866. DAGB0_WRCLI5__VIRT_CHAN_MASK
31867. DAGB0_WRCLI5__VIRT_CHAN__SHIFT
31868. DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK
31869. DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT
31870. DAGB0_WRCLI6__MAX_BW_ENABLE_MASK
31871. DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT
31872. DAGB0_WRCLI6__MAX_BW_MASK
31873. DAGB0_WRCLI6__MAX_BW__SHIFT
31874. DAGB0_WRCLI6__MAX_OSD_MASK
31875. DAGB0_WRCLI6__MAX_OSD__SHIFT
31876. DAGB0_WRCLI6__MIN_BW_ENABLE_MASK
31877. DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT
31878. DAGB0_WRCLI6__MIN_BW_MASK
31879. DAGB0_WRCLI6__MIN_BW__SHIFT
31880. DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK
31881. DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
31882. DAGB0_WRCLI6__URG_HIGH_MASK
31883. DAGB0_WRCLI6__URG_HIGH__SHIFT
31884. DAGB0_WRCLI6__URG_LOW_MASK
31885. DAGB0_WRCLI6__URG_LOW__SHIFT
31886. DAGB0_WRCLI6__VIRT_CHAN_MASK
31887. DAGB0_WRCLI6__VIRT_CHAN__SHIFT
31888. DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK
31889. DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT
31890. DAGB0_WRCLI7__MAX_BW_ENABLE_MASK
31891. DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT
31892. DAGB0_WRCLI7__MAX_BW_MASK
31893. DAGB0_WRCLI7__MAX_BW__SHIFT
31894. DAGB0_WRCLI7__MAX_OSD_MASK
31895. DAGB0_WRCLI7__MAX_OSD__SHIFT
31896. DAGB0_WRCLI7__MIN_BW_ENABLE_MASK
31897. DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT
31898. DAGB0_WRCLI7__MIN_BW_MASK
31899. DAGB0_WRCLI7__MIN_BW__SHIFT
31900. DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK
31901. DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
31902. DAGB0_WRCLI7__URG_HIGH_MASK
31903. DAGB0_WRCLI7__URG_HIGH__SHIFT
31904. DAGB0_WRCLI7__URG_LOW_MASK
31905. DAGB0_WRCLI7__URG_LOW__SHIFT
31906. DAGB0_WRCLI7__VIRT_CHAN_MASK
31907. DAGB0_WRCLI7__VIRT_CHAN__SHIFT
31908. DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK
31909. DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT
31910. DAGB0_WRCLI8__MAX_BW_ENABLE_MASK
31911. DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT
31912. DAGB0_WRCLI8__MAX_BW_MASK
31913. DAGB0_WRCLI8__MAX_BW__SHIFT
31914. DAGB0_WRCLI8__MAX_OSD_MASK
31915. DAGB0_WRCLI8__MAX_OSD__SHIFT
31916. DAGB0_WRCLI8__MIN_BW_ENABLE_MASK
31917. DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT
31918. DAGB0_WRCLI8__MIN_BW_MASK
31919. DAGB0_WRCLI8__MIN_BW__SHIFT
31920. DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK
31921. DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
31922. DAGB0_WRCLI8__URG_HIGH_MASK
31923. DAGB0_WRCLI8__URG_HIGH__SHIFT
31924. DAGB0_WRCLI8__URG_LOW_MASK
31925. DAGB0_WRCLI8__URG_LOW__SHIFT
31926. DAGB0_WRCLI8__VIRT_CHAN_MASK
31927. DAGB0_WRCLI8__VIRT_CHAN__SHIFT
31928. DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK
31929. DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT
31930. DAGB0_WRCLI9__MAX_BW_ENABLE_MASK
31931. DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT
31932. DAGB0_WRCLI9__MAX_BW_MASK
31933. DAGB0_WRCLI9__MAX_BW__SHIFT
31934. DAGB0_WRCLI9__MAX_OSD_MASK
31935. DAGB0_WRCLI9__MAX_OSD__SHIFT
31936. DAGB0_WRCLI9__MIN_BW_ENABLE_MASK
31937. DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT
31938. DAGB0_WRCLI9__MIN_BW_MASK
31939. DAGB0_WRCLI9__MIN_BW__SHIFT
31940. DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK
31941. DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
31942. DAGB0_WRCLI9__URG_HIGH_MASK
31943. DAGB0_WRCLI9__URG_HIGH__SHIFT
31944. DAGB0_WRCLI9__URG_LOW_MASK
31945. DAGB0_WRCLI9__URG_LOW__SHIFT
31946. DAGB0_WRCLI9__VIRT_CHAN_MASK
31947. DAGB0_WRCLI9__VIRT_CHAN__SHIFT
31948. DAGB0_WRCLI_ASK_PENDING__BUSY_MASK
31949. DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT
31950. DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
31951. DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
31952. DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK
31953. DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
31954. DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK
31955. DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
31956. DAGB0_WRCLI_GO_PENDING__BUSY_MASK
31957. DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT
31958. DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK
31959. DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT
31960. DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK
31961. DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT
31962. DAGB0_WRCLI_OARB_PENDING__BUSY_MASK
31963. DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT
31964. DAGB0_WRCLI_OSD_PENDING__BUSY_MASK
31965. DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT
31966. DAGB0_WRCLI_TLB_PENDING__BUSY_MASK
31967. DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT
31968. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
31969. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
31970. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
31971. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
31972. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
31973. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
31974. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
31975. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
31976. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
31977. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
31978. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
31979. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
31980. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
31981. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
31982. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
31983. DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
31984. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
31985. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
31986. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
31987. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
31988. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
31989. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
31990. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
31991. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
31992. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
31993. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
31994. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
31995. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
31996. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
31997. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
31998. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
31999. DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
32000. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK
32001. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT
32002. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK
32003. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT
32004. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK
32005. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT
32006. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK
32007. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT
32008. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK
32009. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT
32010. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK
32011. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT
32012. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK
32013. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT
32014. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK
32015. DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT
32016. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK
32017. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT
32018. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK
32019. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT
32020. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK
32021. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT
32022. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK
32023. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT
32024. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK
32025. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT
32026. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK
32027. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT
32028. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK
32029. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT
32030. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK
32031. DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT
32032. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
32033. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
32034. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
32035. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
32036. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
32037. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
32038. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
32039. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
32040. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
32041. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
32042. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
32043. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
32044. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
32045. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
32046. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
32047. DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
32048. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
32049. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
32050. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
32051. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
32052. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
32053. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
32054. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
32055. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
32056. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
32057. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
32058. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
32059. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
32060. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
32061. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
32062. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
32063. DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
32064. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK
32065. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT
32066. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK
32067. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT
32068. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK
32069. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT
32070. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK
32071. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT
32072. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK
32073. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT
32074. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK
32075. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT
32076. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK
32077. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT
32078. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK
32079. DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT
32080. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK
32081. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT
32082. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK
32083. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT
32084. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK
32085. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT
32086. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK
32087. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT
32088. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK
32089. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT
32090. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK
32091. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT
32092. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK
32093. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT
32094. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK
32095. DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT
32096. DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK
32097. DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
32098. DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
32099. DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
32100. DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
32101. DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
32102. DAGB0_WR_ADDR_DAGB__WHOAMI_MASK
32103. DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT
32104. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
32105. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
32106. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
32107. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
32108. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
32109. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
32110. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
32111. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
32112. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
32113. DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
32114. DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
32115. DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
32116. DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
32117. DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
32118. DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
32119. DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
32120. DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
32121. DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
32122. DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
32123. DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
32124. DAGB0_WR_CNTL_MISC__HDP_CID_MASK
32125. DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT
32126. DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK
32127. DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
32128. DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
32129. DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
32130. DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
32131. DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
32132. DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
32133. DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
32134. DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK
32135. DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT
32136. DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
32137. DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
32138. DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
32139. DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
32140. DAGB0_WR_CNTL__IO_LEVEL_MASK
32141. DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
32142. DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
32143. DAGB0_WR_CNTL__IO_LEVEL__SHIFT
32144. DAGB0_WR_CNTL__SCLK_FREQ_MASK
32145. DAGB0_WR_CNTL__SCLK_FREQ__SHIFT
32146. DAGB0_WR_CNTL__SHARE_VC_NUM_MASK
32147. DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT
32148. DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK
32149. DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
32150. DAGB0_WR_CREDITS_FULL__FULL_MASK
32151. DAGB0_WR_CREDITS_FULL__FULL__SHIFT
32152. DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
32153. DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
32154. DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
32155. DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
32156. DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
32157. DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
32158. DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
32159. DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
32160. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
32161. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
32162. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
32163. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
32164. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
32165. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
32166. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
32167. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
32168. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
32169. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
32170. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
32171. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
32172. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
32173. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
32174. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
32175. DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
32176. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
32177. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
32178. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
32179. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
32180. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
32181. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
32182. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
32183. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
32184. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
32185. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
32186. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
32187. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
32188. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
32189. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
32190. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
32191. DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
32192. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK
32193. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT
32194. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK
32195. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT
32196. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK
32197. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT
32198. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK
32199. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT
32200. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK
32201. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT
32202. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK
32203. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT
32204. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK
32205. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT
32206. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK
32207. DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT
32208. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK
32209. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT
32210. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK
32211. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT
32212. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK
32213. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT
32214. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK
32215. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT
32216. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK
32217. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT
32218. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK
32219. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT
32220. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK
32221. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT
32222. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK
32223. DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT
32224. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
32225. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
32226. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
32227. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
32228. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
32229. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
32230. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
32231. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
32232. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
32233. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
32234. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
32235. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
32236. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
32237. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
32238. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
32239. DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
32240. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
32241. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
32242. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
32243. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
32244. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
32245. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
32246. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
32247. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
32248. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
32249. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
32250. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
32251. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
32252. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
32253. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
32254. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
32255. DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
32256. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK
32257. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT
32258. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK
32259. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT
32260. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK
32261. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT
32262. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK
32263. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT
32264. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK
32265. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT
32266. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK
32267. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT
32268. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK
32269. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT
32270. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK
32271. DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT
32272. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK
32273. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT
32274. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK
32275. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT
32276. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK
32277. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT
32278. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK
32279. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT
32280. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK
32281. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT
32282. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK
32283. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT
32284. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK
32285. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT
32286. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK
32287. DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT
32288. DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK
32289. DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
32290. DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
32291. DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
32292. DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
32293. DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
32294. DAGB0_WR_DATA_DAGB__WHOAMI_MASK
32295. DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT
32296. DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK
32297. DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT
32298. DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK
32299. DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT
32300. DAGB0_WR_GMI_CNTL__LEVEL_MASK
32301. DAGB0_WR_GMI_CNTL__LEVEL__SHIFT
32302. DAGB0_WR_GMI_CNTL__MAX_BURST_MASK
32303. DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT
32304. DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
32305. DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
32306. DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
32307. DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
32308. DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK
32309. DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
32310. DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
32311. DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
32312. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
32313. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
32314. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
32315. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
32316. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
32317. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
32318. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
32319. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
32320. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
32321. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
32322. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
32323. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
32324. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
32325. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
32326. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
32327. DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
32328. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
32329. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
32330. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
32331. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
32332. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
32333. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
32334. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
32335. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
32336. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
32337. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
32338. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
32339. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
32340. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
32341. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
32342. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
32343. DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
32344. DAGB0_WR_TLB_CREDIT__TLB0_MASK
32345. DAGB0_WR_TLB_CREDIT__TLB0__SHIFT
32346. DAGB0_WR_TLB_CREDIT__TLB1_MASK
32347. DAGB0_WR_TLB_CREDIT__TLB1__SHIFT
32348. DAGB0_WR_TLB_CREDIT__TLB2_MASK
32349. DAGB0_WR_TLB_CREDIT__TLB2__SHIFT
32350. DAGB0_WR_TLB_CREDIT__TLB3_MASK
32351. DAGB0_WR_TLB_CREDIT__TLB3__SHIFT
32352. DAGB0_WR_TLB_CREDIT__TLB4_MASK
32353. DAGB0_WR_TLB_CREDIT__TLB4__SHIFT
32354. DAGB0_WR_TLB_CREDIT__TLB5_MASK
32355. DAGB0_WR_TLB_CREDIT__TLB5__SHIFT
32356. DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK
32357. DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT
32358. DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
32359. DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
32360. DAGB0_WR_VC0_CNTL__MAX_BW_MASK
32361. DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT
32362. DAGB0_WR_VC0_CNTL__MAX_OSD_MASK
32363. DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT
32364. DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
32365. DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
32366. DAGB0_WR_VC0_CNTL__MIN_BW_MASK
32367. DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT
32368. DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
32369. DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
32370. DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK
32371. DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT
32372. DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK
32373. DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT
32374. DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
32375. DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
32376. DAGB0_WR_VC1_CNTL__MAX_BW_MASK
32377. DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT
32378. DAGB0_WR_VC1_CNTL__MAX_OSD_MASK
32379. DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT
32380. DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
32381. DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
32382. DAGB0_WR_VC1_CNTL__MIN_BW_MASK
32383. DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT
32384. DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
32385. DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
32386. DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK
32387. DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT
32388. DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK
32389. DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT
32390. DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
32391. DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
32392. DAGB0_WR_VC2_CNTL__MAX_BW_MASK
32393. DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT
32394. DAGB0_WR_VC2_CNTL__MAX_OSD_MASK
32395. DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT
32396. DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
32397. DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
32398. DAGB0_WR_VC2_CNTL__MIN_BW_MASK
32399. DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT
32400. DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
32401. DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
32402. DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK
32403. DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT
32404. DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK
32405. DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT
32406. DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
32407. DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
32408. DAGB0_WR_VC3_CNTL__MAX_BW_MASK
32409. DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT
32410. DAGB0_WR_VC3_CNTL__MAX_OSD_MASK
32411. DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT
32412. DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
32413. DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
32414. DAGB0_WR_VC3_CNTL__MIN_BW_MASK
32415. DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT
32416. DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
32417. DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
32418. DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK
32419. DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT
32420. DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK
32421. DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT
32422. DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
32423. DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
32424. DAGB0_WR_VC4_CNTL__MAX_BW_MASK
32425. DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT
32426. DAGB0_WR_VC4_CNTL__MAX_OSD_MASK
32427. DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT
32428. DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
32429. DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
32430. DAGB0_WR_VC4_CNTL__MIN_BW_MASK
32431. DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT
32432. DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
32433. DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
32434. DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK
32435. DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT
32436. DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK
32437. DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT
32438. DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
32439. DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
32440. DAGB0_WR_VC5_CNTL__MAX_BW_MASK
32441. DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT
32442. DAGB0_WR_VC5_CNTL__MAX_OSD_MASK
32443. DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT
32444. DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
32445. DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
32446. DAGB0_WR_VC5_CNTL__MIN_BW_MASK
32447. DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT
32448. DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
32449. DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
32450. DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK
32451. DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT
32452. DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK
32453. DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT
32454. DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
32455. DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
32456. DAGB0_WR_VC6_CNTL__MAX_BW_MASK
32457. DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT
32458. DAGB0_WR_VC6_CNTL__MAX_OSD_MASK
32459. DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT
32460. DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
32461. DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
32462. DAGB0_WR_VC6_CNTL__MIN_BW_MASK
32463. DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT
32464. DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
32465. DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
32466. DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK
32467. DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT
32468. DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK
32469. DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT
32470. DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
32471. DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
32472. DAGB0_WR_VC7_CNTL__MAX_BW_MASK
32473. DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT
32474. DAGB0_WR_VC7_CNTL__MAX_OSD_MASK
32475. DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT
32476. DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
32477. DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
32478. DAGB0_WR_VC7_CNTL__MIN_BW_MASK
32479. DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT
32480. DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
32481. DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
32482. DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK
32483. DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT
32484. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
32485. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
32486. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
32487. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
32488. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
32489. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
32490. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
32491. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
32492. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
32493. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
32494. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
32495. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
32496. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
32497. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
32498. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
32499. DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
32500. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
32501. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
32502. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
32503. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
32504. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
32505. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
32506. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
32507. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
32508. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
32509. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
32510. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
32511. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
32512. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
32513. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
32514. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
32515. DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
32516. DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
32517. DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
32518. DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
32519. DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
32520. DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
32521. DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
32522. DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK
32523. DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
32524. DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
32525. DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
32526. DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
32527. DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
32528. DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
32529. DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
32530. DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK
32531. DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
32532. DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
32533. DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
32534. DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK
32535. DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
32536. DAGB1_CNTL_MISC2__SWAP_CTL_MASK
32537. DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT
32538. DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK
32539. DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
32540. DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK
32541. DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
32542. DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK
32543. DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT
32544. DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
32545. DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
32546. DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK
32547. DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT
32548. DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK
32549. DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT
32550. DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK
32551. DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT
32552. DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK
32553. DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT
32554. DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK
32555. DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT
32556. DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK
32557. DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT
32558. DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK
32559. DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT
32560. DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK
32561. DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT
32562. DAGB1_DAGB_DLY__CLI_MASK
32563. DAGB1_DAGB_DLY__CLI__SHIFT
32564. DAGB1_DAGB_DLY__DLY_MASK
32565. DAGB1_DAGB_DLY__DLY__SHIFT
32566. DAGB1_DAGB_DLY__POS_MASK
32567. DAGB1_DAGB_DLY__POS__SHIFT
32568. DAGB1_FIFO_EMPTY__EMPTY_MASK
32569. DAGB1_FIFO_EMPTY__EMPTY__SHIFT
32570. DAGB1_FIFO_FULL__FULL_MASK
32571. DAGB1_FIFO_FULL__FULL__SHIFT
32572. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
32573. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
32574. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
32575. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
32576. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
32577. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
32578. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
32579. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
32580. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
32581. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
32582. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
32583. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
32584. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
32585. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
32586. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
32587. DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
32588. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
32589. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
32590. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
32591. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
32592. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
32593. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
32594. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
32595. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
32596. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
32597. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
32598. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
32599. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
32600. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
32601. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
32602. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
32603. DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
32604. DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK
32605. DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT
32606. DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK
32607. DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT
32608. DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK
32609. DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
32610. DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
32611. DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
32612. DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK
32613. DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
32614. DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK
32615. DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT
32616. DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK
32617. DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT
32618. DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK
32619. DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
32620. DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
32621. DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
32622. DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK
32623. DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
32624. DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK
32625. DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT
32626. DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK
32627. DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT
32628. DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK
32629. DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
32630. DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
32631. DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
32632. DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK
32633. DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
32634. DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK
32635. DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
32636. DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK
32637. DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT
32638. DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK
32639. DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT
32640. DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
32641. DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
32642. DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
32643. DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
32644. DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
32645. DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
32646. DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
32647. DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
32648. DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
32649. DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
32650. DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
32651. DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
32652. DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK
32653. DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT
32654. DAGB1_RDCLI0__MAX_BW_ENABLE_MASK
32655. DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT
32656. DAGB1_RDCLI0__MAX_BW_MASK
32657. DAGB1_RDCLI0__MAX_BW__SHIFT
32658. DAGB1_RDCLI0__MAX_OSD_MASK
32659. DAGB1_RDCLI0__MAX_OSD__SHIFT
32660. DAGB1_RDCLI0__MIN_BW_ENABLE_MASK
32661. DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT
32662. DAGB1_RDCLI0__MIN_BW_MASK
32663. DAGB1_RDCLI0__MIN_BW__SHIFT
32664. DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK
32665. DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
32666. DAGB1_RDCLI0__URG_HIGH_MASK
32667. DAGB1_RDCLI0__URG_HIGH__SHIFT
32668. DAGB1_RDCLI0__URG_LOW_MASK
32669. DAGB1_RDCLI0__URG_LOW__SHIFT
32670. DAGB1_RDCLI0__VIRT_CHAN_MASK
32671. DAGB1_RDCLI0__VIRT_CHAN__SHIFT
32672. DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK
32673. DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT
32674. DAGB1_RDCLI10__MAX_BW_ENABLE_MASK
32675. DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT
32676. DAGB1_RDCLI10__MAX_BW_MASK
32677. DAGB1_RDCLI10__MAX_BW__SHIFT
32678. DAGB1_RDCLI10__MAX_OSD_MASK
32679. DAGB1_RDCLI10__MAX_OSD__SHIFT
32680. DAGB1_RDCLI10__MIN_BW_ENABLE_MASK
32681. DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT
32682. DAGB1_RDCLI10__MIN_BW_MASK
32683. DAGB1_RDCLI10__MIN_BW__SHIFT
32684. DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK
32685. DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
32686. DAGB1_RDCLI10__URG_HIGH_MASK
32687. DAGB1_RDCLI10__URG_HIGH__SHIFT
32688. DAGB1_RDCLI10__URG_LOW_MASK
32689. DAGB1_RDCLI10__URG_LOW__SHIFT
32690. DAGB1_RDCLI10__VIRT_CHAN_MASK
32691. DAGB1_RDCLI10__VIRT_CHAN__SHIFT
32692. DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK
32693. DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT
32694. DAGB1_RDCLI11__MAX_BW_ENABLE_MASK
32695. DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT
32696. DAGB1_RDCLI11__MAX_BW_MASK
32697. DAGB1_RDCLI11__MAX_BW__SHIFT
32698. DAGB1_RDCLI11__MAX_OSD_MASK
32699. DAGB1_RDCLI11__MAX_OSD__SHIFT
32700. DAGB1_RDCLI11__MIN_BW_ENABLE_MASK
32701. DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT
32702. DAGB1_RDCLI11__MIN_BW_MASK
32703. DAGB1_RDCLI11__MIN_BW__SHIFT
32704. DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK
32705. DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
32706. DAGB1_RDCLI11__URG_HIGH_MASK
32707. DAGB1_RDCLI11__URG_HIGH__SHIFT
32708. DAGB1_RDCLI11__URG_LOW_MASK
32709. DAGB1_RDCLI11__URG_LOW__SHIFT
32710. DAGB1_RDCLI11__VIRT_CHAN_MASK
32711. DAGB1_RDCLI11__VIRT_CHAN__SHIFT
32712. DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK
32713. DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT
32714. DAGB1_RDCLI12__MAX_BW_ENABLE_MASK
32715. DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT
32716. DAGB1_RDCLI12__MAX_BW_MASK
32717. DAGB1_RDCLI12__MAX_BW__SHIFT
32718. DAGB1_RDCLI12__MAX_OSD_MASK
32719. DAGB1_RDCLI12__MAX_OSD__SHIFT
32720. DAGB1_RDCLI12__MIN_BW_ENABLE_MASK
32721. DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT
32722. DAGB1_RDCLI12__MIN_BW_MASK
32723. DAGB1_RDCLI12__MIN_BW__SHIFT
32724. DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK
32725. DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
32726. DAGB1_RDCLI12__URG_HIGH_MASK
32727. DAGB1_RDCLI12__URG_HIGH__SHIFT
32728. DAGB1_RDCLI12__URG_LOW_MASK
32729. DAGB1_RDCLI12__URG_LOW__SHIFT
32730. DAGB1_RDCLI12__VIRT_CHAN_MASK
32731. DAGB1_RDCLI12__VIRT_CHAN__SHIFT
32732. DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK
32733. DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT
32734. DAGB1_RDCLI13__MAX_BW_ENABLE_MASK
32735. DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT
32736. DAGB1_RDCLI13__MAX_BW_MASK
32737. DAGB1_RDCLI13__MAX_BW__SHIFT
32738. DAGB1_RDCLI13__MAX_OSD_MASK
32739. DAGB1_RDCLI13__MAX_OSD__SHIFT
32740. DAGB1_RDCLI13__MIN_BW_ENABLE_MASK
32741. DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT
32742. DAGB1_RDCLI13__MIN_BW_MASK
32743. DAGB1_RDCLI13__MIN_BW__SHIFT
32744. DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK
32745. DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
32746. DAGB1_RDCLI13__URG_HIGH_MASK
32747. DAGB1_RDCLI13__URG_HIGH__SHIFT
32748. DAGB1_RDCLI13__URG_LOW_MASK
32749. DAGB1_RDCLI13__URG_LOW__SHIFT
32750. DAGB1_RDCLI13__VIRT_CHAN_MASK
32751. DAGB1_RDCLI13__VIRT_CHAN__SHIFT
32752. DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK
32753. DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT
32754. DAGB1_RDCLI14__MAX_BW_ENABLE_MASK
32755. DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT
32756. DAGB1_RDCLI14__MAX_BW_MASK
32757. DAGB1_RDCLI14__MAX_BW__SHIFT
32758. DAGB1_RDCLI14__MAX_OSD_MASK
32759. DAGB1_RDCLI14__MAX_OSD__SHIFT
32760. DAGB1_RDCLI14__MIN_BW_ENABLE_MASK
32761. DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT
32762. DAGB1_RDCLI14__MIN_BW_MASK
32763. DAGB1_RDCLI14__MIN_BW__SHIFT
32764. DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK
32765. DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
32766. DAGB1_RDCLI14__URG_HIGH_MASK
32767. DAGB1_RDCLI14__URG_HIGH__SHIFT
32768. DAGB1_RDCLI14__URG_LOW_MASK
32769. DAGB1_RDCLI14__URG_LOW__SHIFT
32770. DAGB1_RDCLI14__VIRT_CHAN_MASK
32771. DAGB1_RDCLI14__VIRT_CHAN__SHIFT
32772. DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK
32773. DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT
32774. DAGB1_RDCLI15__MAX_BW_ENABLE_MASK
32775. DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT
32776. DAGB1_RDCLI15__MAX_BW_MASK
32777. DAGB1_RDCLI15__MAX_BW__SHIFT
32778. DAGB1_RDCLI15__MAX_OSD_MASK
32779. DAGB1_RDCLI15__MAX_OSD__SHIFT
32780. DAGB1_RDCLI15__MIN_BW_ENABLE_MASK
32781. DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT
32782. DAGB1_RDCLI15__MIN_BW_MASK
32783. DAGB1_RDCLI15__MIN_BW__SHIFT
32784. DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK
32785. DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
32786. DAGB1_RDCLI15__URG_HIGH_MASK
32787. DAGB1_RDCLI15__URG_HIGH__SHIFT
32788. DAGB1_RDCLI15__URG_LOW_MASK
32789. DAGB1_RDCLI15__URG_LOW__SHIFT
32790. DAGB1_RDCLI15__VIRT_CHAN_MASK
32791. DAGB1_RDCLI15__VIRT_CHAN__SHIFT
32792. DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK
32793. DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT
32794. DAGB1_RDCLI1__MAX_BW_ENABLE_MASK
32795. DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT
32796. DAGB1_RDCLI1__MAX_BW_MASK
32797. DAGB1_RDCLI1__MAX_BW__SHIFT
32798. DAGB1_RDCLI1__MAX_OSD_MASK
32799. DAGB1_RDCLI1__MAX_OSD__SHIFT
32800. DAGB1_RDCLI1__MIN_BW_ENABLE_MASK
32801. DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT
32802. DAGB1_RDCLI1__MIN_BW_MASK
32803. DAGB1_RDCLI1__MIN_BW__SHIFT
32804. DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK
32805. DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
32806. DAGB1_RDCLI1__URG_HIGH_MASK
32807. DAGB1_RDCLI1__URG_HIGH__SHIFT
32808. DAGB1_RDCLI1__URG_LOW_MASK
32809. DAGB1_RDCLI1__URG_LOW__SHIFT
32810. DAGB1_RDCLI1__VIRT_CHAN_MASK
32811. DAGB1_RDCLI1__VIRT_CHAN__SHIFT
32812. DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK
32813. DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT
32814. DAGB1_RDCLI2__MAX_BW_ENABLE_MASK
32815. DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT
32816. DAGB1_RDCLI2__MAX_BW_MASK
32817. DAGB1_RDCLI2__MAX_BW__SHIFT
32818. DAGB1_RDCLI2__MAX_OSD_MASK
32819. DAGB1_RDCLI2__MAX_OSD__SHIFT
32820. DAGB1_RDCLI2__MIN_BW_ENABLE_MASK
32821. DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT
32822. DAGB1_RDCLI2__MIN_BW_MASK
32823. DAGB1_RDCLI2__MIN_BW__SHIFT
32824. DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK
32825. DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
32826. DAGB1_RDCLI2__URG_HIGH_MASK
32827. DAGB1_RDCLI2__URG_HIGH__SHIFT
32828. DAGB1_RDCLI2__URG_LOW_MASK
32829. DAGB1_RDCLI2__URG_LOW__SHIFT
32830. DAGB1_RDCLI2__VIRT_CHAN_MASK
32831. DAGB1_RDCLI2__VIRT_CHAN__SHIFT
32832. DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK
32833. DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT
32834. DAGB1_RDCLI3__MAX_BW_ENABLE_MASK
32835. DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT
32836. DAGB1_RDCLI3__MAX_BW_MASK
32837. DAGB1_RDCLI3__MAX_BW__SHIFT
32838. DAGB1_RDCLI3__MAX_OSD_MASK
32839. DAGB1_RDCLI3__MAX_OSD__SHIFT
32840. DAGB1_RDCLI3__MIN_BW_ENABLE_MASK
32841. DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT
32842. DAGB1_RDCLI3__MIN_BW_MASK
32843. DAGB1_RDCLI3__MIN_BW__SHIFT
32844. DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK
32845. DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
32846. DAGB1_RDCLI3__URG_HIGH_MASK
32847. DAGB1_RDCLI3__URG_HIGH__SHIFT
32848. DAGB1_RDCLI3__URG_LOW_MASK
32849. DAGB1_RDCLI3__URG_LOW__SHIFT
32850. DAGB1_RDCLI3__VIRT_CHAN_MASK
32851. DAGB1_RDCLI3__VIRT_CHAN__SHIFT
32852. DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK
32853. DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT
32854. DAGB1_RDCLI4__MAX_BW_ENABLE_MASK
32855. DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT
32856. DAGB1_RDCLI4__MAX_BW_MASK
32857. DAGB1_RDCLI4__MAX_BW__SHIFT
32858. DAGB1_RDCLI4__MAX_OSD_MASK
32859. DAGB1_RDCLI4__MAX_OSD__SHIFT
32860. DAGB1_RDCLI4__MIN_BW_ENABLE_MASK
32861. DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT
32862. DAGB1_RDCLI4__MIN_BW_MASK
32863. DAGB1_RDCLI4__MIN_BW__SHIFT
32864. DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK
32865. DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
32866. DAGB1_RDCLI4__URG_HIGH_MASK
32867. DAGB1_RDCLI4__URG_HIGH__SHIFT
32868. DAGB1_RDCLI4__URG_LOW_MASK
32869. DAGB1_RDCLI4__URG_LOW__SHIFT
32870. DAGB1_RDCLI4__VIRT_CHAN_MASK
32871. DAGB1_RDCLI4__VIRT_CHAN__SHIFT
32872. DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK
32873. DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT
32874. DAGB1_RDCLI5__MAX_BW_ENABLE_MASK
32875. DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT
32876. DAGB1_RDCLI5__MAX_BW_MASK
32877. DAGB1_RDCLI5__MAX_BW__SHIFT
32878. DAGB1_RDCLI5__MAX_OSD_MASK
32879. DAGB1_RDCLI5__MAX_OSD__SHIFT
32880. DAGB1_RDCLI5__MIN_BW_ENABLE_MASK
32881. DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT
32882. DAGB1_RDCLI5__MIN_BW_MASK
32883. DAGB1_RDCLI5__MIN_BW__SHIFT
32884. DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK
32885. DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
32886. DAGB1_RDCLI5__URG_HIGH_MASK
32887. DAGB1_RDCLI5__URG_HIGH__SHIFT
32888. DAGB1_RDCLI5__URG_LOW_MASK
32889. DAGB1_RDCLI5__URG_LOW__SHIFT
32890. DAGB1_RDCLI5__VIRT_CHAN_MASK
32891. DAGB1_RDCLI5__VIRT_CHAN__SHIFT
32892. DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK
32893. DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT
32894. DAGB1_RDCLI6__MAX_BW_ENABLE_MASK
32895. DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT
32896. DAGB1_RDCLI6__MAX_BW_MASK
32897. DAGB1_RDCLI6__MAX_BW__SHIFT
32898. DAGB1_RDCLI6__MAX_OSD_MASK
32899. DAGB1_RDCLI6__MAX_OSD__SHIFT
32900. DAGB1_RDCLI6__MIN_BW_ENABLE_MASK
32901. DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT
32902. DAGB1_RDCLI6__MIN_BW_MASK
32903. DAGB1_RDCLI6__MIN_BW__SHIFT
32904. DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK
32905. DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
32906. DAGB1_RDCLI6__URG_HIGH_MASK
32907. DAGB1_RDCLI6__URG_HIGH__SHIFT
32908. DAGB1_RDCLI6__URG_LOW_MASK
32909. DAGB1_RDCLI6__URG_LOW__SHIFT
32910. DAGB1_RDCLI6__VIRT_CHAN_MASK
32911. DAGB1_RDCLI6__VIRT_CHAN__SHIFT
32912. DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK
32913. DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT
32914. DAGB1_RDCLI7__MAX_BW_ENABLE_MASK
32915. DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT
32916. DAGB1_RDCLI7__MAX_BW_MASK
32917. DAGB1_RDCLI7__MAX_BW__SHIFT
32918. DAGB1_RDCLI7__MAX_OSD_MASK
32919. DAGB1_RDCLI7__MAX_OSD__SHIFT
32920. DAGB1_RDCLI7__MIN_BW_ENABLE_MASK
32921. DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT
32922. DAGB1_RDCLI7__MIN_BW_MASK
32923. DAGB1_RDCLI7__MIN_BW__SHIFT
32924. DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK
32925. DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
32926. DAGB1_RDCLI7__URG_HIGH_MASK
32927. DAGB1_RDCLI7__URG_HIGH__SHIFT
32928. DAGB1_RDCLI7__URG_LOW_MASK
32929. DAGB1_RDCLI7__URG_LOW__SHIFT
32930. DAGB1_RDCLI7__VIRT_CHAN_MASK
32931. DAGB1_RDCLI7__VIRT_CHAN__SHIFT
32932. DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK
32933. DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT
32934. DAGB1_RDCLI8__MAX_BW_ENABLE_MASK
32935. DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT
32936. DAGB1_RDCLI8__MAX_BW_MASK
32937. DAGB1_RDCLI8__MAX_BW__SHIFT
32938. DAGB1_RDCLI8__MAX_OSD_MASK
32939. DAGB1_RDCLI8__MAX_OSD__SHIFT
32940. DAGB1_RDCLI8__MIN_BW_ENABLE_MASK
32941. DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT
32942. DAGB1_RDCLI8__MIN_BW_MASK
32943. DAGB1_RDCLI8__MIN_BW__SHIFT
32944. DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK
32945. DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
32946. DAGB1_RDCLI8__URG_HIGH_MASK
32947. DAGB1_RDCLI8__URG_HIGH__SHIFT
32948. DAGB1_RDCLI8__URG_LOW_MASK
32949. DAGB1_RDCLI8__URG_LOW__SHIFT
32950. DAGB1_RDCLI8__VIRT_CHAN_MASK
32951. DAGB1_RDCLI8__VIRT_CHAN__SHIFT
32952. DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK
32953. DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT
32954. DAGB1_RDCLI9__MAX_BW_ENABLE_MASK
32955. DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT
32956. DAGB1_RDCLI9__MAX_BW_MASK
32957. DAGB1_RDCLI9__MAX_BW__SHIFT
32958. DAGB1_RDCLI9__MAX_OSD_MASK
32959. DAGB1_RDCLI9__MAX_OSD__SHIFT
32960. DAGB1_RDCLI9__MIN_BW_ENABLE_MASK
32961. DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT
32962. DAGB1_RDCLI9__MIN_BW_MASK
32963. DAGB1_RDCLI9__MIN_BW__SHIFT
32964. DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK
32965. DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
32966. DAGB1_RDCLI9__URG_HIGH_MASK
32967. DAGB1_RDCLI9__URG_HIGH__SHIFT
32968. DAGB1_RDCLI9__URG_LOW_MASK
32969. DAGB1_RDCLI9__URG_LOW__SHIFT
32970. DAGB1_RDCLI9__VIRT_CHAN_MASK
32971. DAGB1_RDCLI9__VIRT_CHAN__SHIFT
32972. DAGB1_RDCLI_ASK_PENDING__BUSY_MASK
32973. DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT
32974. DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK
32975. DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
32976. DAGB1_RDCLI_GO_PENDING__BUSY_MASK
32977. DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT
32978. DAGB1_RDCLI_OARB_PENDING__BUSY_MASK
32979. DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT
32980. DAGB1_RDCLI_OSD_PENDING__BUSY_MASK
32981. DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT
32982. DAGB1_RDCLI_TLB_PENDING__BUSY_MASK
32983. DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT
32984. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
32985. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
32986. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
32987. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
32988. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
32989. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
32990. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
32991. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
32992. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
32993. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
32994. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
32995. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
32996. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
32997. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
32998. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
32999. DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
33000. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
33001. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
33002. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
33003. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
33004. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
33005. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
33006. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
33007. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
33008. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
33009. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
33010. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
33011. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
33012. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
33013. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
33014. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
33015. DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
33016. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
33017. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
33018. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
33019. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
33020. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
33021. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
33022. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
33023. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
33024. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
33025. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
33026. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
33027. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
33028. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
33029. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
33030. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
33031. DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
33032. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
33033. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
33034. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
33035. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
33036. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
33037. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
33038. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
33039. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
33040. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
33041. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
33042. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
33043. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
33044. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
33045. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
33046. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
33047. DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
33048. DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK
33049. DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
33050. DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
33051. DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
33052. DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
33053. DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
33054. DAGB1_RD_ADDR_DAGB__WHOAMI_MASK
33055. DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT
33056. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
33057. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
33058. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
33059. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
33060. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
33061. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
33062. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
33063. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
33064. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
33065. DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
33066. DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
33067. DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
33068. DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
33069. DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
33070. DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
33071. DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
33072. DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
33073. DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
33074. DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
33075. DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
33076. DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK
33077. DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
33078. DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
33079. DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
33080. DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
33081. DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
33082. DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
33083. DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
33084. DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK
33085. DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT
33086. DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
33087. DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
33088. DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
33089. DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
33090. DAGB1_RD_CNTL__IO_LEVEL_MASK
33091. DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
33092. DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
33093. DAGB1_RD_CNTL__IO_LEVEL__SHIFT
33094. DAGB1_RD_CNTL__SCLK_FREQ_MASK
33095. DAGB1_RD_CNTL__SCLK_FREQ__SHIFT
33096. DAGB1_RD_CNTL__SHARE_VC_NUM_MASK
33097. DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT
33098. DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK
33099. DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
33100. DAGB1_RD_CREDITS_FULL__FULL_MASK
33101. DAGB1_RD_CREDITS_FULL__FULL__SHIFT
33102. DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK
33103. DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT
33104. DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK
33105. DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT
33106. DAGB1_RD_GMI_CNTL__LEVEL_MASK
33107. DAGB1_RD_GMI_CNTL__LEVEL__SHIFT
33108. DAGB1_RD_GMI_CNTL__MAX_BURST_MASK
33109. DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT
33110. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
33111. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
33112. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
33113. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
33114. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
33115. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
33116. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
33117. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
33118. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
33119. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
33120. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
33121. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
33122. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
33123. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
33124. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
33125. DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
33126. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
33127. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
33128. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
33129. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
33130. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
33131. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
33132. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
33133. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
33134. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
33135. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
33136. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
33137. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
33138. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
33139. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
33140. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
33141. DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
33142. DAGB1_RD_TLB_CREDIT__TLB0_MASK
33143. DAGB1_RD_TLB_CREDIT__TLB0__SHIFT
33144. DAGB1_RD_TLB_CREDIT__TLB1_MASK
33145. DAGB1_RD_TLB_CREDIT__TLB1__SHIFT
33146. DAGB1_RD_TLB_CREDIT__TLB2_MASK
33147. DAGB1_RD_TLB_CREDIT__TLB2__SHIFT
33148. DAGB1_RD_TLB_CREDIT__TLB3_MASK
33149. DAGB1_RD_TLB_CREDIT__TLB3__SHIFT
33150. DAGB1_RD_TLB_CREDIT__TLB4_MASK
33151. DAGB1_RD_TLB_CREDIT__TLB4__SHIFT
33152. DAGB1_RD_TLB_CREDIT__TLB5_MASK
33153. DAGB1_RD_TLB_CREDIT__TLB5__SHIFT
33154. DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK
33155. DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT
33156. DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
33157. DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
33158. DAGB1_RD_VC0_CNTL__MAX_BW_MASK
33159. DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT
33160. DAGB1_RD_VC0_CNTL__MAX_OSD_MASK
33161. DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT
33162. DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
33163. DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
33164. DAGB1_RD_VC0_CNTL__MIN_BW_MASK
33165. DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT
33166. DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
33167. DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
33168. DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK
33169. DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT
33170. DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK
33171. DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT
33172. DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
33173. DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
33174. DAGB1_RD_VC1_CNTL__MAX_BW_MASK
33175. DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT
33176. DAGB1_RD_VC1_CNTL__MAX_OSD_MASK
33177. DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT
33178. DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
33179. DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
33180. DAGB1_RD_VC1_CNTL__MIN_BW_MASK
33181. DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT
33182. DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
33183. DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
33184. DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK
33185. DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT
33186. DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK
33187. DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT
33188. DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
33189. DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
33190. DAGB1_RD_VC2_CNTL__MAX_BW_MASK
33191. DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT
33192. DAGB1_RD_VC2_CNTL__MAX_OSD_MASK
33193. DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT
33194. DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
33195. DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
33196. DAGB1_RD_VC2_CNTL__MIN_BW_MASK
33197. DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT
33198. DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
33199. DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
33200. DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK
33201. DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT
33202. DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK
33203. DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT
33204. DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
33205. DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
33206. DAGB1_RD_VC3_CNTL__MAX_BW_MASK
33207. DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT
33208. DAGB1_RD_VC3_CNTL__MAX_OSD_MASK
33209. DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT
33210. DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
33211. DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
33212. DAGB1_RD_VC3_CNTL__MIN_BW_MASK
33213. DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT
33214. DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
33215. DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
33216. DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK
33217. DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT
33218. DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK
33219. DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT
33220. DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
33221. DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
33222. DAGB1_RD_VC4_CNTL__MAX_BW_MASK
33223. DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT
33224. DAGB1_RD_VC4_CNTL__MAX_OSD_MASK
33225. DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT
33226. DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
33227. DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
33228. DAGB1_RD_VC4_CNTL__MIN_BW_MASK
33229. DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT
33230. DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
33231. DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
33232. DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK
33233. DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT
33234. DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK
33235. DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT
33236. DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
33237. DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
33238. DAGB1_RD_VC5_CNTL__MAX_BW_MASK
33239. DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT
33240. DAGB1_RD_VC5_CNTL__MAX_OSD_MASK
33241. DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT
33242. DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
33243. DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
33244. DAGB1_RD_VC5_CNTL__MIN_BW_MASK
33245. DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT
33246. DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
33247. DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
33248. DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK
33249. DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT
33250. DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK
33251. DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT
33252. DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
33253. DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
33254. DAGB1_RD_VC6_CNTL__MAX_BW_MASK
33255. DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT
33256. DAGB1_RD_VC6_CNTL__MAX_OSD_MASK
33257. DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT
33258. DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
33259. DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
33260. DAGB1_RD_VC6_CNTL__MIN_BW_MASK
33261. DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT
33262. DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
33263. DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
33264. DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK
33265. DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT
33266. DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK
33267. DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT
33268. DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
33269. DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
33270. DAGB1_RD_VC7_CNTL__MAX_BW_MASK
33271. DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT
33272. DAGB1_RD_VC7_CNTL__MAX_OSD_MASK
33273. DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT
33274. DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
33275. DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
33276. DAGB1_RD_VC7_CNTL__MIN_BW_MASK
33277. DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT
33278. DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
33279. DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
33280. DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK
33281. DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT
33282. DAGB1_RESERVE0__RESERVE_MASK
33283. DAGB1_RESERVE0__RESERVE__SHIFT
33284. DAGB1_RESERVE10__RESERVE_MASK
33285. DAGB1_RESERVE10__RESERVE__SHIFT
33286. DAGB1_RESERVE11__RESERVE_MASK
33287. DAGB1_RESERVE11__RESERVE__SHIFT
33288. DAGB1_RESERVE12__RESERVE_MASK
33289. DAGB1_RESERVE12__RESERVE__SHIFT
33290. DAGB1_RESERVE13__RESERVE_MASK
33291. DAGB1_RESERVE13__RESERVE__SHIFT
33292. DAGB1_RESERVE14__RESERVE_MASK
33293. DAGB1_RESERVE14__RESERVE__SHIFT
33294. DAGB1_RESERVE15__RESERVE_MASK
33295. DAGB1_RESERVE15__RESERVE__SHIFT
33296. DAGB1_RESERVE16__RESERVE_MASK
33297. DAGB1_RESERVE16__RESERVE__SHIFT
33298. DAGB1_RESERVE17__RESERVE_MASK
33299. DAGB1_RESERVE17__RESERVE__SHIFT
33300. DAGB1_RESERVE1__RESERVE_MASK
33301. DAGB1_RESERVE1__RESERVE__SHIFT
33302. DAGB1_RESERVE2__RESERVE_MASK
33303. DAGB1_RESERVE2__RESERVE__SHIFT
33304. DAGB1_RESERVE3__RESERVE_MASK
33305. DAGB1_RESERVE3__RESERVE__SHIFT
33306. DAGB1_RESERVE4__RESERVE_MASK
33307. DAGB1_RESERVE4__RESERVE__SHIFT
33308. DAGB1_RESERVE5__RESERVE_MASK
33309. DAGB1_RESERVE5__RESERVE__SHIFT
33310. DAGB1_RESERVE6__RESERVE_MASK
33311. DAGB1_RESERVE6__RESERVE__SHIFT
33312. DAGB1_RESERVE7__RESERVE_MASK
33313. DAGB1_RESERVE7__RESERVE__SHIFT
33314. DAGB1_RESERVE8__RESERVE_MASK
33315. DAGB1_RESERVE8__RESERVE__SHIFT
33316. DAGB1_RESERVE9__RESERVE_MASK
33317. DAGB1_RESERVE9__RESERVE__SHIFT
33318. DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK
33319. DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT
33320. DAGB1_WRCLI0__MAX_BW_ENABLE_MASK
33321. DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT
33322. DAGB1_WRCLI0__MAX_BW_MASK
33323. DAGB1_WRCLI0__MAX_BW__SHIFT
33324. DAGB1_WRCLI0__MAX_OSD_MASK
33325. DAGB1_WRCLI0__MAX_OSD__SHIFT
33326. DAGB1_WRCLI0__MIN_BW_ENABLE_MASK
33327. DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT
33328. DAGB1_WRCLI0__MIN_BW_MASK
33329. DAGB1_WRCLI0__MIN_BW__SHIFT
33330. DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK
33331. DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
33332. DAGB1_WRCLI0__URG_HIGH_MASK
33333. DAGB1_WRCLI0__URG_HIGH__SHIFT
33334. DAGB1_WRCLI0__URG_LOW_MASK
33335. DAGB1_WRCLI0__URG_LOW__SHIFT
33336. DAGB1_WRCLI0__VIRT_CHAN_MASK
33337. DAGB1_WRCLI0__VIRT_CHAN__SHIFT
33338. DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK
33339. DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT
33340. DAGB1_WRCLI10__MAX_BW_ENABLE_MASK
33341. DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT
33342. DAGB1_WRCLI10__MAX_BW_MASK
33343. DAGB1_WRCLI10__MAX_BW__SHIFT
33344. DAGB1_WRCLI10__MAX_OSD_MASK
33345. DAGB1_WRCLI10__MAX_OSD__SHIFT
33346. DAGB1_WRCLI10__MIN_BW_ENABLE_MASK
33347. DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT
33348. DAGB1_WRCLI10__MIN_BW_MASK
33349. DAGB1_WRCLI10__MIN_BW__SHIFT
33350. DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK
33351. DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
33352. DAGB1_WRCLI10__URG_HIGH_MASK
33353. DAGB1_WRCLI10__URG_HIGH__SHIFT
33354. DAGB1_WRCLI10__URG_LOW_MASK
33355. DAGB1_WRCLI10__URG_LOW__SHIFT
33356. DAGB1_WRCLI10__VIRT_CHAN_MASK
33357. DAGB1_WRCLI10__VIRT_CHAN__SHIFT
33358. DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK
33359. DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT
33360. DAGB1_WRCLI11__MAX_BW_ENABLE_MASK
33361. DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT
33362. DAGB1_WRCLI11__MAX_BW_MASK
33363. DAGB1_WRCLI11__MAX_BW__SHIFT
33364. DAGB1_WRCLI11__MAX_OSD_MASK
33365. DAGB1_WRCLI11__MAX_OSD__SHIFT
33366. DAGB1_WRCLI11__MIN_BW_ENABLE_MASK
33367. DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT
33368. DAGB1_WRCLI11__MIN_BW_MASK
33369. DAGB1_WRCLI11__MIN_BW__SHIFT
33370. DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK
33371. DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
33372. DAGB1_WRCLI11__URG_HIGH_MASK
33373. DAGB1_WRCLI11__URG_HIGH__SHIFT
33374. DAGB1_WRCLI11__URG_LOW_MASK
33375. DAGB1_WRCLI11__URG_LOW__SHIFT
33376. DAGB1_WRCLI11__VIRT_CHAN_MASK
33377. DAGB1_WRCLI11__VIRT_CHAN__SHIFT
33378. DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK
33379. DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT
33380. DAGB1_WRCLI12__MAX_BW_ENABLE_MASK
33381. DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT
33382. DAGB1_WRCLI12__MAX_BW_MASK
33383. DAGB1_WRCLI12__MAX_BW__SHIFT
33384. DAGB1_WRCLI12__MAX_OSD_MASK
33385. DAGB1_WRCLI12__MAX_OSD__SHIFT
33386. DAGB1_WRCLI12__MIN_BW_ENABLE_MASK
33387. DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT
33388. DAGB1_WRCLI12__MIN_BW_MASK
33389. DAGB1_WRCLI12__MIN_BW__SHIFT
33390. DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK
33391. DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
33392. DAGB1_WRCLI12__URG_HIGH_MASK
33393. DAGB1_WRCLI12__URG_HIGH__SHIFT
33394. DAGB1_WRCLI12__URG_LOW_MASK
33395. DAGB1_WRCLI12__URG_LOW__SHIFT
33396. DAGB1_WRCLI12__VIRT_CHAN_MASK
33397. DAGB1_WRCLI12__VIRT_CHAN__SHIFT
33398. DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK
33399. DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT
33400. DAGB1_WRCLI13__MAX_BW_ENABLE_MASK
33401. DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT
33402. DAGB1_WRCLI13__MAX_BW_MASK
33403. DAGB1_WRCLI13__MAX_BW__SHIFT
33404. DAGB1_WRCLI13__MAX_OSD_MASK
33405. DAGB1_WRCLI13__MAX_OSD__SHIFT
33406. DAGB1_WRCLI13__MIN_BW_ENABLE_MASK
33407. DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT
33408. DAGB1_WRCLI13__MIN_BW_MASK
33409. DAGB1_WRCLI13__MIN_BW__SHIFT
33410. DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK
33411. DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
33412. DAGB1_WRCLI13__URG_HIGH_MASK
33413. DAGB1_WRCLI13__URG_HIGH__SHIFT
33414. DAGB1_WRCLI13__URG_LOW_MASK
33415. DAGB1_WRCLI13__URG_LOW__SHIFT
33416. DAGB1_WRCLI13__VIRT_CHAN_MASK
33417. DAGB1_WRCLI13__VIRT_CHAN__SHIFT
33418. DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK
33419. DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT
33420. DAGB1_WRCLI14__MAX_BW_ENABLE_MASK
33421. DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT
33422. DAGB1_WRCLI14__MAX_BW_MASK
33423. DAGB1_WRCLI14__MAX_BW__SHIFT
33424. DAGB1_WRCLI14__MAX_OSD_MASK
33425. DAGB1_WRCLI14__MAX_OSD__SHIFT
33426. DAGB1_WRCLI14__MIN_BW_ENABLE_MASK
33427. DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT
33428. DAGB1_WRCLI14__MIN_BW_MASK
33429. DAGB1_WRCLI14__MIN_BW__SHIFT
33430. DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK
33431. DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
33432. DAGB1_WRCLI14__URG_HIGH_MASK
33433. DAGB1_WRCLI14__URG_HIGH__SHIFT
33434. DAGB1_WRCLI14__URG_LOW_MASK
33435. DAGB1_WRCLI14__URG_LOW__SHIFT
33436. DAGB1_WRCLI14__VIRT_CHAN_MASK
33437. DAGB1_WRCLI14__VIRT_CHAN__SHIFT
33438. DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK
33439. DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT
33440. DAGB1_WRCLI15__MAX_BW_ENABLE_MASK
33441. DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT
33442. DAGB1_WRCLI15__MAX_BW_MASK
33443. DAGB1_WRCLI15__MAX_BW__SHIFT
33444. DAGB1_WRCLI15__MAX_OSD_MASK
33445. DAGB1_WRCLI15__MAX_OSD__SHIFT
33446. DAGB1_WRCLI15__MIN_BW_ENABLE_MASK
33447. DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT
33448. DAGB1_WRCLI15__MIN_BW_MASK
33449. DAGB1_WRCLI15__MIN_BW__SHIFT
33450. DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK
33451. DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
33452. DAGB1_WRCLI15__URG_HIGH_MASK
33453. DAGB1_WRCLI15__URG_HIGH__SHIFT
33454. DAGB1_WRCLI15__URG_LOW_MASK
33455. DAGB1_WRCLI15__URG_LOW__SHIFT
33456. DAGB1_WRCLI15__VIRT_CHAN_MASK
33457. DAGB1_WRCLI15__VIRT_CHAN__SHIFT
33458. DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK
33459. DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT
33460. DAGB1_WRCLI1__MAX_BW_ENABLE_MASK
33461. DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT
33462. DAGB1_WRCLI1__MAX_BW_MASK
33463. DAGB1_WRCLI1__MAX_BW__SHIFT
33464. DAGB1_WRCLI1__MAX_OSD_MASK
33465. DAGB1_WRCLI1__MAX_OSD__SHIFT
33466. DAGB1_WRCLI1__MIN_BW_ENABLE_MASK
33467. DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT
33468. DAGB1_WRCLI1__MIN_BW_MASK
33469. DAGB1_WRCLI1__MIN_BW__SHIFT
33470. DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK
33471. DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
33472. DAGB1_WRCLI1__URG_HIGH_MASK
33473. DAGB1_WRCLI1__URG_HIGH__SHIFT
33474. DAGB1_WRCLI1__URG_LOW_MASK
33475. DAGB1_WRCLI1__URG_LOW__SHIFT
33476. DAGB1_WRCLI1__VIRT_CHAN_MASK
33477. DAGB1_WRCLI1__VIRT_CHAN__SHIFT
33478. DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK
33479. DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT
33480. DAGB1_WRCLI2__MAX_BW_ENABLE_MASK
33481. DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT
33482. DAGB1_WRCLI2__MAX_BW_MASK
33483. DAGB1_WRCLI2__MAX_BW__SHIFT
33484. DAGB1_WRCLI2__MAX_OSD_MASK
33485. DAGB1_WRCLI2__MAX_OSD__SHIFT
33486. DAGB1_WRCLI2__MIN_BW_ENABLE_MASK
33487. DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT
33488. DAGB1_WRCLI2__MIN_BW_MASK
33489. DAGB1_WRCLI2__MIN_BW__SHIFT
33490. DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK
33491. DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
33492. DAGB1_WRCLI2__URG_HIGH_MASK
33493. DAGB1_WRCLI2__URG_HIGH__SHIFT
33494. DAGB1_WRCLI2__URG_LOW_MASK
33495. DAGB1_WRCLI2__URG_LOW__SHIFT
33496. DAGB1_WRCLI2__VIRT_CHAN_MASK
33497. DAGB1_WRCLI2__VIRT_CHAN__SHIFT
33498. DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK
33499. DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT
33500. DAGB1_WRCLI3__MAX_BW_ENABLE_MASK
33501. DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT
33502. DAGB1_WRCLI3__MAX_BW_MASK
33503. DAGB1_WRCLI3__MAX_BW__SHIFT
33504. DAGB1_WRCLI3__MAX_OSD_MASK
33505. DAGB1_WRCLI3__MAX_OSD__SHIFT
33506. DAGB1_WRCLI3__MIN_BW_ENABLE_MASK
33507. DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT
33508. DAGB1_WRCLI3__MIN_BW_MASK
33509. DAGB1_WRCLI3__MIN_BW__SHIFT
33510. DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK
33511. DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
33512. DAGB1_WRCLI3__URG_HIGH_MASK
33513. DAGB1_WRCLI3__URG_HIGH__SHIFT
33514. DAGB1_WRCLI3__URG_LOW_MASK
33515. DAGB1_WRCLI3__URG_LOW__SHIFT
33516. DAGB1_WRCLI3__VIRT_CHAN_MASK
33517. DAGB1_WRCLI3__VIRT_CHAN__SHIFT
33518. DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK
33519. DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT
33520. DAGB1_WRCLI4__MAX_BW_ENABLE_MASK
33521. DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT
33522. DAGB1_WRCLI4__MAX_BW_MASK
33523. DAGB1_WRCLI4__MAX_BW__SHIFT
33524. DAGB1_WRCLI4__MAX_OSD_MASK
33525. DAGB1_WRCLI4__MAX_OSD__SHIFT
33526. DAGB1_WRCLI4__MIN_BW_ENABLE_MASK
33527. DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT
33528. DAGB1_WRCLI4__MIN_BW_MASK
33529. DAGB1_WRCLI4__MIN_BW__SHIFT
33530. DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK
33531. DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
33532. DAGB1_WRCLI4__URG_HIGH_MASK
33533. DAGB1_WRCLI4__URG_HIGH__SHIFT
33534. DAGB1_WRCLI4__URG_LOW_MASK
33535. DAGB1_WRCLI4__URG_LOW__SHIFT
33536. DAGB1_WRCLI4__VIRT_CHAN_MASK
33537. DAGB1_WRCLI4__VIRT_CHAN__SHIFT
33538. DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK
33539. DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT
33540. DAGB1_WRCLI5__MAX_BW_ENABLE_MASK
33541. DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT
33542. DAGB1_WRCLI5__MAX_BW_MASK
33543. DAGB1_WRCLI5__MAX_BW__SHIFT
33544. DAGB1_WRCLI5__MAX_OSD_MASK
33545. DAGB1_WRCLI5__MAX_OSD__SHIFT
33546. DAGB1_WRCLI5__MIN_BW_ENABLE_MASK
33547. DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT
33548. DAGB1_WRCLI5__MIN_BW_MASK
33549. DAGB1_WRCLI5__MIN_BW__SHIFT
33550. DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK
33551. DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
33552. DAGB1_WRCLI5__URG_HIGH_MASK
33553. DAGB1_WRCLI5__URG_HIGH__SHIFT
33554. DAGB1_WRCLI5__URG_LOW_MASK
33555. DAGB1_WRCLI5__URG_LOW__SHIFT
33556. DAGB1_WRCLI5__VIRT_CHAN_MASK
33557. DAGB1_WRCLI5__VIRT_CHAN__SHIFT
33558. DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK
33559. DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT
33560. DAGB1_WRCLI6__MAX_BW_ENABLE_MASK
33561. DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT
33562. DAGB1_WRCLI6__MAX_BW_MASK
33563. DAGB1_WRCLI6__MAX_BW__SHIFT
33564. DAGB1_WRCLI6__MAX_OSD_MASK
33565. DAGB1_WRCLI6__MAX_OSD__SHIFT
33566. DAGB1_WRCLI6__MIN_BW_ENABLE_MASK
33567. DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT
33568. DAGB1_WRCLI6__MIN_BW_MASK
33569. DAGB1_WRCLI6__MIN_BW__SHIFT
33570. DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK
33571. DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
33572. DAGB1_WRCLI6__URG_HIGH_MASK
33573. DAGB1_WRCLI6__URG_HIGH__SHIFT
33574. DAGB1_WRCLI6__URG_LOW_MASK
33575. DAGB1_WRCLI6__URG_LOW__SHIFT
33576. DAGB1_WRCLI6__VIRT_CHAN_MASK
33577. DAGB1_WRCLI6__VIRT_CHAN__SHIFT
33578. DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK
33579. DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT
33580. DAGB1_WRCLI7__MAX_BW_ENABLE_MASK
33581. DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT
33582. DAGB1_WRCLI7__MAX_BW_MASK
33583. DAGB1_WRCLI7__MAX_BW__SHIFT
33584. DAGB1_WRCLI7__MAX_OSD_MASK
33585. DAGB1_WRCLI7__MAX_OSD__SHIFT
33586. DAGB1_WRCLI7__MIN_BW_ENABLE_MASK
33587. DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT
33588. DAGB1_WRCLI7__MIN_BW_MASK
33589. DAGB1_WRCLI7__MIN_BW__SHIFT
33590. DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK
33591. DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
33592. DAGB1_WRCLI7__URG_HIGH_MASK
33593. DAGB1_WRCLI7__URG_HIGH__SHIFT
33594. DAGB1_WRCLI7__URG_LOW_MASK
33595. DAGB1_WRCLI7__URG_LOW__SHIFT
33596. DAGB1_WRCLI7__VIRT_CHAN_MASK
33597. DAGB1_WRCLI7__VIRT_CHAN__SHIFT
33598. DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK
33599. DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT
33600. DAGB1_WRCLI8__MAX_BW_ENABLE_MASK
33601. DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT
33602. DAGB1_WRCLI8__MAX_BW_MASK
33603. DAGB1_WRCLI8__MAX_BW__SHIFT
33604. DAGB1_WRCLI8__MAX_OSD_MASK
33605. DAGB1_WRCLI8__MAX_OSD__SHIFT
33606. DAGB1_WRCLI8__MIN_BW_ENABLE_MASK
33607. DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT
33608. DAGB1_WRCLI8__MIN_BW_MASK
33609. DAGB1_WRCLI8__MIN_BW__SHIFT
33610. DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK
33611. DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
33612. DAGB1_WRCLI8__URG_HIGH_MASK
33613. DAGB1_WRCLI8__URG_HIGH__SHIFT
33614. DAGB1_WRCLI8__URG_LOW_MASK
33615. DAGB1_WRCLI8__URG_LOW__SHIFT
33616. DAGB1_WRCLI8__VIRT_CHAN_MASK
33617. DAGB1_WRCLI8__VIRT_CHAN__SHIFT
33618. DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK
33619. DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT
33620. DAGB1_WRCLI9__MAX_BW_ENABLE_MASK
33621. DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT
33622. DAGB1_WRCLI9__MAX_BW_MASK
33623. DAGB1_WRCLI9__MAX_BW__SHIFT
33624. DAGB1_WRCLI9__MAX_OSD_MASK
33625. DAGB1_WRCLI9__MAX_OSD__SHIFT
33626. DAGB1_WRCLI9__MIN_BW_ENABLE_MASK
33627. DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT
33628. DAGB1_WRCLI9__MIN_BW_MASK
33629. DAGB1_WRCLI9__MIN_BW__SHIFT
33630. DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK
33631. DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
33632. DAGB1_WRCLI9__URG_HIGH_MASK
33633. DAGB1_WRCLI9__URG_HIGH__SHIFT
33634. DAGB1_WRCLI9__URG_LOW_MASK
33635. DAGB1_WRCLI9__URG_LOW__SHIFT
33636. DAGB1_WRCLI9__VIRT_CHAN_MASK
33637. DAGB1_WRCLI9__VIRT_CHAN__SHIFT
33638. DAGB1_WRCLI_ASK_PENDING__BUSY_MASK
33639. DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT
33640. DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
33641. DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
33642. DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK
33643. DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
33644. DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK
33645. DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
33646. DAGB1_WRCLI_GO_PENDING__BUSY_MASK
33647. DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT
33648. DAGB1_WRCLI_OARB_PENDING__BUSY_MASK
33649. DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT
33650. DAGB1_WRCLI_OSD_PENDING__BUSY_MASK
33651. DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT
33652. DAGB1_WRCLI_TLB_PENDING__BUSY_MASK
33653. DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT
33654. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
33655. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
33656. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
33657. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
33658. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
33659. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
33660. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
33661. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
33662. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
33663. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
33664. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
33665. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
33666. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
33667. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
33668. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
33669. DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
33670. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
33671. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
33672. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
33673. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
33674. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
33675. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
33676. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
33677. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
33678. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
33679. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
33680. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
33681. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
33682. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
33683. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
33684. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
33685. DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
33686. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
33687. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
33688. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
33689. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
33690. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
33691. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
33692. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
33693. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
33694. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
33695. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
33696. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
33697. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
33698. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
33699. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
33700. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
33701. DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
33702. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
33703. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
33704. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
33705. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
33706. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
33707. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
33708. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
33709. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
33710. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
33711. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
33712. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
33713. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
33714. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
33715. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
33716. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
33717. DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
33718. DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK
33719. DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
33720. DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
33721. DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
33722. DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
33723. DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
33724. DAGB1_WR_ADDR_DAGB__WHOAMI_MASK
33725. DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT
33726. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
33727. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
33728. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
33729. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
33730. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
33731. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
33732. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
33733. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
33734. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
33735. DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
33736. DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
33737. DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
33738. DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
33739. DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
33740. DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
33741. DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
33742. DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
33743. DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
33744. DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
33745. DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
33746. DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK
33747. DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
33748. DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
33749. DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
33750. DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
33751. DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
33752. DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
33753. DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
33754. DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK
33755. DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT
33756. DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
33757. DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
33758. DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
33759. DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
33760. DAGB1_WR_CNTL__IO_LEVEL_MASK
33761. DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
33762. DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
33763. DAGB1_WR_CNTL__IO_LEVEL__SHIFT
33764. DAGB1_WR_CNTL__SCLK_FREQ_MASK
33765. DAGB1_WR_CNTL__SCLK_FREQ__SHIFT
33766. DAGB1_WR_CNTL__SHARE_VC_NUM_MASK
33767. DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT
33768. DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK
33769. DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
33770. DAGB1_WR_CREDITS_FULL__FULL_MASK
33771. DAGB1_WR_CREDITS_FULL__FULL__SHIFT
33772. DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
33773. DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
33774. DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
33775. DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
33776. DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
33777. DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
33778. DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
33779. DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
33780. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
33781. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
33782. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
33783. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
33784. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
33785. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
33786. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
33787. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
33788. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
33789. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
33790. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
33791. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
33792. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
33793. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
33794. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
33795. DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
33796. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
33797. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
33798. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
33799. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
33800. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
33801. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
33802. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
33803. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
33804. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
33805. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
33806. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
33807. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
33808. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
33809. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
33810. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
33811. DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
33812. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
33813. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
33814. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
33815. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
33816. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
33817. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
33818. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
33819. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
33820. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
33821. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
33822. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
33823. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
33824. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
33825. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
33826. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
33827. DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
33828. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
33829. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
33830. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
33831. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
33832. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
33833. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
33834. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
33835. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
33836. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
33837. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
33838. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
33839. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
33840. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
33841. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
33842. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
33843. DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
33844. DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK
33845. DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
33846. DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
33847. DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
33848. DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
33849. DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
33850. DAGB1_WR_DATA_DAGB__WHOAMI_MASK
33851. DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT
33852. DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK
33853. DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT
33854. DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK
33855. DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT
33856. DAGB1_WR_GMI_CNTL__LEVEL_MASK
33857. DAGB1_WR_GMI_CNTL__LEVEL__SHIFT
33858. DAGB1_WR_GMI_CNTL__MAX_BURST_MASK
33859. DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT
33860. DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
33861. DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
33862. DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
33863. DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
33864. DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK
33865. DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
33866. DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
33867. DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
33868. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
33869. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
33870. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
33871. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
33872. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
33873. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
33874. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
33875. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
33876. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
33877. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
33878. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
33879. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
33880. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
33881. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
33882. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
33883. DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
33884. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
33885. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
33886. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
33887. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
33888. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
33889. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
33890. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
33891. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
33892. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
33893. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
33894. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
33895. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
33896. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
33897. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
33898. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
33899. DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
33900. DAGB1_WR_TLB_CREDIT__TLB0_MASK
33901. DAGB1_WR_TLB_CREDIT__TLB0__SHIFT
33902. DAGB1_WR_TLB_CREDIT__TLB1_MASK
33903. DAGB1_WR_TLB_CREDIT__TLB1__SHIFT
33904. DAGB1_WR_TLB_CREDIT__TLB2_MASK
33905. DAGB1_WR_TLB_CREDIT__TLB2__SHIFT
33906. DAGB1_WR_TLB_CREDIT__TLB3_MASK
33907. DAGB1_WR_TLB_CREDIT__TLB3__SHIFT
33908. DAGB1_WR_TLB_CREDIT__TLB4_MASK
33909. DAGB1_WR_TLB_CREDIT__TLB4__SHIFT
33910. DAGB1_WR_TLB_CREDIT__TLB5_MASK
33911. DAGB1_WR_TLB_CREDIT__TLB5__SHIFT
33912. DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK
33913. DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT
33914. DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
33915. DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
33916. DAGB1_WR_VC0_CNTL__MAX_BW_MASK
33917. DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT
33918. DAGB1_WR_VC0_CNTL__MAX_OSD_MASK
33919. DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT
33920. DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
33921. DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
33922. DAGB1_WR_VC0_CNTL__MIN_BW_MASK
33923. DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT
33924. DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
33925. DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
33926. DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK
33927. DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT
33928. DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK
33929. DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT
33930. DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
33931. DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
33932. DAGB1_WR_VC1_CNTL__MAX_BW_MASK
33933. DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT
33934. DAGB1_WR_VC1_CNTL__MAX_OSD_MASK
33935. DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT
33936. DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
33937. DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
33938. DAGB1_WR_VC1_CNTL__MIN_BW_MASK
33939. DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT
33940. DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
33941. DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
33942. DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK
33943. DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT
33944. DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK
33945. DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT
33946. DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
33947. DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
33948. DAGB1_WR_VC2_CNTL__MAX_BW_MASK
33949. DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT
33950. DAGB1_WR_VC2_CNTL__MAX_OSD_MASK
33951. DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT
33952. DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
33953. DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
33954. DAGB1_WR_VC2_CNTL__MIN_BW_MASK
33955. DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT
33956. DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
33957. DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
33958. DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK
33959. DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT
33960. DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK
33961. DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT
33962. DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
33963. DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
33964. DAGB1_WR_VC3_CNTL__MAX_BW_MASK
33965. DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT
33966. DAGB1_WR_VC3_CNTL__MAX_OSD_MASK
33967. DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT
33968. DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
33969. DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
33970. DAGB1_WR_VC3_CNTL__MIN_BW_MASK
33971. DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT
33972. DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
33973. DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
33974. DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK
33975. DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT
33976. DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK
33977. DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT
33978. DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
33979. DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
33980. DAGB1_WR_VC4_CNTL__MAX_BW_MASK
33981. DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT
33982. DAGB1_WR_VC4_CNTL__MAX_OSD_MASK
33983. DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT
33984. DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
33985. DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
33986. DAGB1_WR_VC4_CNTL__MIN_BW_MASK
33987. DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT
33988. DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
33989. DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
33990. DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK
33991. DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT
33992. DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK
33993. DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT
33994. DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
33995. DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
33996. DAGB1_WR_VC5_CNTL__MAX_BW_MASK
33997. DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT
33998. DAGB1_WR_VC5_CNTL__MAX_OSD_MASK
33999. DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT
34000. DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
34001. DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
34002. DAGB1_WR_VC5_CNTL__MIN_BW_MASK
34003. DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT
34004. DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
34005. DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
34006. DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK
34007. DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT
34008. DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK
34009. DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT
34010. DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
34011. DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
34012. DAGB1_WR_VC6_CNTL__MAX_BW_MASK
34013. DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT
34014. DAGB1_WR_VC6_CNTL__MAX_OSD_MASK
34015. DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT
34016. DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
34017. DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
34018. DAGB1_WR_VC6_CNTL__MIN_BW_MASK
34019. DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT
34020. DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
34021. DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
34022. DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK
34023. DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT
34024. DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK
34025. DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT
34026. DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
34027. DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
34028. DAGB1_WR_VC7_CNTL__MAX_BW_MASK
34029. DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT
34030. DAGB1_WR_VC7_CNTL__MAX_OSD_MASK
34031. DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT
34032. DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
34033. DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
34034. DAGB1_WR_VC7_CNTL__MIN_BW_MASK
34035. DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT
34036. DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
34037. DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
34038. DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK
34039. DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT
34040. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
34041. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
34042. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
34043. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
34044. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
34045. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
34046. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
34047. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
34048. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
34049. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
34050. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
34051. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
34052. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
34053. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
34054. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
34055. DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
34056. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
34057. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
34058. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
34059. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
34060. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
34061. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
34062. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
34063. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
34064. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
34065. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
34066. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
34067. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
34068. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
34069. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
34070. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
34071. DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
34072. DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
34073. DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
34074. DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
34075. DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
34076. DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
34077. DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
34078. DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK
34079. DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
34080. DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
34081. DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
34082. DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
34083. DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
34084. DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
34085. DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
34086. DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK
34087. DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
34088. DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
34089. DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
34090. DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK
34091. DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
34092. DAGB2_CNTL_MISC2__SWAP_CTL_MASK
34093. DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT
34094. DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK
34095. DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
34096. DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK
34097. DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
34098. DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK
34099. DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT
34100. DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
34101. DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
34102. DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK
34103. DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT
34104. DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK
34105. DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT
34106. DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK
34107. DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT
34108. DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK
34109. DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT
34110. DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK
34111. DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT
34112. DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK
34113. DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT
34114. DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK
34115. DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT
34116. DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK
34117. DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT
34118. DAGB2_DAGB_DLY__CLI_MASK
34119. DAGB2_DAGB_DLY__CLI__SHIFT
34120. DAGB2_DAGB_DLY__DLY_MASK
34121. DAGB2_DAGB_DLY__DLY__SHIFT
34122. DAGB2_DAGB_DLY__POS_MASK
34123. DAGB2_DAGB_DLY__POS__SHIFT
34124. DAGB2_FIFO_EMPTY__EMPTY_MASK
34125. DAGB2_FIFO_EMPTY__EMPTY__SHIFT
34126. DAGB2_FIFO_FULL__FULL_MASK
34127. DAGB2_FIFO_FULL__FULL__SHIFT
34128. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
34129. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
34130. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
34131. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
34132. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
34133. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
34134. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
34135. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
34136. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
34137. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
34138. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
34139. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
34140. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
34141. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
34142. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
34143. DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
34144. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
34145. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
34146. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
34147. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
34148. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
34149. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
34150. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
34151. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
34152. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
34153. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
34154. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
34155. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
34156. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
34157. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
34158. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
34159. DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
34160. DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK
34161. DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT
34162. DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK
34163. DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT
34164. DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK
34165. DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
34166. DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
34167. DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
34168. DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK
34169. DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
34170. DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK
34171. DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT
34172. DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK
34173. DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT
34174. DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK
34175. DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
34176. DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
34177. DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
34178. DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK
34179. DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
34180. DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK
34181. DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT
34182. DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK
34183. DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT
34184. DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK
34185. DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
34186. DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
34187. DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
34188. DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK
34189. DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
34190. DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
34191. DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
34192. DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK
34193. DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
34194. DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK
34195. DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
34196. DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
34197. DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
34198. DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
34199. DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
34200. DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
34201. DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
34202. DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
34203. DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
34204. DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
34205. DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
34206. DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
34207. DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
34208. DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK
34209. DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT
34210. DAGB2_RDCLI0__MAX_BW_ENABLE_MASK
34211. DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT
34212. DAGB2_RDCLI0__MAX_BW_MASK
34213. DAGB2_RDCLI0__MAX_BW__SHIFT
34214. DAGB2_RDCLI0__MAX_OSD_MASK
34215. DAGB2_RDCLI0__MAX_OSD__SHIFT
34216. DAGB2_RDCLI0__MIN_BW_ENABLE_MASK
34217. DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT
34218. DAGB2_RDCLI0__MIN_BW_MASK
34219. DAGB2_RDCLI0__MIN_BW__SHIFT
34220. DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK
34221. DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
34222. DAGB2_RDCLI0__URG_HIGH_MASK
34223. DAGB2_RDCLI0__URG_HIGH__SHIFT
34224. DAGB2_RDCLI0__URG_LOW_MASK
34225. DAGB2_RDCLI0__URG_LOW__SHIFT
34226. DAGB2_RDCLI0__VIRT_CHAN_MASK
34227. DAGB2_RDCLI0__VIRT_CHAN__SHIFT
34228. DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK
34229. DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT
34230. DAGB2_RDCLI10__MAX_BW_ENABLE_MASK
34231. DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT
34232. DAGB2_RDCLI10__MAX_BW_MASK
34233. DAGB2_RDCLI10__MAX_BW__SHIFT
34234. DAGB2_RDCLI10__MAX_OSD_MASK
34235. DAGB2_RDCLI10__MAX_OSD__SHIFT
34236. DAGB2_RDCLI10__MIN_BW_ENABLE_MASK
34237. DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT
34238. DAGB2_RDCLI10__MIN_BW_MASK
34239. DAGB2_RDCLI10__MIN_BW__SHIFT
34240. DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK
34241. DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
34242. DAGB2_RDCLI10__URG_HIGH_MASK
34243. DAGB2_RDCLI10__URG_HIGH__SHIFT
34244. DAGB2_RDCLI10__URG_LOW_MASK
34245. DAGB2_RDCLI10__URG_LOW__SHIFT
34246. DAGB2_RDCLI10__VIRT_CHAN_MASK
34247. DAGB2_RDCLI10__VIRT_CHAN__SHIFT
34248. DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK
34249. DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT
34250. DAGB2_RDCLI11__MAX_BW_ENABLE_MASK
34251. DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT
34252. DAGB2_RDCLI11__MAX_BW_MASK
34253. DAGB2_RDCLI11__MAX_BW__SHIFT
34254. DAGB2_RDCLI11__MAX_OSD_MASK
34255. DAGB2_RDCLI11__MAX_OSD__SHIFT
34256. DAGB2_RDCLI11__MIN_BW_ENABLE_MASK
34257. DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT
34258. DAGB2_RDCLI11__MIN_BW_MASK
34259. DAGB2_RDCLI11__MIN_BW__SHIFT
34260. DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK
34261. DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
34262. DAGB2_RDCLI11__URG_HIGH_MASK
34263. DAGB2_RDCLI11__URG_HIGH__SHIFT
34264. DAGB2_RDCLI11__URG_LOW_MASK
34265. DAGB2_RDCLI11__URG_LOW__SHIFT
34266. DAGB2_RDCLI11__VIRT_CHAN_MASK
34267. DAGB2_RDCLI11__VIRT_CHAN__SHIFT
34268. DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK
34269. DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT
34270. DAGB2_RDCLI12__MAX_BW_ENABLE_MASK
34271. DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT
34272. DAGB2_RDCLI12__MAX_BW_MASK
34273. DAGB2_RDCLI12__MAX_BW__SHIFT
34274. DAGB2_RDCLI12__MAX_OSD_MASK
34275. DAGB2_RDCLI12__MAX_OSD__SHIFT
34276. DAGB2_RDCLI12__MIN_BW_ENABLE_MASK
34277. DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT
34278. DAGB2_RDCLI12__MIN_BW_MASK
34279. DAGB2_RDCLI12__MIN_BW__SHIFT
34280. DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK
34281. DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
34282. DAGB2_RDCLI12__URG_HIGH_MASK
34283. DAGB2_RDCLI12__URG_HIGH__SHIFT
34284. DAGB2_RDCLI12__URG_LOW_MASK
34285. DAGB2_RDCLI12__URG_LOW__SHIFT
34286. DAGB2_RDCLI12__VIRT_CHAN_MASK
34287. DAGB2_RDCLI12__VIRT_CHAN__SHIFT
34288. DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK
34289. DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT
34290. DAGB2_RDCLI13__MAX_BW_ENABLE_MASK
34291. DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT
34292. DAGB2_RDCLI13__MAX_BW_MASK
34293. DAGB2_RDCLI13__MAX_BW__SHIFT
34294. DAGB2_RDCLI13__MAX_OSD_MASK
34295. DAGB2_RDCLI13__MAX_OSD__SHIFT
34296. DAGB2_RDCLI13__MIN_BW_ENABLE_MASK
34297. DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT
34298. DAGB2_RDCLI13__MIN_BW_MASK
34299. DAGB2_RDCLI13__MIN_BW__SHIFT
34300. DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK
34301. DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
34302. DAGB2_RDCLI13__URG_HIGH_MASK
34303. DAGB2_RDCLI13__URG_HIGH__SHIFT
34304. DAGB2_RDCLI13__URG_LOW_MASK
34305. DAGB2_RDCLI13__URG_LOW__SHIFT
34306. DAGB2_RDCLI13__VIRT_CHAN_MASK
34307. DAGB2_RDCLI13__VIRT_CHAN__SHIFT
34308. DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK
34309. DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT
34310. DAGB2_RDCLI14__MAX_BW_ENABLE_MASK
34311. DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT
34312. DAGB2_RDCLI14__MAX_BW_MASK
34313. DAGB2_RDCLI14__MAX_BW__SHIFT
34314. DAGB2_RDCLI14__MAX_OSD_MASK
34315. DAGB2_RDCLI14__MAX_OSD__SHIFT
34316. DAGB2_RDCLI14__MIN_BW_ENABLE_MASK
34317. DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT
34318. DAGB2_RDCLI14__MIN_BW_MASK
34319. DAGB2_RDCLI14__MIN_BW__SHIFT
34320. DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK
34321. DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
34322. DAGB2_RDCLI14__URG_HIGH_MASK
34323. DAGB2_RDCLI14__URG_HIGH__SHIFT
34324. DAGB2_RDCLI14__URG_LOW_MASK
34325. DAGB2_RDCLI14__URG_LOW__SHIFT
34326. DAGB2_RDCLI14__VIRT_CHAN_MASK
34327. DAGB2_RDCLI14__VIRT_CHAN__SHIFT
34328. DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK
34329. DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT
34330. DAGB2_RDCLI15__MAX_BW_ENABLE_MASK
34331. DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT
34332. DAGB2_RDCLI15__MAX_BW_MASK
34333. DAGB2_RDCLI15__MAX_BW__SHIFT
34334. DAGB2_RDCLI15__MAX_OSD_MASK
34335. DAGB2_RDCLI15__MAX_OSD__SHIFT
34336. DAGB2_RDCLI15__MIN_BW_ENABLE_MASK
34337. DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT
34338. DAGB2_RDCLI15__MIN_BW_MASK
34339. DAGB2_RDCLI15__MIN_BW__SHIFT
34340. DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK
34341. DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
34342. DAGB2_RDCLI15__URG_HIGH_MASK
34343. DAGB2_RDCLI15__URG_HIGH__SHIFT
34344. DAGB2_RDCLI15__URG_LOW_MASK
34345. DAGB2_RDCLI15__URG_LOW__SHIFT
34346. DAGB2_RDCLI15__VIRT_CHAN_MASK
34347. DAGB2_RDCLI15__VIRT_CHAN__SHIFT
34348. DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK
34349. DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT
34350. DAGB2_RDCLI1__MAX_BW_ENABLE_MASK
34351. DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT
34352. DAGB2_RDCLI1__MAX_BW_MASK
34353. DAGB2_RDCLI1__MAX_BW__SHIFT
34354. DAGB2_RDCLI1__MAX_OSD_MASK
34355. DAGB2_RDCLI1__MAX_OSD__SHIFT
34356. DAGB2_RDCLI1__MIN_BW_ENABLE_MASK
34357. DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT
34358. DAGB2_RDCLI1__MIN_BW_MASK
34359. DAGB2_RDCLI1__MIN_BW__SHIFT
34360. DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK
34361. DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
34362. DAGB2_RDCLI1__URG_HIGH_MASK
34363. DAGB2_RDCLI1__URG_HIGH__SHIFT
34364. DAGB2_RDCLI1__URG_LOW_MASK
34365. DAGB2_RDCLI1__URG_LOW__SHIFT
34366. DAGB2_RDCLI1__VIRT_CHAN_MASK
34367. DAGB2_RDCLI1__VIRT_CHAN__SHIFT
34368. DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK
34369. DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT
34370. DAGB2_RDCLI2__MAX_BW_ENABLE_MASK
34371. DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT
34372. DAGB2_RDCLI2__MAX_BW_MASK
34373. DAGB2_RDCLI2__MAX_BW__SHIFT
34374. DAGB2_RDCLI2__MAX_OSD_MASK
34375. DAGB2_RDCLI2__MAX_OSD__SHIFT
34376. DAGB2_RDCLI2__MIN_BW_ENABLE_MASK
34377. DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT
34378. DAGB2_RDCLI2__MIN_BW_MASK
34379. DAGB2_RDCLI2__MIN_BW__SHIFT
34380. DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK
34381. DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
34382. DAGB2_RDCLI2__URG_HIGH_MASK
34383. DAGB2_RDCLI2__URG_HIGH__SHIFT
34384. DAGB2_RDCLI2__URG_LOW_MASK
34385. DAGB2_RDCLI2__URG_LOW__SHIFT
34386. DAGB2_RDCLI2__VIRT_CHAN_MASK
34387. DAGB2_RDCLI2__VIRT_CHAN__SHIFT
34388. DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK
34389. DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT
34390. DAGB2_RDCLI3__MAX_BW_ENABLE_MASK
34391. DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT
34392. DAGB2_RDCLI3__MAX_BW_MASK
34393. DAGB2_RDCLI3__MAX_BW__SHIFT
34394. DAGB2_RDCLI3__MAX_OSD_MASK
34395. DAGB2_RDCLI3__MAX_OSD__SHIFT
34396. DAGB2_RDCLI3__MIN_BW_ENABLE_MASK
34397. DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT
34398. DAGB2_RDCLI3__MIN_BW_MASK
34399. DAGB2_RDCLI3__MIN_BW__SHIFT
34400. DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK
34401. DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
34402. DAGB2_RDCLI3__URG_HIGH_MASK
34403. DAGB2_RDCLI3__URG_HIGH__SHIFT
34404. DAGB2_RDCLI3__URG_LOW_MASK
34405. DAGB2_RDCLI3__URG_LOW__SHIFT
34406. DAGB2_RDCLI3__VIRT_CHAN_MASK
34407. DAGB2_RDCLI3__VIRT_CHAN__SHIFT
34408. DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK
34409. DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT
34410. DAGB2_RDCLI4__MAX_BW_ENABLE_MASK
34411. DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT
34412. DAGB2_RDCLI4__MAX_BW_MASK
34413. DAGB2_RDCLI4__MAX_BW__SHIFT
34414. DAGB2_RDCLI4__MAX_OSD_MASK
34415. DAGB2_RDCLI4__MAX_OSD__SHIFT
34416. DAGB2_RDCLI4__MIN_BW_ENABLE_MASK
34417. DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT
34418. DAGB2_RDCLI4__MIN_BW_MASK
34419. DAGB2_RDCLI4__MIN_BW__SHIFT
34420. DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK
34421. DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
34422. DAGB2_RDCLI4__URG_HIGH_MASK
34423. DAGB2_RDCLI4__URG_HIGH__SHIFT
34424. DAGB2_RDCLI4__URG_LOW_MASK
34425. DAGB2_RDCLI4__URG_LOW__SHIFT
34426. DAGB2_RDCLI4__VIRT_CHAN_MASK
34427. DAGB2_RDCLI4__VIRT_CHAN__SHIFT
34428. DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK
34429. DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT
34430. DAGB2_RDCLI5__MAX_BW_ENABLE_MASK
34431. DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT
34432. DAGB2_RDCLI5__MAX_BW_MASK
34433. DAGB2_RDCLI5__MAX_BW__SHIFT
34434. DAGB2_RDCLI5__MAX_OSD_MASK
34435. DAGB2_RDCLI5__MAX_OSD__SHIFT
34436. DAGB2_RDCLI5__MIN_BW_ENABLE_MASK
34437. DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT
34438. DAGB2_RDCLI5__MIN_BW_MASK
34439. DAGB2_RDCLI5__MIN_BW__SHIFT
34440. DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK
34441. DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
34442. DAGB2_RDCLI5__URG_HIGH_MASK
34443. DAGB2_RDCLI5__URG_HIGH__SHIFT
34444. DAGB2_RDCLI5__URG_LOW_MASK
34445. DAGB2_RDCLI5__URG_LOW__SHIFT
34446. DAGB2_RDCLI5__VIRT_CHAN_MASK
34447. DAGB2_RDCLI5__VIRT_CHAN__SHIFT
34448. DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK
34449. DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT
34450. DAGB2_RDCLI6__MAX_BW_ENABLE_MASK
34451. DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT
34452. DAGB2_RDCLI6__MAX_BW_MASK
34453. DAGB2_RDCLI6__MAX_BW__SHIFT
34454. DAGB2_RDCLI6__MAX_OSD_MASK
34455. DAGB2_RDCLI6__MAX_OSD__SHIFT
34456. DAGB2_RDCLI6__MIN_BW_ENABLE_MASK
34457. DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT
34458. DAGB2_RDCLI6__MIN_BW_MASK
34459. DAGB2_RDCLI6__MIN_BW__SHIFT
34460. DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK
34461. DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
34462. DAGB2_RDCLI6__URG_HIGH_MASK
34463. DAGB2_RDCLI6__URG_HIGH__SHIFT
34464. DAGB2_RDCLI6__URG_LOW_MASK
34465. DAGB2_RDCLI6__URG_LOW__SHIFT
34466. DAGB2_RDCLI6__VIRT_CHAN_MASK
34467. DAGB2_RDCLI6__VIRT_CHAN__SHIFT
34468. DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK
34469. DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT
34470. DAGB2_RDCLI7__MAX_BW_ENABLE_MASK
34471. DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT
34472. DAGB2_RDCLI7__MAX_BW_MASK
34473. DAGB2_RDCLI7__MAX_BW__SHIFT
34474. DAGB2_RDCLI7__MAX_OSD_MASK
34475. DAGB2_RDCLI7__MAX_OSD__SHIFT
34476. DAGB2_RDCLI7__MIN_BW_ENABLE_MASK
34477. DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT
34478. DAGB2_RDCLI7__MIN_BW_MASK
34479. DAGB2_RDCLI7__MIN_BW__SHIFT
34480. DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK
34481. DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
34482. DAGB2_RDCLI7__URG_HIGH_MASK
34483. DAGB2_RDCLI7__URG_HIGH__SHIFT
34484. DAGB2_RDCLI7__URG_LOW_MASK
34485. DAGB2_RDCLI7__URG_LOW__SHIFT
34486. DAGB2_RDCLI7__VIRT_CHAN_MASK
34487. DAGB2_RDCLI7__VIRT_CHAN__SHIFT
34488. DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK
34489. DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT
34490. DAGB2_RDCLI8__MAX_BW_ENABLE_MASK
34491. DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT
34492. DAGB2_RDCLI8__MAX_BW_MASK
34493. DAGB2_RDCLI8__MAX_BW__SHIFT
34494. DAGB2_RDCLI8__MAX_OSD_MASK
34495. DAGB2_RDCLI8__MAX_OSD__SHIFT
34496. DAGB2_RDCLI8__MIN_BW_ENABLE_MASK
34497. DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT
34498. DAGB2_RDCLI8__MIN_BW_MASK
34499. DAGB2_RDCLI8__MIN_BW__SHIFT
34500. DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK
34501. DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
34502. DAGB2_RDCLI8__URG_HIGH_MASK
34503. DAGB2_RDCLI8__URG_HIGH__SHIFT
34504. DAGB2_RDCLI8__URG_LOW_MASK
34505. DAGB2_RDCLI8__URG_LOW__SHIFT
34506. DAGB2_RDCLI8__VIRT_CHAN_MASK
34507. DAGB2_RDCLI8__VIRT_CHAN__SHIFT
34508. DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK
34509. DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT
34510. DAGB2_RDCLI9__MAX_BW_ENABLE_MASK
34511. DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT
34512. DAGB2_RDCLI9__MAX_BW_MASK
34513. DAGB2_RDCLI9__MAX_BW__SHIFT
34514. DAGB2_RDCLI9__MAX_OSD_MASK
34515. DAGB2_RDCLI9__MAX_OSD__SHIFT
34516. DAGB2_RDCLI9__MIN_BW_ENABLE_MASK
34517. DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT
34518. DAGB2_RDCLI9__MIN_BW_MASK
34519. DAGB2_RDCLI9__MIN_BW__SHIFT
34520. DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK
34521. DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
34522. DAGB2_RDCLI9__URG_HIGH_MASK
34523. DAGB2_RDCLI9__URG_HIGH__SHIFT
34524. DAGB2_RDCLI9__URG_LOW_MASK
34525. DAGB2_RDCLI9__URG_LOW__SHIFT
34526. DAGB2_RDCLI9__VIRT_CHAN_MASK
34527. DAGB2_RDCLI9__VIRT_CHAN__SHIFT
34528. DAGB2_RDCLI_ASK_PENDING__BUSY_MASK
34529. DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT
34530. DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK
34531. DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
34532. DAGB2_RDCLI_GO_PENDING__BUSY_MASK
34533. DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT
34534. DAGB2_RDCLI_OARB_PENDING__BUSY_MASK
34535. DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT
34536. DAGB2_RDCLI_OSD_PENDING__BUSY_MASK
34537. DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT
34538. DAGB2_RDCLI_TLB_PENDING__BUSY_MASK
34539. DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT
34540. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
34541. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
34542. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
34543. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
34544. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
34545. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
34546. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
34547. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
34548. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
34549. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
34550. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
34551. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
34552. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
34553. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
34554. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
34555. DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
34556. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
34557. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
34558. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
34559. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
34560. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
34561. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
34562. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
34563. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
34564. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
34565. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
34566. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
34567. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
34568. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
34569. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
34570. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
34571. DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
34572. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
34573. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
34574. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
34575. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
34576. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
34577. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
34578. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
34579. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
34580. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
34581. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
34582. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
34583. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
34584. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
34585. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
34586. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
34587. DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
34588. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
34589. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
34590. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
34591. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
34592. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
34593. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
34594. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
34595. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
34596. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
34597. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
34598. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
34599. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
34600. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
34601. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
34602. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
34603. DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
34604. DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK
34605. DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
34606. DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
34607. DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
34608. DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
34609. DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
34610. DAGB2_RD_ADDR_DAGB__WHOAMI_MASK
34611. DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT
34612. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
34613. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
34614. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
34615. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
34616. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
34617. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
34618. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
34619. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
34620. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
34621. DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
34622. DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
34623. DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
34624. DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
34625. DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
34626. DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
34627. DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
34628. DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
34629. DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
34630. DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
34631. DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
34632. DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK
34633. DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
34634. DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
34635. DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
34636. DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
34637. DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
34638. DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
34639. DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
34640. DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK
34641. DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT
34642. DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
34643. DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
34644. DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
34645. DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
34646. DAGB2_RD_CNTL__IO_LEVEL_MASK
34647. DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
34648. DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
34649. DAGB2_RD_CNTL__IO_LEVEL__SHIFT
34650. DAGB2_RD_CNTL__SCLK_FREQ_MASK
34651. DAGB2_RD_CNTL__SCLK_FREQ__SHIFT
34652. DAGB2_RD_CNTL__SHARE_VC_NUM_MASK
34653. DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT
34654. DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK
34655. DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
34656. DAGB2_RD_CREDITS_FULL__FULL_MASK
34657. DAGB2_RD_CREDITS_FULL__FULL__SHIFT
34658. DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK
34659. DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT
34660. DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK
34661. DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT
34662. DAGB2_RD_GMI_CNTL__LEVEL_MASK
34663. DAGB2_RD_GMI_CNTL__LEVEL__SHIFT
34664. DAGB2_RD_GMI_CNTL__MAX_BURST_MASK
34665. DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT
34666. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
34667. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
34668. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
34669. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
34670. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
34671. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
34672. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
34673. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
34674. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
34675. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
34676. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
34677. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
34678. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
34679. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
34680. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
34681. DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
34682. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
34683. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
34684. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
34685. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
34686. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
34687. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
34688. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
34689. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
34690. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
34691. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
34692. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
34693. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
34694. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
34695. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
34696. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
34697. DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
34698. DAGB2_RD_TLB_CREDIT__TLB0_MASK
34699. DAGB2_RD_TLB_CREDIT__TLB0__SHIFT
34700. DAGB2_RD_TLB_CREDIT__TLB1_MASK
34701. DAGB2_RD_TLB_CREDIT__TLB1__SHIFT
34702. DAGB2_RD_TLB_CREDIT__TLB2_MASK
34703. DAGB2_RD_TLB_CREDIT__TLB2__SHIFT
34704. DAGB2_RD_TLB_CREDIT__TLB3_MASK
34705. DAGB2_RD_TLB_CREDIT__TLB3__SHIFT
34706. DAGB2_RD_TLB_CREDIT__TLB4_MASK
34707. DAGB2_RD_TLB_CREDIT__TLB4__SHIFT
34708. DAGB2_RD_TLB_CREDIT__TLB5_MASK
34709. DAGB2_RD_TLB_CREDIT__TLB5__SHIFT
34710. DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK
34711. DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT
34712. DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
34713. DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
34714. DAGB2_RD_VC0_CNTL__MAX_BW_MASK
34715. DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT
34716. DAGB2_RD_VC0_CNTL__MAX_OSD_MASK
34717. DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT
34718. DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
34719. DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
34720. DAGB2_RD_VC0_CNTL__MIN_BW_MASK
34721. DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT
34722. DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
34723. DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
34724. DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK
34725. DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT
34726. DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK
34727. DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT
34728. DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
34729. DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
34730. DAGB2_RD_VC1_CNTL__MAX_BW_MASK
34731. DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT
34732. DAGB2_RD_VC1_CNTL__MAX_OSD_MASK
34733. DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT
34734. DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
34735. DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
34736. DAGB2_RD_VC1_CNTL__MIN_BW_MASK
34737. DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT
34738. DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
34739. DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
34740. DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK
34741. DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT
34742. DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK
34743. DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT
34744. DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
34745. DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
34746. DAGB2_RD_VC2_CNTL__MAX_BW_MASK
34747. DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT
34748. DAGB2_RD_VC2_CNTL__MAX_OSD_MASK
34749. DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT
34750. DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
34751. DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
34752. DAGB2_RD_VC2_CNTL__MIN_BW_MASK
34753. DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT
34754. DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
34755. DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
34756. DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK
34757. DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT
34758. DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK
34759. DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT
34760. DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
34761. DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
34762. DAGB2_RD_VC3_CNTL__MAX_BW_MASK
34763. DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT
34764. DAGB2_RD_VC3_CNTL__MAX_OSD_MASK
34765. DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT
34766. DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
34767. DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
34768. DAGB2_RD_VC3_CNTL__MIN_BW_MASK
34769. DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT
34770. DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
34771. DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
34772. DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK
34773. DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT
34774. DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK
34775. DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT
34776. DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
34777. DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
34778. DAGB2_RD_VC4_CNTL__MAX_BW_MASK
34779. DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT
34780. DAGB2_RD_VC4_CNTL__MAX_OSD_MASK
34781. DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT
34782. DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
34783. DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
34784. DAGB2_RD_VC4_CNTL__MIN_BW_MASK
34785. DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT
34786. DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
34787. DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
34788. DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK
34789. DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT
34790. DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK
34791. DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT
34792. DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
34793. DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
34794. DAGB2_RD_VC5_CNTL__MAX_BW_MASK
34795. DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT
34796. DAGB2_RD_VC5_CNTL__MAX_OSD_MASK
34797. DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT
34798. DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
34799. DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
34800. DAGB2_RD_VC5_CNTL__MIN_BW_MASK
34801. DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT
34802. DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
34803. DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
34804. DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK
34805. DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT
34806. DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK
34807. DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT
34808. DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
34809. DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
34810. DAGB2_RD_VC6_CNTL__MAX_BW_MASK
34811. DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT
34812. DAGB2_RD_VC6_CNTL__MAX_OSD_MASK
34813. DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT
34814. DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
34815. DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
34816. DAGB2_RD_VC6_CNTL__MIN_BW_MASK
34817. DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT
34818. DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
34819. DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
34820. DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK
34821. DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT
34822. DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK
34823. DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT
34824. DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
34825. DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
34826. DAGB2_RD_VC7_CNTL__MAX_BW_MASK
34827. DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT
34828. DAGB2_RD_VC7_CNTL__MAX_OSD_MASK
34829. DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT
34830. DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
34831. DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
34832. DAGB2_RD_VC7_CNTL__MIN_BW_MASK
34833. DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT
34834. DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
34835. DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
34836. DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK
34837. DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT
34838. DAGB2_RESERVE0__RESERVE_MASK
34839. DAGB2_RESERVE0__RESERVE__SHIFT
34840. DAGB2_RESERVE10__RESERVE_MASK
34841. DAGB2_RESERVE10__RESERVE__SHIFT
34842. DAGB2_RESERVE11__RESERVE_MASK
34843. DAGB2_RESERVE11__RESERVE__SHIFT
34844. DAGB2_RESERVE12__RESERVE_MASK
34845. DAGB2_RESERVE12__RESERVE__SHIFT
34846. DAGB2_RESERVE13__RESERVE_MASK
34847. DAGB2_RESERVE13__RESERVE__SHIFT
34848. DAGB2_RESERVE1__RESERVE_MASK
34849. DAGB2_RESERVE1__RESERVE__SHIFT
34850. DAGB2_RESERVE2__RESERVE_MASK
34851. DAGB2_RESERVE2__RESERVE__SHIFT
34852. DAGB2_RESERVE3__RESERVE_MASK
34853. DAGB2_RESERVE3__RESERVE__SHIFT
34854. DAGB2_RESERVE4__RESERVE_MASK
34855. DAGB2_RESERVE4__RESERVE__SHIFT
34856. DAGB2_RESERVE5__RESERVE_MASK
34857. DAGB2_RESERVE5__RESERVE__SHIFT
34858. DAGB2_RESERVE6__RESERVE_MASK
34859. DAGB2_RESERVE6__RESERVE__SHIFT
34860. DAGB2_RESERVE7__RESERVE_MASK
34861. DAGB2_RESERVE7__RESERVE__SHIFT
34862. DAGB2_RESERVE8__RESERVE_MASK
34863. DAGB2_RESERVE8__RESERVE__SHIFT
34864. DAGB2_RESERVE9__RESERVE_MASK
34865. DAGB2_RESERVE9__RESERVE__SHIFT
34866. DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK
34867. DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT
34868. DAGB2_WRCLI0__MAX_BW_ENABLE_MASK
34869. DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT
34870. DAGB2_WRCLI0__MAX_BW_MASK
34871. DAGB2_WRCLI0__MAX_BW__SHIFT
34872. DAGB2_WRCLI0__MAX_OSD_MASK
34873. DAGB2_WRCLI0__MAX_OSD__SHIFT
34874. DAGB2_WRCLI0__MIN_BW_ENABLE_MASK
34875. DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT
34876. DAGB2_WRCLI0__MIN_BW_MASK
34877. DAGB2_WRCLI0__MIN_BW__SHIFT
34878. DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK
34879. DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
34880. DAGB2_WRCLI0__URG_HIGH_MASK
34881. DAGB2_WRCLI0__URG_HIGH__SHIFT
34882. DAGB2_WRCLI0__URG_LOW_MASK
34883. DAGB2_WRCLI0__URG_LOW__SHIFT
34884. DAGB2_WRCLI0__VIRT_CHAN_MASK
34885. DAGB2_WRCLI0__VIRT_CHAN__SHIFT
34886. DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK
34887. DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT
34888. DAGB2_WRCLI10__MAX_BW_ENABLE_MASK
34889. DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT
34890. DAGB2_WRCLI10__MAX_BW_MASK
34891. DAGB2_WRCLI10__MAX_BW__SHIFT
34892. DAGB2_WRCLI10__MAX_OSD_MASK
34893. DAGB2_WRCLI10__MAX_OSD__SHIFT
34894. DAGB2_WRCLI10__MIN_BW_ENABLE_MASK
34895. DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT
34896. DAGB2_WRCLI10__MIN_BW_MASK
34897. DAGB2_WRCLI10__MIN_BW__SHIFT
34898. DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK
34899. DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
34900. DAGB2_WRCLI10__URG_HIGH_MASK
34901. DAGB2_WRCLI10__URG_HIGH__SHIFT
34902. DAGB2_WRCLI10__URG_LOW_MASK
34903. DAGB2_WRCLI10__URG_LOW__SHIFT
34904. DAGB2_WRCLI10__VIRT_CHAN_MASK
34905. DAGB2_WRCLI10__VIRT_CHAN__SHIFT
34906. DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK
34907. DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT
34908. DAGB2_WRCLI11__MAX_BW_ENABLE_MASK
34909. DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT
34910. DAGB2_WRCLI11__MAX_BW_MASK
34911. DAGB2_WRCLI11__MAX_BW__SHIFT
34912. DAGB2_WRCLI11__MAX_OSD_MASK
34913. DAGB2_WRCLI11__MAX_OSD__SHIFT
34914. DAGB2_WRCLI11__MIN_BW_ENABLE_MASK
34915. DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT
34916. DAGB2_WRCLI11__MIN_BW_MASK
34917. DAGB2_WRCLI11__MIN_BW__SHIFT
34918. DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK
34919. DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
34920. DAGB2_WRCLI11__URG_HIGH_MASK
34921. DAGB2_WRCLI11__URG_HIGH__SHIFT
34922. DAGB2_WRCLI11__URG_LOW_MASK
34923. DAGB2_WRCLI11__URG_LOW__SHIFT
34924. DAGB2_WRCLI11__VIRT_CHAN_MASK
34925. DAGB2_WRCLI11__VIRT_CHAN__SHIFT
34926. DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK
34927. DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT
34928. DAGB2_WRCLI12__MAX_BW_ENABLE_MASK
34929. DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT
34930. DAGB2_WRCLI12__MAX_BW_MASK
34931. DAGB2_WRCLI12__MAX_BW__SHIFT
34932. DAGB2_WRCLI12__MAX_OSD_MASK
34933. DAGB2_WRCLI12__MAX_OSD__SHIFT
34934. DAGB2_WRCLI12__MIN_BW_ENABLE_MASK
34935. DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT
34936. DAGB2_WRCLI12__MIN_BW_MASK
34937. DAGB2_WRCLI12__MIN_BW__SHIFT
34938. DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK
34939. DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
34940. DAGB2_WRCLI12__URG_HIGH_MASK
34941. DAGB2_WRCLI12__URG_HIGH__SHIFT
34942. DAGB2_WRCLI12__URG_LOW_MASK
34943. DAGB2_WRCLI12__URG_LOW__SHIFT
34944. DAGB2_WRCLI12__VIRT_CHAN_MASK
34945. DAGB2_WRCLI12__VIRT_CHAN__SHIFT
34946. DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK
34947. DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT
34948. DAGB2_WRCLI13__MAX_BW_ENABLE_MASK
34949. DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT
34950. DAGB2_WRCLI13__MAX_BW_MASK
34951. DAGB2_WRCLI13__MAX_BW__SHIFT
34952. DAGB2_WRCLI13__MAX_OSD_MASK
34953. DAGB2_WRCLI13__MAX_OSD__SHIFT
34954. DAGB2_WRCLI13__MIN_BW_ENABLE_MASK
34955. DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT
34956. DAGB2_WRCLI13__MIN_BW_MASK
34957. DAGB2_WRCLI13__MIN_BW__SHIFT
34958. DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK
34959. DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
34960. DAGB2_WRCLI13__URG_HIGH_MASK
34961. DAGB2_WRCLI13__URG_HIGH__SHIFT
34962. DAGB2_WRCLI13__URG_LOW_MASK
34963. DAGB2_WRCLI13__URG_LOW__SHIFT
34964. DAGB2_WRCLI13__VIRT_CHAN_MASK
34965. DAGB2_WRCLI13__VIRT_CHAN__SHIFT
34966. DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK
34967. DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT
34968. DAGB2_WRCLI14__MAX_BW_ENABLE_MASK
34969. DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT
34970. DAGB2_WRCLI14__MAX_BW_MASK
34971. DAGB2_WRCLI14__MAX_BW__SHIFT
34972. DAGB2_WRCLI14__MAX_OSD_MASK
34973. DAGB2_WRCLI14__MAX_OSD__SHIFT
34974. DAGB2_WRCLI14__MIN_BW_ENABLE_MASK
34975. DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT
34976. DAGB2_WRCLI14__MIN_BW_MASK
34977. DAGB2_WRCLI14__MIN_BW__SHIFT
34978. DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK
34979. DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
34980. DAGB2_WRCLI14__URG_HIGH_MASK
34981. DAGB2_WRCLI14__URG_HIGH__SHIFT
34982. DAGB2_WRCLI14__URG_LOW_MASK
34983. DAGB2_WRCLI14__URG_LOW__SHIFT
34984. DAGB2_WRCLI14__VIRT_CHAN_MASK
34985. DAGB2_WRCLI14__VIRT_CHAN__SHIFT
34986. DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK
34987. DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT
34988. DAGB2_WRCLI15__MAX_BW_ENABLE_MASK
34989. DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT
34990. DAGB2_WRCLI15__MAX_BW_MASK
34991. DAGB2_WRCLI15__MAX_BW__SHIFT
34992. DAGB2_WRCLI15__MAX_OSD_MASK
34993. DAGB2_WRCLI15__MAX_OSD__SHIFT
34994. DAGB2_WRCLI15__MIN_BW_ENABLE_MASK
34995. DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT
34996. DAGB2_WRCLI15__MIN_BW_MASK
34997. DAGB2_WRCLI15__MIN_BW__SHIFT
34998. DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK
34999. DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
35000. DAGB2_WRCLI15__URG_HIGH_MASK
35001. DAGB2_WRCLI15__URG_HIGH__SHIFT
35002. DAGB2_WRCLI15__URG_LOW_MASK
35003. DAGB2_WRCLI15__URG_LOW__SHIFT
35004. DAGB2_WRCLI15__VIRT_CHAN_MASK
35005. DAGB2_WRCLI15__VIRT_CHAN__SHIFT
35006. DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK
35007. DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT
35008. DAGB2_WRCLI1__MAX_BW_ENABLE_MASK
35009. DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT
35010. DAGB2_WRCLI1__MAX_BW_MASK
35011. DAGB2_WRCLI1__MAX_BW__SHIFT
35012. DAGB2_WRCLI1__MAX_OSD_MASK
35013. DAGB2_WRCLI1__MAX_OSD__SHIFT
35014. DAGB2_WRCLI1__MIN_BW_ENABLE_MASK
35015. DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT
35016. DAGB2_WRCLI1__MIN_BW_MASK
35017. DAGB2_WRCLI1__MIN_BW__SHIFT
35018. DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK
35019. DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
35020. DAGB2_WRCLI1__URG_HIGH_MASK
35021. DAGB2_WRCLI1__URG_HIGH__SHIFT
35022. DAGB2_WRCLI1__URG_LOW_MASK
35023. DAGB2_WRCLI1__URG_LOW__SHIFT
35024. DAGB2_WRCLI1__VIRT_CHAN_MASK
35025. DAGB2_WRCLI1__VIRT_CHAN__SHIFT
35026. DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK
35027. DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT
35028. DAGB2_WRCLI2__MAX_BW_ENABLE_MASK
35029. DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT
35030. DAGB2_WRCLI2__MAX_BW_MASK
35031. DAGB2_WRCLI2__MAX_BW__SHIFT
35032. DAGB2_WRCLI2__MAX_OSD_MASK
35033. DAGB2_WRCLI2__MAX_OSD__SHIFT
35034. DAGB2_WRCLI2__MIN_BW_ENABLE_MASK
35035. DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT
35036. DAGB2_WRCLI2__MIN_BW_MASK
35037. DAGB2_WRCLI2__MIN_BW__SHIFT
35038. DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK
35039. DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
35040. DAGB2_WRCLI2__URG_HIGH_MASK
35041. DAGB2_WRCLI2__URG_HIGH__SHIFT
35042. DAGB2_WRCLI2__URG_LOW_MASK
35043. DAGB2_WRCLI2__URG_LOW__SHIFT
35044. DAGB2_WRCLI2__VIRT_CHAN_MASK
35045. DAGB2_WRCLI2__VIRT_CHAN__SHIFT
35046. DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK
35047. DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT
35048. DAGB2_WRCLI3__MAX_BW_ENABLE_MASK
35049. DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT
35050. DAGB2_WRCLI3__MAX_BW_MASK
35051. DAGB2_WRCLI3__MAX_BW__SHIFT
35052. DAGB2_WRCLI3__MAX_OSD_MASK
35053. DAGB2_WRCLI3__MAX_OSD__SHIFT
35054. DAGB2_WRCLI3__MIN_BW_ENABLE_MASK
35055. DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT
35056. DAGB2_WRCLI3__MIN_BW_MASK
35057. DAGB2_WRCLI3__MIN_BW__SHIFT
35058. DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK
35059. DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
35060. DAGB2_WRCLI3__URG_HIGH_MASK
35061. DAGB2_WRCLI3__URG_HIGH__SHIFT
35062. DAGB2_WRCLI3__URG_LOW_MASK
35063. DAGB2_WRCLI3__URG_LOW__SHIFT
35064. DAGB2_WRCLI3__VIRT_CHAN_MASK
35065. DAGB2_WRCLI3__VIRT_CHAN__SHIFT
35066. DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK
35067. DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT
35068. DAGB2_WRCLI4__MAX_BW_ENABLE_MASK
35069. DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT
35070. DAGB2_WRCLI4__MAX_BW_MASK
35071. DAGB2_WRCLI4__MAX_BW__SHIFT
35072. DAGB2_WRCLI4__MAX_OSD_MASK
35073. DAGB2_WRCLI4__MAX_OSD__SHIFT
35074. DAGB2_WRCLI4__MIN_BW_ENABLE_MASK
35075. DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT
35076. DAGB2_WRCLI4__MIN_BW_MASK
35077. DAGB2_WRCLI4__MIN_BW__SHIFT
35078. DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK
35079. DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
35080. DAGB2_WRCLI4__URG_HIGH_MASK
35081. DAGB2_WRCLI4__URG_HIGH__SHIFT
35082. DAGB2_WRCLI4__URG_LOW_MASK
35083. DAGB2_WRCLI4__URG_LOW__SHIFT
35084. DAGB2_WRCLI4__VIRT_CHAN_MASK
35085. DAGB2_WRCLI4__VIRT_CHAN__SHIFT
35086. DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK
35087. DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT
35088. DAGB2_WRCLI5__MAX_BW_ENABLE_MASK
35089. DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT
35090. DAGB2_WRCLI5__MAX_BW_MASK
35091. DAGB2_WRCLI5__MAX_BW__SHIFT
35092. DAGB2_WRCLI5__MAX_OSD_MASK
35093. DAGB2_WRCLI5__MAX_OSD__SHIFT
35094. DAGB2_WRCLI5__MIN_BW_ENABLE_MASK
35095. DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT
35096. DAGB2_WRCLI5__MIN_BW_MASK
35097. DAGB2_WRCLI5__MIN_BW__SHIFT
35098. DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK
35099. DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
35100. DAGB2_WRCLI5__URG_HIGH_MASK
35101. DAGB2_WRCLI5__URG_HIGH__SHIFT
35102. DAGB2_WRCLI5__URG_LOW_MASK
35103. DAGB2_WRCLI5__URG_LOW__SHIFT
35104. DAGB2_WRCLI5__VIRT_CHAN_MASK
35105. DAGB2_WRCLI5__VIRT_CHAN__SHIFT
35106. DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK
35107. DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT
35108. DAGB2_WRCLI6__MAX_BW_ENABLE_MASK
35109. DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT
35110. DAGB2_WRCLI6__MAX_BW_MASK
35111. DAGB2_WRCLI6__MAX_BW__SHIFT
35112. DAGB2_WRCLI6__MAX_OSD_MASK
35113. DAGB2_WRCLI6__MAX_OSD__SHIFT
35114. DAGB2_WRCLI6__MIN_BW_ENABLE_MASK
35115. DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT
35116. DAGB2_WRCLI6__MIN_BW_MASK
35117. DAGB2_WRCLI6__MIN_BW__SHIFT
35118. DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK
35119. DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
35120. DAGB2_WRCLI6__URG_HIGH_MASK
35121. DAGB2_WRCLI6__URG_HIGH__SHIFT
35122. DAGB2_WRCLI6__URG_LOW_MASK
35123. DAGB2_WRCLI6__URG_LOW__SHIFT
35124. DAGB2_WRCLI6__VIRT_CHAN_MASK
35125. DAGB2_WRCLI6__VIRT_CHAN__SHIFT
35126. DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK
35127. DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT
35128. DAGB2_WRCLI7__MAX_BW_ENABLE_MASK
35129. DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT
35130. DAGB2_WRCLI7__MAX_BW_MASK
35131. DAGB2_WRCLI7__MAX_BW__SHIFT
35132. DAGB2_WRCLI7__MAX_OSD_MASK
35133. DAGB2_WRCLI7__MAX_OSD__SHIFT
35134. DAGB2_WRCLI7__MIN_BW_ENABLE_MASK
35135. DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT
35136. DAGB2_WRCLI7__MIN_BW_MASK
35137. DAGB2_WRCLI7__MIN_BW__SHIFT
35138. DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK
35139. DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
35140. DAGB2_WRCLI7__URG_HIGH_MASK
35141. DAGB2_WRCLI7__URG_HIGH__SHIFT
35142. DAGB2_WRCLI7__URG_LOW_MASK
35143. DAGB2_WRCLI7__URG_LOW__SHIFT
35144. DAGB2_WRCLI7__VIRT_CHAN_MASK
35145. DAGB2_WRCLI7__VIRT_CHAN__SHIFT
35146. DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK
35147. DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT
35148. DAGB2_WRCLI8__MAX_BW_ENABLE_MASK
35149. DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT
35150. DAGB2_WRCLI8__MAX_BW_MASK
35151. DAGB2_WRCLI8__MAX_BW__SHIFT
35152. DAGB2_WRCLI8__MAX_OSD_MASK
35153. DAGB2_WRCLI8__MAX_OSD__SHIFT
35154. DAGB2_WRCLI8__MIN_BW_ENABLE_MASK
35155. DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT
35156. DAGB2_WRCLI8__MIN_BW_MASK
35157. DAGB2_WRCLI8__MIN_BW__SHIFT
35158. DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK
35159. DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
35160. DAGB2_WRCLI8__URG_HIGH_MASK
35161. DAGB2_WRCLI8__URG_HIGH__SHIFT
35162. DAGB2_WRCLI8__URG_LOW_MASK
35163. DAGB2_WRCLI8__URG_LOW__SHIFT
35164. DAGB2_WRCLI8__VIRT_CHAN_MASK
35165. DAGB2_WRCLI8__VIRT_CHAN__SHIFT
35166. DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK
35167. DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT
35168. DAGB2_WRCLI9__MAX_BW_ENABLE_MASK
35169. DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT
35170. DAGB2_WRCLI9__MAX_BW_MASK
35171. DAGB2_WRCLI9__MAX_BW__SHIFT
35172. DAGB2_WRCLI9__MAX_OSD_MASK
35173. DAGB2_WRCLI9__MAX_OSD__SHIFT
35174. DAGB2_WRCLI9__MIN_BW_ENABLE_MASK
35175. DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT
35176. DAGB2_WRCLI9__MIN_BW_MASK
35177. DAGB2_WRCLI9__MIN_BW__SHIFT
35178. DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK
35179. DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
35180. DAGB2_WRCLI9__URG_HIGH_MASK
35181. DAGB2_WRCLI9__URG_HIGH__SHIFT
35182. DAGB2_WRCLI9__URG_LOW_MASK
35183. DAGB2_WRCLI9__URG_LOW__SHIFT
35184. DAGB2_WRCLI9__VIRT_CHAN_MASK
35185. DAGB2_WRCLI9__VIRT_CHAN__SHIFT
35186. DAGB2_WRCLI_ASK_PENDING__BUSY_MASK
35187. DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT
35188. DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
35189. DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
35190. DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK
35191. DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
35192. DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK
35193. DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
35194. DAGB2_WRCLI_GO_PENDING__BUSY_MASK
35195. DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT
35196. DAGB2_WRCLI_OARB_PENDING__BUSY_MASK
35197. DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT
35198. DAGB2_WRCLI_OSD_PENDING__BUSY_MASK
35199. DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT
35200. DAGB2_WRCLI_TLB_PENDING__BUSY_MASK
35201. DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT
35202. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
35203. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
35204. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
35205. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
35206. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
35207. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
35208. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
35209. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
35210. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
35211. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
35212. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
35213. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
35214. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
35215. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
35216. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
35217. DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
35218. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
35219. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
35220. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
35221. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
35222. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
35223. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
35224. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
35225. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
35226. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
35227. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
35228. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
35229. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
35230. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
35231. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
35232. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
35233. DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
35234. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
35235. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
35236. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
35237. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
35238. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
35239. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
35240. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
35241. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
35242. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
35243. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
35244. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
35245. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
35246. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
35247. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
35248. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
35249. DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
35250. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
35251. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
35252. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
35253. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
35254. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
35255. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
35256. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
35257. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
35258. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
35259. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
35260. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
35261. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
35262. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
35263. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
35264. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
35265. DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
35266. DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK
35267. DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
35268. DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
35269. DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
35270. DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
35271. DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
35272. DAGB2_WR_ADDR_DAGB__WHOAMI_MASK
35273. DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT
35274. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
35275. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
35276. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
35277. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
35278. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
35279. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
35280. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
35281. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
35282. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
35283. DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
35284. DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
35285. DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
35286. DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
35287. DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
35288. DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
35289. DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
35290. DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
35291. DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
35292. DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
35293. DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
35294. DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK
35295. DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
35296. DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
35297. DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
35298. DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
35299. DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
35300. DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
35301. DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
35302. DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK
35303. DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT
35304. DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
35305. DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
35306. DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
35307. DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
35308. DAGB2_WR_CNTL__IO_LEVEL_MASK
35309. DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
35310. DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
35311. DAGB2_WR_CNTL__IO_LEVEL__SHIFT
35312. DAGB2_WR_CNTL__SCLK_FREQ_MASK
35313. DAGB2_WR_CNTL__SCLK_FREQ__SHIFT
35314. DAGB2_WR_CNTL__SHARE_VC_NUM_MASK
35315. DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT
35316. DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK
35317. DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
35318. DAGB2_WR_CREDITS_FULL__FULL_MASK
35319. DAGB2_WR_CREDITS_FULL__FULL__SHIFT
35320. DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
35321. DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
35322. DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
35323. DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
35324. DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
35325. DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
35326. DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
35327. DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
35328. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
35329. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
35330. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
35331. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
35332. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
35333. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
35334. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
35335. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
35336. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
35337. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
35338. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
35339. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
35340. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
35341. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
35342. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
35343. DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
35344. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
35345. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
35346. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
35347. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
35348. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
35349. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
35350. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
35351. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
35352. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
35353. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
35354. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
35355. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
35356. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
35357. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
35358. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
35359. DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
35360. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
35361. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
35362. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
35363. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
35364. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
35365. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
35366. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
35367. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
35368. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
35369. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
35370. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
35371. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
35372. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
35373. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
35374. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
35375. DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
35376. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
35377. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
35378. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
35379. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
35380. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
35381. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
35382. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
35383. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
35384. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
35385. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
35386. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
35387. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
35388. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
35389. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
35390. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
35391. DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
35392. DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK
35393. DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
35394. DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
35395. DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
35396. DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
35397. DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
35398. DAGB2_WR_DATA_DAGB__WHOAMI_MASK
35399. DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT
35400. DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK
35401. DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT
35402. DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK
35403. DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT
35404. DAGB2_WR_GMI_CNTL__LEVEL_MASK
35405. DAGB2_WR_GMI_CNTL__LEVEL__SHIFT
35406. DAGB2_WR_GMI_CNTL__MAX_BURST_MASK
35407. DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT
35408. DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
35409. DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
35410. DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
35411. DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
35412. DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK
35413. DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
35414. DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
35415. DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
35416. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
35417. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
35418. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
35419. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
35420. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
35421. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
35422. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
35423. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
35424. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
35425. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
35426. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
35427. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
35428. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
35429. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
35430. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
35431. DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
35432. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
35433. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
35434. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
35435. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
35436. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
35437. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
35438. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
35439. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
35440. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
35441. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
35442. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
35443. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
35444. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
35445. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
35446. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
35447. DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
35448. DAGB2_WR_TLB_CREDIT__TLB0_MASK
35449. DAGB2_WR_TLB_CREDIT__TLB0__SHIFT
35450. DAGB2_WR_TLB_CREDIT__TLB1_MASK
35451. DAGB2_WR_TLB_CREDIT__TLB1__SHIFT
35452. DAGB2_WR_TLB_CREDIT__TLB2_MASK
35453. DAGB2_WR_TLB_CREDIT__TLB2__SHIFT
35454. DAGB2_WR_TLB_CREDIT__TLB3_MASK
35455. DAGB2_WR_TLB_CREDIT__TLB3__SHIFT
35456. DAGB2_WR_TLB_CREDIT__TLB4_MASK
35457. DAGB2_WR_TLB_CREDIT__TLB4__SHIFT
35458. DAGB2_WR_TLB_CREDIT__TLB5_MASK
35459. DAGB2_WR_TLB_CREDIT__TLB5__SHIFT
35460. DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK
35461. DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT
35462. DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
35463. DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
35464. DAGB2_WR_VC0_CNTL__MAX_BW_MASK
35465. DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT
35466. DAGB2_WR_VC0_CNTL__MAX_OSD_MASK
35467. DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT
35468. DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
35469. DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
35470. DAGB2_WR_VC0_CNTL__MIN_BW_MASK
35471. DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT
35472. DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
35473. DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
35474. DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK
35475. DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT
35476. DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK
35477. DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT
35478. DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
35479. DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
35480. DAGB2_WR_VC1_CNTL__MAX_BW_MASK
35481. DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT
35482. DAGB2_WR_VC1_CNTL__MAX_OSD_MASK
35483. DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT
35484. DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
35485. DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
35486. DAGB2_WR_VC1_CNTL__MIN_BW_MASK
35487. DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT
35488. DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
35489. DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
35490. DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK
35491. DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT
35492. DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK
35493. DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT
35494. DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
35495. DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
35496. DAGB2_WR_VC2_CNTL__MAX_BW_MASK
35497. DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT
35498. DAGB2_WR_VC2_CNTL__MAX_OSD_MASK
35499. DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT
35500. DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
35501. DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
35502. DAGB2_WR_VC2_CNTL__MIN_BW_MASK
35503. DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT
35504. DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
35505. DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
35506. DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK
35507. DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT
35508. DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK
35509. DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT
35510. DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
35511. DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
35512. DAGB2_WR_VC3_CNTL__MAX_BW_MASK
35513. DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT
35514. DAGB2_WR_VC3_CNTL__MAX_OSD_MASK
35515. DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT
35516. DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
35517. DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
35518. DAGB2_WR_VC3_CNTL__MIN_BW_MASK
35519. DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT
35520. DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
35521. DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
35522. DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK
35523. DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT
35524. DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK
35525. DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT
35526. DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
35527. DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
35528. DAGB2_WR_VC4_CNTL__MAX_BW_MASK
35529. DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT
35530. DAGB2_WR_VC4_CNTL__MAX_OSD_MASK
35531. DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT
35532. DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
35533. DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
35534. DAGB2_WR_VC4_CNTL__MIN_BW_MASK
35535. DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT
35536. DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
35537. DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
35538. DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK
35539. DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT
35540. DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK
35541. DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT
35542. DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
35543. DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
35544. DAGB2_WR_VC5_CNTL__MAX_BW_MASK
35545. DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT
35546. DAGB2_WR_VC5_CNTL__MAX_OSD_MASK
35547. DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT
35548. DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
35549. DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
35550. DAGB2_WR_VC5_CNTL__MIN_BW_MASK
35551. DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT
35552. DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
35553. DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
35554. DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK
35555. DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT
35556. DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK
35557. DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT
35558. DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
35559. DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
35560. DAGB2_WR_VC6_CNTL__MAX_BW_MASK
35561. DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT
35562. DAGB2_WR_VC6_CNTL__MAX_OSD_MASK
35563. DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT
35564. DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
35565. DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
35566. DAGB2_WR_VC6_CNTL__MIN_BW_MASK
35567. DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT
35568. DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
35569. DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
35570. DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK
35571. DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT
35572. DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK
35573. DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT
35574. DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
35575. DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
35576. DAGB2_WR_VC7_CNTL__MAX_BW_MASK
35577. DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT
35578. DAGB2_WR_VC7_CNTL__MAX_OSD_MASK
35579. DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT
35580. DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
35581. DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
35582. DAGB2_WR_VC7_CNTL__MIN_BW_MASK
35583. DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT
35584. DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
35585. DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
35586. DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK
35587. DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT
35588. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
35589. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
35590. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
35591. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
35592. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
35593. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
35594. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
35595. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
35596. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
35597. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
35598. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
35599. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
35600. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
35601. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
35602. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
35603. DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
35604. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
35605. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
35606. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
35607. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
35608. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
35609. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
35610. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
35611. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
35612. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
35613. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
35614. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
35615. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
35616. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
35617. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
35618. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
35619. DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
35620. DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
35621. DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
35622. DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
35623. DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
35624. DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
35625. DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
35626. DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK
35627. DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
35628. DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
35629. DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
35630. DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
35631. DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
35632. DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
35633. DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
35634. DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK
35635. DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
35636. DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
35637. DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
35638. DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK
35639. DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
35640. DAGB3_CNTL_MISC2__SWAP_CTL_MASK
35641. DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT
35642. DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK
35643. DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
35644. DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK
35645. DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
35646. DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK
35647. DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT
35648. DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
35649. DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
35650. DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK
35651. DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT
35652. DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK
35653. DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT
35654. DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK
35655. DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT
35656. DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK
35657. DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT
35658. DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK
35659. DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT
35660. DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK
35661. DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT
35662. DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK
35663. DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT
35664. DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK
35665. DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT
35666. DAGB3_DAGB_DLY__CLI_MASK
35667. DAGB3_DAGB_DLY__CLI__SHIFT
35668. DAGB3_DAGB_DLY__DLY_MASK
35669. DAGB3_DAGB_DLY__DLY__SHIFT
35670. DAGB3_DAGB_DLY__POS_MASK
35671. DAGB3_DAGB_DLY__POS__SHIFT
35672. DAGB3_FIFO_EMPTY__EMPTY_MASK
35673. DAGB3_FIFO_EMPTY__EMPTY__SHIFT
35674. DAGB3_FIFO_FULL__FULL_MASK
35675. DAGB3_FIFO_FULL__FULL__SHIFT
35676. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
35677. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
35678. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
35679. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
35680. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
35681. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
35682. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
35683. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
35684. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
35685. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
35686. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
35687. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
35688. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
35689. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
35690. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
35691. DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
35692. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
35693. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
35694. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
35695. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
35696. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
35697. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
35698. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
35699. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
35700. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
35701. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
35702. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
35703. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
35704. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
35705. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
35706. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
35707. DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
35708. DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK
35709. DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT
35710. DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK
35711. DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT
35712. DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK
35713. DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
35714. DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
35715. DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
35716. DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK
35717. DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
35718. DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK
35719. DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT
35720. DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK
35721. DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT
35722. DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK
35723. DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
35724. DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
35725. DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
35726. DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK
35727. DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
35728. DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK
35729. DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT
35730. DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK
35731. DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT
35732. DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK
35733. DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
35734. DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
35735. DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
35736. DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK
35737. DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
35738. DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK
35739. DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
35740. DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK
35741. DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT
35742. DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK
35743. DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT
35744. DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
35745. DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
35746. DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
35747. DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
35748. DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
35749. DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
35750. DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
35751. DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
35752. DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
35753. DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
35754. DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
35755. DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
35756. DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK
35757. DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT
35758. DAGB3_RDCLI0__MAX_BW_ENABLE_MASK
35759. DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT
35760. DAGB3_RDCLI0__MAX_BW_MASK
35761. DAGB3_RDCLI0__MAX_BW__SHIFT
35762. DAGB3_RDCLI0__MAX_OSD_MASK
35763. DAGB3_RDCLI0__MAX_OSD__SHIFT
35764. DAGB3_RDCLI0__MIN_BW_ENABLE_MASK
35765. DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT
35766. DAGB3_RDCLI0__MIN_BW_MASK
35767. DAGB3_RDCLI0__MIN_BW__SHIFT
35768. DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK
35769. DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
35770. DAGB3_RDCLI0__URG_HIGH_MASK
35771. DAGB3_RDCLI0__URG_HIGH__SHIFT
35772. DAGB3_RDCLI0__URG_LOW_MASK
35773. DAGB3_RDCLI0__URG_LOW__SHIFT
35774. DAGB3_RDCLI0__VIRT_CHAN_MASK
35775. DAGB3_RDCLI0__VIRT_CHAN__SHIFT
35776. DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK
35777. DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT
35778. DAGB3_RDCLI10__MAX_BW_ENABLE_MASK
35779. DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT
35780. DAGB3_RDCLI10__MAX_BW_MASK
35781. DAGB3_RDCLI10__MAX_BW__SHIFT
35782. DAGB3_RDCLI10__MAX_OSD_MASK
35783. DAGB3_RDCLI10__MAX_OSD__SHIFT
35784. DAGB3_RDCLI10__MIN_BW_ENABLE_MASK
35785. DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT
35786. DAGB3_RDCLI10__MIN_BW_MASK
35787. DAGB3_RDCLI10__MIN_BW__SHIFT
35788. DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK
35789. DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
35790. DAGB3_RDCLI10__URG_HIGH_MASK
35791. DAGB3_RDCLI10__URG_HIGH__SHIFT
35792. DAGB3_RDCLI10__URG_LOW_MASK
35793. DAGB3_RDCLI10__URG_LOW__SHIFT
35794. DAGB3_RDCLI10__VIRT_CHAN_MASK
35795. DAGB3_RDCLI10__VIRT_CHAN__SHIFT
35796. DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK
35797. DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT
35798. DAGB3_RDCLI11__MAX_BW_ENABLE_MASK
35799. DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT
35800. DAGB3_RDCLI11__MAX_BW_MASK
35801. DAGB3_RDCLI11__MAX_BW__SHIFT
35802. DAGB3_RDCLI11__MAX_OSD_MASK
35803. DAGB3_RDCLI11__MAX_OSD__SHIFT
35804. DAGB3_RDCLI11__MIN_BW_ENABLE_MASK
35805. DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT
35806. DAGB3_RDCLI11__MIN_BW_MASK
35807. DAGB3_RDCLI11__MIN_BW__SHIFT
35808. DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK
35809. DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
35810. DAGB3_RDCLI11__URG_HIGH_MASK
35811. DAGB3_RDCLI11__URG_HIGH__SHIFT
35812. DAGB3_RDCLI11__URG_LOW_MASK
35813. DAGB3_RDCLI11__URG_LOW__SHIFT
35814. DAGB3_RDCLI11__VIRT_CHAN_MASK
35815. DAGB3_RDCLI11__VIRT_CHAN__SHIFT
35816. DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK
35817. DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT
35818. DAGB3_RDCLI12__MAX_BW_ENABLE_MASK
35819. DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT
35820. DAGB3_RDCLI12__MAX_BW_MASK
35821. DAGB3_RDCLI12__MAX_BW__SHIFT
35822. DAGB3_RDCLI12__MAX_OSD_MASK
35823. DAGB3_RDCLI12__MAX_OSD__SHIFT
35824. DAGB3_RDCLI12__MIN_BW_ENABLE_MASK
35825. DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT
35826. DAGB3_RDCLI12__MIN_BW_MASK
35827. DAGB3_RDCLI12__MIN_BW__SHIFT
35828. DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK
35829. DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
35830. DAGB3_RDCLI12__URG_HIGH_MASK
35831. DAGB3_RDCLI12__URG_HIGH__SHIFT
35832. DAGB3_RDCLI12__URG_LOW_MASK
35833. DAGB3_RDCLI12__URG_LOW__SHIFT
35834. DAGB3_RDCLI12__VIRT_CHAN_MASK
35835. DAGB3_RDCLI12__VIRT_CHAN__SHIFT
35836. DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK
35837. DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT
35838. DAGB3_RDCLI13__MAX_BW_ENABLE_MASK
35839. DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT
35840. DAGB3_RDCLI13__MAX_BW_MASK
35841. DAGB3_RDCLI13__MAX_BW__SHIFT
35842. DAGB3_RDCLI13__MAX_OSD_MASK
35843. DAGB3_RDCLI13__MAX_OSD__SHIFT
35844. DAGB3_RDCLI13__MIN_BW_ENABLE_MASK
35845. DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT
35846. DAGB3_RDCLI13__MIN_BW_MASK
35847. DAGB3_RDCLI13__MIN_BW__SHIFT
35848. DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK
35849. DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
35850. DAGB3_RDCLI13__URG_HIGH_MASK
35851. DAGB3_RDCLI13__URG_HIGH__SHIFT
35852. DAGB3_RDCLI13__URG_LOW_MASK
35853. DAGB3_RDCLI13__URG_LOW__SHIFT
35854. DAGB3_RDCLI13__VIRT_CHAN_MASK
35855. DAGB3_RDCLI13__VIRT_CHAN__SHIFT
35856. DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK
35857. DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT
35858. DAGB3_RDCLI14__MAX_BW_ENABLE_MASK
35859. DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT
35860. DAGB3_RDCLI14__MAX_BW_MASK
35861. DAGB3_RDCLI14__MAX_BW__SHIFT
35862. DAGB3_RDCLI14__MAX_OSD_MASK
35863. DAGB3_RDCLI14__MAX_OSD__SHIFT
35864. DAGB3_RDCLI14__MIN_BW_ENABLE_MASK
35865. DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT
35866. DAGB3_RDCLI14__MIN_BW_MASK
35867. DAGB3_RDCLI14__MIN_BW__SHIFT
35868. DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK
35869. DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
35870. DAGB3_RDCLI14__URG_HIGH_MASK
35871. DAGB3_RDCLI14__URG_HIGH__SHIFT
35872. DAGB3_RDCLI14__URG_LOW_MASK
35873. DAGB3_RDCLI14__URG_LOW__SHIFT
35874. DAGB3_RDCLI14__VIRT_CHAN_MASK
35875. DAGB3_RDCLI14__VIRT_CHAN__SHIFT
35876. DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK
35877. DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT
35878. DAGB3_RDCLI15__MAX_BW_ENABLE_MASK
35879. DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT
35880. DAGB3_RDCLI15__MAX_BW_MASK
35881. DAGB3_RDCLI15__MAX_BW__SHIFT
35882. DAGB3_RDCLI15__MAX_OSD_MASK
35883. DAGB3_RDCLI15__MAX_OSD__SHIFT
35884. DAGB3_RDCLI15__MIN_BW_ENABLE_MASK
35885. DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT
35886. DAGB3_RDCLI15__MIN_BW_MASK
35887. DAGB3_RDCLI15__MIN_BW__SHIFT
35888. DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK
35889. DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
35890. DAGB3_RDCLI15__URG_HIGH_MASK
35891. DAGB3_RDCLI15__URG_HIGH__SHIFT
35892. DAGB3_RDCLI15__URG_LOW_MASK
35893. DAGB3_RDCLI15__URG_LOW__SHIFT
35894. DAGB3_RDCLI15__VIRT_CHAN_MASK
35895. DAGB3_RDCLI15__VIRT_CHAN__SHIFT
35896. DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK
35897. DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT
35898. DAGB3_RDCLI1__MAX_BW_ENABLE_MASK
35899. DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT
35900. DAGB3_RDCLI1__MAX_BW_MASK
35901. DAGB3_RDCLI1__MAX_BW__SHIFT
35902. DAGB3_RDCLI1__MAX_OSD_MASK
35903. DAGB3_RDCLI1__MAX_OSD__SHIFT
35904. DAGB3_RDCLI1__MIN_BW_ENABLE_MASK
35905. DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT
35906. DAGB3_RDCLI1__MIN_BW_MASK
35907. DAGB3_RDCLI1__MIN_BW__SHIFT
35908. DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK
35909. DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
35910. DAGB3_RDCLI1__URG_HIGH_MASK
35911. DAGB3_RDCLI1__URG_HIGH__SHIFT
35912. DAGB3_RDCLI1__URG_LOW_MASK
35913. DAGB3_RDCLI1__URG_LOW__SHIFT
35914. DAGB3_RDCLI1__VIRT_CHAN_MASK
35915. DAGB3_RDCLI1__VIRT_CHAN__SHIFT
35916. DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK
35917. DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT
35918. DAGB3_RDCLI2__MAX_BW_ENABLE_MASK
35919. DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT
35920. DAGB3_RDCLI2__MAX_BW_MASK
35921. DAGB3_RDCLI2__MAX_BW__SHIFT
35922. DAGB3_RDCLI2__MAX_OSD_MASK
35923. DAGB3_RDCLI2__MAX_OSD__SHIFT
35924. DAGB3_RDCLI2__MIN_BW_ENABLE_MASK
35925. DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT
35926. DAGB3_RDCLI2__MIN_BW_MASK
35927. DAGB3_RDCLI2__MIN_BW__SHIFT
35928. DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK
35929. DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
35930. DAGB3_RDCLI2__URG_HIGH_MASK
35931. DAGB3_RDCLI2__URG_HIGH__SHIFT
35932. DAGB3_RDCLI2__URG_LOW_MASK
35933. DAGB3_RDCLI2__URG_LOW__SHIFT
35934. DAGB3_RDCLI2__VIRT_CHAN_MASK
35935. DAGB3_RDCLI2__VIRT_CHAN__SHIFT
35936. DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK
35937. DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT
35938. DAGB3_RDCLI3__MAX_BW_ENABLE_MASK
35939. DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT
35940. DAGB3_RDCLI3__MAX_BW_MASK
35941. DAGB3_RDCLI3__MAX_BW__SHIFT
35942. DAGB3_RDCLI3__MAX_OSD_MASK
35943. DAGB3_RDCLI3__MAX_OSD__SHIFT
35944. DAGB3_RDCLI3__MIN_BW_ENABLE_MASK
35945. DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT
35946. DAGB3_RDCLI3__MIN_BW_MASK
35947. DAGB3_RDCLI3__MIN_BW__SHIFT
35948. DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK
35949. DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
35950. DAGB3_RDCLI3__URG_HIGH_MASK
35951. DAGB3_RDCLI3__URG_HIGH__SHIFT
35952. DAGB3_RDCLI3__URG_LOW_MASK
35953. DAGB3_RDCLI3__URG_LOW__SHIFT
35954. DAGB3_RDCLI3__VIRT_CHAN_MASK
35955. DAGB3_RDCLI3__VIRT_CHAN__SHIFT
35956. DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK
35957. DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT
35958. DAGB3_RDCLI4__MAX_BW_ENABLE_MASK
35959. DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT
35960. DAGB3_RDCLI4__MAX_BW_MASK
35961. DAGB3_RDCLI4__MAX_BW__SHIFT
35962. DAGB3_RDCLI4__MAX_OSD_MASK
35963. DAGB3_RDCLI4__MAX_OSD__SHIFT
35964. DAGB3_RDCLI4__MIN_BW_ENABLE_MASK
35965. DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT
35966. DAGB3_RDCLI4__MIN_BW_MASK
35967. DAGB3_RDCLI4__MIN_BW__SHIFT
35968. DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK
35969. DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
35970. DAGB3_RDCLI4__URG_HIGH_MASK
35971. DAGB3_RDCLI4__URG_HIGH__SHIFT
35972. DAGB3_RDCLI4__URG_LOW_MASK
35973. DAGB3_RDCLI4__URG_LOW__SHIFT
35974. DAGB3_RDCLI4__VIRT_CHAN_MASK
35975. DAGB3_RDCLI4__VIRT_CHAN__SHIFT
35976. DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK
35977. DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT
35978. DAGB3_RDCLI5__MAX_BW_ENABLE_MASK
35979. DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT
35980. DAGB3_RDCLI5__MAX_BW_MASK
35981. DAGB3_RDCLI5__MAX_BW__SHIFT
35982. DAGB3_RDCLI5__MAX_OSD_MASK
35983. DAGB3_RDCLI5__MAX_OSD__SHIFT
35984. DAGB3_RDCLI5__MIN_BW_ENABLE_MASK
35985. DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT
35986. DAGB3_RDCLI5__MIN_BW_MASK
35987. DAGB3_RDCLI5__MIN_BW__SHIFT
35988. DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK
35989. DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
35990. DAGB3_RDCLI5__URG_HIGH_MASK
35991. DAGB3_RDCLI5__URG_HIGH__SHIFT
35992. DAGB3_RDCLI5__URG_LOW_MASK
35993. DAGB3_RDCLI5__URG_LOW__SHIFT
35994. DAGB3_RDCLI5__VIRT_CHAN_MASK
35995. DAGB3_RDCLI5__VIRT_CHAN__SHIFT
35996. DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK
35997. DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT
35998. DAGB3_RDCLI6__MAX_BW_ENABLE_MASK
35999. DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT
36000. DAGB3_RDCLI6__MAX_BW_MASK
36001. DAGB3_RDCLI6__MAX_BW__SHIFT
36002. DAGB3_RDCLI6__MAX_OSD_MASK
36003. DAGB3_RDCLI6__MAX_OSD__SHIFT
36004. DAGB3_RDCLI6__MIN_BW_ENABLE_MASK
36005. DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT
36006. DAGB3_RDCLI6__MIN_BW_MASK
36007. DAGB3_RDCLI6__MIN_BW__SHIFT
36008. DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK
36009. DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
36010. DAGB3_RDCLI6__URG_HIGH_MASK
36011. DAGB3_RDCLI6__URG_HIGH__SHIFT
36012. DAGB3_RDCLI6__URG_LOW_MASK
36013. DAGB3_RDCLI6__URG_LOW__SHIFT
36014. DAGB3_RDCLI6__VIRT_CHAN_MASK
36015. DAGB3_RDCLI6__VIRT_CHAN__SHIFT
36016. DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK
36017. DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT
36018. DAGB3_RDCLI7__MAX_BW_ENABLE_MASK
36019. DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT
36020. DAGB3_RDCLI7__MAX_BW_MASK
36021. DAGB3_RDCLI7__MAX_BW__SHIFT
36022. DAGB3_RDCLI7__MAX_OSD_MASK
36023. DAGB3_RDCLI7__MAX_OSD__SHIFT
36024. DAGB3_RDCLI7__MIN_BW_ENABLE_MASK
36025. DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT
36026. DAGB3_RDCLI7__MIN_BW_MASK
36027. DAGB3_RDCLI7__MIN_BW__SHIFT
36028. DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK
36029. DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
36030. DAGB3_RDCLI7__URG_HIGH_MASK
36031. DAGB3_RDCLI7__URG_HIGH__SHIFT
36032. DAGB3_RDCLI7__URG_LOW_MASK
36033. DAGB3_RDCLI7__URG_LOW__SHIFT
36034. DAGB3_RDCLI7__VIRT_CHAN_MASK
36035. DAGB3_RDCLI7__VIRT_CHAN__SHIFT
36036. DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK
36037. DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT
36038. DAGB3_RDCLI8__MAX_BW_ENABLE_MASK
36039. DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT
36040. DAGB3_RDCLI8__MAX_BW_MASK
36041. DAGB3_RDCLI8__MAX_BW__SHIFT
36042. DAGB3_RDCLI8__MAX_OSD_MASK
36043. DAGB3_RDCLI8__MAX_OSD__SHIFT
36044. DAGB3_RDCLI8__MIN_BW_ENABLE_MASK
36045. DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT
36046. DAGB3_RDCLI8__MIN_BW_MASK
36047. DAGB3_RDCLI8__MIN_BW__SHIFT
36048. DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK
36049. DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
36050. DAGB3_RDCLI8__URG_HIGH_MASK
36051. DAGB3_RDCLI8__URG_HIGH__SHIFT
36052. DAGB3_RDCLI8__URG_LOW_MASK
36053. DAGB3_RDCLI8__URG_LOW__SHIFT
36054. DAGB3_RDCLI8__VIRT_CHAN_MASK
36055. DAGB3_RDCLI8__VIRT_CHAN__SHIFT
36056. DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK
36057. DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT
36058. DAGB3_RDCLI9__MAX_BW_ENABLE_MASK
36059. DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT
36060. DAGB3_RDCLI9__MAX_BW_MASK
36061. DAGB3_RDCLI9__MAX_BW__SHIFT
36062. DAGB3_RDCLI9__MAX_OSD_MASK
36063. DAGB3_RDCLI9__MAX_OSD__SHIFT
36064. DAGB3_RDCLI9__MIN_BW_ENABLE_MASK
36065. DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT
36066. DAGB3_RDCLI9__MIN_BW_MASK
36067. DAGB3_RDCLI9__MIN_BW__SHIFT
36068. DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK
36069. DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
36070. DAGB3_RDCLI9__URG_HIGH_MASK
36071. DAGB3_RDCLI9__URG_HIGH__SHIFT
36072. DAGB3_RDCLI9__URG_LOW_MASK
36073. DAGB3_RDCLI9__URG_LOW__SHIFT
36074. DAGB3_RDCLI9__VIRT_CHAN_MASK
36075. DAGB3_RDCLI9__VIRT_CHAN__SHIFT
36076. DAGB3_RDCLI_ASK_PENDING__BUSY_MASK
36077. DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT
36078. DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK
36079. DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
36080. DAGB3_RDCLI_GO_PENDING__BUSY_MASK
36081. DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT
36082. DAGB3_RDCLI_OARB_PENDING__BUSY_MASK
36083. DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT
36084. DAGB3_RDCLI_OSD_PENDING__BUSY_MASK
36085. DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT
36086. DAGB3_RDCLI_TLB_PENDING__BUSY_MASK
36087. DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT
36088. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
36089. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
36090. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
36091. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
36092. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
36093. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
36094. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
36095. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
36096. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
36097. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
36098. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
36099. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
36100. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
36101. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
36102. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
36103. DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
36104. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
36105. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
36106. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
36107. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
36108. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
36109. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
36110. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
36111. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
36112. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
36113. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
36114. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
36115. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
36116. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
36117. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
36118. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
36119. DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
36120. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
36121. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
36122. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
36123. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
36124. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
36125. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
36126. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
36127. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
36128. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
36129. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
36130. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
36131. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
36132. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
36133. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
36134. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
36135. DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
36136. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
36137. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
36138. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
36139. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
36140. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
36141. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
36142. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
36143. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
36144. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
36145. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
36146. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
36147. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
36148. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
36149. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
36150. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
36151. DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
36152. DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK
36153. DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
36154. DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
36155. DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
36156. DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
36157. DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
36158. DAGB3_RD_ADDR_DAGB__WHOAMI_MASK
36159. DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT
36160. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
36161. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
36162. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
36163. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
36164. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
36165. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
36166. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
36167. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
36168. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
36169. DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
36170. DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
36171. DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
36172. DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
36173. DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
36174. DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
36175. DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
36176. DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
36177. DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
36178. DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
36179. DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
36180. DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK
36181. DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
36182. DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
36183. DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
36184. DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
36185. DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
36186. DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
36187. DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
36188. DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK
36189. DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT
36190. DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
36191. DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
36192. DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
36193. DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
36194. DAGB3_RD_CNTL__IO_LEVEL_MASK
36195. DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
36196. DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
36197. DAGB3_RD_CNTL__IO_LEVEL__SHIFT
36198. DAGB3_RD_CNTL__SCLK_FREQ_MASK
36199. DAGB3_RD_CNTL__SCLK_FREQ__SHIFT
36200. DAGB3_RD_CNTL__SHARE_VC_NUM_MASK
36201. DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT
36202. DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK
36203. DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
36204. DAGB3_RD_CREDITS_FULL__FULL_MASK
36205. DAGB3_RD_CREDITS_FULL__FULL__SHIFT
36206. DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK
36207. DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT
36208. DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK
36209. DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT
36210. DAGB3_RD_GMI_CNTL__LEVEL_MASK
36211. DAGB3_RD_GMI_CNTL__LEVEL__SHIFT
36212. DAGB3_RD_GMI_CNTL__MAX_BURST_MASK
36213. DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT
36214. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
36215. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
36216. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
36217. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
36218. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
36219. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
36220. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
36221. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
36222. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
36223. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
36224. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
36225. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
36226. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
36227. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
36228. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
36229. DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
36230. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
36231. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
36232. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
36233. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
36234. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
36235. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
36236. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
36237. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
36238. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
36239. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
36240. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
36241. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
36242. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
36243. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
36244. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
36245. DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
36246. DAGB3_RD_TLB_CREDIT__TLB0_MASK
36247. DAGB3_RD_TLB_CREDIT__TLB0__SHIFT
36248. DAGB3_RD_TLB_CREDIT__TLB1_MASK
36249. DAGB3_RD_TLB_CREDIT__TLB1__SHIFT
36250. DAGB3_RD_TLB_CREDIT__TLB2_MASK
36251. DAGB3_RD_TLB_CREDIT__TLB2__SHIFT
36252. DAGB3_RD_TLB_CREDIT__TLB3_MASK
36253. DAGB3_RD_TLB_CREDIT__TLB3__SHIFT
36254. DAGB3_RD_TLB_CREDIT__TLB4_MASK
36255. DAGB3_RD_TLB_CREDIT__TLB4__SHIFT
36256. DAGB3_RD_TLB_CREDIT__TLB5_MASK
36257. DAGB3_RD_TLB_CREDIT__TLB5__SHIFT
36258. DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK
36259. DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT
36260. DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
36261. DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
36262. DAGB3_RD_VC0_CNTL__MAX_BW_MASK
36263. DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT
36264. DAGB3_RD_VC0_CNTL__MAX_OSD_MASK
36265. DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT
36266. DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
36267. DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
36268. DAGB3_RD_VC0_CNTL__MIN_BW_MASK
36269. DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT
36270. DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
36271. DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
36272. DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK
36273. DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT
36274. DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK
36275. DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT
36276. DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
36277. DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
36278. DAGB3_RD_VC1_CNTL__MAX_BW_MASK
36279. DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT
36280. DAGB3_RD_VC1_CNTL__MAX_OSD_MASK
36281. DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT
36282. DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
36283. DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
36284. DAGB3_RD_VC1_CNTL__MIN_BW_MASK
36285. DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT
36286. DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
36287. DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
36288. DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK
36289. DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT
36290. DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK
36291. DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT
36292. DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
36293. DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
36294. DAGB3_RD_VC2_CNTL__MAX_BW_MASK
36295. DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT
36296. DAGB3_RD_VC2_CNTL__MAX_OSD_MASK
36297. DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT
36298. DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
36299. DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
36300. DAGB3_RD_VC2_CNTL__MIN_BW_MASK
36301. DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT
36302. DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
36303. DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
36304. DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK
36305. DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT
36306. DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK
36307. DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT
36308. DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
36309. DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
36310. DAGB3_RD_VC3_CNTL__MAX_BW_MASK
36311. DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT
36312. DAGB3_RD_VC3_CNTL__MAX_OSD_MASK
36313. DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT
36314. DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
36315. DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
36316. DAGB3_RD_VC3_CNTL__MIN_BW_MASK
36317. DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT
36318. DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
36319. DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
36320. DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK
36321. DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT
36322. DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK
36323. DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT
36324. DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
36325. DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
36326. DAGB3_RD_VC4_CNTL__MAX_BW_MASK
36327. DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT
36328. DAGB3_RD_VC4_CNTL__MAX_OSD_MASK
36329. DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT
36330. DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
36331. DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
36332. DAGB3_RD_VC4_CNTL__MIN_BW_MASK
36333. DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT
36334. DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
36335. DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
36336. DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK
36337. DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT
36338. DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK
36339. DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT
36340. DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
36341. DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
36342. DAGB3_RD_VC5_CNTL__MAX_BW_MASK
36343. DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT
36344. DAGB3_RD_VC5_CNTL__MAX_OSD_MASK
36345. DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT
36346. DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
36347. DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
36348. DAGB3_RD_VC5_CNTL__MIN_BW_MASK
36349. DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT
36350. DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
36351. DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
36352. DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK
36353. DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT
36354. DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK
36355. DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT
36356. DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
36357. DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
36358. DAGB3_RD_VC6_CNTL__MAX_BW_MASK
36359. DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT
36360. DAGB3_RD_VC6_CNTL__MAX_OSD_MASK
36361. DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT
36362. DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
36363. DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
36364. DAGB3_RD_VC6_CNTL__MIN_BW_MASK
36365. DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT
36366. DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
36367. DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
36368. DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK
36369. DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT
36370. DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK
36371. DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT
36372. DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
36373. DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
36374. DAGB3_RD_VC7_CNTL__MAX_BW_MASK
36375. DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT
36376. DAGB3_RD_VC7_CNTL__MAX_OSD_MASK
36377. DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT
36378. DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
36379. DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
36380. DAGB3_RD_VC7_CNTL__MIN_BW_MASK
36381. DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT
36382. DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
36383. DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
36384. DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK
36385. DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT
36386. DAGB3_RESERVE0__RESERVE_MASK
36387. DAGB3_RESERVE0__RESERVE__SHIFT
36388. DAGB3_RESERVE10__RESERVE_MASK
36389. DAGB3_RESERVE10__RESERVE__SHIFT
36390. DAGB3_RESERVE11__RESERVE_MASK
36391. DAGB3_RESERVE11__RESERVE__SHIFT
36392. DAGB3_RESERVE12__RESERVE_MASK
36393. DAGB3_RESERVE12__RESERVE__SHIFT
36394. DAGB3_RESERVE13__RESERVE_MASK
36395. DAGB3_RESERVE13__RESERVE__SHIFT
36396. DAGB3_RESERVE1__RESERVE_MASK
36397. DAGB3_RESERVE1__RESERVE__SHIFT
36398. DAGB3_RESERVE2__RESERVE_MASK
36399. DAGB3_RESERVE2__RESERVE__SHIFT
36400. DAGB3_RESERVE3__RESERVE_MASK
36401. DAGB3_RESERVE3__RESERVE__SHIFT
36402. DAGB3_RESERVE4__RESERVE_MASK
36403. DAGB3_RESERVE4__RESERVE__SHIFT
36404. DAGB3_RESERVE5__RESERVE_MASK
36405. DAGB3_RESERVE5__RESERVE__SHIFT
36406. DAGB3_RESERVE6__RESERVE_MASK
36407. DAGB3_RESERVE6__RESERVE__SHIFT
36408. DAGB3_RESERVE7__RESERVE_MASK
36409. DAGB3_RESERVE7__RESERVE__SHIFT
36410. DAGB3_RESERVE8__RESERVE_MASK
36411. DAGB3_RESERVE8__RESERVE__SHIFT
36412. DAGB3_RESERVE9__RESERVE_MASK
36413. DAGB3_RESERVE9__RESERVE__SHIFT
36414. DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK
36415. DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT
36416. DAGB3_WRCLI0__MAX_BW_ENABLE_MASK
36417. DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT
36418. DAGB3_WRCLI0__MAX_BW_MASK
36419. DAGB3_WRCLI0__MAX_BW__SHIFT
36420. DAGB3_WRCLI0__MAX_OSD_MASK
36421. DAGB3_WRCLI0__MAX_OSD__SHIFT
36422. DAGB3_WRCLI0__MIN_BW_ENABLE_MASK
36423. DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT
36424. DAGB3_WRCLI0__MIN_BW_MASK
36425. DAGB3_WRCLI0__MIN_BW__SHIFT
36426. DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK
36427. DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
36428. DAGB3_WRCLI0__URG_HIGH_MASK
36429. DAGB3_WRCLI0__URG_HIGH__SHIFT
36430. DAGB3_WRCLI0__URG_LOW_MASK
36431. DAGB3_WRCLI0__URG_LOW__SHIFT
36432. DAGB3_WRCLI0__VIRT_CHAN_MASK
36433. DAGB3_WRCLI0__VIRT_CHAN__SHIFT
36434. DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK
36435. DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT
36436. DAGB3_WRCLI10__MAX_BW_ENABLE_MASK
36437. DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT
36438. DAGB3_WRCLI10__MAX_BW_MASK
36439. DAGB3_WRCLI10__MAX_BW__SHIFT
36440. DAGB3_WRCLI10__MAX_OSD_MASK
36441. DAGB3_WRCLI10__MAX_OSD__SHIFT
36442. DAGB3_WRCLI10__MIN_BW_ENABLE_MASK
36443. DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT
36444. DAGB3_WRCLI10__MIN_BW_MASK
36445. DAGB3_WRCLI10__MIN_BW__SHIFT
36446. DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK
36447. DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
36448. DAGB3_WRCLI10__URG_HIGH_MASK
36449. DAGB3_WRCLI10__URG_HIGH__SHIFT
36450. DAGB3_WRCLI10__URG_LOW_MASK
36451. DAGB3_WRCLI10__URG_LOW__SHIFT
36452. DAGB3_WRCLI10__VIRT_CHAN_MASK
36453. DAGB3_WRCLI10__VIRT_CHAN__SHIFT
36454. DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK
36455. DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT
36456. DAGB3_WRCLI11__MAX_BW_ENABLE_MASK
36457. DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT
36458. DAGB3_WRCLI11__MAX_BW_MASK
36459. DAGB3_WRCLI11__MAX_BW__SHIFT
36460. DAGB3_WRCLI11__MAX_OSD_MASK
36461. DAGB3_WRCLI11__MAX_OSD__SHIFT
36462. DAGB3_WRCLI11__MIN_BW_ENABLE_MASK
36463. DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT
36464. DAGB3_WRCLI11__MIN_BW_MASK
36465. DAGB3_WRCLI11__MIN_BW__SHIFT
36466. DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK
36467. DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
36468. DAGB3_WRCLI11__URG_HIGH_MASK
36469. DAGB3_WRCLI11__URG_HIGH__SHIFT
36470. DAGB3_WRCLI11__URG_LOW_MASK
36471. DAGB3_WRCLI11__URG_LOW__SHIFT
36472. DAGB3_WRCLI11__VIRT_CHAN_MASK
36473. DAGB3_WRCLI11__VIRT_CHAN__SHIFT
36474. DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK
36475. DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT
36476. DAGB3_WRCLI12__MAX_BW_ENABLE_MASK
36477. DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT
36478. DAGB3_WRCLI12__MAX_BW_MASK
36479. DAGB3_WRCLI12__MAX_BW__SHIFT
36480. DAGB3_WRCLI12__MAX_OSD_MASK
36481. DAGB3_WRCLI12__MAX_OSD__SHIFT
36482. DAGB3_WRCLI12__MIN_BW_ENABLE_MASK
36483. DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT
36484. DAGB3_WRCLI12__MIN_BW_MASK
36485. DAGB3_WRCLI12__MIN_BW__SHIFT
36486. DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK
36487. DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
36488. DAGB3_WRCLI12__URG_HIGH_MASK
36489. DAGB3_WRCLI12__URG_HIGH__SHIFT
36490. DAGB3_WRCLI12__URG_LOW_MASK
36491. DAGB3_WRCLI12__URG_LOW__SHIFT
36492. DAGB3_WRCLI12__VIRT_CHAN_MASK
36493. DAGB3_WRCLI12__VIRT_CHAN__SHIFT
36494. DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK
36495. DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT
36496. DAGB3_WRCLI13__MAX_BW_ENABLE_MASK
36497. DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT
36498. DAGB3_WRCLI13__MAX_BW_MASK
36499. DAGB3_WRCLI13__MAX_BW__SHIFT
36500. DAGB3_WRCLI13__MAX_OSD_MASK
36501. DAGB3_WRCLI13__MAX_OSD__SHIFT
36502. DAGB3_WRCLI13__MIN_BW_ENABLE_MASK
36503. DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT
36504. DAGB3_WRCLI13__MIN_BW_MASK
36505. DAGB3_WRCLI13__MIN_BW__SHIFT
36506. DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK
36507. DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
36508. DAGB3_WRCLI13__URG_HIGH_MASK
36509. DAGB3_WRCLI13__URG_HIGH__SHIFT
36510. DAGB3_WRCLI13__URG_LOW_MASK
36511. DAGB3_WRCLI13__URG_LOW__SHIFT
36512. DAGB3_WRCLI13__VIRT_CHAN_MASK
36513. DAGB3_WRCLI13__VIRT_CHAN__SHIFT
36514. DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK
36515. DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT
36516. DAGB3_WRCLI14__MAX_BW_ENABLE_MASK
36517. DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT
36518. DAGB3_WRCLI14__MAX_BW_MASK
36519. DAGB3_WRCLI14__MAX_BW__SHIFT
36520. DAGB3_WRCLI14__MAX_OSD_MASK
36521. DAGB3_WRCLI14__MAX_OSD__SHIFT
36522. DAGB3_WRCLI14__MIN_BW_ENABLE_MASK
36523. DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT
36524. DAGB3_WRCLI14__MIN_BW_MASK
36525. DAGB3_WRCLI14__MIN_BW__SHIFT
36526. DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK
36527. DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
36528. DAGB3_WRCLI14__URG_HIGH_MASK
36529. DAGB3_WRCLI14__URG_HIGH__SHIFT
36530. DAGB3_WRCLI14__URG_LOW_MASK
36531. DAGB3_WRCLI14__URG_LOW__SHIFT
36532. DAGB3_WRCLI14__VIRT_CHAN_MASK
36533. DAGB3_WRCLI14__VIRT_CHAN__SHIFT
36534. DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK
36535. DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT
36536. DAGB3_WRCLI15__MAX_BW_ENABLE_MASK
36537. DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT
36538. DAGB3_WRCLI15__MAX_BW_MASK
36539. DAGB3_WRCLI15__MAX_BW__SHIFT
36540. DAGB3_WRCLI15__MAX_OSD_MASK
36541. DAGB3_WRCLI15__MAX_OSD__SHIFT
36542. DAGB3_WRCLI15__MIN_BW_ENABLE_MASK
36543. DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT
36544. DAGB3_WRCLI15__MIN_BW_MASK
36545. DAGB3_WRCLI15__MIN_BW__SHIFT
36546. DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK
36547. DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
36548. DAGB3_WRCLI15__URG_HIGH_MASK
36549. DAGB3_WRCLI15__URG_HIGH__SHIFT
36550. DAGB3_WRCLI15__URG_LOW_MASK
36551. DAGB3_WRCLI15__URG_LOW__SHIFT
36552. DAGB3_WRCLI15__VIRT_CHAN_MASK
36553. DAGB3_WRCLI15__VIRT_CHAN__SHIFT
36554. DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK
36555. DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT
36556. DAGB3_WRCLI1__MAX_BW_ENABLE_MASK
36557. DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT
36558. DAGB3_WRCLI1__MAX_BW_MASK
36559. DAGB3_WRCLI1__MAX_BW__SHIFT
36560. DAGB3_WRCLI1__MAX_OSD_MASK
36561. DAGB3_WRCLI1__MAX_OSD__SHIFT
36562. DAGB3_WRCLI1__MIN_BW_ENABLE_MASK
36563. DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT
36564. DAGB3_WRCLI1__MIN_BW_MASK
36565. DAGB3_WRCLI1__MIN_BW__SHIFT
36566. DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK
36567. DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
36568. DAGB3_WRCLI1__URG_HIGH_MASK
36569. DAGB3_WRCLI1__URG_HIGH__SHIFT
36570. DAGB3_WRCLI1__URG_LOW_MASK
36571. DAGB3_WRCLI1__URG_LOW__SHIFT
36572. DAGB3_WRCLI1__VIRT_CHAN_MASK
36573. DAGB3_WRCLI1__VIRT_CHAN__SHIFT
36574. DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK
36575. DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT
36576. DAGB3_WRCLI2__MAX_BW_ENABLE_MASK
36577. DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT
36578. DAGB3_WRCLI2__MAX_BW_MASK
36579. DAGB3_WRCLI2__MAX_BW__SHIFT
36580. DAGB3_WRCLI2__MAX_OSD_MASK
36581. DAGB3_WRCLI2__MAX_OSD__SHIFT
36582. DAGB3_WRCLI2__MIN_BW_ENABLE_MASK
36583. DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT
36584. DAGB3_WRCLI2__MIN_BW_MASK
36585. DAGB3_WRCLI2__MIN_BW__SHIFT
36586. DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK
36587. DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
36588. DAGB3_WRCLI2__URG_HIGH_MASK
36589. DAGB3_WRCLI2__URG_HIGH__SHIFT
36590. DAGB3_WRCLI2__URG_LOW_MASK
36591. DAGB3_WRCLI2__URG_LOW__SHIFT
36592. DAGB3_WRCLI2__VIRT_CHAN_MASK
36593. DAGB3_WRCLI2__VIRT_CHAN__SHIFT
36594. DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK
36595. DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT
36596. DAGB3_WRCLI3__MAX_BW_ENABLE_MASK
36597. DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT
36598. DAGB3_WRCLI3__MAX_BW_MASK
36599. DAGB3_WRCLI3__MAX_BW__SHIFT
36600. DAGB3_WRCLI3__MAX_OSD_MASK
36601. DAGB3_WRCLI3__MAX_OSD__SHIFT
36602. DAGB3_WRCLI3__MIN_BW_ENABLE_MASK
36603. DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT
36604. DAGB3_WRCLI3__MIN_BW_MASK
36605. DAGB3_WRCLI3__MIN_BW__SHIFT
36606. DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK
36607. DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
36608. DAGB3_WRCLI3__URG_HIGH_MASK
36609. DAGB3_WRCLI3__URG_HIGH__SHIFT
36610. DAGB3_WRCLI3__URG_LOW_MASK
36611. DAGB3_WRCLI3__URG_LOW__SHIFT
36612. DAGB3_WRCLI3__VIRT_CHAN_MASK
36613. DAGB3_WRCLI3__VIRT_CHAN__SHIFT
36614. DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK
36615. DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT
36616. DAGB3_WRCLI4__MAX_BW_ENABLE_MASK
36617. DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT
36618. DAGB3_WRCLI4__MAX_BW_MASK
36619. DAGB3_WRCLI4__MAX_BW__SHIFT
36620. DAGB3_WRCLI4__MAX_OSD_MASK
36621. DAGB3_WRCLI4__MAX_OSD__SHIFT
36622. DAGB3_WRCLI4__MIN_BW_ENABLE_MASK
36623. DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT
36624. DAGB3_WRCLI4__MIN_BW_MASK
36625. DAGB3_WRCLI4__MIN_BW__SHIFT
36626. DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK
36627. DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
36628. DAGB3_WRCLI4__URG_HIGH_MASK
36629. DAGB3_WRCLI4__URG_HIGH__SHIFT
36630. DAGB3_WRCLI4__URG_LOW_MASK
36631. DAGB3_WRCLI4__URG_LOW__SHIFT
36632. DAGB3_WRCLI4__VIRT_CHAN_MASK
36633. DAGB3_WRCLI4__VIRT_CHAN__SHIFT
36634. DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK
36635. DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT
36636. DAGB3_WRCLI5__MAX_BW_ENABLE_MASK
36637. DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT
36638. DAGB3_WRCLI5__MAX_BW_MASK
36639. DAGB3_WRCLI5__MAX_BW__SHIFT
36640. DAGB3_WRCLI5__MAX_OSD_MASK
36641. DAGB3_WRCLI5__MAX_OSD__SHIFT
36642. DAGB3_WRCLI5__MIN_BW_ENABLE_MASK
36643. DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT
36644. DAGB3_WRCLI5__MIN_BW_MASK
36645. DAGB3_WRCLI5__MIN_BW__SHIFT
36646. DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK
36647. DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
36648. DAGB3_WRCLI5__URG_HIGH_MASK
36649. DAGB3_WRCLI5__URG_HIGH__SHIFT
36650. DAGB3_WRCLI5__URG_LOW_MASK
36651. DAGB3_WRCLI5__URG_LOW__SHIFT
36652. DAGB3_WRCLI5__VIRT_CHAN_MASK
36653. DAGB3_WRCLI5__VIRT_CHAN__SHIFT
36654. DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK
36655. DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT
36656. DAGB3_WRCLI6__MAX_BW_ENABLE_MASK
36657. DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT
36658. DAGB3_WRCLI6__MAX_BW_MASK
36659. DAGB3_WRCLI6__MAX_BW__SHIFT
36660. DAGB3_WRCLI6__MAX_OSD_MASK
36661. DAGB3_WRCLI6__MAX_OSD__SHIFT
36662. DAGB3_WRCLI6__MIN_BW_ENABLE_MASK
36663. DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT
36664. DAGB3_WRCLI6__MIN_BW_MASK
36665. DAGB3_WRCLI6__MIN_BW__SHIFT
36666. DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK
36667. DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
36668. DAGB3_WRCLI6__URG_HIGH_MASK
36669. DAGB3_WRCLI6__URG_HIGH__SHIFT
36670. DAGB3_WRCLI6__URG_LOW_MASK
36671. DAGB3_WRCLI6__URG_LOW__SHIFT
36672. DAGB3_WRCLI6__VIRT_CHAN_MASK
36673. DAGB3_WRCLI6__VIRT_CHAN__SHIFT
36674. DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK
36675. DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT
36676. DAGB3_WRCLI7__MAX_BW_ENABLE_MASK
36677. DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT
36678. DAGB3_WRCLI7__MAX_BW_MASK
36679. DAGB3_WRCLI7__MAX_BW__SHIFT
36680. DAGB3_WRCLI7__MAX_OSD_MASK
36681. DAGB3_WRCLI7__MAX_OSD__SHIFT
36682. DAGB3_WRCLI7__MIN_BW_ENABLE_MASK
36683. DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT
36684. DAGB3_WRCLI7__MIN_BW_MASK
36685. DAGB3_WRCLI7__MIN_BW__SHIFT
36686. DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK
36687. DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
36688. DAGB3_WRCLI7__URG_HIGH_MASK
36689. DAGB3_WRCLI7__URG_HIGH__SHIFT
36690. DAGB3_WRCLI7__URG_LOW_MASK
36691. DAGB3_WRCLI7__URG_LOW__SHIFT
36692. DAGB3_WRCLI7__VIRT_CHAN_MASK
36693. DAGB3_WRCLI7__VIRT_CHAN__SHIFT
36694. DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK
36695. DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT
36696. DAGB3_WRCLI8__MAX_BW_ENABLE_MASK
36697. DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT
36698. DAGB3_WRCLI8__MAX_BW_MASK
36699. DAGB3_WRCLI8__MAX_BW__SHIFT
36700. DAGB3_WRCLI8__MAX_OSD_MASK
36701. DAGB3_WRCLI8__MAX_OSD__SHIFT
36702. DAGB3_WRCLI8__MIN_BW_ENABLE_MASK
36703. DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT
36704. DAGB3_WRCLI8__MIN_BW_MASK
36705. DAGB3_WRCLI8__MIN_BW__SHIFT
36706. DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK
36707. DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
36708. DAGB3_WRCLI8__URG_HIGH_MASK
36709. DAGB3_WRCLI8__URG_HIGH__SHIFT
36710. DAGB3_WRCLI8__URG_LOW_MASK
36711. DAGB3_WRCLI8__URG_LOW__SHIFT
36712. DAGB3_WRCLI8__VIRT_CHAN_MASK
36713. DAGB3_WRCLI8__VIRT_CHAN__SHIFT
36714. DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK
36715. DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT
36716. DAGB3_WRCLI9__MAX_BW_ENABLE_MASK
36717. DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT
36718. DAGB3_WRCLI9__MAX_BW_MASK
36719. DAGB3_WRCLI9__MAX_BW__SHIFT
36720. DAGB3_WRCLI9__MAX_OSD_MASK
36721. DAGB3_WRCLI9__MAX_OSD__SHIFT
36722. DAGB3_WRCLI9__MIN_BW_ENABLE_MASK
36723. DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT
36724. DAGB3_WRCLI9__MIN_BW_MASK
36725. DAGB3_WRCLI9__MIN_BW__SHIFT
36726. DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK
36727. DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
36728. DAGB3_WRCLI9__URG_HIGH_MASK
36729. DAGB3_WRCLI9__URG_HIGH__SHIFT
36730. DAGB3_WRCLI9__URG_LOW_MASK
36731. DAGB3_WRCLI9__URG_LOW__SHIFT
36732. DAGB3_WRCLI9__VIRT_CHAN_MASK
36733. DAGB3_WRCLI9__VIRT_CHAN__SHIFT
36734. DAGB3_WRCLI_ASK_PENDING__BUSY_MASK
36735. DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT
36736. DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
36737. DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
36738. DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK
36739. DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
36740. DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK
36741. DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
36742. DAGB3_WRCLI_GO_PENDING__BUSY_MASK
36743. DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT
36744. DAGB3_WRCLI_OARB_PENDING__BUSY_MASK
36745. DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT
36746. DAGB3_WRCLI_OSD_PENDING__BUSY_MASK
36747. DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT
36748. DAGB3_WRCLI_TLB_PENDING__BUSY_MASK
36749. DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT
36750. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
36751. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
36752. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
36753. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
36754. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
36755. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
36756. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
36757. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
36758. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
36759. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
36760. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
36761. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
36762. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
36763. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
36764. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
36765. DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
36766. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
36767. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
36768. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
36769. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
36770. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
36771. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
36772. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
36773. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
36774. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
36775. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
36776. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
36777. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
36778. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
36779. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
36780. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
36781. DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
36782. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
36783. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
36784. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
36785. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
36786. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
36787. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
36788. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
36789. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
36790. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
36791. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
36792. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
36793. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
36794. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
36795. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
36796. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
36797. DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
36798. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
36799. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
36800. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
36801. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
36802. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
36803. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
36804. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
36805. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
36806. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
36807. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
36808. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
36809. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
36810. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
36811. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
36812. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
36813. DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
36814. DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK
36815. DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
36816. DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
36817. DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
36818. DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
36819. DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
36820. DAGB3_WR_ADDR_DAGB__WHOAMI_MASK
36821. DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT
36822. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
36823. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
36824. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
36825. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
36826. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
36827. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
36828. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
36829. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
36830. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
36831. DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
36832. DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
36833. DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
36834. DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
36835. DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
36836. DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
36837. DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
36838. DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
36839. DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
36840. DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
36841. DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
36842. DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK
36843. DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
36844. DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
36845. DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
36846. DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
36847. DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
36848. DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
36849. DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
36850. DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK
36851. DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT
36852. DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
36853. DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
36854. DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
36855. DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
36856. DAGB3_WR_CNTL__IO_LEVEL_MASK
36857. DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
36858. DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
36859. DAGB3_WR_CNTL__IO_LEVEL__SHIFT
36860. DAGB3_WR_CNTL__SCLK_FREQ_MASK
36861. DAGB3_WR_CNTL__SCLK_FREQ__SHIFT
36862. DAGB3_WR_CNTL__SHARE_VC_NUM_MASK
36863. DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT
36864. DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK
36865. DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
36866. DAGB3_WR_CREDITS_FULL__FULL_MASK
36867. DAGB3_WR_CREDITS_FULL__FULL__SHIFT
36868. DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
36869. DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
36870. DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
36871. DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
36872. DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
36873. DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
36874. DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
36875. DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
36876. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
36877. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
36878. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
36879. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
36880. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
36881. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
36882. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
36883. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
36884. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
36885. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
36886. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
36887. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
36888. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
36889. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
36890. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
36891. DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
36892. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
36893. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
36894. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
36895. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
36896. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
36897. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
36898. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
36899. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
36900. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
36901. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
36902. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
36903. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
36904. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
36905. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
36906. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
36907. DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
36908. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
36909. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
36910. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
36911. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
36912. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
36913. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
36914. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
36915. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
36916. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
36917. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
36918. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
36919. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
36920. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
36921. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
36922. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
36923. DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
36924. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
36925. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
36926. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
36927. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
36928. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
36929. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
36930. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
36931. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
36932. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
36933. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
36934. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
36935. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
36936. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
36937. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
36938. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
36939. DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
36940. DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK
36941. DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
36942. DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
36943. DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
36944. DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
36945. DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
36946. DAGB3_WR_DATA_DAGB__WHOAMI_MASK
36947. DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT
36948. DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK
36949. DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT
36950. DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK
36951. DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT
36952. DAGB3_WR_GMI_CNTL__LEVEL_MASK
36953. DAGB3_WR_GMI_CNTL__LEVEL__SHIFT
36954. DAGB3_WR_GMI_CNTL__MAX_BURST_MASK
36955. DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT
36956. DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
36957. DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
36958. DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
36959. DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
36960. DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK
36961. DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
36962. DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
36963. DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
36964. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
36965. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
36966. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
36967. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
36968. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
36969. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
36970. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
36971. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
36972. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
36973. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
36974. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
36975. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
36976. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
36977. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
36978. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
36979. DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
36980. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
36981. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
36982. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
36983. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
36984. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
36985. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
36986. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
36987. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
36988. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
36989. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
36990. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
36991. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
36992. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
36993. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
36994. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
36995. DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
36996. DAGB3_WR_TLB_CREDIT__TLB0_MASK
36997. DAGB3_WR_TLB_CREDIT__TLB0__SHIFT
36998. DAGB3_WR_TLB_CREDIT__TLB1_MASK
36999. DAGB3_WR_TLB_CREDIT__TLB1__SHIFT
37000. DAGB3_WR_TLB_CREDIT__TLB2_MASK
37001. DAGB3_WR_TLB_CREDIT__TLB2__SHIFT
37002. DAGB3_WR_TLB_CREDIT__TLB3_MASK
37003. DAGB3_WR_TLB_CREDIT__TLB3__SHIFT
37004. DAGB3_WR_TLB_CREDIT__TLB4_MASK
37005. DAGB3_WR_TLB_CREDIT__TLB4__SHIFT
37006. DAGB3_WR_TLB_CREDIT__TLB5_MASK
37007. DAGB3_WR_TLB_CREDIT__TLB5__SHIFT
37008. DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK
37009. DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT
37010. DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
37011. DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
37012. DAGB3_WR_VC0_CNTL__MAX_BW_MASK
37013. DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT
37014. DAGB3_WR_VC0_CNTL__MAX_OSD_MASK
37015. DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT
37016. DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
37017. DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
37018. DAGB3_WR_VC0_CNTL__MIN_BW_MASK
37019. DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT
37020. DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
37021. DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
37022. DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK
37023. DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT
37024. DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK
37025. DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT
37026. DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
37027. DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
37028. DAGB3_WR_VC1_CNTL__MAX_BW_MASK
37029. DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT
37030. DAGB3_WR_VC1_CNTL__MAX_OSD_MASK
37031. DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT
37032. DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
37033. DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
37034. DAGB3_WR_VC1_CNTL__MIN_BW_MASK
37035. DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT
37036. DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
37037. DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
37038. DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK
37039. DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT
37040. DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK
37041. DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT
37042. DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
37043. DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
37044. DAGB3_WR_VC2_CNTL__MAX_BW_MASK
37045. DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT
37046. DAGB3_WR_VC2_CNTL__MAX_OSD_MASK
37047. DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT
37048. DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
37049. DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
37050. DAGB3_WR_VC2_CNTL__MIN_BW_MASK
37051. DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT
37052. DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
37053. DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
37054. DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK
37055. DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT
37056. DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK
37057. DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT
37058. DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
37059. DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
37060. DAGB3_WR_VC3_CNTL__MAX_BW_MASK
37061. DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT
37062. DAGB3_WR_VC3_CNTL__MAX_OSD_MASK
37063. DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT
37064. DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
37065. DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
37066. DAGB3_WR_VC3_CNTL__MIN_BW_MASK
37067. DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT
37068. DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
37069. DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
37070. DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK
37071. DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT
37072. DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK
37073. DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT
37074. DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
37075. DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
37076. DAGB3_WR_VC4_CNTL__MAX_BW_MASK
37077. DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT
37078. DAGB3_WR_VC4_CNTL__MAX_OSD_MASK
37079. DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT
37080. DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
37081. DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
37082. DAGB3_WR_VC4_CNTL__MIN_BW_MASK
37083. DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT
37084. DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
37085. DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
37086. DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK
37087. DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT
37088. DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK
37089. DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT
37090. DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
37091. DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
37092. DAGB3_WR_VC5_CNTL__MAX_BW_MASK
37093. DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT
37094. DAGB3_WR_VC5_CNTL__MAX_OSD_MASK
37095. DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT
37096. DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
37097. DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
37098. DAGB3_WR_VC5_CNTL__MIN_BW_MASK
37099. DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT
37100. DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
37101. DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
37102. DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK
37103. DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT
37104. DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK
37105. DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT
37106. DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
37107. DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
37108. DAGB3_WR_VC6_CNTL__MAX_BW_MASK
37109. DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT
37110. DAGB3_WR_VC6_CNTL__MAX_OSD_MASK
37111. DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT
37112. DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
37113. DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
37114. DAGB3_WR_VC6_CNTL__MIN_BW_MASK
37115. DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT
37116. DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
37117. DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
37118. DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK
37119. DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT
37120. DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK
37121. DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT
37122. DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
37123. DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
37124. DAGB3_WR_VC7_CNTL__MAX_BW_MASK
37125. DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT
37126. DAGB3_WR_VC7_CNTL__MAX_OSD_MASK
37127. DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT
37128. DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
37129. DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
37130. DAGB3_WR_VC7_CNTL__MIN_BW_MASK
37131. DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT
37132. DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
37133. DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
37134. DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK
37135. DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT
37136. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
37137. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
37138. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
37139. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
37140. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
37141. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
37142. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
37143. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
37144. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
37145. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
37146. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
37147. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
37148. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
37149. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
37150. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
37151. DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
37152. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
37153. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
37154. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
37155. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
37156. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
37157. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
37158. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
37159. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
37160. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
37161. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
37162. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
37163. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
37164. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
37165. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
37166. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
37167. DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
37168. DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
37169. DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
37170. DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
37171. DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
37172. DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
37173. DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
37174. DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK
37175. DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
37176. DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
37177. DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
37178. DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
37179. DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
37180. DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
37181. DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
37182. DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK
37183. DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
37184. DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
37185. DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
37186. DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK
37187. DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
37188. DAGB4_CNTL_MISC2__SWAP_CTL_MASK
37189. DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT
37190. DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK
37191. DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
37192. DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK
37193. DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
37194. DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK
37195. DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT
37196. DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
37197. DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
37198. DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK
37199. DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT
37200. DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK
37201. DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT
37202. DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK
37203. DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT
37204. DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK
37205. DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT
37206. DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK
37207. DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT
37208. DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK
37209. DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT
37210. DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK
37211. DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT
37212. DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK
37213. DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT
37214. DAGB4_DAGB_DLY__CLI_MASK
37215. DAGB4_DAGB_DLY__CLI__SHIFT
37216. DAGB4_DAGB_DLY__DLY_MASK
37217. DAGB4_DAGB_DLY__DLY__SHIFT
37218. DAGB4_DAGB_DLY__POS_MASK
37219. DAGB4_DAGB_DLY__POS__SHIFT
37220. DAGB4_FIFO_EMPTY__EMPTY_MASK
37221. DAGB4_FIFO_EMPTY__EMPTY__SHIFT
37222. DAGB4_FIFO_FULL__FULL_MASK
37223. DAGB4_FIFO_FULL__FULL__SHIFT
37224. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
37225. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
37226. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
37227. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
37228. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
37229. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
37230. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
37231. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
37232. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
37233. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
37234. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
37235. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
37236. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
37237. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
37238. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
37239. DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
37240. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
37241. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
37242. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
37243. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
37244. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
37245. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
37246. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
37247. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
37248. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
37249. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
37250. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
37251. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
37252. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
37253. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
37254. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
37255. DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
37256. DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK
37257. DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT
37258. DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK
37259. DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT
37260. DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK
37261. DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
37262. DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
37263. DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
37264. DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK
37265. DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
37266. DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK
37267. DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT
37268. DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK
37269. DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT
37270. DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK
37271. DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
37272. DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
37273. DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
37274. DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK
37275. DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
37276. DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK
37277. DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT
37278. DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK
37279. DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT
37280. DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK
37281. DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
37282. DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
37283. DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
37284. DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK
37285. DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
37286. DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK
37287. DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
37288. DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK
37289. DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT
37290. DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK
37291. DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT
37292. DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
37293. DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
37294. DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
37295. DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
37296. DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
37297. DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
37298. DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
37299. DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
37300. DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
37301. DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
37302. DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
37303. DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
37304. DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK
37305. DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT
37306. DAGB4_RDCLI0__MAX_BW_ENABLE_MASK
37307. DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT
37308. DAGB4_RDCLI0__MAX_BW_MASK
37309. DAGB4_RDCLI0__MAX_BW__SHIFT
37310. DAGB4_RDCLI0__MAX_OSD_MASK
37311. DAGB4_RDCLI0__MAX_OSD__SHIFT
37312. DAGB4_RDCLI0__MIN_BW_ENABLE_MASK
37313. DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT
37314. DAGB4_RDCLI0__MIN_BW_MASK
37315. DAGB4_RDCLI0__MIN_BW__SHIFT
37316. DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK
37317. DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
37318. DAGB4_RDCLI0__URG_HIGH_MASK
37319. DAGB4_RDCLI0__URG_HIGH__SHIFT
37320. DAGB4_RDCLI0__URG_LOW_MASK
37321. DAGB4_RDCLI0__URG_LOW__SHIFT
37322. DAGB4_RDCLI0__VIRT_CHAN_MASK
37323. DAGB4_RDCLI0__VIRT_CHAN__SHIFT
37324. DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK
37325. DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT
37326. DAGB4_RDCLI10__MAX_BW_ENABLE_MASK
37327. DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT
37328. DAGB4_RDCLI10__MAX_BW_MASK
37329. DAGB4_RDCLI10__MAX_BW__SHIFT
37330. DAGB4_RDCLI10__MAX_OSD_MASK
37331. DAGB4_RDCLI10__MAX_OSD__SHIFT
37332. DAGB4_RDCLI10__MIN_BW_ENABLE_MASK
37333. DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT
37334. DAGB4_RDCLI10__MIN_BW_MASK
37335. DAGB4_RDCLI10__MIN_BW__SHIFT
37336. DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK
37337. DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
37338. DAGB4_RDCLI10__URG_HIGH_MASK
37339. DAGB4_RDCLI10__URG_HIGH__SHIFT
37340. DAGB4_RDCLI10__URG_LOW_MASK
37341. DAGB4_RDCLI10__URG_LOW__SHIFT
37342. DAGB4_RDCLI10__VIRT_CHAN_MASK
37343. DAGB4_RDCLI10__VIRT_CHAN__SHIFT
37344. DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK
37345. DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT
37346. DAGB4_RDCLI11__MAX_BW_ENABLE_MASK
37347. DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT
37348. DAGB4_RDCLI11__MAX_BW_MASK
37349. DAGB4_RDCLI11__MAX_BW__SHIFT
37350. DAGB4_RDCLI11__MAX_OSD_MASK
37351. DAGB4_RDCLI11__MAX_OSD__SHIFT
37352. DAGB4_RDCLI11__MIN_BW_ENABLE_MASK
37353. DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT
37354. DAGB4_RDCLI11__MIN_BW_MASK
37355. DAGB4_RDCLI11__MIN_BW__SHIFT
37356. DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK
37357. DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
37358. DAGB4_RDCLI11__URG_HIGH_MASK
37359. DAGB4_RDCLI11__URG_HIGH__SHIFT
37360. DAGB4_RDCLI11__URG_LOW_MASK
37361. DAGB4_RDCLI11__URG_LOW__SHIFT
37362. DAGB4_RDCLI11__VIRT_CHAN_MASK
37363. DAGB4_RDCLI11__VIRT_CHAN__SHIFT
37364. DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK
37365. DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT
37366. DAGB4_RDCLI12__MAX_BW_ENABLE_MASK
37367. DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT
37368. DAGB4_RDCLI12__MAX_BW_MASK
37369. DAGB4_RDCLI12__MAX_BW__SHIFT
37370. DAGB4_RDCLI12__MAX_OSD_MASK
37371. DAGB4_RDCLI12__MAX_OSD__SHIFT
37372. DAGB4_RDCLI12__MIN_BW_ENABLE_MASK
37373. DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT
37374. DAGB4_RDCLI12__MIN_BW_MASK
37375. DAGB4_RDCLI12__MIN_BW__SHIFT
37376. DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK
37377. DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
37378. DAGB4_RDCLI12__URG_HIGH_MASK
37379. DAGB4_RDCLI12__URG_HIGH__SHIFT
37380. DAGB4_RDCLI12__URG_LOW_MASK
37381. DAGB4_RDCLI12__URG_LOW__SHIFT
37382. DAGB4_RDCLI12__VIRT_CHAN_MASK
37383. DAGB4_RDCLI12__VIRT_CHAN__SHIFT
37384. DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK
37385. DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT
37386. DAGB4_RDCLI13__MAX_BW_ENABLE_MASK
37387. DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT
37388. DAGB4_RDCLI13__MAX_BW_MASK
37389. DAGB4_RDCLI13__MAX_BW__SHIFT
37390. DAGB4_RDCLI13__MAX_OSD_MASK
37391. DAGB4_RDCLI13__MAX_OSD__SHIFT
37392. DAGB4_RDCLI13__MIN_BW_ENABLE_MASK
37393. DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT
37394. DAGB4_RDCLI13__MIN_BW_MASK
37395. DAGB4_RDCLI13__MIN_BW__SHIFT
37396. DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK
37397. DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
37398. DAGB4_RDCLI13__URG_HIGH_MASK
37399. DAGB4_RDCLI13__URG_HIGH__SHIFT
37400. DAGB4_RDCLI13__URG_LOW_MASK
37401. DAGB4_RDCLI13__URG_LOW__SHIFT
37402. DAGB4_RDCLI13__VIRT_CHAN_MASK
37403. DAGB4_RDCLI13__VIRT_CHAN__SHIFT
37404. DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK
37405. DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT
37406. DAGB4_RDCLI14__MAX_BW_ENABLE_MASK
37407. DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT
37408. DAGB4_RDCLI14__MAX_BW_MASK
37409. DAGB4_RDCLI14__MAX_BW__SHIFT
37410. DAGB4_RDCLI14__MAX_OSD_MASK
37411. DAGB4_RDCLI14__MAX_OSD__SHIFT
37412. DAGB4_RDCLI14__MIN_BW_ENABLE_MASK
37413. DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT
37414. DAGB4_RDCLI14__MIN_BW_MASK
37415. DAGB4_RDCLI14__MIN_BW__SHIFT
37416. DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK
37417. DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
37418. DAGB4_RDCLI14__URG_HIGH_MASK
37419. DAGB4_RDCLI14__URG_HIGH__SHIFT
37420. DAGB4_RDCLI14__URG_LOW_MASK
37421. DAGB4_RDCLI14__URG_LOW__SHIFT
37422. DAGB4_RDCLI14__VIRT_CHAN_MASK
37423. DAGB4_RDCLI14__VIRT_CHAN__SHIFT
37424. DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK
37425. DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT
37426. DAGB4_RDCLI15__MAX_BW_ENABLE_MASK
37427. DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT
37428. DAGB4_RDCLI15__MAX_BW_MASK
37429. DAGB4_RDCLI15__MAX_BW__SHIFT
37430. DAGB4_RDCLI15__MAX_OSD_MASK
37431. DAGB4_RDCLI15__MAX_OSD__SHIFT
37432. DAGB4_RDCLI15__MIN_BW_ENABLE_MASK
37433. DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT
37434. DAGB4_RDCLI15__MIN_BW_MASK
37435. DAGB4_RDCLI15__MIN_BW__SHIFT
37436. DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK
37437. DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
37438. DAGB4_RDCLI15__URG_HIGH_MASK
37439. DAGB4_RDCLI15__URG_HIGH__SHIFT
37440. DAGB4_RDCLI15__URG_LOW_MASK
37441. DAGB4_RDCLI15__URG_LOW__SHIFT
37442. DAGB4_RDCLI15__VIRT_CHAN_MASK
37443. DAGB4_RDCLI15__VIRT_CHAN__SHIFT
37444. DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK
37445. DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT
37446. DAGB4_RDCLI1__MAX_BW_ENABLE_MASK
37447. DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT
37448. DAGB4_RDCLI1__MAX_BW_MASK
37449. DAGB4_RDCLI1__MAX_BW__SHIFT
37450. DAGB4_RDCLI1__MAX_OSD_MASK
37451. DAGB4_RDCLI1__MAX_OSD__SHIFT
37452. DAGB4_RDCLI1__MIN_BW_ENABLE_MASK
37453. DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT
37454. DAGB4_RDCLI1__MIN_BW_MASK
37455. DAGB4_RDCLI1__MIN_BW__SHIFT
37456. DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK
37457. DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
37458. DAGB4_RDCLI1__URG_HIGH_MASK
37459. DAGB4_RDCLI1__URG_HIGH__SHIFT
37460. DAGB4_RDCLI1__URG_LOW_MASK
37461. DAGB4_RDCLI1__URG_LOW__SHIFT
37462. DAGB4_RDCLI1__VIRT_CHAN_MASK
37463. DAGB4_RDCLI1__VIRT_CHAN__SHIFT
37464. DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK
37465. DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT
37466. DAGB4_RDCLI2__MAX_BW_ENABLE_MASK
37467. DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT
37468. DAGB4_RDCLI2__MAX_BW_MASK
37469. DAGB4_RDCLI2__MAX_BW__SHIFT
37470. DAGB4_RDCLI2__MAX_OSD_MASK
37471. DAGB4_RDCLI2__MAX_OSD__SHIFT
37472. DAGB4_RDCLI2__MIN_BW_ENABLE_MASK
37473. DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT
37474. DAGB4_RDCLI2__MIN_BW_MASK
37475. DAGB4_RDCLI2__MIN_BW__SHIFT
37476. DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK
37477. DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
37478. DAGB4_RDCLI2__URG_HIGH_MASK
37479. DAGB4_RDCLI2__URG_HIGH__SHIFT
37480. DAGB4_RDCLI2__URG_LOW_MASK
37481. DAGB4_RDCLI2__URG_LOW__SHIFT
37482. DAGB4_RDCLI2__VIRT_CHAN_MASK
37483. DAGB4_RDCLI2__VIRT_CHAN__SHIFT
37484. DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK
37485. DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT
37486. DAGB4_RDCLI3__MAX_BW_ENABLE_MASK
37487. DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT
37488. DAGB4_RDCLI3__MAX_BW_MASK
37489. DAGB4_RDCLI3__MAX_BW__SHIFT
37490. DAGB4_RDCLI3__MAX_OSD_MASK
37491. DAGB4_RDCLI3__MAX_OSD__SHIFT
37492. DAGB4_RDCLI3__MIN_BW_ENABLE_MASK
37493. DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT
37494. DAGB4_RDCLI3__MIN_BW_MASK
37495. DAGB4_RDCLI3__MIN_BW__SHIFT
37496. DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK
37497. DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
37498. DAGB4_RDCLI3__URG_HIGH_MASK
37499. DAGB4_RDCLI3__URG_HIGH__SHIFT
37500. DAGB4_RDCLI3__URG_LOW_MASK
37501. DAGB4_RDCLI3__URG_LOW__SHIFT
37502. DAGB4_RDCLI3__VIRT_CHAN_MASK
37503. DAGB4_RDCLI3__VIRT_CHAN__SHIFT
37504. DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK
37505. DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT
37506. DAGB4_RDCLI4__MAX_BW_ENABLE_MASK
37507. DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT
37508. DAGB4_RDCLI4__MAX_BW_MASK
37509. DAGB4_RDCLI4__MAX_BW__SHIFT
37510. DAGB4_RDCLI4__MAX_OSD_MASK
37511. DAGB4_RDCLI4__MAX_OSD__SHIFT
37512. DAGB4_RDCLI4__MIN_BW_ENABLE_MASK
37513. DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT
37514. DAGB4_RDCLI4__MIN_BW_MASK
37515. DAGB4_RDCLI4__MIN_BW__SHIFT
37516. DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK
37517. DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
37518. DAGB4_RDCLI4__URG_HIGH_MASK
37519. DAGB4_RDCLI4__URG_HIGH__SHIFT
37520. DAGB4_RDCLI4__URG_LOW_MASK
37521. DAGB4_RDCLI4__URG_LOW__SHIFT
37522. DAGB4_RDCLI4__VIRT_CHAN_MASK
37523. DAGB4_RDCLI4__VIRT_CHAN__SHIFT
37524. DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK
37525. DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT
37526. DAGB4_RDCLI5__MAX_BW_ENABLE_MASK
37527. DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT
37528. DAGB4_RDCLI5__MAX_BW_MASK
37529. DAGB4_RDCLI5__MAX_BW__SHIFT
37530. DAGB4_RDCLI5__MAX_OSD_MASK
37531. DAGB4_RDCLI5__MAX_OSD__SHIFT
37532. DAGB4_RDCLI5__MIN_BW_ENABLE_MASK
37533. DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT
37534. DAGB4_RDCLI5__MIN_BW_MASK
37535. DAGB4_RDCLI5__MIN_BW__SHIFT
37536. DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK
37537. DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
37538. DAGB4_RDCLI5__URG_HIGH_MASK
37539. DAGB4_RDCLI5__URG_HIGH__SHIFT
37540. DAGB4_RDCLI5__URG_LOW_MASK
37541. DAGB4_RDCLI5__URG_LOW__SHIFT
37542. DAGB4_RDCLI5__VIRT_CHAN_MASK
37543. DAGB4_RDCLI5__VIRT_CHAN__SHIFT
37544. DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK
37545. DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT
37546. DAGB4_RDCLI6__MAX_BW_ENABLE_MASK
37547. DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT
37548. DAGB4_RDCLI6__MAX_BW_MASK
37549. DAGB4_RDCLI6__MAX_BW__SHIFT
37550. DAGB4_RDCLI6__MAX_OSD_MASK
37551. DAGB4_RDCLI6__MAX_OSD__SHIFT
37552. DAGB4_RDCLI6__MIN_BW_ENABLE_MASK
37553. DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT
37554. DAGB4_RDCLI6__MIN_BW_MASK
37555. DAGB4_RDCLI6__MIN_BW__SHIFT
37556. DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK
37557. DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
37558. DAGB4_RDCLI6__URG_HIGH_MASK
37559. DAGB4_RDCLI6__URG_HIGH__SHIFT
37560. DAGB4_RDCLI6__URG_LOW_MASK
37561. DAGB4_RDCLI6__URG_LOW__SHIFT
37562. DAGB4_RDCLI6__VIRT_CHAN_MASK
37563. DAGB4_RDCLI6__VIRT_CHAN__SHIFT
37564. DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK
37565. DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT
37566. DAGB4_RDCLI7__MAX_BW_ENABLE_MASK
37567. DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT
37568. DAGB4_RDCLI7__MAX_BW_MASK
37569. DAGB4_RDCLI7__MAX_BW__SHIFT
37570. DAGB4_RDCLI7__MAX_OSD_MASK
37571. DAGB4_RDCLI7__MAX_OSD__SHIFT
37572. DAGB4_RDCLI7__MIN_BW_ENABLE_MASK
37573. DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT
37574. DAGB4_RDCLI7__MIN_BW_MASK
37575. DAGB4_RDCLI7__MIN_BW__SHIFT
37576. DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK
37577. DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
37578. DAGB4_RDCLI7__URG_HIGH_MASK
37579. DAGB4_RDCLI7__URG_HIGH__SHIFT
37580. DAGB4_RDCLI7__URG_LOW_MASK
37581. DAGB4_RDCLI7__URG_LOW__SHIFT
37582. DAGB4_RDCLI7__VIRT_CHAN_MASK
37583. DAGB4_RDCLI7__VIRT_CHAN__SHIFT
37584. DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK
37585. DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT
37586. DAGB4_RDCLI8__MAX_BW_ENABLE_MASK
37587. DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT
37588. DAGB4_RDCLI8__MAX_BW_MASK
37589. DAGB4_RDCLI8__MAX_BW__SHIFT
37590. DAGB4_RDCLI8__MAX_OSD_MASK
37591. DAGB4_RDCLI8__MAX_OSD__SHIFT
37592. DAGB4_RDCLI8__MIN_BW_ENABLE_MASK
37593. DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT
37594. DAGB4_RDCLI8__MIN_BW_MASK
37595. DAGB4_RDCLI8__MIN_BW__SHIFT
37596. DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK
37597. DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
37598. DAGB4_RDCLI8__URG_HIGH_MASK
37599. DAGB4_RDCLI8__URG_HIGH__SHIFT
37600. DAGB4_RDCLI8__URG_LOW_MASK
37601. DAGB4_RDCLI8__URG_LOW__SHIFT
37602. DAGB4_RDCLI8__VIRT_CHAN_MASK
37603. DAGB4_RDCLI8__VIRT_CHAN__SHIFT
37604. DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK
37605. DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT
37606. DAGB4_RDCLI9__MAX_BW_ENABLE_MASK
37607. DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT
37608. DAGB4_RDCLI9__MAX_BW_MASK
37609. DAGB4_RDCLI9__MAX_BW__SHIFT
37610. DAGB4_RDCLI9__MAX_OSD_MASK
37611. DAGB4_RDCLI9__MAX_OSD__SHIFT
37612. DAGB4_RDCLI9__MIN_BW_ENABLE_MASK
37613. DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT
37614. DAGB4_RDCLI9__MIN_BW_MASK
37615. DAGB4_RDCLI9__MIN_BW__SHIFT
37616. DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK
37617. DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
37618. DAGB4_RDCLI9__URG_HIGH_MASK
37619. DAGB4_RDCLI9__URG_HIGH__SHIFT
37620. DAGB4_RDCLI9__URG_LOW_MASK
37621. DAGB4_RDCLI9__URG_LOW__SHIFT
37622. DAGB4_RDCLI9__VIRT_CHAN_MASK
37623. DAGB4_RDCLI9__VIRT_CHAN__SHIFT
37624. DAGB4_RDCLI_ASK_PENDING__BUSY_MASK
37625. DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT
37626. DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK
37627. DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
37628. DAGB4_RDCLI_GO_PENDING__BUSY_MASK
37629. DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT
37630. DAGB4_RDCLI_OARB_PENDING__BUSY_MASK
37631. DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT
37632. DAGB4_RDCLI_OSD_PENDING__BUSY_MASK
37633. DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT
37634. DAGB4_RDCLI_TLB_PENDING__BUSY_MASK
37635. DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT
37636. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
37637. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
37638. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
37639. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
37640. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
37641. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
37642. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
37643. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
37644. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
37645. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
37646. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
37647. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
37648. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
37649. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
37650. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
37651. DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
37652. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
37653. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
37654. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
37655. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
37656. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
37657. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
37658. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
37659. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
37660. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
37661. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
37662. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
37663. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
37664. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
37665. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
37666. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
37667. DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
37668. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
37669. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
37670. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
37671. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
37672. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
37673. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
37674. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
37675. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
37676. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
37677. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
37678. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
37679. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
37680. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
37681. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
37682. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
37683. DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
37684. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
37685. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
37686. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
37687. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
37688. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
37689. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
37690. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
37691. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
37692. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
37693. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
37694. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
37695. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
37696. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
37697. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
37698. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
37699. DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
37700. DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK
37701. DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
37702. DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
37703. DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
37704. DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
37705. DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
37706. DAGB4_RD_ADDR_DAGB__WHOAMI_MASK
37707. DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT
37708. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
37709. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
37710. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
37711. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
37712. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
37713. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
37714. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
37715. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
37716. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
37717. DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
37718. DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
37719. DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
37720. DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
37721. DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
37722. DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
37723. DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
37724. DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
37725. DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
37726. DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
37727. DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
37728. DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK
37729. DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
37730. DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
37731. DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
37732. DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
37733. DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
37734. DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
37735. DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
37736. DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK
37737. DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT
37738. DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
37739. DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
37740. DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
37741. DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
37742. DAGB4_RD_CNTL__IO_LEVEL_MASK
37743. DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
37744. DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
37745. DAGB4_RD_CNTL__IO_LEVEL__SHIFT
37746. DAGB4_RD_CNTL__SCLK_FREQ_MASK
37747. DAGB4_RD_CNTL__SCLK_FREQ__SHIFT
37748. DAGB4_RD_CNTL__SHARE_VC_NUM_MASK
37749. DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT
37750. DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK
37751. DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
37752. DAGB4_RD_CREDITS_FULL__FULL_MASK
37753. DAGB4_RD_CREDITS_FULL__FULL__SHIFT
37754. DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK
37755. DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT
37756. DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK
37757. DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT
37758. DAGB4_RD_GMI_CNTL__LEVEL_MASK
37759. DAGB4_RD_GMI_CNTL__LEVEL__SHIFT
37760. DAGB4_RD_GMI_CNTL__MAX_BURST_MASK
37761. DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT
37762. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
37763. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
37764. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
37765. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
37766. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
37767. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
37768. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
37769. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
37770. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
37771. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
37772. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
37773. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
37774. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
37775. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
37776. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
37777. DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
37778. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
37779. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
37780. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
37781. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
37782. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
37783. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
37784. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
37785. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
37786. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
37787. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
37788. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
37789. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
37790. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
37791. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
37792. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
37793. DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
37794. DAGB4_RD_TLB_CREDIT__TLB0_MASK
37795. DAGB4_RD_TLB_CREDIT__TLB0__SHIFT
37796. DAGB4_RD_TLB_CREDIT__TLB1_MASK
37797. DAGB4_RD_TLB_CREDIT__TLB1__SHIFT
37798. DAGB4_RD_TLB_CREDIT__TLB2_MASK
37799. DAGB4_RD_TLB_CREDIT__TLB2__SHIFT
37800. DAGB4_RD_TLB_CREDIT__TLB3_MASK
37801. DAGB4_RD_TLB_CREDIT__TLB3__SHIFT
37802. DAGB4_RD_TLB_CREDIT__TLB4_MASK
37803. DAGB4_RD_TLB_CREDIT__TLB4__SHIFT
37804. DAGB4_RD_TLB_CREDIT__TLB5_MASK
37805. DAGB4_RD_TLB_CREDIT__TLB5__SHIFT
37806. DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK
37807. DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT
37808. DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
37809. DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
37810. DAGB4_RD_VC0_CNTL__MAX_BW_MASK
37811. DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT
37812. DAGB4_RD_VC0_CNTL__MAX_OSD_MASK
37813. DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT
37814. DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
37815. DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
37816. DAGB4_RD_VC0_CNTL__MIN_BW_MASK
37817. DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT
37818. DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
37819. DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
37820. DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK
37821. DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT
37822. DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK
37823. DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT
37824. DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
37825. DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
37826. DAGB4_RD_VC1_CNTL__MAX_BW_MASK
37827. DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT
37828. DAGB4_RD_VC1_CNTL__MAX_OSD_MASK
37829. DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT
37830. DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
37831. DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
37832. DAGB4_RD_VC1_CNTL__MIN_BW_MASK
37833. DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT
37834. DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
37835. DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
37836. DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK
37837. DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT
37838. DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK
37839. DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT
37840. DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
37841. DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
37842. DAGB4_RD_VC2_CNTL__MAX_BW_MASK
37843. DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT
37844. DAGB4_RD_VC2_CNTL__MAX_OSD_MASK
37845. DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT
37846. DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
37847. DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
37848. DAGB4_RD_VC2_CNTL__MIN_BW_MASK
37849. DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT
37850. DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
37851. DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
37852. DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK
37853. DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT
37854. DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK
37855. DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT
37856. DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
37857. DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
37858. DAGB4_RD_VC3_CNTL__MAX_BW_MASK
37859. DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT
37860. DAGB4_RD_VC3_CNTL__MAX_OSD_MASK
37861. DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT
37862. DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
37863. DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
37864. DAGB4_RD_VC3_CNTL__MIN_BW_MASK
37865. DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT
37866. DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
37867. DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
37868. DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK
37869. DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT
37870. DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK
37871. DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT
37872. DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
37873. DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
37874. DAGB4_RD_VC4_CNTL__MAX_BW_MASK
37875. DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT
37876. DAGB4_RD_VC4_CNTL__MAX_OSD_MASK
37877. DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT
37878. DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
37879. DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
37880. DAGB4_RD_VC4_CNTL__MIN_BW_MASK
37881. DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT
37882. DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
37883. DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
37884. DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK
37885. DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT
37886. DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK
37887. DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT
37888. DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
37889. DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
37890. DAGB4_RD_VC5_CNTL__MAX_BW_MASK
37891. DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT
37892. DAGB4_RD_VC5_CNTL__MAX_OSD_MASK
37893. DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT
37894. DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
37895. DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
37896. DAGB4_RD_VC5_CNTL__MIN_BW_MASK
37897. DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT
37898. DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
37899. DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
37900. DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK
37901. DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT
37902. DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK
37903. DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT
37904. DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
37905. DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
37906. DAGB4_RD_VC6_CNTL__MAX_BW_MASK
37907. DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT
37908. DAGB4_RD_VC6_CNTL__MAX_OSD_MASK
37909. DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT
37910. DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
37911. DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
37912. DAGB4_RD_VC6_CNTL__MIN_BW_MASK
37913. DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT
37914. DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
37915. DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
37916. DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK
37917. DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT
37918. DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK
37919. DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT
37920. DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
37921. DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
37922. DAGB4_RD_VC7_CNTL__MAX_BW_MASK
37923. DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT
37924. DAGB4_RD_VC7_CNTL__MAX_OSD_MASK
37925. DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT
37926. DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
37927. DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
37928. DAGB4_RD_VC7_CNTL__MIN_BW_MASK
37929. DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT
37930. DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
37931. DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
37932. DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK
37933. DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT
37934. DAGB4_RESERVE0__RESERVE_MASK
37935. DAGB4_RESERVE0__RESERVE__SHIFT
37936. DAGB4_RESERVE10__RESERVE_MASK
37937. DAGB4_RESERVE10__RESERVE__SHIFT
37938. DAGB4_RESERVE11__RESERVE_MASK
37939. DAGB4_RESERVE11__RESERVE__SHIFT
37940. DAGB4_RESERVE12__RESERVE_MASK
37941. DAGB4_RESERVE12__RESERVE__SHIFT
37942. DAGB4_RESERVE13__RESERVE_MASK
37943. DAGB4_RESERVE13__RESERVE__SHIFT
37944. DAGB4_RESERVE1__RESERVE_MASK
37945. DAGB4_RESERVE1__RESERVE__SHIFT
37946. DAGB4_RESERVE2__RESERVE_MASK
37947. DAGB4_RESERVE2__RESERVE__SHIFT
37948. DAGB4_RESERVE3__RESERVE_MASK
37949. DAGB4_RESERVE3__RESERVE__SHIFT
37950. DAGB4_RESERVE4__RESERVE_MASK
37951. DAGB4_RESERVE4__RESERVE__SHIFT
37952. DAGB4_RESERVE5__RESERVE_MASK
37953. DAGB4_RESERVE5__RESERVE__SHIFT
37954. DAGB4_RESERVE6__RESERVE_MASK
37955. DAGB4_RESERVE6__RESERVE__SHIFT
37956. DAGB4_RESERVE7__RESERVE_MASK
37957. DAGB4_RESERVE7__RESERVE__SHIFT
37958. DAGB4_RESERVE8__RESERVE_MASK
37959. DAGB4_RESERVE8__RESERVE__SHIFT
37960. DAGB4_RESERVE9__RESERVE_MASK
37961. DAGB4_RESERVE9__RESERVE__SHIFT
37962. DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK
37963. DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT
37964. DAGB4_WRCLI0__MAX_BW_ENABLE_MASK
37965. DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT
37966. DAGB4_WRCLI0__MAX_BW_MASK
37967. DAGB4_WRCLI0__MAX_BW__SHIFT
37968. DAGB4_WRCLI0__MAX_OSD_MASK
37969. DAGB4_WRCLI0__MAX_OSD__SHIFT
37970. DAGB4_WRCLI0__MIN_BW_ENABLE_MASK
37971. DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT
37972. DAGB4_WRCLI0__MIN_BW_MASK
37973. DAGB4_WRCLI0__MIN_BW__SHIFT
37974. DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK
37975. DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
37976. DAGB4_WRCLI0__URG_HIGH_MASK
37977. DAGB4_WRCLI0__URG_HIGH__SHIFT
37978. DAGB4_WRCLI0__URG_LOW_MASK
37979. DAGB4_WRCLI0__URG_LOW__SHIFT
37980. DAGB4_WRCLI0__VIRT_CHAN_MASK
37981. DAGB4_WRCLI0__VIRT_CHAN__SHIFT
37982. DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK
37983. DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT
37984. DAGB4_WRCLI10__MAX_BW_ENABLE_MASK
37985. DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT
37986. DAGB4_WRCLI10__MAX_BW_MASK
37987. DAGB4_WRCLI10__MAX_BW__SHIFT
37988. DAGB4_WRCLI10__MAX_OSD_MASK
37989. DAGB4_WRCLI10__MAX_OSD__SHIFT
37990. DAGB4_WRCLI10__MIN_BW_ENABLE_MASK
37991. DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT
37992. DAGB4_WRCLI10__MIN_BW_MASK
37993. DAGB4_WRCLI10__MIN_BW__SHIFT
37994. DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK
37995. DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
37996. DAGB4_WRCLI10__URG_HIGH_MASK
37997. DAGB4_WRCLI10__URG_HIGH__SHIFT
37998. DAGB4_WRCLI10__URG_LOW_MASK
37999. DAGB4_WRCLI10__URG_LOW__SHIFT
38000. DAGB4_WRCLI10__VIRT_CHAN_MASK
38001. DAGB4_WRCLI10__VIRT_CHAN__SHIFT
38002. DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK
38003. DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT
38004. DAGB4_WRCLI11__MAX_BW_ENABLE_MASK
38005. DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT
38006. DAGB4_WRCLI11__MAX_BW_MASK
38007. DAGB4_WRCLI11__MAX_BW__SHIFT
38008. DAGB4_WRCLI11__MAX_OSD_MASK
38009. DAGB4_WRCLI11__MAX_OSD__SHIFT
38010. DAGB4_WRCLI11__MIN_BW_ENABLE_MASK
38011. DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT
38012. DAGB4_WRCLI11__MIN_BW_MASK
38013. DAGB4_WRCLI11__MIN_BW__SHIFT
38014. DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK
38015. DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
38016. DAGB4_WRCLI11__URG_HIGH_MASK
38017. DAGB4_WRCLI11__URG_HIGH__SHIFT
38018. DAGB4_WRCLI11__URG_LOW_MASK
38019. DAGB4_WRCLI11__URG_LOW__SHIFT
38020. DAGB4_WRCLI11__VIRT_CHAN_MASK
38021. DAGB4_WRCLI11__VIRT_CHAN__SHIFT
38022. DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK
38023. DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT
38024. DAGB4_WRCLI12__MAX_BW_ENABLE_MASK
38025. DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT
38026. DAGB4_WRCLI12__MAX_BW_MASK
38027. DAGB4_WRCLI12__MAX_BW__SHIFT
38028. DAGB4_WRCLI12__MAX_OSD_MASK
38029. DAGB4_WRCLI12__MAX_OSD__SHIFT
38030. DAGB4_WRCLI12__MIN_BW_ENABLE_MASK
38031. DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT
38032. DAGB4_WRCLI12__MIN_BW_MASK
38033. DAGB4_WRCLI12__MIN_BW__SHIFT
38034. DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK
38035. DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
38036. DAGB4_WRCLI12__URG_HIGH_MASK
38037. DAGB4_WRCLI12__URG_HIGH__SHIFT
38038. DAGB4_WRCLI12__URG_LOW_MASK
38039. DAGB4_WRCLI12__URG_LOW__SHIFT
38040. DAGB4_WRCLI12__VIRT_CHAN_MASK
38041. DAGB4_WRCLI12__VIRT_CHAN__SHIFT
38042. DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK
38043. DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT
38044. DAGB4_WRCLI13__MAX_BW_ENABLE_MASK
38045. DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT
38046. DAGB4_WRCLI13__MAX_BW_MASK
38047. DAGB4_WRCLI13__MAX_BW__SHIFT
38048. DAGB4_WRCLI13__MAX_OSD_MASK
38049. DAGB4_WRCLI13__MAX_OSD__SHIFT
38050. DAGB4_WRCLI13__MIN_BW_ENABLE_MASK
38051. DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT
38052. DAGB4_WRCLI13__MIN_BW_MASK
38053. DAGB4_WRCLI13__MIN_BW__SHIFT
38054. DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK
38055. DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
38056. DAGB4_WRCLI13__URG_HIGH_MASK
38057. DAGB4_WRCLI13__URG_HIGH__SHIFT
38058. DAGB4_WRCLI13__URG_LOW_MASK
38059. DAGB4_WRCLI13__URG_LOW__SHIFT
38060. DAGB4_WRCLI13__VIRT_CHAN_MASK
38061. DAGB4_WRCLI13__VIRT_CHAN__SHIFT
38062. DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK
38063. DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT
38064. DAGB4_WRCLI14__MAX_BW_ENABLE_MASK
38065. DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT
38066. DAGB4_WRCLI14__MAX_BW_MASK
38067. DAGB4_WRCLI14__MAX_BW__SHIFT
38068. DAGB4_WRCLI14__MAX_OSD_MASK
38069. DAGB4_WRCLI14__MAX_OSD__SHIFT
38070. DAGB4_WRCLI14__MIN_BW_ENABLE_MASK
38071. DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT
38072. DAGB4_WRCLI14__MIN_BW_MASK
38073. DAGB4_WRCLI14__MIN_BW__SHIFT
38074. DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK
38075. DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
38076. DAGB4_WRCLI14__URG_HIGH_MASK
38077. DAGB4_WRCLI14__URG_HIGH__SHIFT
38078. DAGB4_WRCLI14__URG_LOW_MASK
38079. DAGB4_WRCLI14__URG_LOW__SHIFT
38080. DAGB4_WRCLI14__VIRT_CHAN_MASK
38081. DAGB4_WRCLI14__VIRT_CHAN__SHIFT
38082. DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK
38083. DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT
38084. DAGB4_WRCLI15__MAX_BW_ENABLE_MASK
38085. DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT
38086. DAGB4_WRCLI15__MAX_BW_MASK
38087. DAGB4_WRCLI15__MAX_BW__SHIFT
38088. DAGB4_WRCLI15__MAX_OSD_MASK
38089. DAGB4_WRCLI15__MAX_OSD__SHIFT
38090. DAGB4_WRCLI15__MIN_BW_ENABLE_MASK
38091. DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT
38092. DAGB4_WRCLI15__MIN_BW_MASK
38093. DAGB4_WRCLI15__MIN_BW__SHIFT
38094. DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK
38095. DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
38096. DAGB4_WRCLI15__URG_HIGH_MASK
38097. DAGB4_WRCLI15__URG_HIGH__SHIFT
38098. DAGB4_WRCLI15__URG_LOW_MASK
38099. DAGB4_WRCLI15__URG_LOW__SHIFT
38100. DAGB4_WRCLI15__VIRT_CHAN_MASK
38101. DAGB4_WRCLI15__VIRT_CHAN__SHIFT
38102. DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK
38103. DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT
38104. DAGB4_WRCLI1__MAX_BW_ENABLE_MASK
38105. DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT
38106. DAGB4_WRCLI1__MAX_BW_MASK
38107. DAGB4_WRCLI1__MAX_BW__SHIFT
38108. DAGB4_WRCLI1__MAX_OSD_MASK
38109. DAGB4_WRCLI1__MAX_OSD__SHIFT
38110. DAGB4_WRCLI1__MIN_BW_ENABLE_MASK
38111. DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT
38112. DAGB4_WRCLI1__MIN_BW_MASK
38113. DAGB4_WRCLI1__MIN_BW__SHIFT
38114. DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK
38115. DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
38116. DAGB4_WRCLI1__URG_HIGH_MASK
38117. DAGB4_WRCLI1__URG_HIGH__SHIFT
38118. DAGB4_WRCLI1__URG_LOW_MASK
38119. DAGB4_WRCLI1__URG_LOW__SHIFT
38120. DAGB4_WRCLI1__VIRT_CHAN_MASK
38121. DAGB4_WRCLI1__VIRT_CHAN__SHIFT
38122. DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK
38123. DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT
38124. DAGB4_WRCLI2__MAX_BW_ENABLE_MASK
38125. DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT
38126. DAGB4_WRCLI2__MAX_BW_MASK
38127. DAGB4_WRCLI2__MAX_BW__SHIFT
38128. DAGB4_WRCLI2__MAX_OSD_MASK
38129. DAGB4_WRCLI2__MAX_OSD__SHIFT
38130. DAGB4_WRCLI2__MIN_BW_ENABLE_MASK
38131. DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT
38132. DAGB4_WRCLI2__MIN_BW_MASK
38133. DAGB4_WRCLI2__MIN_BW__SHIFT
38134. DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK
38135. DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
38136. DAGB4_WRCLI2__URG_HIGH_MASK
38137. DAGB4_WRCLI2__URG_HIGH__SHIFT
38138. DAGB4_WRCLI2__URG_LOW_MASK
38139. DAGB4_WRCLI2__URG_LOW__SHIFT
38140. DAGB4_WRCLI2__VIRT_CHAN_MASK
38141. DAGB4_WRCLI2__VIRT_CHAN__SHIFT
38142. DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK
38143. DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT
38144. DAGB4_WRCLI3__MAX_BW_ENABLE_MASK
38145. DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT
38146. DAGB4_WRCLI3__MAX_BW_MASK
38147. DAGB4_WRCLI3__MAX_BW__SHIFT
38148. DAGB4_WRCLI3__MAX_OSD_MASK
38149. DAGB4_WRCLI3__MAX_OSD__SHIFT
38150. DAGB4_WRCLI3__MIN_BW_ENABLE_MASK
38151. DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT
38152. DAGB4_WRCLI3__MIN_BW_MASK
38153. DAGB4_WRCLI3__MIN_BW__SHIFT
38154. DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK
38155. DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
38156. DAGB4_WRCLI3__URG_HIGH_MASK
38157. DAGB4_WRCLI3__URG_HIGH__SHIFT
38158. DAGB4_WRCLI3__URG_LOW_MASK
38159. DAGB4_WRCLI3__URG_LOW__SHIFT
38160. DAGB4_WRCLI3__VIRT_CHAN_MASK
38161. DAGB4_WRCLI3__VIRT_CHAN__SHIFT
38162. DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK
38163. DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT
38164. DAGB4_WRCLI4__MAX_BW_ENABLE_MASK
38165. DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT
38166. DAGB4_WRCLI4__MAX_BW_MASK
38167. DAGB4_WRCLI4__MAX_BW__SHIFT
38168. DAGB4_WRCLI4__MAX_OSD_MASK
38169. DAGB4_WRCLI4__MAX_OSD__SHIFT
38170. DAGB4_WRCLI4__MIN_BW_ENABLE_MASK
38171. DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT
38172. DAGB4_WRCLI4__MIN_BW_MASK
38173. DAGB4_WRCLI4__MIN_BW__SHIFT
38174. DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK
38175. DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
38176. DAGB4_WRCLI4__URG_HIGH_MASK
38177. DAGB4_WRCLI4__URG_HIGH__SHIFT
38178. DAGB4_WRCLI4__URG_LOW_MASK
38179. DAGB4_WRCLI4__URG_LOW__SHIFT
38180. DAGB4_WRCLI4__VIRT_CHAN_MASK
38181. DAGB4_WRCLI4__VIRT_CHAN__SHIFT
38182. DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK
38183. DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT
38184. DAGB4_WRCLI5__MAX_BW_ENABLE_MASK
38185. DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT
38186. DAGB4_WRCLI5__MAX_BW_MASK
38187. DAGB4_WRCLI5__MAX_BW__SHIFT
38188. DAGB4_WRCLI5__MAX_OSD_MASK
38189. DAGB4_WRCLI5__MAX_OSD__SHIFT
38190. DAGB4_WRCLI5__MIN_BW_ENABLE_MASK
38191. DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT
38192. DAGB4_WRCLI5__MIN_BW_MASK
38193. DAGB4_WRCLI5__MIN_BW__SHIFT
38194. DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK
38195. DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
38196. DAGB4_WRCLI5__URG_HIGH_MASK
38197. DAGB4_WRCLI5__URG_HIGH__SHIFT
38198. DAGB4_WRCLI5__URG_LOW_MASK
38199. DAGB4_WRCLI5__URG_LOW__SHIFT
38200. DAGB4_WRCLI5__VIRT_CHAN_MASK
38201. DAGB4_WRCLI5__VIRT_CHAN__SHIFT
38202. DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK
38203. DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT
38204. DAGB4_WRCLI6__MAX_BW_ENABLE_MASK
38205. DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT
38206. DAGB4_WRCLI6__MAX_BW_MASK
38207. DAGB4_WRCLI6__MAX_BW__SHIFT
38208. DAGB4_WRCLI6__MAX_OSD_MASK
38209. DAGB4_WRCLI6__MAX_OSD__SHIFT
38210. DAGB4_WRCLI6__MIN_BW_ENABLE_MASK
38211. DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT
38212. DAGB4_WRCLI6__MIN_BW_MASK
38213. DAGB4_WRCLI6__MIN_BW__SHIFT
38214. DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK
38215. DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
38216. DAGB4_WRCLI6__URG_HIGH_MASK
38217. DAGB4_WRCLI6__URG_HIGH__SHIFT
38218. DAGB4_WRCLI6__URG_LOW_MASK
38219. DAGB4_WRCLI6__URG_LOW__SHIFT
38220. DAGB4_WRCLI6__VIRT_CHAN_MASK
38221. DAGB4_WRCLI6__VIRT_CHAN__SHIFT
38222. DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK
38223. DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT
38224. DAGB4_WRCLI7__MAX_BW_ENABLE_MASK
38225. DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT
38226. DAGB4_WRCLI7__MAX_BW_MASK
38227. DAGB4_WRCLI7__MAX_BW__SHIFT
38228. DAGB4_WRCLI7__MAX_OSD_MASK
38229. DAGB4_WRCLI7__MAX_OSD__SHIFT
38230. DAGB4_WRCLI7__MIN_BW_ENABLE_MASK
38231. DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT
38232. DAGB4_WRCLI7__MIN_BW_MASK
38233. DAGB4_WRCLI7__MIN_BW__SHIFT
38234. DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK
38235. DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
38236. DAGB4_WRCLI7__URG_HIGH_MASK
38237. DAGB4_WRCLI7__URG_HIGH__SHIFT
38238. DAGB4_WRCLI7__URG_LOW_MASK
38239. DAGB4_WRCLI7__URG_LOW__SHIFT
38240. DAGB4_WRCLI7__VIRT_CHAN_MASK
38241. DAGB4_WRCLI7__VIRT_CHAN__SHIFT
38242. DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK
38243. DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT
38244. DAGB4_WRCLI8__MAX_BW_ENABLE_MASK
38245. DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT
38246. DAGB4_WRCLI8__MAX_BW_MASK
38247. DAGB4_WRCLI8__MAX_BW__SHIFT
38248. DAGB4_WRCLI8__MAX_OSD_MASK
38249. DAGB4_WRCLI8__MAX_OSD__SHIFT
38250. DAGB4_WRCLI8__MIN_BW_ENABLE_MASK
38251. DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT
38252. DAGB4_WRCLI8__MIN_BW_MASK
38253. DAGB4_WRCLI8__MIN_BW__SHIFT
38254. DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK
38255. DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
38256. DAGB4_WRCLI8__URG_HIGH_MASK
38257. DAGB4_WRCLI8__URG_HIGH__SHIFT
38258. DAGB4_WRCLI8__URG_LOW_MASK
38259. DAGB4_WRCLI8__URG_LOW__SHIFT
38260. DAGB4_WRCLI8__VIRT_CHAN_MASK
38261. DAGB4_WRCLI8__VIRT_CHAN__SHIFT
38262. DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK
38263. DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT
38264. DAGB4_WRCLI9__MAX_BW_ENABLE_MASK
38265. DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT
38266. DAGB4_WRCLI9__MAX_BW_MASK
38267. DAGB4_WRCLI9__MAX_BW__SHIFT
38268. DAGB4_WRCLI9__MAX_OSD_MASK
38269. DAGB4_WRCLI9__MAX_OSD__SHIFT
38270. DAGB4_WRCLI9__MIN_BW_ENABLE_MASK
38271. DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT
38272. DAGB4_WRCLI9__MIN_BW_MASK
38273. DAGB4_WRCLI9__MIN_BW__SHIFT
38274. DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK
38275. DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
38276. DAGB4_WRCLI9__URG_HIGH_MASK
38277. DAGB4_WRCLI9__URG_HIGH__SHIFT
38278. DAGB4_WRCLI9__URG_LOW_MASK
38279. DAGB4_WRCLI9__URG_LOW__SHIFT
38280. DAGB4_WRCLI9__VIRT_CHAN_MASK
38281. DAGB4_WRCLI9__VIRT_CHAN__SHIFT
38282. DAGB4_WRCLI_ASK_PENDING__BUSY_MASK
38283. DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT
38284. DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
38285. DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
38286. DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK
38287. DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
38288. DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK
38289. DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
38290. DAGB4_WRCLI_GO_PENDING__BUSY_MASK
38291. DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT
38292. DAGB4_WRCLI_OARB_PENDING__BUSY_MASK
38293. DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT
38294. DAGB4_WRCLI_OSD_PENDING__BUSY_MASK
38295. DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT
38296. DAGB4_WRCLI_TLB_PENDING__BUSY_MASK
38297. DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT
38298. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
38299. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
38300. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
38301. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
38302. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
38303. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
38304. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
38305. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
38306. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
38307. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
38308. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
38309. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
38310. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
38311. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
38312. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
38313. DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
38314. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
38315. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
38316. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
38317. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
38318. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
38319. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
38320. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
38321. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
38322. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
38323. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
38324. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
38325. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
38326. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
38327. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
38328. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
38329. DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
38330. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
38331. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
38332. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
38333. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
38334. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
38335. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
38336. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
38337. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
38338. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
38339. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
38340. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
38341. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
38342. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
38343. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
38344. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
38345. DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
38346. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
38347. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
38348. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
38349. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
38350. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
38351. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
38352. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
38353. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
38354. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
38355. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
38356. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
38357. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
38358. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
38359. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
38360. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
38361. DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
38362. DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK
38363. DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
38364. DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
38365. DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
38366. DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
38367. DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
38368. DAGB4_WR_ADDR_DAGB__WHOAMI_MASK
38369. DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT
38370. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
38371. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
38372. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
38373. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
38374. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
38375. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
38376. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
38377. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
38378. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
38379. DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
38380. DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
38381. DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
38382. DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
38383. DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
38384. DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
38385. DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
38386. DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
38387. DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
38388. DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
38389. DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
38390. DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK
38391. DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
38392. DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
38393. DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
38394. DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
38395. DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
38396. DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
38397. DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
38398. DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK
38399. DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT
38400. DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
38401. DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
38402. DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
38403. DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
38404. DAGB4_WR_CNTL__IO_LEVEL_MASK
38405. DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
38406. DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
38407. DAGB4_WR_CNTL__IO_LEVEL__SHIFT
38408. DAGB4_WR_CNTL__SCLK_FREQ_MASK
38409. DAGB4_WR_CNTL__SCLK_FREQ__SHIFT
38410. DAGB4_WR_CNTL__SHARE_VC_NUM_MASK
38411. DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT
38412. DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK
38413. DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
38414. DAGB4_WR_CREDITS_FULL__FULL_MASK
38415. DAGB4_WR_CREDITS_FULL__FULL__SHIFT
38416. DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
38417. DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
38418. DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
38419. DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
38420. DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
38421. DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
38422. DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
38423. DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
38424. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
38425. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
38426. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
38427. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
38428. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
38429. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
38430. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
38431. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
38432. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
38433. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
38434. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
38435. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
38436. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
38437. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
38438. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
38439. DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
38440. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
38441. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
38442. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
38443. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
38444. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
38445. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
38446. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
38447. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
38448. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
38449. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
38450. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
38451. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
38452. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
38453. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
38454. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
38455. DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
38456. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
38457. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
38458. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
38459. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
38460. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
38461. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
38462. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
38463. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
38464. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
38465. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
38466. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
38467. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
38468. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
38469. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
38470. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
38471. DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
38472. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
38473. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
38474. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
38475. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
38476. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
38477. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
38478. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
38479. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
38480. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
38481. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
38482. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
38483. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
38484. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
38485. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
38486. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
38487. DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
38488. DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK
38489. DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
38490. DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
38491. DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
38492. DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
38493. DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
38494. DAGB4_WR_DATA_DAGB__WHOAMI_MASK
38495. DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT
38496. DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK
38497. DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT
38498. DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK
38499. DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT
38500. DAGB4_WR_GMI_CNTL__LEVEL_MASK
38501. DAGB4_WR_GMI_CNTL__LEVEL__SHIFT
38502. DAGB4_WR_GMI_CNTL__MAX_BURST_MASK
38503. DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT
38504. DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
38505. DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
38506. DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
38507. DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
38508. DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK
38509. DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
38510. DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
38511. DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
38512. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
38513. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
38514. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
38515. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
38516. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
38517. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
38518. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
38519. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
38520. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
38521. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
38522. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
38523. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
38524. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
38525. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
38526. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
38527. DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
38528. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
38529. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
38530. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
38531. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
38532. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
38533. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
38534. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
38535. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
38536. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
38537. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
38538. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
38539. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
38540. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
38541. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
38542. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
38543. DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
38544. DAGB4_WR_TLB_CREDIT__TLB0_MASK
38545. DAGB4_WR_TLB_CREDIT__TLB0__SHIFT
38546. DAGB4_WR_TLB_CREDIT__TLB1_MASK
38547. DAGB4_WR_TLB_CREDIT__TLB1__SHIFT
38548. DAGB4_WR_TLB_CREDIT__TLB2_MASK
38549. DAGB4_WR_TLB_CREDIT__TLB2__SHIFT
38550. DAGB4_WR_TLB_CREDIT__TLB3_MASK
38551. DAGB4_WR_TLB_CREDIT__TLB3__SHIFT
38552. DAGB4_WR_TLB_CREDIT__TLB4_MASK
38553. DAGB4_WR_TLB_CREDIT__TLB4__SHIFT
38554. DAGB4_WR_TLB_CREDIT__TLB5_MASK
38555. DAGB4_WR_TLB_CREDIT__TLB5__SHIFT
38556. DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK
38557. DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT
38558. DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
38559. DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
38560. DAGB4_WR_VC0_CNTL__MAX_BW_MASK
38561. DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT
38562. DAGB4_WR_VC0_CNTL__MAX_OSD_MASK
38563. DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT
38564. DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
38565. DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
38566. DAGB4_WR_VC0_CNTL__MIN_BW_MASK
38567. DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT
38568. DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
38569. DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
38570. DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK
38571. DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT
38572. DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK
38573. DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT
38574. DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
38575. DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
38576. DAGB4_WR_VC1_CNTL__MAX_BW_MASK
38577. DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT
38578. DAGB4_WR_VC1_CNTL__MAX_OSD_MASK
38579. DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT
38580. DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
38581. DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
38582. DAGB4_WR_VC1_CNTL__MIN_BW_MASK
38583. DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT
38584. DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
38585. DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
38586. DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK
38587. DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT
38588. DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK
38589. DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT
38590. DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
38591. DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
38592. DAGB4_WR_VC2_CNTL__MAX_BW_MASK
38593. DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT
38594. DAGB4_WR_VC2_CNTL__MAX_OSD_MASK
38595. DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT
38596. DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
38597. DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
38598. DAGB4_WR_VC2_CNTL__MIN_BW_MASK
38599. DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT
38600. DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
38601. DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
38602. DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK
38603. DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT
38604. DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK
38605. DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT
38606. DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
38607. DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
38608. DAGB4_WR_VC3_CNTL__MAX_BW_MASK
38609. DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT
38610. DAGB4_WR_VC3_CNTL__MAX_OSD_MASK
38611. DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT
38612. DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
38613. DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
38614. DAGB4_WR_VC3_CNTL__MIN_BW_MASK
38615. DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT
38616. DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
38617. DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
38618. DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK
38619. DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT
38620. DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK
38621. DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT
38622. DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
38623. DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
38624. DAGB4_WR_VC4_CNTL__MAX_BW_MASK
38625. DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT
38626. DAGB4_WR_VC4_CNTL__MAX_OSD_MASK
38627. DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT
38628. DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
38629. DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
38630. DAGB4_WR_VC4_CNTL__MIN_BW_MASK
38631. DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT
38632. DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
38633. DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
38634. DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK
38635. DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT
38636. DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK
38637. DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT
38638. DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
38639. DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
38640. DAGB4_WR_VC5_CNTL__MAX_BW_MASK
38641. DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT
38642. DAGB4_WR_VC5_CNTL__MAX_OSD_MASK
38643. DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT
38644. DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
38645. DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
38646. DAGB4_WR_VC5_CNTL__MIN_BW_MASK
38647. DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT
38648. DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
38649. DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
38650. DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK
38651. DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT
38652. DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK
38653. DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT
38654. DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
38655. DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
38656. DAGB4_WR_VC6_CNTL__MAX_BW_MASK
38657. DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT
38658. DAGB4_WR_VC6_CNTL__MAX_OSD_MASK
38659. DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT
38660. DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
38661. DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
38662. DAGB4_WR_VC6_CNTL__MIN_BW_MASK
38663. DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT
38664. DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
38665. DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
38666. DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK
38667. DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT
38668. DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK
38669. DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT
38670. DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
38671. DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
38672. DAGB4_WR_VC7_CNTL__MAX_BW_MASK
38673. DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT
38674. DAGB4_WR_VC7_CNTL__MAX_OSD_MASK
38675. DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT
38676. DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
38677. DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
38678. DAGB4_WR_VC7_CNTL__MIN_BW_MASK
38679. DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT
38680. DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
38681. DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
38682. DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK
38683. DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT
38684. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
38685. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
38686. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
38687. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
38688. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
38689. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
38690. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
38691. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
38692. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
38693. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
38694. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
38695. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
38696. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
38697. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
38698. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
38699. DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
38700. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
38701. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
38702. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
38703. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
38704. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
38705. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
38706. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
38707. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
38708. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
38709. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
38710. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
38711. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
38712. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
38713. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
38714. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
38715. DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
38716. DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
38717. DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
38718. DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
38719. DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
38720. DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
38721. DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
38722. DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK
38723. DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
38724. DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
38725. DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
38726. DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
38727. DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
38728. DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
38729. DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
38730. DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK
38731. DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
38732. DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
38733. DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
38734. DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK
38735. DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
38736. DAGB5_CNTL_MISC2__SWAP_CTL_MASK
38737. DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT
38738. DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK
38739. DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
38740. DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK
38741. DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
38742. DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK
38743. DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT
38744. DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
38745. DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
38746. DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK
38747. DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT
38748. DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK
38749. DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT
38750. DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK
38751. DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT
38752. DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK
38753. DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT
38754. DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK
38755. DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT
38756. DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK
38757. DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT
38758. DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK
38759. DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT
38760. DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK
38761. DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT
38762. DAGB5_DAGB_DLY__CLI_MASK
38763. DAGB5_DAGB_DLY__CLI__SHIFT
38764. DAGB5_DAGB_DLY__DLY_MASK
38765. DAGB5_DAGB_DLY__DLY__SHIFT
38766. DAGB5_DAGB_DLY__POS_MASK
38767. DAGB5_DAGB_DLY__POS__SHIFT
38768. DAGB5_FIFO_EMPTY__EMPTY_MASK
38769. DAGB5_FIFO_EMPTY__EMPTY__SHIFT
38770. DAGB5_FIFO_FULL__FULL_MASK
38771. DAGB5_FIFO_FULL__FULL__SHIFT
38772. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
38773. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
38774. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
38775. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
38776. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
38777. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
38778. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
38779. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
38780. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
38781. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
38782. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
38783. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
38784. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
38785. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
38786. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
38787. DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
38788. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
38789. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
38790. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
38791. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
38792. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
38793. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
38794. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
38795. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
38796. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
38797. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
38798. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
38799. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
38800. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
38801. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
38802. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
38803. DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
38804. DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK
38805. DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT
38806. DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK
38807. DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT
38808. DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK
38809. DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
38810. DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
38811. DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
38812. DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK
38813. DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
38814. DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK
38815. DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT
38816. DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK
38817. DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT
38818. DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK
38819. DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
38820. DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
38821. DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
38822. DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK
38823. DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
38824. DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK
38825. DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT
38826. DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK
38827. DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT
38828. DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK
38829. DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
38830. DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
38831. DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
38832. DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK
38833. DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
38834. DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK
38835. DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
38836. DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK
38837. DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT
38838. DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK
38839. DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT
38840. DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
38841. DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
38842. DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
38843. DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
38844. DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
38845. DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
38846. DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
38847. DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
38848. DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
38849. DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
38850. DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
38851. DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
38852. DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK
38853. DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT
38854. DAGB5_RDCLI0__MAX_BW_ENABLE_MASK
38855. DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT
38856. DAGB5_RDCLI0__MAX_BW_MASK
38857. DAGB5_RDCLI0__MAX_BW__SHIFT
38858. DAGB5_RDCLI0__MAX_OSD_MASK
38859. DAGB5_RDCLI0__MAX_OSD__SHIFT
38860. DAGB5_RDCLI0__MIN_BW_ENABLE_MASK
38861. DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT
38862. DAGB5_RDCLI0__MIN_BW_MASK
38863. DAGB5_RDCLI0__MIN_BW__SHIFT
38864. DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK
38865. DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
38866. DAGB5_RDCLI0__URG_HIGH_MASK
38867. DAGB5_RDCLI0__URG_HIGH__SHIFT
38868. DAGB5_RDCLI0__URG_LOW_MASK
38869. DAGB5_RDCLI0__URG_LOW__SHIFT
38870. DAGB5_RDCLI0__VIRT_CHAN_MASK
38871. DAGB5_RDCLI0__VIRT_CHAN__SHIFT
38872. DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK
38873. DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT
38874. DAGB5_RDCLI10__MAX_BW_ENABLE_MASK
38875. DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT
38876. DAGB5_RDCLI10__MAX_BW_MASK
38877. DAGB5_RDCLI10__MAX_BW__SHIFT
38878. DAGB5_RDCLI10__MAX_OSD_MASK
38879. DAGB5_RDCLI10__MAX_OSD__SHIFT
38880. DAGB5_RDCLI10__MIN_BW_ENABLE_MASK
38881. DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT
38882. DAGB5_RDCLI10__MIN_BW_MASK
38883. DAGB5_RDCLI10__MIN_BW__SHIFT
38884. DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK
38885. DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
38886. DAGB5_RDCLI10__URG_HIGH_MASK
38887. DAGB5_RDCLI10__URG_HIGH__SHIFT
38888. DAGB5_RDCLI10__URG_LOW_MASK
38889. DAGB5_RDCLI10__URG_LOW__SHIFT
38890. DAGB5_RDCLI10__VIRT_CHAN_MASK
38891. DAGB5_RDCLI10__VIRT_CHAN__SHIFT
38892. DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK
38893. DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT
38894. DAGB5_RDCLI11__MAX_BW_ENABLE_MASK
38895. DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT
38896. DAGB5_RDCLI11__MAX_BW_MASK
38897. DAGB5_RDCLI11__MAX_BW__SHIFT
38898. DAGB5_RDCLI11__MAX_OSD_MASK
38899. DAGB5_RDCLI11__MAX_OSD__SHIFT
38900. DAGB5_RDCLI11__MIN_BW_ENABLE_MASK
38901. DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT
38902. DAGB5_RDCLI11__MIN_BW_MASK
38903. DAGB5_RDCLI11__MIN_BW__SHIFT
38904. DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK
38905. DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
38906. DAGB5_RDCLI11__URG_HIGH_MASK
38907. DAGB5_RDCLI11__URG_HIGH__SHIFT
38908. DAGB5_RDCLI11__URG_LOW_MASK
38909. DAGB5_RDCLI11__URG_LOW__SHIFT
38910. DAGB5_RDCLI11__VIRT_CHAN_MASK
38911. DAGB5_RDCLI11__VIRT_CHAN__SHIFT
38912. DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK
38913. DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT
38914. DAGB5_RDCLI12__MAX_BW_ENABLE_MASK
38915. DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT
38916. DAGB5_RDCLI12__MAX_BW_MASK
38917. DAGB5_RDCLI12__MAX_BW__SHIFT
38918. DAGB5_RDCLI12__MAX_OSD_MASK
38919. DAGB5_RDCLI12__MAX_OSD__SHIFT
38920. DAGB5_RDCLI12__MIN_BW_ENABLE_MASK
38921. DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT
38922. DAGB5_RDCLI12__MIN_BW_MASK
38923. DAGB5_RDCLI12__MIN_BW__SHIFT
38924. DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK
38925. DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
38926. DAGB5_RDCLI12__URG_HIGH_MASK
38927. DAGB5_RDCLI12__URG_HIGH__SHIFT
38928. DAGB5_RDCLI12__URG_LOW_MASK
38929. DAGB5_RDCLI12__URG_LOW__SHIFT
38930. DAGB5_RDCLI12__VIRT_CHAN_MASK
38931. DAGB5_RDCLI12__VIRT_CHAN__SHIFT
38932. DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK
38933. DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT
38934. DAGB5_RDCLI13__MAX_BW_ENABLE_MASK
38935. DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT
38936. DAGB5_RDCLI13__MAX_BW_MASK
38937. DAGB5_RDCLI13__MAX_BW__SHIFT
38938. DAGB5_RDCLI13__MAX_OSD_MASK
38939. DAGB5_RDCLI13__MAX_OSD__SHIFT
38940. DAGB5_RDCLI13__MIN_BW_ENABLE_MASK
38941. DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT
38942. DAGB5_RDCLI13__MIN_BW_MASK
38943. DAGB5_RDCLI13__MIN_BW__SHIFT
38944. DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK
38945. DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
38946. DAGB5_RDCLI13__URG_HIGH_MASK
38947. DAGB5_RDCLI13__URG_HIGH__SHIFT
38948. DAGB5_RDCLI13__URG_LOW_MASK
38949. DAGB5_RDCLI13__URG_LOW__SHIFT
38950. DAGB5_RDCLI13__VIRT_CHAN_MASK
38951. DAGB5_RDCLI13__VIRT_CHAN__SHIFT
38952. DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK
38953. DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT
38954. DAGB5_RDCLI14__MAX_BW_ENABLE_MASK
38955. DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT
38956. DAGB5_RDCLI14__MAX_BW_MASK
38957. DAGB5_RDCLI14__MAX_BW__SHIFT
38958. DAGB5_RDCLI14__MAX_OSD_MASK
38959. DAGB5_RDCLI14__MAX_OSD__SHIFT
38960. DAGB5_RDCLI14__MIN_BW_ENABLE_MASK
38961. DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT
38962. DAGB5_RDCLI14__MIN_BW_MASK
38963. DAGB5_RDCLI14__MIN_BW__SHIFT
38964. DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK
38965. DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
38966. DAGB5_RDCLI14__URG_HIGH_MASK
38967. DAGB5_RDCLI14__URG_HIGH__SHIFT
38968. DAGB5_RDCLI14__URG_LOW_MASK
38969. DAGB5_RDCLI14__URG_LOW__SHIFT
38970. DAGB5_RDCLI14__VIRT_CHAN_MASK
38971. DAGB5_RDCLI14__VIRT_CHAN__SHIFT
38972. DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK
38973. DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT
38974. DAGB5_RDCLI15__MAX_BW_ENABLE_MASK
38975. DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT
38976. DAGB5_RDCLI15__MAX_BW_MASK
38977. DAGB5_RDCLI15__MAX_BW__SHIFT
38978. DAGB5_RDCLI15__MAX_OSD_MASK
38979. DAGB5_RDCLI15__MAX_OSD__SHIFT
38980. DAGB5_RDCLI15__MIN_BW_ENABLE_MASK
38981. DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT
38982. DAGB5_RDCLI15__MIN_BW_MASK
38983. DAGB5_RDCLI15__MIN_BW__SHIFT
38984. DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK
38985. DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
38986. DAGB5_RDCLI15__URG_HIGH_MASK
38987. DAGB5_RDCLI15__URG_HIGH__SHIFT
38988. DAGB5_RDCLI15__URG_LOW_MASK
38989. DAGB5_RDCLI15__URG_LOW__SHIFT
38990. DAGB5_RDCLI15__VIRT_CHAN_MASK
38991. DAGB5_RDCLI15__VIRT_CHAN__SHIFT
38992. DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK
38993. DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT
38994. DAGB5_RDCLI1__MAX_BW_ENABLE_MASK
38995. DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT
38996. DAGB5_RDCLI1__MAX_BW_MASK
38997. DAGB5_RDCLI1__MAX_BW__SHIFT
38998. DAGB5_RDCLI1__MAX_OSD_MASK
38999. DAGB5_RDCLI1__MAX_OSD__SHIFT
39000. DAGB5_RDCLI1__MIN_BW_ENABLE_MASK
39001. DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT
39002. DAGB5_RDCLI1__MIN_BW_MASK
39003. DAGB5_RDCLI1__MIN_BW__SHIFT
39004. DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK
39005. DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
39006. DAGB5_RDCLI1__URG_HIGH_MASK
39007. DAGB5_RDCLI1__URG_HIGH__SHIFT
39008. DAGB5_RDCLI1__URG_LOW_MASK
39009. DAGB5_RDCLI1__URG_LOW__SHIFT
39010. DAGB5_RDCLI1__VIRT_CHAN_MASK
39011. DAGB5_RDCLI1__VIRT_CHAN__SHIFT
39012. DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK
39013. DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT
39014. DAGB5_RDCLI2__MAX_BW_ENABLE_MASK
39015. DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT
39016. DAGB5_RDCLI2__MAX_BW_MASK
39017. DAGB5_RDCLI2__MAX_BW__SHIFT
39018. DAGB5_RDCLI2__MAX_OSD_MASK
39019. DAGB5_RDCLI2__MAX_OSD__SHIFT
39020. DAGB5_RDCLI2__MIN_BW_ENABLE_MASK
39021. DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT
39022. DAGB5_RDCLI2__MIN_BW_MASK
39023. DAGB5_RDCLI2__MIN_BW__SHIFT
39024. DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK
39025. DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
39026. DAGB5_RDCLI2__URG_HIGH_MASK
39027. DAGB5_RDCLI2__URG_HIGH__SHIFT
39028. DAGB5_RDCLI2__URG_LOW_MASK
39029. DAGB5_RDCLI2__URG_LOW__SHIFT
39030. DAGB5_RDCLI2__VIRT_CHAN_MASK
39031. DAGB5_RDCLI2__VIRT_CHAN__SHIFT
39032. DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK
39033. DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT
39034. DAGB5_RDCLI3__MAX_BW_ENABLE_MASK
39035. DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT
39036. DAGB5_RDCLI3__MAX_BW_MASK
39037. DAGB5_RDCLI3__MAX_BW__SHIFT
39038. DAGB5_RDCLI3__MAX_OSD_MASK
39039. DAGB5_RDCLI3__MAX_OSD__SHIFT
39040. DAGB5_RDCLI3__MIN_BW_ENABLE_MASK
39041. DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT
39042. DAGB5_RDCLI3__MIN_BW_MASK
39043. DAGB5_RDCLI3__MIN_BW__SHIFT
39044. DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK
39045. DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
39046. DAGB5_RDCLI3__URG_HIGH_MASK
39047. DAGB5_RDCLI3__URG_HIGH__SHIFT
39048. DAGB5_RDCLI3__URG_LOW_MASK
39049. DAGB5_RDCLI3__URG_LOW__SHIFT
39050. DAGB5_RDCLI3__VIRT_CHAN_MASK
39051. DAGB5_RDCLI3__VIRT_CHAN__SHIFT
39052. DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK
39053. DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT
39054. DAGB5_RDCLI4__MAX_BW_ENABLE_MASK
39055. DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT
39056. DAGB5_RDCLI4__MAX_BW_MASK
39057. DAGB5_RDCLI4__MAX_BW__SHIFT
39058. DAGB5_RDCLI4__MAX_OSD_MASK
39059. DAGB5_RDCLI4__MAX_OSD__SHIFT
39060. DAGB5_RDCLI4__MIN_BW_ENABLE_MASK
39061. DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT
39062. DAGB5_RDCLI4__MIN_BW_MASK
39063. DAGB5_RDCLI4__MIN_BW__SHIFT
39064. DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK
39065. DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
39066. DAGB5_RDCLI4__URG_HIGH_MASK
39067. DAGB5_RDCLI4__URG_HIGH__SHIFT
39068. DAGB5_RDCLI4__URG_LOW_MASK
39069. DAGB5_RDCLI4__URG_LOW__SHIFT
39070. DAGB5_RDCLI4__VIRT_CHAN_MASK
39071. DAGB5_RDCLI4__VIRT_CHAN__SHIFT
39072. DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK
39073. DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT
39074. DAGB5_RDCLI5__MAX_BW_ENABLE_MASK
39075. DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT
39076. DAGB5_RDCLI5__MAX_BW_MASK
39077. DAGB5_RDCLI5__MAX_BW__SHIFT
39078. DAGB5_RDCLI5__MAX_OSD_MASK
39079. DAGB5_RDCLI5__MAX_OSD__SHIFT
39080. DAGB5_RDCLI5__MIN_BW_ENABLE_MASK
39081. DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT
39082. DAGB5_RDCLI5__MIN_BW_MASK
39083. DAGB5_RDCLI5__MIN_BW__SHIFT
39084. DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK
39085. DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
39086. DAGB5_RDCLI5__URG_HIGH_MASK
39087. DAGB5_RDCLI5__URG_HIGH__SHIFT
39088. DAGB5_RDCLI5__URG_LOW_MASK
39089. DAGB5_RDCLI5__URG_LOW__SHIFT
39090. DAGB5_RDCLI5__VIRT_CHAN_MASK
39091. DAGB5_RDCLI5__VIRT_CHAN__SHIFT
39092. DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK
39093. DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT
39094. DAGB5_RDCLI6__MAX_BW_ENABLE_MASK
39095. DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT
39096. DAGB5_RDCLI6__MAX_BW_MASK
39097. DAGB5_RDCLI6__MAX_BW__SHIFT
39098. DAGB5_RDCLI6__MAX_OSD_MASK
39099. DAGB5_RDCLI6__MAX_OSD__SHIFT
39100. DAGB5_RDCLI6__MIN_BW_ENABLE_MASK
39101. DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT
39102. DAGB5_RDCLI6__MIN_BW_MASK
39103. DAGB5_RDCLI6__MIN_BW__SHIFT
39104. DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK
39105. DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
39106. DAGB5_RDCLI6__URG_HIGH_MASK
39107. DAGB5_RDCLI6__URG_HIGH__SHIFT
39108. DAGB5_RDCLI6__URG_LOW_MASK
39109. DAGB5_RDCLI6__URG_LOW__SHIFT
39110. DAGB5_RDCLI6__VIRT_CHAN_MASK
39111. DAGB5_RDCLI6__VIRT_CHAN__SHIFT
39112. DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK
39113. DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT
39114. DAGB5_RDCLI7__MAX_BW_ENABLE_MASK
39115. DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT
39116. DAGB5_RDCLI7__MAX_BW_MASK
39117. DAGB5_RDCLI7__MAX_BW__SHIFT
39118. DAGB5_RDCLI7__MAX_OSD_MASK
39119. DAGB5_RDCLI7__MAX_OSD__SHIFT
39120. DAGB5_RDCLI7__MIN_BW_ENABLE_MASK
39121. DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT
39122. DAGB5_RDCLI7__MIN_BW_MASK
39123. DAGB5_RDCLI7__MIN_BW__SHIFT
39124. DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK
39125. DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
39126. DAGB5_RDCLI7__URG_HIGH_MASK
39127. DAGB5_RDCLI7__URG_HIGH__SHIFT
39128. DAGB5_RDCLI7__URG_LOW_MASK
39129. DAGB5_RDCLI7__URG_LOW__SHIFT
39130. DAGB5_RDCLI7__VIRT_CHAN_MASK
39131. DAGB5_RDCLI7__VIRT_CHAN__SHIFT
39132. DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK
39133. DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT
39134. DAGB5_RDCLI8__MAX_BW_ENABLE_MASK
39135. DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT
39136. DAGB5_RDCLI8__MAX_BW_MASK
39137. DAGB5_RDCLI8__MAX_BW__SHIFT
39138. DAGB5_RDCLI8__MAX_OSD_MASK
39139. DAGB5_RDCLI8__MAX_OSD__SHIFT
39140. DAGB5_RDCLI8__MIN_BW_ENABLE_MASK
39141. DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT
39142. DAGB5_RDCLI8__MIN_BW_MASK
39143. DAGB5_RDCLI8__MIN_BW__SHIFT
39144. DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK
39145. DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
39146. DAGB5_RDCLI8__URG_HIGH_MASK
39147. DAGB5_RDCLI8__URG_HIGH__SHIFT
39148. DAGB5_RDCLI8__URG_LOW_MASK
39149. DAGB5_RDCLI8__URG_LOW__SHIFT
39150. DAGB5_RDCLI8__VIRT_CHAN_MASK
39151. DAGB5_RDCLI8__VIRT_CHAN__SHIFT
39152. DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK
39153. DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT
39154. DAGB5_RDCLI9__MAX_BW_ENABLE_MASK
39155. DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT
39156. DAGB5_RDCLI9__MAX_BW_MASK
39157. DAGB5_RDCLI9__MAX_BW__SHIFT
39158. DAGB5_RDCLI9__MAX_OSD_MASK
39159. DAGB5_RDCLI9__MAX_OSD__SHIFT
39160. DAGB5_RDCLI9__MIN_BW_ENABLE_MASK
39161. DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT
39162. DAGB5_RDCLI9__MIN_BW_MASK
39163. DAGB5_RDCLI9__MIN_BW__SHIFT
39164. DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK
39165. DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
39166. DAGB5_RDCLI9__URG_HIGH_MASK
39167. DAGB5_RDCLI9__URG_HIGH__SHIFT
39168. DAGB5_RDCLI9__URG_LOW_MASK
39169. DAGB5_RDCLI9__URG_LOW__SHIFT
39170. DAGB5_RDCLI9__VIRT_CHAN_MASK
39171. DAGB5_RDCLI9__VIRT_CHAN__SHIFT
39172. DAGB5_RDCLI_ASK_PENDING__BUSY_MASK
39173. DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT
39174. DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK
39175. DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
39176. DAGB5_RDCLI_GO_PENDING__BUSY_MASK
39177. DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT
39178. DAGB5_RDCLI_OARB_PENDING__BUSY_MASK
39179. DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT
39180. DAGB5_RDCLI_OSD_PENDING__BUSY_MASK
39181. DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT
39182. DAGB5_RDCLI_TLB_PENDING__BUSY_MASK
39183. DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT
39184. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
39185. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
39186. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
39187. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
39188. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
39189. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
39190. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
39191. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
39192. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
39193. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
39194. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
39195. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
39196. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
39197. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
39198. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
39199. DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
39200. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
39201. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
39202. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
39203. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
39204. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
39205. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
39206. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
39207. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
39208. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
39209. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
39210. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
39211. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
39212. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
39213. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
39214. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
39215. DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
39216. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
39217. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
39218. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
39219. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
39220. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
39221. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
39222. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
39223. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
39224. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
39225. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
39226. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
39227. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
39228. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
39229. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
39230. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
39231. DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
39232. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
39233. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
39234. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
39235. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
39236. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
39237. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
39238. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
39239. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
39240. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
39241. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
39242. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
39243. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
39244. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
39245. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
39246. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
39247. DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
39248. DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK
39249. DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
39250. DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
39251. DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
39252. DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
39253. DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
39254. DAGB5_RD_ADDR_DAGB__WHOAMI_MASK
39255. DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT
39256. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
39257. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
39258. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
39259. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
39260. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
39261. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
39262. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
39263. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
39264. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
39265. DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
39266. DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
39267. DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
39268. DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
39269. DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
39270. DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
39271. DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
39272. DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
39273. DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
39274. DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
39275. DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
39276. DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK
39277. DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
39278. DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
39279. DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
39280. DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
39281. DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
39282. DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
39283. DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
39284. DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK
39285. DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT
39286. DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
39287. DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
39288. DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
39289. DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
39290. DAGB5_RD_CNTL__IO_LEVEL_MASK
39291. DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
39292. DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
39293. DAGB5_RD_CNTL__IO_LEVEL__SHIFT
39294. DAGB5_RD_CNTL__SCLK_FREQ_MASK
39295. DAGB5_RD_CNTL__SCLK_FREQ__SHIFT
39296. DAGB5_RD_CNTL__SHARE_VC_NUM_MASK
39297. DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT
39298. DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK
39299. DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
39300. DAGB5_RD_CREDITS_FULL__FULL_MASK
39301. DAGB5_RD_CREDITS_FULL__FULL__SHIFT
39302. DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK
39303. DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT
39304. DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK
39305. DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT
39306. DAGB5_RD_GMI_CNTL__LEVEL_MASK
39307. DAGB5_RD_GMI_CNTL__LEVEL__SHIFT
39308. DAGB5_RD_GMI_CNTL__MAX_BURST_MASK
39309. DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT
39310. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
39311. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
39312. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
39313. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
39314. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
39315. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
39316. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
39317. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
39318. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
39319. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
39320. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
39321. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
39322. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
39323. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
39324. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
39325. DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
39326. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
39327. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
39328. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
39329. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
39330. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
39331. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
39332. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
39333. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
39334. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
39335. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
39336. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
39337. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
39338. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
39339. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
39340. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
39341. DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
39342. DAGB5_RD_TLB_CREDIT__TLB0_MASK
39343. DAGB5_RD_TLB_CREDIT__TLB0__SHIFT
39344. DAGB5_RD_TLB_CREDIT__TLB1_MASK
39345. DAGB5_RD_TLB_CREDIT__TLB1__SHIFT
39346. DAGB5_RD_TLB_CREDIT__TLB2_MASK
39347. DAGB5_RD_TLB_CREDIT__TLB2__SHIFT
39348. DAGB5_RD_TLB_CREDIT__TLB3_MASK
39349. DAGB5_RD_TLB_CREDIT__TLB3__SHIFT
39350. DAGB5_RD_TLB_CREDIT__TLB4_MASK
39351. DAGB5_RD_TLB_CREDIT__TLB4__SHIFT
39352. DAGB5_RD_TLB_CREDIT__TLB5_MASK
39353. DAGB5_RD_TLB_CREDIT__TLB5__SHIFT
39354. DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK
39355. DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT
39356. DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
39357. DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
39358. DAGB5_RD_VC0_CNTL__MAX_BW_MASK
39359. DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT
39360. DAGB5_RD_VC0_CNTL__MAX_OSD_MASK
39361. DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT
39362. DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
39363. DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
39364. DAGB5_RD_VC0_CNTL__MIN_BW_MASK
39365. DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT
39366. DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
39367. DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
39368. DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK
39369. DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT
39370. DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK
39371. DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT
39372. DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
39373. DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
39374. DAGB5_RD_VC1_CNTL__MAX_BW_MASK
39375. DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT
39376. DAGB5_RD_VC1_CNTL__MAX_OSD_MASK
39377. DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT
39378. DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
39379. DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
39380. DAGB5_RD_VC1_CNTL__MIN_BW_MASK
39381. DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT
39382. DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
39383. DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
39384. DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK
39385. DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT
39386. DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK
39387. DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT
39388. DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
39389. DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
39390. DAGB5_RD_VC2_CNTL__MAX_BW_MASK
39391. DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT
39392. DAGB5_RD_VC2_CNTL__MAX_OSD_MASK
39393. DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT
39394. DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
39395. DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
39396. DAGB5_RD_VC2_CNTL__MIN_BW_MASK
39397. DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT
39398. DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
39399. DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
39400. DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK
39401. DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT
39402. DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK
39403. DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT
39404. DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
39405. DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
39406. DAGB5_RD_VC3_CNTL__MAX_BW_MASK
39407. DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT
39408. DAGB5_RD_VC3_CNTL__MAX_OSD_MASK
39409. DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT
39410. DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
39411. DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
39412. DAGB5_RD_VC3_CNTL__MIN_BW_MASK
39413. DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT
39414. DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
39415. DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
39416. DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK
39417. DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT
39418. DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK
39419. DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT
39420. DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
39421. DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
39422. DAGB5_RD_VC4_CNTL__MAX_BW_MASK
39423. DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT
39424. DAGB5_RD_VC4_CNTL__MAX_OSD_MASK
39425. DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT
39426. DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
39427. DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
39428. DAGB5_RD_VC4_CNTL__MIN_BW_MASK
39429. DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT
39430. DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
39431. DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
39432. DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK
39433. DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT
39434. DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK
39435. DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT
39436. DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
39437. DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
39438. DAGB5_RD_VC5_CNTL__MAX_BW_MASK
39439. DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT
39440. DAGB5_RD_VC5_CNTL__MAX_OSD_MASK
39441. DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT
39442. DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
39443. DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
39444. DAGB5_RD_VC5_CNTL__MIN_BW_MASK
39445. DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT
39446. DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
39447. DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
39448. DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK
39449. DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT
39450. DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK
39451. DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT
39452. DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
39453. DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
39454. DAGB5_RD_VC6_CNTL__MAX_BW_MASK
39455. DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT
39456. DAGB5_RD_VC6_CNTL__MAX_OSD_MASK
39457. DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT
39458. DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
39459. DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
39460. DAGB5_RD_VC6_CNTL__MIN_BW_MASK
39461. DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT
39462. DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
39463. DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
39464. DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK
39465. DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT
39466. DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK
39467. DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT
39468. DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
39469. DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
39470. DAGB5_RD_VC7_CNTL__MAX_BW_MASK
39471. DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT
39472. DAGB5_RD_VC7_CNTL__MAX_OSD_MASK
39473. DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT
39474. DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
39475. DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
39476. DAGB5_RD_VC7_CNTL__MIN_BW_MASK
39477. DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT
39478. DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
39479. DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
39480. DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK
39481. DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT
39482. DAGB5_RESERVE0__RESERVE_MASK
39483. DAGB5_RESERVE0__RESERVE__SHIFT
39484. DAGB5_RESERVE10__RESERVE_MASK
39485. DAGB5_RESERVE10__RESERVE__SHIFT
39486. DAGB5_RESERVE11__RESERVE_MASK
39487. DAGB5_RESERVE11__RESERVE__SHIFT
39488. DAGB5_RESERVE12__RESERVE_MASK
39489. DAGB5_RESERVE12__RESERVE__SHIFT
39490. DAGB5_RESERVE13__RESERVE_MASK
39491. DAGB5_RESERVE13__RESERVE__SHIFT
39492. DAGB5_RESERVE1__RESERVE_MASK
39493. DAGB5_RESERVE1__RESERVE__SHIFT
39494. DAGB5_RESERVE2__RESERVE_MASK
39495. DAGB5_RESERVE2__RESERVE__SHIFT
39496. DAGB5_RESERVE3__RESERVE_MASK
39497. DAGB5_RESERVE3__RESERVE__SHIFT
39498. DAGB5_RESERVE4__RESERVE_MASK
39499. DAGB5_RESERVE4__RESERVE__SHIFT
39500. DAGB5_RESERVE5__RESERVE_MASK
39501. DAGB5_RESERVE5__RESERVE__SHIFT
39502. DAGB5_RESERVE6__RESERVE_MASK
39503. DAGB5_RESERVE6__RESERVE__SHIFT
39504. DAGB5_RESERVE7__RESERVE_MASK
39505. DAGB5_RESERVE7__RESERVE__SHIFT
39506. DAGB5_RESERVE8__RESERVE_MASK
39507. DAGB5_RESERVE8__RESERVE__SHIFT
39508. DAGB5_RESERVE9__RESERVE_MASK
39509. DAGB5_RESERVE9__RESERVE__SHIFT
39510. DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK
39511. DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT
39512. DAGB5_WRCLI0__MAX_BW_ENABLE_MASK
39513. DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT
39514. DAGB5_WRCLI0__MAX_BW_MASK
39515. DAGB5_WRCLI0__MAX_BW__SHIFT
39516. DAGB5_WRCLI0__MAX_OSD_MASK
39517. DAGB5_WRCLI0__MAX_OSD__SHIFT
39518. DAGB5_WRCLI0__MIN_BW_ENABLE_MASK
39519. DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT
39520. DAGB5_WRCLI0__MIN_BW_MASK
39521. DAGB5_WRCLI0__MIN_BW__SHIFT
39522. DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK
39523. DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
39524. DAGB5_WRCLI0__URG_HIGH_MASK
39525. DAGB5_WRCLI0__URG_HIGH__SHIFT
39526. DAGB5_WRCLI0__URG_LOW_MASK
39527. DAGB5_WRCLI0__URG_LOW__SHIFT
39528. DAGB5_WRCLI0__VIRT_CHAN_MASK
39529. DAGB5_WRCLI0__VIRT_CHAN__SHIFT
39530. DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK
39531. DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT
39532. DAGB5_WRCLI10__MAX_BW_ENABLE_MASK
39533. DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT
39534. DAGB5_WRCLI10__MAX_BW_MASK
39535. DAGB5_WRCLI10__MAX_BW__SHIFT
39536. DAGB5_WRCLI10__MAX_OSD_MASK
39537. DAGB5_WRCLI10__MAX_OSD__SHIFT
39538. DAGB5_WRCLI10__MIN_BW_ENABLE_MASK
39539. DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT
39540. DAGB5_WRCLI10__MIN_BW_MASK
39541. DAGB5_WRCLI10__MIN_BW__SHIFT
39542. DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK
39543. DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
39544. DAGB5_WRCLI10__URG_HIGH_MASK
39545. DAGB5_WRCLI10__URG_HIGH__SHIFT
39546. DAGB5_WRCLI10__URG_LOW_MASK
39547. DAGB5_WRCLI10__URG_LOW__SHIFT
39548. DAGB5_WRCLI10__VIRT_CHAN_MASK
39549. DAGB5_WRCLI10__VIRT_CHAN__SHIFT
39550. DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK
39551. DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT
39552. DAGB5_WRCLI11__MAX_BW_ENABLE_MASK
39553. DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT
39554. DAGB5_WRCLI11__MAX_BW_MASK
39555. DAGB5_WRCLI11__MAX_BW__SHIFT
39556. DAGB5_WRCLI11__MAX_OSD_MASK
39557. DAGB5_WRCLI11__MAX_OSD__SHIFT
39558. DAGB5_WRCLI11__MIN_BW_ENABLE_MASK
39559. DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT
39560. DAGB5_WRCLI11__MIN_BW_MASK
39561. DAGB5_WRCLI11__MIN_BW__SHIFT
39562. DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK
39563. DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
39564. DAGB5_WRCLI11__URG_HIGH_MASK
39565. DAGB5_WRCLI11__URG_HIGH__SHIFT
39566. DAGB5_WRCLI11__URG_LOW_MASK
39567. DAGB5_WRCLI11__URG_LOW__SHIFT
39568. DAGB5_WRCLI11__VIRT_CHAN_MASK
39569. DAGB5_WRCLI11__VIRT_CHAN__SHIFT
39570. DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK
39571. DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT
39572. DAGB5_WRCLI12__MAX_BW_ENABLE_MASK
39573. DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT
39574. DAGB5_WRCLI12__MAX_BW_MASK
39575. DAGB5_WRCLI12__MAX_BW__SHIFT
39576. DAGB5_WRCLI12__MAX_OSD_MASK
39577. DAGB5_WRCLI12__MAX_OSD__SHIFT
39578. DAGB5_WRCLI12__MIN_BW_ENABLE_MASK
39579. DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT
39580. DAGB5_WRCLI12__MIN_BW_MASK
39581. DAGB5_WRCLI12__MIN_BW__SHIFT
39582. DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK
39583. DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
39584. DAGB5_WRCLI12__URG_HIGH_MASK
39585. DAGB5_WRCLI12__URG_HIGH__SHIFT
39586. DAGB5_WRCLI12__URG_LOW_MASK
39587. DAGB5_WRCLI12__URG_LOW__SHIFT
39588. DAGB5_WRCLI12__VIRT_CHAN_MASK
39589. DAGB5_WRCLI12__VIRT_CHAN__SHIFT
39590. DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK
39591. DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT
39592. DAGB5_WRCLI13__MAX_BW_ENABLE_MASK
39593. DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT
39594. DAGB5_WRCLI13__MAX_BW_MASK
39595. DAGB5_WRCLI13__MAX_BW__SHIFT
39596. DAGB5_WRCLI13__MAX_OSD_MASK
39597. DAGB5_WRCLI13__MAX_OSD__SHIFT
39598. DAGB5_WRCLI13__MIN_BW_ENABLE_MASK
39599. DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT
39600. DAGB5_WRCLI13__MIN_BW_MASK
39601. DAGB5_WRCLI13__MIN_BW__SHIFT
39602. DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK
39603. DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
39604. DAGB5_WRCLI13__URG_HIGH_MASK
39605. DAGB5_WRCLI13__URG_HIGH__SHIFT
39606. DAGB5_WRCLI13__URG_LOW_MASK
39607. DAGB5_WRCLI13__URG_LOW__SHIFT
39608. DAGB5_WRCLI13__VIRT_CHAN_MASK
39609. DAGB5_WRCLI13__VIRT_CHAN__SHIFT
39610. DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK
39611. DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT
39612. DAGB5_WRCLI14__MAX_BW_ENABLE_MASK
39613. DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT
39614. DAGB5_WRCLI14__MAX_BW_MASK
39615. DAGB5_WRCLI14__MAX_BW__SHIFT
39616. DAGB5_WRCLI14__MAX_OSD_MASK
39617. DAGB5_WRCLI14__MAX_OSD__SHIFT
39618. DAGB5_WRCLI14__MIN_BW_ENABLE_MASK
39619. DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT
39620. DAGB5_WRCLI14__MIN_BW_MASK
39621. DAGB5_WRCLI14__MIN_BW__SHIFT
39622. DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK
39623. DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
39624. DAGB5_WRCLI14__URG_HIGH_MASK
39625. DAGB5_WRCLI14__URG_HIGH__SHIFT
39626. DAGB5_WRCLI14__URG_LOW_MASK
39627. DAGB5_WRCLI14__URG_LOW__SHIFT
39628. DAGB5_WRCLI14__VIRT_CHAN_MASK
39629. DAGB5_WRCLI14__VIRT_CHAN__SHIFT
39630. DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK
39631. DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT
39632. DAGB5_WRCLI15__MAX_BW_ENABLE_MASK
39633. DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT
39634. DAGB5_WRCLI15__MAX_BW_MASK
39635. DAGB5_WRCLI15__MAX_BW__SHIFT
39636. DAGB5_WRCLI15__MAX_OSD_MASK
39637. DAGB5_WRCLI15__MAX_OSD__SHIFT
39638. DAGB5_WRCLI15__MIN_BW_ENABLE_MASK
39639. DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT
39640. DAGB5_WRCLI15__MIN_BW_MASK
39641. DAGB5_WRCLI15__MIN_BW__SHIFT
39642. DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK
39643. DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
39644. DAGB5_WRCLI15__URG_HIGH_MASK
39645. DAGB5_WRCLI15__URG_HIGH__SHIFT
39646. DAGB5_WRCLI15__URG_LOW_MASK
39647. DAGB5_WRCLI15__URG_LOW__SHIFT
39648. DAGB5_WRCLI15__VIRT_CHAN_MASK
39649. DAGB5_WRCLI15__VIRT_CHAN__SHIFT
39650. DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK
39651. DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT
39652. DAGB5_WRCLI1__MAX_BW_ENABLE_MASK
39653. DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT
39654. DAGB5_WRCLI1__MAX_BW_MASK
39655. DAGB5_WRCLI1__MAX_BW__SHIFT
39656. DAGB5_WRCLI1__MAX_OSD_MASK
39657. DAGB5_WRCLI1__MAX_OSD__SHIFT
39658. DAGB5_WRCLI1__MIN_BW_ENABLE_MASK
39659. DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT
39660. DAGB5_WRCLI1__MIN_BW_MASK
39661. DAGB5_WRCLI1__MIN_BW__SHIFT
39662. DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK
39663. DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
39664. DAGB5_WRCLI1__URG_HIGH_MASK
39665. DAGB5_WRCLI1__URG_HIGH__SHIFT
39666. DAGB5_WRCLI1__URG_LOW_MASK
39667. DAGB5_WRCLI1__URG_LOW__SHIFT
39668. DAGB5_WRCLI1__VIRT_CHAN_MASK
39669. DAGB5_WRCLI1__VIRT_CHAN__SHIFT
39670. DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK
39671. DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT
39672. DAGB5_WRCLI2__MAX_BW_ENABLE_MASK
39673. DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT
39674. DAGB5_WRCLI2__MAX_BW_MASK
39675. DAGB5_WRCLI2__MAX_BW__SHIFT
39676. DAGB5_WRCLI2__MAX_OSD_MASK
39677. DAGB5_WRCLI2__MAX_OSD__SHIFT
39678. DAGB5_WRCLI2__MIN_BW_ENABLE_MASK
39679. DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT
39680. DAGB5_WRCLI2__MIN_BW_MASK
39681. DAGB5_WRCLI2__MIN_BW__SHIFT
39682. DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK
39683. DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
39684. DAGB5_WRCLI2__URG_HIGH_MASK
39685. DAGB5_WRCLI2__URG_HIGH__SHIFT
39686. DAGB5_WRCLI2__URG_LOW_MASK
39687. DAGB5_WRCLI2__URG_LOW__SHIFT
39688. DAGB5_WRCLI2__VIRT_CHAN_MASK
39689. DAGB5_WRCLI2__VIRT_CHAN__SHIFT
39690. DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK
39691. DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT
39692. DAGB5_WRCLI3__MAX_BW_ENABLE_MASK
39693. DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT
39694. DAGB5_WRCLI3__MAX_BW_MASK
39695. DAGB5_WRCLI3__MAX_BW__SHIFT
39696. DAGB5_WRCLI3__MAX_OSD_MASK
39697. DAGB5_WRCLI3__MAX_OSD__SHIFT
39698. DAGB5_WRCLI3__MIN_BW_ENABLE_MASK
39699. DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT
39700. DAGB5_WRCLI3__MIN_BW_MASK
39701. DAGB5_WRCLI3__MIN_BW__SHIFT
39702. DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK
39703. DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
39704. DAGB5_WRCLI3__URG_HIGH_MASK
39705. DAGB5_WRCLI3__URG_HIGH__SHIFT
39706. DAGB5_WRCLI3__URG_LOW_MASK
39707. DAGB5_WRCLI3__URG_LOW__SHIFT
39708. DAGB5_WRCLI3__VIRT_CHAN_MASK
39709. DAGB5_WRCLI3__VIRT_CHAN__SHIFT
39710. DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK
39711. DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT
39712. DAGB5_WRCLI4__MAX_BW_ENABLE_MASK
39713. DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT
39714. DAGB5_WRCLI4__MAX_BW_MASK
39715. DAGB5_WRCLI4__MAX_BW__SHIFT
39716. DAGB5_WRCLI4__MAX_OSD_MASK
39717. DAGB5_WRCLI4__MAX_OSD__SHIFT
39718. DAGB5_WRCLI4__MIN_BW_ENABLE_MASK
39719. DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT
39720. DAGB5_WRCLI4__MIN_BW_MASK
39721. DAGB5_WRCLI4__MIN_BW__SHIFT
39722. DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK
39723. DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
39724. DAGB5_WRCLI4__URG_HIGH_MASK
39725. DAGB5_WRCLI4__URG_HIGH__SHIFT
39726. DAGB5_WRCLI4__URG_LOW_MASK
39727. DAGB5_WRCLI4__URG_LOW__SHIFT
39728. DAGB5_WRCLI4__VIRT_CHAN_MASK
39729. DAGB5_WRCLI4__VIRT_CHAN__SHIFT
39730. DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK
39731. DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT
39732. DAGB5_WRCLI5__MAX_BW_ENABLE_MASK
39733. DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT
39734. DAGB5_WRCLI5__MAX_BW_MASK
39735. DAGB5_WRCLI5__MAX_BW__SHIFT
39736. DAGB5_WRCLI5__MAX_OSD_MASK
39737. DAGB5_WRCLI5__MAX_OSD__SHIFT
39738. DAGB5_WRCLI5__MIN_BW_ENABLE_MASK
39739. DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT
39740. DAGB5_WRCLI5__MIN_BW_MASK
39741. DAGB5_WRCLI5__MIN_BW__SHIFT
39742. DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK
39743. DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
39744. DAGB5_WRCLI5__URG_HIGH_MASK
39745. DAGB5_WRCLI5__URG_HIGH__SHIFT
39746. DAGB5_WRCLI5__URG_LOW_MASK
39747. DAGB5_WRCLI5__URG_LOW__SHIFT
39748. DAGB5_WRCLI5__VIRT_CHAN_MASK
39749. DAGB5_WRCLI5__VIRT_CHAN__SHIFT
39750. DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK
39751. DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT
39752. DAGB5_WRCLI6__MAX_BW_ENABLE_MASK
39753. DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT
39754. DAGB5_WRCLI6__MAX_BW_MASK
39755. DAGB5_WRCLI6__MAX_BW__SHIFT
39756. DAGB5_WRCLI6__MAX_OSD_MASK
39757. DAGB5_WRCLI6__MAX_OSD__SHIFT
39758. DAGB5_WRCLI6__MIN_BW_ENABLE_MASK
39759. DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT
39760. DAGB5_WRCLI6__MIN_BW_MASK
39761. DAGB5_WRCLI6__MIN_BW__SHIFT
39762. DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK
39763. DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
39764. DAGB5_WRCLI6__URG_HIGH_MASK
39765. DAGB5_WRCLI6__URG_HIGH__SHIFT
39766. DAGB5_WRCLI6__URG_LOW_MASK
39767. DAGB5_WRCLI6__URG_LOW__SHIFT
39768. DAGB5_WRCLI6__VIRT_CHAN_MASK
39769. DAGB5_WRCLI6__VIRT_CHAN__SHIFT
39770. DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK
39771. DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT
39772. DAGB5_WRCLI7__MAX_BW_ENABLE_MASK
39773. DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT
39774. DAGB5_WRCLI7__MAX_BW_MASK
39775. DAGB5_WRCLI7__MAX_BW__SHIFT
39776. DAGB5_WRCLI7__MAX_OSD_MASK
39777. DAGB5_WRCLI7__MAX_OSD__SHIFT
39778. DAGB5_WRCLI7__MIN_BW_ENABLE_MASK
39779. DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT
39780. DAGB5_WRCLI7__MIN_BW_MASK
39781. DAGB5_WRCLI7__MIN_BW__SHIFT
39782. DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK
39783. DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
39784. DAGB5_WRCLI7__URG_HIGH_MASK
39785. DAGB5_WRCLI7__URG_HIGH__SHIFT
39786. DAGB5_WRCLI7__URG_LOW_MASK
39787. DAGB5_WRCLI7__URG_LOW__SHIFT
39788. DAGB5_WRCLI7__VIRT_CHAN_MASK
39789. DAGB5_WRCLI7__VIRT_CHAN__SHIFT
39790. DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK
39791. DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT
39792. DAGB5_WRCLI8__MAX_BW_ENABLE_MASK
39793. DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT
39794. DAGB5_WRCLI8__MAX_BW_MASK
39795. DAGB5_WRCLI8__MAX_BW__SHIFT
39796. DAGB5_WRCLI8__MAX_OSD_MASK
39797. DAGB5_WRCLI8__MAX_OSD__SHIFT
39798. DAGB5_WRCLI8__MIN_BW_ENABLE_MASK
39799. DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT
39800. DAGB5_WRCLI8__MIN_BW_MASK
39801. DAGB5_WRCLI8__MIN_BW__SHIFT
39802. DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK
39803. DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
39804. DAGB5_WRCLI8__URG_HIGH_MASK
39805. DAGB5_WRCLI8__URG_HIGH__SHIFT
39806. DAGB5_WRCLI8__URG_LOW_MASK
39807. DAGB5_WRCLI8__URG_LOW__SHIFT
39808. DAGB5_WRCLI8__VIRT_CHAN_MASK
39809. DAGB5_WRCLI8__VIRT_CHAN__SHIFT
39810. DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK
39811. DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT
39812. DAGB5_WRCLI9__MAX_BW_ENABLE_MASK
39813. DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT
39814. DAGB5_WRCLI9__MAX_BW_MASK
39815. DAGB5_WRCLI9__MAX_BW__SHIFT
39816. DAGB5_WRCLI9__MAX_OSD_MASK
39817. DAGB5_WRCLI9__MAX_OSD__SHIFT
39818. DAGB5_WRCLI9__MIN_BW_ENABLE_MASK
39819. DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT
39820. DAGB5_WRCLI9__MIN_BW_MASK
39821. DAGB5_WRCLI9__MIN_BW__SHIFT
39822. DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK
39823. DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
39824. DAGB5_WRCLI9__URG_HIGH_MASK
39825. DAGB5_WRCLI9__URG_HIGH__SHIFT
39826. DAGB5_WRCLI9__URG_LOW_MASK
39827. DAGB5_WRCLI9__URG_LOW__SHIFT
39828. DAGB5_WRCLI9__VIRT_CHAN_MASK
39829. DAGB5_WRCLI9__VIRT_CHAN__SHIFT
39830. DAGB5_WRCLI_ASK_PENDING__BUSY_MASK
39831. DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT
39832. DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
39833. DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
39834. DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK
39835. DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
39836. DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK
39837. DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
39838. DAGB5_WRCLI_GO_PENDING__BUSY_MASK
39839. DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT
39840. DAGB5_WRCLI_OARB_PENDING__BUSY_MASK
39841. DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT
39842. DAGB5_WRCLI_OSD_PENDING__BUSY_MASK
39843. DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT
39844. DAGB5_WRCLI_TLB_PENDING__BUSY_MASK
39845. DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT
39846. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
39847. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
39848. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
39849. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
39850. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
39851. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
39852. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
39853. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
39854. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
39855. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
39856. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
39857. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
39858. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
39859. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
39860. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
39861. DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
39862. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
39863. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
39864. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
39865. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
39866. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
39867. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
39868. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
39869. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
39870. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
39871. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
39872. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
39873. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
39874. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
39875. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
39876. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
39877. DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
39878. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
39879. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
39880. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
39881. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
39882. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
39883. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
39884. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
39885. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
39886. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
39887. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
39888. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
39889. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
39890. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
39891. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
39892. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
39893. DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
39894. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
39895. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
39896. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
39897. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
39898. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
39899. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
39900. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
39901. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
39902. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
39903. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
39904. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
39905. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
39906. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
39907. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
39908. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
39909. DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
39910. DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK
39911. DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
39912. DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
39913. DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
39914. DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
39915. DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
39916. DAGB5_WR_ADDR_DAGB__WHOAMI_MASK
39917. DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT
39918. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
39919. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
39920. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
39921. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
39922. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
39923. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
39924. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
39925. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
39926. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
39927. DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
39928. DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
39929. DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
39930. DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
39931. DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
39932. DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
39933. DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
39934. DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
39935. DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
39936. DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
39937. DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
39938. DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK
39939. DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
39940. DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
39941. DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
39942. DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
39943. DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
39944. DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
39945. DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
39946. DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK
39947. DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT
39948. DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
39949. DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
39950. DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
39951. DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
39952. DAGB5_WR_CNTL__IO_LEVEL_MASK
39953. DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
39954. DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
39955. DAGB5_WR_CNTL__IO_LEVEL__SHIFT
39956. DAGB5_WR_CNTL__SCLK_FREQ_MASK
39957. DAGB5_WR_CNTL__SCLK_FREQ__SHIFT
39958. DAGB5_WR_CNTL__SHARE_VC_NUM_MASK
39959. DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT
39960. DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK
39961. DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
39962. DAGB5_WR_CREDITS_FULL__FULL_MASK
39963. DAGB5_WR_CREDITS_FULL__FULL__SHIFT
39964. DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
39965. DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
39966. DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
39967. DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
39968. DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
39969. DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
39970. DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
39971. DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
39972. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
39973. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
39974. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
39975. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
39976. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
39977. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
39978. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
39979. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
39980. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
39981. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
39982. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
39983. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
39984. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
39985. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
39986. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
39987. DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
39988. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
39989. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
39990. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
39991. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
39992. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
39993. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
39994. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
39995. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
39996. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
39997. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
39998. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
39999. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
40000. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
40001. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
40002. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
40003. DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
40004. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
40005. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
40006. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
40007. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
40008. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
40009. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
40010. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
40011. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
40012. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
40013. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
40014. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
40015. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
40016. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
40017. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
40018. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
40019. DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
40020. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
40021. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
40022. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
40023. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
40024. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
40025. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
40026. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
40027. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
40028. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
40029. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
40030. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
40031. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
40032. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
40033. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
40034. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
40035. DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
40036. DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK
40037. DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
40038. DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
40039. DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
40040. DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
40041. DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
40042. DAGB5_WR_DATA_DAGB__WHOAMI_MASK
40043. DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT
40044. DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK
40045. DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT
40046. DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK
40047. DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT
40048. DAGB5_WR_GMI_CNTL__LEVEL_MASK
40049. DAGB5_WR_GMI_CNTL__LEVEL__SHIFT
40050. DAGB5_WR_GMI_CNTL__MAX_BURST_MASK
40051. DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT
40052. DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
40053. DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
40054. DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
40055. DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
40056. DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK
40057. DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
40058. DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
40059. DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
40060. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
40061. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
40062. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
40063. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
40064. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
40065. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
40066. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
40067. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
40068. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
40069. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
40070. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
40071. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
40072. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
40073. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
40074. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
40075. DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
40076. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
40077. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
40078. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
40079. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
40080. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
40081. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
40082. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
40083. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
40084. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
40085. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
40086. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
40087. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
40088. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
40089. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
40090. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
40091. DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
40092. DAGB5_WR_TLB_CREDIT__TLB0_MASK
40093. DAGB5_WR_TLB_CREDIT__TLB0__SHIFT
40094. DAGB5_WR_TLB_CREDIT__TLB1_MASK
40095. DAGB5_WR_TLB_CREDIT__TLB1__SHIFT
40096. DAGB5_WR_TLB_CREDIT__TLB2_MASK
40097. DAGB5_WR_TLB_CREDIT__TLB2__SHIFT
40098. DAGB5_WR_TLB_CREDIT__TLB3_MASK
40099. DAGB5_WR_TLB_CREDIT__TLB3__SHIFT
40100. DAGB5_WR_TLB_CREDIT__TLB4_MASK
40101. DAGB5_WR_TLB_CREDIT__TLB4__SHIFT
40102. DAGB5_WR_TLB_CREDIT__TLB5_MASK
40103. DAGB5_WR_TLB_CREDIT__TLB5__SHIFT
40104. DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK
40105. DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT
40106. DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
40107. DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
40108. DAGB5_WR_VC0_CNTL__MAX_BW_MASK
40109. DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT
40110. DAGB5_WR_VC0_CNTL__MAX_OSD_MASK
40111. DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT
40112. DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
40113. DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
40114. DAGB5_WR_VC0_CNTL__MIN_BW_MASK
40115. DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT
40116. DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
40117. DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
40118. DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK
40119. DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT
40120. DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK
40121. DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT
40122. DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
40123. DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
40124. DAGB5_WR_VC1_CNTL__MAX_BW_MASK
40125. DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT
40126. DAGB5_WR_VC1_CNTL__MAX_OSD_MASK
40127. DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT
40128. DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
40129. DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
40130. DAGB5_WR_VC1_CNTL__MIN_BW_MASK
40131. DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT
40132. DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
40133. DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
40134. DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK
40135. DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT
40136. DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK
40137. DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT
40138. DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
40139. DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
40140. DAGB5_WR_VC2_CNTL__MAX_BW_MASK
40141. DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT
40142. DAGB5_WR_VC2_CNTL__MAX_OSD_MASK
40143. DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT
40144. DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
40145. DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
40146. DAGB5_WR_VC2_CNTL__MIN_BW_MASK
40147. DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT
40148. DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
40149. DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
40150. DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK
40151. DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT
40152. DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK
40153. DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT
40154. DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
40155. DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
40156. DAGB5_WR_VC3_CNTL__MAX_BW_MASK
40157. DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT
40158. DAGB5_WR_VC3_CNTL__MAX_OSD_MASK
40159. DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT
40160. DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
40161. DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
40162. DAGB5_WR_VC3_CNTL__MIN_BW_MASK
40163. DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT
40164. DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
40165. DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
40166. DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK
40167. DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT
40168. DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK
40169. DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT
40170. DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
40171. DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
40172. DAGB5_WR_VC4_CNTL__MAX_BW_MASK
40173. DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT
40174. DAGB5_WR_VC4_CNTL__MAX_OSD_MASK
40175. DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT
40176. DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
40177. DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
40178. DAGB5_WR_VC4_CNTL__MIN_BW_MASK
40179. DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT
40180. DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
40181. DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
40182. DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK
40183. DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT
40184. DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK
40185. DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT
40186. DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
40187. DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
40188. DAGB5_WR_VC5_CNTL__MAX_BW_MASK
40189. DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT
40190. DAGB5_WR_VC5_CNTL__MAX_OSD_MASK
40191. DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT
40192. DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
40193. DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
40194. DAGB5_WR_VC5_CNTL__MIN_BW_MASK
40195. DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT
40196. DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
40197. DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
40198. DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK
40199. DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT
40200. DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK
40201. DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT
40202. DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
40203. DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
40204. DAGB5_WR_VC6_CNTL__MAX_BW_MASK
40205. DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT
40206. DAGB5_WR_VC6_CNTL__MAX_OSD_MASK
40207. DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT
40208. DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
40209. DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
40210. DAGB5_WR_VC6_CNTL__MIN_BW_MASK
40211. DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT
40212. DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
40213. DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
40214. DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK
40215. DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT
40216. DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK
40217. DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT
40218. DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
40219. DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
40220. DAGB5_WR_VC7_CNTL__MAX_BW_MASK
40221. DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT
40222. DAGB5_WR_VC7_CNTL__MAX_OSD_MASK
40223. DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT
40224. DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
40225. DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
40226. DAGB5_WR_VC7_CNTL__MIN_BW_MASK
40227. DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT
40228. DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
40229. DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
40230. DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK
40231. DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT
40232. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
40233. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
40234. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
40235. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
40236. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
40237. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
40238. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
40239. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
40240. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
40241. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
40242. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
40243. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
40244. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
40245. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
40246. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
40247. DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
40248. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
40249. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
40250. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
40251. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
40252. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
40253. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
40254. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
40255. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
40256. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
40257. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
40258. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
40259. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
40260. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
40261. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
40262. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
40263. DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
40264. DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
40265. DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
40266. DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
40267. DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
40268. DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
40269. DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
40270. DAGB6_CNTL_MISC2__DISABLE_RDRET_CG_MASK
40271. DAGB6_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
40272. DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
40273. DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
40274. DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
40275. DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
40276. DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
40277. DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
40278. DAGB6_CNTL_MISC2__DISABLE_WRRET_CG_MASK
40279. DAGB6_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
40280. DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
40281. DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
40282. DAGB6_CNTL_MISC2__RDRET_FIFO_PERF_MASK
40283. DAGB6_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
40284. DAGB6_CNTL_MISC2__SWAP_CTL_MASK
40285. DAGB6_CNTL_MISC2__SWAP_CTL__SHIFT
40286. DAGB6_CNTL_MISC2__URG_BOOST_ENABLE_MASK
40287. DAGB6_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
40288. DAGB6_CNTL_MISC2__URG_HALT_ENABLE_MASK
40289. DAGB6_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
40290. DAGB6_CNTL_MISC__BW_INIT_CYCLE_MASK
40291. DAGB6_CNTL_MISC__BW_INIT_CYCLE__SHIFT
40292. DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
40293. DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
40294. DAGB6_CNTL_MISC__EA_VC0_REMAP_MASK
40295. DAGB6_CNTL_MISC__EA_VC0_REMAP__SHIFT
40296. DAGB6_CNTL_MISC__EA_VC1_REMAP_MASK
40297. DAGB6_CNTL_MISC__EA_VC1_REMAP__SHIFT
40298. DAGB6_CNTL_MISC__EA_VC2_REMAP_MASK
40299. DAGB6_CNTL_MISC__EA_VC2_REMAP__SHIFT
40300. DAGB6_CNTL_MISC__EA_VC3_REMAP_MASK
40301. DAGB6_CNTL_MISC__EA_VC3_REMAP__SHIFT
40302. DAGB6_CNTL_MISC__EA_VC4_REMAP_MASK
40303. DAGB6_CNTL_MISC__EA_VC4_REMAP__SHIFT
40304. DAGB6_CNTL_MISC__EA_VC5_REMAP_MASK
40305. DAGB6_CNTL_MISC__EA_VC5_REMAP__SHIFT
40306. DAGB6_CNTL_MISC__EA_VC6_REMAP_MASK
40307. DAGB6_CNTL_MISC__EA_VC6_REMAP__SHIFT
40308. DAGB6_CNTL_MISC__EA_VC7_REMAP_MASK
40309. DAGB6_CNTL_MISC__EA_VC7_REMAP__SHIFT
40310. DAGB6_DAGB_DLY__CLI_MASK
40311. DAGB6_DAGB_DLY__CLI__SHIFT
40312. DAGB6_DAGB_DLY__DLY_MASK
40313. DAGB6_DAGB_DLY__DLY__SHIFT
40314. DAGB6_DAGB_DLY__POS_MASK
40315. DAGB6_DAGB_DLY__POS__SHIFT
40316. DAGB6_FIFO_EMPTY__EMPTY_MASK
40317. DAGB6_FIFO_EMPTY__EMPTY__SHIFT
40318. DAGB6_FIFO_FULL__FULL_MASK
40319. DAGB6_FIFO_FULL__FULL__SHIFT
40320. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
40321. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
40322. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
40323. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
40324. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
40325. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
40326. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
40327. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
40328. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
40329. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
40330. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
40331. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
40332. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
40333. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
40334. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
40335. DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
40336. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
40337. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
40338. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
40339. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
40340. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
40341. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
40342. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
40343. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
40344. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
40345. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
40346. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
40347. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
40348. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
40349. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
40350. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
40351. DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
40352. DAGB6_PERFCOUNTER0_CFG__CLEAR_MASK
40353. DAGB6_PERFCOUNTER0_CFG__CLEAR__SHIFT
40354. DAGB6_PERFCOUNTER0_CFG__ENABLE_MASK
40355. DAGB6_PERFCOUNTER0_CFG__ENABLE__SHIFT
40356. DAGB6_PERFCOUNTER0_CFG__PERF_MODE_MASK
40357. DAGB6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
40358. DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
40359. DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
40360. DAGB6_PERFCOUNTER0_CFG__PERF_SEL_MASK
40361. DAGB6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
40362. DAGB6_PERFCOUNTER1_CFG__CLEAR_MASK
40363. DAGB6_PERFCOUNTER1_CFG__CLEAR__SHIFT
40364. DAGB6_PERFCOUNTER1_CFG__ENABLE_MASK
40365. DAGB6_PERFCOUNTER1_CFG__ENABLE__SHIFT
40366. DAGB6_PERFCOUNTER1_CFG__PERF_MODE_MASK
40367. DAGB6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
40368. DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
40369. DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
40370. DAGB6_PERFCOUNTER1_CFG__PERF_SEL_MASK
40371. DAGB6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
40372. DAGB6_PERFCOUNTER2_CFG__CLEAR_MASK
40373. DAGB6_PERFCOUNTER2_CFG__CLEAR__SHIFT
40374. DAGB6_PERFCOUNTER2_CFG__ENABLE_MASK
40375. DAGB6_PERFCOUNTER2_CFG__ENABLE__SHIFT
40376. DAGB6_PERFCOUNTER2_CFG__PERF_MODE_MASK
40377. DAGB6_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
40378. DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
40379. DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
40380. DAGB6_PERFCOUNTER2_CFG__PERF_SEL_MASK
40381. DAGB6_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
40382. DAGB6_PERFCOUNTER_HI__COMPARE_VALUE_MASK
40383. DAGB6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
40384. DAGB6_PERFCOUNTER_HI__COUNTER_HI_MASK
40385. DAGB6_PERFCOUNTER_HI__COUNTER_HI__SHIFT
40386. DAGB6_PERFCOUNTER_LO__COUNTER_LO_MASK
40387. DAGB6_PERFCOUNTER_LO__COUNTER_LO__SHIFT
40388. DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
40389. DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
40390. DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
40391. DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
40392. DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
40393. DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
40394. DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
40395. DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
40396. DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
40397. DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
40398. DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
40399. DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
40400. DAGB6_RDCLI0__CHECK_TLB_CREDIT_MASK
40401. DAGB6_RDCLI0__CHECK_TLB_CREDIT__SHIFT
40402. DAGB6_RDCLI0__MAX_BW_ENABLE_MASK
40403. DAGB6_RDCLI0__MAX_BW_ENABLE__SHIFT
40404. DAGB6_RDCLI0__MAX_BW_MASK
40405. DAGB6_RDCLI0__MAX_BW__SHIFT
40406. DAGB6_RDCLI0__MAX_OSD_MASK
40407. DAGB6_RDCLI0__MAX_OSD__SHIFT
40408. DAGB6_RDCLI0__MIN_BW_ENABLE_MASK
40409. DAGB6_RDCLI0__MIN_BW_ENABLE__SHIFT
40410. DAGB6_RDCLI0__MIN_BW_MASK
40411. DAGB6_RDCLI0__MIN_BW__SHIFT
40412. DAGB6_RDCLI0__OSD_LIMITER_ENABLE_MASK
40413. DAGB6_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
40414. DAGB6_RDCLI0__URG_HIGH_MASK
40415. DAGB6_RDCLI0__URG_HIGH__SHIFT
40416. DAGB6_RDCLI0__URG_LOW_MASK
40417. DAGB6_RDCLI0__URG_LOW__SHIFT
40418. DAGB6_RDCLI0__VIRT_CHAN_MASK
40419. DAGB6_RDCLI0__VIRT_CHAN__SHIFT
40420. DAGB6_RDCLI10__CHECK_TLB_CREDIT_MASK
40421. DAGB6_RDCLI10__CHECK_TLB_CREDIT__SHIFT
40422. DAGB6_RDCLI10__MAX_BW_ENABLE_MASK
40423. DAGB6_RDCLI10__MAX_BW_ENABLE__SHIFT
40424. DAGB6_RDCLI10__MAX_BW_MASK
40425. DAGB6_RDCLI10__MAX_BW__SHIFT
40426. DAGB6_RDCLI10__MAX_OSD_MASK
40427. DAGB6_RDCLI10__MAX_OSD__SHIFT
40428. DAGB6_RDCLI10__MIN_BW_ENABLE_MASK
40429. DAGB6_RDCLI10__MIN_BW_ENABLE__SHIFT
40430. DAGB6_RDCLI10__MIN_BW_MASK
40431. DAGB6_RDCLI10__MIN_BW__SHIFT
40432. DAGB6_RDCLI10__OSD_LIMITER_ENABLE_MASK
40433. DAGB6_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
40434. DAGB6_RDCLI10__URG_HIGH_MASK
40435. DAGB6_RDCLI10__URG_HIGH__SHIFT
40436. DAGB6_RDCLI10__URG_LOW_MASK
40437. DAGB6_RDCLI10__URG_LOW__SHIFT
40438. DAGB6_RDCLI10__VIRT_CHAN_MASK
40439. DAGB6_RDCLI10__VIRT_CHAN__SHIFT
40440. DAGB6_RDCLI11__CHECK_TLB_CREDIT_MASK
40441. DAGB6_RDCLI11__CHECK_TLB_CREDIT__SHIFT
40442. DAGB6_RDCLI11__MAX_BW_ENABLE_MASK
40443. DAGB6_RDCLI11__MAX_BW_ENABLE__SHIFT
40444. DAGB6_RDCLI11__MAX_BW_MASK
40445. DAGB6_RDCLI11__MAX_BW__SHIFT
40446. DAGB6_RDCLI11__MAX_OSD_MASK
40447. DAGB6_RDCLI11__MAX_OSD__SHIFT
40448. DAGB6_RDCLI11__MIN_BW_ENABLE_MASK
40449. DAGB6_RDCLI11__MIN_BW_ENABLE__SHIFT
40450. DAGB6_RDCLI11__MIN_BW_MASK
40451. DAGB6_RDCLI11__MIN_BW__SHIFT
40452. DAGB6_RDCLI11__OSD_LIMITER_ENABLE_MASK
40453. DAGB6_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
40454. DAGB6_RDCLI11__URG_HIGH_MASK
40455. DAGB6_RDCLI11__URG_HIGH__SHIFT
40456. DAGB6_RDCLI11__URG_LOW_MASK
40457. DAGB6_RDCLI11__URG_LOW__SHIFT
40458. DAGB6_RDCLI11__VIRT_CHAN_MASK
40459. DAGB6_RDCLI11__VIRT_CHAN__SHIFT
40460. DAGB6_RDCLI12__CHECK_TLB_CREDIT_MASK
40461. DAGB6_RDCLI12__CHECK_TLB_CREDIT__SHIFT
40462. DAGB6_RDCLI12__MAX_BW_ENABLE_MASK
40463. DAGB6_RDCLI12__MAX_BW_ENABLE__SHIFT
40464. DAGB6_RDCLI12__MAX_BW_MASK
40465. DAGB6_RDCLI12__MAX_BW__SHIFT
40466. DAGB6_RDCLI12__MAX_OSD_MASK
40467. DAGB6_RDCLI12__MAX_OSD__SHIFT
40468. DAGB6_RDCLI12__MIN_BW_ENABLE_MASK
40469. DAGB6_RDCLI12__MIN_BW_ENABLE__SHIFT
40470. DAGB6_RDCLI12__MIN_BW_MASK
40471. DAGB6_RDCLI12__MIN_BW__SHIFT
40472. DAGB6_RDCLI12__OSD_LIMITER_ENABLE_MASK
40473. DAGB6_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
40474. DAGB6_RDCLI12__URG_HIGH_MASK
40475. DAGB6_RDCLI12__URG_HIGH__SHIFT
40476. DAGB6_RDCLI12__URG_LOW_MASK
40477. DAGB6_RDCLI12__URG_LOW__SHIFT
40478. DAGB6_RDCLI12__VIRT_CHAN_MASK
40479. DAGB6_RDCLI12__VIRT_CHAN__SHIFT
40480. DAGB6_RDCLI13__CHECK_TLB_CREDIT_MASK
40481. DAGB6_RDCLI13__CHECK_TLB_CREDIT__SHIFT
40482. DAGB6_RDCLI13__MAX_BW_ENABLE_MASK
40483. DAGB6_RDCLI13__MAX_BW_ENABLE__SHIFT
40484. DAGB6_RDCLI13__MAX_BW_MASK
40485. DAGB6_RDCLI13__MAX_BW__SHIFT
40486. DAGB6_RDCLI13__MAX_OSD_MASK
40487. DAGB6_RDCLI13__MAX_OSD__SHIFT
40488. DAGB6_RDCLI13__MIN_BW_ENABLE_MASK
40489. DAGB6_RDCLI13__MIN_BW_ENABLE__SHIFT
40490. DAGB6_RDCLI13__MIN_BW_MASK
40491. DAGB6_RDCLI13__MIN_BW__SHIFT
40492. DAGB6_RDCLI13__OSD_LIMITER_ENABLE_MASK
40493. DAGB6_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
40494. DAGB6_RDCLI13__URG_HIGH_MASK
40495. DAGB6_RDCLI13__URG_HIGH__SHIFT
40496. DAGB6_RDCLI13__URG_LOW_MASK
40497. DAGB6_RDCLI13__URG_LOW__SHIFT
40498. DAGB6_RDCLI13__VIRT_CHAN_MASK
40499. DAGB6_RDCLI13__VIRT_CHAN__SHIFT
40500. DAGB6_RDCLI14__CHECK_TLB_CREDIT_MASK
40501. DAGB6_RDCLI14__CHECK_TLB_CREDIT__SHIFT
40502. DAGB6_RDCLI14__MAX_BW_ENABLE_MASK
40503. DAGB6_RDCLI14__MAX_BW_ENABLE__SHIFT
40504. DAGB6_RDCLI14__MAX_BW_MASK
40505. DAGB6_RDCLI14__MAX_BW__SHIFT
40506. DAGB6_RDCLI14__MAX_OSD_MASK
40507. DAGB6_RDCLI14__MAX_OSD__SHIFT
40508. DAGB6_RDCLI14__MIN_BW_ENABLE_MASK
40509. DAGB6_RDCLI14__MIN_BW_ENABLE__SHIFT
40510. DAGB6_RDCLI14__MIN_BW_MASK
40511. DAGB6_RDCLI14__MIN_BW__SHIFT
40512. DAGB6_RDCLI14__OSD_LIMITER_ENABLE_MASK
40513. DAGB6_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
40514. DAGB6_RDCLI14__URG_HIGH_MASK
40515. DAGB6_RDCLI14__URG_HIGH__SHIFT
40516. DAGB6_RDCLI14__URG_LOW_MASK
40517. DAGB6_RDCLI14__URG_LOW__SHIFT
40518. DAGB6_RDCLI14__VIRT_CHAN_MASK
40519. DAGB6_RDCLI14__VIRT_CHAN__SHIFT
40520. DAGB6_RDCLI15__CHECK_TLB_CREDIT_MASK
40521. DAGB6_RDCLI15__CHECK_TLB_CREDIT__SHIFT
40522. DAGB6_RDCLI15__MAX_BW_ENABLE_MASK
40523. DAGB6_RDCLI15__MAX_BW_ENABLE__SHIFT
40524. DAGB6_RDCLI15__MAX_BW_MASK
40525. DAGB6_RDCLI15__MAX_BW__SHIFT
40526. DAGB6_RDCLI15__MAX_OSD_MASK
40527. DAGB6_RDCLI15__MAX_OSD__SHIFT
40528. DAGB6_RDCLI15__MIN_BW_ENABLE_MASK
40529. DAGB6_RDCLI15__MIN_BW_ENABLE__SHIFT
40530. DAGB6_RDCLI15__MIN_BW_MASK
40531. DAGB6_RDCLI15__MIN_BW__SHIFT
40532. DAGB6_RDCLI15__OSD_LIMITER_ENABLE_MASK
40533. DAGB6_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
40534. DAGB6_RDCLI15__URG_HIGH_MASK
40535. DAGB6_RDCLI15__URG_HIGH__SHIFT
40536. DAGB6_RDCLI15__URG_LOW_MASK
40537. DAGB6_RDCLI15__URG_LOW__SHIFT
40538. DAGB6_RDCLI15__VIRT_CHAN_MASK
40539. DAGB6_RDCLI15__VIRT_CHAN__SHIFT
40540. DAGB6_RDCLI1__CHECK_TLB_CREDIT_MASK
40541. DAGB6_RDCLI1__CHECK_TLB_CREDIT__SHIFT
40542. DAGB6_RDCLI1__MAX_BW_ENABLE_MASK
40543. DAGB6_RDCLI1__MAX_BW_ENABLE__SHIFT
40544. DAGB6_RDCLI1__MAX_BW_MASK
40545. DAGB6_RDCLI1__MAX_BW__SHIFT
40546. DAGB6_RDCLI1__MAX_OSD_MASK
40547. DAGB6_RDCLI1__MAX_OSD__SHIFT
40548. DAGB6_RDCLI1__MIN_BW_ENABLE_MASK
40549. DAGB6_RDCLI1__MIN_BW_ENABLE__SHIFT
40550. DAGB6_RDCLI1__MIN_BW_MASK
40551. DAGB6_RDCLI1__MIN_BW__SHIFT
40552. DAGB6_RDCLI1__OSD_LIMITER_ENABLE_MASK
40553. DAGB6_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
40554. DAGB6_RDCLI1__URG_HIGH_MASK
40555. DAGB6_RDCLI1__URG_HIGH__SHIFT
40556. DAGB6_RDCLI1__URG_LOW_MASK
40557. DAGB6_RDCLI1__URG_LOW__SHIFT
40558. DAGB6_RDCLI1__VIRT_CHAN_MASK
40559. DAGB6_RDCLI1__VIRT_CHAN__SHIFT
40560. DAGB6_RDCLI2__CHECK_TLB_CREDIT_MASK
40561. DAGB6_RDCLI2__CHECK_TLB_CREDIT__SHIFT
40562. DAGB6_RDCLI2__MAX_BW_ENABLE_MASK
40563. DAGB6_RDCLI2__MAX_BW_ENABLE__SHIFT
40564. DAGB6_RDCLI2__MAX_BW_MASK
40565. DAGB6_RDCLI2__MAX_BW__SHIFT
40566. DAGB6_RDCLI2__MAX_OSD_MASK
40567. DAGB6_RDCLI2__MAX_OSD__SHIFT
40568. DAGB6_RDCLI2__MIN_BW_ENABLE_MASK
40569. DAGB6_RDCLI2__MIN_BW_ENABLE__SHIFT
40570. DAGB6_RDCLI2__MIN_BW_MASK
40571. DAGB6_RDCLI2__MIN_BW__SHIFT
40572. DAGB6_RDCLI2__OSD_LIMITER_ENABLE_MASK
40573. DAGB6_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
40574. DAGB6_RDCLI2__URG_HIGH_MASK
40575. DAGB6_RDCLI2__URG_HIGH__SHIFT
40576. DAGB6_RDCLI2__URG_LOW_MASK
40577. DAGB6_RDCLI2__URG_LOW__SHIFT
40578. DAGB6_RDCLI2__VIRT_CHAN_MASK
40579. DAGB6_RDCLI2__VIRT_CHAN__SHIFT
40580. DAGB6_RDCLI3__CHECK_TLB_CREDIT_MASK
40581. DAGB6_RDCLI3__CHECK_TLB_CREDIT__SHIFT
40582. DAGB6_RDCLI3__MAX_BW_ENABLE_MASK
40583. DAGB6_RDCLI3__MAX_BW_ENABLE__SHIFT
40584. DAGB6_RDCLI3__MAX_BW_MASK
40585. DAGB6_RDCLI3__MAX_BW__SHIFT
40586. DAGB6_RDCLI3__MAX_OSD_MASK
40587. DAGB6_RDCLI3__MAX_OSD__SHIFT
40588. DAGB6_RDCLI3__MIN_BW_ENABLE_MASK
40589. DAGB6_RDCLI3__MIN_BW_ENABLE__SHIFT
40590. DAGB6_RDCLI3__MIN_BW_MASK
40591. DAGB6_RDCLI3__MIN_BW__SHIFT
40592. DAGB6_RDCLI3__OSD_LIMITER_ENABLE_MASK
40593. DAGB6_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
40594. DAGB6_RDCLI3__URG_HIGH_MASK
40595. DAGB6_RDCLI3__URG_HIGH__SHIFT
40596. DAGB6_RDCLI3__URG_LOW_MASK
40597. DAGB6_RDCLI3__URG_LOW__SHIFT
40598. DAGB6_RDCLI3__VIRT_CHAN_MASK
40599. DAGB6_RDCLI3__VIRT_CHAN__SHIFT
40600. DAGB6_RDCLI4__CHECK_TLB_CREDIT_MASK
40601. DAGB6_RDCLI4__CHECK_TLB_CREDIT__SHIFT
40602. DAGB6_RDCLI4__MAX_BW_ENABLE_MASK
40603. DAGB6_RDCLI4__MAX_BW_ENABLE__SHIFT
40604. DAGB6_RDCLI4__MAX_BW_MASK
40605. DAGB6_RDCLI4__MAX_BW__SHIFT
40606. DAGB6_RDCLI4__MAX_OSD_MASK
40607. DAGB6_RDCLI4__MAX_OSD__SHIFT
40608. DAGB6_RDCLI4__MIN_BW_ENABLE_MASK
40609. DAGB6_RDCLI4__MIN_BW_ENABLE__SHIFT
40610. DAGB6_RDCLI4__MIN_BW_MASK
40611. DAGB6_RDCLI4__MIN_BW__SHIFT
40612. DAGB6_RDCLI4__OSD_LIMITER_ENABLE_MASK
40613. DAGB6_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
40614. DAGB6_RDCLI4__URG_HIGH_MASK
40615. DAGB6_RDCLI4__URG_HIGH__SHIFT
40616. DAGB6_RDCLI4__URG_LOW_MASK
40617. DAGB6_RDCLI4__URG_LOW__SHIFT
40618. DAGB6_RDCLI4__VIRT_CHAN_MASK
40619. DAGB6_RDCLI4__VIRT_CHAN__SHIFT
40620. DAGB6_RDCLI5__CHECK_TLB_CREDIT_MASK
40621. DAGB6_RDCLI5__CHECK_TLB_CREDIT__SHIFT
40622. DAGB6_RDCLI5__MAX_BW_ENABLE_MASK
40623. DAGB6_RDCLI5__MAX_BW_ENABLE__SHIFT
40624. DAGB6_RDCLI5__MAX_BW_MASK
40625. DAGB6_RDCLI5__MAX_BW__SHIFT
40626. DAGB6_RDCLI5__MAX_OSD_MASK
40627. DAGB6_RDCLI5__MAX_OSD__SHIFT
40628. DAGB6_RDCLI5__MIN_BW_ENABLE_MASK
40629. DAGB6_RDCLI5__MIN_BW_ENABLE__SHIFT
40630. DAGB6_RDCLI5__MIN_BW_MASK
40631. DAGB6_RDCLI5__MIN_BW__SHIFT
40632. DAGB6_RDCLI5__OSD_LIMITER_ENABLE_MASK
40633. DAGB6_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
40634. DAGB6_RDCLI5__URG_HIGH_MASK
40635. DAGB6_RDCLI5__URG_HIGH__SHIFT
40636. DAGB6_RDCLI5__URG_LOW_MASK
40637. DAGB6_RDCLI5__URG_LOW__SHIFT
40638. DAGB6_RDCLI5__VIRT_CHAN_MASK
40639. DAGB6_RDCLI5__VIRT_CHAN__SHIFT
40640. DAGB6_RDCLI6__CHECK_TLB_CREDIT_MASK
40641. DAGB6_RDCLI6__CHECK_TLB_CREDIT__SHIFT
40642. DAGB6_RDCLI6__MAX_BW_ENABLE_MASK
40643. DAGB6_RDCLI6__MAX_BW_ENABLE__SHIFT
40644. DAGB6_RDCLI6__MAX_BW_MASK
40645. DAGB6_RDCLI6__MAX_BW__SHIFT
40646. DAGB6_RDCLI6__MAX_OSD_MASK
40647. DAGB6_RDCLI6__MAX_OSD__SHIFT
40648. DAGB6_RDCLI6__MIN_BW_ENABLE_MASK
40649. DAGB6_RDCLI6__MIN_BW_ENABLE__SHIFT
40650. DAGB6_RDCLI6__MIN_BW_MASK
40651. DAGB6_RDCLI6__MIN_BW__SHIFT
40652. DAGB6_RDCLI6__OSD_LIMITER_ENABLE_MASK
40653. DAGB6_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
40654. DAGB6_RDCLI6__URG_HIGH_MASK
40655. DAGB6_RDCLI6__URG_HIGH__SHIFT
40656. DAGB6_RDCLI6__URG_LOW_MASK
40657. DAGB6_RDCLI6__URG_LOW__SHIFT
40658. DAGB6_RDCLI6__VIRT_CHAN_MASK
40659. DAGB6_RDCLI6__VIRT_CHAN__SHIFT
40660. DAGB6_RDCLI7__CHECK_TLB_CREDIT_MASK
40661. DAGB6_RDCLI7__CHECK_TLB_CREDIT__SHIFT
40662. DAGB6_RDCLI7__MAX_BW_ENABLE_MASK
40663. DAGB6_RDCLI7__MAX_BW_ENABLE__SHIFT
40664. DAGB6_RDCLI7__MAX_BW_MASK
40665. DAGB6_RDCLI7__MAX_BW__SHIFT
40666. DAGB6_RDCLI7__MAX_OSD_MASK
40667. DAGB6_RDCLI7__MAX_OSD__SHIFT
40668. DAGB6_RDCLI7__MIN_BW_ENABLE_MASK
40669. DAGB6_RDCLI7__MIN_BW_ENABLE__SHIFT
40670. DAGB6_RDCLI7__MIN_BW_MASK
40671. DAGB6_RDCLI7__MIN_BW__SHIFT
40672. DAGB6_RDCLI7__OSD_LIMITER_ENABLE_MASK
40673. DAGB6_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
40674. DAGB6_RDCLI7__URG_HIGH_MASK
40675. DAGB6_RDCLI7__URG_HIGH__SHIFT
40676. DAGB6_RDCLI7__URG_LOW_MASK
40677. DAGB6_RDCLI7__URG_LOW__SHIFT
40678. DAGB6_RDCLI7__VIRT_CHAN_MASK
40679. DAGB6_RDCLI7__VIRT_CHAN__SHIFT
40680. DAGB6_RDCLI8__CHECK_TLB_CREDIT_MASK
40681. DAGB6_RDCLI8__CHECK_TLB_CREDIT__SHIFT
40682. DAGB6_RDCLI8__MAX_BW_ENABLE_MASK
40683. DAGB6_RDCLI8__MAX_BW_ENABLE__SHIFT
40684. DAGB6_RDCLI8__MAX_BW_MASK
40685. DAGB6_RDCLI8__MAX_BW__SHIFT
40686. DAGB6_RDCLI8__MAX_OSD_MASK
40687. DAGB6_RDCLI8__MAX_OSD__SHIFT
40688. DAGB6_RDCLI8__MIN_BW_ENABLE_MASK
40689. DAGB6_RDCLI8__MIN_BW_ENABLE__SHIFT
40690. DAGB6_RDCLI8__MIN_BW_MASK
40691. DAGB6_RDCLI8__MIN_BW__SHIFT
40692. DAGB6_RDCLI8__OSD_LIMITER_ENABLE_MASK
40693. DAGB6_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
40694. DAGB6_RDCLI8__URG_HIGH_MASK
40695. DAGB6_RDCLI8__URG_HIGH__SHIFT
40696. DAGB6_RDCLI8__URG_LOW_MASK
40697. DAGB6_RDCLI8__URG_LOW__SHIFT
40698. DAGB6_RDCLI8__VIRT_CHAN_MASK
40699. DAGB6_RDCLI8__VIRT_CHAN__SHIFT
40700. DAGB6_RDCLI9__CHECK_TLB_CREDIT_MASK
40701. DAGB6_RDCLI9__CHECK_TLB_CREDIT__SHIFT
40702. DAGB6_RDCLI9__MAX_BW_ENABLE_MASK
40703. DAGB6_RDCLI9__MAX_BW_ENABLE__SHIFT
40704. DAGB6_RDCLI9__MAX_BW_MASK
40705. DAGB6_RDCLI9__MAX_BW__SHIFT
40706. DAGB6_RDCLI9__MAX_OSD_MASK
40707. DAGB6_RDCLI9__MAX_OSD__SHIFT
40708. DAGB6_RDCLI9__MIN_BW_ENABLE_MASK
40709. DAGB6_RDCLI9__MIN_BW_ENABLE__SHIFT
40710. DAGB6_RDCLI9__MIN_BW_MASK
40711. DAGB6_RDCLI9__MIN_BW__SHIFT
40712. DAGB6_RDCLI9__OSD_LIMITER_ENABLE_MASK
40713. DAGB6_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
40714. DAGB6_RDCLI9__URG_HIGH_MASK
40715. DAGB6_RDCLI9__URG_HIGH__SHIFT
40716. DAGB6_RDCLI9__URG_LOW_MASK
40717. DAGB6_RDCLI9__URG_LOW__SHIFT
40718. DAGB6_RDCLI9__VIRT_CHAN_MASK
40719. DAGB6_RDCLI9__VIRT_CHAN__SHIFT
40720. DAGB6_RDCLI_ASK_PENDING__BUSY_MASK
40721. DAGB6_RDCLI_ASK_PENDING__BUSY__SHIFT
40722. DAGB6_RDCLI_GBLSEND_PENDING__BUSY_MASK
40723. DAGB6_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
40724. DAGB6_RDCLI_GO_PENDING__BUSY_MASK
40725. DAGB6_RDCLI_GO_PENDING__BUSY__SHIFT
40726. DAGB6_RDCLI_OARB_PENDING__BUSY_MASK
40727. DAGB6_RDCLI_OARB_PENDING__BUSY__SHIFT
40728. DAGB6_RDCLI_OSD_PENDING__BUSY_MASK
40729. DAGB6_RDCLI_OSD_PENDING__BUSY__SHIFT
40730. DAGB6_RDCLI_TLB_PENDING__BUSY_MASK
40731. DAGB6_RDCLI_TLB_PENDING__BUSY__SHIFT
40732. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
40733. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
40734. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
40735. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
40736. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
40737. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
40738. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
40739. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
40740. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
40741. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
40742. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
40743. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
40744. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
40745. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
40746. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
40747. DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
40748. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
40749. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
40750. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
40751. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
40752. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
40753. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
40754. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
40755. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
40756. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
40757. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
40758. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
40759. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
40760. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
40761. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
40762. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
40763. DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
40764. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
40765. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
40766. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
40767. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
40768. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
40769. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
40770. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
40771. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
40772. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
40773. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
40774. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
40775. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
40776. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
40777. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
40778. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
40779. DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
40780. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
40781. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
40782. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
40783. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
40784. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
40785. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
40786. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
40787. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
40788. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
40789. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
40790. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
40791. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
40792. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
40793. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
40794. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
40795. DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
40796. DAGB6_RD_ADDR_DAGB__DAGB_ENABLE_MASK
40797. DAGB6_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
40798. DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
40799. DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
40800. DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
40801. DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
40802. DAGB6_RD_ADDR_DAGB__WHOAMI_MASK
40803. DAGB6_RD_ADDR_DAGB__WHOAMI__SHIFT
40804. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
40805. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
40806. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
40807. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
40808. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
40809. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
40810. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
40811. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
40812. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
40813. DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
40814. DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
40815. DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
40816. DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
40817. DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
40818. DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
40819. DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
40820. DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
40821. DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
40822. DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
40823. DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
40824. DAGB6_RD_CNTL_MISC__IO_EA_CREDIT_MASK
40825. DAGB6_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
40826. DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
40827. DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
40828. DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
40829. DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
40830. DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
40831. DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
40832. DAGB6_RD_CNTL_MISC__UTCL2_CID_MASK
40833. DAGB6_RD_CNTL_MISC__UTCL2_CID__SHIFT
40834. DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
40835. DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
40836. DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
40837. DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
40838. DAGB6_RD_CNTL__IO_LEVEL_MASK
40839. DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
40840. DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
40841. DAGB6_RD_CNTL__IO_LEVEL__SHIFT
40842. DAGB6_RD_CNTL__SCLK_FREQ_MASK
40843. DAGB6_RD_CNTL__SCLK_FREQ__SHIFT
40844. DAGB6_RD_CNTL__SHARE_VC_NUM_MASK
40845. DAGB6_RD_CNTL__SHARE_VC_NUM__SHIFT
40846. DAGB6_RD_CNTL__VC_MAX_BW_WINDOW_MASK
40847. DAGB6_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
40848. DAGB6_RD_CREDITS_FULL__FULL_MASK
40849. DAGB6_RD_CREDITS_FULL__FULL__SHIFT
40850. DAGB6_RD_GMI_CNTL__EA_CREDIT_MASK
40851. DAGB6_RD_GMI_CNTL__EA_CREDIT__SHIFT
40852. DAGB6_RD_GMI_CNTL__LAZY_TIMER_MASK
40853. DAGB6_RD_GMI_CNTL__LAZY_TIMER__SHIFT
40854. DAGB6_RD_GMI_CNTL__LEVEL_MASK
40855. DAGB6_RD_GMI_CNTL__LEVEL__SHIFT
40856. DAGB6_RD_GMI_CNTL__MAX_BURST_MASK
40857. DAGB6_RD_GMI_CNTL__MAX_BURST__SHIFT
40858. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
40859. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
40860. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
40861. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
40862. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
40863. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
40864. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
40865. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
40866. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
40867. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
40868. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
40869. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
40870. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
40871. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
40872. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
40873. DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
40874. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
40875. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
40876. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
40877. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
40878. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
40879. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
40880. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
40881. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
40882. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
40883. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
40884. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
40885. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
40886. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
40887. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
40888. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
40889. DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
40890. DAGB6_RD_TLB_CREDIT__TLB0_MASK
40891. DAGB6_RD_TLB_CREDIT__TLB0__SHIFT
40892. DAGB6_RD_TLB_CREDIT__TLB1_MASK
40893. DAGB6_RD_TLB_CREDIT__TLB1__SHIFT
40894. DAGB6_RD_TLB_CREDIT__TLB2_MASK
40895. DAGB6_RD_TLB_CREDIT__TLB2__SHIFT
40896. DAGB6_RD_TLB_CREDIT__TLB3_MASK
40897. DAGB6_RD_TLB_CREDIT__TLB3__SHIFT
40898. DAGB6_RD_TLB_CREDIT__TLB4_MASK
40899. DAGB6_RD_TLB_CREDIT__TLB4__SHIFT
40900. DAGB6_RD_TLB_CREDIT__TLB5_MASK
40901. DAGB6_RD_TLB_CREDIT__TLB5__SHIFT
40902. DAGB6_RD_VC0_CNTL__EA_CREDIT_MASK
40903. DAGB6_RD_VC0_CNTL__EA_CREDIT__SHIFT
40904. DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
40905. DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
40906. DAGB6_RD_VC0_CNTL__MAX_BW_MASK
40907. DAGB6_RD_VC0_CNTL__MAX_BW__SHIFT
40908. DAGB6_RD_VC0_CNTL__MAX_OSD_MASK
40909. DAGB6_RD_VC0_CNTL__MAX_OSD__SHIFT
40910. DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
40911. DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
40912. DAGB6_RD_VC0_CNTL__MIN_BW_MASK
40913. DAGB6_RD_VC0_CNTL__MIN_BW__SHIFT
40914. DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
40915. DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
40916. DAGB6_RD_VC0_CNTL__STOR_CREDIT_MASK
40917. DAGB6_RD_VC0_CNTL__STOR_CREDIT__SHIFT
40918. DAGB6_RD_VC1_CNTL__EA_CREDIT_MASK
40919. DAGB6_RD_VC1_CNTL__EA_CREDIT__SHIFT
40920. DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
40921. DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
40922. DAGB6_RD_VC1_CNTL__MAX_BW_MASK
40923. DAGB6_RD_VC1_CNTL__MAX_BW__SHIFT
40924. DAGB6_RD_VC1_CNTL__MAX_OSD_MASK
40925. DAGB6_RD_VC1_CNTL__MAX_OSD__SHIFT
40926. DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
40927. DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
40928. DAGB6_RD_VC1_CNTL__MIN_BW_MASK
40929. DAGB6_RD_VC1_CNTL__MIN_BW__SHIFT
40930. DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
40931. DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
40932. DAGB6_RD_VC1_CNTL__STOR_CREDIT_MASK
40933. DAGB6_RD_VC1_CNTL__STOR_CREDIT__SHIFT
40934. DAGB6_RD_VC2_CNTL__EA_CREDIT_MASK
40935. DAGB6_RD_VC2_CNTL__EA_CREDIT__SHIFT
40936. DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
40937. DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
40938. DAGB6_RD_VC2_CNTL__MAX_BW_MASK
40939. DAGB6_RD_VC2_CNTL__MAX_BW__SHIFT
40940. DAGB6_RD_VC2_CNTL__MAX_OSD_MASK
40941. DAGB6_RD_VC2_CNTL__MAX_OSD__SHIFT
40942. DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
40943. DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
40944. DAGB6_RD_VC2_CNTL__MIN_BW_MASK
40945. DAGB6_RD_VC2_CNTL__MIN_BW__SHIFT
40946. DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
40947. DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
40948. DAGB6_RD_VC2_CNTL__STOR_CREDIT_MASK
40949. DAGB6_RD_VC2_CNTL__STOR_CREDIT__SHIFT
40950. DAGB6_RD_VC3_CNTL__EA_CREDIT_MASK
40951. DAGB6_RD_VC3_CNTL__EA_CREDIT__SHIFT
40952. DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
40953. DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
40954. DAGB6_RD_VC3_CNTL__MAX_BW_MASK
40955. DAGB6_RD_VC3_CNTL__MAX_BW__SHIFT
40956. DAGB6_RD_VC3_CNTL__MAX_OSD_MASK
40957. DAGB6_RD_VC3_CNTL__MAX_OSD__SHIFT
40958. DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
40959. DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
40960. DAGB6_RD_VC3_CNTL__MIN_BW_MASK
40961. DAGB6_RD_VC3_CNTL__MIN_BW__SHIFT
40962. DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
40963. DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
40964. DAGB6_RD_VC3_CNTL__STOR_CREDIT_MASK
40965. DAGB6_RD_VC3_CNTL__STOR_CREDIT__SHIFT
40966. DAGB6_RD_VC4_CNTL__EA_CREDIT_MASK
40967. DAGB6_RD_VC4_CNTL__EA_CREDIT__SHIFT
40968. DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
40969. DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
40970. DAGB6_RD_VC4_CNTL__MAX_BW_MASK
40971. DAGB6_RD_VC4_CNTL__MAX_BW__SHIFT
40972. DAGB6_RD_VC4_CNTL__MAX_OSD_MASK
40973. DAGB6_RD_VC4_CNTL__MAX_OSD__SHIFT
40974. DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
40975. DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
40976. DAGB6_RD_VC4_CNTL__MIN_BW_MASK
40977. DAGB6_RD_VC4_CNTL__MIN_BW__SHIFT
40978. DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
40979. DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
40980. DAGB6_RD_VC4_CNTL__STOR_CREDIT_MASK
40981. DAGB6_RD_VC4_CNTL__STOR_CREDIT__SHIFT
40982. DAGB6_RD_VC5_CNTL__EA_CREDIT_MASK
40983. DAGB6_RD_VC5_CNTL__EA_CREDIT__SHIFT
40984. DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
40985. DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
40986. DAGB6_RD_VC5_CNTL__MAX_BW_MASK
40987. DAGB6_RD_VC5_CNTL__MAX_BW__SHIFT
40988. DAGB6_RD_VC5_CNTL__MAX_OSD_MASK
40989. DAGB6_RD_VC5_CNTL__MAX_OSD__SHIFT
40990. DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
40991. DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
40992. DAGB6_RD_VC5_CNTL__MIN_BW_MASK
40993. DAGB6_RD_VC5_CNTL__MIN_BW__SHIFT
40994. DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
40995. DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
40996. DAGB6_RD_VC5_CNTL__STOR_CREDIT_MASK
40997. DAGB6_RD_VC5_CNTL__STOR_CREDIT__SHIFT
40998. DAGB6_RD_VC6_CNTL__EA_CREDIT_MASK
40999. DAGB6_RD_VC6_CNTL__EA_CREDIT__SHIFT
41000. DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
41001. DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
41002. DAGB6_RD_VC6_CNTL__MAX_BW_MASK
41003. DAGB6_RD_VC6_CNTL__MAX_BW__SHIFT
41004. DAGB6_RD_VC6_CNTL__MAX_OSD_MASK
41005. DAGB6_RD_VC6_CNTL__MAX_OSD__SHIFT
41006. DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
41007. DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
41008. DAGB6_RD_VC6_CNTL__MIN_BW_MASK
41009. DAGB6_RD_VC6_CNTL__MIN_BW__SHIFT
41010. DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
41011. DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
41012. DAGB6_RD_VC6_CNTL__STOR_CREDIT_MASK
41013. DAGB6_RD_VC6_CNTL__STOR_CREDIT__SHIFT
41014. DAGB6_RD_VC7_CNTL__EA_CREDIT_MASK
41015. DAGB6_RD_VC7_CNTL__EA_CREDIT__SHIFT
41016. DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
41017. DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
41018. DAGB6_RD_VC7_CNTL__MAX_BW_MASK
41019. DAGB6_RD_VC7_CNTL__MAX_BW__SHIFT
41020. DAGB6_RD_VC7_CNTL__MAX_OSD_MASK
41021. DAGB6_RD_VC7_CNTL__MAX_OSD__SHIFT
41022. DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
41023. DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
41024. DAGB6_RD_VC7_CNTL__MIN_BW_MASK
41025. DAGB6_RD_VC7_CNTL__MIN_BW__SHIFT
41026. DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
41027. DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
41028. DAGB6_RD_VC7_CNTL__STOR_CREDIT_MASK
41029. DAGB6_RD_VC7_CNTL__STOR_CREDIT__SHIFT
41030. DAGB6_RESERVE0__RESERVE_MASK
41031. DAGB6_RESERVE0__RESERVE__SHIFT
41032. DAGB6_RESERVE10__RESERVE_MASK
41033. DAGB6_RESERVE10__RESERVE__SHIFT
41034. DAGB6_RESERVE11__RESERVE_MASK
41035. DAGB6_RESERVE11__RESERVE__SHIFT
41036. DAGB6_RESERVE12__RESERVE_MASK
41037. DAGB6_RESERVE12__RESERVE__SHIFT
41038. DAGB6_RESERVE13__RESERVE_MASK
41039. DAGB6_RESERVE13__RESERVE__SHIFT
41040. DAGB6_RESERVE1__RESERVE_MASK
41041. DAGB6_RESERVE1__RESERVE__SHIFT
41042. DAGB6_RESERVE2__RESERVE_MASK
41043. DAGB6_RESERVE2__RESERVE__SHIFT
41044. DAGB6_RESERVE3__RESERVE_MASK
41045. DAGB6_RESERVE3__RESERVE__SHIFT
41046. DAGB6_RESERVE4__RESERVE_MASK
41047. DAGB6_RESERVE4__RESERVE__SHIFT
41048. DAGB6_RESERVE5__RESERVE_MASK
41049. DAGB6_RESERVE5__RESERVE__SHIFT
41050. DAGB6_RESERVE6__RESERVE_MASK
41051. DAGB6_RESERVE6__RESERVE__SHIFT
41052. DAGB6_RESERVE7__RESERVE_MASK
41053. DAGB6_RESERVE7__RESERVE__SHIFT
41054. DAGB6_RESERVE8__RESERVE_MASK
41055. DAGB6_RESERVE8__RESERVE__SHIFT
41056. DAGB6_RESERVE9__RESERVE_MASK
41057. DAGB6_RESERVE9__RESERVE__SHIFT
41058. DAGB6_WRCLI0__CHECK_TLB_CREDIT_MASK
41059. DAGB6_WRCLI0__CHECK_TLB_CREDIT__SHIFT
41060. DAGB6_WRCLI0__MAX_BW_ENABLE_MASK
41061. DAGB6_WRCLI0__MAX_BW_ENABLE__SHIFT
41062. DAGB6_WRCLI0__MAX_BW_MASK
41063. DAGB6_WRCLI0__MAX_BW__SHIFT
41064. DAGB6_WRCLI0__MAX_OSD_MASK
41065. DAGB6_WRCLI0__MAX_OSD__SHIFT
41066. DAGB6_WRCLI0__MIN_BW_ENABLE_MASK
41067. DAGB6_WRCLI0__MIN_BW_ENABLE__SHIFT
41068. DAGB6_WRCLI0__MIN_BW_MASK
41069. DAGB6_WRCLI0__MIN_BW__SHIFT
41070. DAGB6_WRCLI0__OSD_LIMITER_ENABLE_MASK
41071. DAGB6_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
41072. DAGB6_WRCLI0__URG_HIGH_MASK
41073. DAGB6_WRCLI0__URG_HIGH__SHIFT
41074. DAGB6_WRCLI0__URG_LOW_MASK
41075. DAGB6_WRCLI0__URG_LOW__SHIFT
41076. DAGB6_WRCLI0__VIRT_CHAN_MASK
41077. DAGB6_WRCLI0__VIRT_CHAN__SHIFT
41078. DAGB6_WRCLI10__CHECK_TLB_CREDIT_MASK
41079. DAGB6_WRCLI10__CHECK_TLB_CREDIT__SHIFT
41080. DAGB6_WRCLI10__MAX_BW_ENABLE_MASK
41081. DAGB6_WRCLI10__MAX_BW_ENABLE__SHIFT
41082. DAGB6_WRCLI10__MAX_BW_MASK
41083. DAGB6_WRCLI10__MAX_BW__SHIFT
41084. DAGB6_WRCLI10__MAX_OSD_MASK
41085. DAGB6_WRCLI10__MAX_OSD__SHIFT
41086. DAGB6_WRCLI10__MIN_BW_ENABLE_MASK
41087. DAGB6_WRCLI10__MIN_BW_ENABLE__SHIFT
41088. DAGB6_WRCLI10__MIN_BW_MASK
41089. DAGB6_WRCLI10__MIN_BW__SHIFT
41090. DAGB6_WRCLI10__OSD_LIMITER_ENABLE_MASK
41091. DAGB6_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
41092. DAGB6_WRCLI10__URG_HIGH_MASK
41093. DAGB6_WRCLI10__URG_HIGH__SHIFT
41094. DAGB6_WRCLI10__URG_LOW_MASK
41095. DAGB6_WRCLI10__URG_LOW__SHIFT
41096. DAGB6_WRCLI10__VIRT_CHAN_MASK
41097. DAGB6_WRCLI10__VIRT_CHAN__SHIFT
41098. DAGB6_WRCLI11__CHECK_TLB_CREDIT_MASK
41099. DAGB6_WRCLI11__CHECK_TLB_CREDIT__SHIFT
41100. DAGB6_WRCLI11__MAX_BW_ENABLE_MASK
41101. DAGB6_WRCLI11__MAX_BW_ENABLE__SHIFT
41102. DAGB6_WRCLI11__MAX_BW_MASK
41103. DAGB6_WRCLI11__MAX_BW__SHIFT
41104. DAGB6_WRCLI11__MAX_OSD_MASK
41105. DAGB6_WRCLI11__MAX_OSD__SHIFT
41106. DAGB6_WRCLI11__MIN_BW_ENABLE_MASK
41107. DAGB6_WRCLI11__MIN_BW_ENABLE__SHIFT
41108. DAGB6_WRCLI11__MIN_BW_MASK
41109. DAGB6_WRCLI11__MIN_BW__SHIFT
41110. DAGB6_WRCLI11__OSD_LIMITER_ENABLE_MASK
41111. DAGB6_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
41112. DAGB6_WRCLI11__URG_HIGH_MASK
41113. DAGB6_WRCLI11__URG_HIGH__SHIFT
41114. DAGB6_WRCLI11__URG_LOW_MASK
41115. DAGB6_WRCLI11__URG_LOW__SHIFT
41116. DAGB6_WRCLI11__VIRT_CHAN_MASK
41117. DAGB6_WRCLI11__VIRT_CHAN__SHIFT
41118. DAGB6_WRCLI12__CHECK_TLB_CREDIT_MASK
41119. DAGB6_WRCLI12__CHECK_TLB_CREDIT__SHIFT
41120. DAGB6_WRCLI12__MAX_BW_ENABLE_MASK
41121. DAGB6_WRCLI12__MAX_BW_ENABLE__SHIFT
41122. DAGB6_WRCLI12__MAX_BW_MASK
41123. DAGB6_WRCLI12__MAX_BW__SHIFT
41124. DAGB6_WRCLI12__MAX_OSD_MASK
41125. DAGB6_WRCLI12__MAX_OSD__SHIFT
41126. DAGB6_WRCLI12__MIN_BW_ENABLE_MASK
41127. DAGB6_WRCLI12__MIN_BW_ENABLE__SHIFT
41128. DAGB6_WRCLI12__MIN_BW_MASK
41129. DAGB6_WRCLI12__MIN_BW__SHIFT
41130. DAGB6_WRCLI12__OSD_LIMITER_ENABLE_MASK
41131. DAGB6_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
41132. DAGB6_WRCLI12__URG_HIGH_MASK
41133. DAGB6_WRCLI12__URG_HIGH__SHIFT
41134. DAGB6_WRCLI12__URG_LOW_MASK
41135. DAGB6_WRCLI12__URG_LOW__SHIFT
41136. DAGB6_WRCLI12__VIRT_CHAN_MASK
41137. DAGB6_WRCLI12__VIRT_CHAN__SHIFT
41138. DAGB6_WRCLI13__CHECK_TLB_CREDIT_MASK
41139. DAGB6_WRCLI13__CHECK_TLB_CREDIT__SHIFT
41140. DAGB6_WRCLI13__MAX_BW_ENABLE_MASK
41141. DAGB6_WRCLI13__MAX_BW_ENABLE__SHIFT
41142. DAGB6_WRCLI13__MAX_BW_MASK
41143. DAGB6_WRCLI13__MAX_BW__SHIFT
41144. DAGB6_WRCLI13__MAX_OSD_MASK
41145. DAGB6_WRCLI13__MAX_OSD__SHIFT
41146. DAGB6_WRCLI13__MIN_BW_ENABLE_MASK
41147. DAGB6_WRCLI13__MIN_BW_ENABLE__SHIFT
41148. DAGB6_WRCLI13__MIN_BW_MASK
41149. DAGB6_WRCLI13__MIN_BW__SHIFT
41150. DAGB6_WRCLI13__OSD_LIMITER_ENABLE_MASK
41151. DAGB6_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
41152. DAGB6_WRCLI13__URG_HIGH_MASK
41153. DAGB6_WRCLI13__URG_HIGH__SHIFT
41154. DAGB6_WRCLI13__URG_LOW_MASK
41155. DAGB6_WRCLI13__URG_LOW__SHIFT
41156. DAGB6_WRCLI13__VIRT_CHAN_MASK
41157. DAGB6_WRCLI13__VIRT_CHAN__SHIFT
41158. DAGB6_WRCLI14__CHECK_TLB_CREDIT_MASK
41159. DAGB6_WRCLI14__CHECK_TLB_CREDIT__SHIFT
41160. DAGB6_WRCLI14__MAX_BW_ENABLE_MASK
41161. DAGB6_WRCLI14__MAX_BW_ENABLE__SHIFT
41162. DAGB6_WRCLI14__MAX_BW_MASK
41163. DAGB6_WRCLI14__MAX_BW__SHIFT
41164. DAGB6_WRCLI14__MAX_OSD_MASK
41165. DAGB6_WRCLI14__MAX_OSD__SHIFT
41166. DAGB6_WRCLI14__MIN_BW_ENABLE_MASK
41167. DAGB6_WRCLI14__MIN_BW_ENABLE__SHIFT
41168. DAGB6_WRCLI14__MIN_BW_MASK
41169. DAGB6_WRCLI14__MIN_BW__SHIFT
41170. DAGB6_WRCLI14__OSD_LIMITER_ENABLE_MASK
41171. DAGB6_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
41172. DAGB6_WRCLI14__URG_HIGH_MASK
41173. DAGB6_WRCLI14__URG_HIGH__SHIFT
41174. DAGB6_WRCLI14__URG_LOW_MASK
41175. DAGB6_WRCLI14__URG_LOW__SHIFT
41176. DAGB6_WRCLI14__VIRT_CHAN_MASK
41177. DAGB6_WRCLI14__VIRT_CHAN__SHIFT
41178. DAGB6_WRCLI15__CHECK_TLB_CREDIT_MASK
41179. DAGB6_WRCLI15__CHECK_TLB_CREDIT__SHIFT
41180. DAGB6_WRCLI15__MAX_BW_ENABLE_MASK
41181. DAGB6_WRCLI15__MAX_BW_ENABLE__SHIFT
41182. DAGB6_WRCLI15__MAX_BW_MASK
41183. DAGB6_WRCLI15__MAX_BW__SHIFT
41184. DAGB6_WRCLI15__MAX_OSD_MASK
41185. DAGB6_WRCLI15__MAX_OSD__SHIFT
41186. DAGB6_WRCLI15__MIN_BW_ENABLE_MASK
41187. DAGB6_WRCLI15__MIN_BW_ENABLE__SHIFT
41188. DAGB6_WRCLI15__MIN_BW_MASK
41189. DAGB6_WRCLI15__MIN_BW__SHIFT
41190. DAGB6_WRCLI15__OSD_LIMITER_ENABLE_MASK
41191. DAGB6_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
41192. DAGB6_WRCLI15__URG_HIGH_MASK
41193. DAGB6_WRCLI15__URG_HIGH__SHIFT
41194. DAGB6_WRCLI15__URG_LOW_MASK
41195. DAGB6_WRCLI15__URG_LOW__SHIFT
41196. DAGB6_WRCLI15__VIRT_CHAN_MASK
41197. DAGB6_WRCLI15__VIRT_CHAN__SHIFT
41198. DAGB6_WRCLI1__CHECK_TLB_CREDIT_MASK
41199. DAGB6_WRCLI1__CHECK_TLB_CREDIT__SHIFT
41200. DAGB6_WRCLI1__MAX_BW_ENABLE_MASK
41201. DAGB6_WRCLI1__MAX_BW_ENABLE__SHIFT
41202. DAGB6_WRCLI1__MAX_BW_MASK
41203. DAGB6_WRCLI1__MAX_BW__SHIFT
41204. DAGB6_WRCLI1__MAX_OSD_MASK
41205. DAGB6_WRCLI1__MAX_OSD__SHIFT
41206. DAGB6_WRCLI1__MIN_BW_ENABLE_MASK
41207. DAGB6_WRCLI1__MIN_BW_ENABLE__SHIFT
41208. DAGB6_WRCLI1__MIN_BW_MASK
41209. DAGB6_WRCLI1__MIN_BW__SHIFT
41210. DAGB6_WRCLI1__OSD_LIMITER_ENABLE_MASK
41211. DAGB6_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
41212. DAGB6_WRCLI1__URG_HIGH_MASK
41213. DAGB6_WRCLI1__URG_HIGH__SHIFT
41214. DAGB6_WRCLI1__URG_LOW_MASK
41215. DAGB6_WRCLI1__URG_LOW__SHIFT
41216. DAGB6_WRCLI1__VIRT_CHAN_MASK
41217. DAGB6_WRCLI1__VIRT_CHAN__SHIFT
41218. DAGB6_WRCLI2__CHECK_TLB_CREDIT_MASK
41219. DAGB6_WRCLI2__CHECK_TLB_CREDIT__SHIFT
41220. DAGB6_WRCLI2__MAX_BW_ENABLE_MASK
41221. DAGB6_WRCLI2__MAX_BW_ENABLE__SHIFT
41222. DAGB6_WRCLI2__MAX_BW_MASK
41223. DAGB6_WRCLI2__MAX_BW__SHIFT
41224. DAGB6_WRCLI2__MAX_OSD_MASK
41225. DAGB6_WRCLI2__MAX_OSD__SHIFT
41226. DAGB6_WRCLI2__MIN_BW_ENABLE_MASK
41227. DAGB6_WRCLI2__MIN_BW_ENABLE__SHIFT
41228. DAGB6_WRCLI2__MIN_BW_MASK
41229. DAGB6_WRCLI2__MIN_BW__SHIFT
41230. DAGB6_WRCLI2__OSD_LIMITER_ENABLE_MASK
41231. DAGB6_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
41232. DAGB6_WRCLI2__URG_HIGH_MASK
41233. DAGB6_WRCLI2__URG_HIGH__SHIFT
41234. DAGB6_WRCLI2__URG_LOW_MASK
41235. DAGB6_WRCLI2__URG_LOW__SHIFT
41236. DAGB6_WRCLI2__VIRT_CHAN_MASK
41237. DAGB6_WRCLI2__VIRT_CHAN__SHIFT
41238. DAGB6_WRCLI3__CHECK_TLB_CREDIT_MASK
41239. DAGB6_WRCLI3__CHECK_TLB_CREDIT__SHIFT
41240. DAGB6_WRCLI3__MAX_BW_ENABLE_MASK
41241. DAGB6_WRCLI3__MAX_BW_ENABLE__SHIFT
41242. DAGB6_WRCLI3__MAX_BW_MASK
41243. DAGB6_WRCLI3__MAX_BW__SHIFT
41244. DAGB6_WRCLI3__MAX_OSD_MASK
41245. DAGB6_WRCLI3__MAX_OSD__SHIFT
41246. DAGB6_WRCLI3__MIN_BW_ENABLE_MASK
41247. DAGB6_WRCLI3__MIN_BW_ENABLE__SHIFT
41248. DAGB6_WRCLI3__MIN_BW_MASK
41249. DAGB6_WRCLI3__MIN_BW__SHIFT
41250. DAGB6_WRCLI3__OSD_LIMITER_ENABLE_MASK
41251. DAGB6_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
41252. DAGB6_WRCLI3__URG_HIGH_MASK
41253. DAGB6_WRCLI3__URG_HIGH__SHIFT
41254. DAGB6_WRCLI3__URG_LOW_MASK
41255. DAGB6_WRCLI3__URG_LOW__SHIFT
41256. DAGB6_WRCLI3__VIRT_CHAN_MASK
41257. DAGB6_WRCLI3__VIRT_CHAN__SHIFT
41258. DAGB6_WRCLI4__CHECK_TLB_CREDIT_MASK
41259. DAGB6_WRCLI4__CHECK_TLB_CREDIT__SHIFT
41260. DAGB6_WRCLI4__MAX_BW_ENABLE_MASK
41261. DAGB6_WRCLI4__MAX_BW_ENABLE__SHIFT
41262. DAGB6_WRCLI4__MAX_BW_MASK
41263. DAGB6_WRCLI4__MAX_BW__SHIFT
41264. DAGB6_WRCLI4__MAX_OSD_MASK
41265. DAGB6_WRCLI4__MAX_OSD__SHIFT
41266. DAGB6_WRCLI4__MIN_BW_ENABLE_MASK
41267. DAGB6_WRCLI4__MIN_BW_ENABLE__SHIFT
41268. DAGB6_WRCLI4__MIN_BW_MASK
41269. DAGB6_WRCLI4__MIN_BW__SHIFT
41270. DAGB6_WRCLI4__OSD_LIMITER_ENABLE_MASK
41271. DAGB6_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
41272. DAGB6_WRCLI4__URG_HIGH_MASK
41273. DAGB6_WRCLI4__URG_HIGH__SHIFT
41274. DAGB6_WRCLI4__URG_LOW_MASK
41275. DAGB6_WRCLI4__URG_LOW__SHIFT
41276. DAGB6_WRCLI4__VIRT_CHAN_MASK
41277. DAGB6_WRCLI4__VIRT_CHAN__SHIFT
41278. DAGB6_WRCLI5__CHECK_TLB_CREDIT_MASK
41279. DAGB6_WRCLI5__CHECK_TLB_CREDIT__SHIFT
41280. DAGB6_WRCLI5__MAX_BW_ENABLE_MASK
41281. DAGB6_WRCLI5__MAX_BW_ENABLE__SHIFT
41282. DAGB6_WRCLI5__MAX_BW_MASK
41283. DAGB6_WRCLI5__MAX_BW__SHIFT
41284. DAGB6_WRCLI5__MAX_OSD_MASK
41285. DAGB6_WRCLI5__MAX_OSD__SHIFT
41286. DAGB6_WRCLI5__MIN_BW_ENABLE_MASK
41287. DAGB6_WRCLI5__MIN_BW_ENABLE__SHIFT
41288. DAGB6_WRCLI5__MIN_BW_MASK
41289. DAGB6_WRCLI5__MIN_BW__SHIFT
41290. DAGB6_WRCLI5__OSD_LIMITER_ENABLE_MASK
41291. DAGB6_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
41292. DAGB6_WRCLI5__URG_HIGH_MASK
41293. DAGB6_WRCLI5__URG_HIGH__SHIFT
41294. DAGB6_WRCLI5__URG_LOW_MASK
41295. DAGB6_WRCLI5__URG_LOW__SHIFT
41296. DAGB6_WRCLI5__VIRT_CHAN_MASK
41297. DAGB6_WRCLI5__VIRT_CHAN__SHIFT
41298. DAGB6_WRCLI6__CHECK_TLB_CREDIT_MASK
41299. DAGB6_WRCLI6__CHECK_TLB_CREDIT__SHIFT
41300. DAGB6_WRCLI6__MAX_BW_ENABLE_MASK
41301. DAGB6_WRCLI6__MAX_BW_ENABLE__SHIFT
41302. DAGB6_WRCLI6__MAX_BW_MASK
41303. DAGB6_WRCLI6__MAX_BW__SHIFT
41304. DAGB6_WRCLI6__MAX_OSD_MASK
41305. DAGB6_WRCLI6__MAX_OSD__SHIFT
41306. DAGB6_WRCLI6__MIN_BW_ENABLE_MASK
41307. DAGB6_WRCLI6__MIN_BW_ENABLE__SHIFT
41308. DAGB6_WRCLI6__MIN_BW_MASK
41309. DAGB6_WRCLI6__MIN_BW__SHIFT
41310. DAGB6_WRCLI6__OSD_LIMITER_ENABLE_MASK
41311. DAGB6_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
41312. DAGB6_WRCLI6__URG_HIGH_MASK
41313. DAGB6_WRCLI6__URG_HIGH__SHIFT
41314. DAGB6_WRCLI6__URG_LOW_MASK
41315. DAGB6_WRCLI6__URG_LOW__SHIFT
41316. DAGB6_WRCLI6__VIRT_CHAN_MASK
41317. DAGB6_WRCLI6__VIRT_CHAN__SHIFT
41318. DAGB6_WRCLI7__CHECK_TLB_CREDIT_MASK
41319. DAGB6_WRCLI7__CHECK_TLB_CREDIT__SHIFT
41320. DAGB6_WRCLI7__MAX_BW_ENABLE_MASK
41321. DAGB6_WRCLI7__MAX_BW_ENABLE__SHIFT
41322. DAGB6_WRCLI7__MAX_BW_MASK
41323. DAGB6_WRCLI7__MAX_BW__SHIFT
41324. DAGB6_WRCLI7__MAX_OSD_MASK
41325. DAGB6_WRCLI7__MAX_OSD__SHIFT
41326. DAGB6_WRCLI7__MIN_BW_ENABLE_MASK
41327. DAGB6_WRCLI7__MIN_BW_ENABLE__SHIFT
41328. DAGB6_WRCLI7__MIN_BW_MASK
41329. DAGB6_WRCLI7__MIN_BW__SHIFT
41330. DAGB6_WRCLI7__OSD_LIMITER_ENABLE_MASK
41331. DAGB6_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
41332. DAGB6_WRCLI7__URG_HIGH_MASK
41333. DAGB6_WRCLI7__URG_HIGH__SHIFT
41334. DAGB6_WRCLI7__URG_LOW_MASK
41335. DAGB6_WRCLI7__URG_LOW__SHIFT
41336. DAGB6_WRCLI7__VIRT_CHAN_MASK
41337. DAGB6_WRCLI7__VIRT_CHAN__SHIFT
41338. DAGB6_WRCLI8__CHECK_TLB_CREDIT_MASK
41339. DAGB6_WRCLI8__CHECK_TLB_CREDIT__SHIFT
41340. DAGB6_WRCLI8__MAX_BW_ENABLE_MASK
41341. DAGB6_WRCLI8__MAX_BW_ENABLE__SHIFT
41342. DAGB6_WRCLI8__MAX_BW_MASK
41343. DAGB6_WRCLI8__MAX_BW__SHIFT
41344. DAGB6_WRCLI8__MAX_OSD_MASK
41345. DAGB6_WRCLI8__MAX_OSD__SHIFT
41346. DAGB6_WRCLI8__MIN_BW_ENABLE_MASK
41347. DAGB6_WRCLI8__MIN_BW_ENABLE__SHIFT
41348. DAGB6_WRCLI8__MIN_BW_MASK
41349. DAGB6_WRCLI8__MIN_BW__SHIFT
41350. DAGB6_WRCLI8__OSD_LIMITER_ENABLE_MASK
41351. DAGB6_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
41352. DAGB6_WRCLI8__URG_HIGH_MASK
41353. DAGB6_WRCLI8__URG_HIGH__SHIFT
41354. DAGB6_WRCLI8__URG_LOW_MASK
41355. DAGB6_WRCLI8__URG_LOW__SHIFT
41356. DAGB6_WRCLI8__VIRT_CHAN_MASK
41357. DAGB6_WRCLI8__VIRT_CHAN__SHIFT
41358. DAGB6_WRCLI9__CHECK_TLB_CREDIT_MASK
41359. DAGB6_WRCLI9__CHECK_TLB_CREDIT__SHIFT
41360. DAGB6_WRCLI9__MAX_BW_ENABLE_MASK
41361. DAGB6_WRCLI9__MAX_BW_ENABLE__SHIFT
41362. DAGB6_WRCLI9__MAX_BW_MASK
41363. DAGB6_WRCLI9__MAX_BW__SHIFT
41364. DAGB6_WRCLI9__MAX_OSD_MASK
41365. DAGB6_WRCLI9__MAX_OSD__SHIFT
41366. DAGB6_WRCLI9__MIN_BW_ENABLE_MASK
41367. DAGB6_WRCLI9__MIN_BW_ENABLE__SHIFT
41368. DAGB6_WRCLI9__MIN_BW_MASK
41369. DAGB6_WRCLI9__MIN_BW__SHIFT
41370. DAGB6_WRCLI9__OSD_LIMITER_ENABLE_MASK
41371. DAGB6_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
41372. DAGB6_WRCLI9__URG_HIGH_MASK
41373. DAGB6_WRCLI9__URG_HIGH__SHIFT
41374. DAGB6_WRCLI9__URG_LOW_MASK
41375. DAGB6_WRCLI9__URG_LOW__SHIFT
41376. DAGB6_WRCLI9__VIRT_CHAN_MASK
41377. DAGB6_WRCLI9__VIRT_CHAN__SHIFT
41378. DAGB6_WRCLI_ASK_PENDING__BUSY_MASK
41379. DAGB6_WRCLI_ASK_PENDING__BUSY__SHIFT
41380. DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
41381. DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
41382. DAGB6_WRCLI_DBUS_GO_PENDING__BUSY_MASK
41383. DAGB6_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
41384. DAGB6_WRCLI_GBLSEND_PENDING__BUSY_MASK
41385. DAGB6_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
41386. DAGB6_WRCLI_GO_PENDING__BUSY_MASK
41387. DAGB6_WRCLI_GO_PENDING__BUSY__SHIFT
41388. DAGB6_WRCLI_OARB_PENDING__BUSY_MASK
41389. DAGB6_WRCLI_OARB_PENDING__BUSY__SHIFT
41390. DAGB6_WRCLI_OSD_PENDING__BUSY_MASK
41391. DAGB6_WRCLI_OSD_PENDING__BUSY__SHIFT
41392. DAGB6_WRCLI_TLB_PENDING__BUSY_MASK
41393. DAGB6_WRCLI_TLB_PENDING__BUSY__SHIFT
41394. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
41395. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
41396. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
41397. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
41398. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
41399. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
41400. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
41401. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
41402. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
41403. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
41404. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
41405. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
41406. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
41407. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
41408. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
41409. DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
41410. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
41411. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
41412. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
41413. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
41414. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
41415. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
41416. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
41417. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
41418. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
41419. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
41420. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
41421. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
41422. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
41423. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
41424. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
41425. DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
41426. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
41427. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
41428. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
41429. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
41430. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
41431. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
41432. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
41433. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
41434. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
41435. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
41436. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
41437. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
41438. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
41439. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
41440. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
41441. DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
41442. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
41443. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
41444. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
41445. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
41446. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
41447. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
41448. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
41449. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
41450. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
41451. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
41452. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
41453. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
41454. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
41455. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
41456. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
41457. DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
41458. DAGB6_WR_ADDR_DAGB__DAGB_ENABLE_MASK
41459. DAGB6_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
41460. DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
41461. DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
41462. DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
41463. DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
41464. DAGB6_WR_ADDR_DAGB__WHOAMI_MASK
41465. DAGB6_WR_ADDR_DAGB__WHOAMI__SHIFT
41466. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
41467. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
41468. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
41469. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
41470. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
41471. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
41472. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
41473. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
41474. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
41475. DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
41476. DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
41477. DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
41478. DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
41479. DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
41480. DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
41481. DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
41482. DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
41483. DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
41484. DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
41485. DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
41486. DAGB6_WR_CNTL_MISC__IO_EA_CREDIT_MASK
41487. DAGB6_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
41488. DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
41489. DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
41490. DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
41491. DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
41492. DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
41493. DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
41494. DAGB6_WR_CNTL_MISC__UTCL2_CID_MASK
41495. DAGB6_WR_CNTL_MISC__UTCL2_CID__SHIFT
41496. DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
41497. DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
41498. DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
41499. DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
41500. DAGB6_WR_CNTL__IO_LEVEL_MASK
41501. DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
41502. DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
41503. DAGB6_WR_CNTL__IO_LEVEL__SHIFT
41504. DAGB6_WR_CNTL__SCLK_FREQ_MASK
41505. DAGB6_WR_CNTL__SCLK_FREQ__SHIFT
41506. DAGB6_WR_CNTL__SHARE_VC_NUM_MASK
41507. DAGB6_WR_CNTL__SHARE_VC_NUM__SHIFT
41508. DAGB6_WR_CNTL__VC_MAX_BW_WINDOW_MASK
41509. DAGB6_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
41510. DAGB6_WR_CREDITS_FULL__FULL_MASK
41511. DAGB6_WR_CREDITS_FULL__FULL__SHIFT
41512. DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
41513. DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
41514. DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
41515. DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
41516. DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
41517. DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
41518. DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
41519. DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
41520. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
41521. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
41522. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
41523. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
41524. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
41525. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
41526. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
41527. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
41528. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
41529. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
41530. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
41531. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
41532. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
41533. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
41534. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
41535. DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
41536. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
41537. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
41538. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
41539. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
41540. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
41541. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
41542. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
41543. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
41544. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
41545. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
41546. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
41547. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
41548. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
41549. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
41550. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
41551. DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
41552. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
41553. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
41554. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
41555. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
41556. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
41557. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
41558. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
41559. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
41560. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
41561. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
41562. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
41563. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
41564. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
41565. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
41566. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
41567. DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
41568. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
41569. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
41570. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
41571. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
41572. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
41573. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
41574. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
41575. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
41576. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
41577. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
41578. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
41579. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
41580. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
41581. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
41582. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
41583. DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
41584. DAGB6_WR_DATA_DAGB__DAGB_ENABLE_MASK
41585. DAGB6_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
41586. DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
41587. DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
41588. DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
41589. DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
41590. DAGB6_WR_DATA_DAGB__WHOAMI_MASK
41591. DAGB6_WR_DATA_DAGB__WHOAMI__SHIFT
41592. DAGB6_WR_GMI_CNTL__EA_CREDIT_MASK
41593. DAGB6_WR_GMI_CNTL__EA_CREDIT__SHIFT
41594. DAGB6_WR_GMI_CNTL__LAZY_TIMER_MASK
41595. DAGB6_WR_GMI_CNTL__LAZY_TIMER__SHIFT
41596. DAGB6_WR_GMI_CNTL__LEVEL_MASK
41597. DAGB6_WR_GMI_CNTL__LEVEL__SHIFT
41598. DAGB6_WR_GMI_CNTL__MAX_BURST_MASK
41599. DAGB6_WR_GMI_CNTL__MAX_BURST__SHIFT
41600. DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
41601. DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
41602. DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
41603. DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
41604. DAGB6_WR_MISC_CREDIT__OSD_CREDIT_MASK
41605. DAGB6_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
41606. DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
41607. DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
41608. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
41609. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
41610. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
41611. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
41612. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
41613. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
41614. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
41615. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
41616. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
41617. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
41618. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
41619. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
41620. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
41621. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
41622. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
41623. DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
41624. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
41625. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
41626. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
41627. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
41628. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
41629. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
41630. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
41631. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
41632. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
41633. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
41634. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
41635. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
41636. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
41637. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
41638. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
41639. DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
41640. DAGB6_WR_TLB_CREDIT__TLB0_MASK
41641. DAGB6_WR_TLB_CREDIT__TLB0__SHIFT
41642. DAGB6_WR_TLB_CREDIT__TLB1_MASK
41643. DAGB6_WR_TLB_CREDIT__TLB1__SHIFT
41644. DAGB6_WR_TLB_CREDIT__TLB2_MASK
41645. DAGB6_WR_TLB_CREDIT__TLB2__SHIFT
41646. DAGB6_WR_TLB_CREDIT__TLB3_MASK
41647. DAGB6_WR_TLB_CREDIT__TLB3__SHIFT
41648. DAGB6_WR_TLB_CREDIT__TLB4_MASK
41649. DAGB6_WR_TLB_CREDIT__TLB4__SHIFT
41650. DAGB6_WR_TLB_CREDIT__TLB5_MASK
41651. DAGB6_WR_TLB_CREDIT__TLB5__SHIFT
41652. DAGB6_WR_VC0_CNTL__EA_CREDIT_MASK
41653. DAGB6_WR_VC0_CNTL__EA_CREDIT__SHIFT
41654. DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
41655. DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
41656. DAGB6_WR_VC0_CNTL__MAX_BW_MASK
41657. DAGB6_WR_VC0_CNTL__MAX_BW__SHIFT
41658. DAGB6_WR_VC0_CNTL__MAX_OSD_MASK
41659. DAGB6_WR_VC0_CNTL__MAX_OSD__SHIFT
41660. DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
41661. DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
41662. DAGB6_WR_VC0_CNTL__MIN_BW_MASK
41663. DAGB6_WR_VC0_CNTL__MIN_BW__SHIFT
41664. DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
41665. DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
41666. DAGB6_WR_VC0_CNTL__STOR_CREDIT_MASK
41667. DAGB6_WR_VC0_CNTL__STOR_CREDIT__SHIFT
41668. DAGB6_WR_VC1_CNTL__EA_CREDIT_MASK
41669. DAGB6_WR_VC1_CNTL__EA_CREDIT__SHIFT
41670. DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
41671. DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
41672. DAGB6_WR_VC1_CNTL__MAX_BW_MASK
41673. DAGB6_WR_VC1_CNTL__MAX_BW__SHIFT
41674. DAGB6_WR_VC1_CNTL__MAX_OSD_MASK
41675. DAGB6_WR_VC1_CNTL__MAX_OSD__SHIFT
41676. DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
41677. DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
41678. DAGB6_WR_VC1_CNTL__MIN_BW_MASK
41679. DAGB6_WR_VC1_CNTL__MIN_BW__SHIFT
41680. DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
41681. DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
41682. DAGB6_WR_VC1_CNTL__STOR_CREDIT_MASK
41683. DAGB6_WR_VC1_CNTL__STOR_CREDIT__SHIFT
41684. DAGB6_WR_VC2_CNTL__EA_CREDIT_MASK
41685. DAGB6_WR_VC2_CNTL__EA_CREDIT__SHIFT
41686. DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
41687. DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
41688. DAGB6_WR_VC2_CNTL__MAX_BW_MASK
41689. DAGB6_WR_VC2_CNTL__MAX_BW__SHIFT
41690. DAGB6_WR_VC2_CNTL__MAX_OSD_MASK
41691. DAGB6_WR_VC2_CNTL__MAX_OSD__SHIFT
41692. DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
41693. DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
41694. DAGB6_WR_VC2_CNTL__MIN_BW_MASK
41695. DAGB6_WR_VC2_CNTL__MIN_BW__SHIFT
41696. DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
41697. DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
41698. DAGB6_WR_VC2_CNTL__STOR_CREDIT_MASK
41699. DAGB6_WR_VC2_CNTL__STOR_CREDIT__SHIFT
41700. DAGB6_WR_VC3_CNTL__EA_CREDIT_MASK
41701. DAGB6_WR_VC3_CNTL__EA_CREDIT__SHIFT
41702. DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
41703. DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
41704. DAGB6_WR_VC3_CNTL__MAX_BW_MASK
41705. DAGB6_WR_VC3_CNTL__MAX_BW__SHIFT
41706. DAGB6_WR_VC3_CNTL__MAX_OSD_MASK
41707. DAGB6_WR_VC3_CNTL__MAX_OSD__SHIFT
41708. DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
41709. DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
41710. DAGB6_WR_VC3_CNTL__MIN_BW_MASK
41711. DAGB6_WR_VC3_CNTL__MIN_BW__SHIFT
41712. DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
41713. DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
41714. DAGB6_WR_VC3_CNTL__STOR_CREDIT_MASK
41715. DAGB6_WR_VC3_CNTL__STOR_CREDIT__SHIFT
41716. DAGB6_WR_VC4_CNTL__EA_CREDIT_MASK
41717. DAGB6_WR_VC4_CNTL__EA_CREDIT__SHIFT
41718. DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
41719. DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
41720. DAGB6_WR_VC4_CNTL__MAX_BW_MASK
41721. DAGB6_WR_VC4_CNTL__MAX_BW__SHIFT
41722. DAGB6_WR_VC4_CNTL__MAX_OSD_MASK
41723. DAGB6_WR_VC4_CNTL__MAX_OSD__SHIFT
41724. DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
41725. DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
41726. DAGB6_WR_VC4_CNTL__MIN_BW_MASK
41727. DAGB6_WR_VC4_CNTL__MIN_BW__SHIFT
41728. DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
41729. DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
41730. DAGB6_WR_VC4_CNTL__STOR_CREDIT_MASK
41731. DAGB6_WR_VC4_CNTL__STOR_CREDIT__SHIFT
41732. DAGB6_WR_VC5_CNTL__EA_CREDIT_MASK
41733. DAGB6_WR_VC5_CNTL__EA_CREDIT__SHIFT
41734. DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
41735. DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
41736. DAGB6_WR_VC5_CNTL__MAX_BW_MASK
41737. DAGB6_WR_VC5_CNTL__MAX_BW__SHIFT
41738. DAGB6_WR_VC5_CNTL__MAX_OSD_MASK
41739. DAGB6_WR_VC5_CNTL__MAX_OSD__SHIFT
41740. DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
41741. DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
41742. DAGB6_WR_VC5_CNTL__MIN_BW_MASK
41743. DAGB6_WR_VC5_CNTL__MIN_BW__SHIFT
41744. DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
41745. DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
41746. DAGB6_WR_VC5_CNTL__STOR_CREDIT_MASK
41747. DAGB6_WR_VC5_CNTL__STOR_CREDIT__SHIFT
41748. DAGB6_WR_VC6_CNTL__EA_CREDIT_MASK
41749. DAGB6_WR_VC6_CNTL__EA_CREDIT__SHIFT
41750. DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
41751. DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
41752. DAGB6_WR_VC6_CNTL__MAX_BW_MASK
41753. DAGB6_WR_VC6_CNTL__MAX_BW__SHIFT
41754. DAGB6_WR_VC6_CNTL__MAX_OSD_MASK
41755. DAGB6_WR_VC6_CNTL__MAX_OSD__SHIFT
41756. DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
41757. DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
41758. DAGB6_WR_VC6_CNTL__MIN_BW_MASK
41759. DAGB6_WR_VC6_CNTL__MIN_BW__SHIFT
41760. DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
41761. DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
41762. DAGB6_WR_VC6_CNTL__STOR_CREDIT_MASK
41763. DAGB6_WR_VC6_CNTL__STOR_CREDIT__SHIFT
41764. DAGB6_WR_VC7_CNTL__EA_CREDIT_MASK
41765. DAGB6_WR_VC7_CNTL__EA_CREDIT__SHIFT
41766. DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
41767. DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
41768. DAGB6_WR_VC7_CNTL__MAX_BW_MASK
41769. DAGB6_WR_VC7_CNTL__MAX_BW__SHIFT
41770. DAGB6_WR_VC7_CNTL__MAX_OSD_MASK
41771. DAGB6_WR_VC7_CNTL__MAX_OSD__SHIFT
41772. DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
41773. DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
41774. DAGB6_WR_VC7_CNTL__MIN_BW_MASK
41775. DAGB6_WR_VC7_CNTL__MIN_BW__SHIFT
41776. DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
41777. DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
41778. DAGB6_WR_VC7_CNTL__STOR_CREDIT_MASK
41779. DAGB6_WR_VC7_CNTL__STOR_CREDIT__SHIFT
41780. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
41781. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
41782. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
41783. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
41784. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
41785. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
41786. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
41787. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
41788. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
41789. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
41790. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
41791. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
41792. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
41793. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
41794. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
41795. DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
41796. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
41797. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
41798. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
41799. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
41800. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
41801. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
41802. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
41803. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
41804. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
41805. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
41806. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
41807. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
41808. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
41809. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
41810. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
41811. DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
41812. DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK
41813. DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT
41814. DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK
41815. DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT
41816. DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
41817. DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT
41818. DAGB7_CNTL_MISC2__DISABLE_RDRET_CG_MASK
41819. DAGB7_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT
41820. DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
41821. DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT
41822. DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
41823. DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT
41824. DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
41825. DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT
41826. DAGB7_CNTL_MISC2__DISABLE_WRRET_CG_MASK
41827. DAGB7_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT
41828. DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK
41829. DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT
41830. DAGB7_CNTL_MISC2__RDRET_FIFO_PERF_MASK
41831. DAGB7_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT
41832. DAGB7_CNTL_MISC2__SWAP_CTL_MASK
41833. DAGB7_CNTL_MISC2__SWAP_CTL__SHIFT
41834. DAGB7_CNTL_MISC2__URG_BOOST_ENABLE_MASK
41835. DAGB7_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT
41836. DAGB7_CNTL_MISC2__URG_HALT_ENABLE_MASK
41837. DAGB7_CNTL_MISC2__URG_HALT_ENABLE__SHIFT
41838. DAGB7_CNTL_MISC__BW_INIT_CYCLE_MASK
41839. DAGB7_CNTL_MISC__BW_INIT_CYCLE__SHIFT
41840. DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE_MASK
41841. DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT
41842. DAGB7_CNTL_MISC__EA_VC0_REMAP_MASK
41843. DAGB7_CNTL_MISC__EA_VC0_REMAP__SHIFT
41844. DAGB7_CNTL_MISC__EA_VC1_REMAP_MASK
41845. DAGB7_CNTL_MISC__EA_VC1_REMAP__SHIFT
41846. DAGB7_CNTL_MISC__EA_VC2_REMAP_MASK
41847. DAGB7_CNTL_MISC__EA_VC2_REMAP__SHIFT
41848. DAGB7_CNTL_MISC__EA_VC3_REMAP_MASK
41849. DAGB7_CNTL_MISC__EA_VC3_REMAP__SHIFT
41850. DAGB7_CNTL_MISC__EA_VC4_REMAP_MASK
41851. DAGB7_CNTL_MISC__EA_VC4_REMAP__SHIFT
41852. DAGB7_CNTL_MISC__EA_VC5_REMAP_MASK
41853. DAGB7_CNTL_MISC__EA_VC5_REMAP__SHIFT
41854. DAGB7_CNTL_MISC__EA_VC6_REMAP_MASK
41855. DAGB7_CNTL_MISC__EA_VC6_REMAP__SHIFT
41856. DAGB7_CNTL_MISC__EA_VC7_REMAP_MASK
41857. DAGB7_CNTL_MISC__EA_VC7_REMAP__SHIFT
41858. DAGB7_DAGB_DLY__CLI_MASK
41859. DAGB7_DAGB_DLY__CLI__SHIFT
41860. DAGB7_DAGB_DLY__DLY_MASK
41861. DAGB7_DAGB_DLY__DLY__SHIFT
41862. DAGB7_DAGB_DLY__POS_MASK
41863. DAGB7_DAGB_DLY__POS__SHIFT
41864. DAGB7_FIFO_EMPTY__EMPTY_MASK
41865. DAGB7_FIFO_EMPTY__EMPTY__SHIFT
41866. DAGB7_FIFO_FULL__FULL_MASK
41867. DAGB7_FIFO_FULL__FULL__SHIFT
41868. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
41869. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
41870. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
41871. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
41872. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
41873. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
41874. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
41875. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
41876. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
41877. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
41878. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
41879. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
41880. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
41881. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
41882. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
41883. DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
41884. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
41885. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
41886. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
41887. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
41888. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
41889. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
41890. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
41891. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
41892. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
41893. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
41894. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
41895. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
41896. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
41897. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
41898. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
41899. DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
41900. DAGB7_PERFCOUNTER0_CFG__CLEAR_MASK
41901. DAGB7_PERFCOUNTER0_CFG__CLEAR__SHIFT
41902. DAGB7_PERFCOUNTER0_CFG__ENABLE_MASK
41903. DAGB7_PERFCOUNTER0_CFG__ENABLE__SHIFT
41904. DAGB7_PERFCOUNTER0_CFG__PERF_MODE_MASK
41905. DAGB7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
41906. DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
41907. DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
41908. DAGB7_PERFCOUNTER0_CFG__PERF_SEL_MASK
41909. DAGB7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
41910. DAGB7_PERFCOUNTER1_CFG__CLEAR_MASK
41911. DAGB7_PERFCOUNTER1_CFG__CLEAR__SHIFT
41912. DAGB7_PERFCOUNTER1_CFG__ENABLE_MASK
41913. DAGB7_PERFCOUNTER1_CFG__ENABLE__SHIFT
41914. DAGB7_PERFCOUNTER1_CFG__PERF_MODE_MASK
41915. DAGB7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
41916. DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
41917. DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
41918. DAGB7_PERFCOUNTER1_CFG__PERF_SEL_MASK
41919. DAGB7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
41920. DAGB7_PERFCOUNTER2_CFG__CLEAR_MASK
41921. DAGB7_PERFCOUNTER2_CFG__CLEAR__SHIFT
41922. DAGB7_PERFCOUNTER2_CFG__ENABLE_MASK
41923. DAGB7_PERFCOUNTER2_CFG__ENABLE__SHIFT
41924. DAGB7_PERFCOUNTER2_CFG__PERF_MODE_MASK
41925. DAGB7_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
41926. DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
41927. DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
41928. DAGB7_PERFCOUNTER2_CFG__PERF_SEL_MASK
41929. DAGB7_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
41930. DAGB7_PERFCOUNTER_HI__COMPARE_VALUE_MASK
41931. DAGB7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
41932. DAGB7_PERFCOUNTER_HI__COUNTER_HI_MASK
41933. DAGB7_PERFCOUNTER_HI__COUNTER_HI__SHIFT
41934. DAGB7_PERFCOUNTER_LO__COUNTER_LO_MASK
41935. DAGB7_PERFCOUNTER_LO__COUNTER_LO__SHIFT
41936. DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
41937. DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
41938. DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
41939. DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
41940. DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
41941. DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
41942. DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
41943. DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
41944. DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
41945. DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
41946. DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
41947. DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
41948. DAGB7_RDCLI0__CHECK_TLB_CREDIT_MASK
41949. DAGB7_RDCLI0__CHECK_TLB_CREDIT__SHIFT
41950. DAGB7_RDCLI0__MAX_BW_ENABLE_MASK
41951. DAGB7_RDCLI0__MAX_BW_ENABLE__SHIFT
41952. DAGB7_RDCLI0__MAX_BW_MASK
41953. DAGB7_RDCLI0__MAX_BW__SHIFT
41954. DAGB7_RDCLI0__MAX_OSD_MASK
41955. DAGB7_RDCLI0__MAX_OSD__SHIFT
41956. DAGB7_RDCLI0__MIN_BW_ENABLE_MASK
41957. DAGB7_RDCLI0__MIN_BW_ENABLE__SHIFT
41958. DAGB7_RDCLI0__MIN_BW_MASK
41959. DAGB7_RDCLI0__MIN_BW__SHIFT
41960. DAGB7_RDCLI0__OSD_LIMITER_ENABLE_MASK
41961. DAGB7_RDCLI0__OSD_LIMITER_ENABLE__SHIFT
41962. DAGB7_RDCLI0__URG_HIGH_MASK
41963. DAGB7_RDCLI0__URG_HIGH__SHIFT
41964. DAGB7_RDCLI0__URG_LOW_MASK
41965. DAGB7_RDCLI0__URG_LOW__SHIFT
41966. DAGB7_RDCLI0__VIRT_CHAN_MASK
41967. DAGB7_RDCLI0__VIRT_CHAN__SHIFT
41968. DAGB7_RDCLI10__CHECK_TLB_CREDIT_MASK
41969. DAGB7_RDCLI10__CHECK_TLB_CREDIT__SHIFT
41970. DAGB7_RDCLI10__MAX_BW_ENABLE_MASK
41971. DAGB7_RDCLI10__MAX_BW_ENABLE__SHIFT
41972. DAGB7_RDCLI10__MAX_BW_MASK
41973. DAGB7_RDCLI10__MAX_BW__SHIFT
41974. DAGB7_RDCLI10__MAX_OSD_MASK
41975. DAGB7_RDCLI10__MAX_OSD__SHIFT
41976. DAGB7_RDCLI10__MIN_BW_ENABLE_MASK
41977. DAGB7_RDCLI10__MIN_BW_ENABLE__SHIFT
41978. DAGB7_RDCLI10__MIN_BW_MASK
41979. DAGB7_RDCLI10__MIN_BW__SHIFT
41980. DAGB7_RDCLI10__OSD_LIMITER_ENABLE_MASK
41981. DAGB7_RDCLI10__OSD_LIMITER_ENABLE__SHIFT
41982. DAGB7_RDCLI10__URG_HIGH_MASK
41983. DAGB7_RDCLI10__URG_HIGH__SHIFT
41984. DAGB7_RDCLI10__URG_LOW_MASK
41985. DAGB7_RDCLI10__URG_LOW__SHIFT
41986. DAGB7_RDCLI10__VIRT_CHAN_MASK
41987. DAGB7_RDCLI10__VIRT_CHAN__SHIFT
41988. DAGB7_RDCLI11__CHECK_TLB_CREDIT_MASK
41989. DAGB7_RDCLI11__CHECK_TLB_CREDIT__SHIFT
41990. DAGB7_RDCLI11__MAX_BW_ENABLE_MASK
41991. DAGB7_RDCLI11__MAX_BW_ENABLE__SHIFT
41992. DAGB7_RDCLI11__MAX_BW_MASK
41993. DAGB7_RDCLI11__MAX_BW__SHIFT
41994. DAGB7_RDCLI11__MAX_OSD_MASK
41995. DAGB7_RDCLI11__MAX_OSD__SHIFT
41996. DAGB7_RDCLI11__MIN_BW_ENABLE_MASK
41997. DAGB7_RDCLI11__MIN_BW_ENABLE__SHIFT
41998. DAGB7_RDCLI11__MIN_BW_MASK
41999. DAGB7_RDCLI11__MIN_BW__SHIFT
42000. DAGB7_RDCLI11__OSD_LIMITER_ENABLE_MASK
42001. DAGB7_RDCLI11__OSD_LIMITER_ENABLE__SHIFT
42002. DAGB7_RDCLI11__URG_HIGH_MASK
42003. DAGB7_RDCLI11__URG_HIGH__SHIFT
42004. DAGB7_RDCLI11__URG_LOW_MASK
42005. DAGB7_RDCLI11__URG_LOW__SHIFT
42006. DAGB7_RDCLI11__VIRT_CHAN_MASK
42007. DAGB7_RDCLI11__VIRT_CHAN__SHIFT
42008. DAGB7_RDCLI12__CHECK_TLB_CREDIT_MASK
42009. DAGB7_RDCLI12__CHECK_TLB_CREDIT__SHIFT
42010. DAGB7_RDCLI12__MAX_BW_ENABLE_MASK
42011. DAGB7_RDCLI12__MAX_BW_ENABLE__SHIFT
42012. DAGB7_RDCLI12__MAX_BW_MASK
42013. DAGB7_RDCLI12__MAX_BW__SHIFT
42014. DAGB7_RDCLI12__MAX_OSD_MASK
42015. DAGB7_RDCLI12__MAX_OSD__SHIFT
42016. DAGB7_RDCLI12__MIN_BW_ENABLE_MASK
42017. DAGB7_RDCLI12__MIN_BW_ENABLE__SHIFT
42018. DAGB7_RDCLI12__MIN_BW_MASK
42019. DAGB7_RDCLI12__MIN_BW__SHIFT
42020. DAGB7_RDCLI12__OSD_LIMITER_ENABLE_MASK
42021. DAGB7_RDCLI12__OSD_LIMITER_ENABLE__SHIFT
42022. DAGB7_RDCLI12__URG_HIGH_MASK
42023. DAGB7_RDCLI12__URG_HIGH__SHIFT
42024. DAGB7_RDCLI12__URG_LOW_MASK
42025. DAGB7_RDCLI12__URG_LOW__SHIFT
42026. DAGB7_RDCLI12__VIRT_CHAN_MASK
42027. DAGB7_RDCLI12__VIRT_CHAN__SHIFT
42028. DAGB7_RDCLI13__CHECK_TLB_CREDIT_MASK
42029. DAGB7_RDCLI13__CHECK_TLB_CREDIT__SHIFT
42030. DAGB7_RDCLI13__MAX_BW_ENABLE_MASK
42031. DAGB7_RDCLI13__MAX_BW_ENABLE__SHIFT
42032. DAGB7_RDCLI13__MAX_BW_MASK
42033. DAGB7_RDCLI13__MAX_BW__SHIFT
42034. DAGB7_RDCLI13__MAX_OSD_MASK
42035. DAGB7_RDCLI13__MAX_OSD__SHIFT
42036. DAGB7_RDCLI13__MIN_BW_ENABLE_MASK
42037. DAGB7_RDCLI13__MIN_BW_ENABLE__SHIFT
42038. DAGB7_RDCLI13__MIN_BW_MASK
42039. DAGB7_RDCLI13__MIN_BW__SHIFT
42040. DAGB7_RDCLI13__OSD_LIMITER_ENABLE_MASK
42041. DAGB7_RDCLI13__OSD_LIMITER_ENABLE__SHIFT
42042. DAGB7_RDCLI13__URG_HIGH_MASK
42043. DAGB7_RDCLI13__URG_HIGH__SHIFT
42044. DAGB7_RDCLI13__URG_LOW_MASK
42045. DAGB7_RDCLI13__URG_LOW__SHIFT
42046. DAGB7_RDCLI13__VIRT_CHAN_MASK
42047. DAGB7_RDCLI13__VIRT_CHAN__SHIFT
42048. DAGB7_RDCLI14__CHECK_TLB_CREDIT_MASK
42049. DAGB7_RDCLI14__CHECK_TLB_CREDIT__SHIFT
42050. DAGB7_RDCLI14__MAX_BW_ENABLE_MASK
42051. DAGB7_RDCLI14__MAX_BW_ENABLE__SHIFT
42052. DAGB7_RDCLI14__MAX_BW_MASK
42053. DAGB7_RDCLI14__MAX_BW__SHIFT
42054. DAGB7_RDCLI14__MAX_OSD_MASK
42055. DAGB7_RDCLI14__MAX_OSD__SHIFT
42056. DAGB7_RDCLI14__MIN_BW_ENABLE_MASK
42057. DAGB7_RDCLI14__MIN_BW_ENABLE__SHIFT
42058. DAGB7_RDCLI14__MIN_BW_MASK
42059. DAGB7_RDCLI14__MIN_BW__SHIFT
42060. DAGB7_RDCLI14__OSD_LIMITER_ENABLE_MASK
42061. DAGB7_RDCLI14__OSD_LIMITER_ENABLE__SHIFT
42062. DAGB7_RDCLI14__URG_HIGH_MASK
42063. DAGB7_RDCLI14__URG_HIGH__SHIFT
42064. DAGB7_RDCLI14__URG_LOW_MASK
42065. DAGB7_RDCLI14__URG_LOW__SHIFT
42066. DAGB7_RDCLI14__VIRT_CHAN_MASK
42067. DAGB7_RDCLI14__VIRT_CHAN__SHIFT
42068. DAGB7_RDCLI15__CHECK_TLB_CREDIT_MASK
42069. DAGB7_RDCLI15__CHECK_TLB_CREDIT__SHIFT
42070. DAGB7_RDCLI15__MAX_BW_ENABLE_MASK
42071. DAGB7_RDCLI15__MAX_BW_ENABLE__SHIFT
42072. DAGB7_RDCLI15__MAX_BW_MASK
42073. DAGB7_RDCLI15__MAX_BW__SHIFT
42074. DAGB7_RDCLI15__MAX_OSD_MASK
42075. DAGB7_RDCLI15__MAX_OSD__SHIFT
42076. DAGB7_RDCLI15__MIN_BW_ENABLE_MASK
42077. DAGB7_RDCLI15__MIN_BW_ENABLE__SHIFT
42078. DAGB7_RDCLI15__MIN_BW_MASK
42079. DAGB7_RDCLI15__MIN_BW__SHIFT
42080. DAGB7_RDCLI15__OSD_LIMITER_ENABLE_MASK
42081. DAGB7_RDCLI15__OSD_LIMITER_ENABLE__SHIFT
42082. DAGB7_RDCLI15__URG_HIGH_MASK
42083. DAGB7_RDCLI15__URG_HIGH__SHIFT
42084. DAGB7_RDCLI15__URG_LOW_MASK
42085. DAGB7_RDCLI15__URG_LOW__SHIFT
42086. DAGB7_RDCLI15__VIRT_CHAN_MASK
42087. DAGB7_RDCLI15__VIRT_CHAN__SHIFT
42088. DAGB7_RDCLI1__CHECK_TLB_CREDIT_MASK
42089. DAGB7_RDCLI1__CHECK_TLB_CREDIT__SHIFT
42090. DAGB7_RDCLI1__MAX_BW_ENABLE_MASK
42091. DAGB7_RDCLI1__MAX_BW_ENABLE__SHIFT
42092. DAGB7_RDCLI1__MAX_BW_MASK
42093. DAGB7_RDCLI1__MAX_BW__SHIFT
42094. DAGB7_RDCLI1__MAX_OSD_MASK
42095. DAGB7_RDCLI1__MAX_OSD__SHIFT
42096. DAGB7_RDCLI1__MIN_BW_ENABLE_MASK
42097. DAGB7_RDCLI1__MIN_BW_ENABLE__SHIFT
42098. DAGB7_RDCLI1__MIN_BW_MASK
42099. DAGB7_RDCLI1__MIN_BW__SHIFT
42100. DAGB7_RDCLI1__OSD_LIMITER_ENABLE_MASK
42101. DAGB7_RDCLI1__OSD_LIMITER_ENABLE__SHIFT
42102. DAGB7_RDCLI1__URG_HIGH_MASK
42103. DAGB7_RDCLI1__URG_HIGH__SHIFT
42104. DAGB7_RDCLI1__URG_LOW_MASK
42105. DAGB7_RDCLI1__URG_LOW__SHIFT
42106. DAGB7_RDCLI1__VIRT_CHAN_MASK
42107. DAGB7_RDCLI1__VIRT_CHAN__SHIFT
42108. DAGB7_RDCLI2__CHECK_TLB_CREDIT_MASK
42109. DAGB7_RDCLI2__CHECK_TLB_CREDIT__SHIFT
42110. DAGB7_RDCLI2__MAX_BW_ENABLE_MASK
42111. DAGB7_RDCLI2__MAX_BW_ENABLE__SHIFT
42112. DAGB7_RDCLI2__MAX_BW_MASK
42113. DAGB7_RDCLI2__MAX_BW__SHIFT
42114. DAGB7_RDCLI2__MAX_OSD_MASK
42115. DAGB7_RDCLI2__MAX_OSD__SHIFT
42116. DAGB7_RDCLI2__MIN_BW_ENABLE_MASK
42117. DAGB7_RDCLI2__MIN_BW_ENABLE__SHIFT
42118. DAGB7_RDCLI2__MIN_BW_MASK
42119. DAGB7_RDCLI2__MIN_BW__SHIFT
42120. DAGB7_RDCLI2__OSD_LIMITER_ENABLE_MASK
42121. DAGB7_RDCLI2__OSD_LIMITER_ENABLE__SHIFT
42122. DAGB7_RDCLI2__URG_HIGH_MASK
42123. DAGB7_RDCLI2__URG_HIGH__SHIFT
42124. DAGB7_RDCLI2__URG_LOW_MASK
42125. DAGB7_RDCLI2__URG_LOW__SHIFT
42126. DAGB7_RDCLI2__VIRT_CHAN_MASK
42127. DAGB7_RDCLI2__VIRT_CHAN__SHIFT
42128. DAGB7_RDCLI3__CHECK_TLB_CREDIT_MASK
42129. DAGB7_RDCLI3__CHECK_TLB_CREDIT__SHIFT
42130. DAGB7_RDCLI3__MAX_BW_ENABLE_MASK
42131. DAGB7_RDCLI3__MAX_BW_ENABLE__SHIFT
42132. DAGB7_RDCLI3__MAX_BW_MASK
42133. DAGB7_RDCLI3__MAX_BW__SHIFT
42134. DAGB7_RDCLI3__MAX_OSD_MASK
42135. DAGB7_RDCLI3__MAX_OSD__SHIFT
42136. DAGB7_RDCLI3__MIN_BW_ENABLE_MASK
42137. DAGB7_RDCLI3__MIN_BW_ENABLE__SHIFT
42138. DAGB7_RDCLI3__MIN_BW_MASK
42139. DAGB7_RDCLI3__MIN_BW__SHIFT
42140. DAGB7_RDCLI3__OSD_LIMITER_ENABLE_MASK
42141. DAGB7_RDCLI3__OSD_LIMITER_ENABLE__SHIFT
42142. DAGB7_RDCLI3__URG_HIGH_MASK
42143. DAGB7_RDCLI3__URG_HIGH__SHIFT
42144. DAGB7_RDCLI3__URG_LOW_MASK
42145. DAGB7_RDCLI3__URG_LOW__SHIFT
42146. DAGB7_RDCLI3__VIRT_CHAN_MASK
42147. DAGB7_RDCLI3__VIRT_CHAN__SHIFT
42148. DAGB7_RDCLI4__CHECK_TLB_CREDIT_MASK
42149. DAGB7_RDCLI4__CHECK_TLB_CREDIT__SHIFT
42150. DAGB7_RDCLI4__MAX_BW_ENABLE_MASK
42151. DAGB7_RDCLI4__MAX_BW_ENABLE__SHIFT
42152. DAGB7_RDCLI4__MAX_BW_MASK
42153. DAGB7_RDCLI4__MAX_BW__SHIFT
42154. DAGB7_RDCLI4__MAX_OSD_MASK
42155. DAGB7_RDCLI4__MAX_OSD__SHIFT
42156. DAGB7_RDCLI4__MIN_BW_ENABLE_MASK
42157. DAGB7_RDCLI4__MIN_BW_ENABLE__SHIFT
42158. DAGB7_RDCLI4__MIN_BW_MASK
42159. DAGB7_RDCLI4__MIN_BW__SHIFT
42160. DAGB7_RDCLI4__OSD_LIMITER_ENABLE_MASK
42161. DAGB7_RDCLI4__OSD_LIMITER_ENABLE__SHIFT
42162. DAGB7_RDCLI4__URG_HIGH_MASK
42163. DAGB7_RDCLI4__URG_HIGH__SHIFT
42164. DAGB7_RDCLI4__URG_LOW_MASK
42165. DAGB7_RDCLI4__URG_LOW__SHIFT
42166. DAGB7_RDCLI4__VIRT_CHAN_MASK
42167. DAGB7_RDCLI4__VIRT_CHAN__SHIFT
42168. DAGB7_RDCLI5__CHECK_TLB_CREDIT_MASK
42169. DAGB7_RDCLI5__CHECK_TLB_CREDIT__SHIFT
42170. DAGB7_RDCLI5__MAX_BW_ENABLE_MASK
42171. DAGB7_RDCLI5__MAX_BW_ENABLE__SHIFT
42172. DAGB7_RDCLI5__MAX_BW_MASK
42173. DAGB7_RDCLI5__MAX_BW__SHIFT
42174. DAGB7_RDCLI5__MAX_OSD_MASK
42175. DAGB7_RDCLI5__MAX_OSD__SHIFT
42176. DAGB7_RDCLI5__MIN_BW_ENABLE_MASK
42177. DAGB7_RDCLI5__MIN_BW_ENABLE__SHIFT
42178. DAGB7_RDCLI5__MIN_BW_MASK
42179. DAGB7_RDCLI5__MIN_BW__SHIFT
42180. DAGB7_RDCLI5__OSD_LIMITER_ENABLE_MASK
42181. DAGB7_RDCLI5__OSD_LIMITER_ENABLE__SHIFT
42182. DAGB7_RDCLI5__URG_HIGH_MASK
42183. DAGB7_RDCLI5__URG_HIGH__SHIFT
42184. DAGB7_RDCLI5__URG_LOW_MASK
42185. DAGB7_RDCLI5__URG_LOW__SHIFT
42186. DAGB7_RDCLI5__VIRT_CHAN_MASK
42187. DAGB7_RDCLI5__VIRT_CHAN__SHIFT
42188. DAGB7_RDCLI6__CHECK_TLB_CREDIT_MASK
42189. DAGB7_RDCLI6__CHECK_TLB_CREDIT__SHIFT
42190. DAGB7_RDCLI6__MAX_BW_ENABLE_MASK
42191. DAGB7_RDCLI6__MAX_BW_ENABLE__SHIFT
42192. DAGB7_RDCLI6__MAX_BW_MASK
42193. DAGB7_RDCLI6__MAX_BW__SHIFT
42194. DAGB7_RDCLI6__MAX_OSD_MASK
42195. DAGB7_RDCLI6__MAX_OSD__SHIFT
42196. DAGB7_RDCLI6__MIN_BW_ENABLE_MASK
42197. DAGB7_RDCLI6__MIN_BW_ENABLE__SHIFT
42198. DAGB7_RDCLI6__MIN_BW_MASK
42199. DAGB7_RDCLI6__MIN_BW__SHIFT
42200. DAGB7_RDCLI6__OSD_LIMITER_ENABLE_MASK
42201. DAGB7_RDCLI6__OSD_LIMITER_ENABLE__SHIFT
42202. DAGB7_RDCLI6__URG_HIGH_MASK
42203. DAGB7_RDCLI6__URG_HIGH__SHIFT
42204. DAGB7_RDCLI6__URG_LOW_MASK
42205. DAGB7_RDCLI6__URG_LOW__SHIFT
42206. DAGB7_RDCLI6__VIRT_CHAN_MASK
42207. DAGB7_RDCLI6__VIRT_CHAN__SHIFT
42208. DAGB7_RDCLI7__CHECK_TLB_CREDIT_MASK
42209. DAGB7_RDCLI7__CHECK_TLB_CREDIT__SHIFT
42210. DAGB7_RDCLI7__MAX_BW_ENABLE_MASK
42211. DAGB7_RDCLI7__MAX_BW_ENABLE__SHIFT
42212. DAGB7_RDCLI7__MAX_BW_MASK
42213. DAGB7_RDCLI7__MAX_BW__SHIFT
42214. DAGB7_RDCLI7__MAX_OSD_MASK
42215. DAGB7_RDCLI7__MAX_OSD__SHIFT
42216. DAGB7_RDCLI7__MIN_BW_ENABLE_MASK
42217. DAGB7_RDCLI7__MIN_BW_ENABLE__SHIFT
42218. DAGB7_RDCLI7__MIN_BW_MASK
42219. DAGB7_RDCLI7__MIN_BW__SHIFT
42220. DAGB7_RDCLI7__OSD_LIMITER_ENABLE_MASK
42221. DAGB7_RDCLI7__OSD_LIMITER_ENABLE__SHIFT
42222. DAGB7_RDCLI7__URG_HIGH_MASK
42223. DAGB7_RDCLI7__URG_HIGH__SHIFT
42224. DAGB7_RDCLI7__URG_LOW_MASK
42225. DAGB7_RDCLI7__URG_LOW__SHIFT
42226. DAGB7_RDCLI7__VIRT_CHAN_MASK
42227. DAGB7_RDCLI7__VIRT_CHAN__SHIFT
42228. DAGB7_RDCLI8__CHECK_TLB_CREDIT_MASK
42229. DAGB7_RDCLI8__CHECK_TLB_CREDIT__SHIFT
42230. DAGB7_RDCLI8__MAX_BW_ENABLE_MASK
42231. DAGB7_RDCLI8__MAX_BW_ENABLE__SHIFT
42232. DAGB7_RDCLI8__MAX_BW_MASK
42233. DAGB7_RDCLI8__MAX_BW__SHIFT
42234. DAGB7_RDCLI8__MAX_OSD_MASK
42235. DAGB7_RDCLI8__MAX_OSD__SHIFT
42236. DAGB7_RDCLI8__MIN_BW_ENABLE_MASK
42237. DAGB7_RDCLI8__MIN_BW_ENABLE__SHIFT
42238. DAGB7_RDCLI8__MIN_BW_MASK
42239. DAGB7_RDCLI8__MIN_BW__SHIFT
42240. DAGB7_RDCLI8__OSD_LIMITER_ENABLE_MASK
42241. DAGB7_RDCLI8__OSD_LIMITER_ENABLE__SHIFT
42242. DAGB7_RDCLI8__URG_HIGH_MASK
42243. DAGB7_RDCLI8__URG_HIGH__SHIFT
42244. DAGB7_RDCLI8__URG_LOW_MASK
42245. DAGB7_RDCLI8__URG_LOW__SHIFT
42246. DAGB7_RDCLI8__VIRT_CHAN_MASK
42247. DAGB7_RDCLI8__VIRT_CHAN__SHIFT
42248. DAGB7_RDCLI9__CHECK_TLB_CREDIT_MASK
42249. DAGB7_RDCLI9__CHECK_TLB_CREDIT__SHIFT
42250. DAGB7_RDCLI9__MAX_BW_ENABLE_MASK
42251. DAGB7_RDCLI9__MAX_BW_ENABLE__SHIFT
42252. DAGB7_RDCLI9__MAX_BW_MASK
42253. DAGB7_RDCLI9__MAX_BW__SHIFT
42254. DAGB7_RDCLI9__MAX_OSD_MASK
42255. DAGB7_RDCLI9__MAX_OSD__SHIFT
42256. DAGB7_RDCLI9__MIN_BW_ENABLE_MASK
42257. DAGB7_RDCLI9__MIN_BW_ENABLE__SHIFT
42258. DAGB7_RDCLI9__MIN_BW_MASK
42259. DAGB7_RDCLI9__MIN_BW__SHIFT
42260. DAGB7_RDCLI9__OSD_LIMITER_ENABLE_MASK
42261. DAGB7_RDCLI9__OSD_LIMITER_ENABLE__SHIFT
42262. DAGB7_RDCLI9__URG_HIGH_MASK
42263. DAGB7_RDCLI9__URG_HIGH__SHIFT
42264. DAGB7_RDCLI9__URG_LOW_MASK
42265. DAGB7_RDCLI9__URG_LOW__SHIFT
42266. DAGB7_RDCLI9__VIRT_CHAN_MASK
42267. DAGB7_RDCLI9__VIRT_CHAN__SHIFT
42268. DAGB7_RDCLI_ASK_PENDING__BUSY_MASK
42269. DAGB7_RDCLI_ASK_PENDING__BUSY__SHIFT
42270. DAGB7_RDCLI_GBLSEND_PENDING__BUSY_MASK
42271. DAGB7_RDCLI_GBLSEND_PENDING__BUSY__SHIFT
42272. DAGB7_RDCLI_GO_PENDING__BUSY_MASK
42273. DAGB7_RDCLI_GO_PENDING__BUSY__SHIFT
42274. DAGB7_RDCLI_OARB_PENDING__BUSY_MASK
42275. DAGB7_RDCLI_OARB_PENDING__BUSY__SHIFT
42276. DAGB7_RDCLI_OSD_PENDING__BUSY_MASK
42277. DAGB7_RDCLI_OSD_PENDING__BUSY__SHIFT
42278. DAGB7_RDCLI_TLB_PENDING__BUSY_MASK
42279. DAGB7_RDCLI_TLB_PENDING__BUSY__SHIFT
42280. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
42281. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
42282. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
42283. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
42284. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
42285. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
42286. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
42287. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
42288. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
42289. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
42290. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
42291. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
42292. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
42293. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
42294. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
42295. DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
42296. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
42297. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
42298. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
42299. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
42300. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
42301. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
42302. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
42303. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
42304. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
42305. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
42306. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
42307. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
42308. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
42309. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
42310. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
42311. DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
42312. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
42313. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
42314. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
42315. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
42316. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
42317. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
42318. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
42319. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
42320. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
42321. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
42322. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
42323. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
42324. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
42325. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
42326. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
42327. DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
42328. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
42329. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
42330. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
42331. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
42332. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
42333. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
42334. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
42335. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
42336. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
42337. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
42338. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
42339. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
42340. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
42341. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
42342. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
42343. DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
42344. DAGB7_RD_ADDR_DAGB__DAGB_ENABLE_MASK
42345. DAGB7_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT
42346. DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK
42347. DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
42348. DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
42349. DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
42350. DAGB7_RD_ADDR_DAGB__WHOAMI_MASK
42351. DAGB7_RD_ADDR_DAGB__WHOAMI__SHIFT
42352. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
42353. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
42354. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
42355. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
42356. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
42357. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
42358. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
42359. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
42360. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
42361. DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
42362. DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
42363. DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
42364. DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY_MASK
42365. DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT
42366. DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
42367. DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
42368. DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
42369. DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
42370. DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT_MASK
42371. DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT
42372. DAGB7_RD_CNTL_MISC__IO_EA_CREDIT_MASK
42373. DAGB7_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT
42374. DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
42375. DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
42376. DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
42377. DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
42378. DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK
42379. DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
42380. DAGB7_RD_CNTL_MISC__UTCL2_CID_MASK
42381. DAGB7_RD_CNTL_MISC__UTCL2_CID__SHIFT
42382. DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW_MASK
42383. DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT
42384. DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK
42385. DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
42386. DAGB7_RD_CNTL__IO_LEVEL_MASK
42387. DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
42388. DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
42389. DAGB7_RD_CNTL__IO_LEVEL__SHIFT
42390. DAGB7_RD_CNTL__SCLK_FREQ_MASK
42391. DAGB7_RD_CNTL__SCLK_FREQ__SHIFT
42392. DAGB7_RD_CNTL__SHARE_VC_NUM_MASK
42393. DAGB7_RD_CNTL__SHARE_VC_NUM__SHIFT
42394. DAGB7_RD_CNTL__VC_MAX_BW_WINDOW_MASK
42395. DAGB7_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT
42396. DAGB7_RD_CREDITS_FULL__FULL_MASK
42397. DAGB7_RD_CREDITS_FULL__FULL__SHIFT
42398. DAGB7_RD_GMI_CNTL__EA_CREDIT_MASK
42399. DAGB7_RD_GMI_CNTL__EA_CREDIT__SHIFT
42400. DAGB7_RD_GMI_CNTL__LAZY_TIMER_MASK
42401. DAGB7_RD_GMI_CNTL__LAZY_TIMER__SHIFT
42402. DAGB7_RD_GMI_CNTL__LEVEL_MASK
42403. DAGB7_RD_GMI_CNTL__LEVEL__SHIFT
42404. DAGB7_RD_GMI_CNTL__MAX_BURST_MASK
42405. DAGB7_RD_GMI_CNTL__MAX_BURST__SHIFT
42406. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
42407. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
42408. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
42409. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
42410. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
42411. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
42412. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
42413. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
42414. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
42415. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
42416. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
42417. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
42418. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
42419. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
42420. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
42421. DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
42422. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK
42423. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
42424. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK
42425. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
42426. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK
42427. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
42428. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK
42429. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
42430. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK
42431. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
42432. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK
42433. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
42434. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK
42435. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
42436. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK
42437. DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
42438. DAGB7_RD_TLB_CREDIT__TLB0_MASK
42439. DAGB7_RD_TLB_CREDIT__TLB0__SHIFT
42440. DAGB7_RD_TLB_CREDIT__TLB1_MASK
42441. DAGB7_RD_TLB_CREDIT__TLB1__SHIFT
42442. DAGB7_RD_TLB_CREDIT__TLB2_MASK
42443. DAGB7_RD_TLB_CREDIT__TLB2__SHIFT
42444. DAGB7_RD_TLB_CREDIT__TLB3_MASK
42445. DAGB7_RD_TLB_CREDIT__TLB3__SHIFT
42446. DAGB7_RD_TLB_CREDIT__TLB4_MASK
42447. DAGB7_RD_TLB_CREDIT__TLB4__SHIFT
42448. DAGB7_RD_TLB_CREDIT__TLB5_MASK
42449. DAGB7_RD_TLB_CREDIT__TLB5__SHIFT
42450. DAGB7_RD_VC0_CNTL__EA_CREDIT_MASK
42451. DAGB7_RD_VC0_CNTL__EA_CREDIT__SHIFT
42452. DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE_MASK
42453. DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT
42454. DAGB7_RD_VC0_CNTL__MAX_BW_MASK
42455. DAGB7_RD_VC0_CNTL__MAX_BW__SHIFT
42456. DAGB7_RD_VC0_CNTL__MAX_OSD_MASK
42457. DAGB7_RD_VC0_CNTL__MAX_OSD__SHIFT
42458. DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE_MASK
42459. DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT
42460. DAGB7_RD_VC0_CNTL__MIN_BW_MASK
42461. DAGB7_RD_VC0_CNTL__MIN_BW__SHIFT
42462. DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
42463. DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
42464. DAGB7_RD_VC0_CNTL__STOR_CREDIT_MASK
42465. DAGB7_RD_VC0_CNTL__STOR_CREDIT__SHIFT
42466. DAGB7_RD_VC1_CNTL__EA_CREDIT_MASK
42467. DAGB7_RD_VC1_CNTL__EA_CREDIT__SHIFT
42468. DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE_MASK
42469. DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT
42470. DAGB7_RD_VC1_CNTL__MAX_BW_MASK
42471. DAGB7_RD_VC1_CNTL__MAX_BW__SHIFT
42472. DAGB7_RD_VC1_CNTL__MAX_OSD_MASK
42473. DAGB7_RD_VC1_CNTL__MAX_OSD__SHIFT
42474. DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE_MASK
42475. DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT
42476. DAGB7_RD_VC1_CNTL__MIN_BW_MASK
42477. DAGB7_RD_VC1_CNTL__MIN_BW__SHIFT
42478. DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
42479. DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
42480. DAGB7_RD_VC1_CNTL__STOR_CREDIT_MASK
42481. DAGB7_RD_VC1_CNTL__STOR_CREDIT__SHIFT
42482. DAGB7_RD_VC2_CNTL__EA_CREDIT_MASK
42483. DAGB7_RD_VC2_CNTL__EA_CREDIT__SHIFT
42484. DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE_MASK
42485. DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT
42486. DAGB7_RD_VC2_CNTL__MAX_BW_MASK
42487. DAGB7_RD_VC2_CNTL__MAX_BW__SHIFT
42488. DAGB7_RD_VC2_CNTL__MAX_OSD_MASK
42489. DAGB7_RD_VC2_CNTL__MAX_OSD__SHIFT
42490. DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE_MASK
42491. DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT
42492. DAGB7_RD_VC2_CNTL__MIN_BW_MASK
42493. DAGB7_RD_VC2_CNTL__MIN_BW__SHIFT
42494. DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
42495. DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
42496. DAGB7_RD_VC2_CNTL__STOR_CREDIT_MASK
42497. DAGB7_RD_VC2_CNTL__STOR_CREDIT__SHIFT
42498. DAGB7_RD_VC3_CNTL__EA_CREDIT_MASK
42499. DAGB7_RD_VC3_CNTL__EA_CREDIT__SHIFT
42500. DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE_MASK
42501. DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT
42502. DAGB7_RD_VC3_CNTL__MAX_BW_MASK
42503. DAGB7_RD_VC3_CNTL__MAX_BW__SHIFT
42504. DAGB7_RD_VC3_CNTL__MAX_OSD_MASK
42505. DAGB7_RD_VC3_CNTL__MAX_OSD__SHIFT
42506. DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE_MASK
42507. DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT
42508. DAGB7_RD_VC3_CNTL__MIN_BW_MASK
42509. DAGB7_RD_VC3_CNTL__MIN_BW__SHIFT
42510. DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
42511. DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
42512. DAGB7_RD_VC3_CNTL__STOR_CREDIT_MASK
42513. DAGB7_RD_VC3_CNTL__STOR_CREDIT__SHIFT
42514. DAGB7_RD_VC4_CNTL__EA_CREDIT_MASK
42515. DAGB7_RD_VC4_CNTL__EA_CREDIT__SHIFT
42516. DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE_MASK
42517. DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT
42518. DAGB7_RD_VC4_CNTL__MAX_BW_MASK
42519. DAGB7_RD_VC4_CNTL__MAX_BW__SHIFT
42520. DAGB7_RD_VC4_CNTL__MAX_OSD_MASK
42521. DAGB7_RD_VC4_CNTL__MAX_OSD__SHIFT
42522. DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE_MASK
42523. DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT
42524. DAGB7_RD_VC4_CNTL__MIN_BW_MASK
42525. DAGB7_RD_VC4_CNTL__MIN_BW__SHIFT
42526. DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
42527. DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
42528. DAGB7_RD_VC4_CNTL__STOR_CREDIT_MASK
42529. DAGB7_RD_VC4_CNTL__STOR_CREDIT__SHIFT
42530. DAGB7_RD_VC5_CNTL__EA_CREDIT_MASK
42531. DAGB7_RD_VC5_CNTL__EA_CREDIT__SHIFT
42532. DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE_MASK
42533. DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT
42534. DAGB7_RD_VC5_CNTL__MAX_BW_MASK
42535. DAGB7_RD_VC5_CNTL__MAX_BW__SHIFT
42536. DAGB7_RD_VC5_CNTL__MAX_OSD_MASK
42537. DAGB7_RD_VC5_CNTL__MAX_OSD__SHIFT
42538. DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE_MASK
42539. DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT
42540. DAGB7_RD_VC5_CNTL__MIN_BW_MASK
42541. DAGB7_RD_VC5_CNTL__MIN_BW__SHIFT
42542. DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
42543. DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
42544. DAGB7_RD_VC5_CNTL__STOR_CREDIT_MASK
42545. DAGB7_RD_VC5_CNTL__STOR_CREDIT__SHIFT
42546. DAGB7_RD_VC6_CNTL__EA_CREDIT_MASK
42547. DAGB7_RD_VC6_CNTL__EA_CREDIT__SHIFT
42548. DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE_MASK
42549. DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT
42550. DAGB7_RD_VC6_CNTL__MAX_BW_MASK
42551. DAGB7_RD_VC6_CNTL__MAX_BW__SHIFT
42552. DAGB7_RD_VC6_CNTL__MAX_OSD_MASK
42553. DAGB7_RD_VC6_CNTL__MAX_OSD__SHIFT
42554. DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE_MASK
42555. DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT
42556. DAGB7_RD_VC6_CNTL__MIN_BW_MASK
42557. DAGB7_RD_VC6_CNTL__MIN_BW__SHIFT
42558. DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
42559. DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
42560. DAGB7_RD_VC6_CNTL__STOR_CREDIT_MASK
42561. DAGB7_RD_VC6_CNTL__STOR_CREDIT__SHIFT
42562. DAGB7_RD_VC7_CNTL__EA_CREDIT_MASK
42563. DAGB7_RD_VC7_CNTL__EA_CREDIT__SHIFT
42564. DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE_MASK
42565. DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT
42566. DAGB7_RD_VC7_CNTL__MAX_BW_MASK
42567. DAGB7_RD_VC7_CNTL__MAX_BW__SHIFT
42568. DAGB7_RD_VC7_CNTL__MAX_OSD_MASK
42569. DAGB7_RD_VC7_CNTL__MAX_OSD__SHIFT
42570. DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE_MASK
42571. DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT
42572. DAGB7_RD_VC7_CNTL__MIN_BW_MASK
42573. DAGB7_RD_VC7_CNTL__MIN_BW__SHIFT
42574. DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
42575. DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
42576. DAGB7_RD_VC7_CNTL__STOR_CREDIT_MASK
42577. DAGB7_RD_VC7_CNTL__STOR_CREDIT__SHIFT
42578. DAGB7_RESERVE0__RESERVE_MASK
42579. DAGB7_RESERVE0__RESERVE__SHIFT
42580. DAGB7_RESERVE10__RESERVE_MASK
42581. DAGB7_RESERVE10__RESERVE__SHIFT
42582. DAGB7_RESERVE11__RESERVE_MASK
42583. DAGB7_RESERVE11__RESERVE__SHIFT
42584. DAGB7_RESERVE12__RESERVE_MASK
42585. DAGB7_RESERVE12__RESERVE__SHIFT
42586. DAGB7_RESERVE13__RESERVE_MASK
42587. DAGB7_RESERVE13__RESERVE__SHIFT
42588. DAGB7_RESERVE1__RESERVE_MASK
42589. DAGB7_RESERVE1__RESERVE__SHIFT
42590. DAGB7_RESERVE2__RESERVE_MASK
42591. DAGB7_RESERVE2__RESERVE__SHIFT
42592. DAGB7_RESERVE3__RESERVE_MASK
42593. DAGB7_RESERVE3__RESERVE__SHIFT
42594. DAGB7_RESERVE4__RESERVE_MASK
42595. DAGB7_RESERVE4__RESERVE__SHIFT
42596. DAGB7_RESERVE5__RESERVE_MASK
42597. DAGB7_RESERVE5__RESERVE__SHIFT
42598. DAGB7_RESERVE6__RESERVE_MASK
42599. DAGB7_RESERVE6__RESERVE__SHIFT
42600. DAGB7_RESERVE7__RESERVE_MASK
42601. DAGB7_RESERVE7__RESERVE__SHIFT
42602. DAGB7_RESERVE8__RESERVE_MASK
42603. DAGB7_RESERVE8__RESERVE__SHIFT
42604. DAGB7_RESERVE9__RESERVE_MASK
42605. DAGB7_RESERVE9__RESERVE__SHIFT
42606. DAGB7_WRCLI0__CHECK_TLB_CREDIT_MASK
42607. DAGB7_WRCLI0__CHECK_TLB_CREDIT__SHIFT
42608. DAGB7_WRCLI0__MAX_BW_ENABLE_MASK
42609. DAGB7_WRCLI0__MAX_BW_ENABLE__SHIFT
42610. DAGB7_WRCLI0__MAX_BW_MASK
42611. DAGB7_WRCLI0__MAX_BW__SHIFT
42612. DAGB7_WRCLI0__MAX_OSD_MASK
42613. DAGB7_WRCLI0__MAX_OSD__SHIFT
42614. DAGB7_WRCLI0__MIN_BW_ENABLE_MASK
42615. DAGB7_WRCLI0__MIN_BW_ENABLE__SHIFT
42616. DAGB7_WRCLI0__MIN_BW_MASK
42617. DAGB7_WRCLI0__MIN_BW__SHIFT
42618. DAGB7_WRCLI0__OSD_LIMITER_ENABLE_MASK
42619. DAGB7_WRCLI0__OSD_LIMITER_ENABLE__SHIFT
42620. DAGB7_WRCLI0__URG_HIGH_MASK
42621. DAGB7_WRCLI0__URG_HIGH__SHIFT
42622. DAGB7_WRCLI0__URG_LOW_MASK
42623. DAGB7_WRCLI0__URG_LOW__SHIFT
42624. DAGB7_WRCLI0__VIRT_CHAN_MASK
42625. DAGB7_WRCLI0__VIRT_CHAN__SHIFT
42626. DAGB7_WRCLI10__CHECK_TLB_CREDIT_MASK
42627. DAGB7_WRCLI10__CHECK_TLB_CREDIT__SHIFT
42628. DAGB7_WRCLI10__MAX_BW_ENABLE_MASK
42629. DAGB7_WRCLI10__MAX_BW_ENABLE__SHIFT
42630. DAGB7_WRCLI10__MAX_BW_MASK
42631. DAGB7_WRCLI10__MAX_BW__SHIFT
42632. DAGB7_WRCLI10__MAX_OSD_MASK
42633. DAGB7_WRCLI10__MAX_OSD__SHIFT
42634. DAGB7_WRCLI10__MIN_BW_ENABLE_MASK
42635. DAGB7_WRCLI10__MIN_BW_ENABLE__SHIFT
42636. DAGB7_WRCLI10__MIN_BW_MASK
42637. DAGB7_WRCLI10__MIN_BW__SHIFT
42638. DAGB7_WRCLI10__OSD_LIMITER_ENABLE_MASK
42639. DAGB7_WRCLI10__OSD_LIMITER_ENABLE__SHIFT
42640. DAGB7_WRCLI10__URG_HIGH_MASK
42641. DAGB7_WRCLI10__URG_HIGH__SHIFT
42642. DAGB7_WRCLI10__URG_LOW_MASK
42643. DAGB7_WRCLI10__URG_LOW__SHIFT
42644. DAGB7_WRCLI10__VIRT_CHAN_MASK
42645. DAGB7_WRCLI10__VIRT_CHAN__SHIFT
42646. DAGB7_WRCLI11__CHECK_TLB_CREDIT_MASK
42647. DAGB7_WRCLI11__CHECK_TLB_CREDIT__SHIFT
42648. DAGB7_WRCLI11__MAX_BW_ENABLE_MASK
42649. DAGB7_WRCLI11__MAX_BW_ENABLE__SHIFT
42650. DAGB7_WRCLI11__MAX_BW_MASK
42651. DAGB7_WRCLI11__MAX_BW__SHIFT
42652. DAGB7_WRCLI11__MAX_OSD_MASK
42653. DAGB7_WRCLI11__MAX_OSD__SHIFT
42654. DAGB7_WRCLI11__MIN_BW_ENABLE_MASK
42655. DAGB7_WRCLI11__MIN_BW_ENABLE__SHIFT
42656. DAGB7_WRCLI11__MIN_BW_MASK
42657. DAGB7_WRCLI11__MIN_BW__SHIFT
42658. DAGB7_WRCLI11__OSD_LIMITER_ENABLE_MASK
42659. DAGB7_WRCLI11__OSD_LIMITER_ENABLE__SHIFT
42660. DAGB7_WRCLI11__URG_HIGH_MASK
42661. DAGB7_WRCLI11__URG_HIGH__SHIFT
42662. DAGB7_WRCLI11__URG_LOW_MASK
42663. DAGB7_WRCLI11__URG_LOW__SHIFT
42664. DAGB7_WRCLI11__VIRT_CHAN_MASK
42665. DAGB7_WRCLI11__VIRT_CHAN__SHIFT
42666. DAGB7_WRCLI12__CHECK_TLB_CREDIT_MASK
42667. DAGB7_WRCLI12__CHECK_TLB_CREDIT__SHIFT
42668. DAGB7_WRCLI12__MAX_BW_ENABLE_MASK
42669. DAGB7_WRCLI12__MAX_BW_ENABLE__SHIFT
42670. DAGB7_WRCLI12__MAX_BW_MASK
42671. DAGB7_WRCLI12__MAX_BW__SHIFT
42672. DAGB7_WRCLI12__MAX_OSD_MASK
42673. DAGB7_WRCLI12__MAX_OSD__SHIFT
42674. DAGB7_WRCLI12__MIN_BW_ENABLE_MASK
42675. DAGB7_WRCLI12__MIN_BW_ENABLE__SHIFT
42676. DAGB7_WRCLI12__MIN_BW_MASK
42677. DAGB7_WRCLI12__MIN_BW__SHIFT
42678. DAGB7_WRCLI12__OSD_LIMITER_ENABLE_MASK
42679. DAGB7_WRCLI12__OSD_LIMITER_ENABLE__SHIFT
42680. DAGB7_WRCLI12__URG_HIGH_MASK
42681. DAGB7_WRCLI12__URG_HIGH__SHIFT
42682. DAGB7_WRCLI12__URG_LOW_MASK
42683. DAGB7_WRCLI12__URG_LOW__SHIFT
42684. DAGB7_WRCLI12__VIRT_CHAN_MASK
42685. DAGB7_WRCLI12__VIRT_CHAN__SHIFT
42686. DAGB7_WRCLI13__CHECK_TLB_CREDIT_MASK
42687. DAGB7_WRCLI13__CHECK_TLB_CREDIT__SHIFT
42688. DAGB7_WRCLI13__MAX_BW_ENABLE_MASK
42689. DAGB7_WRCLI13__MAX_BW_ENABLE__SHIFT
42690. DAGB7_WRCLI13__MAX_BW_MASK
42691. DAGB7_WRCLI13__MAX_BW__SHIFT
42692. DAGB7_WRCLI13__MAX_OSD_MASK
42693. DAGB7_WRCLI13__MAX_OSD__SHIFT
42694. DAGB7_WRCLI13__MIN_BW_ENABLE_MASK
42695. DAGB7_WRCLI13__MIN_BW_ENABLE__SHIFT
42696. DAGB7_WRCLI13__MIN_BW_MASK
42697. DAGB7_WRCLI13__MIN_BW__SHIFT
42698. DAGB7_WRCLI13__OSD_LIMITER_ENABLE_MASK
42699. DAGB7_WRCLI13__OSD_LIMITER_ENABLE__SHIFT
42700. DAGB7_WRCLI13__URG_HIGH_MASK
42701. DAGB7_WRCLI13__URG_HIGH__SHIFT
42702. DAGB7_WRCLI13__URG_LOW_MASK
42703. DAGB7_WRCLI13__URG_LOW__SHIFT
42704. DAGB7_WRCLI13__VIRT_CHAN_MASK
42705. DAGB7_WRCLI13__VIRT_CHAN__SHIFT
42706. DAGB7_WRCLI14__CHECK_TLB_CREDIT_MASK
42707. DAGB7_WRCLI14__CHECK_TLB_CREDIT__SHIFT
42708. DAGB7_WRCLI14__MAX_BW_ENABLE_MASK
42709. DAGB7_WRCLI14__MAX_BW_ENABLE__SHIFT
42710. DAGB7_WRCLI14__MAX_BW_MASK
42711. DAGB7_WRCLI14__MAX_BW__SHIFT
42712. DAGB7_WRCLI14__MAX_OSD_MASK
42713. DAGB7_WRCLI14__MAX_OSD__SHIFT
42714. DAGB7_WRCLI14__MIN_BW_ENABLE_MASK
42715. DAGB7_WRCLI14__MIN_BW_ENABLE__SHIFT
42716. DAGB7_WRCLI14__MIN_BW_MASK
42717. DAGB7_WRCLI14__MIN_BW__SHIFT
42718. DAGB7_WRCLI14__OSD_LIMITER_ENABLE_MASK
42719. DAGB7_WRCLI14__OSD_LIMITER_ENABLE__SHIFT
42720. DAGB7_WRCLI14__URG_HIGH_MASK
42721. DAGB7_WRCLI14__URG_HIGH__SHIFT
42722. DAGB7_WRCLI14__URG_LOW_MASK
42723. DAGB7_WRCLI14__URG_LOW__SHIFT
42724. DAGB7_WRCLI14__VIRT_CHAN_MASK
42725. DAGB7_WRCLI14__VIRT_CHAN__SHIFT
42726. DAGB7_WRCLI15__CHECK_TLB_CREDIT_MASK
42727. DAGB7_WRCLI15__CHECK_TLB_CREDIT__SHIFT
42728. DAGB7_WRCLI15__MAX_BW_ENABLE_MASK
42729. DAGB7_WRCLI15__MAX_BW_ENABLE__SHIFT
42730. DAGB7_WRCLI15__MAX_BW_MASK
42731. DAGB7_WRCLI15__MAX_BW__SHIFT
42732. DAGB7_WRCLI15__MAX_OSD_MASK
42733. DAGB7_WRCLI15__MAX_OSD__SHIFT
42734. DAGB7_WRCLI15__MIN_BW_ENABLE_MASK
42735. DAGB7_WRCLI15__MIN_BW_ENABLE__SHIFT
42736. DAGB7_WRCLI15__MIN_BW_MASK
42737. DAGB7_WRCLI15__MIN_BW__SHIFT
42738. DAGB7_WRCLI15__OSD_LIMITER_ENABLE_MASK
42739. DAGB7_WRCLI15__OSD_LIMITER_ENABLE__SHIFT
42740. DAGB7_WRCLI15__URG_HIGH_MASK
42741. DAGB7_WRCLI15__URG_HIGH__SHIFT
42742. DAGB7_WRCLI15__URG_LOW_MASK
42743. DAGB7_WRCLI15__URG_LOW__SHIFT
42744. DAGB7_WRCLI15__VIRT_CHAN_MASK
42745. DAGB7_WRCLI15__VIRT_CHAN__SHIFT
42746. DAGB7_WRCLI1__CHECK_TLB_CREDIT_MASK
42747. DAGB7_WRCLI1__CHECK_TLB_CREDIT__SHIFT
42748. DAGB7_WRCLI1__MAX_BW_ENABLE_MASK
42749. DAGB7_WRCLI1__MAX_BW_ENABLE__SHIFT
42750. DAGB7_WRCLI1__MAX_BW_MASK
42751. DAGB7_WRCLI1__MAX_BW__SHIFT
42752. DAGB7_WRCLI1__MAX_OSD_MASK
42753. DAGB7_WRCLI1__MAX_OSD__SHIFT
42754. DAGB7_WRCLI1__MIN_BW_ENABLE_MASK
42755. DAGB7_WRCLI1__MIN_BW_ENABLE__SHIFT
42756. DAGB7_WRCLI1__MIN_BW_MASK
42757. DAGB7_WRCLI1__MIN_BW__SHIFT
42758. DAGB7_WRCLI1__OSD_LIMITER_ENABLE_MASK
42759. DAGB7_WRCLI1__OSD_LIMITER_ENABLE__SHIFT
42760. DAGB7_WRCLI1__URG_HIGH_MASK
42761. DAGB7_WRCLI1__URG_HIGH__SHIFT
42762. DAGB7_WRCLI1__URG_LOW_MASK
42763. DAGB7_WRCLI1__URG_LOW__SHIFT
42764. DAGB7_WRCLI1__VIRT_CHAN_MASK
42765. DAGB7_WRCLI1__VIRT_CHAN__SHIFT
42766. DAGB7_WRCLI2__CHECK_TLB_CREDIT_MASK
42767. DAGB7_WRCLI2__CHECK_TLB_CREDIT__SHIFT
42768. DAGB7_WRCLI2__MAX_BW_ENABLE_MASK
42769. DAGB7_WRCLI2__MAX_BW_ENABLE__SHIFT
42770. DAGB7_WRCLI2__MAX_BW_MASK
42771. DAGB7_WRCLI2__MAX_BW__SHIFT
42772. DAGB7_WRCLI2__MAX_OSD_MASK
42773. DAGB7_WRCLI2__MAX_OSD__SHIFT
42774. DAGB7_WRCLI2__MIN_BW_ENABLE_MASK
42775. DAGB7_WRCLI2__MIN_BW_ENABLE__SHIFT
42776. DAGB7_WRCLI2__MIN_BW_MASK
42777. DAGB7_WRCLI2__MIN_BW__SHIFT
42778. DAGB7_WRCLI2__OSD_LIMITER_ENABLE_MASK
42779. DAGB7_WRCLI2__OSD_LIMITER_ENABLE__SHIFT
42780. DAGB7_WRCLI2__URG_HIGH_MASK
42781. DAGB7_WRCLI2__URG_HIGH__SHIFT
42782. DAGB7_WRCLI2__URG_LOW_MASK
42783. DAGB7_WRCLI2__URG_LOW__SHIFT
42784. DAGB7_WRCLI2__VIRT_CHAN_MASK
42785. DAGB7_WRCLI2__VIRT_CHAN__SHIFT
42786. DAGB7_WRCLI3__CHECK_TLB_CREDIT_MASK
42787. DAGB7_WRCLI3__CHECK_TLB_CREDIT__SHIFT
42788. DAGB7_WRCLI3__MAX_BW_ENABLE_MASK
42789. DAGB7_WRCLI3__MAX_BW_ENABLE__SHIFT
42790. DAGB7_WRCLI3__MAX_BW_MASK
42791. DAGB7_WRCLI3__MAX_BW__SHIFT
42792. DAGB7_WRCLI3__MAX_OSD_MASK
42793. DAGB7_WRCLI3__MAX_OSD__SHIFT
42794. DAGB7_WRCLI3__MIN_BW_ENABLE_MASK
42795. DAGB7_WRCLI3__MIN_BW_ENABLE__SHIFT
42796. DAGB7_WRCLI3__MIN_BW_MASK
42797. DAGB7_WRCLI3__MIN_BW__SHIFT
42798. DAGB7_WRCLI3__OSD_LIMITER_ENABLE_MASK
42799. DAGB7_WRCLI3__OSD_LIMITER_ENABLE__SHIFT
42800. DAGB7_WRCLI3__URG_HIGH_MASK
42801. DAGB7_WRCLI3__URG_HIGH__SHIFT
42802. DAGB7_WRCLI3__URG_LOW_MASK
42803. DAGB7_WRCLI3__URG_LOW__SHIFT
42804. DAGB7_WRCLI3__VIRT_CHAN_MASK
42805. DAGB7_WRCLI3__VIRT_CHAN__SHIFT
42806. DAGB7_WRCLI4__CHECK_TLB_CREDIT_MASK
42807. DAGB7_WRCLI4__CHECK_TLB_CREDIT__SHIFT
42808. DAGB7_WRCLI4__MAX_BW_ENABLE_MASK
42809. DAGB7_WRCLI4__MAX_BW_ENABLE__SHIFT
42810. DAGB7_WRCLI4__MAX_BW_MASK
42811. DAGB7_WRCLI4__MAX_BW__SHIFT
42812. DAGB7_WRCLI4__MAX_OSD_MASK
42813. DAGB7_WRCLI4__MAX_OSD__SHIFT
42814. DAGB7_WRCLI4__MIN_BW_ENABLE_MASK
42815. DAGB7_WRCLI4__MIN_BW_ENABLE__SHIFT
42816. DAGB7_WRCLI4__MIN_BW_MASK
42817. DAGB7_WRCLI4__MIN_BW__SHIFT
42818. DAGB7_WRCLI4__OSD_LIMITER_ENABLE_MASK
42819. DAGB7_WRCLI4__OSD_LIMITER_ENABLE__SHIFT
42820. DAGB7_WRCLI4__URG_HIGH_MASK
42821. DAGB7_WRCLI4__URG_HIGH__SHIFT
42822. DAGB7_WRCLI4__URG_LOW_MASK
42823. DAGB7_WRCLI4__URG_LOW__SHIFT
42824. DAGB7_WRCLI4__VIRT_CHAN_MASK
42825. DAGB7_WRCLI4__VIRT_CHAN__SHIFT
42826. DAGB7_WRCLI5__CHECK_TLB_CREDIT_MASK
42827. DAGB7_WRCLI5__CHECK_TLB_CREDIT__SHIFT
42828. DAGB7_WRCLI5__MAX_BW_ENABLE_MASK
42829. DAGB7_WRCLI5__MAX_BW_ENABLE__SHIFT
42830. DAGB7_WRCLI5__MAX_BW_MASK
42831. DAGB7_WRCLI5__MAX_BW__SHIFT
42832. DAGB7_WRCLI5__MAX_OSD_MASK
42833. DAGB7_WRCLI5__MAX_OSD__SHIFT
42834. DAGB7_WRCLI5__MIN_BW_ENABLE_MASK
42835. DAGB7_WRCLI5__MIN_BW_ENABLE__SHIFT
42836. DAGB7_WRCLI5__MIN_BW_MASK
42837. DAGB7_WRCLI5__MIN_BW__SHIFT
42838. DAGB7_WRCLI5__OSD_LIMITER_ENABLE_MASK
42839. DAGB7_WRCLI5__OSD_LIMITER_ENABLE__SHIFT
42840. DAGB7_WRCLI5__URG_HIGH_MASK
42841. DAGB7_WRCLI5__URG_HIGH__SHIFT
42842. DAGB7_WRCLI5__URG_LOW_MASK
42843. DAGB7_WRCLI5__URG_LOW__SHIFT
42844. DAGB7_WRCLI5__VIRT_CHAN_MASK
42845. DAGB7_WRCLI5__VIRT_CHAN__SHIFT
42846. DAGB7_WRCLI6__CHECK_TLB_CREDIT_MASK
42847. DAGB7_WRCLI6__CHECK_TLB_CREDIT__SHIFT
42848. DAGB7_WRCLI6__MAX_BW_ENABLE_MASK
42849. DAGB7_WRCLI6__MAX_BW_ENABLE__SHIFT
42850. DAGB7_WRCLI6__MAX_BW_MASK
42851. DAGB7_WRCLI6__MAX_BW__SHIFT
42852. DAGB7_WRCLI6__MAX_OSD_MASK
42853. DAGB7_WRCLI6__MAX_OSD__SHIFT
42854. DAGB7_WRCLI6__MIN_BW_ENABLE_MASK
42855. DAGB7_WRCLI6__MIN_BW_ENABLE__SHIFT
42856. DAGB7_WRCLI6__MIN_BW_MASK
42857. DAGB7_WRCLI6__MIN_BW__SHIFT
42858. DAGB7_WRCLI6__OSD_LIMITER_ENABLE_MASK
42859. DAGB7_WRCLI6__OSD_LIMITER_ENABLE__SHIFT
42860. DAGB7_WRCLI6__URG_HIGH_MASK
42861. DAGB7_WRCLI6__URG_HIGH__SHIFT
42862. DAGB7_WRCLI6__URG_LOW_MASK
42863. DAGB7_WRCLI6__URG_LOW__SHIFT
42864. DAGB7_WRCLI6__VIRT_CHAN_MASK
42865. DAGB7_WRCLI6__VIRT_CHAN__SHIFT
42866. DAGB7_WRCLI7__CHECK_TLB_CREDIT_MASK
42867. DAGB7_WRCLI7__CHECK_TLB_CREDIT__SHIFT
42868. DAGB7_WRCLI7__MAX_BW_ENABLE_MASK
42869. DAGB7_WRCLI7__MAX_BW_ENABLE__SHIFT
42870. DAGB7_WRCLI7__MAX_BW_MASK
42871. DAGB7_WRCLI7__MAX_BW__SHIFT
42872. DAGB7_WRCLI7__MAX_OSD_MASK
42873. DAGB7_WRCLI7__MAX_OSD__SHIFT
42874. DAGB7_WRCLI7__MIN_BW_ENABLE_MASK
42875. DAGB7_WRCLI7__MIN_BW_ENABLE__SHIFT
42876. DAGB7_WRCLI7__MIN_BW_MASK
42877. DAGB7_WRCLI7__MIN_BW__SHIFT
42878. DAGB7_WRCLI7__OSD_LIMITER_ENABLE_MASK
42879. DAGB7_WRCLI7__OSD_LIMITER_ENABLE__SHIFT
42880. DAGB7_WRCLI7__URG_HIGH_MASK
42881. DAGB7_WRCLI7__URG_HIGH__SHIFT
42882. DAGB7_WRCLI7__URG_LOW_MASK
42883. DAGB7_WRCLI7__URG_LOW__SHIFT
42884. DAGB7_WRCLI7__VIRT_CHAN_MASK
42885. DAGB7_WRCLI7__VIRT_CHAN__SHIFT
42886. DAGB7_WRCLI8__CHECK_TLB_CREDIT_MASK
42887. DAGB7_WRCLI8__CHECK_TLB_CREDIT__SHIFT
42888. DAGB7_WRCLI8__MAX_BW_ENABLE_MASK
42889. DAGB7_WRCLI8__MAX_BW_ENABLE__SHIFT
42890. DAGB7_WRCLI8__MAX_BW_MASK
42891. DAGB7_WRCLI8__MAX_BW__SHIFT
42892. DAGB7_WRCLI8__MAX_OSD_MASK
42893. DAGB7_WRCLI8__MAX_OSD__SHIFT
42894. DAGB7_WRCLI8__MIN_BW_ENABLE_MASK
42895. DAGB7_WRCLI8__MIN_BW_ENABLE__SHIFT
42896. DAGB7_WRCLI8__MIN_BW_MASK
42897. DAGB7_WRCLI8__MIN_BW__SHIFT
42898. DAGB7_WRCLI8__OSD_LIMITER_ENABLE_MASK
42899. DAGB7_WRCLI8__OSD_LIMITER_ENABLE__SHIFT
42900. DAGB7_WRCLI8__URG_HIGH_MASK
42901. DAGB7_WRCLI8__URG_HIGH__SHIFT
42902. DAGB7_WRCLI8__URG_LOW_MASK
42903. DAGB7_WRCLI8__URG_LOW__SHIFT
42904. DAGB7_WRCLI8__VIRT_CHAN_MASK
42905. DAGB7_WRCLI8__VIRT_CHAN__SHIFT
42906. DAGB7_WRCLI9__CHECK_TLB_CREDIT_MASK
42907. DAGB7_WRCLI9__CHECK_TLB_CREDIT__SHIFT
42908. DAGB7_WRCLI9__MAX_BW_ENABLE_MASK
42909. DAGB7_WRCLI9__MAX_BW_ENABLE__SHIFT
42910. DAGB7_WRCLI9__MAX_BW_MASK
42911. DAGB7_WRCLI9__MAX_BW__SHIFT
42912. DAGB7_WRCLI9__MAX_OSD_MASK
42913. DAGB7_WRCLI9__MAX_OSD__SHIFT
42914. DAGB7_WRCLI9__MIN_BW_ENABLE_MASK
42915. DAGB7_WRCLI9__MIN_BW_ENABLE__SHIFT
42916. DAGB7_WRCLI9__MIN_BW_MASK
42917. DAGB7_WRCLI9__MIN_BW__SHIFT
42918. DAGB7_WRCLI9__OSD_LIMITER_ENABLE_MASK
42919. DAGB7_WRCLI9__OSD_LIMITER_ENABLE__SHIFT
42920. DAGB7_WRCLI9__URG_HIGH_MASK
42921. DAGB7_WRCLI9__URG_HIGH__SHIFT
42922. DAGB7_WRCLI9__URG_LOW_MASK
42923. DAGB7_WRCLI9__URG_LOW__SHIFT
42924. DAGB7_WRCLI9__VIRT_CHAN_MASK
42925. DAGB7_WRCLI9__VIRT_CHAN__SHIFT
42926. DAGB7_WRCLI_ASK_PENDING__BUSY_MASK
42927. DAGB7_WRCLI_ASK_PENDING__BUSY__SHIFT
42928. DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY_MASK
42929. DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT
42930. DAGB7_WRCLI_DBUS_GO_PENDING__BUSY_MASK
42931. DAGB7_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT
42932. DAGB7_WRCLI_GBLSEND_PENDING__BUSY_MASK
42933. DAGB7_WRCLI_GBLSEND_PENDING__BUSY__SHIFT
42934. DAGB7_WRCLI_GO_PENDING__BUSY_MASK
42935. DAGB7_WRCLI_GO_PENDING__BUSY__SHIFT
42936. DAGB7_WRCLI_OARB_PENDING__BUSY_MASK
42937. DAGB7_WRCLI_OARB_PENDING__BUSY__SHIFT
42938. DAGB7_WRCLI_OSD_PENDING__BUSY_MASK
42939. DAGB7_WRCLI_OSD_PENDING__BUSY__SHIFT
42940. DAGB7_WRCLI_TLB_PENDING__BUSY_MASK
42941. DAGB7_WRCLI_TLB_PENDING__BUSY__SHIFT
42942. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK
42943. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
42944. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK
42945. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
42946. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK
42947. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
42948. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK
42949. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
42950. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK
42951. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
42952. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK
42953. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
42954. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK
42955. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
42956. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK
42957. DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
42958. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK
42959. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
42960. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK
42961. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
42962. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK
42963. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
42964. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK
42965. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
42966. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK
42967. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
42968. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK
42969. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
42970. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK
42971. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
42972. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK
42973. DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
42974. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK
42975. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT
42976. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK
42977. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT
42978. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK
42979. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT
42980. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK
42981. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT
42982. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK
42983. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT
42984. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK
42985. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT
42986. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK
42987. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT
42988. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK
42989. DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT
42990. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK
42991. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT
42992. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK
42993. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT
42994. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK
42995. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT
42996. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK
42997. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT
42998. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK
42999. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT
43000. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK
43001. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT
43002. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK
43003. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT
43004. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK
43005. DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT
43006. DAGB7_WR_ADDR_DAGB__DAGB_ENABLE_MASK
43007. DAGB7_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT
43008. DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK
43009. DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT
43010. DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK
43011. DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT
43012. DAGB7_WR_ADDR_DAGB__WHOAMI_MASK
43013. DAGB7_WR_ADDR_DAGB__WHOAMI__SHIFT
43014. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
43015. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK
43016. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT
43017. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK
43018. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT
43019. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK
43020. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT
43021. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK
43022. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT
43023. DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT
43024. DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
43025. DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
43026. DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY_MASK
43027. DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT
43028. DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
43029. DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
43030. DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK
43031. DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT
43032. DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT_MASK
43033. DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT
43034. DAGB7_WR_CNTL_MISC__IO_EA_CREDIT_MASK
43035. DAGB7_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT
43036. DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK
43037. DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT
43038. DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK
43039. DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT
43040. DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK
43041. DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT
43042. DAGB7_WR_CNTL_MISC__UTCL2_CID_MASK
43043. DAGB7_WR_CNTL_MISC__UTCL2_CID__SHIFT
43044. DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW_MASK
43045. DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT
43046. DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK
43047. DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT
43048. DAGB7_WR_CNTL__IO_LEVEL_MASK
43049. DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK
43050. DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT
43051. DAGB7_WR_CNTL__IO_LEVEL__SHIFT
43052. DAGB7_WR_CNTL__SCLK_FREQ_MASK
43053. DAGB7_WR_CNTL__SCLK_FREQ__SHIFT
43054. DAGB7_WR_CNTL__SHARE_VC_NUM_MASK
43055. DAGB7_WR_CNTL__SHARE_VC_NUM__SHIFT
43056. DAGB7_WR_CNTL__VC_MAX_BW_WINDOW_MASK
43057. DAGB7_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT
43058. DAGB7_WR_CREDITS_FULL__FULL_MASK
43059. DAGB7_WR_CREDITS_FULL__FULL__SHIFT
43060. DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK
43061. DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT
43062. DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK
43063. DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT
43064. DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK
43065. DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT
43066. DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK
43067. DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT
43068. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK
43069. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT
43070. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK
43071. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT
43072. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK
43073. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT
43074. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK
43075. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT
43076. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK
43077. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT
43078. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK
43079. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT
43080. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK
43081. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT
43082. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK
43083. DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT
43084. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK
43085. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT
43086. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK
43087. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT
43088. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK
43089. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT
43090. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK
43091. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT
43092. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK
43093. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT
43094. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK
43095. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT
43096. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK
43097. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT
43098. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK
43099. DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT
43100. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK
43101. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT
43102. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK
43103. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT
43104. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK
43105. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT
43106. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK
43107. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT
43108. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK
43109. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT
43110. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK
43111. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT
43112. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK
43113. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT
43114. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK
43115. DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT
43116. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK
43117. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT
43118. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK
43119. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT
43120. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK
43121. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT
43122. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK
43123. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT
43124. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK
43125. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT
43126. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK
43127. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT
43128. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK
43129. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT
43130. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK
43131. DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT
43132. DAGB7_WR_DATA_DAGB__DAGB_ENABLE_MASK
43133. DAGB7_WR_DATA_DAGB__DAGB_ENABLE__SHIFT
43134. DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK
43135. DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT
43136. DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK
43137. DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT
43138. DAGB7_WR_DATA_DAGB__WHOAMI_MASK
43139. DAGB7_WR_DATA_DAGB__WHOAMI__SHIFT
43140. DAGB7_WR_GMI_CNTL__EA_CREDIT_MASK
43141. DAGB7_WR_GMI_CNTL__EA_CREDIT__SHIFT
43142. DAGB7_WR_GMI_CNTL__LAZY_TIMER_MASK
43143. DAGB7_WR_GMI_CNTL__LAZY_TIMER__SHIFT
43144. DAGB7_WR_GMI_CNTL__LEVEL_MASK
43145. DAGB7_WR_GMI_CNTL__LEVEL__SHIFT
43146. DAGB7_WR_GMI_CNTL__MAX_BURST_MASK
43147. DAGB7_WR_GMI_CNTL__MAX_BURST__SHIFT
43148. DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK
43149. DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT
43150. DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK
43151. DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT
43152. DAGB7_WR_MISC_CREDIT__OSD_CREDIT_MASK
43153. DAGB7_WR_MISC_CREDIT__OSD_CREDIT__SHIFT
43154. DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK
43155. DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT
43156. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK
43157. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT
43158. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK
43159. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT
43160. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK
43161. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT
43162. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK
43163. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT
43164. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK
43165. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT
43166. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK
43167. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT
43168. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK
43169. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT
43170. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK
43171. DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT
43172. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK
43173. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT
43174. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK
43175. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT
43176. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK
43177. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT
43178. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK
43179. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT
43180. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK
43181. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT
43182. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK
43183. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT
43184. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK
43185. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT
43186. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK
43187. DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT
43188. DAGB7_WR_TLB_CREDIT__TLB0_MASK
43189. DAGB7_WR_TLB_CREDIT__TLB0__SHIFT
43190. DAGB7_WR_TLB_CREDIT__TLB1_MASK
43191. DAGB7_WR_TLB_CREDIT__TLB1__SHIFT
43192. DAGB7_WR_TLB_CREDIT__TLB2_MASK
43193. DAGB7_WR_TLB_CREDIT__TLB2__SHIFT
43194. DAGB7_WR_TLB_CREDIT__TLB3_MASK
43195. DAGB7_WR_TLB_CREDIT__TLB3__SHIFT
43196. DAGB7_WR_TLB_CREDIT__TLB4_MASK
43197. DAGB7_WR_TLB_CREDIT__TLB4__SHIFT
43198. DAGB7_WR_TLB_CREDIT__TLB5_MASK
43199. DAGB7_WR_TLB_CREDIT__TLB5__SHIFT
43200. DAGB7_WR_VC0_CNTL__EA_CREDIT_MASK
43201. DAGB7_WR_VC0_CNTL__EA_CREDIT__SHIFT
43202. DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE_MASK
43203. DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT
43204. DAGB7_WR_VC0_CNTL__MAX_BW_MASK
43205. DAGB7_WR_VC0_CNTL__MAX_BW__SHIFT
43206. DAGB7_WR_VC0_CNTL__MAX_OSD_MASK
43207. DAGB7_WR_VC0_CNTL__MAX_OSD__SHIFT
43208. DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE_MASK
43209. DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT
43210. DAGB7_WR_VC0_CNTL__MIN_BW_MASK
43211. DAGB7_WR_VC0_CNTL__MIN_BW__SHIFT
43212. DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK
43213. DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT
43214. DAGB7_WR_VC0_CNTL__STOR_CREDIT_MASK
43215. DAGB7_WR_VC0_CNTL__STOR_CREDIT__SHIFT
43216. DAGB7_WR_VC1_CNTL__EA_CREDIT_MASK
43217. DAGB7_WR_VC1_CNTL__EA_CREDIT__SHIFT
43218. DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE_MASK
43219. DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT
43220. DAGB7_WR_VC1_CNTL__MAX_BW_MASK
43221. DAGB7_WR_VC1_CNTL__MAX_BW__SHIFT
43222. DAGB7_WR_VC1_CNTL__MAX_OSD_MASK
43223. DAGB7_WR_VC1_CNTL__MAX_OSD__SHIFT
43224. DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE_MASK
43225. DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT
43226. DAGB7_WR_VC1_CNTL__MIN_BW_MASK
43227. DAGB7_WR_VC1_CNTL__MIN_BW__SHIFT
43228. DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK
43229. DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT
43230. DAGB7_WR_VC1_CNTL__STOR_CREDIT_MASK
43231. DAGB7_WR_VC1_CNTL__STOR_CREDIT__SHIFT
43232. DAGB7_WR_VC2_CNTL__EA_CREDIT_MASK
43233. DAGB7_WR_VC2_CNTL__EA_CREDIT__SHIFT
43234. DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE_MASK
43235. DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT
43236. DAGB7_WR_VC2_CNTL__MAX_BW_MASK
43237. DAGB7_WR_VC2_CNTL__MAX_BW__SHIFT
43238. DAGB7_WR_VC2_CNTL__MAX_OSD_MASK
43239. DAGB7_WR_VC2_CNTL__MAX_OSD__SHIFT
43240. DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE_MASK
43241. DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT
43242. DAGB7_WR_VC2_CNTL__MIN_BW_MASK
43243. DAGB7_WR_VC2_CNTL__MIN_BW__SHIFT
43244. DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK
43245. DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT
43246. DAGB7_WR_VC2_CNTL__STOR_CREDIT_MASK
43247. DAGB7_WR_VC2_CNTL__STOR_CREDIT__SHIFT
43248. DAGB7_WR_VC3_CNTL__EA_CREDIT_MASK
43249. DAGB7_WR_VC3_CNTL__EA_CREDIT__SHIFT
43250. DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE_MASK
43251. DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT
43252. DAGB7_WR_VC3_CNTL__MAX_BW_MASK
43253. DAGB7_WR_VC3_CNTL__MAX_BW__SHIFT
43254. DAGB7_WR_VC3_CNTL__MAX_OSD_MASK
43255. DAGB7_WR_VC3_CNTL__MAX_OSD__SHIFT
43256. DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE_MASK
43257. DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT
43258. DAGB7_WR_VC3_CNTL__MIN_BW_MASK
43259. DAGB7_WR_VC3_CNTL__MIN_BW__SHIFT
43260. DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK
43261. DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT
43262. DAGB7_WR_VC3_CNTL__STOR_CREDIT_MASK
43263. DAGB7_WR_VC3_CNTL__STOR_CREDIT__SHIFT
43264. DAGB7_WR_VC4_CNTL__EA_CREDIT_MASK
43265. DAGB7_WR_VC4_CNTL__EA_CREDIT__SHIFT
43266. DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE_MASK
43267. DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT
43268. DAGB7_WR_VC4_CNTL__MAX_BW_MASK
43269. DAGB7_WR_VC4_CNTL__MAX_BW__SHIFT
43270. DAGB7_WR_VC4_CNTL__MAX_OSD_MASK
43271. DAGB7_WR_VC4_CNTL__MAX_OSD__SHIFT
43272. DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE_MASK
43273. DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT
43274. DAGB7_WR_VC4_CNTL__MIN_BW_MASK
43275. DAGB7_WR_VC4_CNTL__MIN_BW__SHIFT
43276. DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK
43277. DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT
43278. DAGB7_WR_VC4_CNTL__STOR_CREDIT_MASK
43279. DAGB7_WR_VC4_CNTL__STOR_CREDIT__SHIFT
43280. DAGB7_WR_VC5_CNTL__EA_CREDIT_MASK
43281. DAGB7_WR_VC5_CNTL__EA_CREDIT__SHIFT
43282. DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE_MASK
43283. DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT
43284. DAGB7_WR_VC5_CNTL__MAX_BW_MASK
43285. DAGB7_WR_VC5_CNTL__MAX_BW__SHIFT
43286. DAGB7_WR_VC5_CNTL__MAX_OSD_MASK
43287. DAGB7_WR_VC5_CNTL__MAX_OSD__SHIFT
43288. DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE_MASK
43289. DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT
43290. DAGB7_WR_VC5_CNTL__MIN_BW_MASK
43291. DAGB7_WR_VC5_CNTL__MIN_BW__SHIFT
43292. DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK
43293. DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT
43294. DAGB7_WR_VC5_CNTL__STOR_CREDIT_MASK
43295. DAGB7_WR_VC5_CNTL__STOR_CREDIT__SHIFT
43296. DAGB7_WR_VC6_CNTL__EA_CREDIT_MASK
43297. DAGB7_WR_VC6_CNTL__EA_CREDIT__SHIFT
43298. DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE_MASK
43299. DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT
43300. DAGB7_WR_VC6_CNTL__MAX_BW_MASK
43301. DAGB7_WR_VC6_CNTL__MAX_BW__SHIFT
43302. DAGB7_WR_VC6_CNTL__MAX_OSD_MASK
43303. DAGB7_WR_VC6_CNTL__MAX_OSD__SHIFT
43304. DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE_MASK
43305. DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT
43306. DAGB7_WR_VC6_CNTL__MIN_BW_MASK
43307. DAGB7_WR_VC6_CNTL__MIN_BW__SHIFT
43308. DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK
43309. DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT
43310. DAGB7_WR_VC6_CNTL__STOR_CREDIT_MASK
43311. DAGB7_WR_VC6_CNTL__STOR_CREDIT__SHIFT
43312. DAGB7_WR_VC7_CNTL__EA_CREDIT_MASK
43313. DAGB7_WR_VC7_CNTL__EA_CREDIT__SHIFT
43314. DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE_MASK
43315. DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT
43316. DAGB7_WR_VC7_CNTL__MAX_BW_MASK
43317. DAGB7_WR_VC7_CNTL__MAX_BW__SHIFT
43318. DAGB7_WR_VC7_CNTL__MAX_OSD_MASK
43319. DAGB7_WR_VC7_CNTL__MAX_OSD__SHIFT
43320. DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE_MASK
43321. DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT
43322. DAGB7_WR_VC7_CNTL__MIN_BW_MASK
43323. DAGB7_WR_VC7_CNTL__MIN_BW__SHIFT
43324. DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK
43325. DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT
43326. DAGB7_WR_VC7_CNTL__STOR_CREDIT_MASK
43327. DAGB7_WR_VC7_CNTL__STOR_CREDIT__SHIFT
43328. DAGC_IMPROVED_LOWBETA0
43329. DAGC_IMPROVED_LOWBETA1
43330. DAGC_NORMAL
43331. DAGC_data_set
43332. DAI
43333. DAIF_ERRCTX
43334. DAIF_MASK
43335. DAIF_PROCCTX
43336. DAIF_PROCCTX_NOIRQ
43337. DAILINK_CDNDP
43338. DAILINK_COMP_ARRAY
43339. DAILINK_DA7219
43340. DAILINK_DMIC
43341. DAILINK_MAX98357A
43342. DAILINK_RT5514
43343. DAILINK_RT5514_DSP
43344. DAINT
43345. DAINTMSK
43346. DAINT_INEP
43347. DAINT_OUTEP
43348. DAINT_OUTEP_SHIFT
43349. DAIO
43350. DAIOTYP
43351. DAIO_OUT_MAX
43352. DAI_ALIGN_MASK
43353. DAI_ALIGN_MASK_SFT
43354. DAI_ALIGN_SFT
43355. DAI_AP_DSP
43356. DAI_CODEC_CP
43357. DAI_CODEC_SUB
43358. DAI_DSP_CODEC
43359. DAI_DUP_WR_MASK
43360. DAI_DUP_WR_MASK_SFT
43361. DAI_DUP_WR_SFT
43362. DAI_FMT_BASE
43363. DAI_HD_MASK
43364. DAI_HD_MASK_SFT
43365. DAI_HD_SFT
43366. DAI_I2S0
43367. DAI_I2S1
43368. DAI_I2S2
43369. DAI_I2S3
43370. DAI_I2S5
43371. DAI_I2S_NUM
43372. DAI_ID_I2S
43373. DAI_ID_SPDIF
43374. DAI_INT
43375. DAI_LINK_BE_I2S0
43376. DAI_LINK_BE_I2S1
43377. DAI_LINK_BE_I2S2
43378. DAI_LINK_BE_I2S3
43379. DAI_LINK_BE_MRG_BT
43380. DAI_LINK_CAPTURE
43381. DAI_LINK_CODEC_I2S
43382. DAI_LINK_FE_BT_IN
43383. DAI_LINK_FE_BT_OUT
43384. DAI_LINK_FE_MULTI_CH_OUT
43385. DAI_LINK_FE_PCM0_IN
43386. DAI_LINK_FE_PCM1_IN
43387. DAI_LINK_HDMI
43388. DAI_LINK_HDMI_I2S
43389. DAI_LINK_INTERCODEC
43390. DAI_LINK_PLAYBACK
43391. DAI_MANAGER
43392. DAI_MODE_MASK
43393. DAI_MODE_MASK_SFT
43394. DAI_MODE_SFT
43395. DAI_NAME_SIZE
43396. DAI_NORMAL_MODE_MASK
43397. DAI_NORMAL_MODE_MASK_SFT
43398. DAI_NORMAL_MODE_SFT
43399. DAI_ON_MASK
43400. DAI_ON_MASK_SFT
43401. DAI_ON_SFT
43402. DAI_OPENED
43403. DAI_PCM_LOOPBACK_CH_MASK
43404. DAI_PCM_LOOPBACK_CH_MASK_SFT
43405. DAI_PCM_LOOPBACK_CH_SFT
43406. DALGN
43407. DALLAS_MAXIM_DS1343
43408. DALLAS_MAXIM_DS1344
43409. DAL_DC_DCE_DCE110_CLK_MGR_H_
43410. DAL_DC_DCE_DCE112_CLK_MGR_H_
43411. DAL_DC_DCE_DCE120_CLK_MGR_H_
43412. DAL_DC_DCN10_RV1_CLK_MGR_CLK_H_
43413. DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_
43414. DAL_DC_DCN20_DCN20_VMID_H_
43415. DAL_DC_DCN21_DCN21_HUBBUB_H_
43416. DAL_DC_DCN21_DCN21_HUBP_H_
43417. DAL_DC_INC_HW_VMID_H_
43418. DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
43419. DAL_INVALID_IRQ_HANDLER_IDX
43420. DAL_IRQ_SOURCES_NUMBER
43421. DAL_LOGGER_NOT_IMPL
43422. DAL_PFLIP_IRQ_SRC_NUM
43423. DAL_STATS_ENABLE_REGKEY
43424. DAL_STATS_ENABLE_REGKEY_DEFAULT
43425. DAL_STATS_ENABLE_REGKEY_ENABLED
43426. DAL_STATS_ENTRIES_REGKEY
43427. DAL_STATS_ENTRIES_REGKEY_DEFAULT
43428. DAL_STATS_ENTRIES_REGKEY_MAX
43429. DAL_STATS_EVENT_ENTRIES_DEFAULT
43430. DAL_VALID_IRQ_SRC_NUM
43431. DAL_VECTOR_APPEND
43432. DAL_VECTOR_AT_INDEX
43433. DAL_VECTOR_INSERT_AT
43434. DAL_VECTOR_SET_AT_INDEX
43435. DAM
43436. DANCEPAD_MAP_CONFIG
43437. DANGER_STATUS
43438. DANUBE_MAX_PIN
43439. DAOIMAP
43440. DAOIMAP_END
43441. DAOIMAP_START
43442. DAPC
43443. DAPCR
43444. DAPCR_AP1E
43445. DAPCR_AP2E
43446. DAPCR_CODE
43447. DAPM_ARROW
43448. DAPM_DIRECT
43449. DAPM_UPDATE_STAT
43450. DAPQ_BUFF_SIZE
43451. DAPQ_DATA_BUFF
43452. DAPQ_OFFSET
43453. DAPQ_STRUCT_SIZE
43454. DAPTSR
43455. DAPTSR_APnDK
43456. DAPTSR_APnTS
43457. DAP_BUFF_SIZE
43458. DAQDS__size
43459. DAQDS_wChannels
43460. DAQDS_wFlags
43461. DAQDS_wFormat
43462. DAQDS_wIntMsg
43463. DAQDS_wSampleRate
43464. DAQDS_wSampleSize
43465. DAQDS_wSize
43466. DAQDS_wStart
43467. DAQP_AI_FIFO_REG
43468. DAQP_AO_REG
43469. DAQP_AUX_CONVERSION
43470. DAQP_AUX_DATA_LOST
43471. DAQP_AUX_DA_BUFFER
43472. DAQP_AUX_DA_UPDATE
43473. DAQP_AUX_DA_UPDATE_DIRECT
43474. DAQP_AUX_DA_UPDATE_EXTERNAL
43475. DAQP_AUX_DA_UPDATE_OVERFLOW
43476. DAQP_AUX_DA_UPDATE_PACER
43477. DAQP_AUX_EXT_ANALOG_TRIG
43478. DAQP_AUX_FIFO_EMPTY
43479. DAQP_AUX_FIFO_NEARFULL
43480. DAQP_AUX_PRETRIG
43481. DAQP_AUX_REG
43482. DAQP_AUX_RUNNING
43483. DAQP_AUX_TIMER_CLK_SRC_EXT
43484. DAQP_AUX_TIMER_INT_ENA
43485. DAQP_AUX_TIMER_MODE
43486. DAQP_AUX_TIMER_MODE_EXT
43487. DAQP_AUX_TIMER_MODE_GO
43488. DAQP_AUX_TIMER_MODE_PAUSE
43489. DAQP_AUX_TIMER_MODE_RELOAD
43490. DAQP_AUX_TIMER_OVERFLOW
43491. DAQP_AUX_TRIGGERED
43492. DAQP_CMD_ARM
43493. DAQP_CMD_FIFO_DATA
43494. DAQP_CMD_LATCH
43495. DAQP_CMD_REG
43496. DAQP_CMD_RSTF
43497. DAQP_CMD_RSTQ
43498. DAQP_CMD_SCANRATE
43499. DAQP_CMD_SCANRATE_100KHZ
43500. DAQP_CMD_SCANRATE_25KHZ
43501. DAQP_CMD_SCANRATE_50KHZ
43502. DAQP_CMD_STOP
43503. DAQP_CTRL_EOS_INT_ENA
43504. DAQP_CTRL_EXPANSION
43505. DAQP_CTRL_FIFO_INT_ENA
43506. DAQP_CTRL_PACER_CLK
43507. DAQP_CTRL_PACER_CLK_100KHZ
43508. DAQP_CTRL_PACER_CLK_1MHZ
43509. DAQP_CTRL_PACER_CLK_5MHZ
43510. DAQP_CTRL_PACER_CLK_EXT
43511. DAQP_CTRL_REG
43512. DAQP_CTRL_TRIG_EDGE
43513. DAQP_CTRL_TRIG_MODE
43514. DAQP_CTRL_TRIG_SRC
43515. DAQP_DI_REG
43516. DAQP_DO_REG
43517. DAQP_FIFO_SIZE
43518. DAQP_MAX_TIMER_SPEED
43519. DAQP_PACER_HIGH_REG
43520. DAQP_PACER_LOW_REG
43521. DAQP_PACER_MID_REG
43522. DAQP_SCANLIST_CHANNEL
43523. DAQP_SCANLIST_DIFFERENTIAL
43524. DAQP_SCANLIST_EXT_CHANNEL
43525. DAQP_SCANLIST_EXT_GAIN
43526. DAQP_SCANLIST_GAIN
43527. DAQP_SCANLIST_REG
43528. DAQP_SCANLIST_START
43529. DAQP_STATUS_DATA_LOST
43530. DAQP_STATUS_END_OF_SCAN
43531. DAQP_STATUS_EVENTS
43532. DAQP_STATUS_FIFO_EMPTY
43533. DAQP_STATUS_FIFO_FULL
43534. DAQP_STATUS_FIFO_NEARFULL
43535. DAQP_STATUS_FIFO_THRESHOLD
43536. DAQP_STATUS_IDLE
43537. DAQP_STATUS_REG
43538. DAQP_STATUS_RUNNING
43539. DAQP_TIMER_REG
43540. DAQ_ATRIG_LOW_4020_REG
43541. DAQ_OPTIONS
43542. DAQ_SYNC_REG
43543. DAR
43544. DARB
43545. DARBF_GATING_DIS
43546. DARBH
43547. DARFRC
43548. DARH
43549. DARK_TIME
43550. DARK_YOFS_REG
43551. DARL
43552. DARLA20
43553. DARLA24
43554. DARN_ERR
43555. DARQ_BUFF_SIZE
43556. DARQ_DATA_BUFF
43557. DARQ_OFFSET
43558. DARQ_STRUCT_SIZE
43559. DARROW_CHAR
43560. DARTMAP_RPNMASK
43561. DARTMAP_VALID
43562. DART_BASE_U4
43563. DART_BASE_U4_BASE_MASK
43564. DART_BASE_U4_BASE_SHIFT
43565. DART_CNTL
43566. DART_CNTL_U3_BASE_MASK
43567. DART_CNTL_U3_BASE_SHIFT
43568. DART_CNTL_U3_ENABLE
43569. DART_CNTL_U3_FLUSHTLB
43570. DART_CNTL_U3_SIZE_MASK
43571. DART_CNTL_U3_SIZE_SHIFT
43572. DART_CNTL_U4_ENABLE
43573. DART_CNTL_U4_FLUSHTLB
43574. DART_CNTL_U4_IDLE
43575. DART_CNTL_U4_IONE
43576. DART_CNTL_U4_IONE_MASK
43577. DART_CNTL_U4_PAR_EN
43578. DART_EXCP_U3
43579. DART_EXCP_U4
43580. DART_IN
43581. DART_OUT
43582. DART_PAGE_SHIFT
43583. DART_PAGE_SIZE
43584. DART_REG
43585. DART_SIZE_U4
43586. DART_SIZE_U4_SIZE_MASK
43587. DART_SIZE_U4_SIZE_SHIFT
43588. DART_TAGS_U3
43589. DART_TAGS_U4
43590. DART_U4_BYPASS_BASE
43591. DAR_AFT_CONF
43592. DAR_ASM_CTRL1
43593. DAR_ASM_CTRL1_AES
43594. DAR_ASM_CTRL1_CBC
43595. DAR_ASM_CTRL1_CLEAR
43596. DAR_ASM_CTRL1_CTR
43597. DAR_ASM_CTRL1_LOAD_MAC
43598. DAR_ASM_CTRL1_SELFTST
43599. DAR_ASM_CTRL1_START
43600. DAR_ASM_CTRL2
43601. DAR_ASM_CTRL2_DATA_REG_TYPE_SEL
43602. DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT
43603. DAR_ASM_CTRL2_TSTPAS
43604. DAR_ASM_DATA_0
43605. DAR_ASM_DATA_1
43606. DAR_ASM_DATA_2
43607. DAR_ASM_DATA_3
43608. DAR_ASM_DATA_4
43609. DAR_ASM_DATA_5
43610. DAR_ASM_DATA_6
43611. DAR_ASM_DATA_7
43612. DAR_ASM_DATA_8
43613. DAR_ASM_DATA_9
43614. DAR_ASM_DATA_A
43615. DAR_ASM_DATA_B
43616. DAR_ASM_DATA_C
43617. DAR_ASM_DATA_D
43618. DAR_ASM_DATA_E
43619. DAR_ASM_DATA_F
43620. DAR_BUFF_SIZE
43621. DAR_CCA1_ED_FNL
43622. DAR_CLK_OUT_CTRL
43623. DAR_CLK_OUT_CTRL_DIV
43624. DAR_CLK_OUT_CTRL_DS
43625. DAR_CLK_OUT_CTRL_EN
43626. DAR_CLK_OUT_CTRL_EXTEND
43627. DAR_CLK_OUT_CTRL_HIZ
43628. DAR_CLK_OUT_CTRL_SR
43629. DAR_EVENT_TMR_LSB
43630. DAR_EVENT_TMR_MSB
43631. DAR_EVENT_TMR_USB
43632. DAR_IRQSTS1_CCAIRQ
43633. DAR_IRQSTS1_FILTERFAIL_IRQ
43634. DAR_IRQSTS1_PLL_UNLOCK_IRQ
43635. DAR_IRQSTS1_RXIRQ
43636. DAR_IRQSTS1_RXWTRMRKIRQ
43637. DAR_IRQSTS1_RX_FRM_PEND
43638. DAR_IRQSTS1_SEQIRQ
43639. DAR_IRQSTS1_TXIRQ
43640. DAR_IRQSTS2_ASM_IRQ
43641. DAR_IRQSTS2_CCA
43642. DAR_IRQSTS2_CRCVALID
43643. DAR_IRQSTS2_PB_ERR_IRQ
43644. DAR_IRQSTS2_PI
43645. DAR_IRQSTS2_SRCADDR
43646. DAR_IRQSTS2_TMRSTATUS
43647. DAR_IRQSTS2_WAKE_IRQ
43648. DAR_IRQSTS3_TMR1IRQ
43649. DAR_IRQSTS3_TMR1MSK
43650. DAR_IRQSTS3_TMR2IRQ
43651. DAR_IRQSTS3_TMR2MSK
43652. DAR_IRQSTS3_TMR3IRQ
43653. DAR_IRQSTS3_TMR3MSK
43654. DAR_IRQSTS3_TMR4IRQ
43655. DAR_IRQSTS3_TMR4MSK
43656. DAR_IRQ_STS1
43657. DAR_IRQ_STS2
43658. DAR_IRQ_STS3
43659. DAR_LQI_VALUE
43660. DAR_OVERWRITE_VER
43661. DAR_PA_PWR
43662. DAR_PHY_CTRL1
43663. DAR_PHY_CTRL1_AUTOACK
43664. DAR_PHY_CTRL1_CCABFRTX
43665. DAR_PHY_CTRL1_CCABFRTX_SHIFT
43666. DAR_PHY_CTRL1_RXACKRQD
43667. DAR_PHY_CTRL1_SLOTTED
43668. DAR_PHY_CTRL1_TMRTRIGEN
43669. DAR_PHY_CTRL1_XCVSEQ_MASK
43670. DAR_PHY_CTRL2
43671. DAR_PHY_CTRL2_CCAMSK
43672. DAR_PHY_CTRL2_CRC_MSK
43673. DAR_PHY_CTRL2_FILTERFAIL_MSK
43674. DAR_PHY_CTRL2_PLL_UNLOCK_MSK
43675. DAR_PHY_CTRL2_RXMSK
43676. DAR_PHY_CTRL2_RX_WMRK_MSK
43677. DAR_PHY_CTRL2_SEQMSK
43678. DAR_PHY_CTRL2_TXMSK
43679. DAR_PHY_CTRL3
43680. DAR_PHY_CTRL3_ASM_MSK
43681. DAR_PHY_CTRL3_PB_ERR_MSK
43682. DAR_PHY_CTRL3_TMR1CMP_EN
43683. DAR_PHY_CTRL3_TMR2CMP_EN
43684. DAR_PHY_CTRL3_TMR3CMP_EN
43685. DAR_PHY_CTRL3_TMR4CMP_EN
43686. DAR_PHY_CTRL3_WAKE_MSK
43687. DAR_PHY_CTRL4
43688. DAR_PHY_CTRL4_CCATYPE
43689. DAR_PHY_CTRL4_CCATYPE_MASK
43690. DAR_PHY_CTRL4_CCATYPE_SHIFT
43691. DAR_PHY_CTRL4_PANCORDNTR0
43692. DAR_PHY_CTRL4_PROMISCUOUS
43693. DAR_PHY_CTRL4_TC2PRIME_EN
43694. DAR_PHY_CTRL4_TC3TMOUT
43695. DAR_PHY_CTRL4_TMRLOAD
43696. DAR_PHY_CTRL4_TRCV_MSK
43697. DAR_PLL_FRAC0_LSB
43698. DAR_PLL_FRAC0_MSB
43699. DAR_PLL_INT0
43700. DAR_PWR_MODES
43701. DAR_PWR_MODES_ASM_CLK_EN
43702. DAR_PWR_MODES_AUTODOZE
43703. DAR_PWR_MODES_PMC_MODE
43704. DAR_PWR_MODES_XTALEN
43705. DAR_PWR_MODES_XTAL_READY
43706. DAR_RSSI_CCA_CONT
43707. DAR_RX_FRAME_LENGTH_MASK
43708. DAR_RX_FRM_LEN
43709. DAR_SEQ_STATE
43710. DAR_SRC_ADDRS_SUM_LSB
43711. DAR_SRC_ADDRS_SUM_MSB
43712. DAR_SRC_CTRL
43713. DAR_SRC_CTRL_ACK_FRM_PND
43714. DAR_SRC_CTRL_INDEX
43715. DAR_SRC_CTRL_INDEX_DISABLE
43716. DAR_SRC_CTRL_INDEX_EN
43717. DAR_SRC_CTRL_INDEX_SHIFT
43718. DAR_SRC_CTRL_SRCADDR_EN
43719. DAR_T1CMP_LSB
43720. DAR_T1CMP_MSB
43721. DAR_T1CMP_USB
43722. DAR_T2CMP_LSB
43723. DAR_T2CMP_MSB
43724. DAR_T2CMP_USB
43725. DAR_T2PRIMECMP_LSB
43726. DAR_T2PRIMECMP_MSB
43727. DAR_T3CMP_LSB
43728. DAR_T3CMP_MSB
43729. DAR_T3CMP_USB
43730. DAR_T4CMP_LSB
43731. DAR_T4CMP_MSB
43732. DAR_T4CMP_USB
43733. DAR_TIMESTAMP_LSB
43734. DAR_TIMESTAMP_MSB
43735. DAR_TIMESTAMP_USB
43736. DAS08AOX_AO_LSB_REG
43737. DAS08AOX_AO_MSB_REG
43738. DAS08AOX_AO_UPDATE_REG
43739. DAS08JR_AO_LSB_REG
43740. DAS08JR_AO_MSB_REG
43741. DAS08JR_AO_UPDATE_REG
43742. DAS08JR_DI_REG
43743. DAS08JR_DO_REG
43744. DAS08_AI_LSB_REG
43745. DAS08_AI_MSB_REG
43746. DAS08_AI_TRIG_REG
43747. DAS08_CONTROL_DO
43748. DAS08_CONTROL_DO_MASK
43749. DAS08_CONTROL_INTE
43750. DAS08_CONTROL_MUX
43751. DAS08_CONTROL_MUX_MASK
43752. DAS08_CONTROL_REG
43753. DAS08_GAIN_REG
43754. DAS08_STATUS_AI_BUSY
43755. DAS08_STATUS_DI
43756. DAS08_STATUS_IRQ
43757. DAS08_STATUS_REG
43758. DAS1600_BURST_REG
43759. DAS1600_BURST_VAL
43760. DAS1600_CONV_DISABLE
43761. DAS1600_CONV_REG
43762. DAS1600_ENABLE_REG
43763. DAS1600_ENABLE_VAL
43764. DAS1600_STATUS_BME
43765. DAS1600_STATUS_CD
43766. DAS1600_STATUS_CLK_10MHZ
43767. DAS1600_STATUS_ME
43768. DAS1600_STATUS_REG
43769. DAS1600_STATUS_WS
43770. DAS16CS_AI_DATA_REG
43771. DAS16CS_AI_MUX_HI_CHAN
43772. DAS16CS_AI_MUX_LO_CHAN
43773. DAS16CS_AI_MUX_REG
43774. DAS16CS_AI_MUX_SINGLE_CHAN
43775. DAS16CS_DIO_REG
43776. DAS16CS_MISC1_AI_CONV
43777. DAS16CS_MISC1_AI_CONV_EXT_NEG
43778. DAS16CS_MISC1_AI_CONV_EXT_POS
43779. DAS16CS_MISC1_AI_CONV_MASK
43780. DAS16CS_MISC1_AI_CONV_PACER
43781. DAS16CS_MISC1_AI_CONV_SW
43782. DAS16CS_MISC1_DAC0CS
43783. DAS16CS_MISC1_DAC1CS
43784. DAS16CS_MISC1_DACCLK
43785. DAS16CS_MISC1_DACSD
43786. DAS16CS_MISC1_DAC_MASK
43787. DAS16CS_MISC1_EOC
43788. DAS16CS_MISC1_INTB
43789. DAS16CS_MISC1_INTE
43790. DAS16CS_MISC1_INT_SRC
43791. DAS16CS_MISC1_INT_SRC_EOS
43792. DAS16CS_MISC1_INT_SRC_EXT
43793. DAS16CS_MISC1_INT_SRC_FHF
43794. DAS16CS_MISC1_INT_SRC_FNE
43795. DAS16CS_MISC1_INT_SRC_MASK
43796. DAS16CS_MISC1_INT_SRC_NONE
43797. DAS16CS_MISC1_INT_SRC_PACER
43798. DAS16CS_MISC1_MA_MASK
43799. DAS16CS_MISC1_OVR
43800. DAS16CS_MISC1_REG
43801. DAS16CS_MISC1_SEDIFF
43802. DAS16CS_MISC2_AI_GAIN
43803. DAS16CS_MISC2_AI_GAIN_1
43804. DAS16CS_MISC2_AI_GAIN_2
43805. DAS16CS_MISC2_AI_GAIN_4
43806. DAS16CS_MISC2_AI_GAIN_8
43807. DAS16CS_MISC2_AI_GAIN_MASK
43808. DAS16CS_MISC2_BME
43809. DAS16CS_MISC2_CLK2
43810. DAS16CS_MISC2_CTR1
43811. DAS16CS_MISC2_FFNE
43812. DAS16CS_MISC2_LDIR
43813. DAS16CS_MISC2_REG
43814. DAS16CS_MISC2_TRG0
43815. DAS16CS_MISC2_TRGCLR
43816. DAS16CS_MISC2_TRGPOL
43817. DAS16CS_MISC2_TRGSEL
43818. DAS16CS_MISC2_UDIR
43819. DAS16CS_TIMER_BASE
43820. DAS16M1_8254_IOBASE1
43821. DAS16M1_8254_IOBASE2
43822. DAS16M1_8254_IOBASE3
43823. DAS16M1_8255_IOBASE
43824. DAS16M1_AI_FIFO_SZ
43825. DAS16M1_AI_REG
43826. DAS16M1_AI_TO_CHAN
43827. DAS16M1_AI_TO_SAMPLE
43828. DAS16M1_CLR_INTR_REG
43829. DAS16M1_CS_EXT_TRIG
43830. DAS16M1_CS_IRQDATA
43831. DAS16M1_CS_OVRUN
43832. DAS16M1_CS_REG
43833. DAS16M1_DI_REG
43834. DAS16M1_DO_REG
43835. DAS16M1_INTR_CTRL_INTE
43836. DAS16M1_INTR_CTRL_IRQ
43837. DAS16M1_INTR_CTRL_PACER
43838. DAS16M1_INTR_CTRL_PACER_EXT
43839. DAS16M1_INTR_CTRL_PACER_INT
43840. DAS16M1_INTR_CTRL_PACER_MASK
43841. DAS16M1_INTR_CTRL_REG
43842. DAS16M1_Q_ADDR_REG
43843. DAS16M1_Q_CHAN
43844. DAS16M1_Q_RANGE
43845. DAS16M1_Q_REG
43846. DAS16M1_SIZE2
43847. DAS16_AI_LSB_REG
43848. DAS16_AI_MSB_REG
43849. DAS16_AO_LSB_REG
43850. DAS16_AO_MSB_REG
43851. DAS16_CTRL_DMAE
43852. DAS16_CTRL_EXT_PACER
43853. DAS16_CTRL_INTE
43854. DAS16_CTRL_INT_PACER
43855. DAS16_CTRL_IRQ
43856. DAS16_CTRL_PACING_MASK
43857. DAS16_CTRL_REG
43858. DAS16_CTRL_SOFT_PACER
43859. DAS16_DIO_REG
43860. DAS16_DMA_SIZE
43861. DAS16_GAIN_REG
43862. DAS16_MUX_REG
43863. DAS16_PACER_BURST_LEN
43864. DAS16_PACER_CTR0
43865. DAS16_PACER_REG
43866. DAS16_PACER_TRIG0
43867. DAS16_STATUS_BUSY
43868. DAS16_STATUS_INT
43869. DAS16_STATUS_MUXBIT
43870. DAS16_STATUS_REG
43871. DAS16_STATUS_UNIPOLAR
43872. DAS16_TIMER_BASE_REG
43873. DAS16_TRIG_REG
43874. DAS1800_BURST_LENGTH
43875. DAS1800_BURST_RATE
43876. DAS1800_CONTROL_A
43877. DAS1800_CONTROL_B
43878. DAS1800_CONTROL_C
43879. DAS1800_COUNTER
43880. DAS1800_DAC
43881. DAS1800_DIGITAL
43882. DAS1800_FIFO
43883. DAS1800_ID_AO
43884. DAS1800_ID_HC
43885. DAS1800_ID_HR
43886. DAS1800_ID_HR_DA
43887. DAS1800_ID_ST
43888. DAS1800_ID_ST_DA
43889. DAS1800_QRAM
43890. DAS1800_QRAM_ADDRESS
43891. DAS1800_SELECT
43892. DAS1800_SIZE
43893. DAS1800_STATUS
43894. DAS6402_AI_DATA_REG
43895. DAS6402_AI_MUX_HI
43896. DAS6402_AI_MUX_LO
43897. DAS6402_AI_MUX_REG
43898. DAS6402_AO_DATA_REG
43899. DAS6402_AO_LSB_REG
43900. DAS6402_AO_MSB_REG
43901. DAS6402_AO_RANGE
43902. DAS6402_AO_RANGE_MASK
43903. DAS6402_CTRL_BURSTEN
43904. DAS6402_CTRL_EXT_FALL_TRIG
43905. DAS6402_CTRL_EXT_RISE_TRIG
43906. DAS6402_CTRL_INTE
43907. DAS6402_CTRL_IRQ
43908. DAS6402_CTRL_PACER_TRIG
43909. DAS6402_CTRL_REG
43910. DAS6402_CTRL_SOFT_TRIG
43911. DAS6402_CTRL_TRIG
43912. DAS6402_CTRL_XINTE
43913. DAS6402_DI_DO_REG
43914. DAS6402_MODE_DMA
43915. DAS6402_MODE_DMA1
43916. DAS6402_MODE_DMA3
43917. DAS6402_MODE_ENHANCED
43918. DAS6402_MODE_EOB
43919. DAS6402_MODE_FIFOHFULL
43920. DAS6402_MODE_FIFONEPTY
43921. DAS6402_MODE_POLLED
43922. DAS6402_MODE_RANGE
43923. DAS6402_MODE_REG
43924. DAS6402_MODE_SE
43925. DAS6402_MODE_UNI
43926. DAS6402_STATUS_10MHZ
43927. DAS6402_STATUS_FFNE
43928. DAS6402_STATUS_FFULL
43929. DAS6402_STATUS_FHALF
43930. DAS6402_STATUS_INDGT
43931. DAS6402_STATUS_INT
43932. DAS6402_STATUS_REG
43933. DAS6402_STATUS_W_10MHZ
43934. DAS6402_STATUS_W_ARMED
43935. DAS6402_STATUS_W_CLRINT
43936. DAS6402_STATUS_W_CLRXIN
43937. DAS6402_STATUS_W_CLRXTR
43938. DAS6402_STATUS_W_EXTEND
43939. DAS6402_STATUS_W_POSTMODE
43940. DAS6402_STATUS_XINT
43941. DAS6402_STATUS_XTRIG
43942. DAS6402_TIMER_BASE
43943. DAS6402_TRIG_PRETRIG
43944. DAS6402_TRIG_REG
43945. DAS6402_TRIG_TGEN
43946. DAS6402_TRIG_TGPOL
43947. DAS6402_TRIG_TGSEL
43948. DAS800_8254
43949. DAS800_CONTROL1
43950. DAS800_CONV_CONTROL
43951. DAS800_GAIN
43952. DAS800_ID
43953. DAS800_LSB
43954. DAS800_MSB
43955. DAS800_SCAN_LIMITS
43956. DAS800_STATUS
43957. DAS800_STATUS2
43958. DAS802_16_HALF_FIFO_SZ
43959. DASDAPIVER
43960. DASDLIMIT
43961. DASDUSED
43962. DASD_API_VERSION
43963. DASD_BUS_ID_SIZE
43964. DASD_BYPASS_CACHE
43965. DASD_CHANQ_MAX_SIZE
43966. DASD_CQR_ALLOW_SLOCK
43967. DASD_CQR_CLEARED
43968. DASD_CQR_CLEAR_PENDING
43969. DASD_CQR_DONE
43970. DASD_CQR_ERROR
43971. DASD_CQR_FAILED
43972. DASD_CQR_FILLED
43973. DASD_CQR_FLAGS_FAILFAST
43974. DASD_CQR_FLAGS_USE_ERP
43975. DASD_CQR_IN_ERP
43976. DASD_CQR_IN_IO
43977. DASD_CQR_MAX_CCW
43978. DASD_CQR_NEED_ERP
43979. DASD_CQR_QUEUED
43980. DASD_CQR_SUCCESS
43981. DASD_CQR_SUPPRESS_CR
43982. DASD_CQR_SUPPRESS_FP
43983. DASD_CQR_SUPPRESS_IL
43984. DASD_CQR_SUPPRESS_NRF
43985. DASD_CQR_TERMINATED
43986. DASD_CQR_VERIFY_PATH
43987. DASD_DEFINE_ATTR
43988. DASD_DIAG_CODE_31BIT
43989. DASD_DIAG_CODE_64BIT
43990. DASD_DIAG_FLAGA_DEFAULT
43991. DASD_DIAG_FLAGA_FORMAT_64BIT
43992. DASD_DIAG_MAGIC
43993. DASD_DIAG_MOD
43994. DASD_DIAG_RWFLAG_ASYNC
43995. DASD_DIAG_RWFLAG_NOCACHE
43996. DASD_ECKD_CCW_DEFINE_EXTENT
43997. DASD_ECKD_CCW_DSO
43998. DASD_ECKD_CCW_ERASE
43999. DASD_ECKD_CCW_LOCATE_RECORD
44000. DASD_ECKD_CCW_LOCATE_RECORD_EXT
44001. DASD_ECKD_CCW_PFX
44002. DASD_ECKD_CCW_PFX_READ
44003. DASD_ECKD_CCW_PSF
44004. DASD_ECKD_CCW_RCD
44005. DASD_ECKD_CCW_READ
44006. DASD_ECKD_CCW_READ_CKD
44007. DASD_ECKD_CCW_READ_CKD_MT
44008. DASD_ECKD_CCW_READ_COUNT
44009. DASD_ECKD_CCW_READ_COUNT_MT
44010. DASD_ECKD_CCW_READ_HOME_ADDRESS
44011. DASD_ECKD_CCW_READ_KD
44012. DASD_ECKD_CCW_READ_KD_MT
44013. DASD_ECKD_CCW_READ_MT
44014. DASD_ECKD_CCW_READ_RECORD_ZERO
44015. DASD_ECKD_CCW_READ_TRACK
44016. DASD_ECKD_CCW_READ_TRACK_DATA
44017. DASD_ECKD_CCW_RELEASE
44018. DASD_ECKD_CCW_RESERVE
44019. DASD_ECKD_CCW_RSCK
44020. DASD_ECKD_CCW_RSSD
44021. DASD_ECKD_CCW_SLCK
44022. DASD_ECKD_CCW_SNID
44023. DASD_ECKD_CCW_SNSS
44024. DASD_ECKD_CCW_WRITE
44025. DASD_ECKD_CCW_WRITE_CKD
44026. DASD_ECKD_CCW_WRITE_CKD_MT
44027. DASD_ECKD_CCW_WRITE_FULL_TRACK
44028. DASD_ECKD_CCW_WRITE_HOME_ADDRESS
44029. DASD_ECKD_CCW_WRITE_KD
44030. DASD_ECKD_CCW_WRITE_KD_MT
44031. DASD_ECKD_CCW_WRITE_MT
44032. DASD_ECKD_CCW_WRITE_RECORD_ZERO
44033. DASD_ECKD_CCW_WRITE_TRACK_DATA
44034. DASD_ECKD_CHANQ_MAX_SIZE
44035. DASD_ECKD_H
44036. DASD_ECKD_MAGIC
44037. DASD_ECKD_MAX_BLOCKS
44038. DASD_ECKD_MAX_BLOCKS_RAW
44039. DASD_ECKD_PATH_INTERVAL
44040. DASD_ECKD_PATH_THRHLD
44041. DASD_ECKD_PG_GROUPED
44042. DASD_ECKD_RAS_EXTS_MAX
44043. DASD_ECKD_RCD_DATA_SIZE
44044. DASD_EER_BUSID_SIZE
44045. DASD_EER_DISABLE
44046. DASD_EER_FATALERROR
44047. DASD_EER_NOPATH
44048. DASD_EER_NOSPC
44049. DASD_EER_PPRCSUSPEND
44050. DASD_EER_STATECHANGE
44051. DASD_EER_TRIGGER
44052. DASD_EXPIRES
44053. DASD_EXPIRES_MAX
44054. DASD_FBA_CCW_DEFINE_EXTENT
44055. DASD_FBA_CCW_LOCATE
44056. DASD_FBA_CCW_READ
44057. DASD_FBA_CCW_WRITE
44058. DASD_FBA_H
44059. DASD_FBA_MAGIC
44060. DASD_FBA_MAX_BLOCKS
44061. DASD_FEATURE_DEFAULT
44062. DASD_FEATURE_DISCARD
44063. DASD_FEATURE_ERPLOG
44064. DASD_FEATURE_FAILFAST
44065. DASD_FEATURE_FAILONSLCK
44066. DASD_FEATURE_INITIAL_ONLINE
44067. DASD_FEATURE_PATH_AUTODISABLE
44068. DASD_FEATURE_READONLY
44069. DASD_FEATURE_USEDIAG
44070. DASD_FEATURE_USERAW
44071. DASD_FLAG_ABORTALL
44072. DASD_FLAG_DEVICE_RO
44073. DASD_FLAG_EER_IN_USE
44074. DASD_FLAG_EER_SNSS
44075. DASD_FLAG_IS_RESERVED
44076. DASD_FLAG_LOCK_STOLEN
44077. DASD_FLAG_OFFLINE
44078. DASD_FLAG_PATH_VERIFY
44079. DASD_FLAG_SAFE_OFFLINE
44080. DASD_FLAG_SAFE_OFFLINE_RUNNING
44081. DASD_FLAG_SUC
44082. DASD_FLAG_SUSPENDED
44083. DASD_FMT_ERR_BLKSIZE
44084. DASD_FMT_ERR_KEY_LENGTH
44085. DASD_FMT_ERR_RECORD_ID
44086. DASD_FMT_ERR_TOO_FEW_RECORDS
44087. DASD_FMT_ERR_TOO_MANY_RECORDS
44088. DASD_FMT_INT_COMPAT
44089. DASD_FMT_INT_ESE_FULL
44090. DASD_FMT_INT_FMT_HA
44091. DASD_FMT_INT_FMT_NOR0
44092. DASD_FMT_INT_FMT_R0
44093. DASD_FMT_INT_INVAL
44094. DASD_FORMAT_CDL
44095. DASD_FORMAT_LDL
44096. DASD_FORMAT_NONE
44097. DASD_H
44098. DASD_INHIBIT_LOAD
44099. DASD_INTERVAL_MAX
44100. DASD_INT_H
44101. DASD_IOCTL_LETTER
44102. DASD_IPLDEV
44103. DASD_MAJOR
44104. DASD_MAX_PARAMS
44105. DASD_NORMAL_CACHE
44106. DASD_PARTN_BITS
44107. DASD_PARTN_MASK
44108. DASD_PATH_CUIR
44109. DASD_PATH_IFCC
44110. DASD_PATH_MISCABLED
44111. DASD_PATH_NOHPF
44112. DASD_PATH_NPP
44113. DASD_PATH_OPERATIONAL
44114. DASD_PATH_PP
44115. DASD_PATH_TBV
44116. DASD_PER_MAJOR
44117. DASD_PROFILE_GLOBAL_ONLY
44118. DASD_PROFILE_OFF
44119. DASD_PROFILE_ON
44120. DASD_RAW_BLOCKSIZE
44121. DASD_RAW_BLOCK_PER_TRACK
44122. DASD_RAW_SECTORS_PER_TRACK
44123. DASD_REC_ACCESS
44124. DASD_REQ_PER_DEV
44125. DASD_RETRIES
44126. DASD_RETRIES_MAX
44127. DASD_SENSE_BIT_0
44128. DASD_SENSE_BIT_1
44129. DASD_SENSE_BIT_2
44130. DASD_SENSE_BIT_3
44131. DASD_SEQ_ACCESS
44132. DASD_SEQ_PRESTAGE
44133. DASD_SIM_LOG
44134. DASD_SIM_MSG_TO_OP
44135. DASD_SIM_SENSE
44136. DASD_SLEEPON_END_TAG
44137. DASD_SLEEPON_START_TAG
44138. DASD_STATE_BASIC
44139. DASD_STATE_KNOWN
44140. DASD_STATE_NEW
44141. DASD_STATE_ONLINE
44142. DASD_STATE_READY
44143. DASD_STATE_UNFMT
44144. DASD_STOPPED_DC_WAIT
44145. DASD_STOPPED_NOSPC
44146. DASD_STOPPED_NOT_ACC
44147. DASD_STOPPED_PENDING
44148. DASD_STOPPED_PM
44149. DASD_STOPPED_QUIESCE
44150. DASD_STOPPED_SU
44151. DASD_SUPPORT
44152. DASD_THRHLD_MAX
44153. DASD_UNRESUMED_PM
44154. DASFV2_ROCEE_CRD_NUM
44155. DASH_HZ
44156. DAS_AVAIL
44157. DAS_BYP_INS
44158. DAS_BYP_RMV
44159. DAS_BYP_ST
44160. DAT
44161. DAT1BYTE
44162. DAT2BYTE
44163. DATA
44164. DATA0
44165. DATA0_PID
44166. DATA1
44167. DATA16
44168. DATA1_PID
44169. DATA2
44170. DATA2_PID
44171. DATA32
44172. DATA8BIT
44173. DATAADDR_LEN
44174. DATAADDR_POS
44175. DATABUF_OFFSET
44176. DATADIGEST
44177. DATADIPHIT_F
44178. DATADIPHIT_S
44179. DATADIPHIT_V
44180. DATADIR_IN
44181. DATADIR_OUT
44182. DATADUR_A
44183. DATADUR_A_F0
44184. DATADUR_A_F1
44185. DATADUR_B
44186. DATAEN_ACTIVE_LOW
44187. DATAFLASH_SHIFT_EXTID
44188. DATAFLASH_SHIFT_ID
44189. DATAFORMAT
44190. DATAHD
44191. DATAHOFST
44192. DATAIN
44193. DATAIN_COMPLETE_CONNECTION_RECOVERY
44194. DATAIN_COMPLETE_NORMAL
44195. DATAIN_COMPLETE_WITHIN_COMMAND_RECOVERY
44196. DATAIN_CONNECTION_RECOVERY
44197. DATAIN_WITHIN_COMMAND_RECOVERY
44198. DATALEN_MASK
44199. DATALEN_MSG
44200. DATALEN_SEG
44201. DATALKPTYPE_G
44202. DATALKPTYPE_M
44203. DATALKPTYPE_S
44204. DATALKPTYPE_V
44205. DATAMODUL_MODE_CONTINUOUS
44206. DATAMODUL_MODE_CONTINUOUS_NOSYNC
44207. DATAMODUL_MODE_PACKET
44208. DATAMODUL_MODULATION_SHAPE_0_3
44209. DATAMODUL_MODULATION_SHAPE_0_5
44210. DATAMODUL_MODULATION_SHAPE_1_0
44211. DATAMODUL_MODULATION_SHAPE_2BR
44212. DATAMODUL_MODULATION_SHAPE_BR
44213. DATAMODUL_MODULATION_SHAPE_NONE
44214. DATAMODUL_MODULATION_TYPE_FSK
44215. DATAMODUL_MODULATION_TYPE_OOK
44216. DATAMOVER_ADDR
44217. DATAOFST
44218. DATAOF_TRACE_ENTRY
44219. DATAOK
44220. DATAOUT
44221. DATAOUT_CANNOT_RECOVER
44222. DATAOUT_NORMAL
44223. DATAOUT_PDU_SENT
44224. DATAOUT_SEND_R2T
44225. DATAOUT_SEND_TO_TRANSPORT
44226. DATAOUT_SEQUENCE_COMPLETE
44227. DATAOUT_SEQUENCE_GOT_R2T
44228. DATAOUT_SEQUENCE_WITHIN_COMMAND_RECOVERY
44229. DATAOUT_WITHIN_COMMAND_RECOVERY
44230. DATAPATH_H
44231. DATAPDUINORDER
44232. DATAPILOT_U2_PRODUCT_ID
44233. DATAPILOT_U2_VENDOR_ID
44234. DATAPORT
44235. DATAPORTNUM_G
44236. DATAPORTNUM_M
44237. DATAPORTNUM_S
44238. DATAPORTNUM_V
44239. DATAREG
44240. DATASEQUENCEINORDER
44241. DATASET_A
44242. DATASET_AB
44243. DATASET_B
44244. DATASIZE
44245. DATASLOTSIZE
44246. DATAVIDH1_G
44247. DATAVIDH1_M
44248. DATAVIDH1_S
44249. DATAVIDH2_F
44250. DATAVIDH2_S
44251. DATAVIDH2_V
44252. DATAVOFST
44253. DATAX0
44254. DATAX1
44255. DATAY0
44256. DATAY1
44257. DATAZ0
44258. DATAZ1
44259. DATA_0
44260. DATA_1
44261. DATA_1_DELAY
44262. DATA_2
44263. DATA_240A_OFFSET
44264. DATA_99
44265. DATA_ABORT
44266. DATA_AHB_CLK_CGC_ON
44267. DATA_ATTR
44268. DATA_AUTOINC
44269. DATA_A_IN_1
44270. DATA_A_IN_2
44271. DATA_A_OUT
44272. DATA_B
44273. DATA_BIT_WIDTH_10
44274. DATA_BIT_WIDTH_20
44275. DATA_BIT_WIDTH_40
44276. DATA_BLIND_DEF
44277. DATA_BLIND_VAL
44278. DATA_BLOB_LENGTH
44279. DATA_BLOCK_BITS_DEF
44280. DATA_BLOCK_CEA_TIMING
44281. DATA_BLOCK_COLOR_CHARACTERISTICS
44282. DATA_BLOCK_CONTENT_SIZE
44283. DATA_BLOCK_CTA
44284. DATA_BLOCK_DISPLAY_DEVICE_DATA
44285. DATA_BLOCK_DISPLAY_INTERFACE
44286. DATA_BLOCK_DISPLAY_PARAMETERS
44287. DATA_BLOCK_FOOTER_SIZE
44288. DATA_BLOCK_GP_ASCII_STRING
44289. DATA_BLOCK_HEADER_SIZE
44290. DATA_BLOCK_INTERFACE_POWER_SEQUENCING
44291. DATA_BLOCK_PRODUCT_ID
44292. DATA_BLOCK_PRODUCT_SERIAL_NUMBER
44293. DATA_BLOCK_SHIFT
44294. DATA_BLOCK_SIZE
44295. DATA_BLOCK_STEREO_DISPLAY_INTERFACE
44296. DATA_BLOCK_TILED_DISPLAY
44297. DATA_BLOCK_TRANSFER_CHARACTERISTICS
44298. DATA_BLOCK_TX_SUPR
44299. DATA_BLOCK_TYPE_1_DETAILED_TIMING
44300. DATA_BLOCK_TYPE_2_DETAILED_TIMING
44301. DATA_BLOCK_TYPE_3_SHORT_TIMING
44302. DATA_BLOCK_TYPE_4_DMT_TIMING
44303. DATA_BLOCK_VENDOR_SPECIFIC
44304. DATA_BLOCK_VESA_TIMING
44305. DATA_BLOCK_VIDEO_TIMING_RANGE
44306. DATA_BMP_LOAD
44307. DATA_BU
44308. DATA_BUFF0_BASE
44309. DATA_BUFF0_SIZE
44310. DATA_BUFF1_BASE
44311. DATA_BUFF1_SIZE
44312. DATA_BUFF2_BASE
44313. DATA_BUFF2_SIZE
44314. DATA_BUFF3_BASE
44315. DATA_BUFF3_SIZE
44316. DATA_BUFFER_STATUS_LEVEL
44317. DATA_BUFFER_STATUS_LEVEL_TX
44318. DATA_BUFFER_THLD_CTRL
44319. DATA_BUFFER_THLD_CTRL_RX_BUF
44320. DATA_BUFSIZE
44321. DATA_BUF_OVERFLOW_INT
44322. DATA_BUF_SIZE_OFFSET
44323. DATA_BUF_SZ
44324. DATA_BUF_XFERS
44325. DATA_BUS_ACCESS_MODE_16BIT
44326. DATA_BUS_ACCESS_MODE_8BIT
44327. DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT
44328. DATA_BW
44329. DATA_BYTE_SWAP
44330. DATA_CACHE
44331. DATA_CACHE_MODE
44332. DATA_CARRY
44333. DATA_CHANGED
44334. DATA_CHAR
44335. DATA_CHAR_1
44336. DATA_CI_GET
44337. DATA_CI_PUT
44338. DATA_CNT
44339. DATA_COLUMN_MASK
44340. DATA_COMMON_INTERFACE
44341. DATA_COMPL
44342. DATA_CORR
44343. DATA_CRC_FAIL
44344. DATA_CRC_OK
44345. DATA_CTRL
44346. DATA_D
44347. DATA_DATA
44348. DATA_DEBUG_MESSAGE
44349. DATA_DEV_BLOCK_SIZE_MAX_SECTORS
44350. DATA_DEV_BLOCK_SIZE_MIN_SECTORS
44351. DATA_DIRECT
44352. DATA_DIR_BYRECIPIENT
44353. DATA_DIR_FROM_HOST
44354. DATA_DIR_IN
44355. DATA_DIR_NONE
44356. DATA_DIR_OUT
44357. DATA_DIR_RX
44358. DATA_DIR_TO_HOST
44359. DATA_DIR_TX
44360. DATA_DIR_UNKNOWN
44361. DATA_DMA_CTRL
44362. DATA_DONE_EN
44363. DATA_DONE_INT
44364. DATA_DONE_INT_EN
44365. DATA_DONE_MASK
44366. DATA_DONE_ST
44367. DATA_DRQ_EN
44368. DATA_DT
44369. DATA_ECHO
44370. DATA_ENABLE
44371. DATA_END
44372. DATA_ENDIAN
44373. DATA_EQU_PREV
44374. DATA_ERROR
44375. DATA_ESCAPE
44376. DATA_FIFO_AREA
44377. DATA_FMT_DIGEST
44378. DATA_FMT_DIGEST_WITH_ALGO
44379. DATA_FMT_HEX
44380. DATA_FMT_STRING
44381. DATA_FORCE_STOP
44382. DATA_FORMAT
44383. DATA_FORMAT_MSK
44384. DATA_FORMAT_RGB
44385. DATA_FORMAT_YUV
44386. DATA_FRAGMENT
44387. DATA_FRAMETAG
44388. DATA_FRAME_SIZE
44389. DATA_FRAME_WS_HEADER_SIZE
44390. DATA_FROM_PC_READY
44391. DATA_FROM_TABLE
44392. DATA_FSECTION
44393. DATA_GA
44394. DATA_GATE_EN
44395. DATA_GENERIC
44396. DATA_GENERIC_ENHANCE
44397. DATA_GENERIC_ENHANCE_READ
44398. DATA_GO
44399. DATA_H
44400. DATA_HEADER
44401. DATA_ID
44402. DATA_IN
44403. DATA_INT_CLR
44404. DATA_INT_EXT
44405. DATA_IN_AREA
44406. DATA_IN_DIR
44407. DATA_IN_PAGE
44408. DATA_IN_PHASE
44409. DATA_IN_PIPE_ID
44410. DATA_IN_ST
44411. DATA_IN_TOKEN_INTERRUPT
44412. DATA_IN_TOKEN_INTERRUPT_ENABLE
44413. DATA_IN_URB_INFLIGHT
44414. DATA_IPMPE
44415. DATA_IRCOMMAND
44416. DATA_IRQ_EN
44417. DATA_K_VALUE_SEL
44418. DATA_L
44419. DATA_LANES_PRG_REG_MASK
44420. DATA_LANES_PRG_REG_SHIFT
44421. DATA_LANE_EN
44422. DATA_LANE_RDY
44423. DATA_LANE_START
44424. DATA_LANE_STATE
44425. DATA_LANE_ULPM_REQ
44426. DATA_LANE_ULPOUT_TIME
44427. DATA_LAST_BLOCK_CONTENT_SIZE
44428. DATA_LAST_BLOCK_SIZE
44429. DATA_LATCHING
44430. DATA_LE32
44431. DATA_LEFT
44432. DATA_LEFT_ALIGN
44433. DATA_LEN
44434. DATA_LENGTH_MASK
44435. DATA_LENGTH_SHIFT
44436. DATA_LEN_MASK
44437. DATA_LINK_ACTIVE
44438. DATA_LINK_M_N_MASK
44439. DATA_LINK_N_MAX
44440. DATA_LOST
44441. DATA_MAIN
44442. DATA_MASK
44443. DATA_MAX
44444. DATA_MEM_ADDRESS_MASK
44445. DATA_MEM_ADDRESS_SHIFT
44446. DATA_MIPI_CSI
44447. DATA_MODE_GET_FREE_PAGES
44448. DATA_MODE_LIMIT
44449. DATA_MODE_SLAB
44450. DATA_MODE_VMALLOC
44451. DATA_MPEG_PLAY
44452. DATA_MPEG_RECORD
44453. DATA_MPEG_VIDEO_EVENT
44454. DATA_MSGTYPE
44455. DATA_NAME
44456. DATA_NODE_ATTR
44457. DATA_NONE
44458. DATA_OFFSET
44459. DATA_ONLY
44460. DATA_OPT1_TLV_TYPE
44461. DATA_OPT2_TLV_TYPE
44462. DATA_OUT
44463. DATA_OUTBUF
44464. DATA_OUT_AREA
44465. DATA_OUT_DIR
44466. DATA_OUT_PHASE
44467. DATA_OUT_PING_TOKEN_INTERRUPT
44468. DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE
44469. DATA_OUT_PIPE_ID
44470. DATA_OUT_ST
44471. DATA_OUT_TOKEN_INTERRUPT
44472. DATA_OUT_TOKEN_INTERRUPT_ENABLE
44473. DATA_OUT_URB_INFLIGHT
44474. DATA_OVER_UNDER
44475. DATA_PACKET_RECEIVED_INTERRUPT
44476. DATA_PACKET_RECEIVED_INTERRUPT_ENABLE
44477. DATA_PACKET_TRANSMITTED_INTERRUPT
44478. DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE
44479. DATA_PARTITION_SIZE_KiB
44480. DATA_PATH
44481. DATA_PATH_GROUP
44482. DATA_PA_TO_VA
44483. DATA_PES_PLAY
44484. DATA_PES_RECORD
44485. DATA_PHASE
44486. DATA_PINS_BITS
44487. DATA_PINS_MASK
44488. DATA_PINS_PER_REG
44489. DATA_PIPING
44490. DATA_PIPING_FLAG
44491. DATA_PKT_RX_EN
44492. DATA_PKT_SZ
44493. DATA_PKT_SZ_1K
44494. DATA_PKT_SZ_256
44495. DATA_PKT_SZ_4K
44496. DATA_PKT_SZ_512
44497. DATA_PKT_SZ_8K
44498. DATA_PKT_TX_EN
44499. DATA_PLANE_PURGE
44500. DATA_PORT
44501. DATA_PORT_OFF
44502. DATA_PRESENT
44503. DATA_PROCESSING16
44504. DATA_PROCESSING32_DM
44505. DATA_PROCESSING32_DNM
44506. DATA_PROCESSING32_NM
44507. DATA_PROCESSING_DM
44508. DATA_PROCESSING_DNM
44509. DATA_PROCESSING_NM
44510. DATA_PROTECT
44511. DATA_PTR
44512. DATA_QUEUE_WATER_MARK
44513. DATA_RAM0
44514. DATA_RAM_SIZE
44515. DATA_RATE_MAX_SPEED
44516. DATA_RATE_MIN_SPEED
44517. DATA_RCV_EPT
44518. DATA_RD_STATIC_64
44519. DATA_RD_SWAP
44520. DATA_READ
44521. DATA_READY
44522. DATA_REC
44523. DATA_RECEIVED
44524. DATA_REG
44525. DATA_REG0
44526. DATA_REGS_OFFSET
44527. DATA_REG_HI
44528. DATA_REG_LOW
44529. DATA_REG_OFFSET
44530. DATA_REQ1_TLV_TYPE
44531. DATA_RESP1_TLV_TYPE
44532. DATA_RI
44533. DATA_ROW_MASK
44534. DATA_RX_ZONE
44535. DATA_S
44536. DATA_S1
44537. DATA_S2
44538. DATA_S3
44539. DATA_SC_SHT
44540. DATA_SECTIONS
44541. DATA_SEC_ERASE
44542. DATA_SEL
44543. DATA_SGE
44544. DATA_SHIFT
44545. DATA_SHORT
44546. DATA_SIZE
44547. DATA_SIZE_BITS
44548. DATA_SLOT_2
44549. DATA_SND_EPT
44550. DATA_SNOOP_ENABLE_V1
44551. DATA_SNOOP_ENABLE_V2
44552. DATA_STAGE
44553. DATA_STAGE_IN
44554. DATA_STAGE_OUT
44555. DATA_STATE_NEED_ZLP
44556. DATA_STATE_RECV
44557. DATA_STATE_XMIT
44558. DATA_STORAGE_EXCEPTION
44559. DATA_STREAMING
44560. DATA_STRING_LEN
44561. DATA_STROB
44562. DATA_STROBE_EN
44563. DATA_STROB_DELAY_2CYC
44564. DATA_STROB_EDO_EN
44565. DATA_STROB_INV_POL
44566. DATA_STRUCTURE_VER_OFFSET
44567. DATA_SWAP_ENABLE
44568. DATA_TABLES
44569. DATA_THS_PREPARE
44570. DATA_THS_TRAIL
44571. DATA_THS_ZERO
44572. DATA_TIMEOUT
44573. DATA_TLPX
44574. DATA_TO_ANY_EXIT
44575. DATA_TO_ANY_INIT
44576. DATA_TO_FLASH
44577. DATA_TO_PC_READY
44578. DATA_TRAN_DONE
44579. DATA_TS_PLAY
44580. DATA_TS_RECORD
44581. DATA_TTA_GET
44582. DATA_TTA_GO
44583. DATA_TWAKEUP
44584. DATA_TX_ZONE
44585. DATA_TYPE
44586. DATA_TYPE_ABGR24_6666
44587. DATA_TYPE_ABGR32_8888
44588. DATA_TYPE_ABGR_1555
44589. DATA_TYPE_ABGR_4444
44590. DATA_TYPE_ARGB24_6666
44591. DATA_TYPE_ARGB32_8888
44592. DATA_TYPE_ARGB_1555
44593. DATA_TYPE_ARGB_4444
44594. DATA_TYPE_BGR16_565
44595. DATA_TYPE_BGR24_888
44596. DATA_TYPE_BGRA24_6666
44597. DATA_TYPE_BGRA32_8888
44598. DATA_TYPE_BGRA_4444
44599. DATA_TYPE_BGRA_5551
44600. DATA_TYPE_C420
44601. DATA_TYPE_C422
44602. DATA_TYPE_C444
44603. DATA_TYPE_CBY422
44604. DATA_TYPE_CRY422
44605. DATA_TYPE_EMBEDDED_DATA_8BIT
44606. DATA_TYPE_MASK
44607. DATA_TYPE_MV
44608. DATA_TYPE_RAW_10BIT
44609. DATA_TYPE_RAW_12BIT
44610. DATA_TYPE_RAW_14BIT
44611. DATA_TYPE_RAW_6BIT
44612. DATA_TYPE_RAW_8BIT
44613. DATA_TYPE_RGB16_565
44614. DATA_TYPE_RGB24_888
44615. DATA_TYPE_RGBA24_6666
44616. DATA_TYPE_RGBA32_8888
44617. DATA_TYPE_RGBA_4444
44618. DATA_TYPE_RGBA_5551
44619. DATA_TYPE_SHIFT
44620. DATA_TYPE_Y420
44621. DATA_TYPE_Y422
44622. DATA_TYPE_Y444
44623. DATA_TYPE_YC444
44624. DATA_TYPE_YCB422
44625. DATA_TYPE_YCR422
44626. DATA_TYPE_YUV422_8BIT
44627. DATA_ULPM_EN
44628. DATA_UNCORR
44629. DATA_VALID
44630. DATA_VA_TO_PA
44631. DATA_V_IN_1
44632. DATA_V_IN_2
44633. DATA_V_OUT
44634. DATA_W
44635. DATA_WIDTH
44636. DATA_WINDOW
44637. DATA_WR_STATIC_64
44638. DATA_WR_SWAP
44639. DATA_XFER_MODE_DMA
44640. DATA_XFER_SZ
44641. DATA_ZONE
44642. DATE_CENTURY_S
44643. DATE_DAY_MASK
44644. DATE_MONTH_MASK
44645. DATE_MONTH_S
44646. DATE_REG
44647. DATE_YEAR_MASK
44648. DATE_YEAR_S
44649. DATIMER_VAL
44650. DAT_CLR_BUF
44651. DAT_ERR
44652. DAT_GET_DEV_STAT
44653. DAT_GET_ERR_CODE
44654. DAT_ILLEGAL
44655. DAT_OFFSET
44656. DAT_PRTCT
44657. DAT_RD_ERR_STAT
44658. DAT_RD_FRAME
44659. DAT_RD_TEST
44660. DAT_REMAP_CFG
44661. DAT_SEL_EP
44662. DAT_SEL_EP_CLRI
44663. DAT_TIMEOUT
44664. DAT_WR_BYTE
44665. DAUGHTER_ID
44666. DAUGHTER_TYPEVER_MASK
44667. DAUGHTER_TYPE_MASK
44668. DAUGHTER_VER_MASK
44669. DAVINCI_AINTC_FIQ_REG0
44670. DAVINCI_AINTC_FIQ_REG1
44671. DAVINCI_AINTC_IRQ_EABASE_REG
44672. DAVINCI_AINTC_IRQ_ENT_REG0
44673. DAVINCI_AINTC_IRQ_ENT_REG1
44674. DAVINCI_AINTC_IRQ_INCTL_REG
44675. DAVINCI_AINTC_IRQ_INTPRI0_REG
44676. DAVINCI_AINTC_IRQ_INTPRI7_REG
44677. DAVINCI_AINTC_IRQ_IRQENTRY
44678. DAVINCI_AINTC_IRQ_REG0
44679. DAVINCI_AINTC_IRQ_REG1
44680. DAVINCI_ARM_INTC_BASE
44681. DAVINCI_ASP0_BASE
44682. DAVINCI_ASP0_RX_INT
44683. DAVINCI_ASP0_TX_INT
44684. DAVINCI_ASP1_BASE
44685. DAVINCI_ASP1_RX_INT
44686. DAVINCI_ASP1_TX_INT
44687. DAVINCI_ATA_BASE
44688. DAVINCI_AUTOREQ_REG
44689. DAVINCI_BASE_OFFSET
44690. DAVINCI_CPPI_EOI_REG
44691. DAVINCI_CPPI_INTVEC_REG
44692. DAVINCI_CPPI_STATERAM_BASE_OFFSET
44693. DAVINCI_CPUIDLE_MAX_STATES
44694. DAVINCI_CPU_ID_DA830
44695. DAVINCI_CPU_ID_DA850
44696. DAVINCI_CPU_ID_DM355
44697. DAVINCI_CPU_ID_DM365
44698. DAVINCI_CPU_ID_DM6446
44699. DAVINCI_CPU_ID_DM6467
44700. DAVINCI_CP_INTC_CHAN_MAP
44701. DAVINCI_CP_INTC_CTRL
44702. DAVINCI_CP_INTC_GLOBAL_ENABLE
44703. DAVINCI_CP_INTC_GPIR_NONE
44704. DAVINCI_CP_INTC_HOST_CTRL
44705. DAVINCI_CP_INTC_HOST_ENABLE
44706. DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR
44707. DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET
44708. DAVINCI_CP_INTC_PRIO_IDX
44709. DAVINCI_CP_INTC_PRI_INDX_MASK
44710. DAVINCI_CP_INTC_SYS_ENABLE_CLR
44711. DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR
44712. DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET
44713. DAVINCI_CP_INTC_SYS_POLARITY
44714. DAVINCI_CP_INTC_SYS_STAT_CLR
44715. DAVINCI_CP_INTC_SYS_STAT_IDX_CLR
44716. DAVINCI_CP_INTC_SYS_TYPE
44717. DAVINCI_DA830_DMA_MCASP1_AREVT
44718. DAVINCI_DA830_DMA_MCASP1_AXEVT
44719. DAVINCI_DA830_DMA_MCASP2_AREVT
44720. DAVINCI_DA830_DMA_MCASP2_AXEVT
44721. DAVINCI_DA830_MCASP1_REG_BASE
44722. DAVINCI_DA830_MCASP2_REG_BASE
44723. DAVINCI_DA8XX_DMA_MCASP0_AREVT
44724. DAVINCI_DA8XX_DMA_MCASP0_AXEVT
44725. DAVINCI_DA8XX_MCASP0_REG_BASE
44726. DAVINCI_DM365_ASP0_BASE
44727. DAVINCI_DM365_VC_BASE
44728. DAVINCI_DM646X_DMA_MCASP0_AREVT0
44729. DAVINCI_DM646X_DMA_MCASP0_AXEVT0
44730. DAVINCI_DM646X_DMA_MCASP1_AXEVT1
44731. DAVINCI_DM646X_MCASP0_REG_BASE
44732. DAVINCI_DM646X_MCASP1_REG_BASE
44733. DAVINCI_DMA_ALL_CHANNELS_DISABLE
44734. DAVINCI_DMA_ALL_CHANNELS_ENABLE
44735. DAVINCI_DMA_ASP0_RX
44736. DAVINCI_DMA_ASP0_TX
44737. DAVINCI_DMA_ASP1_RX
44738. DAVINCI_DMA_ASP1_TX
44739. DAVINCI_DMA_CTRL_DISABLE
44740. DAVINCI_DMA_CTRL_ENABLE
44741. DAVINCI_DMA_VC_RX
44742. DAVINCI_DMA_VC_TX
44743. DAVINCI_EMAC_DEBUG
44744. DAVINCI_GPIO_BASE
44745. DAVINCI_GPSC_ARMDOMAIN
44746. DAVINCI_GPSC_DSPDOMAIN
44747. DAVINCI_I2C_BASE
44748. DAVINCI_I2C_CLKH_REG
44749. DAVINCI_I2C_CLKL_REG
44750. DAVINCI_I2C_CNT_REG
44751. DAVINCI_I2C_DCLR_PDCLR0
44752. DAVINCI_I2C_DCLR_PDCLR1
44753. DAVINCI_I2C_DCLR_REG
44754. DAVINCI_I2C_DIN_PDIN0
44755. DAVINCI_I2C_DIN_PDIN1
44756. DAVINCI_I2C_DIN_REG
44757. DAVINCI_I2C_DIR_PDIR0
44758. DAVINCI_I2C_DIR_PDIR1
44759. DAVINCI_I2C_DIR_REG
44760. DAVINCI_I2C_DOUT_REG
44761. DAVINCI_I2C_DRR_REG
44762. DAVINCI_I2C_DSET_PDSET0
44763. DAVINCI_I2C_DSET_PDSET1
44764. DAVINCI_I2C_DSET_REG
44765. DAVINCI_I2C_DXR_REG
44766. DAVINCI_I2C_EMDR_REG
44767. DAVINCI_I2C_FUNC_PFUNC0
44768. DAVINCI_I2C_FUNC_REG
44769. DAVINCI_I2C_IMR_AAS
44770. DAVINCI_I2C_IMR_AL
44771. DAVINCI_I2C_IMR_ARDY
44772. DAVINCI_I2C_IMR_NACK
44773. DAVINCI_I2C_IMR_REG
44774. DAVINCI_I2C_IMR_RRDY
44775. DAVINCI_I2C_IMR_SCD
44776. DAVINCI_I2C_IMR_XRDY
44777. DAVINCI_I2C_IVR_AAS
44778. DAVINCI_I2C_IVR_AL
44779. DAVINCI_I2C_IVR_ARDY
44780. DAVINCI_I2C_IVR_NACK
44781. DAVINCI_I2C_IVR_RDR
44782. DAVINCI_I2C_IVR_REG
44783. DAVINCI_I2C_IVR_SCD
44784. DAVINCI_I2C_IVR_XRDY
44785. DAVINCI_I2C_MAX_TRIES
44786. DAVINCI_I2C_MDR_IRS
44787. DAVINCI_I2C_MDR_MST
44788. DAVINCI_I2C_MDR_NACK
44789. DAVINCI_I2C_MDR_REG
44790. DAVINCI_I2C_MDR_RM
44791. DAVINCI_I2C_MDR_STP
44792. DAVINCI_I2C_MDR_STT
44793. DAVINCI_I2C_MDR_TRX
44794. DAVINCI_I2C_MDR_XA
44795. DAVINCI_I2C_OAR_REG
44796. DAVINCI_I2C_OWN_ADDRESS
44797. DAVINCI_I2C_PM_TIMEOUT
44798. DAVINCI_I2C_PSC_REG
44799. DAVINCI_I2C_SAR_REG
44800. DAVINCI_I2C_STR_AL
44801. DAVINCI_I2C_STR_ARDY
44802. DAVINCI_I2C_STR_BB
44803. DAVINCI_I2C_STR_NACK
44804. DAVINCI_I2C_STR_REG
44805. DAVINCI_I2C_STR_RSFULL
44806. DAVINCI_I2C_STR_SCD
44807. DAVINCI_I2C_TIMEOUT
44808. DAVINCI_I2S_FORMATS
44809. DAVINCI_I2S_RATES
44810. DAVINCI_INTC_IRQ
44811. DAVINCI_INTC_START
44812. DAVINCI_INTR_DRVVBUS
44813. DAVINCI_KEYSCAN_AUTODET
44814. DAVINCI_KEYSCAN_CHATOFF
44815. DAVINCI_KEYSCAN_CONTTIME
44816. DAVINCI_KEYSCAN_CURRENTST
44817. DAVINCI_KEYSCAN_EMUCTRL
44818. DAVINCI_KEYSCAN_H
44819. DAVINCI_KEYSCAN_INTCLR
44820. DAVINCI_KEYSCAN_INTENA
44821. DAVINCI_KEYSCAN_INTERVAL
44822. DAVINCI_KEYSCAN_INTFLAG
44823. DAVINCI_KEYSCAN_INT_ALL
44824. DAVINCI_KEYSCAN_INT_CHANGE
44825. DAVINCI_KEYSCAN_INT_CONT
44826. DAVINCI_KEYSCAN_INT_OFF
44827. DAVINCI_KEYSCAN_INT_ON
44828. DAVINCI_KEYSCAN_IODFTCTRL
44829. DAVINCI_KEYSCAN_KEYCTRL
44830. DAVINCI_KEYSCAN_KEYEN
44831. DAVINCI_KEYSCAN_MATRIX_4X4
44832. DAVINCI_KEYSCAN_MATRIX_5X3
44833. DAVINCI_KEYSCAN_OUTTYPE
44834. DAVINCI_KEYSCAN_PREVMODE
44835. DAVINCI_KEYSCAN_PREVSTATE
44836. DAVINCI_KEYSCAN_SCANMODE
44837. DAVINCI_KEYSCAN_STRBWIDTH
44838. DAVINCI_LPSC_AEMIF
44839. DAVINCI_LPSC_ARM
44840. DAVINCI_LPSC_ATA
44841. DAVINCI_LPSC_CFG27
44842. DAVINCI_LPSC_CFG3
44843. DAVINCI_LPSC_CFG5
44844. DAVINCI_LPSC_CROSSBAR
44845. DAVINCI_LPSC_DDR_EMIF
44846. DAVINCI_LPSC_EMAC
44847. DAVINCI_LPSC_EMAC_WRAPPER
44848. DAVINCI_LPSC_GEM
44849. DAVINCI_LPSC_GPIO
44850. DAVINCI_LPSC_I2C
44851. DAVINCI_LPSC_IMCOP
44852. DAVINCI_LPSC_MMC_SD
44853. DAVINCI_LPSC_McBSP
44854. DAVINCI_LPSC_PWM0
44855. DAVINCI_LPSC_PWM1
44856. DAVINCI_LPSC_PWM2
44857. DAVINCI_LPSC_SCR2
44858. DAVINCI_LPSC_SCR3
44859. DAVINCI_LPSC_SCR4
44860. DAVINCI_LPSC_SPI
44861. DAVINCI_LPSC_SYSTEM_SUBSYS
44862. DAVINCI_LPSC_TIMER0
44863. DAVINCI_LPSC_TIMER1
44864. DAVINCI_LPSC_TIMER2
44865. DAVINCI_LPSC_TPCC
44866. DAVINCI_LPSC_TPTC0
44867. DAVINCI_LPSC_TPTC1
44868. DAVINCI_LPSC_UART0
44869. DAVINCI_LPSC_UART1
44870. DAVINCI_LPSC_UART2
44871. DAVINCI_LPSC_UHPI
44872. DAVINCI_LPSC_USB
44873. DAVINCI_LPSC_VLYNQ
44874. DAVINCI_LPSC_VPSSMSTR
44875. DAVINCI_LPSC_VPSSSLV
44876. DAVINCI_MAX_RATE_ERROR_PPM
44877. DAVINCI_MCASP_ACLKRCTL_REG
44878. DAVINCI_MCASP_ACLKXCTL_REG
44879. DAVINCI_MCASP_AHCLKRCTL_REG
44880. DAVINCI_MCASP_AHCLKXCTL_REG
44881. DAVINCI_MCASP_AMUTE_REG
44882. DAVINCI_MCASP_DITCSRA_REG
44883. DAVINCI_MCASP_DITCSRB_REG
44884. DAVINCI_MCASP_DITUDRA_REG
44885. DAVINCI_MCASP_DITUDRB_REG
44886. DAVINCI_MCASP_DIT_MODE
44887. DAVINCI_MCASP_EVTCTLR_REG
44888. DAVINCI_MCASP_EVTCTLX_REG
44889. DAVINCI_MCASP_GBLCTLR_REG
44890. DAVINCI_MCASP_GBLCTLX_REG
44891. DAVINCI_MCASP_GBLCTL_REG
44892. DAVINCI_MCASP_H
44893. DAVINCI_MCASP_IIS_MODE
44894. DAVINCI_MCASP_LBCTL_REG
44895. DAVINCI_MCASP_PCM_FMTS
44896. DAVINCI_MCASP_PDCLR_REG
44897. DAVINCI_MCASP_PDIR_REG
44898. DAVINCI_MCASP_PDOUT_REG
44899. DAVINCI_MCASP_PDSET_REG
44900. DAVINCI_MCASP_PFUNC_REG
44901. DAVINCI_MCASP_PID_REG
44902. DAVINCI_MCASP_PWREMUMGT_REG
44903. DAVINCI_MCASP_RATES
44904. DAVINCI_MCASP_REVTCTL_REG
44905. DAVINCI_MCASP_RXBUF_REG
44906. DAVINCI_MCASP_RXCLKCHK_REG
44907. DAVINCI_MCASP_RXFMCTL_REG
44908. DAVINCI_MCASP_RXFMT_REG
44909. DAVINCI_MCASP_RXMASK_REG
44910. DAVINCI_MCASP_RXSTAT_REG
44911. DAVINCI_MCASP_RXTDMSLOT_REG
44912. DAVINCI_MCASP_RXTDM_REG
44913. DAVINCI_MCASP_TLGC_REG
44914. DAVINCI_MCASP_TLMR_REG
44915. DAVINCI_MCASP_TXBUF_REG
44916. DAVINCI_MCASP_TXCLKCHK_REG
44917. DAVINCI_MCASP_TXDITCTL_REG
44918. DAVINCI_MCASP_TXFMCTL_REG
44919. DAVINCI_MCASP_TXFMT_REG
44920. DAVINCI_MCASP_TXMASK_REG
44921. DAVINCI_MCASP_TXSTAT_REG
44922. DAVINCI_MCASP_TXTDMSLOT_REG
44923. DAVINCI_MCASP_TXTDM_REG
44924. DAVINCI_MCASP_V2_AFIFO_BASE
44925. DAVINCI_MCASP_V3_AFIFO_BASE
44926. DAVINCI_MCASP_XEVTCTL_REG
44927. DAVINCI_MCASP_XRSRCTL_BASE_REG
44928. DAVINCI_MCASP_XRSRCTL_REG
44929. DAVINCI_MCBSP_CLKGDV
44930. DAVINCI_MCBSP_DRR_REG
44931. DAVINCI_MCBSP_DXR_REG
44932. DAVINCI_MCBSP_PCR_CLKRM
44933. DAVINCI_MCBSP_PCR_CLKRP
44934. DAVINCI_MCBSP_PCR_CLKXM
44935. DAVINCI_MCBSP_PCR_CLKXP
44936. DAVINCI_MCBSP_PCR_FSRM
44937. DAVINCI_MCBSP_PCR_FSRP
44938. DAVINCI_MCBSP_PCR_FSXM
44939. DAVINCI_MCBSP_PCR_FSXP
44940. DAVINCI_MCBSP_PCR_REG
44941. DAVINCI_MCBSP_PCR_SCLKME
44942. DAVINCI_MCBSP_RCR_RDATDLY
44943. DAVINCI_MCBSP_RCR_REG
44944. DAVINCI_MCBSP_RCR_RFIG
44945. DAVINCI_MCBSP_RCR_RFRLEN1
44946. DAVINCI_MCBSP_RCR_RFRLEN2
44947. DAVINCI_MCBSP_RCR_RPHASE
44948. DAVINCI_MCBSP_RCR_RWDLEN1
44949. DAVINCI_MCBSP_RCR_RWDLEN2
44950. DAVINCI_MCBSP_SPCR_FREE
44951. DAVINCI_MCBSP_SPCR_FRST
44952. DAVINCI_MCBSP_SPCR_GRST
44953. DAVINCI_MCBSP_SPCR_REG
44954. DAVINCI_MCBSP_SPCR_RINTM
44955. DAVINCI_MCBSP_SPCR_RRST
44956. DAVINCI_MCBSP_SPCR_XINTM
44957. DAVINCI_MCBSP_SPCR_XRST
44958. DAVINCI_MCBSP_SRGR_CLKSM
44959. DAVINCI_MCBSP_SRGR_FPER
44960. DAVINCI_MCBSP_SRGR_FSGM
44961. DAVINCI_MCBSP_SRGR_FWID
44962. DAVINCI_MCBSP_SRGR_REG
44963. DAVINCI_MCBSP_WORD_12
44964. DAVINCI_MCBSP_WORD_16
44965. DAVINCI_MCBSP_WORD_20
44966. DAVINCI_MCBSP_WORD_24
44967. DAVINCI_MCBSP_WORD_32
44968. DAVINCI_MCBSP_WORD_8
44969. DAVINCI_MCBSP_XCR_REG
44970. DAVINCI_MCBSP_XCR_XDATDLY
44971. DAVINCI_MCBSP_XCR_XFIG
44972. DAVINCI_MCBSP_XCR_XFRLEN1
44973. DAVINCI_MCBSP_XCR_XFRLEN2
44974. DAVINCI_MCBSP_XCR_XPHASE
44975. DAVINCI_MCBSP_XCR_XWDLEN1
44976. DAVINCI_MCBSP_XCR_XWDLEN2
44977. DAVINCI_MMCARGHL
44978. DAVINCI_MMCBLEN
44979. DAVINCI_MMCBLNC
44980. DAVINCI_MMCCIDX
44981. DAVINCI_MMCCKC
44982. DAVINCI_MMCCLK
44983. DAVINCI_MMCCMD
44984. DAVINCI_MMCCTL
44985. DAVINCI_MMCDRR
44986. DAVINCI_MMCDRSP
44987. DAVINCI_MMCDXR
44988. DAVINCI_MMCETOK
44989. DAVINCI_MMCFIFOCTL
44990. DAVINCI_MMCIM
44991. DAVINCI_MMCNBLC
44992. DAVINCI_MMCNBLK
44993. DAVINCI_MMCRSP01
44994. DAVINCI_MMCRSP23
44995. DAVINCI_MMCRSP45
44996. DAVINCI_MMCRSP67
44997. DAVINCI_MMCSD0_BASE
44998. DAVINCI_MMCST0
44999. DAVINCI_MMCST1
45000. DAVINCI_MMCTOD
45001. DAVINCI_MMCTODC
45002. DAVINCI_MMCTOR
45003. DAVINCI_MMCTORC
45004. DAVINCI_MMC_DATADIR_NONE
45005. DAVINCI_MMC_DATADIR_READ
45006. DAVINCI_MMC_DATADIR_WRITE
45007. DAVINCI_N_AINTC_IRQ
45008. DAVINCI_N_GPIO
45009. DAVINCI_PLL1_BASE
45010. DAVINCI_PLL2_BASE
45011. DAVINCI_PRTCIF_PID
45012. DAVINCI_PWR_SLEEP_CNTRL_BASE
45013. DAVINCI_RNDIS_REG
45014. DAVINCI_RXCPPI_BUFCNT0_REG
45015. DAVINCI_RXCPPI_BUFCNT1_REG
45016. DAVINCI_RXCPPI_BUFCNT2_REG
45017. DAVINCI_RXCPPI_BUFCNT3_REG
45018. DAVINCI_RXCPPI_CTRL_REG
45019. DAVINCI_RXCPPI_INTCLR_REG
45020. DAVINCI_RXCPPI_INTENAB_REG
45021. DAVINCI_RXCPPI_MASKED_REG
45022. DAVINCI_RXCPPI_RAW_REG
45023. DAVINCI_RXCPPI_STATERAM_OFFSET
45024. DAVINCI_SDIOCTL
45025. DAVINCI_SDIOIEN
45026. DAVINCI_SDIOIST
45027. DAVINCI_SDIOST0
45028. DAVINCI_SYSMOD_VIRT
45029. DAVINCI_SYSTEM_MODULE_BASE
45030. DAVINCI_TIMER0_BASE
45031. DAVINCI_TIMER1_BASE
45032. DAVINCI_TIMER_CLKSRC_BITS
45033. DAVINCI_TIMER_CLOCKEVENT_IRQ
45034. DAVINCI_TIMER_CLOCKSOURCE_IRQ
45035. DAVINCI_TIMER_ENAMODE_DISABLED
45036. DAVINCI_TIMER_ENAMODE_MASK
45037. DAVINCI_TIMER_ENAMODE_ONESHOT
45038. DAVINCI_TIMER_ENAMODE_PERIODIC
45039. DAVINCI_TIMER_ENAMODE_SHIFT_TIM12
45040. DAVINCI_TIMER_ENAMODE_SHIFT_TIM34
45041. DAVINCI_TIMER_MAX_DELTA
45042. DAVINCI_TIMER_MIN_DELTA
45043. DAVINCI_TIMER_NUM_IRQS
45044. DAVINCI_TIMER_REG_PRD12
45045. DAVINCI_TIMER_REG_PRD34
45046. DAVINCI_TIMER_REG_TCR
45047. DAVINCI_TIMER_REG_TGCR
45048. DAVINCI_TIMER_REG_TIM12
45049. DAVINCI_TIMER_REG_TIM34
45050. DAVINCI_TIMER_RESET_MASK
45051. DAVINCI_TIMER_TGCR_DEFAULT
45052. DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED
45053. DAVINCI_TIMER_TIMMODE_MASK
45054. DAVINCI_TIMER_UNRESET
45055. DAVINCI_TXCPPI_CTRL_REG
45056. DAVINCI_TXCPPI_INTCLR_REG
45057. DAVINCI_TXCPPI_INTENAB_REG
45058. DAVINCI_TXCPPI_MASKED_REG
45059. DAVINCI_TXCPPI_RAW_REG
45060. DAVINCI_TXCPPI_STATERAM_OFFSET
45061. DAVINCI_TXCPPI_TEAR_REG
45062. DAVINCI_UART0_BASE
45063. DAVINCI_UART1_BASE
45064. DAVINCI_UART2_BASE
45065. DAVINCI_USB_CTRL_REG
45066. DAVINCI_USB_EOI_INTVEC
45067. DAVINCI_USB_EOI_REG
45068. DAVINCI_USB_INT_MASK_CLR_REG
45069. DAVINCI_USB_INT_MASK_REG
45070. DAVINCI_USB_INT_MASK_SET_REG
45071. DAVINCI_USB_INT_SET_REG
45072. DAVINCI_USB_INT_SOURCE_REG
45073. DAVINCI_USB_INT_SRC_CLR_REG
45074. DAVINCI_USB_INT_SRC_MASKED_REG
45075. DAVINCI_USB_OTG_BASE
45076. DAVINCI_USB_RXINT_MASK
45077. DAVINCI_USB_RXINT_SHIFT
45078. DAVINCI_USB_RX_ENDPTS_MASK
45079. DAVINCI_USB_STAT_REG
45080. DAVINCI_USB_TXINT_MASK
45081. DAVINCI_USB_TXINT_SHIFT
45082. DAVINCI_USB_TX_ENDPTS_MASK
45083. DAVINCI_USB_USBINT_MASK
45084. DAVINCI_USB_USBINT_SHIFT
45085. DAVINCI_USB_VERSION_REG
45086. DAVINCI_VCIF_RATES
45087. DAVINCI_VC_CELLS
45088. DAVINCI_VC_CQ93VC_CELL
45089. DAVINCI_VC_CTRL
45090. DAVINCI_VC_CTRL_MASK
45091. DAVINCI_VC_CTRL_RD_BITS_8
45092. DAVINCI_VC_CTRL_RD_UNSIGNED
45093. DAVINCI_VC_CTRL_RFIFOCL
45094. DAVINCI_VC_CTRL_RFIFOEN
45095. DAVINCI_VC_CTRL_RFIFOMD_WORD_1
45096. DAVINCI_VC_CTRL_RSTADC
45097. DAVINCI_VC_CTRL_RSTDAC
45098. DAVINCI_VC_CTRL_WD_BITS_8
45099. DAVINCI_VC_CTRL_WD_UNSIGNED
45100. DAVINCI_VC_CTRL_WFIFOCL
45101. DAVINCI_VC_CTRL_WFIFOEN
45102. DAVINCI_VC_CTRL_WFIFOMD_WORD_1
45103. DAVINCI_VC_EMUL_CTRL
45104. DAVINCI_VC_FIFOSTAT
45105. DAVINCI_VC_INTCLR
45106. DAVINCI_VC_INTEN
45107. DAVINCI_VC_INTSTATUS
45108. DAVINCI_VC_INT_MASK
45109. DAVINCI_VC_INT_RDRDY_MASK
45110. DAVINCI_VC_INT_RERROVF_MASK
45111. DAVINCI_VC_INT_RERRUDR_MASK
45112. DAVINCI_VC_INT_WDREQ_MASK
45113. DAVINCI_VC_INT_WERROVF_MASKBIT
45114. DAVINCI_VC_INT_WERRUDR_MASK
45115. DAVINCI_VC_PID
45116. DAVINCI_VC_REG05
45117. DAVINCI_VC_REG05_PGA_GAIN
45118. DAVINCI_VC_REG09
45119. DAVINCI_VC_REG09_DIG_ATTEN
45120. DAVINCI_VC_REG09_MUTE
45121. DAVINCI_VC_REG12
45122. DAVINCI_VC_REG12_POWER_ALL_OFF
45123. DAVINCI_VC_REG12_POWER_ALL_ON
45124. DAVINCI_VC_RFIFO
45125. DAVINCI_VC_TST_CTRL
45126. DAVINCI_VC_VCIF_CELL
45127. DAVINCI_VC_WFIFO
45128. DAVINCI_VPIF_BASE
45129. DAVINCI_WDOG_BASE
45130. DAWRX_DR
45131. DAWRX_DW
45132. DAWRX_HYP
45133. DAWRX_KERNEL
45134. DAWRX_USER
45135. DAWRX_WT
45136. DAWRX_WTI
45137. DAWR_A2091
45138. DAWR_A3000
45139. DAWR_LENGTH_MAX
45140. DAX1_MAJOR
45141. DAX1_MINOR
45142. DAX1_STR
45143. DAX2_MAJOR
45144. DAX2_MINOR
45145. DAX2_STR
45146. DAXDEV_ALIVE
45147. DAXDEV_F_SYNC
45148. DAXDEV_SYNC
45149. DAXDEV_WRITE_CACHE
45150. DAXFS_MAGIC
45151. DAX_ADDR_TYPE_NONE
45152. DAX_ADDR_TYPE_RA
45153. DAX_ADDR_TYPE_VA
45154. DAX_ADDR_TYPE_VA_ALT
45155. DAX_CA_ELEMS
45156. DAX_CCB_BUF_MAXLEN
45157. DAX_CCB_COMPLETED
45158. DAX_CCB_ENQUEUED
45159. DAX_CCB_INPROGRESS
45160. DAX_CCB_NOTFOUND
45161. DAX_CCB_RETRIES
45162. DAX_CCB_USEC
45163. DAX_DBG_FLG_ALL
45164. DAX_DBG_FLG_BASIC
45165. DAX_DBG_FLG_INFO
45166. DAX_DBG_FLG_STAT
45167. DAX_DEVICE_MODALIAS_FMT
45168. DAX_EMPTY
45169. DAX_HASH_SIZE
45170. DAX_KILL_COMPLETED
45171. DAX_KILL_DEQUEUED
45172. DAX_KILL_KILLED
45173. DAX_KILL_NOTFOUND
45174. DAX_LOCKED
45175. DAX_MAX_CCBS
45176. DAX_MMAP_LEN
45177. DAX_NAME
45178. DAX_NAME_LEN
45179. DAX_OP_EXTRACT
45180. DAX_OP_INVERT
45181. DAX_OP_SCAN_RANGE
45182. DAX_OP_SCAN_VALUE
45183. DAX_OP_SELECT
45184. DAX_OP_SYNC_NOP
45185. DAX_OP_TRANSLATE
45186. DAX_PMD
45187. DAX_SHIFT
45188. DAX_SIG
45189. DAX_SUBMIT_ERR_ARG_INVAL
45190. DAX_SUBMIT_ERR_BUSY
45191. DAX_SUBMIT_ERR_CCB_ARR_MMU_MISS
45192. DAX_SUBMIT_ERR_CCB_INVAL
45193. DAX_SUBMIT_ERR_INTERNAL
45194. DAX_SUBMIT_ERR_NOACCESS
45195. DAX_SUBMIT_ERR_NOMAP
45196. DAX_SUBMIT_ERR_NO_CA_AVAIL
45197. DAX_SUBMIT_ERR_RETRY
45198. DAX_SUBMIT_ERR_THR_INIT
45199. DAX_SUBMIT_ERR_TOOMANY
45200. DAX_SUBMIT_ERR_UNAVAIL
45201. DAX_SUBMIT_ERR_WOULDBLOCK
45202. DAX_SUBMIT_OK
45203. DAX_WAIT_TABLE_BITS
45204. DAX_WAIT_TABLE_ENTRIES
45205. DAX_ZERO_PAGE
45206. DAY
45207. DAYALARM
45208. DAYALARM_ADDR
45209. DAYALARM_DAYSAL_MASK
45210. DAYALARM_DAYSAL_SHIFT
45211. DAYNA
45212. DAYNALINK_PROM_BASE
45213. DAYNA_8390_BASE
45214. DAYNA_8390_MEM
45215. DAYNA_CARD_STATUS
45216. DAYNA_CLEAR_INT
45217. DAYNA_CMD_DATA
45218. DAYNA_INT_CARD
45219. DAYNA_RESET
45220. DAYNA_RX_READY
45221. DAYNA_RX_REQUEST
45222. DAYNA_SONIC_MAC_ADDR
45223. DAYNA_SONIC_REGISTERS
45224. DAYNA_TX_READY
45225. DAYR
45226. DAYR_ADDR
45227. DAYR_DAYS_MASK
45228. DAYR_DAYS_SHIFT
45229. DAYS
45230. DAYS_DELTA
45231. DAYS_REG_MSK
45232. DAYS_TENS
45233. DAYS_UNITS
45234. DAY_AS_SECONDS
45235. DAY_MASK
45236. DAZZLE_DVC_50_REV_1_NTSC
45237. DAZZLE_DVC_80_REV_1_PAL
45238. DAZZLE_DVC_90_REV_1_SECAM
45239. DAZ_HWID
45240. DA_EMULATE_3PC
45241. DA_EMULATE_ALUA
45242. DA_EMULATE_CAW
45243. DA_EMULATE_MODEL_ALIAS
45244. DA_EMULATE_PR
45245. DA_EMULATE_REST_REORD
45246. DA_EMULATE_TAS
45247. DA_EMULATE_TPU
45248. DA_EMULATE_TPWS
45249. DA_EMULATE_UA_INTLLCK_CTRL
45250. DA_EMULATE_WRITE_CACHE
45251. DA_ENFORCE_PR_ISIDS
45252. DA_FAILED
45253. DA_FORCE_PR_APTPL
45254. DA_HS_EXIT
45255. DA_ID_REQUEST_SZ
45256. DA_IS_NONROT
45257. DA_MASK
45258. DA_MAX_UNMAP_BLOCK_DESC_COUNT
45259. DA_MAX_UNMAP_LBA_COUNT
45260. DA_MAX_WRITE_SAME_LEN
45261. DA_NONE
45262. DA_PASSED
45263. DA_SHIFT
45264. DA_STATUS_MAX_SECTORS_MAX
45265. DA_STATUS_MAX_SECTORS_MIN
45266. DA_UNMAP_GRANULARITY_ALIGNMENT_DEFAULT
45267. DA_UNMAP_GRANULARITY_DEFAULT
45268. DA_UNMAP_ZEROES_DATA_DEFAULT
45269. DB
45270. DB0_GPIO_PIN
45271. DB0_MARK
45272. DB1000_BCSR_HEXLED_OFS
45273. DB1000_BCSR_PHYS_ADDR
45274. DB1200_BCSR_HEXLED_OFS
45275. DB1200_BCSR_PHYS_ADDR
45276. DB1200_DC_INT
45277. DB1200_ETH_INT
45278. DB1200_ETH_PHYS_ADDR
45279. DB1200_FLASHBUSY_INT
45280. DB1200_IDE_INT
45281. DB1200_IDE_PHYS_ADDR
45282. DB1200_IDE_PHYS_LEN
45283. DB1200_IDE_REG_SHIFT
45284. DB1200_INT_BEGIN
45285. DB1200_INT_END
45286. DB1200_NAND_PHYS_ADDR
45287. DB1200_PC0_EJECT_INT
45288. DB1200_PC0_INSERT_INT
45289. DB1200_PC0_INT
45290. DB1200_PC0_STSCHG_INT
45291. DB1200_PC1_EJECT_INT
45292. DB1200_PC1_INSERT_INT
45293. DB1200_PC1_INT
45294. DB1200_PC1_STSCHG_INT
45295. DB1200_SD0_EJECT_INT
45296. DB1200_SD0_INSERT_INT
45297. DB1300_AC97_INT
45298. DB1300_AC97_PEN_INT
45299. DB1300_BCSR_HEXLED_OFS
45300. DB1300_BCSR_PHYS_ADDR
45301. DB1300_CF_EJECT_INT
45302. DB1300_CF_INSERT_INT
45303. DB1300_CF_INT
45304. DB1300_DC_INT
45305. DB1300_ETH_INT
45306. DB1300_ETH_PHYS_ADDR
45307. DB1300_ETH_PHYS_END
45308. DB1300_FIRST_INT
45309. DB1300_FLASH_INT
45310. DB1300_HDMI_INT
45311. DB1300_HOST_VBUS_OC_INT
45312. DB1300_IDE_INT
45313. DB1300_IDE_PHYS_ADDR
45314. DB1300_IDE_PHYS_LEN
45315. DB1300_IDE_REG_SHIFT
45316. DB1300_LAST_INT
45317. DB1300_NAND_PHYS_ADDR
45318. DB1300_NAND_PHYS_END
45319. DB1300_OTG_VBUS_OC_INT
45320. DB1300_SD1_EJECT_INT
45321. DB1300_SD1_INSERT_INT
45322. DB1300_VIDEO_INT
45323. DB1550_BCSR_HEXLED_OFS
45324. DB1550_BCSR_PHYS_ADDR
45325. DB15_GPIO_PIN
45326. DB1_MARK
45327. DB2K_ACQ_CONTROL_ADC_PACER_COMPATIBILITY_MODE
45328. DB2K_ACQ_CONTROL_ADC_PACER_DISABLE
45329. DB2K_ACQ_CONTROL_ADC_PACER_ENABLE
45330. DB2K_ACQ_CONTROL_ADC_PACER_ENABLE_DAC_PACER
45331. DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL
45332. DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL_RISING
45333. DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL
45334. DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL_OUT_ENABLE
45335. DB2K_ACQ_CONTROL_ADC_PACER_NORMAL_MODE
45336. DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE
45337. DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO
45338. DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO
45339. DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST
45340. DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST
45341. DB2K_ACQ_STATUS_ADC_NOT_READY
45342. DB2K_ACQ_STATUS_ADC_PACER_OVERRUN
45343. DB2K_ACQ_STATUS_ARBITRATION_FAILURE
45344. DB2K_ACQ_STATUS_CONFIG_PIPE_FULL
45345. DB2K_ACQ_STATUS_DAC_PACER_OVERRUN
45346. DB2K_ACQ_STATUS_LOGIC_SCANNING
45347. DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA
45348. DB2K_ACQ_STATUS_RESULTS_FIFO_MORE_1_SAMPLE
45349. DB2K_ACQ_STATUS_RESULTS_FIFO_OVERRUN
45350. DB2K_ACQ_STATUS_SCAN_LIST_FIFO_EMPTY
45351. DB2K_CPLD_STATUS_INIT
45352. DB2K_CPLD_STATUS_TXREADY
45353. DB2K_CPLD_VERSION_MASK
45354. DB2K_CPLD_VERSION_NEW
45355. DB2K_DAC_CONTROL_DAC_DISABLE
45356. DB2K_DAC_CONTROL_DAC_ENABLE
45357. DB2K_DAC_CONTROL_DATA_IS_SIGNED
45358. DB2K_DAC_CONTROL_ENABLE_BIT
45359. DB2K_DAC_CONTROL_PATTERN_DISABLE
45360. DB2K_DAC_CONTROL_PATTERN_ENABLE
45361. DB2K_DAC_CONTROL_RESET_FIFO
45362. DB2K_DAC_STATUS_CAL_BUSY
45363. DB2K_DAC_STATUS_DAC_BUSY
45364. DB2K_DAC_STATUS_DAC_FULL
45365. DB2K_DAC_STATUS_REF_BUSY
45366. DB2K_DAC_STATUS_TRIG_BUSY
45367. DB2K_FIRMWARE
45368. DB2K_REF_DACS_SELECT_NEG_REF
45369. DB2K_REF_DACS_SELECT_POS_REF
45370. DB2K_REF_DACS_SET
45371. DB2K_REG_ACQ_ADC_RESULT
45372. DB2K_REG_ACQ_CONTROL
45373. DB2K_REG_ACQ_DIGITAL_MARK
45374. DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH
45375. DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW
45376. DB2K_REG_ACQ_RESULTS_FIFO
45377. DB2K_REG_ACQ_RESULTS_SHADOW
45378. DB2K_REG_ACQ_SCAN_COUNTER
45379. DB2K_REG_ACQ_SCAN_LIST_FIFO
45380. DB2K_REG_ACQ_STATUS
45381. DB2K_REG_ACQ_TRIGGER_COUNT
45382. DB2K_REG_CAL_EEPROM
45383. DB2K_REG_CAL_EEPROM_CONTROL
45384. DB2K_REG_COUNTER_INPUT
45385. DB2K_REG_COUNTER_TIMER_CONTROL
45386. DB2K_REG_CPLD_STATUS
45387. DB2K_REG_CPLD_WDATA
45388. DB2K_REG_DAC_CONTROL
45389. DB2K_REG_DAC_FIFO
45390. DB2K_REG_DAC_PACER_CLOCK_DIV
45391. DB2K_REG_DAC_SCAN_COUNTER
45392. DB2K_REG_DAC_SETTING
45393. DB2K_REG_DAC_STATUS
45394. DB2K_REG_DIO_CONTROL
45395. DB2K_REG_DIO_P2_EXP_IO_16_BIT
45396. DB2K_REG_DIO_P2_EXP_IO_8_BIT
45397. DB2K_REG_DMA_CONTROL
45398. DB2K_REG_P3_CONTROL
45399. DB2K_REG_P3_HSIO_DATA
45400. DB2K_REG_REF_DACS
45401. DB2K_REG_TIMER_DIV
45402. DB2K_REG_TRIG_CONTROL
45403. DB2K_REG_TRIG_DACS
45404. DB2K_TRIG_CONTROL_DISABLE
45405. DB2K_TRIG_CONTROL_EDGE_HI_LO
45406. DB2K_TRIG_CONTROL_EDGE_LO_HI
45407. DB2K_TRIG_CONTROL_ENABLE
45408. DB2K_TRIG_CONTROL_LEVEL_ABOVE
45409. DB2K_TRIG_CONTROL_LEVEL_BELOW
45410. DB2K_TRIG_CONTROL_SENSE_EDGE
45411. DB2K_TRIG_CONTROL_SENSE_LEVEL
45412. DB2K_TRIG_CONTROL_TYPE_ANALOG
45413. DB2K_TRIG_CONTROL_TYPE_TTL
45414. DB2_MARK
45415. DB3_MARK
45416. DB4_MARK
45417. DB5_MARK
45418. DB8500_DMA_MEMCPY_EV_0
45419. DB8500_DMA_MEMCPY_EV_1
45420. DB8500_DMA_MEMCPY_EV_2
45421. DB8500_DMA_MEMCPY_EV_3
45422. DB8500_DMA_MEMCPY_EV_4
45423. DB8500_DMA_MEMCPY_EV_5
45424. DB8500_FUNC_GROUPS
45425. DB8500_NUM_REGULATORS
45426. DB8500_PIN_A12
45427. DB8500_PIN_A18
45428. DB8500_PIN_A22
45429. DB8500_PIN_A3
45430. DB8500_PIN_A5
45431. DB8500_PIN_A7
45432. DB8500_PIN_A9
45433. DB8500_PIN_AA1
45434. DB8500_PIN_AA2
45435. DB8500_PIN_AA3
45436. DB8500_PIN_AA4
45437. DB8500_PIN_AB2
45438. DB8500_PIN_AB3
45439. DB8500_PIN_AB4
45440. DB8500_PIN_AC1
45441. DB8500_PIN_AC2
45442. DB8500_PIN_AC27
45443. DB8500_PIN_AC28
45444. DB8500_PIN_AC29
45445. DB8500_PIN_AC3
45446. DB8500_PIN_AC4
45447. DB8500_PIN_AD26
45448. DB8500_PIN_AD27
45449. DB8500_PIN_AD28
45450. DB8500_PIN_AD29
45451. DB8500_PIN_AD3
45452. DB8500_PIN_AD4
45453. DB8500_PIN_AD5
45454. DB8500_PIN_AE1
45455. DB8500_PIN_AE2
45456. DB8500_PIN_AE23
45457. DB8500_PIN_AE26
45458. DB8500_PIN_AE27
45459. DB8500_PIN_AE29
45460. DB8500_PIN_AE3
45461. DB8500_PIN_AE4
45462. DB8500_PIN_AF13
45463. DB8500_PIN_AF2
45464. DB8500_PIN_AF23
45465. DB8500_PIN_AF24
45466. DB8500_PIN_AF25
45467. DB8500_PIN_AF27
45468. DB8500_PIN_AF28
45469. DB8500_PIN_AF3
45470. DB8500_PIN_AF5
45471. DB8500_PIN_AF6
45472. DB8500_PIN_AF7
45473. DB8500_PIN_AF8
45474. DB8500_PIN_AG10
45475. DB8500_PIN_AG12
45476. DB8500_PIN_AG13
45477. DB8500_PIN_AG14
45478. DB8500_PIN_AG15
45479. DB8500_PIN_AG2
45480. DB8500_PIN_AG23
45481. DB8500_PIN_AG24
45482. DB8500_PIN_AG25
45483. DB8500_PIN_AG26
45484. DB8500_PIN_AG28
45485. DB8500_PIN_AG29
45486. DB8500_PIN_AG4
45487. DB8500_PIN_AG5
45488. DB8500_PIN_AG6
45489. DB8500_PIN_AG7
45490. DB8500_PIN_AG8
45491. DB8500_PIN_AG9
45492. DB8500_PIN_AH10
45493. DB8500_PIN_AH11
45494. DB8500_PIN_AH12
45495. DB8500_PIN_AH13
45496. DB8500_PIN_AH15
45497. DB8500_PIN_AH16
45498. DB8500_PIN_AH23
45499. DB8500_PIN_AH24
45500. DB8500_PIN_AH26
45501. DB8500_PIN_AH27
45502. DB8500_PIN_AH3
45503. DB8500_PIN_AH4
45504. DB8500_PIN_AH6
45505. DB8500_PIN_AH7
45506. DB8500_PIN_AH9
45507. DB8500_PIN_AJ11
45508. DB8500_PIN_AJ15
45509. DB8500_PIN_AJ23
45510. DB8500_PIN_AJ27
45511. DB8500_PIN_AJ3
45512. DB8500_PIN_AJ5
45513. DB8500_PIN_AJ6
45514. DB8500_PIN_AJ9
45515. DB8500_PIN_B10
45516. DB8500_PIN_B11
45517. DB8500_PIN_B13
45518. DB8500_PIN_B14
45519. DB8500_PIN_B16
45520. DB8500_PIN_B17
45521. DB8500_PIN_B19
45522. DB8500_PIN_B20
45523. DB8500_PIN_B21
45524. DB8500_PIN_B24
45525. DB8500_PIN_B3
45526. DB8500_PIN_B4
45527. DB8500_PIN_B6
45528. DB8500_PIN_B7
45529. DB8500_PIN_B9
45530. DB8500_PIN_C1
45531. DB8500_PIN_C10
45532. DB8500_PIN_C11
45533. DB8500_PIN_C12
45534. DB8500_PIN_C13
45535. DB8500_PIN_C14
45536. DB8500_PIN_C15
45537. DB8500_PIN_C16
45538. DB8500_PIN_C17
45539. DB8500_PIN_C18
45540. DB8500_PIN_C19
45541. DB8500_PIN_C2
45542. DB8500_PIN_C20
45543. DB8500_PIN_C21
45544. DB8500_PIN_C22
45545. DB8500_PIN_C23
45546. DB8500_PIN_C4
45547. DB8500_PIN_C5
45548. DB8500_PIN_C6
45549. DB8500_PIN_C7
45550. DB8500_PIN_C8
45551. DB8500_PIN_C9
45552. DB8500_PIN_D12
45553. DB8500_PIN_D13
45554. DB8500_PIN_D16
45555. DB8500_PIN_D17
45556. DB8500_PIN_D2
45557. DB8500_PIN_D20
45558. DB8500_PIN_D21
45559. DB8500_PIN_D22
45560. DB8500_PIN_D23
45561. DB8500_PIN_D3
45562. DB8500_PIN_D5
45563. DB8500_PIN_D6
45564. DB8500_PIN_D7
45565. DB8500_PIN_D8
45566. DB8500_PIN_D9
45567. DB8500_PIN_E1
45568. DB8500_PIN_E2
45569. DB8500_PIN_E3
45570. DB8500_PIN_E4
45571. DB8500_PIN_E6
45572. DB8500_PIN_E8
45573. DB8500_PIN_F1
45574. DB8500_PIN_F3
45575. DB8500_PIN_F4
45576. DB8500_PIN_G2
45577. DB8500_PIN_G3
45578. DB8500_PIN_G4
45579. DB8500_PIN_G5
45580. DB8500_PIN_GROUP
45581. DB8500_PIN_H1
45582. DB8500_PIN_H2
45583. DB8500_PIN_H3
45584. DB8500_PIN_H4
45585. DB8500_PIN_J2
45586. DB8500_PIN_J3
45587. DB8500_PIN_V2
45588. DB8500_PIN_V3
45589. DB8500_PIN_W2
45590. DB8500_PIN_W3
45591. DB8500_PIN_Y2
45592. DB8500_PIN_Y4
45593. DB8500_PRCMU_FW_VERSION_OFFSET
45594. DB8500_PRCMU_LEGACY_OFFSET
45595. DB8500_PRCM_DSI_SW_RESET
45596. DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN
45597. DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN
45598. DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN
45599. DB8500_PRCM_LINE_VALUE
45600. DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0
45601. DB8500_REGULATOR_SWITCH_B2R2_MCDE
45602. DB8500_REGULATOR_SWITCH_ESRAM12
45603. DB8500_REGULATOR_SWITCH_ESRAM12RET
45604. DB8500_REGULATOR_SWITCH_ESRAM34
45605. DB8500_REGULATOR_SWITCH_ESRAM34RET
45606. DB8500_REGULATOR_SWITCH_SGA
45607. DB8500_REGULATOR_SWITCH_SIAMMDSP
45608. DB8500_REGULATOR_SWITCH_SIAMMDSPRET
45609. DB8500_REGULATOR_SWITCH_SIAPIPE
45610. DB8500_REGULATOR_SWITCH_SVAMMDSP
45611. DB8500_REGULATOR_SWITCH_SVAMMDSPRET
45612. DB8500_REGULATOR_SWITCH_SVAPIPE
45613. DB8500_REGULATOR_VAPE
45614. DB8500_REGULATOR_VARM
45615. DB8500_REGULATOR_VMODEM
45616. DB8500_REGULATOR_VPLL
45617. DB8500_REGULATOR_VRF1
45618. DB8500_REGULATOR_VSMPS1
45619. DB8500_REGULATOR_VSMPS2
45620. DB8500_REGULATOR_VSMPS3
45621. DB88F5281_7SEG_BASE
45622. DB88F5281_7SEG_SIZE
45623. DB88F5281_NAND_BASE
45624. DB88F5281_NAND_SIZE
45625. DB88F5281_NOR_BASE
45626. DB88F5281_NOR_BOOT_BASE
45627. DB88F5281_NOR_BOOT_SIZE
45628. DB88F5281_NOR_SIZE
45629. DB88F5281_PCI_SLOT0_IRQ_PIN
45630. DB88F5281_PCI_SLOT0_OFFS
45631. DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN
45632. DB9_ARG_MODE
45633. DB9_ARG_PARPORT
45634. DB9_CD32_PAD
45635. DB9_DOWN
45636. DB9_FIRE1
45637. DB9_FIRE2
45638. DB9_FIRE3
45639. DB9_FIRE4
45640. DB9_GENESIS5_PAD
45641. DB9_GENESIS6_DELAY
45642. DB9_GENESIS6_PAD
45643. DB9_GENESIS_PAD
45644. DB9_LEFT
45645. DB9_MAX_DEVICES
45646. DB9_MAX_PAD
45647. DB9_MAX_PORTS
45648. DB9_MULTI2_STICK
45649. DB9_MULTI_0802
45650. DB9_MULTI_0802_2
45651. DB9_MULTI_STICK
45652. DB9_NORMAL
45653. DB9_NOSELECT
45654. DB9_REFRESH_TIME
45655. DB9_RIGHT
45656. DB9_SATURN_DELAY
45657. DB9_SATURN_DPP
45658. DB9_SATURN_DPP_2
45659. DB9_SATURN_PAD
45660. DB9_UP
45661. DBAM0
45662. DBAM1
45663. DBAM_DIMM
45664. DBAM_MAX_VALUE
45665. DBANDCSR0
45666. DBANDCSR1
45667. DBAR1
45668. DBAR2
45669. DBAT
45670. DBAT_ENTRY_NUM
45671. DBCOL
45672. DBCOL_BORDCOL
45673. DBCR0_ACTIVE_EVENTS
45674. DBCR0_BRT
45675. DBCR0_BT
45676. DBCR0_CIRPT
45677. DBCR0_CRET
45678. DBCR0_DAC1R
45679. DBCR0_DAC1W
45680. DBCR0_DAC2R
45681. DBCR0_DAC2W
45682. DBCR0_EDE
45683. DBCR0_EDM
45684. DBCR0_FT
45685. DBCR0_IA1
45686. DBCR0_IA12
45687. DBCR0_IA12T
45688. DBCR0_IA12X
45689. DBCR0_IA2
45690. DBCR0_IA3
45691. DBCR0_IA34
45692. DBCR0_IA34T
45693. DBCR0_IA34X
45694. DBCR0_IA4
45695. DBCR0_IAC1
45696. DBCR0_IAC2
45697. DBCR0_IAC3
45698. DBCR0_IAC4
45699. DBCR0_IC
45700. DBCR0_ICMP
45701. DBCR0_IDM
45702. DBCR0_IRPT
45703. DBCR0_RET
45704. DBCR0_RST
45705. DBCR0_RST_CHIP
45706. DBCR0_RST_CORE
45707. DBCR0_RST_NONE
45708. DBCR0_RST_SYSTEM
45709. DBCR0_TDE
45710. DBCR0_TIE
45711. DBCR1_ACTIVE_EVENTS
45712. DBCR1_DAC1R
45713. DBCR1_DAC1W
45714. DBCR1_DAC2R
45715. DBCR1_DAC2W
45716. DBCR1_IAC12AT
45717. DBCR1_IAC12M
45718. DBCR1_IAC12MX
45719. DBCR1_IAC1ER
45720. DBCR1_IAC1ER_01
45721. DBCR1_IAC1ER_10
45722. DBCR1_IAC1ER_11
45723. DBCR1_IAC1US
45724. DBCR1_IAC2ER
45725. DBCR1_IAC2ER_01
45726. DBCR1_IAC2ER_10
45727. DBCR1_IAC2ER_11
45728. DBCR1_IAC2US
45729. DBCR1_IAC34AT
45730. DBCR1_IAC34M
45731. DBCR1_IAC34MX
45732. DBCR1_IAC3ER
45733. DBCR1_IAC3ER_01
45734. DBCR1_IAC3ER_10
45735. DBCR1_IAC3ER_11
45736. DBCR1_IAC3US
45737. DBCR1_IAC4ER
45738. DBCR1_IAC4ER_01
45739. DBCR1_IAC4ER_10
45740. DBCR1_IAC4ER_11
45741. DBCR1_IAC4US
45742. DBCR2_DAC12A
45743. DBCR2_DAC12M
45744. DBCR2_DAC12MM
45745. DBCR2_DAC12MODE
45746. DBCR2_DAC12MX
45747. DBCR2_DAC1ER
45748. DBCR2_DAC1US
45749. DBCR2_DAC2ER
45750. DBCR2_DAC2US
45751. DBCR2_DVC1BE
45752. DBCR2_DVC1BE_SHIFT
45753. DBCR2_DVC1M
45754. DBCR2_DVC1M_SHIFT
45755. DBCR2_DVC2BE
45756. DBCR2_DVC2BE_SHIFT
45757. DBCR2_DVC2M
45758. DBCR2_DVC2M_SHIFT
45759. DBCR_ACTIVE_EVENTS
45760. DBCR_BT
45761. DBCR_D1R
45762. DBCR_D1S
45763. DBCR_D1W
45764. DBCR_D2R
45765. DBCR_D2S
45766. DBCR_D2W
45767. DBCR_DAC1R
45768. DBCR_DAC1W
45769. DBCR_DAC2R
45770. DBCR_DAC2W
45771. DBCR_EDE
45772. DBCR_EDM
45773. DBCR_FER
45774. DBCR_FT
45775. DBCR_IA1
45776. DBCR_IA2
45777. DBCR_IAC12I
45778. DBCR_IAC12MODE
45779. DBCR_IAC12X
45780. DBCR_IAC34I
45781. DBCR_IAC34MODE
45782. DBCR_IAC34X
45783. DBCR_IC
45784. DBCR_IDM
45785. DBCR_JII
45786. DBCR_JOI
45787. DBCR_RST
45788. DBCR_RST_CHIP
45789. DBCR_RST_CORE
45790. DBCR_RST_NONE
45791. DBCR_RST_SYSTEM
45792. DBCR_SBT
45793. DBCR_SDA
45794. DBCR_SED
45795. DBCR_SIA
45796. DBCR_STD
45797. DBCR_TDE
45798. DBC_CONTEXT_SIZE
45799. DBC_CTRL_DBC_ENABLE
45800. DBC_CTRL_DBC_RUN
45801. DBC_CTRL_DBC_RUN_CHANGE
45802. DBC_CTRL_HALT_IN_TR
45803. DBC_CTRL_HALT_OUT_TR
45804. DBC_CTRL_MAXBURST
45805. DBC_CTRL_PORT_ENABLE
45806. DBC_DBC32_ABS
45807. DBC_DBC32_INCR_MASK
45808. DBC_DBC32_INCR_SFT
45809. DBC_DBC32_PATH_L2
45810. DBC_DBC32_PATH_LAST
45811. DBC_DBC32_PATH_MASK
45812. DBC_DBC32_PATH_ROCE
45813. DBC_DBC32_PATH_SFT
45814. DBC_DBC32_TYPE_LAST
45815. DBC_DBC32_TYPE_MASK
45816. DBC_DBC32_TYPE_SFT
45817. DBC_DBC32_TYPE_SQ
45818. DBC_DBC32_XID_MASK
45819. DBC_DBC32_XID_SFT
45820. DBC_DBC_DEBUG_TRACE
45821. DBC_DBC_INDEX_MASK
45822. DBC_DBC_INDEX_SFT
45823. DBC_DBC_PATH_ENGINE
45824. DBC_DBC_PATH_L2
45825. DBC_DBC_PATH_LAST
45826. DBC_DBC_PATH_MASK
45827. DBC_DBC_PATH_ROCE
45828. DBC_DBC_PATH_SFT
45829. DBC_DBC_TYPE_CQ
45830. DBC_DBC_TYPE_CQ_ARMALL
45831. DBC_DBC_TYPE_CQ_ARMENA
45832. DBC_DBC_TYPE_CQ_ARMSE
45833. DBC_DBC_TYPE_CQ_CUTOFF_ACK
45834. DBC_DBC_TYPE_LAST
45835. DBC_DBC_TYPE_MASK
45836. DBC_DBC_TYPE_NQ
45837. DBC_DBC_TYPE_NQ_ARM
45838. DBC_DBC_TYPE_NULL
45839. DBC_DBC_TYPE_RQ
45840. DBC_DBC_TYPE_SFT
45841. DBC_DBC_TYPE_SQ
45842. DBC_DBC_TYPE_SRQ
45843. DBC_DBC_TYPE_SRQ_ARM
45844. DBC_DBC_TYPE_SRQ_ARMENA
45845. DBC_DBC_XID_MASK
45846. DBC_DBC_XID_SFT
45847. DBC_DEVICE_REV
45848. DBC_DOOR_BELL_TARGET
45849. DBC_MAX_PACKET
45850. DBC_MAX_STRING_LENGTH
45851. DBC_PERIOD_US
45852. DBC_PORTSC_CONFIG_CHANGE
45853. DBC_PORTSC_CONN_CHANGE
45854. DBC_PORTSC_CONN_STATUS
45855. DBC_PORTSC_LINK_CHANGE
45856. DBC_PORTSC_PORT_ENABLED
45857. DBC_PORTSC_RESET_CHANGE
45858. DBC_PRODUCT_ID
45859. DBC_PROTOCOL
45860. DBC_QUEUE_SIZE
45861. DBC_REG
45862. DBC_STRING_MANUFACTURER
45863. DBC_STRING_PRODUCT
45864. DBC_STRING_SERIAL
45865. DBC_VENDOR_ID
45866. DBC_WRITE_BUF_SIZE
45867. DBDEV_TAB_SIZE
45868. DBDMA_ALIGN
45869. DBDMA_CLEAR
45870. DBDMA_DO_RESET
45871. DBDMA_DO_STOP
45872. DBDMA_MEM_CHAN
45873. DBDMA_NOP
45874. DBDMA_SET
45875. DBDMA_STOP
45876. DBEACON_FRAME_OFF
45877. DBEACON_INFO
45878. DBELL_ADDR
45879. DBELL_DATA
45880. DBELL_DOWN_ARM
45881. DBELL_DOWN_HOST
45882. DBELL_EXITS
45883. DBELL_INF
45884. DBELL_INIT
45885. DBELL_PCI_MASK
45886. DBELL_RESET_ARM
45887. DBELL_RESET_HOST
45888. DBELL_RNWR
45889. DBELL_SA_MASK
45890. DBELL_SID
45891. DBELL_TID
45892. DBELL_UP_ARM
45893. DBELL_UP_HOST
45894. DBF
45895. DBFIFO_HP_INT_F
45896. DBFIFO_HP_INT_S
45897. DBFIFO_HP_INT_V
45898. DBFIFO_LP_INT_F
45899. DBFIFO_LP_INT_S
45900. DBFIFO_LP_INT_V
45901. DBFS_D0C_HDR_VERSION
45902. DBFS_D204_HDR_VERSION
45903. DBFS_D2FC_HDR_VERSION
45904. DBF_ALERT
45905. DBF_CRIT
45906. DBF_DEBUG
45907. DBF_DEV_EVENT
45908. DBF_DEV_HEX
45909. DBF_EMERG
45910. DBF_ERR
45911. DBF_ERROR
45912. DBF_ERROR_HEX
45913. DBF_EVENT
45914. DBF_EVENT_DEVID
45915. DBF_EXCEPTION
45916. DBF_FPD
45917. DBF_HEX
45918. DBF_INFO
45919. DBF_LH
45920. DBF_LIKE_HELL
45921. DBF_LPD
45922. DBF_MAX_SPRINTF_ARGS
45923. DBF_NAME_LEN
45924. DBF_NOTICE
45925. DBF_WARN
45926. DBF_WARNING
45927. DBG
45928. DBG1
45929. DBG2
45930. DBG3
45931. DBG4
45932. DBGA
45933. DBGA2
45934. DBGBH
45935. DBGBXVR
45936. DBGC
45937. DBGCMD
45938. DBGCPUNREN
45939. DBGCPUPREN
45940. DBGCPUREN
45941. DBGC_CUR_DBGBUF_BASE_ADDR_LSB
45942. DBGC_CUR_DBGBUF_BASE_ADDR_MSB
45943. DBGC_CUR_DBGBUF_STATUS
45944. DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK
45945. DBGC_DBGBUF_WRAP_AROUND
45946. DBGC_IN_SAMPLE
45947. DBGC_OUT_CTRL
45948. DBGC_RESUME_CMD
45949. DBGC_SUSPEND_CMD
45950. DBGC_SUSPEND_RESUME
45951. DBGDATA
45952. DBGDCONT
45953. DBGDEV_TYPE
45954. DBGDEV_TYPE_DIQ
45955. DBGDEV_TYPE_ILLEGAL
45956. DBGDEV_TYPE_NODIQ
45957. DBGDEV_TYPE_TEST
45958. DBGEN
45959. DBGERR
45960. DBGF
45961. DBGFS_DUMP
45962. DBGFS_DUMP_DI
45963. DBGFS_PRINT_INT
45964. DBGFS_PRINT_STR
45965. DBGICMDBUSY_F
45966. DBGICMDBUSY_S
45967. DBGICMDBUSY_V
45968. DBGICMDMODE_M
45969. DBGICMDMODE_S
45970. DBGICMDMODE_V
45971. DBGICMDSTRT_F
45972. DBGICMDSTRT_S
45973. DBGICMDSTRT_V
45974. DBGICMD_M
45975. DBGICMD_S
45976. DBGICMD_V
45977. DBGINFO
45978. DBGINST0
45979. DBGINST1
45980. DBGISR
45981. DBGITID_M
45982. DBGITID_S
45983. DBGITID_V
45984. DBGI_MODE_IDT52100
45985. DBGI_MODE_MBUS
45986. DBGLAENABLE_F
45987. DBGLAENABLE_S
45988. DBGLAENABLE_V
45989. DBGLAMODE_G
45990. DBGLAMODE_M
45991. DBGLAMODE_S
45992. DBGLARPTR_M
45993. DBGLARPTR_S
45994. DBGLARPTR_V
45995. DBGLAWHLF_F
45996. DBGLAWHLF_S
45997. DBGLAWHLF_V
45998. DBGLAWPTR_G
45999. DBGLAWPTR_M
46000. DBGLAWPTR_S
46001. DBGLVL_API
46002. DBGLVL_BUF
46003. DBGLVL_BUS
46004. DBGLVL_CMD
46005. DBGLVL_CPU
46006. DBGLVL_DVB
46007. DBGLVL_ENC
46008. DBGLVL_FW
46009. DBGLVL_I2C
46010. DBGLVL_IRQ
46011. DBGLVL_THR
46012. DBGLVL_VBI
46013. DBGMD10_MARK
46014. DBGMD11_MARK
46015. DBGMD20_MARK
46016. DBGMD21_MARK
46017. DBGMDT0_MARK
46018. DBGMDT1_MARK
46019. DBGMDT2_MARK
46020. DBGMODE
46021. DBGPORT
46022. DBGPORTPTR
46023. DBGPR
46024. DBGPR_MDIO
46025. DBGP_CLAIM
46026. DBGP_DONE
46027. DBGP_ENABLED
46028. DBGP_EPADDR
46029. DBGP_ERRCODE
46030. DBGP_ERROR
46031. DBGP_ERR_BAD
46032. DBGP_ERR_SIGNAL
46033. DBGP_GO
46034. DBGP_INUSE
46035. DBGP_LEN
46036. DBGP_LOOPS
46037. DBGP_MAX_PACKET
46038. DBGP_OUT
46039. DBGP_OWNER
46040. DBGP_PID_GET
46041. DBGP_PID_SET
46042. DBGP_REQ_EP0_LEN
46043. DBGP_REQ_LEN
46044. DBGP_TIMEOUT
46045. DBGP_TYPE_MAX
46046. DBGRBUF
46047. DBGRCR_OFFS
46048. DBGS
46049. DBGSEL0
46050. DBGSEL1
46051. DBGSTATUS
46052. DBGSTR
46053. DBGSTR1
46054. DBGSTR3
46055. DBGST_ACTIVE
46056. DBGST_ASLEEP
46057. DBGST_INACTIVE
46058. DBGST_INIT
46059. DBGST_SUSPENDED
46060. DBGTBUF
46061. DBGU0_HWID
46062. DBGU1_HWID
46063. DBGUNDO
46064. DBGU_BASE__INST0_SEG0
46065. DBGU_BASE__INST0_SEG1
46066. DBGU_BASE__INST0_SEG2
46067. DBGU_BASE__INST0_SEG3
46068. DBGU_BASE__INST0_SEG4
46069. DBGU_BASE__INST1_SEG0
46070. DBGU_BASE__INST1_SEG1
46071. DBGU_BASE__INST1_SEG2
46072. DBGU_BASE__INST1_SEG3
46073. DBGU_BASE__INST1_SEG4
46074. DBGU_BASE__INST2_SEG0
46075. DBGU_BASE__INST2_SEG1
46076. DBGU_BASE__INST2_SEG2
46077. DBGU_BASE__INST2_SEG3
46078. DBGU_BASE__INST2_SEG4
46079. DBGU_BASE__INST3_SEG0
46080. DBGU_BASE__INST3_SEG1
46081. DBGU_BASE__INST3_SEG2
46082. DBGU_BASE__INST3_SEG3
46083. DBGU_BASE__INST3_SEG4
46084. DBGU_BASE__INST4_SEG0
46085. DBGU_BASE__INST4_SEG1
46086. DBGU_BASE__INST4_SEG2
46087. DBGU_BASE__INST4_SEG3
46088. DBGU_BASE__INST4_SEG4
46089. DBGU_IO0_BASE__INST0_SEG0
46090. DBGU_IO0_BASE__INST0_SEG1
46091. DBGU_IO0_BASE__INST0_SEG2
46092. DBGU_IO0_BASE__INST0_SEG3
46093. DBGU_IO0_BASE__INST0_SEG4
46094. DBGU_IO0_BASE__INST1_SEG0
46095. DBGU_IO0_BASE__INST1_SEG1
46096. DBGU_IO0_BASE__INST1_SEG2
46097. DBGU_IO0_BASE__INST1_SEG3
46098. DBGU_IO0_BASE__INST1_SEG4
46099. DBGU_IO0_BASE__INST2_SEG0
46100. DBGU_IO0_BASE__INST2_SEG1
46101. DBGU_IO0_BASE__INST2_SEG2
46102. DBGU_IO0_BASE__INST2_SEG3
46103. DBGU_IO0_BASE__INST2_SEG4
46104. DBGU_IO0_BASE__INST3_SEG0
46105. DBGU_IO0_BASE__INST3_SEG1
46106. DBGU_IO0_BASE__INST3_SEG2
46107. DBGU_IO0_BASE__INST3_SEG3
46108. DBGU_IO0_BASE__INST3_SEG4
46109. DBGU_IO0_BASE__INST4_SEG0
46110. DBGU_IO0_BASE__INST4_SEG1
46111. DBGU_IO0_BASE__INST4_SEG2
46112. DBGU_IO0_BASE__INST4_SEG3
46113. DBGU_IO0_BASE__INST4_SEG4
46114. DBGU_IO0_BASE__INST5_SEG0
46115. DBGU_IO0_BASE__INST5_SEG1
46116. DBGU_IO0_BASE__INST5_SEG2
46117. DBGU_IO0_BASE__INST5_SEG3
46118. DBGU_IO0_BASE__INST5_SEG4
46119. DBGU_IO0_BASE__INST6_SEG0
46120. DBGU_IO0_BASE__INST6_SEG1
46121. DBGU_IO0_BASE__INST6_SEG2
46122. DBGU_IO0_BASE__INST6_SEG3
46123. DBGU_IO0_BASE__INST6_SEG4
46124. DBGU_IO_BASE__INST0_SEG0
46125. DBGU_IO_BASE__INST0_SEG1
46126. DBGU_IO_BASE__INST0_SEG2
46127. DBGU_IO_BASE__INST0_SEG3
46128. DBGU_IO_BASE__INST0_SEG4
46129. DBGU_IO_BASE__INST0_SEG5
46130. DBGU_IO_BASE__INST1_SEG0
46131. DBGU_IO_BASE__INST1_SEG1
46132. DBGU_IO_BASE__INST1_SEG2
46133. DBGU_IO_BASE__INST1_SEG3
46134. DBGU_IO_BASE__INST1_SEG4
46135. DBGU_IO_BASE__INST1_SEG5
46136. DBGU_IO_BASE__INST2_SEG0
46137. DBGU_IO_BASE__INST2_SEG1
46138. DBGU_IO_BASE__INST2_SEG2
46139. DBGU_IO_BASE__INST2_SEG3
46140. DBGU_IO_BASE__INST2_SEG4
46141. DBGU_IO_BASE__INST2_SEG5
46142. DBGU_IO_BASE__INST3_SEG0
46143. DBGU_IO_BASE__INST3_SEG1
46144. DBGU_IO_BASE__INST3_SEG2
46145. DBGU_IO_BASE__INST3_SEG3
46146. DBGU_IO_BASE__INST3_SEG4
46147. DBGU_IO_BASE__INST3_SEG5
46148. DBGU_IO_BASE__INST4_SEG0
46149. DBGU_IO_BASE__INST4_SEG1
46150. DBGU_IO_BASE__INST4_SEG2
46151. DBGU_IO_BASE__INST4_SEG3
46152. DBGU_IO_BASE__INST4_SEG4
46153. DBGU_IO_BASE__INST4_SEG5
46154. DBGU_IO_BASE__INST5_SEG0
46155. DBGU_IO_BASE__INST5_SEG1
46156. DBGU_IO_BASE__INST5_SEG2
46157. DBGU_IO_BASE__INST5_SEG3
46158. DBGU_IO_BASE__INST5_SEG4
46159. DBGU_IO_BASE__INST5_SEG5
46160. DBGU_IO_BASE__INST6_SEG0
46161. DBGU_IO_BASE__INST6_SEG1
46162. DBGU_IO_BASE__INST6_SEG2
46163. DBGU_IO_BASE__INST6_SEG3
46164. DBGU_IO_BASE__INST6_SEG4
46165. DBGU_IO_BASE__INST6_SEG5
46166. DBGU_IO_BASE__INST7_SEG0
46167. DBGU_IO_BASE__INST7_SEG1
46168. DBGU_IO_BASE__INST7_SEG2
46169. DBGU_IO_BASE__INST7_SEG3
46170. DBGU_IO_BASE__INST7_SEG4
46171. DBGU_IO_BASE__INST7_SEG5
46172. DBGU_IO_HWID
46173. DBGU_NBIO_BASE__INST0_SEG0
46174. DBGU_NBIO_BASE__INST0_SEG1
46175. DBGU_NBIO_BASE__INST0_SEG2
46176. DBGU_NBIO_BASE__INST0_SEG3
46177. DBGU_NBIO_BASE__INST0_SEG4
46178. DBGU_NBIO_BASE__INST1_SEG0
46179. DBGU_NBIO_BASE__INST1_SEG1
46180. DBGU_NBIO_BASE__INST1_SEG2
46181. DBGU_NBIO_BASE__INST1_SEG3
46182. DBGU_NBIO_BASE__INST1_SEG4
46183. DBGU_NBIO_BASE__INST2_SEG0
46184. DBGU_NBIO_BASE__INST2_SEG1
46185. DBGU_NBIO_BASE__INST2_SEG2
46186. DBGU_NBIO_BASE__INST2_SEG3
46187. DBGU_NBIO_BASE__INST2_SEG4
46188. DBGU_NBIO_BASE__INST3_SEG0
46189. DBGU_NBIO_BASE__INST3_SEG1
46190. DBGU_NBIO_BASE__INST3_SEG2
46191. DBGU_NBIO_BASE__INST3_SEG3
46192. DBGU_NBIO_BASE__INST3_SEG4
46193. DBGU_NBIO_BASE__INST4_SEG0
46194. DBGU_NBIO_BASE__INST4_SEG1
46195. DBGU_NBIO_BASE__INST4_SEG2
46196. DBGU_NBIO_BASE__INST4_SEG3
46197. DBGU_NBIO_BASE__INST4_SEG4
46198. DBGU_NBIO_HWID
46199. DBGVCR32_EL2
46200. DBG_
46201. DBG_0
46202. DBG_1
46203. DBG_8192C
46204. DBG_8712
46205. DBG_871X
46206. DBG_871X_LEVEL
46207. DBG_871X_SEL
46208. DBG_871X_SEL_NL
46209. DBG_88E
46210. DBG_88E_LEVEL
46211. DBG_ACTIVE_EL0
46212. DBG_ACTIVE_EL1
46213. DBG_ADV
46214. DBG_ALL
46215. DBG_APP_NOT_IDLE
46216. DBG_ARCH_ID_RESERVED
46217. DBG_ASS
46218. DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK
46219. DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT
46220. DBG_ATTN_BIT_MAPPING_VAL_MASK
46221. DBG_ATTN_BIT_MAPPING_VAL_SHIFT
46222. DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK
46223. DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT
46224. DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK
46225. DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT
46226. DBG_ATTN_REG_NUM_REG_ATTN_MASK
46227. DBG_ATTN_REG_NUM_REG_ATTN_SHIFT
46228. DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK
46229. DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT
46230. DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK
46231. DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT
46232. DBG_ATTN_REG_STS_ADDRESS_MASK
46233. DBG_ATTN_REG_STS_ADDRESS_SHIFT
46234. DBG_ATTR_MOD
46235. DBG_BASIC
46236. DBG_BCR_BVR_WCR_WVR
46237. DBG_BCR_BVR_WCR_WVR_EL1
46238. DBG_BITMAP
46239. DBG_BLOCK_ID_AVP
46240. DBG_BLOCK_ID_BCI0
46241. DBG_BLOCK_ID_BCI0_BY2
46242. DBG_BLOCK_ID_BCI0_BY4
46243. DBG_BLOCK_ID_BCI0_BY8
46244. DBG_BLOCK_ID_BCI1
46245. DBG_BLOCK_ID_BCI2
46246. DBG_BLOCK_ID_BCI2_BY2
46247. DBG_BLOCK_ID_BCI3
46248. DBG_BLOCK_ID_CB00
46249. DBG_BLOCK_ID_CB00_BY16
46250. DBG_BLOCK_ID_CB00_BY2
46251. DBG_BLOCK_ID_CB00_BY4
46252. DBG_BLOCK_ID_CB00_BY8
46253. DBG_BLOCK_ID_CB01
46254. DBG_BLOCK_ID_CB02
46255. DBG_BLOCK_ID_CB02_BY2
46256. DBG_BLOCK_ID_CB03
46257. DBG_BLOCK_ID_CB04
46258. DBG_BLOCK_ID_CB04_BY2
46259. DBG_BLOCK_ID_CB04_BY4
46260. DBG_BLOCK_ID_CB10
46261. DBG_BLOCK_ID_CB10_BY2
46262. DBG_BLOCK_ID_CB10_BY4
46263. DBG_BLOCK_ID_CB10_BY8
46264. DBG_BLOCK_ID_CB11
46265. DBG_BLOCK_ID_CB12
46266. DBG_BLOCK_ID_CB12_BY2
46267. DBG_BLOCK_ID_CB13
46268. DBG_BLOCK_ID_CB14
46269. DBG_BLOCK_ID_CB14_BY2
46270. DBG_BLOCK_ID_CB14_BY4
46271. DBG_BLOCK_ID_CB_BY2
46272. DBG_BLOCK_ID_CB_BY4
46273. DBG_BLOCK_ID_CB_BY8
46274. DBG_BLOCK_ID_CG
46275. DBG_BLOCK_ID_CG_BY2
46276. DBG_BLOCK_ID_CG_BY4
46277. DBG_BLOCK_ID_CP0
46278. DBG_BLOCK_ID_CP0_BY2
46279. DBG_BLOCK_ID_CP0_BY4
46280. DBG_BLOCK_ID_CP0_BY8
46281. DBG_BLOCK_ID_CP1
46282. DBG_BLOCK_ID_CP2
46283. DBG_BLOCK_ID_CP2_BY2
46284. DBG_BLOCK_ID_CSC
46285. DBG_BLOCK_ID_CSC_BY2
46286. DBG_BLOCK_ID_CSC_BY4
46287. DBG_BLOCK_ID_CSC_BY8
46288. DBG_BLOCK_ID_DB00
46289. DBG_BLOCK_ID_DB00_BY16
46290. DBG_BLOCK_ID_DB00_BY2
46291. DBG_BLOCK_ID_DB00_BY8
46292. DBG_BLOCK_ID_DB01
46293. DBG_BLOCK_ID_DB02
46294. DBG_BLOCK_ID_DB02_BY2
46295. DBG_BLOCK_ID_DB03
46296. DBG_BLOCK_ID_DB04
46297. DBG_BLOCK_ID_DB04_BY2
46298. DBG_BLOCK_ID_DB04_BY4
46299. DBG_BLOCK_ID_DB10
46300. DBG_BLOCK_ID_DB10_BY2
46301. DBG_BLOCK_ID_DB10_BY4
46302. DBG_BLOCK_ID_DB10_BY8
46303. DBG_BLOCK_ID_DB11
46304. DBG_BLOCK_ID_DB12
46305. DBG_BLOCK_ID_DB12_BY2
46306. DBG_BLOCK_ID_DB13
46307. DBG_BLOCK_ID_DB14
46308. DBG_BLOCK_ID_DB14_BY2
46309. DBG_BLOCK_ID_DB14_BY4
46310. DBG_BLOCK_ID_DBG
46311. DBG_BLOCK_ID_DB_BY2
46312. DBG_BLOCK_ID_DB_BY4
46313. DBG_BLOCK_ID_DB_BY8
46314. DBG_BLOCK_ID_DMA0
46315. DBG_BLOCK_ID_DMA0_BY16
46316. DBG_BLOCK_ID_DMA0_BY2
46317. DBG_BLOCK_ID_DMA0_BY4
46318. DBG_BLOCK_ID_DMA0_BY8
46319. DBG_BLOCK_ID_DMA1
46320. DBG_BLOCK_ID_GDS
46321. DBG_BLOCK_ID_GMCON
46322. DBG_BLOCK_ID_GMCON_BY2
46323. DBG_BLOCK_ID_GRBM
46324. DBG_BLOCK_ID_GRBM_BY2
46325. DBG_BLOCK_ID_IA
46326. DBG_BLOCK_ID_IA_BY2
46327. DBG_BLOCK_ID_IH
46328. DBG_BLOCK_ID_IH_BY2
46329. DBG_BLOCK_ID_LDS00
46330. DBG_BLOCK_ID_LDS01
46331. DBG_BLOCK_ID_LDS02
46332. DBG_BLOCK_ID_LDS02_BY2
46333. DBG_BLOCK_ID_LDS03
46334. DBG_BLOCK_ID_LDS04
46335. DBG_BLOCK_ID_LDS04_BY2
46336. DBG_BLOCK_ID_LDS04_BY4
46337. DBG_BLOCK_ID_LDS05
46338. DBG_BLOCK_ID_LDS06
46339. DBG_BLOCK_ID_LDS06_BY2
46340. DBG_BLOCK_ID_LDS07
46341. DBG_BLOCK_ID_LDS08
46342. DBG_BLOCK_ID_LDS08_BY2
46343. DBG_BLOCK_ID_LDS08_BY4
46344. DBG_BLOCK_ID_LDS08_BY8
46345. DBG_BLOCK_ID_LDS09
46346. DBG_BLOCK_ID_LDS0A
46347. DBG_BLOCK_ID_LDS0A_BY2
46348. DBG_BLOCK_ID_LDS0B
46349. DBG_BLOCK_ID_LDS10
46350. DBG_BLOCK_ID_LDS10_BY16
46351. DBG_BLOCK_ID_LDS10_BY2
46352. DBG_BLOCK_ID_LDS10_BY4
46353. DBG_BLOCK_ID_LDS10_BY8
46354. DBG_BLOCK_ID_LDS11
46355. DBG_BLOCK_ID_LDS12
46356. DBG_BLOCK_ID_LDS12_BY2
46357. DBG_BLOCK_ID_LDS13
46358. DBG_BLOCK_ID_LDS14
46359. DBG_BLOCK_ID_LDS14_BY2
46360. DBG_BLOCK_ID_LDS14_BY4
46361. DBG_BLOCK_ID_LDS15
46362. DBG_BLOCK_ID_LDS16
46363. DBG_BLOCK_ID_LDS16_BY2
46364. DBG_BLOCK_ID_LDS17
46365. DBG_BLOCK_ID_LDS18
46366. DBG_BLOCK_ID_LDS18_BY2
46367. DBG_BLOCK_ID_LDS18_BY4
46368. DBG_BLOCK_ID_LDS18_BY8
46369. DBG_BLOCK_ID_LDS19
46370. DBG_BLOCK_ID_LDS1A
46371. DBG_BLOCK_ID_LDS1A_BY2
46372. DBG_BLOCK_ID_LDS1B
46373. DBG_BLOCK_ID_LDS_BY16
46374. DBG_BLOCK_ID_LDS_BY2
46375. DBG_BLOCK_ID_LDS_BY4
46376. DBG_BLOCK_ID_LDS_BY8
46377. DBG_BLOCK_ID_MCB
46378. DBG_BLOCK_ID_MCB_BY2
46379. DBG_BLOCK_ID_MCC0
46380. DBG_BLOCK_ID_MCC0_BY2
46381. DBG_BLOCK_ID_MCC0_BY4
46382. DBG_BLOCK_ID_MCC1
46383. DBG_BLOCK_ID_MCC2
46384. DBG_BLOCK_ID_MCC2_BY2
46385. DBG_BLOCK_ID_MCC3
46386. DBG_BLOCK_ID_MCC_BY2
46387. DBG_BLOCK_ID_MCC_BY4
46388. DBG_BLOCK_ID_MCD0
46389. DBG_BLOCK_ID_MCD0_BY16
46390. DBG_BLOCK_ID_MCD0_BY2
46391. DBG_BLOCK_ID_MCD0_BY4
46392. DBG_BLOCK_ID_MCD0_BY8
46393. DBG_BLOCK_ID_MCD1
46394. DBG_BLOCK_ID_MCD2
46395. DBG_BLOCK_ID_MCD2_BY2
46396. DBG_BLOCK_ID_MCD3
46397. DBG_BLOCK_ID_MCD4
46398. DBG_BLOCK_ID_MCD4_BY2
46399. DBG_BLOCK_ID_MCD4_BY4
46400. DBG_BLOCK_ID_MCD5
46401. DBG_BLOCK_ID_MCD_BY16
46402. DBG_BLOCK_ID_MCD_BY2
46403. DBG_BLOCK_ID_MCD_BY4
46404. DBG_BLOCK_ID_MCD_BY8
46405. DBG_BLOCK_ID_PA0
46406. DBG_BLOCK_ID_PA0_BY2
46407. DBG_BLOCK_ID_PA1
46408. DBG_BLOCK_ID_PA_BY2
46409. DBG_BLOCK_ID_PC0
46410. DBG_BLOCK_ID_PC0_BY2
46411. DBG_BLOCK_ID_PC0_BY4
46412. DBG_BLOCK_ID_PC0_BY8
46413. DBG_BLOCK_ID_PC1
46414. DBG_BLOCK_ID_PDMA
46415. DBG_BLOCK_ID_RESERVED
46416. DBG_BLOCK_ID_RESERVED_BY16
46417. DBG_BLOCK_ID_RESERVED_BY2
46418. DBG_BLOCK_ID_RESERVED_BY4
46419. DBG_BLOCK_ID_RESERVED_BY8
46420. DBG_BLOCK_ID_RLC
46421. DBG_BLOCK_ID_SC
46422. DBG_BLOCK_ID_SCB0
46423. DBG_BLOCK_ID_SCB0_BY16
46424. DBG_BLOCK_ID_SCB0_BY2
46425. DBG_BLOCK_ID_SCB0_BY4
46426. DBG_BLOCK_ID_SCB0_BY8
46427. DBG_BLOCK_ID_SCB1
46428. DBG_BLOCK_ID_SCF0
46429. DBG_BLOCK_ID_SCF0_BY2
46430. DBG_BLOCK_ID_SCF0_BY4
46431. DBG_BLOCK_ID_SCF1
46432. DBG_BLOCK_ID_SCT0
46433. DBG_BLOCK_ID_SCT0_BY2
46434. DBG_BLOCK_ID_SCT0_BY4
46435. DBG_BLOCK_ID_SCT1
46436. DBG_BLOCK_ID_SDMA0
46437. DBG_BLOCK_ID_SDMA0_BY16
46438. DBG_BLOCK_ID_SDMA0_BY2
46439. DBG_BLOCK_ID_SDMA0_BY4
46440. DBG_BLOCK_ID_SDMA0_BY8
46441. DBG_BLOCK_ID_SDMA1
46442. DBG_BLOCK_ID_SEM
46443. DBG_BLOCK_ID_SMU
46444. DBG_BLOCK_ID_SPIM
46445. DBG_BLOCK_ID_SPIM_BY2
46446. DBG_BLOCK_ID_SPIS
46447. DBG_BLOCK_ID_SPIS_BY2
46448. DBG_BLOCK_ID_SPIS_BY4
46449. DBG_BLOCK_ID_SPM0
46450. DBG_BLOCK_ID_SPM0_BY2
46451. DBG_BLOCK_ID_SPM0_BY4
46452. DBG_BLOCK_ID_SPM1
46453. DBG_BLOCK_ID_SPS00
46454. DBG_BLOCK_ID_SPS00_BY2
46455. DBG_BLOCK_ID_SPS00_BY4
46456. DBG_BLOCK_ID_SPS00_BY8
46457. DBG_BLOCK_ID_SPS01
46458. DBG_BLOCK_ID_SPS02
46459. DBG_BLOCK_ID_SPS02_BY2
46460. DBG_BLOCK_ID_SPS10
46461. DBG_BLOCK_ID_SPS11
46462. DBG_BLOCK_ID_SPS11_BY2
46463. DBG_BLOCK_ID_SPS11_BY4
46464. DBG_BLOCK_ID_SPS12
46465. DBG_BLOCK_ID_SPS_BY2
46466. DBG_BLOCK_ID_SPS_BY4
46467. DBG_BLOCK_ID_SPS_BY8
46468. DBG_BLOCK_ID_SQ
46469. DBG_BLOCK_ID_SQ00
46470. DBG_BLOCK_ID_SQ01
46471. DBG_BLOCK_ID_SQ10
46472. DBG_BLOCK_ID_SQ11
46473. DBG_BLOCK_ID_SQA
46474. DBG_BLOCK_ID_SQA00
46475. DBG_BLOCK_ID_SQA01
46476. DBG_BLOCK_ID_SQA02
46477. DBG_BLOCK_ID_SQA02_BY2
46478. DBG_BLOCK_ID_SQA10
46479. DBG_BLOCK_ID_SQA11
46480. DBG_BLOCK_ID_SQA11_BY2
46481. DBG_BLOCK_ID_SQA11_BY4
46482. DBG_BLOCK_ID_SQA12
46483. DBG_BLOCK_ID_SQA_BY2
46484. DBG_BLOCK_ID_SQA_BY4
46485. DBG_BLOCK_ID_SQA_BY8
46486. DBG_BLOCK_ID_SQB00
46487. DBG_BLOCK_ID_SQB01
46488. DBG_BLOCK_ID_SQB10
46489. DBG_BLOCK_ID_SQB10_BY2
46490. DBG_BLOCK_ID_SQB11
46491. DBG_BLOCK_ID_SQB_BY16
46492. DBG_BLOCK_ID_SQB_BY2
46493. DBG_BLOCK_ID_SQB_BY4
46494. DBG_BLOCK_ID_SQB_BY8
46495. DBG_BLOCK_ID_SQ_BY2
46496. DBG_BLOCK_ID_SQ_BY4
46497. DBG_BLOCK_ID_SRBM
46498. DBG_BLOCK_ID_SX0
46499. DBG_BLOCK_ID_SX0_BY16
46500. DBG_BLOCK_ID_SX0_BY2
46501. DBG_BLOCK_ID_SX0_BY4
46502. DBG_BLOCK_ID_SX0_BY8
46503. DBG_BLOCK_ID_SX1
46504. DBG_BLOCK_ID_SX2
46505. DBG_BLOCK_ID_SX2_BY2
46506. DBG_BLOCK_ID_SX3
46507. DBG_BLOCK_ID_SXM0
46508. DBG_BLOCK_ID_SXM0_BY2
46509. DBG_BLOCK_ID_SXM0_BY4
46510. DBG_BLOCK_ID_SXM0_BY8
46511. DBG_BLOCK_ID_SXM1
46512. DBG_BLOCK_ID_SXM_BY16
46513. DBG_BLOCK_ID_SXS0
46514. DBG_BLOCK_ID_SXS1
46515. DBG_BLOCK_ID_SXS2
46516. DBG_BLOCK_ID_SXS2_BY2
46517. DBG_BLOCK_ID_SXS3
46518. DBG_BLOCK_ID_SXS4
46519. DBG_BLOCK_ID_SXS4_BY2
46520. DBG_BLOCK_ID_SXS4_BY4
46521. DBG_BLOCK_ID_SXS5
46522. DBG_BLOCK_ID_SXS6
46523. DBG_BLOCK_ID_SXS6_BY2
46524. DBG_BLOCK_ID_SXS7
46525. DBG_BLOCK_ID_SXS8
46526. DBG_BLOCK_ID_SXS9
46527. DBG_BLOCK_ID_SXS_BY16
46528. DBG_BLOCK_ID_SXS_BY2
46529. DBG_BLOCK_ID_SXS_BY4
46530. DBG_BLOCK_ID_SXS_BY8
46531. DBG_BLOCK_ID_TA00
46532. DBG_BLOCK_ID_TA00_BY16
46533. DBG_BLOCK_ID_TA00_BY2
46534. DBG_BLOCK_ID_TA00_BY4
46535. DBG_BLOCK_ID_TA00_BY8
46536. DBG_BLOCK_ID_TA01
46537. DBG_BLOCK_ID_TA02
46538. DBG_BLOCK_ID_TA02_BY2
46539. DBG_BLOCK_ID_TA03
46540. DBG_BLOCK_ID_TA04
46541. DBG_BLOCK_ID_TA04_BY2
46542. DBG_BLOCK_ID_TA04_BY4
46543. DBG_BLOCK_ID_TA05
46544. DBG_BLOCK_ID_TA06
46545. DBG_BLOCK_ID_TA06_BY2
46546. DBG_BLOCK_ID_TA07
46547. DBG_BLOCK_ID_TA08
46548. DBG_BLOCK_ID_TA08_BY2
46549. DBG_BLOCK_ID_TA08_BY4
46550. DBG_BLOCK_ID_TA08_BY8
46551. DBG_BLOCK_ID_TA09
46552. DBG_BLOCK_ID_TA0A
46553. DBG_BLOCK_ID_TA0A_BY2
46554. DBG_BLOCK_ID_TA0B
46555. DBG_BLOCK_ID_TA10
46556. DBG_BLOCK_ID_TA10_BY16
46557. DBG_BLOCK_ID_TA10_BY2
46558. DBG_BLOCK_ID_TA10_BY4
46559. DBG_BLOCK_ID_TA10_BY8
46560. DBG_BLOCK_ID_TA11
46561. DBG_BLOCK_ID_TA12
46562. DBG_BLOCK_ID_TA12_BY2
46563. DBG_BLOCK_ID_TA13
46564. DBG_BLOCK_ID_TA14
46565. DBG_BLOCK_ID_TA14_BY2
46566. DBG_BLOCK_ID_TA14_BY4
46567. DBG_BLOCK_ID_TA15
46568. DBG_BLOCK_ID_TA16
46569. DBG_BLOCK_ID_TA16_BY2
46570. DBG_BLOCK_ID_TA17
46571. DBG_BLOCK_ID_TA18
46572. DBG_BLOCK_ID_TA18_BY2
46573. DBG_BLOCK_ID_TA18_BY4
46574. DBG_BLOCK_ID_TA18_BY8
46575. DBG_BLOCK_ID_TA19
46576. DBG_BLOCK_ID_TA1A
46577. DBG_BLOCK_ID_TA1A_BY2
46578. DBG_BLOCK_ID_TA1B
46579. DBG_BLOCK_ID_TA_BY16
46580. DBG_BLOCK_ID_TA_BY2
46581. DBG_BLOCK_ID_TA_BY4
46582. DBG_BLOCK_ID_TA_BY8
46583. DBG_BLOCK_ID_TCAA
46584. DBG_BLOCK_ID_TCAA_BY2
46585. DBG_BLOCK_ID_TCAA_BY4
46586. DBG_BLOCK_ID_TCAA_BY8
46587. DBG_BLOCK_ID_TCAB
46588. DBG_BLOCK_ID_TCA_BY2
46589. DBG_BLOCK_ID_TCA_BY8
46590. DBG_BLOCK_ID_TCC0
46591. DBG_BLOCK_ID_TCC0_BY16
46592. DBG_BLOCK_ID_TCC0_BY2
46593. DBG_BLOCK_ID_TCC0_BY4
46594. DBG_BLOCK_ID_TCC0_BY8
46595. DBG_BLOCK_ID_TCC1
46596. DBG_BLOCK_ID_TCC2
46597. DBG_BLOCK_ID_TCC2_BY2
46598. DBG_BLOCK_ID_TCC3
46599. DBG_BLOCK_ID_TCC4
46600. DBG_BLOCK_ID_TCC4_BY2
46601. DBG_BLOCK_ID_TCC4_BY4
46602. DBG_BLOCK_ID_TCC5
46603. DBG_BLOCK_ID_TCC6
46604. DBG_BLOCK_ID_TCC6_BY2
46605. DBG_BLOCK_ID_TCC7
46606. DBG_BLOCK_ID_TCCA
46607. DBG_BLOCK_ID_TCCA_BY2
46608. DBG_BLOCK_ID_TCCB
46609. DBG_BLOCK_ID_TCC_BY16
46610. DBG_BLOCK_ID_TCC_BY2
46611. DBG_BLOCK_ID_TCC_BY4
46612. DBG_BLOCK_ID_TCC_BY8
46613. DBG_BLOCK_ID_TCP0
46614. DBG_BLOCK_ID_TCP0_BY16
46615. DBG_BLOCK_ID_TCP0_BY2
46616. DBG_BLOCK_ID_TCP0_BY4
46617. DBG_BLOCK_ID_TCP0_BY8
46618. DBG_BLOCK_ID_TCP1
46619. DBG_BLOCK_ID_TCP10
46620. DBG_BLOCK_ID_TCP10_BY2
46621. DBG_BLOCK_ID_TCP11
46622. DBG_BLOCK_ID_TCP12
46623. DBG_BLOCK_ID_TCP12_BY2
46624. DBG_BLOCK_ID_TCP12_BY4
46625. DBG_BLOCK_ID_TCP13
46626. DBG_BLOCK_ID_TCP14
46627. DBG_BLOCK_ID_TCP14_BY2
46628. DBG_BLOCK_ID_TCP15
46629. DBG_BLOCK_ID_TCP16
46630. DBG_BLOCK_ID_TCP16_BY16
46631. DBG_BLOCK_ID_TCP16_BY2
46632. DBG_BLOCK_ID_TCP16_BY4
46633. DBG_BLOCK_ID_TCP16_BY8
46634. DBG_BLOCK_ID_TCP17
46635. DBG_BLOCK_ID_TCP18
46636. DBG_BLOCK_ID_TCP18_BY2
46637. DBG_BLOCK_ID_TCP19
46638. DBG_BLOCK_ID_TCP2
46639. DBG_BLOCK_ID_TCP20
46640. DBG_BLOCK_ID_TCP20_BY2
46641. DBG_BLOCK_ID_TCP20_BY4
46642. DBG_BLOCK_ID_TCP21
46643. DBG_BLOCK_ID_TCP22
46644. DBG_BLOCK_ID_TCP22_BY2
46645. DBG_BLOCK_ID_TCP23
46646. DBG_BLOCK_ID_TCP2_BY2
46647. DBG_BLOCK_ID_TCP3
46648. DBG_BLOCK_ID_TCP4
46649. DBG_BLOCK_ID_TCP4_BY2
46650. DBG_BLOCK_ID_TCP4_BY4
46651. DBG_BLOCK_ID_TCP5
46652. DBG_BLOCK_ID_TCP6
46653. DBG_BLOCK_ID_TCP6_BY2
46654. DBG_BLOCK_ID_TCP7
46655. DBG_BLOCK_ID_TCP8
46656. DBG_BLOCK_ID_TCP8_BY2
46657. DBG_BLOCK_ID_TCP8_BY4
46658. DBG_BLOCK_ID_TCP8_BY8
46659. DBG_BLOCK_ID_TCP9
46660. DBG_BLOCK_ID_TCP_BY16
46661. DBG_BLOCK_ID_TCP_BY2
46662. DBG_BLOCK_ID_TCP_BY4
46663. DBG_BLOCK_ID_TCP_BY8
46664. DBG_BLOCK_ID_TCP_RESERVED0
46665. DBG_BLOCK_ID_TCP_RESERVED0_BY2
46666. DBG_BLOCK_ID_TCP_RESERVED0_BY4
46667. DBG_BLOCK_ID_TCP_RESERVED0_BY8
46668. DBG_BLOCK_ID_TCP_RESERVED1
46669. DBG_BLOCK_ID_TCP_RESERVED2
46670. DBG_BLOCK_ID_TCP_RESERVED2_BY2
46671. DBG_BLOCK_ID_TCP_RESERVED3
46672. DBG_BLOCK_ID_TCP_RESERVED4
46673. DBG_BLOCK_ID_TCP_RESERVED4_BY2
46674. DBG_BLOCK_ID_TCP_RESERVED4_BY4
46675. DBG_BLOCK_ID_TCP_RESERVED5
46676. DBG_BLOCK_ID_TCP_RESERVED6
46677. DBG_BLOCK_ID_TCP_RESERVED6_BY2
46678. DBG_BLOCK_ID_TCP_RESERVED7
46679. DBG_BLOCK_ID_TD00
46680. DBG_BLOCK_ID_TD00_BY16
46681. DBG_BLOCK_ID_TD00_BY2
46682. DBG_BLOCK_ID_TD00_BY4
46683. DBG_BLOCK_ID_TD00_BY8
46684. DBG_BLOCK_ID_TD01
46685. DBG_BLOCK_ID_TD02
46686. DBG_BLOCK_ID_TD02_BY2
46687. DBG_BLOCK_ID_TD03
46688. DBG_BLOCK_ID_TD04
46689. DBG_BLOCK_ID_TD04_BY2
46690. DBG_BLOCK_ID_TD04_BY4
46691. DBG_BLOCK_ID_TD05
46692. DBG_BLOCK_ID_TD06
46693. DBG_BLOCK_ID_TD06_BY2
46694. DBG_BLOCK_ID_TD07
46695. DBG_BLOCK_ID_TD08
46696. DBG_BLOCK_ID_TD08_BY2
46697. DBG_BLOCK_ID_TD08_BY4
46698. DBG_BLOCK_ID_TD08_BY8
46699. DBG_BLOCK_ID_TD09
46700. DBG_BLOCK_ID_TD0A
46701. DBG_BLOCK_ID_TD0A_BY2
46702. DBG_BLOCK_ID_TD0B
46703. DBG_BLOCK_ID_TD10
46704. DBG_BLOCK_ID_TD10_BY16
46705. DBG_BLOCK_ID_TD10_BY2
46706. DBG_BLOCK_ID_TD10_BY4
46707. DBG_BLOCK_ID_TD10_BY8
46708. DBG_BLOCK_ID_TD11
46709. DBG_BLOCK_ID_TD12
46710. DBG_BLOCK_ID_TD12_BY2
46711. DBG_BLOCK_ID_TD13
46712. DBG_BLOCK_ID_TD14
46713. DBG_BLOCK_ID_TD14_BY2
46714. DBG_BLOCK_ID_TD14_BY4
46715. DBG_BLOCK_ID_TD15
46716. DBG_BLOCK_ID_TD16
46717. DBG_BLOCK_ID_TD16_BY2
46718. DBG_BLOCK_ID_TD17
46719. DBG_BLOCK_ID_TD18
46720. DBG_BLOCK_ID_TD18_BY2
46721. DBG_BLOCK_ID_TD18_BY4
46722. DBG_BLOCK_ID_TD18_BY8
46723. DBG_BLOCK_ID_TD19
46724. DBG_BLOCK_ID_TD1A
46725. DBG_BLOCK_ID_TD1A_BY2
46726. DBG_BLOCK_ID_TD1B
46727. DBG_BLOCK_ID_TD_BY16
46728. DBG_BLOCK_ID_TD_BY2
46729. DBG_BLOCK_ID_TD_BY4
46730. DBG_BLOCK_ID_TD_BY8
46731. DBG_BLOCK_ID_UNUSED0
46732. DBG_BLOCK_ID_UNUSED0_BY2
46733. DBG_BLOCK_ID_UNUSED0_BY4
46734. DBG_BLOCK_ID_UNUSED1
46735. DBG_BLOCK_ID_UNUSED10
46736. DBG_BLOCK_ID_UNUSED10_BY2
46737. DBG_BLOCK_ID_UNUSED10_BY4
46738. DBG_BLOCK_ID_UNUSED11
46739. DBG_BLOCK_ID_UNUSED12
46740. DBG_BLOCK_ID_UNUSED12_BY2
46741. DBG_BLOCK_ID_UNUSED13
46742. DBG_BLOCK_ID_UNUSED13_BY2
46743. DBG_BLOCK_ID_UNUSED14
46744. DBG_BLOCK_ID_UNUSED14_BY2
46745. DBG_BLOCK_ID_UNUSED15
46746. DBG_BLOCK_ID_UNUSED15_BY2
46747. DBG_BLOCK_ID_UNUSED16
46748. DBG_BLOCK_ID_UNUSED17
46749. DBG_BLOCK_ID_UNUSED17_BY2
46750. DBG_BLOCK_ID_UNUSED17_BY4
46751. DBG_BLOCK_ID_UNUSED18
46752. DBG_BLOCK_ID_UNUSED19
46753. DBG_BLOCK_ID_UNUSED19_BY2
46754. DBG_BLOCK_ID_UNUSED1_BY4
46755. DBG_BLOCK_ID_UNUSED2
46756. DBG_BLOCK_ID_UNUSED20
46757. DBG_BLOCK_ID_UNUSED20_BY2
46758. DBG_BLOCK_ID_UNUSED20_BY4
46759. DBG_BLOCK_ID_UNUSED21
46760. DBG_BLOCK_ID_UNUSED22
46761. DBG_BLOCK_ID_UNUSED22_BY2
46762. DBG_BLOCK_ID_UNUSED23
46763. DBG_BLOCK_ID_UNUSED24
46764. DBG_BLOCK_ID_UNUSED24_BY2
46765. DBG_BLOCK_ID_UNUSED24_BY4
46766. DBG_BLOCK_ID_UNUSED25
46767. DBG_BLOCK_ID_UNUSED25_BY2
46768. DBG_BLOCK_ID_UNUSED26
46769. DBG_BLOCK_ID_UNUSED26_BY2
46770. DBG_BLOCK_ID_UNUSED27
46771. DBG_BLOCK_ID_UNUSED28
46772. DBG_BLOCK_ID_UNUSED28_BY2
46773. DBG_BLOCK_ID_UNUSED28_BY4
46774. DBG_BLOCK_ID_UNUSED29
46775. DBG_BLOCK_ID_UNUSED3
46776. DBG_BLOCK_ID_UNUSED30
46777. DBG_BLOCK_ID_UNUSED30_BY2
46778. DBG_BLOCK_ID_UNUSED31
46779. DBG_BLOCK_ID_UNUSED31_BY2
46780. DBG_BLOCK_ID_UNUSED32
46781. DBG_BLOCK_ID_UNUSED32_BY2
46782. DBG_BLOCK_ID_UNUSED32_BY4
46783. DBG_BLOCK_ID_UNUSED33
46784. DBG_BLOCK_ID_UNUSED33_BY2
46785. DBG_BLOCK_ID_UNUSED34
46786. DBG_BLOCK_ID_UNUSED34_BY2
46787. DBG_BLOCK_ID_UNUSED35
46788. DBG_BLOCK_ID_UNUSED35_BY2
46789. DBG_BLOCK_ID_UNUSED35_BY4
46790. DBG_BLOCK_ID_UNUSED36
46791. DBG_BLOCK_ID_UNUSED36_BY2
46792. DBG_BLOCK_ID_UNUSED36_BY4
46793. DBG_BLOCK_ID_UNUSED37
46794. DBG_BLOCK_ID_UNUSED37_BY2
46795. DBG_BLOCK_ID_UNUSED38
46796. DBG_BLOCK_ID_UNUSED38_BY2
46797. DBG_BLOCK_ID_UNUSED39
46798. DBG_BLOCK_ID_UNUSED39_BY2
46799. DBG_BLOCK_ID_UNUSED39_BY4
46800. DBG_BLOCK_ID_UNUSED4
46801. DBG_BLOCK_ID_UNUSED40
46802. DBG_BLOCK_ID_UNUSED40_BY2
46803. DBG_BLOCK_ID_UNUSED40_BY4
46804. DBG_BLOCK_ID_UNUSED41
46805. DBG_BLOCK_ID_UNUSED41_BY2
46806. DBG_BLOCK_ID_UNUSED42
46807. DBG_BLOCK_ID_UNUSED42_BY2
46808. DBG_BLOCK_ID_UNUSED43
46809. DBG_BLOCK_ID_UNUSED43_BY2
46810. DBG_BLOCK_ID_UNUSED43_BY4
46811. DBG_BLOCK_ID_UNUSED44
46812. DBG_BLOCK_ID_UNUSED45
46813. DBG_BLOCK_ID_UNUSED45_BY2
46814. DBG_BLOCK_ID_UNUSED46
46815. DBG_BLOCK_ID_UNUSED47
46816. DBG_BLOCK_ID_UNUSED47_BY2
46817. DBG_BLOCK_ID_UNUSED47_BY4
46818. DBG_BLOCK_ID_UNUSED48
46819. DBG_BLOCK_ID_UNUSED49
46820. DBG_BLOCK_ID_UNUSED49_BY2
46821. DBG_BLOCK_ID_UNUSED4_BY2
46822. DBG_BLOCK_ID_UNUSED4_BY4
46823. DBG_BLOCK_ID_UNUSED5
46824. DBG_BLOCK_ID_UNUSED50
46825. DBG_BLOCK_ID_UNUSED51
46826. DBG_BLOCK_ID_UNUSED51_BY2
46827. DBG_BLOCK_ID_UNUSED52
46828. DBG_BLOCK_ID_UNUSED6
46829. DBG_BLOCK_ID_UNUSED6_BY2
46830. DBG_BLOCK_ID_UNUSED7
46831. DBG_BLOCK_ID_UNUSED8
46832. DBG_BLOCK_ID_UNUSED8_BY2
46833. DBG_BLOCK_ID_UNUSED9
46834. DBG_BLOCK_ID_UVDM
46835. DBG_BLOCK_ID_UVDU
46836. DBG_BLOCK_ID_UVDU_BY2
46837. DBG_BLOCK_ID_UVDU_BY4
46838. DBG_BLOCK_ID_UVD_BY2
46839. DBG_BLOCK_ID_VC0
46840. DBG_BLOCK_ID_VC0_BY2
46841. DBG_BLOCK_ID_VC0_BY4
46842. DBG_BLOCK_ID_VC1
46843. DBG_BLOCK_ID_VCE
46844. DBG_BLOCK_ID_VCE_BY2
46845. DBG_BLOCK_ID_VGT0
46846. DBG_BLOCK_ID_VGT0_BY16
46847. DBG_BLOCK_ID_VGT0_BY2
46848. DBG_BLOCK_ID_VGT0_BY4
46849. DBG_BLOCK_ID_VGT0_BY8
46850. DBG_BLOCK_ID_VGT1
46851. DBG_BLOCK_ID_VMC
46852. DBG_BLOCK_ID_VMC_BY2
46853. DBG_BLOCK_ID_XBR
46854. DBG_BNODE_MOD
46855. DBG_BNODE_REFS
46856. DBG_BPT
46857. DBG_BSS_MATCH
46858. DBG_BSS_TABLE
46859. DBG_BSS_TABLE_RM
46860. DBG_BTB_FLUSH
46861. DBG_BT_INFO
46862. DBG_BT_INFO_INIT
46863. DBG_BUFFER
46864. DBG_BUGON
46865. DBG_BUS
46866. DBG_BUSY
46867. DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK
46868. DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT
46869. DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK
46870. DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT
46871. DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK
46872. DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT
46873. DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK
46874. DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT
46875. DBG_BUS_CLIENT_CPU
46876. DBG_BUS_CLIENT_OTHER_ENGINE
46877. DBG_BUS_CLIENT_RBCB
46878. DBG_BUS_CLIENT_RBCF
46879. DBG_BUS_CLIENT_RBCH
46880. DBG_BUS_CLIENT_RBCM
46881. DBG_BUS_CLIENT_RBCN
46882. DBG_BUS_CLIENT_RBCP
46883. DBG_BUS_CLIENT_RBCQ
46884. DBG_BUS_CLIENT_RBCR
46885. DBG_BUS_CLIENT_RBCS
46886. DBG_BUS_CLIENT_RBCT
46887. DBG_BUS_CLIENT_RBCU
46888. DBG_BUS_CLIENT_RBCV
46889. DBG_BUS_CLIENT_RBCW
46890. DBG_BUS_CLIENT_RBCX
46891. DBG_BUS_CLIENT_RBCY
46892. DBG_BUS_CLIENT_RBCZ
46893. DBG_BUS_CLIENT_TIMESTAMP
46894. DBG_BUS_CONSTRAINT_OP_EQ
46895. DBG_BUS_CONSTRAINT_OP_GE
46896. DBG_BUS_CONSTRAINT_OP_GEC
46897. DBG_BUS_CONSTRAINT_OP_GT
46898. DBG_BUS_CONSTRAINT_OP_GTC
46899. DBG_BUS_CONSTRAINT_OP_LE
46900. DBG_BUS_CONSTRAINT_OP_LEC
46901. DBG_BUS_CONSTRAINT_OP_LT
46902. DBG_BUS_CONSTRAINT_OP_LTC
46903. DBG_BUS_CONSTRAINT_OP_NE
46904. DBG_BUS_FILTER_TYPE_OFF
46905. DBG_BUS_FILTER_TYPE_ON
46906. DBG_BUS_FILTER_TYPE_POST
46907. DBG_BUS_FILTER_TYPE_PRE
46908. DBG_BUS_FRAME_MODE_0HW_4ST
46909. DBG_BUS_FRAME_MODE_4HW_0ST
46910. DBG_BUS_FRAME_MODE_8HW_0ST
46911. DBG_BUS_LINE_IS_256B_MASK
46912. DBG_BUS_LINE_IS_256B_SHIFT
46913. DBG_BUS_LINE_NUM_OF_GROUPS_MASK
46914. DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT
46915. DBG_BUS_LINE_RESERVED_MASK
46916. DBG_BUS_LINE_RESERVED_SHIFT
46917. DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX
46918. DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX
46919. DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX
46920. DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX
46921. DBG_BUS_OTHER_ENGINE_MODE_NONE
46922. DBG_BUS_POST_TRIGGER_DROP
46923. DBG_BUS_POST_TRIGGER_RECORD
46924. DBG_BUS_PRE_TRIGGER_DROP
46925. DBG_BUS_PRE_TRIGGER_NUM_CHUNKS
46926. DBG_BUS_PRE_TRIGGER_START_FROM_ZERO
46927. DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST
46928. DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST
46929. DBG_BUS_STATE_IDLE
46930. DBG_BUS_STATE_READY
46931. DBG_BUS_STATE_RECORDING
46932. DBG_BUS_STATE_STOPPED
46933. DBG_BUS_STORM_MODE_DRA_FSM
46934. DBG_BUS_STORM_MODE_DRA_RW
46935. DBG_BUS_STORM_MODE_DRA_W
46936. DBG_BUS_STORM_MODE_EXT_STORE
46937. DBG_BUS_STORM_MODE_FOC
46938. DBG_BUS_STORM_MODE_LD_ST_ADDR
46939. DBG_BUS_STORM_MODE_PRAM_ADDR
46940. DBG_BUS_STORM_MODE_PRINTF
46941. DBG_BUS_STORM_MODE_RH
46942. DBG_BUS_TARGET_ID_INT_BUF
46943. DBG_BUS_TARGET_ID_NIG
46944. DBG_BUS_TARGET_ID_PCI
46945. DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK
46946. DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT
46947. DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK
46948. DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT
46949. DBG_BYPASS
46950. DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD_MASK
46951. DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD__SHIFT
46952. DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN_MASK
46953. DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT
46954. DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK
46955. DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT
46956. DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK
46957. DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT
46958. DBG_CAL
46959. DBG_CARR
46960. DBG_CAT_MOD
46961. DBG_CFG
46962. DBG_CHOP
46963. DBG_CLIENT_BLKID_RESERVED
46964. DBG_CLIENT_BLKID_RESERVED_LAST
46965. DBG_CLIENT_BLKID_acp_0
46966. DBG_CLIENT_BLKID_acp_1
46967. DBG_CLIENT_BLKID_bci0
46968. DBG_CLIENT_BLKID_bci1
46969. DBG_CLIENT_BLKID_bci2
46970. DBG_CLIENT_BLKID_bci3
46971. DBG_CLIENT_BLKID_bif
46972. DBG_CLIENT_BLKID_cb0
46973. DBG_CLIENT_BLKID_cb000
46974. DBG_CLIENT_BLKID_cb001
46975. DBG_CLIENT_BLKID_cb002
46976. DBG_CLIENT_BLKID_cb003
46977. DBG_CLIENT_BLKID_cb1
46978. DBG_CLIENT_BLKID_cb100
46979. DBG_CLIENT_BLKID_cb101
46980. DBG_CLIENT_BLKID_cb102
46981. DBG_CLIENT_BLKID_cb103
46982. DBG_CLIENT_BLKID_cb2
46983. DBG_CLIENT_BLKID_cb200
46984. DBG_CLIENT_BLKID_cb201
46985. DBG_CLIENT_BLKID_cb202
46986. DBG_CLIENT_BLKID_cb203
46987. DBG_CLIENT_BLKID_cb3
46988. DBG_CLIENT_BLKID_cb300
46989. DBG_CLIENT_BLKID_cb301
46990. DBG_CLIENT_BLKID_cb302
46991. DBG_CLIENT_BLKID_cb303
46992. DBG_CLIENT_BLKID_cbr0
46993. DBG_CLIENT_BLKID_cbr1
46994. DBG_CLIENT_BLKID_cpc_0
46995. DBG_CLIENT_BLKID_cpc_1
46996. DBG_CLIENT_BLKID_cpf
46997. DBG_CLIENT_BLKID_cpf_0
46998. DBG_CLIENT_BLKID_cpf_1
46999. DBG_CLIENT_BLKID_cpg_0
47000. DBG_CLIENT_BLKID_cpg_1
47001. DBG_CLIENT_BLKID_dbg
47002. DBG_CLIENT_BLKID_dccg0_0
47003. DBG_CLIENT_BLKID_dccg0_1
47004. DBG_CLIENT_BLKID_dccg0_2
47005. DBG_CLIENT_BLKID_dccg0_3
47006. DBG_CLIENT_BLKID_dccg0_4
47007. DBG_CLIENT_BLKID_dccg0_5
47008. DBG_CLIENT_BLKID_dccg0_6
47009. DBG_CLIENT_BLKID_dccg0_7
47010. DBG_CLIENT_BLKID_dccg0_8
47011. DBG_CLIENT_BLKID_dcfe01_0
47012. DBG_CLIENT_BLKID_dcfe02_0
47013. DBG_CLIENT_BLKID_dcfe03_0
47014. DBG_CLIENT_BLKID_dcfe04_0
47015. DBG_CLIENT_BLKID_dcfe05_0
47016. DBG_CLIENT_BLKID_dcfe06_0
47017. DBG_CLIENT_BLKID_dci_0
47018. DBG_CLIENT_BLKID_dci_pg
47019. DBG_CLIENT_BLKID_dco
47020. DBG_CLIENT_BLKID_dco0
47021. DBG_CLIENT_BLKID_ds
47022. DBG_CLIENT_BLKID_ds0
47023. DBG_CLIENT_BLKID_gck
47024. DBG_CLIENT_BLKID_gdc_0
47025. DBG_CLIENT_BLKID_gdc_1
47026. DBG_CLIENT_BLKID_gdc_10
47027. DBG_CLIENT_BLKID_gdc_11
47028. DBG_CLIENT_BLKID_gdc_12
47029. DBG_CLIENT_BLKID_gdc_13
47030. DBG_CLIENT_BLKID_gdc_14
47031. DBG_CLIENT_BLKID_gdc_15
47032. DBG_CLIENT_BLKID_gdc_16
47033. DBG_CLIENT_BLKID_gdc_17
47034. DBG_CLIENT_BLKID_gdc_18
47035. DBG_CLIENT_BLKID_gdc_19
47036. DBG_CLIENT_BLKID_gdc_2
47037. DBG_CLIENT_BLKID_gdc_20
47038. DBG_CLIENT_BLKID_gdc_21
47039. DBG_CLIENT_BLKID_gdc_22
47040. DBG_CLIENT_BLKID_gdc_23
47041. DBG_CLIENT_BLKID_gdc_24
47042. DBG_CLIENT_BLKID_gdc_25
47043. DBG_CLIENT_BLKID_gdc_26
47044. DBG_CLIENT_BLKID_gdc_27
47045. DBG_CLIENT_BLKID_gdc_28
47046. DBG_CLIENT_BLKID_gdc_3
47047. DBG_CLIENT_BLKID_gdc_4
47048. DBG_CLIENT_BLKID_gdc_5
47049. DBG_CLIENT_BLKID_gdc_6
47050. DBG_CLIENT_BLKID_gdc_7
47051. DBG_CLIENT_BLKID_gdc_8
47052. DBG_CLIENT_BLKID_gdc_9
47053. DBG_CLIENT_BLKID_gdc_one_0
47054. DBG_CLIENT_BLKID_gdc_one_1
47055. DBG_CLIENT_BLKID_gdc_one_10
47056. DBG_CLIENT_BLKID_gdc_one_11
47057. DBG_CLIENT_BLKID_gdc_one_12
47058. DBG_CLIENT_BLKID_gdc_one_13
47059. DBG_CLIENT_BLKID_gdc_one_14
47060. DBG_CLIENT_BLKID_gdc_one_15
47061. DBG_CLIENT_BLKID_gdc_one_16
47062. DBG_CLIENT_BLKID_gdc_one_17
47063. DBG_CLIENT_BLKID_gdc_one_18
47064. DBG_CLIENT_BLKID_gdc_one_19
47065. DBG_CLIENT_BLKID_gdc_one_2
47066. DBG_CLIENT_BLKID_gdc_one_20
47067. DBG_CLIENT_BLKID_gdc_one_21
47068. DBG_CLIENT_BLKID_gdc_one_22
47069. DBG_CLIENT_BLKID_gdc_one_23
47070. DBG_CLIENT_BLKID_gdc_one_24
47071. DBG_CLIENT_BLKID_gdc_one_25
47072. DBG_CLIENT_BLKID_gdc_one_26
47073. DBG_CLIENT_BLKID_gdc_one_27
47074. DBG_CLIENT_BLKID_gdc_one_28
47075. DBG_CLIENT_BLKID_gdc_one_29
47076. DBG_CLIENT_BLKID_gdc_one_3
47077. DBG_CLIENT_BLKID_gdc_one_30
47078. DBG_CLIENT_BLKID_gdc_one_31
47079. DBG_CLIENT_BLKID_gdc_one_32
47080. DBG_CLIENT_BLKID_gdc_one_33
47081. DBG_CLIENT_BLKID_gdc_one_34
47082. DBG_CLIENT_BLKID_gdc_one_35
47083. DBG_CLIENT_BLKID_gdc_one_4
47084. DBG_CLIENT_BLKID_gdc_one_5
47085. DBG_CLIENT_BLKID_gdc_one_6
47086. DBG_CLIENT_BLKID_gdc_one_7
47087. DBG_CLIENT_BLKID_gdc_one_8
47088. DBG_CLIENT_BLKID_gdc_one_9
47089. DBG_CLIENT_BLKID_gmcon
47090. DBG_CLIENT_BLKID_grbm
47091. DBG_CLIENT_BLKID_hdp
47092. DBG_CLIENT_BLKID_ia0
47093. DBG_CLIENT_BLKID_ia1
47094. DBG_CLIENT_BLKID_ih
47095. DBG_CLIENT_BLKID_mcb
47096. DBG_CLIENT_BLKID_mcc0
47097. DBG_CLIENT_BLKID_mcc1
47098. DBG_CLIENT_BLKID_mcc2
47099. DBG_CLIENT_BLKID_mcc3
47100. DBG_CLIENT_BLKID_mcc4
47101. DBG_CLIENT_BLKID_mcc5
47102. DBG_CLIENT_BLKID_mcc6
47103. DBG_CLIENT_BLKID_mcc7
47104. DBG_CLIENT_BLKID_mcd0
47105. DBG_CLIENT_BLKID_mcd0_0
47106. DBG_CLIENT_BLKID_mcd0_1
47107. DBG_CLIENT_BLKID_mcd1
47108. DBG_CLIENT_BLKID_mcd1_0
47109. DBG_CLIENT_BLKID_mcd1_1
47110. DBG_CLIENT_BLKID_mcd2
47111. DBG_CLIENT_BLKID_mcd2_0
47112. DBG_CLIENT_BLKID_mcd2_1
47113. DBG_CLIENT_BLKID_mcd3
47114. DBG_CLIENT_BLKID_mcd3_0
47115. DBG_CLIENT_BLKID_mcd3_1
47116. DBG_CLIENT_BLKID_mcd4
47117. DBG_CLIENT_BLKID_mcd4_0
47118. DBG_CLIENT_BLKID_mcd4_1
47119. DBG_CLIENT_BLKID_mcd5
47120. DBG_CLIENT_BLKID_mcd5_0
47121. DBG_CLIENT_BLKID_mcd5_1
47122. DBG_CLIENT_BLKID_mcd6
47123. DBG_CLIENT_BLKID_mcd6_0
47124. DBG_CLIENT_BLKID_mcd6_1
47125. DBG_CLIENT_BLKID_mcd7
47126. DBG_CLIENT_BLKID_mcd7_0
47127. DBG_CLIENT_BLKID_mcd7_1
47128. DBG_CLIENT_BLKID_mcq0_0
47129. DBG_CLIENT_BLKID_mcq0_1
47130. DBG_CLIENT_BLKID_mcq1_0
47131. DBG_CLIENT_BLKID_mcq1_1
47132. DBG_CLIENT_BLKID_mcq2_0
47133. DBG_CLIENT_BLKID_mcq2_1
47134. DBG_CLIENT_BLKID_mcq3_0
47135. DBG_CLIENT_BLKID_mcq3_1
47136. DBG_CLIENT_BLKID_mcq4_0
47137. DBG_CLIENT_BLKID_mcq4_1
47138. DBG_CLIENT_BLKID_mcq5_0
47139. DBG_CLIENT_BLKID_mcq5_1
47140. DBG_CLIENT_BLKID_mcq6_0
47141. DBG_CLIENT_BLKID_mcq6_1
47142. DBG_CLIENT_BLKID_mcq7_0
47143. DBG_CLIENT_BLKID_mcq7_1
47144. DBG_CLIENT_BLKID_pa0
47145. DBG_CLIENT_BLKID_pa00
47146. DBG_CLIENT_BLKID_pa01
47147. DBG_CLIENT_BLKID_pa1
47148. DBG_CLIENT_BLKID_pa10
47149. DBG_CLIENT_BLKID_pa11
47150. DBG_CLIENT_BLKID_pc0
47151. DBG_CLIENT_BLKID_pc1
47152. DBG_CLIENT_BLKID_pc2
47153. DBG_CLIENT_BLKID_pc3
47154. DBG_CLIENT_BLKID_rlc
47155. DBG_CLIENT_BLKID_sam
47156. DBG_CLIENT_BLKID_sammsp
47157. DBG_CLIENT_BLKID_scb0
47158. DBG_CLIENT_BLKID_scb1
47159. DBG_CLIENT_BLKID_scb2
47160. DBG_CLIENT_BLKID_scb3
47161. DBG_CLIENT_BLKID_scf0
47162. DBG_CLIENT_BLKID_scf1
47163. DBG_CLIENT_BLKID_scf2
47164. DBG_CLIENT_BLKID_scf3
47165. DBG_CLIENT_BLKID_sdma
47166. DBG_CLIENT_BLKID_sdma_0
47167. DBG_CLIENT_BLKID_sdma_1
47168. DBG_CLIENT_BLKID_sem
47169. DBG_CLIENT_BLKID_smu_0
47170. DBG_CLIENT_BLKID_smu_1
47171. DBG_CLIENT_BLKID_smu_2
47172. DBG_CLIENT_BLKID_spim0
47173. DBG_CLIENT_BLKID_spim1
47174. DBG_CLIENT_BLKID_spim2
47175. DBG_CLIENT_BLKID_spim3
47176. DBG_CLIENT_BLKID_srbm
47177. DBG_CLIENT_BLKID_sx0
47178. DBG_CLIENT_BLKID_sx00
47179. DBG_CLIENT_BLKID_sx10
47180. DBG_CLIENT_BLKID_sx20
47181. DBG_CLIENT_BLKID_sx30
47182. DBG_CLIENT_BLKID_tmonw0
47183. DBG_CLIENT_BLKID_tmonw00
47184. DBG_CLIENT_BLKID_tmonw01
47185. DBG_CLIENT_BLKID_tmonw02
47186. DBG_CLIENT_BLKID_tmonw1
47187. DBG_CLIENT_BLKID_uvdb_0
47188. DBG_CLIENT_BLKID_uvdc_0
47189. DBG_CLIENT_BLKID_uvdc_1
47190. DBG_CLIENT_BLKID_uvde_0
47191. DBG_CLIENT_BLKID_uvdf_0
47192. DBG_CLIENT_BLKID_uvdf_1
47193. DBG_CLIENT_BLKID_uvdf_2
47194. DBG_CLIENT_BLKID_uvdf_3
47195. DBG_CLIENT_BLKID_uvdi_0
47196. DBG_CLIENT_BLKID_uvdm_0
47197. DBG_CLIENT_BLKID_uvdm_1
47198. DBG_CLIENT_BLKID_uvdm_2
47199. DBG_CLIENT_BLKID_uvdm_3
47200. DBG_CLIENT_BLKID_uvdt_0
47201. DBG_CLIENT_BLKID_uvdu_0
47202. DBG_CLIENT_BLKID_uvdu_1
47203. DBG_CLIENT_BLKID_uvdu_2
47204. DBG_CLIENT_BLKID_uvdu_3
47205. DBG_CLIENT_BLKID_uvdu_4
47206. DBG_CLIENT_BLKID_uvdu_5
47207. DBG_CLIENT_BLKID_uvdu_6
47208. DBG_CLIENT_BLKID_vcea0_0
47209. DBG_CLIENT_BLKID_vcea0_1
47210. DBG_CLIENT_BLKID_vcea0_2
47211. DBG_CLIENT_BLKID_vcea0_3
47212. DBG_CLIENT_BLKID_vcea1_0
47213. DBG_CLIENT_BLKID_vcea1_1
47214. DBG_CLIENT_BLKID_vcea1_2
47215. DBG_CLIENT_BLKID_vcea1_3
47216. DBG_CLIENT_BLKID_vcea_0
47217. DBG_CLIENT_BLKID_vcea_1
47218. DBG_CLIENT_BLKID_vcea_2
47219. DBG_CLIENT_BLKID_vcea_3
47220. DBG_CLIENT_BLKID_vcea_4
47221. DBG_CLIENT_BLKID_vcea_5
47222. DBG_CLIENT_BLKID_vcea_6
47223. DBG_CLIENT_BLKID_vceb0_0
47224. DBG_CLIENT_BLKID_vceb0_1
47225. DBG_CLIENT_BLKID_vceb1_0
47226. DBG_CLIENT_BLKID_vceb_0
47227. DBG_CLIENT_BLKID_vceb_1
47228. DBG_CLIENT_BLKID_vceb_2
47229. DBG_CLIENT_BLKID_vcec0_0
47230. DBG_CLIENT_BLKID_vcec1_0
47231. DBG_CLIENT_BLKID_vcec_0
47232. DBG_CLIENT_BLKID_vgt0
47233. DBG_CLIENT_BLKID_vgt1
47234. DBG_CLIENT_BLKID_vgt2
47235. DBG_CLIENT_BLKID_vgt3
47236. DBG_CLIENT_BLKID_vmc
47237. DBG_CLIENT_BLKID_wd
47238. DBG_CLIENT_BLKID_xdma
47239. DBG_CLIENT_BLKID_xdma_dbg_client_wrapper
47240. DBG_CLK_CTRL_CLKACT_TRC
47241. DBG_CLK_CTRL_CPU_1XCLKACT
47242. DBG_CLOSE
47243. DBG_CLOSE_CONN
47244. DBG_CMD
47245. DBG_CMD_NUM
47246. DBG_CNT
47247. DBG_COMMAND_EXCEPTION
47248. DBG_CONTINUE
47249. DBG_CONTROL_BREAK
47250. DBG_CONTROL_C
47251. DBG_CORE
47252. DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP
47253. DBG_COREDUMP_LIST_RESP_FLAGS_MORE
47254. DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE
47255. DBG_COUNTER
47256. DBG_DATA
47257. DBG_DBELL
47258. DBG_DEFAULTS
47259. DBG_DEINIT
47260. DBG_DEVS
47261. DBG_DEVSTART
47262. DBG_DFU
47263. DBG_DIS
47264. DBG_DMA
47265. DBG_DMAV
47266. DBG_DMESG
47267. DBG_DRAIN
47268. DBG_DUMP
47269. DBG_DUMP_FW_DOWNLOAD
47270. DBG_DUMP_FW_REQUEST_FRAME
47271. DBG_DUMP_MEM_ADDRESS_MASK
47272. DBG_DUMP_MEM_ADDRESS_SHIFT
47273. DBG_DUMP_MEM_LENGTH_MASK
47274. DBG_DUMP_MEM_LENGTH_SHIFT
47275. DBG_DUMP_MEM_MEM_GROUP_ID_MASK
47276. DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT
47277. DBG_DUMP_MEM_RESERVED_MASK
47278. DBG_DUMP_MEM_RESERVED_SHIFT
47279. DBG_DUMP_MEM_WIDE_BUS_MASK
47280. DBG_DUMP_MEM_WIDE_BUS_SHIFT
47281. DBG_DUMP_MSG
47282. DBG_DUMP_PUT_MSG_FRAME
47283. DBG_DUMP_REG_ADDRESS_MASK
47284. DBG_DUMP_REG_ADDRESS_SHIFT
47285. DBG_DUMP_REG_LENGTH_MASK
47286. DBG_DUMP_REG_LENGTH_SHIFT
47287. DBG_DUMP_REG_WIDE_BUS_MASK
47288. DBG_DUMP_REG_WIDE_BUS_SHIFT
47289. DBG_DUMP_REPLY_FRAME
47290. DBG_DUMP_REQUEST_FRAME
47291. DBG_DUMP_REQUEST_FRAME_HDR
47292. DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK
47293. DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT
47294. DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK
47295. DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT
47296. DBG_DUMP_TM_REPLY_FRAME
47297. DBG_DUMP_TM_REQUEST_FRAME
47298. DBG_EN
47299. DBG_ENABLE_DISABLE_AGC
47300. DBG_ERR
47301. DBG_ESR_EVT
47302. DBG_ESR_EVT_BKPT
47303. DBG_ESR_EVT_BRK
47304. DBG_ESR_EVT_HWBP
47305. DBG_ESR_EVT_HWSS
47306. DBG_ESR_EVT_HWWP
47307. DBG_ESR_EVT_VECC
47308. DBG_EVENT
47309. DBG_EVENT_ID
47310. DBG_EXCEPTION_HANDLED
47311. DBG_EXCEPTION_NOT_HANDLED
47312. DBG_EXCEPTION_PROLOG
47313. DBG_EXIT
47314. DBG_EXTENT
47315. DBG_FAULT
47316. DBG_FEATURE_FW_ASSERTS
47317. DBG_FEATURE_GRC
47318. DBG_FEATURE_IDLE_CHK
47319. DBG_FEATURE_IGU_FIFO
47320. DBG_FEATURE_MCP_TRACE
47321. DBG_FEATURE_NUM
47322. DBG_FEATURE_PROTECTION_OVERRIDE
47323. DBG_FEATURE_REG_FIFO
47324. DBG_FIFO
47325. DBG_FLOW
47326. DBG_FORCE_RELOC
47327. DBG_FUNC
47328. DBG_FW
47329. DBG_GADGET
47330. DBG_GENERAL
47331. DBG_GPIO_EN_A
47332. DBG_GRC_PARAM_CRASH
47333. DBG_GRC_PARAM_DUMP_BMB
47334. DBG_GRC_PARAM_DUMP_BRB
47335. DBG_GRC_PARAM_DUMP_BTB
47336. DBG_GRC_PARAM_DUMP_CAU
47337. DBG_GRC_PARAM_DUMP_CFC
47338. DBG_GRC_PARAM_DUMP_CM
47339. DBG_GRC_PARAM_DUMP_CM_CTX
47340. DBG_GRC_PARAM_DUMP_DIF
47341. DBG_GRC_PARAM_DUMP_DMAE
47342. DBG_GRC_PARAM_DUMP_IGU
47343. DBG_GRC_PARAM_DUMP_IOR
47344. DBG_GRC_PARAM_DUMP_MCP
47345. DBG_GRC_PARAM_DUMP_MSTORM
47346. DBG_GRC_PARAM_DUMP_MULD
47347. DBG_GRC_PARAM_DUMP_NIG
47348. DBG_GRC_PARAM_DUMP_PBUF
47349. DBG_GRC_PARAM_DUMP_PHY
47350. DBG_GRC_PARAM_DUMP_PRS
47351. DBG_GRC_PARAM_DUMP_PSTORM
47352. DBG_GRC_PARAM_DUMP_PXP
47353. DBG_GRC_PARAM_DUMP_QM
47354. DBG_GRC_PARAM_DUMP_RAM
47355. DBG_GRC_PARAM_DUMP_REGS
47356. DBG_GRC_PARAM_DUMP_RSS
47357. DBG_GRC_PARAM_DUMP_SDM
47358. DBG_GRC_PARAM_DUMP_STATIC
47359. DBG_GRC_PARAM_DUMP_TM
47360. DBG_GRC_PARAM_DUMP_TSTORM
47361. DBG_GRC_PARAM_DUMP_USTORM
47362. DBG_GRC_PARAM_DUMP_VFC
47363. DBG_GRC_PARAM_DUMP_XSTORM
47364. DBG_GRC_PARAM_DUMP_YSTORM
47365. DBG_GRC_PARAM_EXCLUDE_ALL
47366. DBG_GRC_PARAM_MCP_TRACE_META_SIZE
47367. DBG_GRC_PARAM_NO_FW_VER
47368. DBG_GRC_PARAM_NO_MCP
47369. DBG_GRC_PARAM_NUM_LCIDS
47370. DBG_GRC_PARAM_NUM_LTIDS
47371. DBG_GRC_PARAM_PARITY_SAFE
47372. DBG_GRC_PARAM_UNSTALL
47373. DBG_HEADER
47374. DBG_HEAVY
47375. DBG_HFC_CALL_TRACE
47376. DBG_HFC_FIFO_VERBOSE
47377. DBG_HFC_URB_ERROR
47378. DBG_HFC_URB_INFO
47379. DBG_HFC_USB_VERBOSE
47380. DBG_HISTORY_INPUT0
47381. DBG_HISTORY_INPUT1
47382. DBG_HISTORY_OUTPUT
47383. DBG_HMC_HYP
47384. DBG_HOOK_ERROR
47385. DBG_HOOK_HANDLED
47386. DBG_HW
47387. DBG_I2C
47388. DBG_IBW
47389. DBG_IDLE_CHK_COND_REG_ADDRESS_MASK
47390. DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT
47391. DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK
47392. DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT
47393. DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK
47394. DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT
47395. DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK
47396. DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT
47397. DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK
47398. DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT
47399. DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK
47400. DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT
47401. DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK
47402. DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT
47403. DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK
47404. DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT
47405. DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK
47406. DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT
47407. DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK
47408. DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT
47409. DBG_IMSG
47410. DBG_INFO
47411. DBG_INIT
47412. DBG_INODE
47413. DBG_INT
47414. DBG_INTERRUPT
47415. DBG_INTR
47416. DBG_IO
47417. DBG_IOCTL
47418. DBG_IRQ
47419. DBG_IRT
47420. DBG_ISOC
47421. DBG_KEY_BUF_LEN
47422. DBG_KG
47423. DBG_LEVEL
47424. DBG_LINK1_LFPS_GEN_PING
47425. DBG_LINK1_LFPS_GEN_PING_SET
47426. DBG_LINK1_LFPS_MIN_DET_U1_EXIT
47427. DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET
47428. DBG_LINK1_LFPS_MIN_GEN_U1_EXIT
47429. DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK
47430. DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET
47431. DBG_LINK1_RXDET_BREAK_DIS
47432. DBG_LINK1_RXDET_BREAK_DIS_SET
47433. DBG_LOAD
47434. DBG_LOOP
47435. DBG_LOTS
47436. DBG_LOUD
47437. DBG_LOW
47438. DBG_MAC80211
47439. DBG_MAC_STATE
47440. DBG_MAGIC
47441. DBG_MAINT
47442. DBG_MAP
47443. DBG_MASK
47444. DBG_MAX_REG_NUM
47445. DBG_MDSCR_KDE
47446. DBG_MDSCR_MASK
47447. DBG_MDSCR_MDE
47448. DBG_MDSCR_SS
47449. DBG_MEM
47450. DBG_MEM_ALL
47451. DBG_MGMT
47452. DBG_MGMT_TIMER
47453. DBG_MIB
47454. DBG_MMAP
47455. DBG_MODE_HDR_EVAL_MODE_MASK
47456. DBG_MODE_HDR_EVAL_MODE_SHIFT
47457. DBG_MODE_HDR_MODES_BUF_OFFSET_MASK
47458. DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT
47459. DBG_MONITOR_MODE
47460. DBG_MPORT
47461. DBG_MSG
47462. DBG_MSIGS
47463. DBG_MSTORM_ID
47464. DBG_NOISY
47465. DBG_NONE
47466. DBG_NORMAL
47467. DBG_NO_STATE_CHANGE
47468. DBG_OBW
47469. DBG_OMSG
47470. DBG_OPEN
47471. DBG_OPEN_CONN
47472. DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK
47473. DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT
47474. DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK
47475. DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT
47476. DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK
47477. DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT
47478. DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK
47479. DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT
47480. DBG_PARAM
47481. DBG_PARAMS
47482. DBG_PARSE
47483. DBG_PASS_EVENT
47484. DBG_PAT
47485. DBG_PCI
47486. DBG_PIO
47487. DBG_PM
47488. DBG_POOL
47489. DBG_PORT
47490. DBG_PORT_SWITCH
47491. DBG_PRINT
47492. DBG_PRINTEXCEPTION_C
47493. DBG_PROBE
47494. DBG_PROC
47495. DBG_PROC_ENTRY
47496. DBG_PROGRESS
47497. DBG_PSCAN
47498. DBG_PSTORM_ID
47499. DBG_QOS
47500. DBG_QUEUE
47501. DBG_RAW_CELL
47502. DBG_RDEV
47503. DBG_READ
47504. DBG_REG
47505. DBG_REGS
47506. DBG_REG_CALENDAR_OUT_DATA
47507. DBG_REG_CLIENT_ENABLE
47508. DBG_REG_DBG_BLOCK_ON
47509. DBG_REG_DBG_PRTY_MASK
47510. DBG_REG_DBG_PRTY_STS
47511. DBG_REG_DBG_PRTY_STS_CLR
47512. DBG_REG_DEBUG_TARGET
47513. DBG_REG_FRAMING_MODE
47514. DBG_REG_FULL_MODE
47515. DBG_REPLY_LATER
47516. DBG_REQ
47517. DBG_RES
47518. DBG_RESET
47519. DBG_RESET_REG_MISCS_PL_HV
47520. DBG_RESET_REG_MISCS_PL_HV_2
47521. DBG_RESET_REG_MISCS_PL_UA
47522. DBG_RESET_REG_MISC_PL_HV
47523. DBG_RESET_REG_MISC_PL_PDA_VAUX
47524. DBG_RESET_REG_MISC_PL_PDA_VMAIN_1
47525. DBG_RESET_REG_MISC_PL_PDA_VMAIN_2
47526. DBG_RESET_REG_MISC_PL_UA
47527. DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL
47528. DBG_RING_INFO_GET_REQ_RING_TYPE_LAST
47529. DBG_RING_INFO_GET_REQ_RING_TYPE_RX
47530. DBG_RING_INFO_GET_REQ_RING_TYPE_TX
47531. DBG_RIPEXCEPTION
47532. DBG_RST
47533. DBG_RUN
47534. DBG_RUN_SG
47535. DBG_RX
47536. DBG_RX_ATMEL_HDR
47537. DBG_RX_BEACON
47538. DBG_RX_CMD
47539. DBG_RX_CTRL
47540. DBG_RX_DATA
47541. DBG_RX_DATA_CONTENT
47542. DBG_RX_FRAGS
47543. DBG_RX_FRAGS_SKB
47544. DBG_RX_MGMT
47545. DBG_RX_MGMT_CONTENT
47546. DBG_SCHED_LIMIT
47547. DBG_SCRATCH
47548. DBG_SET_KSTACK
47549. DBG_SG
47550. DBG_SHOW_FLAG
47551. DBG_SHOW_FLAG_MASKED
47552. DBG_SKB
47553. DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK
47554. DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT
47555. DBG_SPSR_SS
47556. DBG_STACK_BASE
47557. DBG_STATUS_APP_VERSION_NOT_SET
47558. DBG_STATUS_BLOCK_ALREADY_ENABLED
47559. DBG_STATUS_BLOCK_IN_RESET
47560. DBG_STATUS_BLOCK_NOT_ENABLED
47561. DBG_STATUS_CANT_ADD_CONSTRAINT
47562. DBG_STATUS_DATA_DIDNT_TRIGGER
47563. DBG_STATUS_DBG_ARRAY_NOT_SET
47564. DBG_STATUS_DBG_BLOCK_NOT_RESET
47565. DBG_STATUS_DBG_BUS_IN_USE
47566. DBG_STATUS_DUMP_BUF_TOO_SMALL
47567. DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED
47568. DBG_STATUS_FILTER_ALREADY_ENABLED
47569. DBG_STATUS_FILTER_BUG
47570. DBG_STATUS_FW_ASSERTS_PARSE_FAILED
47571. DBG_STATUS_HW_ONLY_RECORDING
47572. DBG_STATUS_IDLE_CHK_PARSE_FAILED
47573. DBG_STATUS_IGU_FIFO_BAD_DATA
47574. DBG_STATUS_INPUT_OVERLAP
47575. DBG_STATUS_INVALID_ARGS
47576. DBG_STATUS_INVALID_NVRAM_BUNDLE
47577. DBG_STATUS_INVALID_PCI_BUF_SIZE
47578. DBG_STATUS_INVALID_TRACE_SIGNATURE
47579. DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET
47580. DBG_STATUS_MCP_COULD_NOT_HALT
47581. DBG_STATUS_MCP_COULD_NOT_MASK_PRTY
47582. DBG_STATUS_MCP_COULD_NOT_RESUME
47583. DBG_STATUS_MCP_TRACE_BAD_DATA
47584. DBG_STATUS_MCP_TRACE_NO_META
47585. DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE
47586. DBG_STATUS_NON_MATCHING_LINES
47587. DBG_STATUS_NO_DATA_RECORDED
47588. DBG_STATUS_NO_FILTER_TRIGGER_64B
47589. DBG_STATUS_NO_INPUT_ENABLED
47590. DBG_STATUS_NVRAM_GET_IMAGE_FAILED
47591. DBG_STATUS_NVRAM_READ_FAILED
47592. DBG_STATUS_OK
47593. DBG_STATUS_OUTPUT_ALREADY_SET
47594. DBG_STATUS_PCI_BUF_ALLOC_FAILED
47595. DBG_STATUS_PCI_BUF_NOT_ALLOCATED
47596. DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA
47597. DBG_STATUS_RECORDING_NOT_STARTED
47598. DBG_STATUS_REG_FIFO_BAD_DATA
47599. DBG_STATUS_RESERVED2
47600. DBG_STATUS_SEMI_FIFO_NOT_EMPTY
47601. DBG_STATUS_STORM_ALREADY_ENABLED
47602. DBG_STATUS_STORM_NOT_ENABLED
47603. DBG_STATUS_TOO_MANY_CONSTRAINTS
47604. DBG_STATUS_TOO_MANY_INPUTS
47605. DBG_STATUS_TOO_MANY_TRIGGER_STATES
47606. DBG_STATUS_TRIGGER_ALREADY_ENABLED
47607. DBG_STATUS_TRIGGER_NOT_ENABLED
47608. DBG_STATUS_UNKNOWN_CHIP
47609. DBG_STATUS_UNSUPPORTED_APP_VERSION
47610. DBG_STATUS_VIRT_MEM_ALLOC_FAILED
47611. DBG_SUBTYPE_SENSOR_READ
47612. DBG_SUPER
47613. DBG_SWITCH_CPU_EVENT
47614. DBG_SW_SEC_CNT
47615. DBG_TERMINATE_PROCESS
47616. DBG_TERMINATE_THREAD
47617. DBG_TINY
47618. DBG_TRACE
47619. DBG_TSTMP
47620. DBG_TSTORM_ID
47621. DBG_TX
47622. DBG_TX_DATA
47623. DBG_TX_DATA_CONTENT
47624. DBG_TX_EVENT
47625. DBG_TX_MGMT
47626. DBG_UDEV_INTEGER
47627. DBG_UINF_INTEGER
47628. DBG_UNABLE_TO_PROVIDE_HANDLE
47629. DBG_URB
47630. DBG_USER_REGS
47631. DBG_USE_TB
47632. DBG_USTORM_ID
47633. DBG_VCC
47634. DBG_VERBOSE
47635. DBG_VERY_NOISY
47636. DBG_WAIT
47637. DBG_WAIT_COMPLETE
47638. DBG_WARN
47639. DBG_WARNING
47640. DBG_WE_EVENTS
47641. DBG_WRITE
47642. DBG_XGENERAL
47643. DBG_XSTORM_ID
47644. DBG_YSTORM_ID
47645. DBG_printk
47646. DBIBCTRL
47647. DBI_BASE_ADDRESS
47648. DBI_BW_CTRL_REG
47649. DBI_CB_TIME_OUT
47650. DBI_CHANNEL_NUMBER_POS
47651. DBI_COMMAND_BUFFER_SIZE
47652. DBI_CS2
47653. DBI_CTRL
47654. DBI_DATA_BUFFER_SIZE
47655. DBI_DATA_WIDTH_16BIT
47656. DBI_DATA_WIDTH_8BIT
47657. DBI_DATA_WIDTH_9BIT
47658. DBI_DATA_WIDTH_OPT1
47659. DBI_DATA_WIDTH_OPT2
47660. DBI_DATA_WIDTH_POS
47661. DBI_FIFO_EMPTY
47662. DBI_FIFO_EMPTY_7_LOCATIONS
47663. DBI_FIFO_EMPTY_HALF
47664. DBI_FIFO_EMPTY_QUARTER
47665. DBI_HS_LP_MODE_MASK
47666. DBI_HS_MODE
47667. DBI_LP_MODE
47668. DBI_NOT_SUPPORTED
47669. DBI_RDATA
47670. DBI_RESOLUTION_REG
47671. DBI_RO_WR_EN
47672. DBI_TO_MBI
47673. DBI_TYPEC_ENABLE
47674. DBI_TYPEC_FREQ_MASK
47675. DBI_TYPEC_FREQ_SHIFT
47676. DBI_TYPEC_OPTION_MASK
47677. DBI_TYPEC_OPTION_SHIFT
47678. DBI_TYPEC_OVERRIDE
47679. DBI_TYPEC_OVERRIDE_COUNTER_MASK
47680. DBI_TYPEC_OVERRIDE_COUNTER_SHIFT
47681. DBI_TYPEC_WIP
47682. DBI_WDATA
47683. DBL
47684. DBLB
47685. DBLEN
47686. DBLEXT_THRESHOLD
47687. DBLK_CTRL
47688. DBLK_STATUS
47689. DBLSEL
47690. DBLT_MODE
47691. DBLV_BYPASS
47692. DBLV_X4
47693. DBLV_X6
47694. DBLV_X8
47695. DBL_BIAS
47696. DBL_BITLENGTH
47697. DBL_EMAX
47698. DBL_EMIN
47699. DBL_EXP_LENGTH
47700. DBL_FX_MAX_EXP
47701. DBL_INFINITY_EXPONENT
47702. DBL_P
47703. DBL_THRESHOLD
47704. DBL_WRAP
47705. DBMSG
47706. DBM_TO_MBM
47707. DBOFF_MASK
47708. DBPRIO_F
47709. DBPRIO_S
47710. DBPRIO_V
47711. DBREAKC_LOAD_BIT
47712. DBREAKC_LOAD_MASK
47713. DBREAKC_MASK_BIT
47714. DBREAKC_MASK_MASK
47715. DBREAKC_STOR_BIT
47716. DBREAKC_STOR_MASK
47717. DBRI_CMD
47718. DBRI_DEBUG
47719. DBRI_INT_BLK
47720. DBRI_MAX_GAIN
47721. DBRI_MAX_PIPE
47722. DBRI_MAX_VOLUME
47723. DBRI_NO_CMDS
47724. DBRI_NO_DESCS
47725. DBRI_NO_PIPES
47726. DBRI_NO_STREAMS
47727. DBRI_PLAY
47728. DBRI_RD_ABT
47729. DBRI_RD_B
47730. DBRI_RD_BBC
47731. DBRI_RD_BCNT
47732. DBRI_RD_C
47733. DBRI_RD_CNT
47734. DBRI_RD_CRC
47735. DBRI_RD_F
47736. DBRI_RD_M
47737. DBRI_RD_OVRN
47738. DBRI_RD_STATUS
47739. DBRI_REC
47740. DBRI_STREAM
47741. DBRI_STREAMNO
47742. DBRI_TD_ABT
47743. DBRI_TD_B
47744. DBRI_TD_CNT
47745. DBRI_TD_D
47746. DBRI_TD_F
47747. DBRI_TD_FCNT
47748. DBRI_TD_I
47749. DBRI_TD_M
47750. DBRI_TD_MAXCNT
47751. DBRI_TD_STATUS
47752. DBRI_TD_TBC
47753. DBRI_TD_UNR
47754. DBR_BLOCK_SIZE
47755. DBR_INDEX_MASK
47756. DBR_MAP_SIZE
47757. DBR_OFFSET
47758. DBR_PATH_L2
47759. DBR_SIZE
47760. DBR_TYPE_CQ
47761. DBR_TYPE_CQ_ARMALL
47762. DBR_TYPE_CQ_ARMENA
47763. DBR_TYPE_CQ_ARMSE
47764. DBR_TYPE_CQ_CUTOFF_ACK
47765. DBR_TYPE_NQ
47766. DBR_TYPE_NQ_ARM
47767. DBR_TYPE_NULL
47768. DBR_TYPE_RQ
47769. DBR_TYPE_SQ
47770. DBR_TYPE_SRQ
47771. DBR_TYPE_SRQ_ARM
47772. DBR_TYPE_SRQ_ARMENA
47773. DBR_XID_MASK
47774. DBR_XID_SFT
47775. DBS
47776. DBSR_BT
47777. DBSR_CIRPT
47778. DBSR_CRET
47779. DBSR_DAC1R
47780. DBSR_DAC1W
47781. DBSR_DAC2R
47782. DBSR_DAC2W
47783. DBSR_IAC1
47784. DBSR_IAC12ATS
47785. DBSR_IAC2
47786. DBSR_IAC3
47787. DBSR_IAC34ATS
47788. DBSR_IAC4
47789. DBSR_IC
47790. DBSR_IDE
47791. DBSR_IRPT
47792. DBSR_MRR
47793. DBSR_RET
47794. DBSR_TIE
47795. DBSTEP
47796. DBSY_DRV
47797. DBSY_OTHER
47798. DBSY_OWN
47799. DBS_DFS_WIDTH_OFFSET
47800. DBTOCR_CNT
47801. DBTOCR_EN
47802. DBTP_DBRP_MASK
47803. DBTP_DBRP_SHIFT
47804. DBTP_DSJW_MASK
47805. DBTP_DSJW_SHIFT
47806. DBTP_DTSEG1_MASK
47807. DBTP_DTSEG1_SHIFT
47808. DBTP_DTSEG2_MASK
47809. DBTP_DTSEG2_SHIFT
47810. DBTP_TDC
47811. DBTYPE_F
47812. DBTYPE_S
47813. DBTYPE_V
47814. DBUFCTRL
47815. DBUF_CTL
47816. DBUF_CTL_S1
47817. DBUF_CTL_S2
47818. DBUF_POWER_REQUEST
47819. DBUF_POWER_STATE
47820. DBUG_ON
47821. DBUSY_TIMER_VALUE
47822. DBVFIFO_SIZE_G
47823. DBVFIFO_SIZE_M
47824. DBVFIFO_SIZE_S
47825. DBWORD
47826. DBX1_CTL1
47827. DBX1_CTL2
47828. DBX1_RMS_SE
47829. DBX2_CTL1
47830. DBX2_CTL2
47831. DBX2_RMS_SE
47832. DBX500_REGULATOR_H
47833. DBX540_PRCMU_FW_VERSION_OFFSET
47834. DBXMASK
47835. DBX_ADJ
47836. DB_ADDR_SHIFT
47837. DB_AGG_CMD_ADD
47838. DB_AGG_CMD_MAX
47839. DB_AGG_CMD_NOP
47840. DB_AGG_CMD_SET
47841. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK
47842. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT
47843. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK
47844. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT
47845. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK
47846. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT
47847. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK
47848. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT
47849. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK
47850. DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT
47851. DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK
47852. DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT
47853. DB_BANK_HEIGHT
47854. DB_BANK_WIDTH
47855. DB_BREAK_BATCH_EVENT
47856. DB_BUSY
47857. DB_BYTE_DISPLAY
47858. DB_CACHE_FLUSH
47859. DB_CACHE_FLUSH_AND_INV
47860. DB_CACHE_FLUSH_AND_INV_EVENT
47861. DB_CACHE_FLUSH_AND_INV_TS_EVENT
47862. DB_CACHE_FLUSH_TS
47863. DB_CFM
47864. DB_CFMN
47865. DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK
47866. DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT
47867. DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK
47868. DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT
47869. DB_CGTT_CLK_CTRL_0__RESERVED_MASK
47870. DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT
47871. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK
47872. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT
47873. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK
47874. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT
47875. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK
47876. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT
47877. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK
47878. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT
47879. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK
47880. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT
47881. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK
47882. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT
47883. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK
47884. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT
47885. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK
47886. DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT
47887. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK
47888. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT
47889. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK
47890. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT
47891. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK
47892. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT
47893. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK
47894. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT
47895. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK
47896. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT
47897. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK
47898. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT
47899. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK
47900. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT
47901. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK
47902. DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT
47903. DB_CLEAN
47904. DB_CLK_OFF_DELAY
47905. DB_CLK_SOFT_RESET
47906. DB_CLK_SOFT_RESET_0
47907. DB_CLK_SOFT_RESET_1
47908. DB_CNTRL_OFF
47909. DB_CNTRl_MASK
47910. DB_CONTEXT_DONE_EVENT
47911. DB_CONTEXT_SUSPEND_EVENT
47912. DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK
47913. DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT
47914. DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK
47915. DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT
47916. DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK
47917. DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT
47918. DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK
47919. DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT
47920. DB_COUNT_CONTROL__SAMPLE_RATE_MASK
47921. DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT
47922. DB_COUNT_CONTROL__SFAIL_ENABLE_MASK
47923. DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT
47924. DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK
47925. DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT
47926. DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK
47927. DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT
47928. DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK
47929. DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT
47930. DB_COUNT_CONTROL__ZPASS_ENABLE_MASK
47931. DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT
47932. DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK
47933. DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT
47934. DB_CP_FLAGS
47935. DB_CP_IRQ_DIS_FLAGS
47936. DB_CP_REARM_FLAGS
47937. DB_CQ_HIGH_FEILD_SHIFT
47938. DB_CQ_HIGH_SET_SHIFT
47939. DB_CQ_NUM_POPPED_SHIFT
47940. DB_CQ_OFFSET
47941. DB_CQ_REARM_SHIFT
47942. DB_CQ_RING_ID_EXT_MASK
47943. DB_CQ_RING_ID_EXT_MASK_SHIFT
47944. DB_CQ_RING_ID_HIGH_MASK
47945. DB_CQ_RING_ID_LOW_MASK
47946. DB_CQ_RING_ID_MASK
47947. DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK
47948. DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT
47949. DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK
47950. DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT
47951. DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK
47952. DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT
47953. DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK
47954. DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT
47955. DB_DEBUG
47956. DB_DEBUG2
47957. DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK
47958. DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT
47959. DB_DEBUG2__CLK_OFF_DELAY_MASK
47960. DB_DEBUG2__CLK_OFF_DELAY__SHIFT
47961. DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK
47962. DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT
47963. DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK
47964. DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT
47965. DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK
47966. DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT
47967. DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK
47968. DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT
47969. DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK
47970. DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK
47971. DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT
47972. DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT
47973. DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK
47974. DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK
47975. DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT
47976. DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT
47977. DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK
47978. DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT
47979. DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK
47980. DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT
47981. DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK
47982. DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT
47983. DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK
47984. DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT
47985. DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK
47986. DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT
47987. DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK
47988. DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT
47989. DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK
47990. DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT
47991. DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK
47992. DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT
47993. DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK
47994. DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT
47995. DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK
47996. DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT
47997. DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK
47998. DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT
47999. DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK
48000. DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT
48001. DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK
48002. DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT
48003. DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK
48004. DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT
48005. DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK
48006. DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT
48007. DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK
48008. DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT
48009. DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK
48010. DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT
48011. DB_DEBUG2__FORCE_ITERATE_256_MASK
48012. DB_DEBUG2__FORCE_ITERATE_256__SHIFT
48013. DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK
48014. DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT
48015. DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK
48016. DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT
48017. DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK
48018. DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT
48019. DB_DEBUG2__RESERVED_MASK
48020. DB_DEBUG2__RESERVED__SHIFT
48021. DB_DEBUG3
48022. DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK
48023. DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT
48024. DB_DEBUG3__DB_EXTRA_DEBUG3_MASK
48025. DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT
48026. DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK
48027. DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT
48028. DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK
48029. DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT
48030. DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK
48031. DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT
48032. DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK
48033. DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT
48034. DB_DEBUG3__DISABLE_DI_DT_STALL_MASK
48035. DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT
48036. DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK
48037. DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT
48038. DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK
48039. DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT
48040. DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK
48041. DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT
48042. DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK
48043. DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT
48044. DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK
48045. DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT
48046. DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK
48047. DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT
48048. DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK
48049. DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT
48050. DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK
48051. DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT
48052. DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK
48053. DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT
48054. DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK
48055. DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT
48056. DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK
48057. DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT
48058. DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK
48059. DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT
48060. DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK
48061. DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT
48062. DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK
48063. DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT
48064. DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK
48065. DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT
48066. DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK
48067. DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT
48068. DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK
48069. DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT
48070. DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK
48071. DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT
48072. DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK
48073. DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT
48074. DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK
48075. DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT
48076. DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK
48077. DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT
48078. DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK
48079. DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT
48080. DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK
48081. DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT
48082. DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK
48083. DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT
48084. DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK
48085. DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT
48086. DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK
48087. DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT
48088. DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK
48089. DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT
48090. DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK
48091. DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT
48092. DB_DEBUG3__FORCE_DB_IS_GOOD_MASK
48093. DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT
48094. DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK
48095. DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT
48096. DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK
48097. DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT
48098. DB_DEBUG4
48099. DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK
48100. DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT
48101. DB_DEBUG4__DB_EXTRA_DEBUG4_MASK
48102. DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT
48103. DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK
48104. DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT
48105. DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK
48106. DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT
48107. DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK
48108. DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT
48109. DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK
48110. DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT
48111. DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK
48112. DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT
48113. DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK
48114. DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT
48115. DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK
48116. DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT
48117. DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK
48118. DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT
48119. DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK
48120. DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT
48121. DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK
48122. DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT
48123. DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK
48124. DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT
48125. DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK
48126. DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT
48127. DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK
48128. DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT
48129. DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK
48130. DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT
48131. DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK
48132. DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT
48133. DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK
48134. DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT
48135. DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK
48136. DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT
48137. DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK
48138. DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT
48139. DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK
48140. DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT
48141. DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK
48142. DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT
48143. DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK
48144. DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT
48145. DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK
48146. DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT
48147. DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK
48148. DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT
48149. DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK
48150. DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT
48151. DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK
48152. DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT
48153. DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK
48154. DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT
48155. DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK
48156. DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT
48157. DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK
48158. DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT
48159. DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK
48160. DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT
48161. DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK
48162. DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT
48163. DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK
48164. DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT
48165. DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK
48166. DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT
48167. DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK
48168. DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT
48169. DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK
48170. DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT
48171. DB_DEBUG4__WR_MEM_BURST_CTL_MASK
48172. DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT
48173. DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK
48174. DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT
48175. DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK
48176. DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT
48177. DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK
48178. DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT
48179. DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK
48180. DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT
48181. DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK
48182. DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT
48183. DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK
48184. DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT
48185. DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK
48186. DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT
48187. DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK
48188. DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT
48189. DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK
48190. DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT
48191. DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK
48192. DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT
48193. DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK
48194. DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT
48195. DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK
48196. DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT
48197. DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK
48198. DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT
48199. DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK
48200. DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT
48201. DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK
48202. DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT
48203. DB_DEBUG__DISABLE_SUMM_SQUADS_MASK
48204. DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT
48205. DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK
48206. DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT
48207. DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK
48208. DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT
48209. DB_DEBUG__FETCH_FULL_Z_TILE_MASK
48210. DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT
48211. DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK
48212. DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT
48213. DB_DEBUG__FORCE_Z_MODE_MASK
48214. DB_DEBUG__FORCE_Z_MODE__SHIFT
48215. DB_DEBUG__NEVER_FREE_Z_ONLY_MASK
48216. DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT
48217. DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK
48218. DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT
48219. DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK
48220. DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT
48221. DB_DEFAULT_PKG_ELEMENTS
48222. DB_DEF_PDU_CQPROC_MASK
48223. DB_DEF_PDU_CQPROC_SHIFT
48224. DB_DEF_PDU_EVENT_SHIFT
48225. DB_DEF_PDU_NUM_POSTED_SHIFT
48226. DB_DEF_PDU_REARM_SHIFT
48227. DB_DEF_PDU_RING_ID_MASK
48228. DB_DEF_PDU_WRB_INDEX_MASK
48229. DB_DEF_PDU_WRB_INDEX_SHIFT
48230. DB_DEPTH_BASE
48231. DB_DEPTH_BOUNDS_MAX__MAX_MASK
48232. DB_DEPTH_BOUNDS_MAX__MAX__SHIFT
48233. DB_DEPTH_BOUNDS_MIN__MIN_MASK
48234. DB_DEPTH_BOUNDS_MIN__MIN__SHIFT
48235. DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK
48236. DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT
48237. DB_DEPTH_CONTROL
48238. DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK
48239. DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT
48240. DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK
48241. DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT
48242. DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK
48243. DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT
48244. DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK
48245. DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT
48246. DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK
48247. DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT
48248. DB_DEPTH_CONTROL__STENCILFUNC_MASK
48249. DB_DEPTH_CONTROL__STENCILFUNC__SHIFT
48250. DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK
48251. DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT
48252. DB_DEPTH_CONTROL__ZFUNC_MASK
48253. DB_DEPTH_CONTROL__ZFUNC__SHIFT
48254. DB_DEPTH_CONTROL__Z_ENABLE_MASK
48255. DB_DEPTH_CONTROL__Z_ENABLE__SHIFT
48256. DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK
48257. DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT
48258. DB_DEPTH_INFO
48259. DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK
48260. DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT
48261. DB_DEPTH_INFO__ARRAY_MODE_MASK
48262. DB_DEPTH_INFO__ARRAY_MODE__SHIFT
48263. DB_DEPTH_INFO__BANK_HEIGHT_MASK
48264. DB_DEPTH_INFO__BANK_HEIGHT__SHIFT
48265. DB_DEPTH_INFO__BANK_WIDTH_MASK
48266. DB_DEPTH_INFO__BANK_WIDTH__SHIFT
48267. DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK
48268. DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT
48269. DB_DEPTH_INFO__NUM_BANKS_MASK
48270. DB_DEPTH_INFO__NUM_BANKS__SHIFT
48271. DB_DEPTH_INFO__PIPE_CONFIG_MASK
48272. DB_DEPTH_INFO__PIPE_CONFIG__SHIFT
48273. DB_DEPTH_SIZE
48274. DB_DEPTH_SIZE_XY__X_MAX_MASK
48275. DB_DEPTH_SIZE_XY__X_MAX__SHIFT
48276. DB_DEPTH_SIZE_XY__Y_MAX_MASK
48277. DB_DEPTH_SIZE_XY__Y_MAX__SHIFT
48278. DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK
48279. DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT
48280. DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK
48281. DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT
48282. DB_DEPTH_SIZE__X_MAX_MASK
48283. DB_DEPTH_SIZE__X_MAX__SHIFT
48284. DB_DEPTH_SIZE__Y_MAX_MASK
48285. DB_DEPTH_SIZE__Y_MAX__SHIFT
48286. DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK
48287. DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT
48288. DB_DEPTH_VIEW
48289. DB_DEPTH_VIEW__MIPID_MASK
48290. DB_DEPTH_VIEW__MIPID__SHIFT
48291. DB_DEPTH_VIEW__SLICE_MAX_HI_MASK
48292. DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT
48293. DB_DEPTH_VIEW__SLICE_MAX_MASK
48294. DB_DEPTH_VIEW__SLICE_MAX__SHIFT
48295. DB_DEPTH_VIEW__SLICE_START_HI_MASK
48296. DB_DEPTH_VIEW__SLICE_START_HI__SHIFT
48297. DB_DEPTH_VIEW__SLICE_START_MASK
48298. DB_DEPTH_VIEW__SLICE_START__SHIFT
48299. DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK
48300. DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT
48301. DB_DEPTH_VIEW__Z_READ_ONLY_MASK
48302. DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT
48303. DB_DEST_TCM
48304. DB_DEST_UCM
48305. DB_DEST_XCM
48306. DB_DFSM_CONFIG__BYPASS_DFSM_MASK
48307. DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT
48308. DB_DFSM_CONFIG__CAM_WATERMARK_MASK
48309. DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT
48310. DB_DFSM_CONFIG__DISABLE_POPS_MASK
48311. DB_DFSM_CONFIG__DISABLE_POPS__SHIFT
48312. DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK
48313. DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT
48314. DB_DFSM_CONFIG__FORCE_FLUSH_MASK
48315. DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT
48316. DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK
48317. DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT
48318. DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK
48319. DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT
48320. DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK
48321. DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT
48322. DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK
48323. DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT
48324. DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK
48325. DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT
48326. DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK
48327. DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT
48328. DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK
48329. DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT
48330. DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK
48331. DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT
48332. DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK
48333. DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT
48334. DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK
48335. DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT
48336. DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK
48337. DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT
48338. DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK
48339. DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT
48340. DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK
48341. DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT
48342. DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK
48343. DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT
48344. DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK
48345. DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT
48346. DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK
48347. DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT
48348. DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK
48349. DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT
48350. DB_DFSM_WATCHDOG__TIMER_TARGET_MASK
48351. DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT
48352. DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK
48353. DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT
48354. DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK
48355. DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT
48356. DB_DWORD_DISPLAY
48357. DB_ECC_ERROR
48358. DB_ECM
48359. DB_ECMN
48360. DB_EDC_MASK
48361. DB_EDC_SHIFT
48362. DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK
48363. DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT
48364. DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK
48365. DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT
48366. DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK
48367. DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT
48368. DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK
48369. DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT
48370. DB_EQAA__INCOHERENT_EQAA_READS_MASK
48371. DB_EQAA__INCOHERENT_EQAA_READS__SHIFT
48372. DB_EQAA__INTERPOLATE_COMP_Z_MASK
48373. DB_EQAA__INTERPOLATE_COMP_Z__SHIFT
48374. DB_EQAA__INTERPOLATE_SRC_Z_MASK
48375. DB_EQAA__INTERPOLATE_SRC_Z__SHIFT
48376. DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK
48377. DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT
48378. DB_EQAA__MAX_ANCHOR_SAMPLES_MASK
48379. DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT
48380. DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK
48381. DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT
48382. DB_EQAA__PS_ITER_SAMPLES_MASK
48383. DB_EQAA__PS_ITER_SAMPLES__SHIFT
48384. DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK
48385. DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT
48386. DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK
48387. DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT
48388. DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK
48389. DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT
48390. DB_EQ_CLR_SHIFT
48391. DB_EQ_EVNT_SHIFT
48392. DB_EQ_HIGH_FEILD_SHIFT
48393. DB_EQ_HIGH_SET_SHIFT
48394. DB_EQ_NUM_POPPED_SHIFT
48395. DB_EQ_OFFSET
48396. DB_EQ_R2I_DLY_SHIFT
48397. DB_EQ_REARM_SHIFT
48398. DB_EQ_RING_ID_EXT_MASK
48399. DB_EQ_RING_ID_EXT_MASK_SHIFT
48400. DB_EQ_RING_ID_HIGH_MASK
48401. DB_EQ_RING_ID_LOW_MASK
48402. DB_EQ_RING_ID_MASK
48403. DB_ESS
48404. DB_ESSN
48405. DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK
48406. DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT
48407. DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK
48408. DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT
48409. DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK
48410. DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT
48411. DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK
48412. DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT
48413. DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK
48414. DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT
48415. DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK
48416. DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT
48417. DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A_MASK
48418. DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A__SHIFT
48419. DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B_MASK
48420. DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B__SHIFT
48421. DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK
48422. DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT
48423. DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK
48424. DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT
48425. DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK
48426. DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT
48427. DB_EXECUTE
48428. DB_Enable_MASK
48429. DB_Enable_SHIFT
48430. DB_FC_DRAIN_THRESH
48431. DB_FC_RESUME_DELAY
48432. DB_FC_RESUME_SIZE
48433. DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK
48434. DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT
48435. DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK
48436. DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT
48437. DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK
48438. DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT
48439. DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK
48440. DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT
48441. DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK
48442. DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT
48443. DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK
48444. DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT
48445. DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK
48446. DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT
48447. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK
48448. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT
48449. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK
48450. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT
48451. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK
48452. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT
48453. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK
48454. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT
48455. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK
48456. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT
48457. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK
48458. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT
48459. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK
48460. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT
48461. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK
48462. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT
48463. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK
48464. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT
48465. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK
48466. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT
48467. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK
48468. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT
48469. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK
48470. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT
48471. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK
48472. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT
48473. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK
48474. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT
48475. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK
48476. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT
48477. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK
48478. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT
48479. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK
48480. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT
48481. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK
48482. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT
48483. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK
48484. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT
48485. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK
48486. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT
48487. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK
48488. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT
48489. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK
48490. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT
48491. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK
48492. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT
48493. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK
48494. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT
48495. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK
48496. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT
48497. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK
48498. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT
48499. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK
48500. DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT
48501. DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK
48502. DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT
48503. DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK
48504. DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT
48505. DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK
48506. DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT
48507. DB_FIFO_DEPTH1__MCC_DEPTH_MASK
48508. DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT
48509. DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK
48510. DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT
48511. DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK
48512. DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT
48513. DB_FIFO_DEPTH1__QC_DEPTH_MASK
48514. DB_FIFO_DEPTH1__QC_DEPTH__SHIFT
48515. DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK
48516. DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT
48517. DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK
48518. DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT
48519. DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK
48520. DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT
48521. DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK
48522. DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT
48523. DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK
48524. DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT
48525. DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK
48526. DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT
48527. DB_FLUSH_AND_INV_DB_DATA_TS
48528. DB_FLUSH_AND_INV_DB_META
48529. DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK
48530. DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT
48531. DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK
48532. DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT
48533. DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK
48534. DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT
48535. DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK
48536. DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT
48537. DB_FREE_CACHELINES__QUAD_READ_REQS_MASK
48538. DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT
48539. DB_GEN
48540. DB_HTILE_DATA_BASE
48541. DB_HTILE_DATA_BASE_HI__BASE_HI_MASK
48542. DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT
48543. DB_HTILE_DATA_BASE__BASE_256B_MASK
48544. DB_HTILE_DATA_BASE__BASE_256B__SHIFT
48545. DB_HTILE_SURFACE
48546. DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK
48547. DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT
48548. DB_HTILE_SURFACE__FULL_CACHE_MASK
48549. DB_HTILE_SURFACE__FULL_CACHE__SHIFT
48550. DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK
48551. DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT
48552. DB_HTILE_SURFACE__LINEAR_MASK
48553. DB_HTILE_SURFACE__LINEAR__SHIFT
48554. DB_HTILE_SURFACE__PIPE_ALIGNED_MASK
48555. DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT
48556. DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK
48557. DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT
48558. DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK
48559. DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT
48560. DB_HTILE_SURFACE__PRELOAD_MASK
48561. DB_HTILE_SURFACE__PRELOAD__SHIFT
48562. DB_HTILE_SURFACE__RB_ALIGNED_MASK
48563. DB_HTILE_SURFACE__RB_ALIGNED__SHIFT
48564. DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK
48565. DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT
48566. DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK
48567. DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT
48568. DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK
48569. DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT
48570. DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK
48571. DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT
48572. DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK
48573. DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT
48574. DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK
48575. DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT
48576. DB_HTILE_SURFACE__TC_COMPATIBLE_MASK
48577. DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT
48578. DB_HWM_GEN
48579. DB_HWM_RX
48580. DB_HWM_TX
48581. DB_IDX
48582. DB_IDX_MASK
48583. DB_IDX_VALID
48584. DB_INTR
48585. DB_IRQ
48586. DB_IRQ_DIS
48587. DB_IRQ_FLAGS
48588. DB_IR_MASK
48589. DB_IR_SHIFT
48590. DB_KEY_CP
48591. DB_KEY_RX
48592. DB_KEY_ST
48593. DB_KEY_TX
48594. DB_KEY_TX_PUSH
48595. DB_L2_DPM_DATA_DPM_TYPE_MASK
48596. DB_L2_DPM_DATA_DPM_TYPE_SHIFT
48597. DB_L2_DPM_DATA_GFS_SRC_EN_MASK
48598. DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT
48599. DB_L2_DPM_DATA_NUM_BDS_MASK
48600. DB_L2_DPM_DATA_NUM_BDS_SHIFT
48601. DB_L2_DPM_DATA_PKT_SIZE_MASK
48602. DB_L2_DPM_DATA_PKT_SIZE_SHIFT
48603. DB_L2_DPM_DATA_RESERVED0_MASK
48604. DB_L2_DPM_DATA_RESERVED0_SHIFT
48605. DB_L2_DPM_DATA_SGE_NUM_MASK
48606. DB_L2_DPM_DATA_SGE_NUM_SHIFT
48607. DB_L2_DPM_DATA_SIZE_MASK
48608. DB_L2_DPM_DATA_SIZE_SHIFT
48609. DB_L2_DPM_SGE_RESERVED0_MASK
48610. DB_L2_DPM_SGE_RESERVED0_SHIFT
48611. DB_L2_DPM_SGE_RESERVED1_MASK
48612. DB_L2_DPM_SGE_RESERVED1_SHIFT
48613. DB_L2_DPM_SGE_ST_VALID_MASK
48614. DB_L2_DPM_SGE_ST_VALID_SHIFT
48615. DB_L2_DPM_SGE_TPH_ST_INDEX_MASK
48616. DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT
48617. DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK
48618. DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT
48619. DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK
48620. DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT
48621. DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK
48622. DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT
48623. DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK
48624. DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT
48625. DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK
48626. DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT
48627. DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK
48628. DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT
48629. DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK
48630. DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT
48631. DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK
48632. DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT
48633. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN_MASK
48634. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN__SHIFT
48635. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK
48636. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT
48637. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK
48638. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT
48639. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK
48640. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT
48641. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK
48642. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT
48643. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK
48644. DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT
48645. DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK
48646. DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT
48647. DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK
48648. DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT
48649. DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK
48650. DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT
48651. DB_LEGACY_ADDR_DEMS_MASK
48652. DB_LEGACY_ADDR_DEMS_SHIFT
48653. DB_LEGACY_ADDR_ICID_MASK
48654. DB_LEGACY_ADDR_ICID_SHIFT
48655. DB_LEGACY_ADDR_RESERVED0_MASK
48656. DB_LEGACY_ADDR_RESERVED0_SHIFT
48657. DB_LONG_TX_PUSH
48658. DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK
48659. DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT
48660. DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK
48661. DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT
48662. DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK
48663. DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT
48664. DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK
48665. DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT
48666. DB_MAC
48667. DB_MACRO_TILE_ASPECT
48668. DB_MASK
48669. DB_MAX_PTRS
48670. DB_MCCQ_NUM_POSTED_SHIFT
48671. DB_MCCQ_OFFSET
48672. DB_MCCQ_RING_ID_MASK
48673. DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK
48674. DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT
48675. DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK
48676. DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT
48677. DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK
48678. DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT
48679. DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK
48680. DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT
48681. DB_NORMALIZE
48682. DB_NUM_BANKS
48683. DB_NUM_DESTINATIONS
48684. DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK
48685. DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT
48686. DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK
48687. DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT
48688. DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK
48689. DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT
48690. DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK
48691. DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT
48692. DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK
48693. DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT
48694. DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK
48695. DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT
48696. DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK
48697. DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT
48698. DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK
48699. DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT
48700. DB_OFFSET
48701. DB_OPTIONS_PAR_ERROR_F
48702. DB_OPTIONS_PAR_ERROR_S
48703. DB_OPTIONS_PAR_ERROR_V
48704. DB_OUT
48705. DB_P
48706. DB_PAGE_SIZE
48707. DB_PCC_MASK
48708. DB_PCC_SHIFT
48709. DB_PCM
48710. DB_PCMN
48711. DB_PEFF_SEL_prezl_tile_mem_stall
48712. DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
48713. DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
48714. DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
48715. DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
48716. DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
48717. DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
48718. DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
48719. DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
48720. DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
48721. DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
48722. DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
48723. DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
48724. DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
48725. DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
48726. DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
48727. DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
48728. DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK
48729. DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
48730. DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
48731. DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
48732. DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK
48733. DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
48734. DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
48735. DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
48736. DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
48737. DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
48738. DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
48739. DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
48740. DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
48741. DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
48742. DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
48743. DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
48744. DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
48745. DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
48746. DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
48747. DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
48748. DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
48749. DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
48750. DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK
48751. DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
48752. DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
48753. DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
48754. DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK
48755. DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
48756. DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
48757. DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
48758. DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
48759. DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
48760. DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
48761. DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
48762. DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
48763. DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
48764. DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK
48765. DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
48766. DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
48767. DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
48768. DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK
48769. DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
48770. DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
48771. DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
48772. DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
48773. DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
48774. DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
48775. DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
48776. DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK
48777. DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT
48778. DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK
48779. DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
48780. DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK
48781. DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT
48782. DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK
48783. DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
48784. DB_PERF_SEL_CB_DB_rdreq_prt_sends
48785. DB_PERF_SEL_CB_DB_rdreq_sends
48786. DB_PERF_SEL_CB_DB_wrreq_prt_sends
48787. DB_PERF_SEL_CB_DB_wrreq_sends
48788. DB_PERF_SEL_DB_CB_context_dones
48789. DB_PERF_SEL_DB_CB_eop_dones
48790. DB_PERF_SEL_DB_CB_lquad_busy
48791. DB_PERF_SEL_DB_CB_lquad_double_format
48792. DB_PERF_SEL_DB_CB_lquad_export_quads
48793. DB_PERF_SEL_DB_CB_lquad_fast_format
48794. DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix
48795. DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix
48796. DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix
48797. DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix
48798. DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending
48799. DB_PERF_SEL_DB_CB_lquad_quads
48800. DB_PERF_SEL_DB_CB_lquad_sends
48801. DB_PERF_SEL_DB_CB_lquad_slow_format
48802. DB_PERF_SEL_DB_CB_lquad_stalls
48803. DB_PERF_SEL_DB_CB_rdret_ack
48804. DB_PERF_SEL_DB_CB_rdret_nack
48805. DB_PERF_SEL_DB_CB_tile_busy
48806. DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS
48807. DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA
48808. DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS
48809. DB_PERF_SEL_DB_CB_tile_sends
48810. DB_PERF_SEL_DB_CB_tile_stalls
48811. DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event
48812. DB_PERF_SEL_DB_CB_wrret_ack
48813. DB_PERF_SEL_DB_CB_wrret_nack
48814. DB_PERF_SEL_DB_SC_c_tile_rate
48815. DB_PERF_SEL_DB_SC_quad_busy
48816. DB_PERF_SEL_DB_SC_quad_double_quad
48817. DB_PERF_SEL_DB_SC_quad_lit_quad
48818. DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke
48819. DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel
48820. DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels
48821. DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels
48822. DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels
48823. DB_PERF_SEL_DB_SC_quad_sends
48824. DB_PERF_SEL_DB_SC_quad_stalls
48825. DB_PERF_SEL_DB_SC_quad_tiles
48826. DB_PERF_SEL_DB_SC_s_tile_rate
48827. DB_PERF_SEL_DB_SC_tile_busy
48828. DB_PERF_SEL_DB_SC_tile_culled
48829. DB_PERF_SEL_DB_SC_tile_df_stalls
48830. DB_PERF_SEL_DB_SC_tile_fast_ops
48831. DB_PERF_SEL_DB_SC_tile_fast_stencil_ops
48832. DB_PERF_SEL_DB_SC_tile_fast_z_ops
48833. DB_PERF_SEL_DB_SC_tile_hier_kill
48834. DB_PERF_SEL_DB_SC_tile_no_ops
48835. DB_PERF_SEL_DB_SC_tile_sends
48836. DB_PERF_SEL_DB_SC_tile_ssaa_kill
48837. DB_PERF_SEL_DB_SC_tile_stalls
48838. DB_PERF_SEL_DB_SC_tile_tile_rate
48839. DB_PERF_SEL_DB_SC_tile_tiles
48840. DB_PERF_SEL_DB_SC_z_tile_rate
48841. DB_PERF_SEL_DFSM_Flush_flushabit
48842. DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo
48843. DB_PERF_SEL_DFSM_Flush_flushabit_forceflush
48844. DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull
48845. DB_PERF_SEL_DFSM_Flush_flushabit_passthrough
48846. DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark
48847. DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling
48848. DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark
48849. DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark
48850. DB_PERF_SEL_DFSM_Flush_flushall
48851. DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush
48852. DB_PERF_SEL_DFSM_Flush_flushall_opmodechange
48853. DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange
48854. DB_PERF_SEL_DFSM_Flush_flushall_watchdog
48855. DB_PERF_SEL_DFSM_Stall_bypass_fifo
48856. DB_PERF_SEL_DFSM_Stall_cam_fifo
48857. DB_PERF_SEL_DFSM_Stall_control_fifo
48858. DB_PERF_SEL_DFSM_Stall_middle_output
48859. DB_PERF_SEL_DFSM_Stall_opmode_change
48860. DB_PERF_SEL_DFSM_Stall_overflow_counter
48861. DB_PERF_SEL_DFSM_Stall_pops_stall_overflow
48862. DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush
48863. DB_PERF_SEL_DFSM_Stall_retained_tile_fifo
48864. DB_PERF_SEL_DFSM_Stall_stalling_general
48865. DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream
48866. DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO
48867. DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow
48868. DB_PERF_SEL_DFSM_cycles_above_watermark
48869. DB_PERF_SEL_DFSM_evicted_squads_above_watermark
48870. DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark
48871. DB_PERF_SEL_DFSM_evicted_tiles_above_watermark
48872. DB_PERF_SEL_DFSM_full_cleared_squads_out
48873. DB_PERF_SEL_DFSM_fully_cleared_pixels_out
48874. DB_PERF_SEL_DFSM_fully_cleared_quads_out
48875. DB_PERF_SEL_DFSM_lit_pixels_in
48876. DB_PERF_SEL_DFSM_lit_samples_in
48877. DB_PERF_SEL_DFSM_lit_samples_out
48878. DB_PERF_SEL_DFSM_prez_killed_squad
48879. DB_PERF_SEL_DFSM_quads_in
48880. DB_PERF_SEL_DFSM_squads_in
48881. DB_PERF_SEL_DFSM_stalled_by_downstream
48882. DB_PERF_SEL_Depth_Tile_Cache_alloc_stall
48883. DB_PERF_SEL_Depth_Tile_Cache_busy
48884. DB_PERF_SEL_Depth_Tile_Cache_data_frees
48885. DB_PERF_SEL_Depth_Tile_Cache_detailed_noop
48886. DB_PERF_SEL_Depth_Tile_Cache_dtile_locked
48887. DB_PERF_SEL_Depth_Tile_Cache_event
48888. DB_PERF_SEL_Depth_Tile_Cache_flushes
48889. DB_PERF_SEL_Depth_Tile_Cache_hits
48890. DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve
48891. DB_PERF_SEL_Depth_Tile_Cache_misses
48892. DB_PERF_SEL_Depth_Tile_Cache_noop_tile
48893. DB_PERF_SEL_Depth_Tile_Cache_sends
48894. DB_PERF_SEL_Depth_Tile_Cache_starves
48895. DB_PERF_SEL_Depth_Tile_Cache_tile_frees
48896. DB_PERF_SEL_MI_psd_req_wrack_counter_stall
48897. DB_PERF_SEL_MI_quad_req_wrack_counter_stall
48898. DB_PERF_SEL_MI_tile_req_wrack_counter_stall
48899. DB_PERF_SEL_MI_zpc_req_wrack_counter_stall
48900. DB_PERF_SEL_Op_Pipe_Busy
48901. DB_PERF_SEL_Op_Pipe_MC_Read_stall
48902. DB_PERF_SEL_Op_Pipe_Postz_Busy
48903. DB_PERF_SEL_Op_Pipe_Prez_Busy
48904. DB_PERF_SEL_Plane_Cache_flushes
48905. DB_PERF_SEL_Plane_Cache_frees
48906. DB_PERF_SEL_Plane_Cache_hits
48907. DB_PERF_SEL_Plane_Cache_misses
48908. DB_PERF_SEL_Plane_Cache_starves
48909. DB_PERF_SEL_PostZ_Samples_failing_DB
48910. DB_PERF_SEL_PostZ_Samples_failing_S
48911. DB_PERF_SEL_PostZ_Samples_failing_Z
48912. DB_PERF_SEL_PostZ_Samples_passing_Z
48913. DB_PERF_SEL_PreZ_Samples_failing_DB
48914. DB_PERF_SEL_PreZ_Samples_failing_S
48915. DB_PERF_SEL_PreZ_Samples_failing_Z
48916. DB_PERF_SEL_PreZ_Samples_passing_Z
48917. DB_PERF_SEL_SC_DB_quad_busy
48918. DB_PERF_SEL_SC_DB_quad_killed_tiles
48919. DB_PERF_SEL_SC_DB_quad_pixels
48920. DB_PERF_SEL_SC_DB_quad_quads
48921. DB_PERF_SEL_SC_DB_quad_sends
48922. DB_PERF_SEL_SC_DB_quad_squads
48923. DB_PERF_SEL_SC_DB_quad_tiles
48924. DB_PERF_SEL_SC_DB_tile_backface
48925. DB_PERF_SEL_SC_DB_tile_busy
48926. DB_PERF_SEL_SC_DB_tile_covered
48927. DB_PERF_SEL_SC_DB_tile_events
48928. DB_PERF_SEL_SC_DB_tile_sends
48929. DB_PERF_SEL_SC_DB_tile_stalls
48930. DB_PERF_SEL_SC_DB_tile_tiles
48931. DB_PERF_SEL_SH_quads_outstanding_sum
48932. DB_PERF_SEL_SX_DB_quad_all_pixels_enabled
48933. DB_PERF_SEL_SX_DB_quad_all_pixels_killed
48934. DB_PERF_SEL_SX_DB_quad_busy
48935. DB_PERF_SEL_SX_DB_quad_double_format
48936. DB_PERF_SEL_SX_DB_quad_export_quads
48937. DB_PERF_SEL_SX_DB_quad_exports
48938. DB_PERF_SEL_SX_DB_quad_fast_format
48939. DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read
48940. DB_PERF_SEL_SX_DB_quad_pixels
48941. DB_PERF_SEL_SX_DB_quad_quads
48942. DB_PERF_SEL_SX_DB_quad_sends
48943. DB_PERF_SEL_SX_DB_quad_slow_format
48944. DB_PERF_SEL_SX_DB_quad_stalls
48945. DB_PERF_SEL_Stencil_Cache_flushes
48946. DB_PERF_SEL_Stencil_Cache_frees
48947. DB_PERF_SEL_Stencil_Cache_hits
48948. DB_PERF_SEL_Stencil_Cache_misses
48949. DB_PERF_SEL_Stencil_Cache_starves
48950. DB_PERF_SEL_Tile_Cache_flushes
48951. DB_PERF_SEL_Tile_Cache_hits
48952. DB_PERF_SEL_Tile_Cache_mem_return_starve
48953. DB_PERF_SEL_Tile_Cache_misses
48954. DB_PERF_SEL_Tile_Cache_starves
48955. DB_PERF_SEL_Tile_Cache_surface_stall
48956. DB_PERF_SEL_Z_Cache_frees
48957. DB_PERF_SEL_Z_Cache_pmask_flushes
48958. DB_PERF_SEL_Z_Cache_pmask_hits
48959. DB_PERF_SEL_Z_Cache_pmask_misses
48960. DB_PERF_SEL_Z_Cache_pmask_starves
48961. DB_PERF_SEL_Z_Cache_separate_Z_flushes
48962. DB_PERF_SEL_Z_Cache_separate_Z_hits
48963. DB_PERF_SEL_Z_Cache_separate_Z_misses
48964. DB_PERF_SEL_Z_Cache_separate_Z_starves
48965. DB_PERF_SEL_clock_main_active
48966. DB_PERF_SEL_clock_mem_export_active
48967. DB_PERF_SEL_clock_reg_active
48968. DB_PERF_SEL_depth_bounds_qtiles_culled
48969. DB_PERF_SEL_depth_bounds_tile_culled
48970. DB_PERF_SEL_di_dt_stall
48971. DB_PERF_SEL_dk_squad_busy
48972. DB_PERF_SEL_dk_squad_sends
48973. DB_PERF_SEL_dk_squad_stalls
48974. DB_PERF_SEL_dk_tile_busy
48975. DB_PERF_SEL_dk_tile_quad_starves
48976. DB_PERF_SEL_dk_tile_sends
48977. DB_PERF_SEL_dk_tile_stalls
48978. DB_PERF_SEL_dkg_tile_rate_tile
48979. DB_PERF_SEL_dtt_sm_clash_stall
48980. DB_PERF_SEL_dtt_sm_miss_stall
48981. DB_PERF_SEL_dtt_sm_slot_stall
48982. DB_PERF_SEL_earlyZ_waiting_for_postZ_done
48983. DB_PERF_SEL_esr_eot_fwd_busy
48984. DB_PERF_SEL_esr_eot_fwd_forward
48985. DB_PERF_SEL_esr_eot_fwd_holding_squad
48986. DB_PERF_SEL_esr_ps_lqf_busy
48987. DB_PERF_SEL_esr_ps_lqf_stall
48988. DB_PERF_SEL_esr_ps_out_busy
48989. DB_PERF_SEL_esr_ps_sqq_busy
48990. DB_PERF_SEL_esr_ps_sqq_stall
48991. DB_PERF_SEL_esr_ps_src_in_sends
48992. DB_PERF_SEL_esr_ps_src_in_squads
48993. DB_PERF_SEL_esr_ps_src_in_squads_unrolled
48994. DB_PERF_SEL_esr_ps_src_in_stall
48995. DB_PERF_SEL_esr_ps_src_in_tile_rate
48996. DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled
48997. DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate
48998. DB_PERF_SEL_esr_ps_src_out_stall
48999. DB_PERF_SEL_esr_sqq_zi_busy
49000. DB_PERF_SEL_esr_sqq_zi_stall
49001. DB_PERF_SEL_etr_out_busy
49002. DB_PERF_SEL_etr_out_cb_tile_stall
49003. DB_PERF_SEL_etr_out_esr_stall
49004. DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall
49005. DB_PERF_SEL_etr_out_send
49006. DB_PERF_SEL_flush_10plane
49007. DB_PERF_SEL_flush_11plane
49008. DB_PERF_SEL_flush_12plane
49009. DB_PERF_SEL_flush_13plane
49010. DB_PERF_SEL_flush_14plane
49011. DB_PERF_SEL_flush_15plane
49012. DB_PERF_SEL_flush_16plane
49013. DB_PERF_SEL_flush_1plane
49014. DB_PERF_SEL_flush_2plane
49015. DB_PERF_SEL_flush_3plane
49016. DB_PERF_SEL_flush_4plane
49017. DB_PERF_SEL_flush_5plane
49018. DB_PERF_SEL_flush_6plane
49019. DB_PERF_SEL_flush_7plane
49020. DB_PERF_SEL_flush_8plane
49021. DB_PERF_SEL_flush_9plane
49022. DB_PERF_SEL_flush_compressed
49023. DB_PERF_SEL_flush_compressed_stencil
49024. DB_PERF_SEL_flush_expanded_stencil
49025. DB_PERF_SEL_flush_expanded_z
49026. DB_PERF_SEL_flush_plane_le4
49027. DB_PERF_SEL_flush_single_stencil
49028. DB_PERF_SEL_his_qtiles_culled
49029. DB_PERF_SEL_his_tile_culled
49030. DB_PERF_SEL_hiz_qtiles_culled
49031. DB_PERF_SEL_hiz_tc_read_starved
49032. DB_PERF_SEL_hiz_tc_write_stall
49033. DB_PERF_SEL_hiz_tile_culled
49034. DB_PERF_SEL_mi_quad_rd_outstanding_sum
49035. DB_PERF_SEL_mi_quad_wr_outstanding_sum
49036. DB_PERF_SEL_mi_rdreq_busy
49037. DB_PERF_SEL_mi_rdreq_stall
49038. DB_PERF_SEL_mi_tile_rd_outstanding_sum
49039. DB_PERF_SEL_mi_tile_wr_outstanding_sum
49040. DB_PERF_SEL_mi_wrreq_busy
49041. DB_PERF_SEL_mi_wrreq_stall
49042. DB_PERF_SEL_planes_flushed
49043. DB_PERF_SEL_postzl_full_launch
49044. DB_PERF_SEL_postzl_partial_launch
49045. DB_PERF_SEL_postzl_partial_waiting
49046. DB_PERF_SEL_postzl_se_busy
49047. DB_PERF_SEL_postzl_se_stall
49048. DB_PERF_SEL_postzl_sq_pt_busy
49049. DB_PERF_SEL_postzl_sq_pt_stall
49050. DB_PERF_SEL_postzl_src_in_sends
49051. DB_PERF_SEL_postzl_src_in_squads
49052. DB_PERF_SEL_postzl_src_in_squads_unrolled
49053. DB_PERF_SEL_postzl_src_in_stall
49054. DB_PERF_SEL_postzl_src_in_tile_rate
49055. DB_PERF_SEL_postzl_src_in_tile_rate_unrolled
49056. DB_PERF_SEL_postzl_src_out_stall
49057. DB_PERF_SEL_postzl_tile_init_stall
49058. DB_PERF_SEL_postzl_tile_mem_stall
49059. DB_PERF_SEL_prezl_src_in_sends
49060. DB_PERF_SEL_prezl_src_in_squads
49061. DB_PERF_SEL_prezl_src_in_squads_unrolled
49062. DB_PERF_SEL_prezl_src_in_stall
49063. DB_PERF_SEL_prezl_src_in_tile_rate
49064. DB_PERF_SEL_prezl_src_in_tile_rate_unrolled
49065. DB_PERF_SEL_prezl_src_out_stall
49066. DB_PERF_SEL_prezl_tile_init_stall
49067. DB_PERF_SEL_prezl_tile_mem_stall
49068. DB_PERF_SEL_qc_busy
49069. DB_PERF_SEL_qc_conflicts
49070. DB_PERF_SEL_qc_full_stall
49071. DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ
49072. DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ
49073. DB_PERF_SEL_qc_xfc
49074. DB_PERF_SEL_quad_rd_32byte_reqs
49075. DB_PERF_SEL_quad_rd_busy
49076. DB_PERF_SEL_quad_rd_mi_stall
49077. DB_PERF_SEL_quad_rd_panic
49078. DB_PERF_SEL_quad_rd_rw_collision
49079. DB_PERF_SEL_quad_rd_sends
49080. DB_PERF_SEL_quad_rd_tag_stall
49081. DB_PERF_SEL_quad_rdret_busy
49082. DB_PERF_SEL_quad_rdret_sends
49083. DB_PERF_SEL_quad_wr_acks
49084. DB_PERF_SEL_quad_wr_busy
49085. DB_PERF_SEL_quad_wr_coherency_stall
49086. DB_PERF_SEL_quad_wr_mi_stall
49087. DB_PERF_SEL_quad_wr_sends
49088. DB_PERF_SEL_reZ_waiting_for_postZ_done
49089. DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop
49090. DB_PERF_SEL_sc_kick_end
49091. DB_PERF_SEL_sc_kick_start
49092. DB_PERF_SEL_tcp_dispatcher_flushes
49093. DB_PERF_SEL_tcp_dispatcher_reads
49094. DB_PERF_SEL_tcp_prefetcher_flushes
49095. DB_PERF_SEL_tcp_prefetcher_reads
49096. DB_PERF_SEL_tcp_preloader_flushes
49097. DB_PERF_SEL_tcp_preloader_reads
49098. DB_PERF_SEL_tile_rd_sends
49099. DB_PERF_SEL_tile_wr_acks
49100. DB_PERF_SEL_tile_wr_sends
49101. DB_PERF_SEL_tiles_compressed_to_decompressed
49102. DB_PERF_SEL_tiles_decomp_on_expclear
49103. DB_PERF_SEL_tiles_s_clear_on_expclear
49104. DB_PERF_SEL_tiles_stencil_fully_summarized
49105. DB_PERF_SEL_tiles_z_clear_on_expclear
49106. DB_PERF_SEL_tiles_z_fully_summarized
49107. DB_PERF_SEL_tl_busy
49108. DB_PERF_SEL_tl_dtc_read_starved
49109. DB_PERF_SEL_tl_events
49110. DB_PERF_SEL_tl_expand_squads
49111. DB_PERF_SEL_tl_flush_expand_squads
49112. DB_PERF_SEL_tl_in_fast_z_stall
49113. DB_PERF_SEL_tl_in_single_stencil_expand_stall
49114. DB_PERF_SEL_tl_in_xfc
49115. DB_PERF_SEL_tl_out_squads
49116. DB_PERF_SEL_tl_out_xfc
49117. DB_PERF_SEL_tl_postZ_noop_squads
49118. DB_PERF_SEL_tl_postZ_squads
49119. DB_PERF_SEL_tl_preZ_noop_squads
49120. DB_PERF_SEL_tl_preZ_squads
49121. DB_PERF_SEL_tl_stencil_locked_stall
49122. DB_PERF_SEL_tl_stencil_stall
49123. DB_PERF_SEL_tl_summarize_squads
49124. DB_PERF_SEL_tl_tile_ops
49125. DB_PERF_SEL_tl_z_decompress_stall
49126. DB_PERF_SEL_tl_z_fetch_stall
49127. DB_PERF_SEL_ts_tc_update_stall
49128. DB_PERF_SEL_tsc_insert_summarize_stall
49129. DB_PERF_SEL_unmapped_z_tile_culled
49130. DB_PERF_SEL_zf_plane_multicycle
49131. DB_PLC
49132. DB_PR
49133. DB_PRELOAD_CONTROL__MAX_X_MASK
49134. DB_PRELOAD_CONTROL__MAX_X__SHIFT
49135. DB_PRELOAD_CONTROL__MAX_Y_MASK
49136. DB_PRELOAD_CONTROL__MAX_Y__SHIFT
49137. DB_PRELOAD_CONTROL__START_X_MASK
49138. DB_PRELOAD_CONTROL__START_X__SHIFT
49139. DB_PRELOAD_CONTROL__START_Y_MASK
49140. DB_PRELOAD_CONTROL__START_Y__SHIFT
49141. DB_PSINVOKE_CHANGE_EVENT
49142. DB_PWM_ADDR_DPI_MASK
49143. DB_PWM_ADDR_DPI_SHIFT
49144. DB_PWM_ADDR_OFFSET_MASK
49145. DB_PWM_ADDR_OFFSET_SHIFT
49146. DB_PWM_ADDR_RESERVED0_MASK
49147. DB_PWM_ADDR_RESERVED0_SHIFT
49148. DB_PWM_ADDR_RESERVED1_MASK
49149. DB_PWM_ADDR_RESERVED1_SHIFT
49150. DB_PWM_ADDR_WID_MASK
49151. DB_PWM_ADDR_WID_SHIFT
49152. DB_QUEUE_COMMAND
49153. DB_QWORD_DISPLAY
49154. DB_RAM
49155. DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK
49156. DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT
49157. DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK
49158. DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT
49159. DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK
49160. DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT
49161. DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK
49162. DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT
49163. DB_RDMA_DPM_PARAMS_OPCODE_MASK
49164. DB_RDMA_DPM_PARAMS_OPCODE_SHIFT
49165. DB_RDMA_DPM_PARAMS_RESERVED0_MASK
49166. DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT
49167. DB_RDMA_DPM_PARAMS_SIZE_MASK
49168. DB_RDMA_DPM_PARAMS_SIZE_SHIFT
49169. DB_RDMA_DPM_PARAMS_S_FLG_MASK
49170. DB_RDMA_DPM_PARAMS_S_FLG_SHIFT
49171. DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK
49172. DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT
49173. DB_READ_DEBUG_0__BUSY_DATA0_MASK
49174. DB_READ_DEBUG_0__BUSY_DATA0__SHIFT
49175. DB_READ_DEBUG_1__BUSY_DATA1_MASK
49176. DB_READ_DEBUG_1__BUSY_DATA1__SHIFT
49177. DB_READ_DEBUG_2__BUSY_DATA2_MASK
49178. DB_READ_DEBUG_2__BUSY_DATA2__SHIFT
49179. DB_READ_DEBUG_3__DEBUG_DATA_MASK
49180. DB_READ_DEBUG_3__DEBUG_DATA__SHIFT
49181. DB_READ_DEBUG_4__DEBUG_DATA_MASK
49182. DB_READ_DEBUG_4__DEBUG_DATA__SHIFT
49183. DB_READ_DEBUG_5__DEBUG_DATA_MASK
49184. DB_READ_DEBUG_5__DEBUG_DATA__SHIFT
49185. DB_READ_DEBUG_6__DEBUG_DATA_MASK
49186. DB_READ_DEBUG_6__DEBUG_DATA__SHIFT
49187. DB_READ_DEBUG_7__DEBUG_DATA_MASK
49188. DB_READ_DEBUG_7__DEBUG_DATA__SHIFT
49189. DB_READ_DEBUG_8__DEBUG_DATA_MASK
49190. DB_READ_DEBUG_8__DEBUG_DATA__SHIFT
49191. DB_READ_DEBUG_9__DEBUG_DATA_MASK
49192. DB_READ_DEBUG_9__DEBUG_DATA__SHIFT
49193. DB_READ_DEBUG_A__DEBUG_DATA_MASK
49194. DB_READ_DEBUG_A__DEBUG_DATA__SHIFT
49195. DB_READ_DEBUG_B__DEBUG_DATA_MASK
49196. DB_READ_DEBUG_B__DEBUG_DATA__SHIFT
49197. DB_READ_DEBUG_C__DEBUG_DATA_MASK
49198. DB_READ_DEBUG_C__DEBUG_DATA__SHIFT
49199. DB_READ_DEBUG_D__DEBUG_DATA_MASK
49200. DB_READ_DEBUG_D__DEBUG_DATA__SHIFT
49201. DB_READ_DEBUG_E__DEBUG_DATA_MASK
49202. DB_READ_DEBUG_E__DEBUG_DATA__SHIFT
49203. DB_READ_DEBUG_F__DEBUG_DATA_MASK
49204. DB_READ_DEBUG_F__DEBUG_DATA__SHIFT
49205. DB_REC_DRY_RUN
49206. DB_REC_KERNEL
49207. DB_REC_ONCE
49208. DB_REC_REAL_DEAL
49209. DB_REC_USER
49210. DB_REC_WIDTH_32B
49211. DB_REC_WIDTH_64B
49212. DB_REG_OFFSET
49213. DB_RENDER_CONTROL
49214. DB_RENDER_CONTROL__COPY_CENTROID_MASK
49215. DB_RENDER_CONTROL__COPY_CENTROID__SHIFT
49216. DB_RENDER_CONTROL__COPY_SAMPLE_MASK
49217. DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT
49218. DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK
49219. DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT
49220. DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK
49221. DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT
49222. DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK
49223. DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT
49224. DB_RENDER_CONTROL__DEPTH_COPY_MASK
49225. DB_RENDER_CONTROL__DEPTH_COPY__SHIFT
49226. DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK
49227. DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT
49228. DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK
49229. DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT
49230. DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK
49231. DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT
49232. DB_RENDER_CONTROL__STENCIL_COPY_MASK
49233. DB_RENDER_CONTROL__STENCIL_COPY__SHIFT
49234. DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK
49235. DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT
49236. DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK
49237. DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT
49238. DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK
49239. DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT
49240. DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK
49241. DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT
49242. DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK
49243. DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT
49244. DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK
49245. DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT
49246. DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK
49247. DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT
49248. DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK
49249. DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT
49250. DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK
49251. DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT
49252. DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK
49253. DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT
49254. DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK
49255. DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT
49256. DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK
49257. DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT
49258. DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK
49259. DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT
49260. DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK
49261. DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT
49262. DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK
49263. DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT
49264. DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK
49265. DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT
49266. DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK
49267. DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT
49268. DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK
49269. DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT
49270. DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK
49271. DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT
49272. DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK
49273. DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT
49274. DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK
49275. DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT
49276. DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK
49277. DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT
49278. DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK
49279. DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT
49280. DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK
49281. DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT
49282. DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK
49283. DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT
49284. DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK
49285. DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT
49286. DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK
49287. DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT
49288. DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK
49289. DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT
49290. DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK
49291. DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT
49292. DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK
49293. DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT
49294. DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK
49295. DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT
49296. DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK
49297. DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT
49298. DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK
49299. DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT
49300. DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK
49301. DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT
49302. DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK
49303. DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT
49304. DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK
49305. DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT
49306. DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK
49307. DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT
49308. DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK
49309. DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT
49310. DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK
49311. DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT
49312. DB_RESERVED_REG_1__FIELD_1_MASK
49313. DB_RESERVED_REG_1__FIELD_1__SHIFT
49314. DB_RESERVED_REG_1__FIELD_2_MASK
49315. DB_RESERVED_REG_1__FIELD_2__SHIFT
49316. DB_RESERVED_REG_2__FIELD_1_MASK
49317. DB_RESERVED_REG_2__FIELD_1__SHIFT
49318. DB_RESERVED_REG_2__FIELD_2_MASK
49319. DB_RESERVED_REG_2__FIELD_2__SHIFT
49320. DB_RESERVED_REG_2__FIELD_3_MASK
49321. DB_RESERVED_REG_2__FIELD_3__SHIFT
49322. DB_RESERVED_REG_2__FIELD_4_MASK
49323. DB_RESERVED_REG_2__FIELD_4__SHIFT
49324. DB_RESERVED_REG_2__FIELD_5_MASK
49325. DB_RESERVED_REG_2__FIELD_5__SHIFT
49326. DB_RESERVED_REG_2__FIELD_6_MASK
49327. DB_RESERVED_REG_2__FIELD_6__SHIFT
49328. DB_RESERVED_REG_2__FIELD_7_MASK
49329. DB_RESERVED_REG_2__FIELD_7__SHIFT
49330. DB_RESERVED_REG_2__FIELD_8_MASK
49331. DB_RESERVED_REG_2__FIELD_8__SHIFT
49332. DB_RESERVED_REG_3__FIELD_1_MASK
49333. DB_RESERVED_REG_3__FIELD_1__SHIFT
49334. DB_RESET
49335. DB_RES_ACCEPT
49336. DB_RES_DEF
49337. DB_RES_DROP
49338. DB_RING_CONTROL__COUNTER_CONTROL_MASK
49339. DB_RING_CONTROL__COUNTER_CONTROL__SHIFT
49340. DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK
49341. DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT
49342. DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK
49343. DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT
49344. DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK
49345. DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT
49346. DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK
49347. DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT
49348. DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK
49349. DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT
49350. DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK
49351. DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT
49352. DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK
49353. DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT
49354. DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK
49355. DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT
49356. DB_RMI_CACHE_POLICY__CC_RD_MASK
49357. DB_RMI_CACHE_POLICY__CC_RD__SHIFT
49358. DB_RMI_CACHE_POLICY__CC_WR_MASK
49359. DB_RMI_CACHE_POLICY__CC_WR__SHIFT
49360. DB_RMI_CACHE_POLICY__CMASK_RD_MASK
49361. DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT
49362. DB_RMI_CACHE_POLICY__CMASK_WR_MASK
49363. DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT
49364. DB_RMI_CACHE_POLICY__DCC_RD_MASK
49365. DB_RMI_CACHE_POLICY__DCC_RD__SHIFT
49366. DB_RMI_CACHE_POLICY__DCC_WR_MASK
49367. DB_RMI_CACHE_POLICY__DCC_WR__SHIFT
49368. DB_RMI_CACHE_POLICY__FMASK_RD_MASK
49369. DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT
49370. DB_RMI_CACHE_POLICY__FMASK_WR_MASK
49371. DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT
49372. DB_RMI_CACHE_POLICY__HTILE_RD_MASK
49373. DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT
49374. DB_RMI_CACHE_POLICY__HTILE_WR_MASK
49375. DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT
49376. DB_RMI_CACHE_POLICY__S_RD_MASK
49377. DB_RMI_CACHE_POLICY__S_RD__SHIFT
49378. DB_RMI_CACHE_POLICY__S_WR_MASK
49379. DB_RMI_CACHE_POLICY__S_WR__SHIFT
49380. DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK
49381. DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT
49382. DB_RMI_CACHE_POLICY__Z_RD_MASK
49383. DB_RMI_CACHE_POLICY__Z_RD__SHIFT
49384. DB_RMI_CACHE_POLICY__Z_WR_MASK
49385. DB_RMI_CACHE_POLICY__Z_WR__SHIFT
49386. DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK
49387. DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT
49388. DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK
49389. DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT
49390. DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK
49391. DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT
49392. DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK
49393. DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT
49394. DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK
49395. DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT
49396. DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK
49397. DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT
49398. DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK
49399. DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT
49400. DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK
49401. DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT
49402. DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK
49403. DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT
49404. DB_RMT
49405. DB_RMTN
49406. DB_ROOT_DEFAULT
49407. DB_ROOT_LEN
49408. DB_ROOT_PREFERRED
49409. DB_RQ_NUM_POSTED_SHIFT
49410. DB_RQ_OFFSET
49411. DB_RQ_RING_ID_MASK
49412. DB_RX
49413. DB_RXULP0_OFFSET
49414. DB_SBA
49415. DB_SBAN
49416. DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK
49417. DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT
49418. DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK
49419. DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT
49420. DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK
49421. DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT
49422. DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK
49423. DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT
49424. DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK
49425. DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT
49426. DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK
49427. DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT
49428. DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK
49429. DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT
49430. DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK
49431. DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT
49432. DB_SHADER_CONTROL__KILL_ENABLE_MASK
49433. DB_SHADER_CONTROL__KILL_ENABLE__SHIFT
49434. DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK
49435. DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT
49436. DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK
49437. DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT
49438. DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK
49439. DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT
49440. DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK
49441. DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT
49442. DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK
49443. DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT
49444. DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK
49445. DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT
49446. DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK
49447. DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT
49448. DB_SHADER_CONTROL__Z_ORDER_MASK
49449. DB_SHADER_CONTROL__Z_ORDER__SHIFT
49450. DB_SMT
49451. DB_SMTN
49452. DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK
49453. DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT
49454. DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK
49455. DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT
49456. DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK
49457. DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT
49458. DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK
49459. DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT
49460. DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK
49461. DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT
49462. DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK
49463. DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT
49464. DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK
49465. DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT
49466. DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK
49467. DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT
49468. DB_STATE_TIMEOUT
49469. DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK
49470. DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT
49471. DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK
49472. DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT
49473. DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK
49474. DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT
49475. DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK
49476. DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT
49477. DB_STENCILREFMASK__STENCILMASK_MASK
49478. DB_STENCILREFMASK__STENCILMASK__SHIFT
49479. DB_STENCILREFMASK__STENCILOPVAL_MASK
49480. DB_STENCILREFMASK__STENCILOPVAL__SHIFT
49481. DB_STENCILREFMASK__STENCILTESTVAL_MASK
49482. DB_STENCILREFMASK__STENCILTESTVAL__SHIFT
49483. DB_STENCILREFMASK__STENCILWRITEMASK_MASK
49484. DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT
49485. DB_STENCIL_CLEAR__CLEAR_MASK
49486. DB_STENCIL_CLEAR__CLEAR__SHIFT
49487. DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK
49488. DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT
49489. DB_STENCIL_CONTROL__STENCILFAIL_MASK
49490. DB_STENCIL_CONTROL__STENCILFAIL__SHIFT
49491. DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK
49492. DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT
49493. DB_STENCIL_CONTROL__STENCILZFAIL_MASK
49494. DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT
49495. DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK
49496. DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT
49497. DB_STENCIL_CONTROL__STENCILZPASS_MASK
49498. DB_STENCIL_CONTROL__STENCILZPASS__SHIFT
49499. DB_STENCIL_INFO
49500. DB_STENCIL_INFO2__EPITCH_MASK
49501. DB_STENCIL_INFO2__EPITCH__SHIFT
49502. DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK
49503. DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT
49504. DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK
49505. DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT
49506. DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK
49507. DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT
49508. DB_STENCIL_INFO__FORMAT_MASK
49509. DB_STENCIL_INFO__FORMAT__SHIFT
49510. DB_STENCIL_INFO__ITERATE_256_MASK
49511. DB_STENCIL_INFO__ITERATE_256__SHIFT
49512. DB_STENCIL_INFO__ITERATE_FLUSH_MASK
49513. DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT
49514. DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK
49515. DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT
49516. DB_STENCIL_INFO__RESERVED_FIELD_1_MASK
49517. DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT
49518. DB_STENCIL_INFO__SW_MODE_MASK
49519. DB_STENCIL_INFO__SW_MODE__SHIFT
49520. DB_STENCIL_INFO__TILE_MODE_INDEX_MASK
49521. DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT
49522. DB_STENCIL_INFO__TILE_SPLIT_MASK
49523. DB_STENCIL_INFO__TILE_SPLIT__SHIFT
49524. DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK
49525. DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT
49526. DB_STENCIL_READ_BASE
49527. DB_STENCIL_READ_BASE_HI__BASE_HI_MASK
49528. DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT
49529. DB_STENCIL_READ_BASE__BASE_256B_MASK
49530. DB_STENCIL_READ_BASE__BASE_256B__SHIFT
49531. DB_STENCIL_WRITE_BASE
49532. DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK
49533. DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT
49534. DB_STENCIL_WRITE_BASE__BASE_256B_MASK
49535. DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT
49536. DB_SUBTILE_CONTROL__MSAA16_X_MASK
49537. DB_SUBTILE_CONTROL__MSAA16_X__SHIFT
49538. DB_SUBTILE_CONTROL__MSAA16_Y_MASK
49539. DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT
49540. DB_SUBTILE_CONTROL__MSAA1_X_MASK
49541. DB_SUBTILE_CONTROL__MSAA1_X__SHIFT
49542. DB_SUBTILE_CONTROL__MSAA1_Y_MASK
49543. DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT
49544. DB_SUBTILE_CONTROL__MSAA2_X_MASK
49545. DB_SUBTILE_CONTROL__MSAA2_X__SHIFT
49546. DB_SUBTILE_CONTROL__MSAA2_Y_MASK
49547. DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT
49548. DB_SUBTILE_CONTROL__MSAA4_X_MASK
49549. DB_SUBTILE_CONTROL__MSAA4_X__SHIFT
49550. DB_SUBTILE_CONTROL__MSAA4_Y_MASK
49551. DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT
49552. DB_SUBTILE_CONTROL__MSAA8_X_MASK
49553. DB_SUBTILE_CONTROL__MSAA8_X__SHIFT
49554. DB_SUBTILE_CONTROL__MSAA8_Y_MASK
49555. DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT
49556. DB_TEST
49557. DB_TEST1
49558. DB_TEST2
49559. DB_TILE_SPLIT
49560. DB_TIMER
49561. DB_TMR_LARGE_OFF
49562. DB_TMR_OUT_MASK
49563. DB_TMR_OUT_OFF
49564. DB_TMR_OUT_UNIT_OFF
49565. DB_TRANSFER
49566. DB_TX
49567. DB_TXULP0_OFFSET
49568. DB_TXULP1_OFFSET
49569. DB_TXULP_NUM_POSTED_MASK
49570. DB_TXULP_NUM_POSTED_SHIFT
49571. DB_TXULP_RING_ID_MASK
49572. DB_TYPE_NO_DEBOUNCE
49573. DB_TYPE_PRESERVE_HIGH_GLITCH
49574. DB_TYPE_PRESERVE_LOW_GLITCH
49575. DB_TYPE_REMOVE_GLITCH
49576. DB_VALUE
49577. DB_VALUE_BY_INDEX
49578. DB_VALUE_EP0_IN
49579. DB_VALUE_EP0_OUT
49580. DB_VALUE_HOST
49581. DB_VECTOR
49582. DB_VPORT_CHANGED_EVENT
49583. DB_WATERMARKS
49584. DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK
49585. DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT
49586. DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK
49587. DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT
49588. DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK
49589. DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT
49590. DB_WATERMARKS__DEPTH_FLUSH_MASK
49591. DB_WATERMARKS__DEPTH_FLUSH__SHIFT
49592. DB_WATERMARKS__DEPTH_FREE_MASK
49593. DB_WATERMARKS__DEPTH_FREE__SHIFT
49594. DB_WATERMARKS__DEPTH_PENDING_FREE_MASK
49595. DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT
49596. DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK
49597. DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT
49598. DB_WATERMARKS__FORCE_SUMMARIZE_MASK
49599. DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT
49600. DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK
49601. DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT
49602. DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK
49603. DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT
49604. DB_WORD_DISPLAY
49605. DB_WRB_POST_CID_MASK
49606. DB_ZPASS_COUNT_HI__COUNT_HI_MASK
49607. DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT
49608. DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK
49609. DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT
49610. DB_Z_INFO
49611. DB_Z_INFO2__EPITCH_MASK
49612. DB_Z_INFO2__EPITCH__SHIFT
49613. DB_Z_INFO__ALLOW_EXPCLEAR_MASK
49614. DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT
49615. DB_Z_INFO__CLEAR_DISALLOWED_MASK
49616. DB_Z_INFO__CLEAR_DISALLOWED__SHIFT
49617. DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK
49618. DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT
49619. DB_Z_INFO__FAULT_BEHAVIOR_MASK
49620. DB_Z_INFO__FAULT_BEHAVIOR__SHIFT
49621. DB_Z_INFO__FORMAT_MASK
49622. DB_Z_INFO__FORMAT__SHIFT
49623. DB_Z_INFO__ITERATE_256_MASK
49624. DB_Z_INFO__ITERATE_256__SHIFT
49625. DB_Z_INFO__ITERATE_FLUSH_MASK
49626. DB_Z_INFO__ITERATE_FLUSH__SHIFT
49627. DB_Z_INFO__MAXMIP_MASK
49628. DB_Z_INFO__MAXMIP__SHIFT
49629. DB_Z_INFO__NUM_SAMPLES_MASK
49630. DB_Z_INFO__NUM_SAMPLES__SHIFT
49631. DB_Z_INFO__PARTIALLY_RESIDENT_MASK
49632. DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT
49633. DB_Z_INFO__READ_SIZE_MASK
49634. DB_Z_INFO__READ_SIZE__SHIFT
49635. DB_Z_INFO__RESERVED_FIELD_1_MASK
49636. DB_Z_INFO__RESERVED_FIELD_1__SHIFT
49637. DB_Z_INFO__SW_MODE_MASK
49638. DB_Z_INFO__SW_MODE__SHIFT
49639. DB_Z_INFO__TILE_MODE_INDEX_MASK
49640. DB_Z_INFO__TILE_MODE_INDEX__SHIFT
49641. DB_Z_INFO__TILE_SPLIT_MASK
49642. DB_Z_INFO__TILE_SPLIT__SHIFT
49643. DB_Z_INFO__TILE_SURFACE_ENABLE_MASK
49644. DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT
49645. DB_Z_INFO__ZRANGE_PRECISION_MASK
49646. DB_Z_INFO__ZRANGE_PRECISION__SHIFT
49647. DB_Z_READ_BASE
49648. DB_Z_READ_BASE_HI__BASE_HI_MASK
49649. DB_Z_READ_BASE_HI__BASE_HI__SHIFT
49650. DB_Z_READ_BASE__BASE_256B_MASK
49651. DB_Z_READ_BASE__BASE_256B__SHIFT
49652. DB_Z_WRITE_BASE
49653. DB_Z_WRITE_BASE_HI__BASE_HI_MASK
49654. DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT
49655. DB_Z_WRITE_BASE__BASE_256B_MASK
49656. DB_Z_WRITE_BASE__BASE_256B__SHIFT
49657. DBox
49658. DC
49659. DC21040
49660. DC21040_DID
49661. DC21040_VID
49662. DC21041
49663. DC21041_DID
49664. DC21041_VID
49665. DC21140
49666. DC21140_DID
49667. DC21140_VID
49668. DC21142
49669. DC21143
49670. DC2114x
49671. DC2114x_BRK
49672. DC2114x_DID
49673. DC2114x_VID
49674. DC21285_ARMCSR_BASE
49675. DC21285_BASE
49676. DC21285_DRAM_A0MR
49677. DC21285_DRAM_A1MR
49678. DC21285_DRAM_A2MR
49679. DC21285_DRAM_A3MR
49680. DC21285_FLASH
49681. DC21285_IO
49682. DC21285_OUTBOUND_WRITE_FLUSH
49683. DC21285_PCI_IACK
49684. DC21285_PCI_IO
49685. DC21285_PCI_MEM
49686. DC21285_PCI_TYPE_0_CONFIG
49687. DC21285_PCI_TYPE_1_CONFIG
49688. DC2DC_CONFIG_CMD
49689. DC390_EEPROM_LEN
49690. DC390_EEPROM_READ
49691. DC390_EE_ADAPT_SCSI_ID
49692. DC390_EE_DELAY
49693. DC390_EE_MODE1
49694. DC390_EE_MODE1_EN_DISC
49695. DC390_EE_MODE1_PARITY_CHK
49696. DC390_EE_MODE1_SEND_START
49697. DC390_EE_MODE1_SYNC_NEGO
49698. DC390_EE_MODE1_TCQ
49699. DC390_EE_MODE2
49700. DC390_EE_MODE2_ACTIVE_NEGATION
49701. DC390_EE_MODE2_GREATER_1G
49702. DC390_EE_MODE2_LUN_CHECK
49703. DC390_EE_MODE2_MORE_2DRV
49704. DC390_EE_MODE2_NO_SEEK
49705. DC390_EE_MODE2_RST_SCSI_BUS
49706. DC390_EE_SPEED
49707. DC390_EE_TAG_CMD_NUM
49708. DC395X_BANNER
49709. DC395X_NAME
49710. DC395X_VERSION
49711. DC395x_ENABLE_MSGOUT
49712. DC395x_END_SCAN
49713. DC395x_H
49714. DC395x_LASTPIO
49715. DC395x_LOCK_IO
49716. DC395x_MAX_CAN_QUEUE
49717. DC395x_MAX_CMD_PER_LUN
49718. DC395x_MAX_CMD_QUEUE
49719. DC395x_MAX_QTAGS
49720. DC395x_MAX_RETRIES
49721. DC395x_MAX_SCSI_ID
49722. DC395x_MAX_SG_LISTENTRY
49723. DC395x_MAX_SG_TABLESIZE
49724. DC395x_MAX_SRB_CNT
49725. DC395x_SEL_TIMEOUT
49726. DC395x_UNLOCK_IO
49727. DC395x_read16
49728. DC395x_read32
49729. DC395x_read8
49730. DC395x_write16
49731. DC395x_write32
49732. DC395x_write8
49733. DC8
49734. DC8051_ACCESS_TIMEOUT
49735. DC8051_COMMAND_TIMEOUT
49736. DC8051_DATA_MEM_SIZE
49737. DCA2_TAG_MAP_BYTE0
49738. DCA2_TAG_MAP_BYTE1
49739. DCA2_TAG_MAP_BYTE2
49740. DCA2_TAG_MAP_BYTE3
49741. DCA2_TAG_MAP_BYTE4
49742. DCA3_TAG_MAP_BIT_TO_INV
49743. DCA3_TAG_MAP_BIT_TO_SEL
49744. DCA3_TAG_MAP_LITERAL_VAL
49745. DCACHE
49746. DCACHELINESIZE
49747. DCACHE_ALIAS
49748. DCACHE_ALIASING_POSSIBLE
49749. DCACHE_ALIAS_EQ
49750. DCACHE_ALIAS_MASK
49751. DCACHE_ALIAS_ORDER
49752. DCACHE_AUTODIR_TYPE
49753. DCACHE_CANT_MOUNT
49754. DCACHE_COOKIE
49755. DCACHE_DENTRY_CURSOR
49756. DCACHE_DENTRY_KILLED
49757. DCACHE_DIRECTORY_TYPE
49758. DCACHE_DISCONNECTED
49759. DCACHE_ENABLE
49760. DCACHE_ENCRYPTED_NAME
49761. DCACHE_ENTRY_TYPE
49762. DCACHE_FALLTHRU
49763. DCACHE_FLUSH
49764. DCACHE_FSNOTIFY_PARENT_WATCHED
49765. DCACHE_GENOCIDE
49766. DCACHE_LRU_LIST
49767. DCACHE_MANAGED_DENTRY
49768. DCACHE_MANAGE_TRANSIT
49769. DCACHE_MAX_ADDR
49770. DCACHE_MAY_FREE
49771. DCACHE_MISS_TYPE
49772. DCACHE_MOUNTED
49773. DCACHE_NEED_AUTOMOUNT
49774. DCACHE_NFSFS_RENAMED
49775. DCACHE_NORCU
49776. DCACHE_N_COLORS
49777. DCACHE_OP_COMPARE
49778. DCACHE_OP_DELETE
49779. DCACHE_OP_HASH
49780. DCACHE_OP_PRUNE
49781. DCACHE_OP_REAL
49782. DCACHE_OP_REVALIDATE
49783. DCACHE_OP_WEAK_REVALIDATE
49784. DCACHE_PAR_LOOKUP
49785. DCACHE_REFERENCED
49786. DCACHE_REGULAR_TYPE
49787. DCACHE_SETMASK
49788. DCACHE_SET_MASK
49789. DCACHE_SHRINK_LIST
49790. DCACHE_SIZE
49791. DCACHE_SPECIAL_TYPE
49792. DCACHE_SYMLINK_TYPE
49793. DCACHE_WAY_SHIFT
49794. DCACHE_WAY_SIZE
49795. DCACHE_WHITEOUT_TYPE
49796. DCAC_DMA_CTRL
49797. DCALR
49798. DCAL_BIT
49799. DCAL_CSS_IID_PN
49800. DCAM
49801. DCAMR
49802. DCAMR_UNSET
49803. DCAN_RAM_INIT_BIT
49804. DCAR
49805. DCAR1
49806. DCAR2
49807. DCA_GET_TAG_TWO_ARGS
49808. DCA_H
49809. DCA_IC
49810. DCA_IC_IE
49811. DCA_ID
49812. DCA_PROVIDER_ADD
49813. DCA_PROVIDER_REMOVE
49814. DCA_TAG_MAP_MASK
49815. DCA_TAG_MAP_VALID
49816. DCA_VERSION
49817. DCBF
49818. DCBST
49819. DCBT
49820. DCBTST
49821. DCBT_BOOK3S_STOP_ALL_STREAM_IDS
49822. DCBT_EO
49823. DCBX_APP_CONFIG_TX_ENABLED
49824. DCBX_APP_ENABLED_MASK
49825. DCBX_APP_ENABLED_SHIFT
49826. DCBX_APP_ENTRY_SF_MASK
49827. DCBX_APP_ENTRY_SF_SHIFT
49828. DCBX_APP_ENTRY_VALID
49829. DCBX_APP_ERROR_MASK
49830. DCBX_APP_ERROR_SHIFT
49831. DCBX_APP_MAX_TCS_MASK
49832. DCBX_APP_MAX_TCS_SHIFT
49833. DCBX_APP_NUM_ENTRIES_MASK
49834. DCBX_APP_NUM_ENTRIES_SHIFT
49835. DCBX_APP_PRI_0
49836. DCBX_APP_PRI_1
49837. DCBX_APP_PRI_2
49838. DCBX_APP_PRI_3
49839. DCBX_APP_PRI_4
49840. DCBX_APP_PRI_5
49841. DCBX_APP_PRI_6
49842. DCBX_APP_PRI_7
49843. DCBX_APP_PRI_MAP_MASK
49844. DCBX_APP_PRI_MAP_SHIFT
49845. DCBX_APP_PROTOCOL_ID_MASK
49846. DCBX_APP_PROTOCOL_ID_SHIFT
49847. DCBX_APP_REM_WILLING
49848. DCBX_APP_RX_ERROR
49849. DCBX_APP_SF_DEFAULT
49850. DCBX_APP_SF_ETHTYPE
49851. DCBX_APP_SF_ETH_TYPE
49852. DCBX_APP_SF_IEEE_ETHTYPE
49853. DCBX_APP_SF_IEEE_MASK
49854. DCBX_APP_SF_IEEE_RESERVED
49855. DCBX_APP_SF_IEEE_SHIFT
49856. DCBX_APP_SF_IEEE_TCP_PORT
49857. DCBX_APP_SF_IEEE_TCP_UDP_PORT
49858. DCBX_APP_SF_IEEE_UDP_PORT
49859. DCBX_APP_SF_MASK
49860. DCBX_APP_SF_PORT
49861. DCBX_APP_SF_SHIFT
49862. DCBX_APP_SF_UDP
49863. DCBX_APP_TLV_RX
49864. DCBX_APP_WILLING
49865. DCBX_APP_WILLING_MASK
49866. DCBX_APP_WILLING_SHIFT
49867. DCBX_BW_PG_BITWIDTH
49868. DCBX_CEE_MAX_VERSION_MASK
49869. DCBX_CEE_MAX_VERSION_SHIFT
49870. DCBX_CEE_STRICT_PRIORITY
49871. DCBX_CEE_VERSION_MASK
49872. DCBX_CEE_VERSION_SHIFT
49873. DCBX_COMP_TIMEOUT
49874. DCBX_CONFIG_MAX_APP_PROTOCOL
49875. DCBX_CONFIG_VERSION_CEE
49876. DCBX_CONFIG_VERSION_DISABLED
49877. DCBX_CONFIG_VERSION_IEEE
49878. DCBX_CONFIG_VERSION_MASK
49879. DCBX_CONFIG_VERSION_SHIFT
49880. DCBX_CONFIG_VERSION_STATIC
49881. DCBX_COS_MAX_NUM
49882. DCBX_COS_MAX_NUM_E2
49883. DCBX_COS_MAX_NUM_E3B0
49884. DCBX_DCBX_ENABLED
49885. DCBX_E2E3_MAX_NUM_COS
49886. DCBX_E3B0_MAX_NUM_COS
49887. DCBX_E3B0_MAX_NUM_COS_PORT0
49888. DCBX_E3B0_MAX_NUM_COS_PORT1
49889. DCBX_ETS_CBS_MASK
49890. DCBX_ETS_CBS_SHIFT
49891. DCBX_ETS_CONFIG_TX_ENABLED
49892. DCBX_ETS_ENABLED_MASK
49893. DCBX_ETS_ENABLED_SHIFT
49894. DCBX_ETS_ERROR_MASK
49895. DCBX_ETS_ERROR_SHIFT
49896. DCBX_ETS_MAX_TCS_MASK
49897. DCBX_ETS_MAX_TCS_SHIFT
49898. DCBX_ETS_RECO_TX_ENABLED
49899. DCBX_ETS_RECO_VALID
49900. DCBX_ETS_REM_WILLING
49901. DCBX_ETS_RX_ERROR
49902. DCBX_ETS_TLV_RX
49903. DCBX_ETS_TSA_CBS
49904. DCBX_ETS_TSA_ETS
49905. DCBX_ETS_TSA_STRICT
49906. DCBX_ETS_WILLING
49907. DCBX_ETS_WILLING_MASK
49908. DCBX_ETS_WILLING_SHIFT
49909. DCBX_ILLEGAL_PG
49910. DCBX_INVALID_COS
49911. DCBX_INVALID_COS_BW
49912. DCBX_IS_PFC_PRI_SOME_PAUSE
49913. DCBX_LOCAL_APP_ERROR
49914. DCBX_LOCAL_APP_MISMATCH
49915. DCBX_LOCAL_ETS_ERROR
49916. DCBX_LOCAL_MIB_MAX_TRY_READ
49917. DCBX_LOCAL_PFC_ERROR
49918. DCBX_LOCAL_PFC_MISMATCH
49919. DCBX_MAX_APP_PROTOCOL
49920. DCBX_MAX_BUFFERS
49921. DCBX_MAX_NUM_COS
49922. DCBX_MAX_NUM_PG_BW_ENTRIES
49923. DCBX_MAX_NUM_PRI_PG_ENTRIES
49924. DCBX_MAX_PROTOCOL_TYPE
49925. DCBX_OOO_TC_MASK
49926. DCBX_OOO_TC_SHIFT
49927. DCBX_PFC_CAPS_MASK
49928. DCBX_PFC_CAPS_SHIFT
49929. DCBX_PFC_CONFIG_TX_ENABLED
49930. DCBX_PFC_ENABLED_MASK
49931. DCBX_PFC_ENABLED_SHIFT
49932. DCBX_PFC_ERROR_MASK
49933. DCBX_PFC_ERROR_SHIFT
49934. DCBX_PFC_FLAGS_MASK
49935. DCBX_PFC_FLAGS_SHIFT
49936. DCBX_PFC_MBC_MASK
49937. DCBX_PFC_MBC_SHIFT
49938. DCBX_PFC_PRI_0
49939. DCBX_PFC_PRI_1
49940. DCBX_PFC_PRI_2
49941. DCBX_PFC_PRI_3
49942. DCBX_PFC_PRI_4
49943. DCBX_PFC_PRI_5
49944. DCBX_PFC_PRI_6
49945. DCBX_PFC_PRI_7
49946. DCBX_PFC_PRI_EN_BITMAP_MASK
49947. DCBX_PFC_PRI_EN_BITMAP_PRI_0
49948. DCBX_PFC_PRI_EN_BITMAP_PRI_1
49949. DCBX_PFC_PRI_EN_BITMAP_PRI_2
49950. DCBX_PFC_PRI_EN_BITMAP_PRI_3
49951. DCBX_PFC_PRI_EN_BITMAP_PRI_4
49952. DCBX_PFC_PRI_EN_BITMAP_PRI_5
49953. DCBX_PFC_PRI_EN_BITMAP_PRI_6
49954. DCBX_PFC_PRI_EN_BITMAP_PRI_7
49955. DCBX_PFC_PRI_EN_BITMAP_SHIFT
49956. DCBX_PFC_PRI_GET_NON_PAUSE
49957. DCBX_PFC_PRI_GET_PAUSE
49958. DCBX_PFC_PRI_MASK
49959. DCBX_PFC_PRI_NON_PAUSE_MASK
49960. DCBX_PFC_PRI_PAUSE_MASK
49961. DCBX_PFC_REM_WILLING
49962. DCBX_PFC_RX_ERROR
49963. DCBX_PFC_TLV_RX
49964. DCBX_PFC_WILLING
49965. DCBX_PFC_WILLING_MASK
49966. DCBX_PFC_WILLING_SHIFT
49967. DCBX_PG_BW_GET
49968. DCBX_PG_BW_SET
49969. DCBX_PRI_PG_BITWIDTH
49970. DCBX_PRI_PG_FBITS
49971. DCBX_PRI_PG_GET
49972. DCBX_PRI_PG_SET
49973. DCBX_PROTOCOL_CEE
49974. DCBX_PROTOCOL_ETH
49975. DCBX_PROTOCOL_FCOE
49976. DCBX_PROTOCOL_ISCSI
49977. DCBX_PROTOCOL_PRECEE
49978. DCBX_PROTOCOL_ROCE
49979. DCBX_PROTOCOL_ROCE_V2
49980. DCBX_READ_LOCAL_MIB
49981. DCBX_READ_REMOTE_MIB
49982. DCBX_REMOTE_APP_TLV_NOT_FOUND
49983. DCBX_REMOTE_ETS_RECO_VALID
49984. DCBX_REMOTE_ETS_TLV_NOT_FOUND
49985. DCBX_REMOTE_MIB_ERROR
49986. DCBX_REMOTE_MIB_VALID
49987. DCBX_REMOTE_PFC_TLV_NOT_FOUND
49988. DCBX_STRICT_PRIORITY
49989. DCBX_STRICT_PRI_PG
49990. DCBX_TCP_OOO_K2_4PORT_TC
49991. DCBX_TCP_OOO_TC
49992. DCBX_TLV_DATA_SIZE
49993. DCBX_VERSION_CEE
49994. DCBX_VERSION_IEEE
49995. DCBZ
49996. DCB_ADDR_SHIFT
49997. DCB_APP_ATTR_ID
49998. DCB_APP_ATTR_IDTYPE
49999. DCB_APP_ATTR_MAX
50000. DCB_APP_ATTR_PRIORITY
50001. DCB_APP_ATTR_UNDEFINED
50002. DCB_APP_EVENT
50003. DCB_APP_IDTYPE_ETHTYPE
50004. DCB_APP_IDTYPE_PORTNUM
50005. DCB_ATTR_APP
50006. DCB_ATTR_BCN
50007. DCB_ATTR_CAP
50008. DCB_ATTR_CEE
50009. DCB_ATTR_CEE_APP
50010. DCB_ATTR_CEE_APP_MAX
50011. DCB_ATTR_CEE_APP_TABLE
50012. DCB_ATTR_CEE_APP_UNSPEC
50013. DCB_ATTR_CEE_FEAT
50014. DCB_ATTR_CEE_MAX
50015. DCB_ATTR_CEE_PEER_APP
50016. DCB_ATTR_CEE_PEER_APP_INFO
50017. DCB_ATTR_CEE_PEER_APP_MAX
50018. DCB_ATTR_CEE_PEER_APP_TABLE
50019. DCB_ATTR_CEE_PEER_APP_UNSPEC
50020. DCB_ATTR_CEE_PEER_PFC
50021. DCB_ATTR_CEE_PEER_PG
50022. DCB_ATTR_CEE_PFC
50023. DCB_ATTR_CEE_RX_PG
50024. DCB_ATTR_CEE_TX_PG
50025. DCB_ATTR_CEE_UNSPEC
50026. DCB_ATTR_DCBX
50027. DCB_ATTR_DCB_BUFFER
50028. DCB_ATTR_FEATCFG
50029. DCB_ATTR_IEEE
50030. DCB_ATTR_IEEE_APP
50031. DCB_ATTR_IEEE_APP_MAX
50032. DCB_ATTR_IEEE_APP_TABLE
50033. DCB_ATTR_IEEE_APP_UNSPEC
50034. DCB_ATTR_IEEE_ETS
50035. DCB_ATTR_IEEE_MAX
50036. DCB_ATTR_IEEE_MAXRATE
50037. DCB_ATTR_IEEE_PEER_APP
50038. DCB_ATTR_IEEE_PEER_ETS
50039. DCB_ATTR_IEEE_PEER_PFC
50040. DCB_ATTR_IEEE_PFC
50041. DCB_ATTR_IEEE_QCN
50042. DCB_ATTR_IEEE_QCN_STATS
50043. DCB_ATTR_IEEE_UNSPEC
50044. DCB_ATTR_IFNAME
50045. DCB_ATTR_MAX
50046. DCB_ATTR_NUMTCS
50047. DCB_ATTR_NUM_TC
50048. DCB_ATTR_PERM_HWADDR
50049. DCB_ATTR_PFC_CFG
50050. DCB_ATTR_PFC_STATE
50051. DCB_ATTR_PG_CFG
50052. DCB_ATTR_SET_ALL
50053. DCB_ATTR_STATE
50054. DCB_ATTR_UNDEFINED
50055. DCB_ATTR_VALUE_UNDEFINED
50056. DCB_BCN_ATTR_ALL
50057. DCB_BCN_ATTR_ALPHA
50058. DCB_BCN_ATTR_BCNA_0
50059. DCB_BCN_ATTR_BCNA_1
50060. DCB_BCN_ATTR_BETA
50061. DCB_BCN_ATTR_C
50062. DCB_BCN_ATTR_GD
50063. DCB_BCN_ATTR_GI
50064. DCB_BCN_ATTR_MAX
50065. DCB_BCN_ATTR_RD
50066. DCB_BCN_ATTR_RI
50067. DCB_BCN_ATTR_RMIN
50068. DCB_BCN_ATTR_RP_0
50069. DCB_BCN_ATTR_RP_1
50070. DCB_BCN_ATTR_RP_2
50071. DCB_BCN_ATTR_RP_3
50072. DCB_BCN_ATTR_RP_4
50073. DCB_BCN_ATTR_RP_5
50074. DCB_BCN_ATTR_RP_6
50075. DCB_BCN_ATTR_RP_7
50076. DCB_BCN_ATTR_RP_ALL
50077. DCB_BCN_ATTR_RU
50078. DCB_BCN_ATTR_TD
50079. DCB_BCN_ATTR_TMAX
50080. DCB_BCN_ATTR_UNDEFINED
50081. DCB_BCN_ATTR_W
50082. DCB_BCN_ATTR_WRTT
50083. DCB_BT445
50084. DCB_CAP_ATTR_ALL
50085. DCB_CAP_ATTR_BCN
50086. DCB_CAP_ATTR_DCBX
50087. DCB_CAP_ATTR_GSP
50088. DCB_CAP_ATTR_MAX
50089. DCB_CAP_ATTR_PFC
50090. DCB_CAP_ATTR_PFC_TCS
50091. DCB_CAP_ATTR_PG
50092. DCB_CAP_ATTR_PG_TCS
50093. DCB_CAP_ATTR_UNDEFINED
50094. DCB_CAP_ATTR_UP2TC
50095. DCB_CAP_DCBX_HOST
50096. DCB_CAP_DCBX_LLD_MANAGED
50097. DCB_CAP_DCBX_STATIC
50098. DCB_CAP_DCBX_VER_CEE
50099. DCB_CAP_DCBX_VER_IEEE
50100. DCB_CMAP0
50101. DCB_CMAP1
50102. DCB_CMAP_ALL
50103. DCB_CMD_BCN_GCFG
50104. DCB_CMD_BCN_SCFG
50105. DCB_CMD_CEE_GET
50106. DCB_CMD_GAPP
50107. DCB_CMD_GCAP
50108. DCB_CMD_GDCBX
50109. DCB_CMD_GFEATCFG
50110. DCB_CMD_GNUMTCS
50111. DCB_CMD_GPERM_HWADDR
50112. DCB_CMD_GSTATE
50113. DCB_CMD_IEEE_DEL
50114. DCB_CMD_IEEE_GET
50115. DCB_CMD_IEEE_SET
50116. DCB_CMD_MAX
50117. DCB_CMD_PFC_GCFG
50118. DCB_CMD_PFC_GSTATE
50119. DCB_CMD_PFC_SCFG
50120. DCB_CMD_PFC_SSTATE
50121. DCB_CMD_PGRX_GCFG
50122. DCB_CMD_PGRX_SCFG
50123. DCB_CMD_PGTX_GCFG
50124. DCB_CMD_PGTX_SCFG
50125. DCB_CMD_SAPP
50126. DCB_CMD_SDCBX
50127. DCB_CMD_SET_ALL
50128. DCB_CMD_SFEATCFG
50129. DCB_CMD_SNUMTCS
50130. DCB_CMD_SSTATE
50131. DCB_CMD_UNDEFINED
50132. DCB_CNDD_EDGE
50133. DCB_CNDD_INTERIOR
50134. DCB_CNDD_INTERIOR_READY
50135. DCB_CNDD_RESET
50136. DCB_CONNECTOR_DMS59_0
50137. DCB_CONNECTOR_DMS59_1
50138. DCB_CONNECTOR_DMS59_DP0
50139. DCB_CONNECTOR_DMS59_DP1
50140. DCB_CONNECTOR_DP
50141. DCB_CONNECTOR_DVI_D
50142. DCB_CONNECTOR_DVI_I
50143. DCB_CONNECTOR_HDMI_0
50144. DCB_CONNECTOR_HDMI_1
50145. DCB_CONNECTOR_HDMI_C
50146. DCB_CONNECTOR_LVDS
50147. DCB_CONNECTOR_LVDS_SPWG
50148. DCB_CONNECTOR_NONE
50149. DCB_CONNECTOR_TV_0
50150. DCB_CONNECTOR_TV_1
50151. DCB_CONNECTOR_TV_3
50152. DCB_CONNECTOR_USB_C
50153. DCB_CONNECTOR_VGA
50154. DCB_CONNECTOR_WFD
50155. DCB_CONNECTOR_eDP
50156. DCB_CREDIT_QUANTUM
50157. DCB_CRS_SHIFT
50158. DCB_CSHOLD_SHIFT
50159. DCB_CSSETUP_SHIFT
50160. DCB_CSWIDTH_SHIFT
50161. DCB_CYCLES
50162. DCB_DATAWIDTH_1
50163. DCB_DATAWIDTH_2
50164. DCB_DATAWIDTH_3
50165. DCB_DATAWIDTH_4
50166. DCB_DSCP_ENABLE
50167. DCB_DSCP_ENABLE_MASK
50168. DCB_DSCP_ENABLE_SHIFT
50169. DCB_ENASYNCACK
50170. DCB_ENCRSINC
50171. DCB_ENDATAPACK
50172. DCB_ENSYNCACK
50173. DCB_ERR_BW_GROUP
50174. DCB_ERR_CONFIG
50175. DCB_ERR_LS_BWG_NONZERO
50176. DCB_ERR_LS_BW_NONZERO
50177. DCB_ERR_LS_GS
50178. DCB_ERR_PARAM
50179. DCB_ERR_TC_BW
50180. DCB_ERR_TC_BW_ZERO
50181. DCB_FEATCFG_ADVERTISE
50182. DCB_FEATCFG_ATTR_ALL
50183. DCB_FEATCFG_ATTR_APP
50184. DCB_FEATCFG_ATTR_MAX
50185. DCB_FEATCFG_ATTR_PFC
50186. DCB_FEATCFG_ATTR_PG
50187. DCB_FEATCFG_ATTR_UNDEFINED
50188. DCB_FEATCFG_ENABLE
50189. DCB_FEATCFG_ERROR
50190. DCB_FEATCFG_WILLING
50191. DCB_GPIO_EXT_POWER_LOW
50192. DCB_GPIO_FAN
50193. DCB_GPIO_FAN_SENSE
50194. DCB_GPIO_LOGO_LED_PWM
50195. DCB_GPIO_LOG_DIR
50196. DCB_GPIO_LOG_DIR_IN
50197. DCB_GPIO_LOG_DIR_OUT
50198. DCB_GPIO_LOG_VAL
50199. DCB_GPIO_LOG_VAL_HI
50200. DCB_GPIO_LOG_VAL_LO
50201. DCB_GPIO_PANEL_POWER
50202. DCB_GPIO_POWER_ALERT
50203. DCB_GPIO_THERM_EXT_POWER_EVENT
50204. DCB_GPIO_TVDAC0
50205. DCB_GPIO_TVDAC1
50206. DCB_GPIO_UNUSED
50207. DCB_GPIO_VID0
50208. DCB_GPIO_VID1
50209. DCB_GPIO_VID2
50210. DCB_GPIO_VID3
50211. DCB_GPIO_VID4
50212. DCB_GPIO_VID5
50213. DCB_GPIO_VID6
50214. DCB_GPIO_VID7
50215. DCB_GPIO_VID_PWM
50216. DCB_HW_CHG
50217. DCB_HW_CHG_RST
50218. DCB_I2C_NV04_BIT
50219. DCB_I2C_NV4E_BIT
50220. DCB_I2C_NVIO_AUX
50221. DCB_I2C_NVIO_BIT
50222. DCB_I2C_PMGR
50223. DCB_I2C_UNUSED
50224. DCB_LG3_BDVERS0
50225. DCB_LG3_ICS1562
50226. DCB_LOC_ON_CHIP
50227. DCB_MAX_NUM_CONNECTOR_ENTRIES
50228. DCB_MAX_NUM_ENTRIES
50229. DCB_MAX_NUM_GPIO_ENTRIES
50230. DCB_MAX_NUM_I2C_ENTRIES
50231. DCB_MAX_TSO_SIZE
50232. DCB_NOT_IMPLEMENTED
50233. DCB_NO_HW_CHG
50234. DCB_NUMTCS_ATTR_ALL
50235. DCB_NUMTCS_ATTR_MAX
50236. DCB_NUMTCS_ATTR_PFC
50237. DCB_NUMTCS_ATTR_PG
50238. DCB_NUMTCS_ATTR_UNDEFINED
50239. DCB_OUTPUT_A
50240. DCB_OUTPUT_ANALOG
50241. DCB_OUTPUT_ANY
50242. DCB_OUTPUT_B
50243. DCB_OUTPUT_C
50244. DCB_OUTPUT_DP
50245. DCB_OUTPUT_EOL
50246. DCB_OUTPUT_LVDS
50247. DCB_OUTPUT_TMDS
50248. DCB_OUTPUT_TV
50249. DCB_OUTPUT_UNUSED
50250. DCB_OUTPUT_WFD
50251. DCB_PFC_UP_ATTR_0
50252. DCB_PFC_UP_ATTR_1
50253. DCB_PFC_UP_ATTR_2
50254. DCB_PFC_UP_ATTR_3
50255. DCB_PFC_UP_ATTR_4
50256. DCB_PFC_UP_ATTR_5
50257. DCB_PFC_UP_ATTR_6
50258. DCB_PFC_UP_ATTR_7
50259. DCB_PFC_UP_ATTR_ALL
50260. DCB_PFC_UP_ATTR_MAX
50261. DCB_PFC_UP_ATTR_UNDEFINED
50262. DCB_PG_ATTR_BW_ID_0
50263. DCB_PG_ATTR_BW_ID_1
50264. DCB_PG_ATTR_BW_ID_2
50265. DCB_PG_ATTR_BW_ID_3
50266. DCB_PG_ATTR_BW_ID_4
50267. DCB_PG_ATTR_BW_ID_5
50268. DCB_PG_ATTR_BW_ID_6
50269. DCB_PG_ATTR_BW_ID_7
50270. DCB_PG_ATTR_BW_ID_ALL
50271. DCB_PG_ATTR_BW_ID_MAX
50272. DCB_PG_ATTR_MAX
50273. DCB_PG_ATTR_TC_0
50274. DCB_PG_ATTR_TC_1
50275. DCB_PG_ATTR_TC_2
50276. DCB_PG_ATTR_TC_3
50277. DCB_PG_ATTR_TC_4
50278. DCB_PG_ATTR_TC_5
50279. DCB_PG_ATTR_TC_6
50280. DCB_PG_ATTR_TC_7
50281. DCB_PG_ATTR_TC_ALL
50282. DCB_PG_ATTR_TC_MAX
50283. DCB_PG_ATTR_UNDEFINED
50284. DCB_RESERVED
50285. DCB_RX_CONFIG
50286. DCB_SUCCESS
50287. DCB_TC_ATTR_PARAM_ALL
50288. DCB_TC_ATTR_PARAM_BW_PCT
50289. DCB_TC_ATTR_PARAM_MAX
50290. DCB_TC_ATTR_PARAM_PGID
50291. DCB_TC_ATTR_PARAM_STRICT_PRIO
50292. DCB_TC_ATTR_PARAM_UNDEFINED
50293. DCB_TC_ATTR_PARAM_UP_MAPPING
50294. DCB_TX_CONFIG
50295. DCB_VAB1
50296. DCB_VC2
50297. DCB_VCC1
50298. DCB_XMAP0
50299. DCB_XMAP1
50300. DCB_XMAP_ALL
50301. DCC
50302. DCC2
50303. DCC2_MODIFIED_ENHANCED_DISABLE
50304. DCCE
50305. DCCG_AUDIO_DTO0_CNTL
50306. DCCG_AUDIO_DTO0_LOAD
50307. DCCG_AUDIO_DTO0_MODULE
50308. DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK
50309. DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT
50310. DCCG_AUDIO_DTO0_PHASE
50311. DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK
50312. DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT
50313. DCCG_AUDIO_DTO0_SOURCE_SEL
50314. DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0
50315. DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1
50316. DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2
50317. DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3
50318. DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4
50319. DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5
50320. DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0
50321. DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1
50322. DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2
50323. DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3
50324. DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4
50325. DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5
50326. DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED
50327. DCCG_AUDIO_DTO1_CNTL
50328. DCCG_AUDIO_DTO1_LOAD
50329. DCCG_AUDIO_DTO1_MODULE
50330. DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK
50331. DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT
50332. DCCG_AUDIO_DTO1_PHASE
50333. DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK
50334. DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT
50335. DCCG_AUDIO_DTO1_USE_512FBR_DTO
50336. DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK
50337. DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT
50338. DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK
50339. DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT
50340. DCCG_AUDIO_DTO2_SOURCE_SEL
50341. DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0
50342. DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1
50343. DCCG_AUDIO_DTO_SEL
50344. DCCG_AUDIO_DTO_SELECT
50345. DCCG_AUDIO_DTO_SEL_AUDIO_DTO0
50346. DCCG_AUDIO_DTO_SEL_AUDIO_DTO1
50347. DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO
50348. DCCG_AUDIO_DTO_SOURCE
50349. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK
50350. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT
50351. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK
50352. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT
50353. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK
50354. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT
50355. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK
50356. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT
50357. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK
50358. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT
50359. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK
50360. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT
50361. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK
50362. DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT
50363. DCCG_AUDIO_DTO_USE_128FBR_FOR_DP
50364. DCCG_AUDIO_DTO_USE_512FBR_DTO
50365. DCCG_AUDIO_DTO_USE_512FBR_FOR_DP
50366. DCCG_AUDIO_DTO_WALLCLOCK_RATIO
50367. DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK
50368. DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT
50369. DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK
50370. DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT
50371. DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK
50372. DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT
50373. DCCG_CBUS_ANTIGLITCH_RESETB__P0PLL_CBUS_ANTIGLITCH_RESETB_MASK
50374. DCCG_CBUS_ANTIGLITCH_RESETB__P0PLL_CBUS_ANTIGLITCH_RESETB__SHIFT
50375. DCCG_CBUS_ANTIGLITCH_RESETB__P1PLL_CBUS_ANTIGLITCH_RESETB_MASK
50376. DCCG_CBUS_ANTIGLITCH_RESETB__P1PLL_CBUS_ANTIGLITCH_RESETB__SHIFT
50377. DCCG_CBUS_ANTIGLITCH_RESETB__P2PLL_CBUS_ANTIGLITCH_RESETB_MASK
50378. DCCG_CBUS_ANTIGLITCH_RESETB__P2PLL_CBUS_ANTIGLITCH_RESETB__SHIFT
50379. DCCG_CBUS_ANTIGLITCH_RESETB__P3PLL_CBUS_ANTIGLITCH_RESETB_MASK
50380. DCCG_CBUS_ANTIGLITCH_RESETB__P3PLL_CBUS_ANTIGLITCH_RESETB__SHIFT
50381. DCCG_CBUS_SPARE__P0PLL_CBUS_SPARE_MASK
50382. DCCG_CBUS_SPARE__P0PLL_CBUS_SPARE__SHIFT
50383. DCCG_CBUS_SPARE__P1PLL_CBUS_SPARE_MASK
50384. DCCG_CBUS_SPARE__P1PLL_CBUS_SPARE__SHIFT
50385. DCCG_CBUS_SPARE__P2PLL_CBUS_SPARE_MASK
50386. DCCG_CBUS_SPARE__P2PLL_CBUS_SPARE__SHIFT
50387. DCCG_CBUS_SPARE__P3PLL_CBUS_SPARE_MASK
50388. DCCG_CBUS_SPARE__P3PLL_CBUS_SPARE__SHIFT
50389. DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK
50390. DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT
50391. DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE
50392. DCCG_COMMON_REG_LIST_DCN_BASE
50393. DCCG_DBG_BLOCK_SEL
50394. DCCG_DBG_BLOCK_SEL_DCCG
50395. DCCG_DBG_BLOCK_SEL_PMON
50396. DCCG_DBG_BLOCK_SEL_PMON2
50397. DCCG_DBG_CLOCK_SEL
50398. DCCG_DBG_CLOCK_SEL_AOMCLK0
50399. DCCG_DBG_CLOCK_SEL_AOMCLK1
50400. DCCG_DBG_CLOCK_SEL_AOMCLK2
50401. DCCG_DBG_CLOCK_SEL_BYTECLK
50402. DCCG_DBG_CLOCK_SEL_DACCLK
50403. DCCG_DBG_CLOCK_SEL_DISPCLK
50404. DCCG_DBG_CLOCK_SEL_DPREFCLK
50405. DCCG_DBG_CLOCK_SEL_DSICLK
50406. DCCG_DBG_CLOCK_SEL_DVOCLK
50407. DCCG_DBG_CLOCK_SEL_ESCCLK
50408. DCCG_DBG_CLOCK_SEL_MVPCLK
50409. DCCG_DBG_CLOCK_SEL_REFCLK
50410. DCCG_DBG_CLOCK_SEL_RSRV
50411. DCCG_DBG_CLOCK_SEL_SCLK
50412. DCCG_DBG_CLOCK_SEL_SYMCLKA
50413. DCCG_DBG_CLOCK_SEL_SYMCLKB
50414. DCCG_DBG_CLOCK_SEL_SYMCLKC
50415. DCCG_DBG_CLOCK_SEL_SYMCLKD
50416. DCCG_DBG_CLOCK_SEL_SYMCLKE
50417. DCCG_DBG_CLOCK_SEL_SYMCLKF
50418. DCCG_DBG_CLOCK_SEL_SYMCLKG
50419. DCCG_DBG_CLOCK_SEL_SYMCLKLPA
50420. DCCG_DBG_CLOCK_SEL_SYMCLKLPB
50421. DCCG_DBG_CLOCK_SEL_UNB_DB_CLK
50422. DCCG_DBG_EN
50423. DCCG_DBG_EN_DISABLE
50424. DCCG_DBG_EN_ENABLE
50425. DCCG_DBG_OUT_BLOCK_SEL
50426. DCCG_DBG_OUT_BLOCK_SEL_DCCG
50427. DCCG_DBG_OUT_BLOCK_SEL_DCIO
50428. DCCG_DBG_OUT_BLOCK_SEL_DCO
50429. DCCG_DBG_OUT_BLOCK_SEL_DSI
50430. DCCG_DEEP_COLOR_CNTL
50431. DCCG_DEEP_COLOR_DTO_2_1_RATIO
50432. DCCG_DEEP_COLOR_DTO_3_2_RATIO
50433. DCCG_DEEP_COLOR_DTO_5_4_RATIO
50434. DCCG_DEEP_COLOR_DTO_DISABLE
50435. DCCG_DISP1_SLOW_SELECT
50436. DCCG_DISP1_SLOW_SELECT_MASK
50437. DCCG_DISP1_SLOW_SELECT_SHIFT
50438. DCCG_DISP2_SLOW_SELECT
50439. DCCG_DISP2_SLOW_SELECT_MASK
50440. DCCG_DISP2_SLOW_SELECT_SHIFT
50441. DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK
50442. DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT
50443. DCCG_DISP_SLOW_SELECT_REG
50444. DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK
50445. DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT
50446. DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK
50447. DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT
50448. DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK
50449. DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT
50450. DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK
50451. DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT
50452. DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK
50453. DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT
50454. DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK
50455. DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT
50456. DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK
50457. DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT
50458. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK
50459. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT
50460. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK
50461. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT
50462. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK
50463. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT
50464. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK
50465. DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT
50466. DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK
50467. DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT
50468. DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK
50469. DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK
50470. DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT
50471. DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT
50472. DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK
50473. DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT
50474. DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK
50475. DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT
50476. DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK
50477. DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT
50478. DCCG_FIFO_ERRDET_OVR_DISABLE
50479. DCCG_FIFO_ERRDET_OVR_EN
50480. DCCG_FIFO_ERRDET_OVR_ENABLE
50481. DCCG_FIFO_ERRDET_RESET
50482. DCCG_FIFO_ERRDET_RESET_FORCE
50483. DCCG_FIFO_ERRDET_RESET_NOOP
50484. DCCG_FIFO_ERRDET_STATE
50485. DCCG_FIFO_ERRDET_STATE_CALIBRATION
50486. DCCG_FIFO_ERRDET_STATE_DETECTION
50487. DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK
50488. DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT
50489. DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK
50490. DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT
50491. DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK
50492. DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT
50493. DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK
50494. DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT
50495. DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK
50496. DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT
50497. DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK
50498. DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT
50499. DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK
50500. DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT
50501. DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK
50502. DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT
50503. DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK
50504. DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT
50505. DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK
50506. DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT
50507. DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK
50508. DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT
50509. DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK
50510. DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT
50511. DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK
50512. DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT
50513. DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK
50514. DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT
50515. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK
50516. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT
50517. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK
50518. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT
50519. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK
50520. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT
50521. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK
50522. DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT
50523. DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK
50524. DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT
50525. DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK
50526. DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT
50527. DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK
50528. DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT
50529. DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK
50530. DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT
50531. DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK
50532. DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT
50533. DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK
50534. DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT
50535. DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK
50536. DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT
50537. DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK
50538. DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT
50539. DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK
50540. DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT
50541. DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK
50542. DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT
50543. DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK
50544. DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT
50545. DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK
50546. DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT
50547. DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK
50548. DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT
50549. DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK
50550. DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT
50551. DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK
50552. DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT
50553. DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK
50554. DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT
50555. DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK
50556. DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT
50557. DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK
50558. DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT
50559. DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK
50560. DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT
50561. DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK
50562. DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT
50563. DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK
50564. DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT
50565. DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK
50566. DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT
50567. DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK
50568. DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT
50569. DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK
50570. DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT
50571. DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK
50572. DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT
50573. DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK
50574. DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT
50575. DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK
50576. DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT
50577. DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK
50578. DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT
50579. DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK
50580. DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT
50581. DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK
50582. DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT
50583. DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK
50584. DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT
50585. DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK
50586. DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT
50587. DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK
50588. DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT
50589. DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK
50590. DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT
50591. DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE_MASK
50592. DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE__SHIFT
50593. DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK
50594. DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT
50595. DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK
50596. DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT
50597. DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK
50598. DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT
50599. DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK
50600. DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT
50601. DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK
50602. DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT
50603. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK
50604. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT
50605. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK
50606. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT
50607. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
50608. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
50609. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
50610. DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
50611. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK
50612. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT
50613. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK
50614. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT
50615. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK
50616. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT
50617. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK
50618. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT
50619. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK
50620. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT
50621. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK
50622. DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT
50623. DCCG_MASK_SH_LIST_DCN2
50624. DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK
50625. DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT
50626. DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK
50627. DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT
50628. DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK
50629. DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT
50630. DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK
50631. DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT
50632. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK
50633. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT
50634. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK
50635. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT
50636. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK
50637. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT
50638. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK
50639. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT
50640. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK
50641. DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT
50642. DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK
50643. DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT
50644. DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK
50645. DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT
50646. DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK
50647. DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT
50648. DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK
50649. DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT
50650. DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK
50651. DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT
50652. DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK
50653. DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT
50654. DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK
50655. DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT
50656. DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK
50657. DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT
50658. DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK
50659. DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT
50660. DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK
50661. DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT
50662. DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK
50663. DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT
50664. DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK
50665. DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT
50666. DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK
50667. DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT
50668. DCCG_PERF_CRTC_SELECT
50669. DCCG_PERF_MODE_HSYNC
50670. DCCG_PERF_MODE_HSYNC_NOOP
50671. DCCG_PERF_MODE_HSYNC_START
50672. DCCG_PERF_MODE_VSYNC
50673. DCCG_PERF_MODE_VSYNC_NOOP
50674. DCCG_PERF_MODE_VSYNC_START
50675. DCCG_PERF_OTG_SELECT
50676. DCCG_PERF_RUN
50677. DCCG_PERF_RUN_NOOP
50678. DCCG_PERF_RUN_START
50679. DCCG_PERF_SEL_CRTC0
50680. DCCG_PERF_SEL_CRTC1
50681. DCCG_PERF_SEL_CRTC2
50682. DCCG_PERF_SEL_CRTC3
50683. DCCG_PERF_SEL_CRTC4
50684. DCCG_PERF_SEL_CRTC5
50685. DCCG_PERF_SEL_OTG0
50686. DCCG_PERF_SEL_OTG1
50687. DCCG_PERF_SEL_OTG2
50688. DCCG_PERF_SEL_OTG3
50689. DCCG_PERF_SEL_OTG4
50690. DCCG_PERF_SEL_OTG5
50691. DCCG_PERF_SEL_RESERVED
50692. DCCG_REG_FIELD_LIST
50693. DCCG_REG_LIST_DCN2
50694. DCCG_SF
50695. DCCG_SFI
50696. DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK
50697. DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT
50698. DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK
50699. DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT
50700. DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK
50701. DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT
50702. DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK
50703. DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT
50704. DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK
50705. DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT
50706. DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK
50707. DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT
50708. DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK
50709. DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT
50710. DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK
50711. DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT
50712. DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET_MASK
50713. DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET__SHIFT
50714. DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET_MASK
50715. DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET__SHIFT
50716. DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK
50717. DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT
50718. DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK
50719. DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT
50720. DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK
50721. DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT
50722. DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK
50723. DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT
50724. DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK
50725. DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT
50726. DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK
50727. DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT
50728. DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK
50729. DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT
50730. DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK
50731. DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT
50732. DCCG_SRII
50733. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK
50734. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT
50735. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK
50736. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT
50737. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK
50738. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT
50739. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK
50740. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT
50741. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK
50742. DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT
50743. DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK
50744. DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT
50745. DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK
50746. DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT
50747. DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK
50748. DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT
50749. DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK
50750. DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT
50751. DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK
50752. DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT
50753. DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK
50754. DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT
50755. DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK
50756. DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT
50757. DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK
50758. DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT
50759. DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK
50760. DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT
50761. DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK
50762. DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT
50763. DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK
50764. DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT
50765. DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK
50766. DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT
50767. DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK
50768. DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT
50769. DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK
50770. DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT
50771. DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK
50772. DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT
50773. DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK
50774. DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT
50775. DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK
50776. DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT
50777. DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK
50778. DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT
50779. DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK
50780. DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT
50781. DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK
50782. DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT
50783. DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK
50784. DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT
50785. DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK
50786. DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT
50787. DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK
50788. DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT
50789. DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK
50790. DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT
50791. DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK
50792. DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT
50793. DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE_MASK
50794. DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE__SHIFT
50795. DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE_MASK
50796. DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE__SHIFT
50797. DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK
50798. DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT
50799. DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK
50800. DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT
50801. DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK
50802. DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT
50803. DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK
50804. DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT
50805. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK
50806. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT
50807. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK
50808. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT
50809. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK
50810. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT
50811. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK
50812. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT
50813. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK
50814. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT
50815. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK
50816. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT
50817. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK
50818. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT
50819. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK
50820. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT
50821. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK
50822. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT
50823. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK
50824. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT
50825. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK
50826. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT
50827. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK
50828. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT
50829. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK
50830. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT
50831. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK
50832. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT
50833. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK
50834. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT
50835. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK
50836. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT
50837. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK
50838. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT
50839. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK
50840. DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT
50841. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK
50842. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT
50843. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK
50844. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT
50845. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK
50846. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT
50847. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK
50848. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT
50849. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK
50850. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT
50851. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK
50852. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT
50853. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK
50854. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT
50855. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK
50856. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT
50857. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK
50858. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT
50859. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK
50860. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT
50861. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK
50862. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT
50863. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK
50864. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT
50865. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK
50866. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT
50867. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK
50868. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT
50869. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK
50870. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT
50871. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK
50872. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT
50873. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK
50874. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT
50875. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK
50876. DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT
50877. DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK
50878. DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT
50879. DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK
50880. DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT
50881. DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK
50882. DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT
50883. DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK
50884. DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT
50885. DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK
50886. DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT
50887. DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK
50888. DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT
50889. DCCHECK
50890. DCCLK_DIV_MASK
50891. DCCLK_DIV_MASK_SFT
50892. DCCLK_DIV_SFT
50893. DCCLK_GEN_ON_MASK
50894. DCCLK_GEN_ON_MASK_SFT
50895. DCCLK_GEN_ON_SFT
50896. DCCLK_INV_MASK
50897. DCCLK_INV_MASK_SFT
50898. DCCLK_INV_SFT
50899. DCCLK_PDN_MASK
50900. DCCLK_PDN_MASK_SFT
50901. DCCLK_PDN_SFT
50902. DCCLK_PHASE_SEL_MASK
50903. DCCLK_PHASE_SEL_MASK_SFT
50904. DCCLK_PHASE_SEL_SFT
50905. DCCLK_RESYNC_BYPASS_MASK
50906. DCCLK_RESYNC_BYPASS_MASK_SFT
50907. DCCLK_RESYNC_BYPASS_SFT
50908. DCCPARAMS_DC
50909. DCCPARAMS_DEN
50910. DCCPARAMS_DEN_MASK
50911. DCCPARAMS_HC
50912. DCCPAV_BURST_THRESH
50913. DCCPAV_ECN_MARKED
50914. DCCPAV_MAX_ACKVEC_LEN
50915. DCCPAV_MAX_RUNLEN
50916. DCCPAV_MIN_OPTLEN
50917. DCCPAV_NOT_RECEIVED
50918. DCCPAV_NUM_ACKVECS
50919. DCCPAV_RECEIVED
50920. DCCPAV_RESERVED
50921. DCCPC_CCID2
50922. DCCPC_CCID3
50923. DCCPDIAG_GETSOCK
50924. DCCPF_ACK_RATIO
50925. DCCPF_ACK_RATIO_MAX
50926. DCCPF_ACTIVE_CLOSEREQ
50927. DCCPF_CCID
50928. DCCPF_CLOSED
50929. DCCPF_CLOSING
50930. DCCPF_DATA_CHECKSUM
50931. DCCPF_ECN_INCAPABLE
50932. DCCPF_LISTEN
50933. DCCPF_MAX_CCID_SPECIFIC
50934. DCCPF_MIN_CCID_SPECIFIC
50935. DCCPF_MIN_CSUM_COVER
50936. DCCPF_NEW_SYN_RECV
50937. DCCPF_OPEN
50938. DCCPF_PARTOPEN
50939. DCCPF_REQUESTING
50940. DCCPF_RESERVED
50941. DCCPF_RESPOND
50942. DCCPF_SEND_ACK_VECTOR
50943. DCCPF_SEND_LEV_RATE
50944. DCCPF_SEND_NDP_COUNT
50945. DCCPF_SEQUENCE_WINDOW
50946. DCCPF_SEQ_WMAX
50947. DCCPF_SEQ_WMIN
50948. DCCPF_SHORT_SEQNOS
50949. DCCPF_TIME_WAIT
50950. DCCPO_ACK_VECTOR_0
50951. DCCPO_ACK_VECTOR_1
50952. DCCPO_CHANGE_L
50953. DCCPO_CHANGE_R
50954. DCCPO_CONFIRM_L
50955. DCCPO_CONFIRM_R
50956. DCCPO_ELAPSED_TIME
50957. DCCPO_MANDATORY
50958. DCCPO_MAX
50959. DCCPO_MAX_RESERVED
50960. DCCPO_MAX_RX_CCID_SPECIFIC
50961. DCCPO_MAX_TX_CCID_SPECIFIC
50962. DCCPO_MIN_RESERVED
50963. DCCPO_MIN_RX_CCID_SPECIFIC
50964. DCCPO_MIN_TX_CCID_SPECIFIC
50965. DCCPO_NDP_COUNT
50966. DCCPO_PADDING
50967. DCCPO_TIMESTAMP
50968. DCCPO_TIMESTAMP_ECHO
50969. DCCPQ_POLICY_MAX
50970. DCCPQ_POLICY_PRIO
50971. DCCPQ_POLICY_SIMPLE
50972. DCCP_ACTIVE_CLOSEREQ
50973. DCCP_BUG
50974. DCCP_BUG_ON
50975. DCCP_CLOSED
50976. DCCP_CLOSING
50977. DCCP_CRIT
50978. DCCP_DEC_STATS
50979. DCCP_FALLBACK_RTT
50980. DCCP_FEATNEG_OVERHEAD
50981. DCCP_FEAT_MAX_SP_VALS
50982. DCCP_FEAT_SUPPORTED_MAX
50983. DCCP_INC_STATS
50984. DCCP_LISTEN
50985. DCCP_MAX_OPT_LEN
50986. DCCP_MAX_PACKET_HDR
50987. DCCP_MAX_RESET_CODES
50988. DCCP_MAX_STATES
50989. DCCP_MIB_ABORTFAILED
50990. DCCP_MIB_ABORTONTIMEOUT
50991. DCCP_MIB_ACTIVEOPENS
50992. DCCP_MIB_ATTEMPTFAILS
50993. DCCP_MIB_CURRESTAB
50994. DCCP_MIB_ESTABRESETS
50995. DCCP_MIB_INERRS
50996. DCCP_MIB_INVALIDOPT
50997. DCCP_MIB_MAX
50998. DCCP_MIB_NUM
50999. DCCP_MIB_OPTMANDATORYERROR
51000. DCCP_MIB_OUTDATAGRAMS
51001. DCCP_MIB_OUTRSTS
51002. DCCP_MIB_OUTSEGS
51003. DCCP_MIB_PASSIVEOPENS
51004. DCCP_MIB_TIMEOUTS
51005. DCCP_MSL
51006. DCCP_NEW_SYN_RECV
51007. DCCP_NLATTR_SIZE
51008. DCCP_NR_PKT_TYPES
51009. DCCP_OPEN
51010. DCCP_OPTVAL_MAXLEN
51011. DCCP_PARTOPEN
51012. DCCP_PASSIVE_CLOSE
51013. DCCP_PASSIVE_CLOSEREQ
51014. DCCP_PKT_ACK
51015. DCCP_PKT_CLOSE
51016. DCCP_PKT_CLOSEREQ
51017. DCCP_PKT_DATA
51018. DCCP_PKT_DATAACK
51019. DCCP_PKT_INVALID
51020. DCCP_PKT_REQUEST
51021. DCCP_PKT_RESET
51022. DCCP_PKT_RESPONSE
51023. DCCP_PKT_SYNC
51024. DCCP_PKT_SYNCACK
51025. DCCP_PKT_WITHOUT_ACK_SEQ
51026. DCCP_PRINTK
51027. DCCP_PR_DEBUG
51028. DCCP_REQUESTING
51029. DCCP_RESET_CODE_ABORTED
51030. DCCP_RESET_CODE_AGGRESSION_PENALTY
51031. DCCP_RESET_CODE_BAD_INIT_COOKIE
51032. DCCP_RESET_CODE_BAD_SERVICE_CODE
51033. DCCP_RESET_CODE_CLOSED
51034. DCCP_RESET_CODE_CONNECTION_REFUSED
51035. DCCP_RESET_CODE_MANDATORY_ERROR
51036. DCCP_RESET_CODE_NO_CONNECTION
51037. DCCP_RESET_CODE_OPTION_ERROR
51038. DCCP_RESET_CODE_PACKET_ERROR
51039. DCCP_RESET_CODE_TOO_BUSY
51040. DCCP_RESET_CODE_UNSPECIFIED
51041. DCCP_RESPOND
51042. DCCP_ROLE_CLIENT
51043. DCCP_ROLE_LISTEN
51044. DCCP_ROLE_SERVER
51045. DCCP_ROLE_UNDEFINED
51046. DCCP_RTO_MAX
51047. DCCP_SANE_RTT_MAX
51048. DCCP_SANE_RTT_MIN
51049. DCCP_SCM_MAX
51050. DCCP_SCM_PRIORITY
51051. DCCP_SCM_QPOLICY_MAX
51052. DCCP_SERVICE_CODE_IS_ABSENT
51053. DCCP_SERVICE_INVALID_VALUE
51054. DCCP_SERVICE_LIST_MAX_LEN
51055. DCCP_SINGLE_OPT_MAXLEN
51056. DCCP_SKB_CB
51057. DCCP_SOCKOPT_AVAILABLE_CCIDS
51058. DCCP_SOCKOPT_CCID
51059. DCCP_SOCKOPT_CCID_RX_INFO
51060. DCCP_SOCKOPT_CCID_TX_INFO
51061. DCCP_SOCKOPT_CHANGE_L
51062. DCCP_SOCKOPT_CHANGE_R
51063. DCCP_SOCKOPT_GET_CUR_MPS
51064. DCCP_SOCKOPT_PACKET_SIZE
51065. DCCP_SOCKOPT_QPOLICY_ID
51066. DCCP_SOCKOPT_QPOLICY_TXQLEN
51067. DCCP_SOCKOPT_RECV_CSCOV
51068. DCCP_SOCKOPT_RX_CCID
51069. DCCP_SOCKOPT_SEND_CSCOV
51070. DCCP_SOCKOPT_SERVER_TIMEWAIT
51071. DCCP_SOCKOPT_SERVICE
51072. DCCP_SOCKOPT_TX_CCID
51073. DCCP_TIMEOUT_INIT
51074. DCCP_TIMEWAIT_LEN
51075. DCCP_TIME_WAIT
51076. DCCP_WARN
51077. DCCR
51078. DCCR_CACHE
51079. DCCR_NOCACHE
51080. DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC
51081. DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED
51082. DCC_ADDRESSING_MODE_MASK
51083. DCC_ADDRESSING_MODE_SINGLE_CHANNEL
51084. DCC_CFG_LED_CNTRL
51085. DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK
51086. DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SHIFT
51087. DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK
51088. DCC_CFG_PORT_CONFIG
51089. DCC_CFG_PORT_CONFIG1
51090. DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK
51091. DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT
51092. DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK
51093. DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK
51094. DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT
51095. DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
51096. DCC_CFG_PORT_CONFIG_LINK_STATE_MASK
51097. DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT
51098. DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK
51099. DCC_CFG_PORT_CONFIG_MTU_CAP_MASK
51100. DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT
51101. DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK
51102. DCC_CFG_PORT_MTU_CAP_10240
51103. DCC_CFG_RESET
51104. DCC_CFG_RESET_ENABLE_CCLK_BCC
51105. DCC_CFG_RESET_RESET_8051
51106. DCC_CFG_RESET_RESET_LCB
51107. DCC_CFG_RESET_RESET_RX_FPE
51108. DCC_CFG_RESET_RESET_TX_FPE
51109. DCC_CFG_SC_VL_TABLE_15_0
51110. DCC_CFG_SC_VL_TABLE_15_0_ENTRY0_SHIFT
51111. DCC_CFG_SC_VL_TABLE_15_0_ENTRY10_SHIFT
51112. DCC_CFG_SC_VL_TABLE_15_0_ENTRY11_SHIFT
51113. DCC_CFG_SC_VL_TABLE_15_0_ENTRY12_SHIFT
51114. DCC_CFG_SC_VL_TABLE_15_0_ENTRY13_SHIFT
51115. DCC_CFG_SC_VL_TABLE_15_0_ENTRY14_SHIFT
51116. DCC_CFG_SC_VL_TABLE_15_0_ENTRY15_SHIFT
51117. DCC_CFG_SC_VL_TABLE_15_0_ENTRY1_SHIFT
51118. DCC_CFG_SC_VL_TABLE_15_0_ENTRY2_SHIFT
51119. DCC_CFG_SC_VL_TABLE_15_0_ENTRY3_SHIFT
51120. DCC_CFG_SC_VL_TABLE_15_0_ENTRY4_SHIFT
51121. DCC_CFG_SC_VL_TABLE_15_0_ENTRY5_SHIFT
51122. DCC_CFG_SC_VL_TABLE_15_0_ENTRY6_SHIFT
51123. DCC_CFG_SC_VL_TABLE_15_0_ENTRY7_SHIFT
51124. DCC_CFG_SC_VL_TABLE_15_0_ENTRY8_SHIFT
51125. DCC_CFG_SC_VL_TABLE_15_0_ENTRY9_SHIFT
51126. DCC_CFG_SC_VL_TABLE_31_16
51127. DCC_CFG_SC_VL_TABLE_31_16_ENTRY16_SHIFT
51128. DCC_CFG_SC_VL_TABLE_31_16_ENTRY17_SHIFT
51129. DCC_CFG_SC_VL_TABLE_31_16_ENTRY18_SHIFT
51130. DCC_CFG_SC_VL_TABLE_31_16_ENTRY19_SHIFT
51131. DCC_CFG_SC_VL_TABLE_31_16_ENTRY20_SHIFT
51132. DCC_CFG_SC_VL_TABLE_31_16_ENTRY21_SHIFT
51133. DCC_CFG_SC_VL_TABLE_31_16_ENTRY22_SHIFT
51134. DCC_CFG_SC_VL_TABLE_31_16_ENTRY23_SHIFT
51135. DCC_CFG_SC_VL_TABLE_31_16_ENTRY24_SHIFT
51136. DCC_CFG_SC_VL_TABLE_31_16_ENTRY25_SHIFT
51137. DCC_CFG_SC_VL_TABLE_31_16_ENTRY26_SHIFT
51138. DCC_CFG_SC_VL_TABLE_31_16_ENTRY27_SHIFT
51139. DCC_CFG_SC_VL_TABLE_31_16_ENTRY28_SHIFT
51140. DCC_CFG_SC_VL_TABLE_31_16_ENTRY29_SHIFT
51141. DCC_CFG_SC_VL_TABLE_31_16_ENTRY30_SHIFT
51142. DCC_CFG_SC_VL_TABLE_31_16_ENTRY31_SHIFT
51143. DCC_CHANNEL_XOR_BIT_17
51144. DCC_CHANNEL_XOR_DISABLE
51145. DCC_CSRS
51146. DCC_CT_AUTO
51147. DCC_CT_NONE
51148. DCC_DELAY_RANGE_1
51149. DCC_DELAY_RANGE_2
51150. DCC_DISABLE
51151. DCC_ENABLE
51152. DCC_ERR_DROPPED_PKT_CNT
51153. DCC_ERR_FLG
51154. DCC_ERR_FLG_BAD_CRDT_ACK_ERR_SMASK
51155. DCC_ERR_FLG_BAD_CTRL_DIST_ERR_SMASK
51156. DCC_ERR_FLG_BAD_CTRL_FLIT_ERR_SMASK
51157. DCC_ERR_FLG_BAD_DLID_TARGET_ERR_SMASK
51158. DCC_ERR_FLG_BAD_HEAD_DIST_ERR_SMASK
51159. DCC_ERR_FLG_BAD_L2_ERR_SMASK
51160. DCC_ERR_FLG_BAD_LVER_ERR_SMASK
51161. DCC_ERR_FLG_BAD_MID_TAIL_ERR_SMASK
51162. DCC_ERR_FLG_BAD_PKT_LENGTH_ERR_SMASK
51163. DCC_ERR_FLG_BAD_PREEMPTION_ERR_SMASK
51164. DCC_ERR_FLG_BAD_SC_ERR_SMASK
51165. DCC_ERR_FLG_BAD_TAIL_DIST_ERR_SMASK
51166. DCC_ERR_FLG_BAD_VL_MARKER_ERR_SMASK
51167. DCC_ERR_FLG_CLR
51168. DCC_ERR_FLG_CSR_ACCESS_BLOCKED_HOST_SMASK
51169. DCC_ERR_FLG_CSR_ACCESS_BLOCKED_UC_SMASK
51170. DCC_ERR_FLG_CSR_INVAL_ADDR_SMASK
51171. DCC_ERR_FLG_CSR_PARITY_ERR_SMASK
51172. DCC_ERR_FLG_DLID_ZERO_ERR_SMASK
51173. DCC_ERR_FLG_EN
51174. DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK
51175. DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK
51176. DCC_ERR_FLG_EVENT_CNTR_PARITY_ERR_SMASK
51177. DCC_ERR_FLG_EVENT_CNTR_ROLLOVER_ERR_SMASK
51178. DCC_ERR_FLG_FMCONFIG_ERR_SMASK
51179. DCC_ERR_FLG_FPE_TX_FIFO_OVFLW_ERR_SMASK
51180. DCC_ERR_FLG_FPE_TX_FIFO_UNFLW_ERR_SMASK
51181. DCC_ERR_FLG_LATE_EBP_ERR_SMASK
51182. DCC_ERR_FLG_LATE_LONG_ERR_SMASK
51183. DCC_ERR_FLG_LATE_SHORT_ERR_SMASK
51184. DCC_ERR_FLG_LENGTH_MTU_ERR_SMASK
51185. DCC_ERR_FLG_LINK_ERR_SMASK
51186. DCC_ERR_FLG_MISC_CNTR_ROLLOVER_ERR_SMASK
51187. DCC_ERR_FLG_NONVL15_STATE_ERR_SMASK
51188. DCC_ERR_FLG_PERM_NVL15_ERR_SMASK
51189. DCC_ERR_FLG_PREEMPTIONVL15_ERR_SMASK
51190. DCC_ERR_FLG_PREEMPTION_ERR_SMASK
51191. DCC_ERR_FLG_RCVPORT_ERR_SMASK
51192. DCC_ERR_FLG_RX_BYTE_SHFT_PARITY_ERR_SMASK
51193. DCC_ERR_FLG_RX_CTRL_PARITY_MBE_ERR_SMASK
51194. DCC_ERR_FLG_RX_EARLY_DROP_ERR_SMASK
51195. DCC_ERR_FLG_SLID_ZERO_ERR_SMASK
51196. DCC_ERR_FLG_TX_BYTE_SHFT_PARITY_ERR_SMASK
51197. DCC_ERR_FLG_TX_CTRL_PARITY_ERR_SMASK
51198. DCC_ERR_FLG_TX_CTRL_PARITY_MBE_ERR_SMASK
51199. DCC_ERR_FLG_TX_SC_PARITY_ERR_SMASK
51200. DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK
51201. DCC_ERR_FLG_UNSUP_PKT_TYPE_SMASK
51202. DCC_ERR_FLG_UNSUP_VL_ERR_SMASK
51203. DCC_ERR_FLG_VL15_MULTI_ERR_SMASK
51204. DCC_ERR_FMCONFIG_ERR_CNT
51205. DCC_ERR_INFO_FMCONFIG
51206. DCC_ERR_INFO_PORTRCV
51207. DCC_ERR_INFO_PORTRCV_HDR0
51208. DCC_ERR_INFO_PORTRCV_HDR1
51209. DCC_ERR_INFO_UNCORRECTABLE
51210. DCC_ERR_PORTRCV_ERR_CNT
51211. DCC_ERR_RCVREMOTE_PHY_ERR_CNT
51212. DCC_ERR_UNCORRECTABLE_CNT
51213. DCC_HALF_REQ_DISALBE
51214. DCC_INFO
51215. DCC_MASK
51216. DCC_PRF_PORT_MARK_FECN_CNT
51217. DCC_PRF_PORT_RCV_BECN_CNT
51218. DCC_PRF_PORT_RCV_BUBBLE_CNT
51219. DCC_PRF_PORT_RCV_CORRECTABLE_CNT
51220. DCC_PRF_PORT_RCV_DATA_CNT
51221. DCC_PRF_PORT_RCV_FECN_CNT
51222. DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT
51223. DCC_PRF_PORT_RCV_PKTS_CNT
51224. DCC_PRF_PORT_VL_MARK_FECN_CNT
51225. DCC_PRF_PORT_VL_RCV_BECN_CNT
51226. DCC_PRF_PORT_VL_RCV_BUBBLE_CNT
51227. DCC_PRF_PORT_VL_RCV_DATA_CNT
51228. DCC_PRF_PORT_VL_RCV_FECN_CNT
51229. DCC_PRF_PORT_VL_RCV_PKTS_CNT
51230. DCC_PRF_PORT_XMIT_CORRECTABLE_CNT
51231. DCC_PRF_PORT_XMIT_DATA_CNT
51232. DCC_PRF_PORT_XMIT_MULTICAST_CNT
51233. DCC_PRF_PORT_XMIT_PKTS_CNT
51234. DCC_PRF_RX_FLOW_CRTL_CNT
51235. DCC_PRF_TX_FLOW_CRTL_CNT
51236. DCC_STATUS_RX
51237. DCC_STATUS_TX
51238. DCD
51239. DCDBAS_BIN_ATTR_RW
51240. DCDBAS_DEV_ATTR_RO
51241. DCDBAS_DEV_ATTR_RW
51242. DCDBAS_DEV_ATTR_WO
51243. DCDC1
51244. DCDC2
51245. DCDC3
51246. DCDC4
51247. DCDCCTRL_DCDC1_MODE_MASK
51248. DCDCCTRL_DCDC1_MODE_SHIFT
51249. DCDCCTRL_DCDCCKEXT_MASK
51250. DCDCCTRL_DCDCCKEXT_SHIFT
51251. DCDCCTRL_DCDCCKSYNC_MASK
51252. DCDCCTRL_DCDCCKSYNC_SHIFT
51253. DCDCCTRL_DCDC_MODE_MASK
51254. DCDCCTRL_DCDC_MODE_SHIFT
51255. DCDCCTRL_RAMP_TIME_MASK
51256. DCDCCTRL_RAMP_TIME_SHIFT
51257. DCDCCTRL_RSVD0_MASK
51258. DCDCCTRL_RSVD0_SHIFT
51259. DCDCCTRL_TSTEP0_MASK
51260. DCDCCTRL_TSTEP0_SHIFT
51261. DCDCCTRL_TSTEP1_MASK
51262. DCDCCTRL_TSTEP1_SHIFT
51263. DCDCCTRL_TSTEP2_MASK
51264. DCDCCTRL_TSTEP2_SHIFT
51265. DCDCCTRL_VCON_ENABLE_MASK
51266. DCDCCTRL_VCON_ENABLE_SHIFT
51267. DCDCCTRL_VCON_RANGE0_MASK
51268. DCDCCTRL_VCON_RANGE0_SHIFT
51269. DCDCCTRL_VCON_RANGE1_MASK
51270. DCDCCTRL_VCON_RANGE1_SHIFT
51271. DCDCCTRL_VDD1_PSKIP_MASK
51272. DCDCCTRL_VDD1_PSKIP_SHIFT
51273. DCDCCTRL_VDD2_PSKIP_MASK
51274. DCDCCTRL_VDD2_PSKIP_SHIFT
51275. DCDCCTRL_VIO_PSKIP_MASK
51276. DCDCCTRL_VIO_PSKIP_SHIFT
51277. DCDCDCDC1_EN_SHIFT
51278. DCDCDCDC1_PG_MSK
51279. DCDCDCDC2_EN_SHIFT
51280. DCDCDCDC2_PG_MSK
51281. DCDCDCDC3_EN_SHIFT
51282. DCDCDCDC3_PG_MSK
51283. DCDCDCDC_EN_MASK
51284. DCDCSR
51285. DCDC_AVS_ECO_MASK
51286. DCDC_AVS_ECO_SHIFT
51287. DCDC_AVS_ENABLE_MASK
51288. DCDC_AVS_ENABLE_SHIFT
51289. DCDC_BIAS_VREG0
51290. DCDC_BIAS_VREG1
51291. DCDC_EXTENDED_EN
51292. DCDC_FREQ_TUNE_SET
51293. DCDC_INT
51294. DCDC_LIMIT_MAX_SEL_MASK
51295. DCDC_LIMIT_MAX_SEL_SHIFT
51296. DCDC_LIMIT_RANGE_MASK
51297. DCDC_LIMIT_RANGE_SHIFT
51298. DCDC_LOW_POWER_MODE_MSK_SET
51299. DCDC_OFFSET_EN
51300. DCDC_VDCDC1_SHIFT
51301. DCDC_VDCDC2_SHIFT
51302. DCDC_VDCDC3_SHIFT
51303. DCDC_VDCDC_MASK
51304. DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK
51305. DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT
51306. DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK
51307. DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT
51308. DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK
51309. DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT
51310. DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK
51311. DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT
51312. DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK
51313. DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT
51314. DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK
51315. DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT
51316. DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK
51317. DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT
51318. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK
51319. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT
51320. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK
51321. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT
51322. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK
51323. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT
51324. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK
51325. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT
51326. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK
51327. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT
51328. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK
51329. DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT
51330. DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK
51331. DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT
51332. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK
51333. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT
51334. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK
51335. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT
51336. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK
51337. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT
51338. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK
51339. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT
51340. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK
51341. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT
51342. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK
51343. DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT
51344. DCDEE
51345. DCDEE_MASK
51346. DCDEE_SHIFT
51347. DCDE_DEV_CHANGE
51348. DCDE_DEV_SCAN
51349. DCDIE
51350. DCD_IP
51351. DCD_OFF
51352. DCD_ON
51353. DCD_state
51354. DCE100_RESOURCE_H_
51355. DCE110STRENC_FROM_STRENC
51356. DCE110TG_FROM_TG
51357. DCE110_DIG_FE_SOURCE_SELECT_DIGA
51358. DCE110_DIG_FE_SOURCE_SELECT_DIGB
51359. DCE110_DIG_FE_SOURCE_SELECT_DIGC
51360. DCE110_DIG_FE_SOURCE_SELECT_DIGD
51361. DCE110_DIG_FE_SOURCE_SELECT_DIGE
51362. DCE110_DIG_FE_SOURCE_SELECT_DIGF
51363. DCE110_DIG_FE_SOURCE_SELECT_DIGG
51364. DCE110_DIG_FE_SOURCE_SELECT_INVALID
51365. DCE110_OPP_REG_DCFE
51366. DCE110_OPP_REG_DCP
51367. DCE110_OPP_REG_FMT
51368. DCE110_OPP_REG_MAX
51369. DCE110_SE
51370. DCE112_CLK_SRC_PLL0
51371. DCE112_CLK_SRC_PLL1
51372. DCE112_CLK_SRC_PLL2
51373. DCE112_CLK_SRC_PLL3
51374. DCE112_CLK_SRC_PLL4
51375. DCE112_CLK_SRC_PLL5
51376. DCE112_CLK_SRC_TOTAL
51377. DCE11_DIG_BE_CNTL
51378. DCE11_DIG_FE_CNTL
51379. DCE11_DP_SEC
51380. DCE120_AUD_COMMON_MASK_SH_LIST
51381. DCE120_CLK_SRC_PLL0
51382. DCE120_CLK_SRC_PLL1
51383. DCE120_CLK_SRC_PLL2
51384. DCE120_CLK_SRC_PLL3
51385. DCE120_CLK_SRC_PLL4
51386. DCE120_CLK_SRC_PLL5
51387. DCE120_CLK_SRC_TOTAL
51388. DCE2_HDMI_OFFSET0
51389. DCE2_HDMI_OFFSET1
51390. DCE3_DACA_AUTODETECT_INT_CONTROL
51391. DCE3_DACA_AUTO_DETECT_CONTROL
51392. DCE3_DACB_AUTODETECT_INT_CONTROL
51393. DCE3_DACB_AUTO_DETECT_CONTROL
51394. DCE3_DISP_INTERRUPT_STATUS
51395. DCE3_DISP_INTERRUPT_STATUS_CONTINUE
51396. DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
51397. DCE3_HDMI0_ACR_PACKET_CONTROL
51398. DCE3_HDMI0_AUDIO_CRC_CONTROL
51399. DCE3_HDMI1_AUDIO_PACKET_CONTROL
51400. DCE3_HDMI1_CONTROL
51401. DCE3_HDMI1_STATUS
51402. DCE3_HDMI_OFFSET0
51403. DCE3_HDMI_OFFSET1
51404. DCE3_LVTMA_DATA_SYNCHRONIZATION
51405. DCE41_DENTIST_DISPCLK_CNTL
51406. DCE8_DCCG_AUDIO_DTO1_MODULE
51407. DCE8_DCCG_AUDIO_DTO1_PHASE
51408. DCEAZ_HWID
51409. DCECLOCK_TYPE_DISPLAY_CLOCK
51410. DCECLOCK_TYPE_DPREFCLK
51411. DCEM_PORTSPEED_100G
51412. DCEM_PORTSPEED_10G
51413. DCEM_PORTSPEED_1G
51414. DCEM_PORTSPEED_20G
51415. DCEM_PORTSPEED_25G
51416. DCEM_PORTSPEED_40G
51417. DCEM_PORTSPEED_4x10G
51418. DCEM_PORTSPEED_NONE
51419. DCE_10_0_D_H
51420. DCE_10_0_ENUM_H
51421. DCE_10_0_SH_MASK_H
51422. DCE_11_0_D_H
51423. DCE_11_0_ENUM_H
51424. DCE_11_0_SH_MASK_H
51425. DCE_11_2_D_H
51426. DCE_11_2_ENUM_H
51427. DCE_11_2_SH_MASK_H
51428. DCE_6_0_D_H
51429. DCE_6_0_SH_MASK_H
51430. DCE_8_0_D_H
51431. DCE_8_0_ENUM_H
51432. DCE_8_0_SH_MASK_H
51433. DCE_AUD
51434. DCE_BASE__INST0_SEG0
51435. DCE_BASE__INST0_SEG1
51436. DCE_BASE__INST0_SEG2
51437. DCE_BASE__INST0_SEG3
51438. DCE_BASE__INST0_SEG4
51439. DCE_BASE__INST0_SEG5
51440. DCE_BASE__INST1_SEG0
51441. DCE_BASE__INST1_SEG1
51442. DCE_BASE__INST1_SEG2
51443. DCE_BASE__INST1_SEG3
51444. DCE_BASE__INST1_SEG4
51445. DCE_BASE__INST1_SEG5
51446. DCE_BASE__INST2_SEG0
51447. DCE_BASE__INST2_SEG1
51448. DCE_BASE__INST2_SEG2
51449. DCE_BASE__INST2_SEG3
51450. DCE_BASE__INST2_SEG4
51451. DCE_BASE__INST2_SEG5
51452. DCE_BASE__INST3_SEG0
51453. DCE_BASE__INST3_SEG1
51454. DCE_BASE__INST3_SEG2
51455. DCE_BASE__INST3_SEG3
51456. DCE_BASE__INST3_SEG4
51457. DCE_BASE__INST3_SEG5
51458. DCE_BASE__INST4_SEG0
51459. DCE_BASE__INST4_SEG1
51460. DCE_BASE__INST4_SEG2
51461. DCE_BASE__INST4_SEG3
51462. DCE_BASE__INST4_SEG4
51463. DCE_BASE__INST4_SEG5
51464. DCE_BASE__INST5_SEG0
51465. DCE_BASE__INST5_SEG1
51466. DCE_BASE__INST5_SEG2
51467. DCE_BASE__INST5_SEG3
51468. DCE_BASE__INST5_SEG4
51469. DCE_BASE__INST5_SEG5
51470. DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1
51471. DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2
51472. DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4
51473. DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS
51474. DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK
51475. DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE
51476. DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA
51477. DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK
51478. DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK
51479. DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE
51480. DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN
51481. DCE_CLOCK_TYPE_DISPCLK
51482. DCE_CLOCK_TYPE_DPREFCLK
51483. DCE_CLOCK_TYPE_PIXELCLK
51484. DCE_ENV_DIAG
51485. DCE_ENV_FPGA_MAXIMUS
51486. DCE_ENV_PRODUCTION_DRV
51487. DCE_HWIP
51488. DCE_I2C_DEFAULT_I2C_SW_SPEED
51489. DCE_I2C_TRANSACTION_ACTION_DP_READ
51490. DCE_I2C_TRANSACTION_ACTION_DP_WRITE
51491. DCE_I2C_TRANSACTION_ACTION_I2C_READ
51492. DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT
51493. DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST
51494. DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT
51495. DCE_I2C_TRANSACTION_ACTION_I2C_WRITE
51496. DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT
51497. DCE_I2C_TRANSACTION_ADDRESS_SPACE_DPCD
51498. DCE_I2C_TRANSACTION_ADDRESS_SPACE_I2C
51499. DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2
51500. DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING
51501. DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED
51502. DCE_MASK
51503. DCE_SEL
51504. DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK
51505. DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT
51506. DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK
51507. DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT
51508. DCE_VERSION_10_0
51509. DCE_VERSION_11_0
51510. DCE_VERSION_11_2
51511. DCE_VERSION_11_22
51512. DCE_VERSION_12_0
51513. DCE_VERSION_12_1
51514. DCE_VERSION_8_0
51515. DCE_VERSION_8_1
51516. DCE_VERSION_8_3
51517. DCE_VERSION_MAX
51518. DCE_VERSION_UNKNOWN
51519. DCE_VERSION__MAJOR_VERSION_MASK
51520. DCE_VERSION__MAJOR_VERSION__SHIFT
51521. DCE_VERSION__MINOR_VERSION_MASK
51522. DCE_VERSION__MINOR_VERSION__SHIFT
51523. DCE_VIRTUAL_VBLANK_PERIOD
51524. DCF
51525. DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK
51526. DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT
51527. DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK
51528. DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT
51529. DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK
51530. DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT
51531. DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
51532. DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
51533. DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
51534. DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
51535. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
51536. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
51537. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
51538. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
51539. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
51540. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
51541. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
51542. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
51543. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
51544. DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
51545. DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET_MASK
51546. DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
51547. DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
51548. DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
51549. DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
51550. DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
51551. DCFE0_DCFE_FLUSH__FLUSH_DEEP_MASK
51552. DCFE0_DCFE_FLUSH__FLUSH_DEEP__SHIFT
51553. DCFE0_DCFE_FLUSH__FLUSH_OCCURED_MASK
51554. DCFE0_DCFE_FLUSH__FLUSH_OCCURED__SHIFT
51555. DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
51556. DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
51557. DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
51558. DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
51559. DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
51560. DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
51561. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
51562. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
51563. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
51564. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
51565. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
51566. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
51567. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
51568. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
51569. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
51570. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
51571. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
51572. DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
51573. DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
51574. DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
51575. DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
51576. DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
51577. DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
51578. DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
51579. DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
51580. DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
51581. DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
51582. DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
51583. DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
51584. DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
51585. DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
51586. DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
51587. DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
51588. DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
51589. DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
51590. DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
51591. DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
51592. DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
51593. DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
51594. DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
51595. DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
51596. DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
51597. DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
51598. DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
51599. DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
51600. DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
51601. DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
51602. DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
51603. DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
51604. DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
51605. DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
51606. DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
51607. DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
51608. DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
51609. DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
51610. DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
51611. DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
51612. DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
51613. DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
51614. DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
51615. DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
51616. DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
51617. DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
51618. DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
51619. DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
51620. DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
51621. DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
51622. DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
51623. DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
51624. DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
51625. DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
51626. DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
51627. DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
51628. DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
51629. DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
51630. DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
51631. DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
51632. DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
51633. DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
51634. DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
51635. DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
51636. DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
51637. DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
51638. DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
51639. DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
51640. DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
51641. DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
51642. DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
51643. DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
51644. DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
51645. DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
51646. DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
51647. DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
51648. DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
51649. DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
51650. DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
51651. DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
51652. DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
51653. DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
51654. DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
51655. DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
51656. DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
51657. DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK
51658. DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT
51659. DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK
51660. DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT
51661. DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK
51662. DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT
51663. DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK
51664. DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT
51665. DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK
51666. DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT
51667. DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
51668. DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
51669. DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
51670. DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
51671. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
51672. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
51673. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
51674. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
51675. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
51676. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
51677. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
51678. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
51679. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
51680. DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
51681. DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET_MASK
51682. DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
51683. DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
51684. DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
51685. DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
51686. DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
51687. DCFE1_DCFE_FLUSH__FLUSH_DEEP_MASK
51688. DCFE1_DCFE_FLUSH__FLUSH_DEEP__SHIFT
51689. DCFE1_DCFE_FLUSH__FLUSH_OCCURED_MASK
51690. DCFE1_DCFE_FLUSH__FLUSH_OCCURED__SHIFT
51691. DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
51692. DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
51693. DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
51694. DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
51695. DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
51696. DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
51697. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
51698. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
51699. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
51700. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
51701. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
51702. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
51703. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
51704. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
51705. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
51706. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
51707. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
51708. DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
51709. DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
51710. DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
51711. DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
51712. DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
51713. DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
51714. DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
51715. DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
51716. DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
51717. DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
51718. DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
51719. DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
51720. DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
51721. DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
51722. DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
51723. DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
51724. DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
51725. DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
51726. DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
51727. DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
51728. DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
51729. DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
51730. DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
51731. DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
51732. DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
51733. DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
51734. DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
51735. DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
51736. DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
51737. DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
51738. DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
51739. DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
51740. DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
51741. DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
51742. DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
51743. DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
51744. DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
51745. DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
51746. DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
51747. DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
51748. DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
51749. DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
51750. DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
51751. DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
51752. DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
51753. DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
51754. DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
51755. DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
51756. DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
51757. DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
51758. DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
51759. DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
51760. DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
51761. DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
51762. DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
51763. DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
51764. DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
51765. DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
51766. DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
51767. DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
51768. DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
51769. DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
51770. DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
51771. DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
51772. DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
51773. DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
51774. DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
51775. DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
51776. DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
51777. DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
51778. DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
51779. DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
51780. DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
51781. DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
51782. DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
51783. DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
51784. DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
51785. DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
51786. DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
51787. DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
51788. DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
51789. DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
51790. DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
51791. DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
51792. DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
51793. DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK
51794. DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT
51795. DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK
51796. DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT
51797. DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK
51798. DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT
51799. DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK
51800. DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT
51801. DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK
51802. DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT
51803. DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
51804. DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
51805. DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
51806. DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
51807. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
51808. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
51809. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
51810. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
51811. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
51812. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
51813. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
51814. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
51815. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
51816. DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
51817. DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET_MASK
51818. DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
51819. DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
51820. DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
51821. DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
51822. DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
51823. DCFE2_DCFE_FLUSH__FLUSH_DEEP_MASK
51824. DCFE2_DCFE_FLUSH__FLUSH_DEEP__SHIFT
51825. DCFE2_DCFE_FLUSH__FLUSH_OCCURED_MASK
51826. DCFE2_DCFE_FLUSH__FLUSH_OCCURED__SHIFT
51827. DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
51828. DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
51829. DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
51830. DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
51831. DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
51832. DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
51833. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
51834. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
51835. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
51836. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
51837. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
51838. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
51839. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
51840. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
51841. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
51842. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
51843. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
51844. DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
51845. DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
51846. DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
51847. DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
51848. DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
51849. DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
51850. DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
51851. DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
51852. DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
51853. DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
51854. DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
51855. DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
51856. DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
51857. DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
51858. DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
51859. DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
51860. DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
51861. DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
51862. DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
51863. DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
51864. DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
51865. DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
51866. DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
51867. DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
51868. DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
51869. DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
51870. DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
51871. DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
51872. DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
51873. DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
51874. DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
51875. DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
51876. DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
51877. DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
51878. DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
51879. DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
51880. DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
51881. DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
51882. DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
51883. DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
51884. DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
51885. DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
51886. DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
51887. DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
51888. DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
51889. DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
51890. DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
51891. DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
51892. DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
51893. DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
51894. DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
51895. DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
51896. DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
51897. DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
51898. DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
51899. DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
51900. DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
51901. DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
51902. DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
51903. DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
51904. DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
51905. DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
51906. DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
51907. DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
51908. DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
51909. DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
51910. DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
51911. DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
51912. DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
51913. DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
51914. DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
51915. DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
51916. DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
51917. DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
51918. DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
51919. DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
51920. DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
51921. DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
51922. DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
51923. DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
51924. DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
51925. DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
51926. DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
51927. DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
51928. DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
51929. DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK
51930. DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT
51931. DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK
51932. DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT
51933. DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK
51934. DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT
51935. DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK
51936. DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT
51937. DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK
51938. DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT
51939. DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
51940. DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
51941. DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
51942. DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
51943. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
51944. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
51945. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
51946. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
51947. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
51948. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
51949. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
51950. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
51951. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
51952. DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
51953. DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET_MASK
51954. DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
51955. DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
51956. DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
51957. DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
51958. DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
51959. DCFE3_DCFE_FLUSH__FLUSH_DEEP_MASK
51960. DCFE3_DCFE_FLUSH__FLUSH_DEEP__SHIFT
51961. DCFE3_DCFE_FLUSH__FLUSH_OCCURED_MASK
51962. DCFE3_DCFE_FLUSH__FLUSH_OCCURED__SHIFT
51963. DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
51964. DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
51965. DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
51966. DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
51967. DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
51968. DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
51969. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
51970. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
51971. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
51972. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
51973. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
51974. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
51975. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
51976. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
51977. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
51978. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
51979. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
51980. DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
51981. DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
51982. DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
51983. DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
51984. DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
51985. DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
51986. DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
51987. DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
51988. DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
51989. DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
51990. DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
51991. DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
51992. DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
51993. DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
51994. DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
51995. DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
51996. DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
51997. DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
51998. DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
51999. DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
52000. DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
52001. DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
52002. DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
52003. DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
52004. DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
52005. DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
52006. DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
52007. DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
52008. DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
52009. DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
52010. DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
52011. DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
52012. DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
52013. DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
52014. DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
52015. DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
52016. DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
52017. DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
52018. DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
52019. DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
52020. DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
52021. DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
52022. DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
52023. DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
52024. DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
52025. DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
52026. DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
52027. DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
52028. DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
52029. DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
52030. DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
52031. DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
52032. DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
52033. DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
52034. DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
52035. DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
52036. DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
52037. DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
52038. DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
52039. DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
52040. DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
52041. DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
52042. DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
52043. DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
52044. DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
52045. DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
52046. DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
52047. DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
52048. DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
52049. DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
52050. DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
52051. DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
52052. DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
52053. DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
52054. DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
52055. DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
52056. DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
52057. DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
52058. DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
52059. DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
52060. DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
52061. DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
52062. DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
52063. DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
52064. DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
52065. DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK
52066. DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT
52067. DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK
52068. DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT
52069. DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK
52070. DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT
52071. DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK
52072. DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT
52073. DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK
52074. DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT
52075. DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
52076. DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
52077. DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
52078. DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
52079. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
52080. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
52081. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
52082. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
52083. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
52084. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
52085. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
52086. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
52087. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
52088. DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
52089. DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET_MASK
52090. DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
52091. DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
52092. DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52093. DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52094. DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52095. DCFE4_DCFE_FLUSH__FLUSH_DEEP_MASK
52096. DCFE4_DCFE_FLUSH__FLUSH_DEEP__SHIFT
52097. DCFE4_DCFE_FLUSH__FLUSH_OCCURED_MASK
52098. DCFE4_DCFE_FLUSH__FLUSH_OCCURED__SHIFT
52099. DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
52100. DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
52101. DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
52102. DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
52103. DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
52104. DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
52105. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
52106. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
52107. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
52108. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
52109. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
52110. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
52111. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
52112. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
52113. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
52114. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
52115. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
52116. DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
52117. DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
52118. DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
52119. DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
52120. DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
52121. DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
52122. DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
52123. DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
52124. DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
52125. DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
52126. DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
52127. DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
52128. DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
52129. DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
52130. DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
52131. DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
52132. DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
52133. DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
52134. DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
52135. DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
52136. DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
52137. DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
52138. DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
52139. DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
52140. DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
52141. DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
52142. DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
52143. DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
52144. DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
52145. DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
52146. DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
52147. DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
52148. DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
52149. DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
52150. DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
52151. DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
52152. DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
52153. DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
52154. DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
52155. DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
52156. DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
52157. DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
52158. DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
52159. DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
52160. DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
52161. DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
52162. DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
52163. DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
52164. DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
52165. DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
52166. DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
52167. DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
52168. DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
52169. DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
52170. DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
52171. DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
52172. DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
52173. DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
52174. DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
52175. DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
52176. DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
52177. DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
52178. DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
52179. DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
52180. DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
52181. DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
52182. DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
52183. DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
52184. DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
52185. DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
52186. DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
52187. DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
52188. DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
52189. DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
52190. DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
52191. DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
52192. DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
52193. DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
52194. DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
52195. DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
52196. DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
52197. DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
52198. DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
52199. DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
52200. DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
52201. DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK
52202. DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT
52203. DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK
52204. DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT
52205. DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK
52206. DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT
52207. DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK
52208. DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT
52209. DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK
52210. DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT
52211. DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
52212. DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
52213. DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
52214. DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
52215. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
52216. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
52217. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
52218. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
52219. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
52220. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
52221. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
52222. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
52223. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
52224. DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
52225. DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET_MASK
52226. DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
52227. DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
52228. DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52229. DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52230. DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52231. DCFE5_DCFE_FLUSH__FLUSH_DEEP_MASK
52232. DCFE5_DCFE_FLUSH__FLUSH_DEEP__SHIFT
52233. DCFE5_DCFE_FLUSH__FLUSH_OCCURED_MASK
52234. DCFE5_DCFE_FLUSH__FLUSH_OCCURED__SHIFT
52235. DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
52236. DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
52237. DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
52238. DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
52239. DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
52240. DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
52241. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
52242. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
52243. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
52244. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
52245. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
52246. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
52247. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
52248. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
52249. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
52250. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
52251. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
52252. DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
52253. DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
52254. DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
52255. DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
52256. DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
52257. DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
52258. DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
52259. DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
52260. DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
52261. DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
52262. DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
52263. DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
52264. DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
52265. DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
52266. DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
52267. DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
52268. DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
52269. DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
52270. DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
52271. DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
52272. DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
52273. DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
52274. DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
52275. DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
52276. DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
52277. DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
52278. DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
52279. DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
52280. DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
52281. DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
52282. DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
52283. DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
52284. DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
52285. DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
52286. DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
52287. DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
52288. DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
52289. DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
52290. DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
52291. DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
52292. DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
52293. DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
52294. DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
52295. DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
52296. DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
52297. DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
52298. DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
52299. DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
52300. DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
52301. DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
52302. DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
52303. DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
52304. DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
52305. DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
52306. DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
52307. DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
52308. DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
52309. DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
52310. DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
52311. DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
52312. DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
52313. DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
52314. DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
52315. DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
52316. DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
52317. DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
52318. DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
52319. DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
52320. DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
52321. DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
52322. DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
52323. DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
52324. DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
52325. DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
52326. DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
52327. DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
52328. DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
52329. DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
52330. DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
52331. DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
52332. DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
52333. DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
52334. DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
52335. DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
52336. DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
52337. DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK
52338. DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT
52339. DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK
52340. DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT
52341. DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK
52342. DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT
52343. DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK
52344. DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT
52345. DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK
52346. DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT
52347. DCFESR_CX_CLR
52348. DCFESR_CX_DONE
52349. DCFESR_CX_EMP
52350. DCFESR_CX_STL
52351. DCFESR_FIFO_EMPTY
52352. DCFESR_TST_PKDONE
52353. DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK
52354. DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
52355. DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE_MASK
52356. DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT
52357. DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK
52358. DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT
52359. DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK
52360. DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT
52361. DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK
52362. DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT
52363. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK
52364. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT
52365. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK
52366. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT
52367. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK
52368. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT
52369. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK
52370. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT
52371. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK
52372. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT
52373. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK
52374. DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT
52375. DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK
52376. DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT
52377. DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK
52378. DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52379. DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52380. DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52381. DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP_MASK
52382. DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT
52383. DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK
52384. DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT
52385. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK
52386. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT
52387. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK
52388. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT
52389. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK
52390. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT
52391. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK
52392. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT
52393. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK
52394. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT
52395. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK
52396. DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT
52397. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK
52398. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT
52399. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK
52400. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT
52401. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK
52402. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT
52403. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK
52404. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT
52405. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK
52406. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT
52407. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK
52408. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT
52409. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK
52410. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT
52411. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK
52412. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT
52413. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK
52414. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT
52415. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK
52416. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT
52417. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK
52418. DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT
52419. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK
52420. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT
52421. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK
52422. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT
52423. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK
52424. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT
52425. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK
52426. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT
52427. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK
52428. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT
52429. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK
52430. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT
52431. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK
52432. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT
52433. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK
52434. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT
52435. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK
52436. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT
52437. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK
52438. DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT
52439. DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK
52440. DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT
52441. DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK
52442. DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52443. DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52444. DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52445. DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP_MASK
52446. DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT
52447. DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK
52448. DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT
52449. DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK
52450. DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT
52451. DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK
52452. DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
52453. DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK
52454. DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT
52455. DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK
52456. DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT
52457. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK
52458. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT
52459. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK
52460. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT
52461. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK
52462. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT
52463. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK
52464. DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT
52465. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK
52466. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT
52467. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK
52468. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT
52469. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK
52470. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT
52471. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK
52472. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT
52473. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK
52474. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT
52475. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK
52476. DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT
52477. DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK
52478. DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT
52479. DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK
52480. DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT
52481. DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK
52482. DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT
52483. DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK
52484. DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT
52485. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK
52486. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT
52487. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK
52488. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT
52489. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK
52490. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT
52491. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK
52492. DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT
52493. DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK
52494. DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT
52495. DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK
52496. DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT
52497. DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK
52498. DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT
52499. DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK
52500. DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
52501. DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK
52502. DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT
52503. DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK
52504. DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT
52505. DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK
52506. DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT
52507. DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK
52508. DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT
52509. DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK
52510. DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT
52511. DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK
52512. DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT
52513. DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK
52514. DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT
52515. DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS_MASK
52516. DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS__SHIFT
52517. DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK
52518. DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT
52519. DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK
52520. DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT
52521. DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA_MASK
52522. DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA__SHIFT
52523. DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE_MASK
52524. DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE__SHIFT
52525. DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK
52526. DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
52527. DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE_MASK
52528. DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT
52529. DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE_MASK
52530. DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE__SHIFT
52531. DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK
52532. DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT
52533. DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK
52534. DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT
52535. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK
52536. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT
52537. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK
52538. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT
52539. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK
52540. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT
52541. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK
52542. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT
52543. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK
52544. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT
52545. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK
52546. DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT
52547. DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK
52548. DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT
52549. DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK
52550. DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52551. DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52552. DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52553. DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP_MASK
52554. DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT
52555. DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK
52556. DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT
52557. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK
52558. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT
52559. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK
52560. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT
52561. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK
52562. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT
52563. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK
52564. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT
52565. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK
52566. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT
52567. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK
52568. DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT
52569. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK
52570. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT
52571. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK
52572. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT
52573. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK
52574. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT
52575. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK
52576. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT
52577. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK
52578. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT
52579. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK
52580. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT
52581. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK
52582. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT
52583. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK
52584. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT
52585. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK
52586. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT
52587. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK
52588. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT
52589. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK
52590. DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT
52591. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK
52592. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT
52593. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK
52594. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT
52595. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK
52596. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT
52597. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK
52598. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT
52599. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK
52600. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT
52601. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK
52602. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT
52603. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK
52604. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT
52605. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK
52606. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT
52607. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK
52608. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT
52609. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK
52610. DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT
52611. DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK
52612. DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT
52613. DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK
52614. DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52615. DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52616. DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52617. DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP_MASK
52618. DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT
52619. DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK
52620. DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT
52621. DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK
52622. DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT
52623. DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK
52624. DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
52625. DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK
52626. DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT
52627. DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK
52628. DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT
52629. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK
52630. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT
52631. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK
52632. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT
52633. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK
52634. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT
52635. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK
52636. DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT
52637. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK
52638. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT
52639. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK
52640. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT
52641. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK
52642. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT
52643. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK
52644. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT
52645. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK
52646. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT
52647. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK
52648. DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT
52649. DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK
52650. DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT
52651. DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK
52652. DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT
52653. DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK
52654. DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT
52655. DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK
52656. DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT
52657. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK
52658. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT
52659. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK
52660. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT
52661. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK
52662. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT
52663. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK
52664. DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT
52665. DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK
52666. DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT
52667. DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK
52668. DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT
52669. DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK
52670. DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT
52671. DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK
52672. DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
52673. DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK
52674. DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT
52675. DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK
52676. DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT
52677. DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK
52678. DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT
52679. DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK
52680. DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT
52681. DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK
52682. DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT
52683. DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON_MASK
52684. DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON__SHIFT
52685. DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE_MASK
52686. DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE__SHIFT
52687. DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE_MASK
52688. DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE__SHIFT
52689. DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS_MASK
52690. DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS__SHIFT
52691. DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK
52692. DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT
52693. DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK
52694. DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT
52695. DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK
52696. DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT
52697. DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK
52698. DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT
52699. DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK
52700. DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT
52701. DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK
52702. DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT
52703. DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK
52704. DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT
52705. DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK
52706. DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT
52707. DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK
52708. DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT
52709. DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK
52710. DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52711. DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52712. DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52713. DCFEV_C_FLUSH__FLUSH_DEEP_MASK
52714. DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT
52715. DCFEV_C_FLUSH__FLUSH_OCCURED_MASK
52716. DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT
52717. DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK
52718. DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT
52719. DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK
52720. DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT
52721. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK
52722. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT
52723. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK
52724. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT
52725. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK
52726. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT
52727. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK
52728. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT
52729. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK
52730. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT
52731. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK
52732. DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT
52733. DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK
52734. DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT
52735. DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK
52736. DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT
52737. DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK
52738. DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT
52739. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK
52740. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT
52741. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK
52742. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT
52743. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK
52744. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT
52745. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK
52746. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT
52747. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK
52748. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT
52749. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK
52750. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT
52751. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK
52752. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT
52753. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK
52754. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT
52755. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK
52756. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT
52757. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK
52758. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT
52759. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK
52760. DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT
52761. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK
52762. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT
52763. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK
52764. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT
52765. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK
52766. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT
52767. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK
52768. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT
52769. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK
52770. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT
52771. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK
52772. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT
52773. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK
52774. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT
52775. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK
52776. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT
52777. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK
52778. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT
52779. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK
52780. DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT
52781. DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK
52782. DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT
52783. DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK
52784. DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52785. DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52786. DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52787. DCFEV_L_FLUSH__FLUSH_DEEP_MASK
52788. DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT
52789. DCFEV_L_FLUSH__FLUSH_OCCURED_MASK
52790. DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT
52791. DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK
52792. DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT
52793. DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK
52794. DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT
52795. DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK
52796. DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT
52797. DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK
52798. DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT
52799. DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK
52800. DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT
52801. DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK
52802. DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT
52803. DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK
52804. DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT
52805. DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK
52806. DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT
52807. DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK
52808. DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT
52809. DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK
52810. DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT
52811. DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK
52812. DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT
52813. DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK
52814. DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT
52815. DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK
52816. DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT
52817. DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK
52818. DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT
52819. DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK
52820. DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT
52821. DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK
52822. DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT
52823. DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK
52824. DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT
52825. DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK
52826. DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT
52827. DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK
52828. DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT
52829. DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK
52830. DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT
52831. DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK
52832. DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT
52833. DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK
52834. DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT
52835. DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK
52836. DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT
52837. DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK
52838. DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT
52839. DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK
52840. DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT
52841. DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK
52842. DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
52843. DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK
52844. DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT
52845. DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK
52846. DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT
52847. DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK
52848. DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT
52849. DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK
52850. DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT
52851. DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK
52852. DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT
52853. DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK
52854. DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT
52855. DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK
52856. DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT
52857. DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK
52858. DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT
52859. DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE_MASK
52860. DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE__SHIFT
52861. DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK
52862. DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT
52863. DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK
52864. DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT
52865. DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK
52866. DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT
52867. DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK
52868. DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT
52869. DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK
52870. DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT
52871. DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK
52872. DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT
52873. DCFE_DBG_SEL__DCFE_DBG_SEL_MASK
52874. DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT
52875. DCFE_FLUSH__ALL_MC_REQ_RET_MASK
52876. DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT
52877. DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK
52878. DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT
52879. DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK
52880. DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT
52881. DCFE_FLUSH__FLUSH_DEEP_MASK
52882. DCFE_FLUSH__FLUSH_DEEP__SHIFT
52883. DCFE_FLUSH__FLUSH_OCCURED_MASK
52884. DCFE_FLUSH__FLUSH_OCCURED__SHIFT
52885. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK
52886. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS__SHIFT
52887. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE_MASK
52888. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
52889. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK
52890. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT
52891. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK
52892. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT
52893. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK
52894. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT
52895. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK
52896. DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT
52897. DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK
52898. DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT
52899. DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK
52900. DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT
52901. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK
52902. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT
52903. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK
52904. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT
52905. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK
52906. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT
52907. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK
52908. DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT
52909. DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK
52910. DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT
52911. DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK
52912. DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT
52913. DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK
52914. DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT
52915. DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK
52916. DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT
52917. DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK
52918. DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT
52919. DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK
52920. DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT
52921. DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK
52922. DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT
52923. DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK
52924. DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT
52925. DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK
52926. DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT
52927. DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK
52928. DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT
52929. DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK
52930. DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT
52931. DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK
52932. DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT
52933. DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK
52934. DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT
52935. DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK
52936. DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT
52937. DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK
52938. DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT
52939. DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK
52940. DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT
52941. DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK
52942. DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT
52943. DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK
52944. DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT
52945. DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK
52946. DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT
52947. DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK
52948. DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT
52949. DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK
52950. DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT
52951. DCFE_MEM_PWR_CTRL_REG_BASE
52952. DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK
52953. DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT
52954. DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK
52955. DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT
52956. DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK
52957. DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT
52958. DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK
52959. DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT
52960. DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK
52961. DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT
52962. DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK
52963. DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT
52964. DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK
52965. DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT
52966. DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK
52967. DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT
52968. DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK
52969. DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT
52970. DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK
52971. DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT
52972. DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK
52973. DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT
52974. DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK
52975. DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT
52976. DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK
52977. DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT
52978. DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK
52979. DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT
52980. DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK
52981. DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT
52982. DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK
52983. DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT
52984. DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK
52985. DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT
52986. DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK
52987. DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT
52988. DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK
52989. DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT
52990. DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK
52991. DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT
52992. DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK
52993. DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT
52994. DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK
52995. DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT
52996. DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK
52997. DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT
52998. DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK
52999. DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT
53000. DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK
53001. DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT
53002. DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK
53003. DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT
53004. DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK
53005. DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT
53006. DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK
53007. DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT
53008. DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK
53009. DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT
53010. DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK
53011. DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT
53012. DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK
53013. DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT
53014. DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK
53015. DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT
53016. DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK
53017. DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT
53018. DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK
53019. DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT
53020. DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK
53021. DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT
53022. DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET_MASK
53023. DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET__SHIFT
53024. DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK
53025. DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT
53026. DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK
53027. DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT
53028. DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK
53029. DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT
53030. DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK
53031. DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT
53032. DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK
53033. DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT
53034. DCFG
53035. DCFG_CCSR_SCRATCHRW1
53036. DCFG_DESCDMA_EN
53037. DCFG_DEVADDR
53038. DCFG_DEVADDR_LIMIT
53039. DCFG_DEVADDR_MASK
53040. DCFG_DEVADDR_SHIFT
53041. DCFG_DEVSPD_FS
53042. DCFG_DEVSPD_FS48
53043. DCFG_DEVSPD_HS
53044. DCFG_DEVSPD_LS
53045. DCFG_DEVSPD_MASK
53046. DCFG_DEVSPD_SHIFT
53047. DCFG_EPMISCNT
53048. DCFG_EPMISCNT_LIMIT
53049. DCFG_EPMISCNT_MASK
53050. DCFG_EPMISCNT_SHIFT
53051. DCFG_IPG_ISOC_SUPPORDED
53052. DCFG_LATMEN
53053. DCFG_MRWAIT
53054. DCFG_MWWAIT
53055. DCFG_NZ_STS_OUT_HSHK
53056. DCFG_PERDIS
53057. DCFG_PERFRINT
53058. DCFG_PERFRINT_LIMIT
53059. DCFG_PERFRINT_MASK
53060. DCFG_PERFRINT_SHIFT
53061. DCFG_XMRL
53062. DCFG_XMRM
53063. DCFG_XMWI
53064. DCFM
53065. DCF_DEV_CHANGE
53066. DCF_DEV_SCAN
53067. DCF_POLLED
53068. DCHANGE
53069. DCHCTL
53070. DCHDFIFDEBUG
53071. DCHR0
53072. DCHR1
53073. DCHREVISION
53074. DCHREVISION_MASK
53075. DCHSTATUS
53076. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK
53077. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT
53078. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK
53079. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT
53080. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK
53081. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT
53082. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK
53083. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT
53084. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK
53085. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT
53086. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK
53087. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT
53088. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK
53089. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT
53090. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK
53091. DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT
53092. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK
53093. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT
53094. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK
53095. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT
53096. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK
53097. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT
53098. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK
53099. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT
53100. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK
53101. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT
53102. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK
53103. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT
53104. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK
53105. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT
53106. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK
53107. DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT
53108. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK
53109. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT
53110. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK
53111. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT
53112. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK
53113. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT
53114. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK
53115. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT
53116. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK
53117. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT
53118. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK
53119. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT
53120. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK
53121. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT
53122. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK
53123. DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT
53124. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK
53125. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT
53126. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK
53127. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT
53128. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK
53129. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT
53130. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK
53131. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT
53132. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK
53133. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT
53134. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK
53135. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT
53136. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK
53137. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT
53138. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK
53139. DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT
53140. DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK
53141. DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT
53142. DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK
53143. DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT
53144. DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK
53145. DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT
53146. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK
53147. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT
53148. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK
53149. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT
53150. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE_MASK
53151. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE__SHIFT
53152. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK
53153. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT
53154. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK
53155. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT
53156. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK
53157. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT
53158. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK
53159. DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT
53160. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK
53161. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT
53162. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK
53163. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT
53164. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK
53165. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT
53166. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK
53167. DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT
53168. DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK
53169. DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT
53170. DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK
53171. DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT
53172. DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK
53173. DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT
53174. DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK
53175. DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT
53176. DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK
53177. DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT
53178. DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK
53179. DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT
53180. DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK
53181. DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT
53182. DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK
53183. DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT
53184. DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK
53185. DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT
53186. DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK
53187. DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT
53188. DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK
53189. DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT
53190. DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK
53191. DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT
53192. DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK
53193. DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT
53194. DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK
53195. DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT
53196. DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK
53197. DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT
53198. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_MASK
53199. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__SHIFT
53200. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_MASK
53201. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__SHIFT
53202. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_MASK
53203. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__SHIFT
53204. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_MASK
53205. DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__SHIFT
53206. DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK
53207. DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT
53208. DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK
53209. DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT
53210. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK
53211. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT
53212. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK
53213. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT
53214. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK
53215. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT
53216. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK
53217. DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT
53218. DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK
53219. DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT
53220. DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK
53221. DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT
53222. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK_MASK
53223. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK__SHIFT
53224. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK
53225. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT
53226. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK
53227. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT
53228. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK
53229. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT
53230. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK
53231. DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT
53232. DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK
53233. DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT
53234. DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK
53235. DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT
53236. DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK
53237. DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT
53238. DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK
53239. DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT
53240. DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK
53241. DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT
53242. DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK
53243. DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT
53244. DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK
53245. DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT
53246. DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK
53247. DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT
53248. DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK
53249. DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT
53250. DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK
53251. DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT
53252. DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK
53253. DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT
53254. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK
53255. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT
53256. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK
53257. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT
53258. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK
53259. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT
53260. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK
53261. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT
53262. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK
53263. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT
53264. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK
53265. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT
53266. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK
53267. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT
53268. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB_MASK
53269. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB__SHIFT
53270. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK
53271. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT
53272. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK
53273. DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT
53274. DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK
53275. DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT
53276. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK
53277. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT
53278. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK
53279. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT
53280. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK
53281. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK
53282. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT
53283. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK
53284. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT
53285. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK
53286. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT
53287. DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT
53288. DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK
53289. DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT
53290. DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK
53291. DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT
53292. DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK
53293. DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT
53294. DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK
53295. DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT
53296. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK
53297. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT
53298. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK
53299. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT
53300. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK
53301. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT
53302. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK
53303. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT
53304. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK
53305. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK
53306. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT
53307. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT
53308. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK
53309. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT
53310. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK
53311. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT
53312. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK
53313. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT
53314. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK
53315. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT
53316. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK
53317. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT
53318. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_MASK
53319. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_RESET_MASK
53320. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_RESET__SHIFT
53321. DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL__SHIFT
53322. DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK
53323. DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT
53324. DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK
53325. DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT
53326. DCHUBBUB_RET_PATH_DCC_CFG10_0__DCC_CFG10_CONSTANT_0_MASK
53327. DCHUBBUB_RET_PATH_DCC_CFG10_0__DCC_CFG10_CONSTANT_0__SHIFT
53328. DCHUBBUB_RET_PATH_DCC_CFG10_1__DCC_CFG10_CONSTANT_1_MASK
53329. DCHUBBUB_RET_PATH_DCC_CFG10_1__DCC_CFG10_CONSTANT_1__SHIFT
53330. DCHUBBUB_RET_PATH_DCC_CFG11_0__DCC_CFG11_CONSTANT_0_MASK
53331. DCHUBBUB_RET_PATH_DCC_CFG11_0__DCC_CFG11_CONSTANT_0__SHIFT
53332. DCHUBBUB_RET_PATH_DCC_CFG11_1__DCC_CFG11_CONSTANT_1_MASK
53333. DCHUBBUB_RET_PATH_DCC_CFG11_1__DCC_CFG11_CONSTANT_1__SHIFT
53334. DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK
53335. DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT
53336. DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK
53337. DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT
53338. DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK
53339. DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT
53340. DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK
53341. DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT
53342. DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK
53343. DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT
53344. DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK
53345. DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT
53346. DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK
53347. DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT
53348. DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK
53349. DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT
53350. DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK
53351. DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT
53352. DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK
53353. DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT
53354. DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK
53355. DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT
53356. DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK
53357. DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT
53358. DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK
53359. DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT
53360. DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK
53361. DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT
53362. DCHUBBUB_RET_PATH_DCC_CFG8_0__DCC_CFG8_CONSTANT_0_MASK
53363. DCHUBBUB_RET_PATH_DCC_CFG8_0__DCC_CFG8_CONSTANT_0__SHIFT
53364. DCHUBBUB_RET_PATH_DCC_CFG8_1__DCC_CFG8_CONSTANT_1_MASK
53365. DCHUBBUB_RET_PATH_DCC_CFG8_1__DCC_CFG8_CONSTANT_1__SHIFT
53366. DCHUBBUB_RET_PATH_DCC_CFG9_0__DCC_CFG9_CONSTANT_0_MASK
53367. DCHUBBUB_RET_PATH_DCC_CFG9_0__DCC_CFG9_CONSTANT_0__SHIFT
53368. DCHUBBUB_RET_PATH_DCC_CFG9_1__DCC_CFG9_CONSTANT_1_MASK
53369. DCHUBBUB_RET_PATH_DCC_CFG9_1__DCC_CFG9_CONSTANT_1__SHIFT
53370. DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK
53371. DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT
53372. DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK
53373. DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT
53374. DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK
53375. DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT
53376. DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK
53377. DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT
53378. DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE_MASK
53379. DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE__SHIFT
53380. DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT_MASK
53381. DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT__SHIFT
53382. DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP_MASK
53383. DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP__SHIFT
53384. DCHUBBUB_SDPIF_APER_BASE__SDPIF_APER_BASE_MASK
53385. DCHUBBUB_SDPIF_APER_BASE__SDPIF_APER_BASE__SHIFT
53386. DCHUBBUB_SDPIF_APER_BASE__SDPIF_LOCK_DRAM_REGS_MASK
53387. DCHUBBUB_SDPIF_APER_BASE__SDPIF_LOCK_DRAM_REGS__SHIFT
53388. DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0_MASK
53389. DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0__SHIFT
53390. DCHUBBUB_SDPIF_APER_DEF_1__SDPIF_APER_DEF_1_MASK
53391. DCHUBBUB_SDPIF_APER_DEF_1__SDPIF_APER_DEF_1__SHIFT
53392. DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP_MASK
53393. DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP__SHIFT
53394. DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK
53395. DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT
53396. DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR_MASK
53397. DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR__SHIFT
53398. DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK
53399. DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT
53400. DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK
53401. DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT
53402. DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK
53403. DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT
53404. DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK
53405. DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT
53406. DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK
53407. DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT
53408. DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK
53409. DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT
53410. DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK
53411. DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT
53412. DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK
53413. DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT
53414. DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK
53415. DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT
53416. DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK
53417. DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT
53418. DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK_MASK
53419. DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK__SHIFT
53420. DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK
53421. DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT
53422. DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO_MASK
53423. DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO__SHIFT
53424. DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC_MASK
53425. DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC__SHIFT
53426. DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO_MASK
53427. DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO__SHIFT
53428. DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC_MASK
53429. DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC__SHIFT
53430. DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK
53431. DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT
53432. DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK
53433. DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT
53434. DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK
53435. DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT
53436. DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK
53437. DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT
53438. DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK
53439. DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT
53440. DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK
53441. DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT
53442. DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE_MASK
53443. DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE__SHIFT
53444. DCHUBBUB_SDPIF_FB_OFFSET__SDPIF_FB_OFFSET_MASK
53445. DCHUBBUB_SDPIF_FB_OFFSET__SDPIF_FB_OFFSET__SHIFT
53446. DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP_MASK
53447. DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP__SHIFT
53448. DCHUBBUB_SDPIF_MARC_BASE_HI_0__SDPIF_MARC_BASE_HI_0_MASK
53449. DCHUBBUB_SDPIF_MARC_BASE_HI_0__SDPIF_MARC_BASE_HI_0__SHIFT
53450. DCHUBBUB_SDPIF_MARC_BASE_HI_1__SDPIF_MARC_BASE_HI_1_MASK
53451. DCHUBBUB_SDPIF_MARC_BASE_HI_1__SDPIF_MARC_BASE_HI_1__SHIFT
53452. DCHUBBUB_SDPIF_MARC_BASE_HI_2__SDPIF_MARC_BASE_HI_2_MASK
53453. DCHUBBUB_SDPIF_MARC_BASE_HI_2__SDPIF_MARC_BASE_HI_2__SHIFT
53454. DCHUBBUB_SDPIF_MARC_BASE_HI_3__SDPIF_MARC_BASE_HI_3_MASK
53455. DCHUBBUB_SDPIF_MARC_BASE_HI_3__SDPIF_MARC_BASE_HI_3__SHIFT
53456. DCHUBBUB_SDPIF_MARC_BASE_LO_0__SDPIF_MARC_BASE_LO_0_MASK
53457. DCHUBBUB_SDPIF_MARC_BASE_LO_0__SDPIF_MARC_BASE_LO_0__SHIFT
53458. DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1_MASK
53459. DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1__SHIFT
53460. DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2_MASK
53461. DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2__SHIFT
53462. DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3_MASK
53463. DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3__SHIFT
53464. DCHUBBUB_SDPIF_MARC_LENGTH_HI_0__SDPIF_MARC_LENGTH_HI_0_MASK
53465. DCHUBBUB_SDPIF_MARC_LENGTH_HI_0__SDPIF_MARC_LENGTH_HI_0__SHIFT
53466. DCHUBBUB_SDPIF_MARC_LENGTH_HI_1__SDPIF_MARC_LENGTH_HI_1_MASK
53467. DCHUBBUB_SDPIF_MARC_LENGTH_HI_1__SDPIF_MARC_LENGTH_HI_1__SHIFT
53468. DCHUBBUB_SDPIF_MARC_LENGTH_HI_2__SDPIF_MARC_LENGTH_HI_2_MASK
53469. DCHUBBUB_SDPIF_MARC_LENGTH_HI_2__SDPIF_MARC_LENGTH_HI_2__SHIFT
53470. DCHUBBUB_SDPIF_MARC_LENGTH_HI_3__SDPIF_MARC_LENGTH_HI_3_MASK
53471. DCHUBBUB_SDPIF_MARC_LENGTH_HI_3__SDPIF_MARC_LENGTH_HI_3__SHIFT
53472. DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0_MASK
53473. DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0__SHIFT
53474. DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1_MASK
53475. DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1__SHIFT
53476. DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2_MASK
53477. DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2__SHIFT
53478. DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3_MASK
53479. DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3__SHIFT
53480. DCHUBBUB_SDPIF_MARC_RELOC_HI_0__SDPIF_MARC_RELOC_HI_0_MASK
53481. DCHUBBUB_SDPIF_MARC_RELOC_HI_0__SDPIF_MARC_RELOC_HI_0__SHIFT
53482. DCHUBBUB_SDPIF_MARC_RELOC_HI_1__SDPIF_MARC_RELOC_HI_1_MASK
53483. DCHUBBUB_SDPIF_MARC_RELOC_HI_1__SDPIF_MARC_RELOC_HI_1__SHIFT
53484. DCHUBBUB_SDPIF_MARC_RELOC_HI_2__SDPIF_MARC_RELOC_HI_2_MASK
53485. DCHUBBUB_SDPIF_MARC_RELOC_HI_2__SDPIF_MARC_RELOC_HI_2__SHIFT
53486. DCHUBBUB_SDPIF_MARC_RELOC_HI_3__SDPIF_MARC_RELOC_HI_3_MASK
53487. DCHUBBUB_SDPIF_MARC_RELOC_HI_3__SDPIF_MARC_RELOC_HI_3__SHIFT
53488. DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0_MASK
53489. DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0__SHIFT
53490. DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0_MASK
53491. DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0__SHIFT
53492. DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1_MASK
53493. DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1__SHIFT
53494. DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1_MASK
53495. DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1__SHIFT
53496. DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2_MASK
53497. DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2__SHIFT
53498. DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2_MASK
53499. DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2__SHIFT
53500. DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3_MASK
53501. DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3__SHIFT
53502. DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3_MASK
53503. DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3__SHIFT
53504. DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK
53505. DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT
53506. DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK
53507. DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT
53508. DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK
53509. DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT
53510. DCHUBBUB_SDPIF_MMIO_CNTRL_0__SDPIF_IOMMU_EN_MASK
53511. DCHUBBUB_SDPIF_MMIO_CNTRL_0__SDPIF_IOMMU_EN__SHIFT
53512. DCHUBBUB_SDPIF_MMIO_CNTRL_1__SDPIF_MARC_EN_MASK
53513. DCHUBBUB_SDPIF_MMIO_CNTRL_1__SDPIF_MARC_EN__SHIFT
53514. DCHUBBUB_SDPIF_MMIO_CNTRL_W__SDPIF_GMC_IOMMU_BYPASS_MASK
53515. DCHUBBUB_SDPIF_MMIO_CNTRL_W__SDPIF_GMC_IOMMU_BYPASS__SHIFT
53516. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK
53517. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT
53518. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK
53519. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT
53520. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK
53521. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT
53522. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK
53523. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT
53524. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE4_DMDATA_SEC_LVL_MASK
53525. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE4_DMDATA_SEC_LVL__SHIFT
53526. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE5_DMDATA_SEC_LVL_MASK
53527. DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE5_DMDATA_SEC_LVL__SHIFT
53528. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK
53529. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT
53530. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK
53531. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT
53532. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK
53533. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT
53534. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK
53535. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT
53536. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE4_SEC_LVL_MASK
53537. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE4_SEC_LVL__SHIFT
53538. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE5_SEC_LVL_MASK
53539. DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE5_SEC_LVL__SHIFT
53540. DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK
53541. DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT
53542. DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK
53543. DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT
53544. DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK
53545. DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT
53546. DCHUBBUB_SPARE__DCHUBBUB_SPARE_MASK
53547. DCHUBBUB_SPARE__DCHUBBUB_SPARE__SHIFT
53548. DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK
53549. DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT
53550. DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK
53551. DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT
53552. DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK
53553. DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT
53554. DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK
53555. DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT
53556. DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK
53557. DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT
53558. DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK
53559. DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT
53560. DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK
53561. DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT
53562. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK
53563. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT
53564. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK
53565. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT
53566. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK
53567. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT
53568. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK
53569. DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT
53570. DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK
53571. DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT
53572. DCHUB_AGP_BASE__AGP_BASE_MASK
53573. DCHUB_AGP_BASE__AGP_BASE__SHIFT
53574. DCHUB_AGP_BOT__AGP_BOT_MASK
53575. DCHUB_AGP_BOT__AGP_BOT__SHIFT
53576. DCHUB_AGP_TOP__AGP_TOP_MASK
53577. DCHUB_AGP_TOP__AGP_TOP__SHIFT
53578. DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL_MASK
53579. DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL__SHIFT
53580. DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN_MASK
53581. DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN__SHIFT
53582. DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ_MASK
53583. DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ__SHIFT
53584. DCHUB_CONTROL_STATUS__REQ_CREDIT_EN_MASK
53585. DCHUB_CONTROL_STATUS__REQ_CREDIT_EN__SHIFT
53586. DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY_MASK
53587. DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY__SHIFT
53588. DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR_MASK
53589. DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR__SHIFT
53590. DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_MASK
53591. DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS__SHIFT
53592. DCHUB_CONTROL_STATUS__SDP_PORT_STATUS_MASK
53593. DCHUB_CONTROL_STATUS__SDP_PORT_STATUS__SHIFT
53594. DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR_MASK
53595. DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR__SHIFT
53596. DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_MASK
53597. DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR__SHIFT
53598. DCHUB_DRAM_APER_BASE__BASE_MASK
53599. DCHUB_DRAM_APER_BASE__BASE__SHIFT
53600. DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS_MASK
53601. DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS__SHIFT
53602. DCHUB_DRAM_APER_DEF__DEF_MASK
53603. DCHUB_DRAM_APER_DEF__DEF__SHIFT
53604. DCHUB_DRAM_APER_TOP__TOP_MASK
53605. DCHUB_DRAM_APER_TOP__TOP__SHIFT
53606. DCHUB_FB_LOCATION__FB_BASE_MASK
53607. DCHUB_FB_LOCATION__FB_BASE__SHIFT
53608. DCHUB_FB_LOCATION__FB_TOP_MASK
53609. DCHUB_FB_LOCATION__FB_TOP__SHIFT
53610. DCHUB_FB_OFFSET__FB_OFFSET_MASK
53611. DCHUB_FB_OFFSET__FB_OFFSET__SHIFT
53612. DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53613. DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53614. DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK
53615. DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT
53616. DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53617. DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53618. DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK
53619. DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT
53620. DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53621. DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53622. DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK
53623. DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT
53624. DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53625. DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53626. DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK
53627. DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT
53628. DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53629. DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53630. DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK
53631. DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT
53632. DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53633. DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53634. DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK
53635. DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT
53636. DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53637. DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53638. DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK
53639. DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT
53640. DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53641. DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53642. DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK
53643. DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT
53644. DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK
53645. DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT
53646. DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK
53647. DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT
53648. DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53649. DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53650. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK
53651. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53652. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK
53653. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53654. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK
53655. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT
53656. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53657. DCHUB_INTERRUPT_DEST__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53658. DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53659. DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53660. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK
53661. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53662. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK
53663. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53664. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK
53665. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT
53666. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53667. DCHUB_INTERRUPT_DEST__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53668. DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53669. DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53670. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK
53671. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53672. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK
53673. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53674. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK
53675. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT
53676. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53677. DCHUB_INTERRUPT_DEST__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53678. DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53679. DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53680. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK
53681. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53682. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK
53683. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53684. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK
53685. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT
53686. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53687. DCHUB_INTERRUPT_DEST__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53688. DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53689. DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53690. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK
53691. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53692. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK
53693. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53694. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK
53695. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT
53696. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53697. DCHUB_INTERRUPT_DEST__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53698. DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53699. DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53700. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK
53701. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53702. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK
53703. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53704. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK
53705. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT
53706. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53707. DCHUB_INTERRUPT_DEST__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53708. DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53709. DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53710. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK
53711. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53712. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK
53713. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53714. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK
53715. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT
53716. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53717. DCHUB_INTERRUPT_DEST__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53718. DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK
53719. DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
53720. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK
53721. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT
53722. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK
53723. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT
53724. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK
53725. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT
53726. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK
53727. DCHUB_INTERRUPT_DEST__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT
53728. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53729. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53730. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53731. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53732. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53733. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53734. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53735. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53736. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53737. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53738. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53739. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53740. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53741. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53742. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53743. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53744. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53745. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53746. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53747. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53748. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53749. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53750. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53751. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53752. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53753. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53754. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53755. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53756. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53757. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53758. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53759. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53760. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
53761. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
53762. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
53763. DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
53764. DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK
53765. DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT
53766. DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK
53767. DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT
53768. DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK
53769. DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT
53770. DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK
53771. DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT
53772. DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK
53773. DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT
53774. DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK
53775. DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT
53776. DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK
53777. DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT
53778. DCHVM_CTRL1__DUMMY1_MASK
53779. DCHVM_CTRL1__DUMMY1__SHIFT
53780. DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK
53781. DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT
53782. DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK
53783. DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT
53784. DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK
53785. DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT
53786. DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK
53787. DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT
53788. DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK
53789. DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT
53790. DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK
53791. DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT
53792. DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK
53793. DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT
53794. DCIDR_GET
53795. DCIDR_PUT
53796. DCIOCHIP_2BIT_DISABLE
53797. DCIOCHIP_2BIT_ENABLE
53798. DCIOCHIP_4BIT_DISABLE
53799. DCIOCHIP_4BIT_ENABLE
53800. DCIOCHIP_5BIT_DISABLE
53801. DCIOCHIP_5BIT_ENABLE
53802. DCIOCHIP_AUXSLAVE_PAD_MODE
53803. DCIOCHIP_AUXSLAVE_PAD_MODE_AUX
53804. DCIOCHIP_AUXSLAVE_PAD_MODE_I2C
53805. DCIOCHIP_AUX_ALL_PWR_OK
53806. DCIOCHIP_AUX_ALL_PWR_OK_0
53807. DCIOCHIP_AUX_ALL_PWR_OK_1
53808. DCIOCHIP_AUX_CSEL0P9
53809. DCIOCHIP_AUX_CSEL1P1
53810. DCIOCHIP_AUX_CSEL_DEC0P9
53811. DCIOCHIP_AUX_CSEL_DEC1P0
53812. DCIOCHIP_AUX_CSEL_INC1P0
53813. DCIOCHIP_AUX_CSEL_INC1P1
53814. DCIOCHIP_AUX_FALLSLEWSEL
53815. DCIOCHIP_AUX_FALLSLEWSEL_HIGH0
53816. DCIOCHIP_AUX_FALLSLEWSEL_HIGH1
53817. DCIOCHIP_AUX_FALLSLEWSEL_LOW
53818. DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH
53819. DCIOCHIP_AUX_HYS_TUNE
53820. DCIOCHIP_AUX_HYS_TUNE_0
53821. DCIOCHIP_AUX_HYS_TUNE_1
53822. DCIOCHIP_AUX_HYS_TUNE_2
53823. DCIOCHIP_AUX_HYS_TUNE_3
53824. DCIOCHIP_AUX_RECEIVER_SEL
53825. DCIOCHIP_AUX_RECEIVER_SEL_0
53826. DCIOCHIP_AUX_RECEIVER_SEL_1
53827. DCIOCHIP_AUX_RECEIVER_SEL_2
53828. DCIOCHIP_AUX_RECEIVER_SEL_3
53829. DCIOCHIP_AUX_RSEL0P9
53830. DCIOCHIP_AUX_RSEL1P1
53831. DCIOCHIP_AUX_RSEL_DEC0P9
53832. DCIOCHIP_AUX_RSEL_DEC1P0
53833. DCIOCHIP_AUX_RSEL_INC1P0
53834. DCIOCHIP_AUX_RSEL_INC1P1
53835. DCIOCHIP_AUX_SPIKESEL
53836. DCIOCHIP_AUX_SPIKESEL_10NS
53837. DCIOCHIP_AUX_SPIKESEL_50NS
53838. DCIOCHIP_AUX_VOD_TUNE
53839. DCIOCHIP_AUX_VOD_TUNE_0
53840. DCIOCHIP_AUX_VOD_TUNE_1
53841. DCIOCHIP_AUX_VOD_TUNE_2
53842. DCIOCHIP_AUX_VOD_TUNE_3
53843. DCIOCHIP_DVO_VREFPON
53844. DCIOCHIP_DVO_VREFPON_DISABLE
53845. DCIOCHIP_DVO_VREFPON_ENABLE
53846. DCIOCHIP_DVO_VREFSEL
53847. DCIOCHIP_DVO_VREFSEL_EXTERNAL
53848. DCIOCHIP_DVO_VREFSEL_ONCHIP
53849. DCIOCHIP_ENABLE_2BIT
53850. DCIOCHIP_ENABLE_4BIT
53851. DCIOCHIP_ENABLE_5BIT
53852. DCIOCHIP_GPIO_I2C_DISABLE
53853. DCIOCHIP_GPIO_I2C_DRIVE
53854. DCIOCHIP_GPIO_I2C_DRIVE_HIGH
53855. DCIOCHIP_GPIO_I2C_DRIVE_LOW
53856. DCIOCHIP_GPIO_I2C_EN
53857. DCIOCHIP_GPIO_I2C_ENABLE
53858. DCIOCHIP_GPIO_I2C_MASK
53859. DCIOCHIP_GPIO_I2C_MASK_DISABLE
53860. DCIOCHIP_GPIO_I2C_MASK_ENABLE
53861. DCIOCHIP_GPIO_MASK_EN
53862. DCIOCHIP_GPIO_MASK_EN_HARDWARE
53863. DCIOCHIP_GPIO_MASK_EN_SOFTWARE
53864. DCIOCHIP_HPD_SEL
53865. DCIOCHIP_HPD_SEL_ASYNC
53866. DCIOCHIP_HPD_SEL_CLOCKED
53867. DCIOCHIP_I2C_COMPSEL
53868. DCIOCHIP_I2C_FALLSLEWSEL
53869. DCIOCHIP_I2C_FALLSLEWSEL_00
53870. DCIOCHIP_I2C_FALLSLEWSEL_01
53871. DCIOCHIP_I2C_FALLSLEWSEL_10
53872. DCIOCHIP_I2C_FALLSLEWSEL_11
53873. DCIOCHIP_I2C_RECEIVER_SEL
53874. DCIOCHIP_I2C_RECEIVER_SEL_0
53875. DCIOCHIP_I2C_RECEIVER_SEL_1
53876. DCIOCHIP_I2C_RECEIVER_SEL_2
53877. DCIOCHIP_I2C_RECEIVER_SEL_3
53878. DCIOCHIP_I2C_REC_COMPARATOR
53879. DCIOCHIP_I2C_REC_SCHMIT
53880. DCIOCHIP_I2C_VPH_1V2_EN
53881. DCIOCHIP_I2C_VPH_1V2_EN_0
53882. DCIOCHIP_I2C_VPH_1V2_EN_1
53883. DCIOCHIP_INVERT
53884. DCIOCHIP_MASIK_5BIT_DISABLE
53885. DCIOCHIP_MASIK_5BIT_ENABLE
53886. DCIOCHIP_MASK
53887. DCIOCHIP_MASK_2BIT
53888. DCIOCHIP_MASK_2BIT_DISABLE
53889. DCIOCHIP_MASK_2BIT_ENABLE
53890. DCIOCHIP_MASK_4BIT
53891. DCIOCHIP_MASK_4BIT_DISABLE
53892. DCIOCHIP_MASK_4BIT_ENABLE
53893. DCIOCHIP_MASK_5BIT
53894. DCIOCHIP_MASK_DISABLE
53895. DCIOCHIP_MASK_ENABLE
53896. DCIOCHIP_PAD_MODE
53897. DCIOCHIP_PAD_MODE_DDC
53898. DCIOCHIP_PAD_MODE_DP
53899. DCIOCHIP_PD_EN
53900. DCIOCHIP_PD_EN_ALLOW
53901. DCIOCHIP_PD_EN_NOTALLOW
53902. DCIOCHIP_POL_INVERT
53903. DCIOCHIP_POL_NON_INVERT
53904. DCIOCHIP_REF_27_SRC_SEL
53905. DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS
53906. DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER
53907. DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS
53908. DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER
53909. DCIOCHIP_SPDIF1_IMODE
53910. DCIOCHIP_SPDIF1_IMODE_OE_A
53911. DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO
53912. DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE
53913. DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN
53914. DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT
53915. DCIO_BL_PWM_CNTL_BL_PWM_EN
53916. DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN
53917. DCIO_BL_PWM_DISABLE
53918. DCIO_BL_PWM_ENABLE
53919. DCIO_BL_PWM_FRACTIONAL_DISABLE
53920. DCIO_BL_PWM_FRACTIONAL_ENABLE
53921. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL
53922. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1
53923. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2
53924. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3
53925. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4
53926. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5
53927. DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6
53928. DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE
53929. DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN
53930. DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE
53931. DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN
53932. DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM
53933. DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM
53934. DCIO_BL_PWM_GRP1_REG_LOCK
53935. DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE
53936. DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE
53937. DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START
53938. DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE
53939. DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE
53940. DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE
53941. DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE
53942. DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL
53943. DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM
53944. DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL
53945. DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS
53946. DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS
53947. DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK
53948. DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT
53949. DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK
53950. DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT
53951. DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK
53952. DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT
53953. DCIO_DACA_SOFT_RESET
53954. DCIO_DACA_SOFT_RESET_ASSERT
53955. DCIO_DACA_SOFT_RESET_DEASSERT
53956. DCIO_DBG_ASYNC_4BIT_SEL
53957. DCIO_DBG_ASYNC_4BIT_SEL_11TO8
53958. DCIO_DBG_ASYNC_4BIT_SEL_15TO12
53959. DCIO_DBG_ASYNC_4BIT_SEL_19TO16
53960. DCIO_DBG_ASYNC_4BIT_SEL_23TO20
53961. DCIO_DBG_ASYNC_4BIT_SEL_27TO24
53962. DCIO_DBG_ASYNC_4BIT_SEL_31TO28
53963. DCIO_DBG_ASYNC_4BIT_SEL_3TO0
53964. DCIO_DBG_ASYNC_4BIT_SEL_7TO4
53965. DCIO_DBG_ASYNC_BLOCK_SEL
53966. DCIO_DBG_ASYNC_BLOCK_SEL_DCCG
53967. DCIO_DBG_ASYNC_BLOCK_SEL_DCIO
53968. DCIO_DBG_ASYNC_BLOCK_SEL_DCO
53969. DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE
53970. DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1
53971. DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2
53972. DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3
53973. DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL
53974. DCIO_DBG_CLOCK_SEL
53975. DCIO_DBG_CLOCK_SEL_DISPCLK
53976. DCIO_DBG_CLOCK_SEL_REFCLK
53977. DCIO_DBG_CLOCK_SEL_SYMCLKA
53978. DCIO_DBG_CLOCK_SEL_SYMCLKB
53979. DCIO_DBG_CLOCK_SEL_SYMCLKC
53980. DCIO_DBG_CLOCK_SEL_SYMCLKD
53981. DCIO_DBG_CLOCK_SEL_SYMCLKE
53982. DCIO_DBG_CLOCK_SEL_SYMCLKF
53983. DCIO_DBG_OUT_12BIT_SEL
53984. DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT
53985. DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT
53986. DCIO_DBG_OUT_12BIT_SEL_MID_12BIT
53987. DCIO_DBG_OUT_12BIT_SEL_OVERRIDE
53988. DCIO_DBG_OUT_PIN_SEL
53989. DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT
53990. DCIO_DBG_OUT_PIN_SEL_LOW_12BIT
53991. DCIO_DCO_DCFE_EXT_VSYNC_MUX
53992. DCIO_DCO_EXT_VSYNC_MASK
53993. DCIO_DCRXPHY_SOFT_RESET
53994. DCIO_DCRXPHY_SOFT_RESET_ASSERT
53995. DCIO_DCRXPHY_SOFT_RESET_DEASSERT
53996. DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN
53997. DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN
53998. DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN
53999. DCIO_DC_GENERICA_SEL
54000. DCIO_DC_GENERICB_SEL
54001. DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL
54002. DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL
54003. DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL
54004. DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL
54005. DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL
54006. DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL
54007. DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP
54008. DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN
54009. DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS
54010. DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE
54011. DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE
54012. DCIO_DC_GPIO_MACRO_DEBUG
54013. DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF
54014. DCIO_DC_GPIO_MACRO_DEBUG_NORMAL
54015. DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2
54016. DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3
54017. DCIO_DC_GPIO_VIP_DEBUG
54018. DCIO_DC_GPIO_VIP_DEBUG_CG_BIG
54019. DCIO_DC_GPIO_VIP_DEBUG_NORMAL
54020. DCIO_DC_GPU_TIMER_READ_SELECT
54021. DCIO_DC_GPU_TIMER_START_POSITION
54022. DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS
54023. DCIO_DC_PAD_EXTERN_SIG_SEL
54024. DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK
54025. DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA
54026. DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK
54027. DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA
54028. DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA
54029. DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB
54030. DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC
54031. DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK
54032. DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC
54033. DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1
54034. DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2
54035. DCIO_DC_PAD_EXTERN_SIG_SEL_MVP
54036. DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0
54037. DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1
54038. DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL
54039. DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA
54040. DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL
54041. DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL
54042. DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK
54043. DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT
54044. DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK
54045. DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT
54046. DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK
54047. DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT
54048. DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK
54049. DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT
54050. DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK
54051. DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT
54052. DCIO_DEBUG15__DCIO_DEBUG15_MASK
54053. DCIO_DEBUG15__DCIO_DEBUG15__SHIFT
54054. DCIO_DEBUG16__DCIO_DEBUG16_MASK
54055. DCIO_DEBUG16__DCIO_DEBUG16__SHIFT
54056. DCIO_DEBUG17__DCIO_DEBUG17_MASK
54057. DCIO_DEBUG17__DCIO_DEBUG17__SHIFT
54058. DCIO_DEBUG18__DCIO_DEBUG18_MASK
54059. DCIO_DEBUG18__DCIO_DEBUG18__SHIFT
54060. DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK
54061. DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT
54062. DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK
54063. DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT
54064. DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK
54065. DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT
54066. DCIO_DEBUG1C__DCIO_DEBUG_UNIPHYA_CFG_MASK
54067. DCIO_DEBUG1C__DCIO_DEBUG_UNIPHYA_CFG__SHIFT
54068. DCIO_DEBUG1D__DCIO_DEBUG_UNIPHYB_CFG_MASK
54069. DCIO_DEBUG1D__DCIO_DEBUG_UNIPHYB_CFG__SHIFT
54070. DCIO_DEBUG1E__DCIO_DEBUG_UNIPHYC_CFG_MASK
54071. DCIO_DEBUG1E__DCIO_DEBUG_UNIPHYC_CFG__SHIFT
54072. DCIO_DEBUG1F__DCIO_DEBUG_UNIPHYD_CFG_MASK
54073. DCIO_DEBUG1F__DCIO_DEBUG_UNIPHYD_CFG__SHIFT
54074. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK
54075. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK
54076. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT
54077. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK
54078. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT
54079. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT
54080. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK
54081. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK
54082. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT
54083. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK
54084. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT
54085. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT
54086. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK
54087. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT
54088. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK
54089. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT
54090. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK
54091. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK
54092. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT
54093. DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT
54094. DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK
54095. DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT
54096. DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK
54097. DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT
54098. DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK
54099. DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT
54100. DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK
54101. DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT
54102. DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK
54103. DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT
54104. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK
54105. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT
54106. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK
54107. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK
54108. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT
54109. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT
54110. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK
54111. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK
54112. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT
54113. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT
54114. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK
54115. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT
54116. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK
54117. DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT
54118. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK
54119. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK
54120. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT
54121. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK
54122. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT
54123. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT
54124. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK
54125. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK
54126. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT
54127. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK
54128. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT
54129. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT
54130. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK
54131. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT
54132. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK
54133. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT
54134. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK
54135. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK
54136. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT
54137. DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT
54138. DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK
54139. DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT
54140. DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK
54141. DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT
54142. DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK
54143. DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT
54144. DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK
54145. DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT
54146. DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK
54147. DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT
54148. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK
54149. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT
54150. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK
54151. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK
54152. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT
54153. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT
54154. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK
54155. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK
54156. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT
54157. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT
54158. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK
54159. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT
54160. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK
54161. DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT
54162. DCIO_DEBUG20__DCIO_DEBUG_UNIPHYE_CFG_MASK
54163. DCIO_DEBUG20__DCIO_DEBUG_UNIPHYE_CFG__SHIFT
54164. DCIO_DEBUG21__DCIO_DEBUG_UNIPHYF_CFG_MASK
54165. DCIO_DEBUG21__DCIO_DEBUG_UNIPHYF_CFG__SHIFT
54166. DCIO_DEBUG22__DCIO_DEBUG_UNIPHYG_CFG_MASK
54167. DCIO_DEBUG22__DCIO_DEBUG_UNIPHYG_CFG__SHIFT
54168. DCIO_DEBUG23__DCIO_DEBUG_UNIPHYLPA_CFG_MASK
54169. DCIO_DEBUG23__DCIO_DEBUG_UNIPHYLPA_CFG__SHIFT
54170. DCIO_DEBUG24__DCIO_DEBUG_UNIPHYLPB_CFG_MASK
54171. DCIO_DEBUG24__DCIO_DEBUG_UNIPHYLPB_CFG__SHIFT
54172. DCIO_DEBUG25__DCIO_DEBUG_DCRXPHY_CFG_MASK
54173. DCIO_DEBUG25__DCIO_DEBUG_DCRXPHY_CFG__SHIFT
54174. DCIO_DEBUG26__DCIO_DEBUG_DPHY_CFG_MASK
54175. DCIO_DEBUG26__DCIO_DEBUG_DPHY_CFG__SHIFT
54176. DCIO_DEBUG27__DCIO_DEBUG_DACA_CFG_MASK
54177. DCIO_DEBUG27__DCIO_DEBUG_DACA_CFG__SHIFT
54178. DCIO_DEBUG28__DCIO_DEBUG_ZCAL_CFG_MASK
54179. DCIO_DEBUG28__DCIO_DEBUG_ZCAL_CFG__SHIFT
54180. DCIO_DEBUG2__DCIO_DEBUG2_MASK
54181. DCIO_DEBUG2__DCIO_DEBUG2__SHIFT
54182. DCIO_DEBUG3__DCIO_DEBUG3_MASK
54183. DCIO_DEBUG3__DCIO_DEBUG3__SHIFT
54184. DCIO_DEBUG4__DCIO_DEBUG4_MASK
54185. DCIO_DEBUG4__DCIO_DEBUG4__SHIFT
54186. DCIO_DEBUG5__DCIO_DEBUG5_MASK
54187. DCIO_DEBUG5__DCIO_DEBUG5__SHIFT
54188. DCIO_DEBUG6__DCIO_DEBUG6_MASK
54189. DCIO_DEBUG6__DCIO_DEBUG6__SHIFT
54190. DCIO_DEBUG7__DCIO_DEBUG7_MASK
54191. DCIO_DEBUG7__DCIO_DEBUG7__SHIFT
54192. DCIO_DEBUG8__DCIO_DEBUG8_MASK
54193. DCIO_DEBUG8__DCIO_DEBUG8__SHIFT
54194. DCIO_DEBUG9__DCIO_DEBUG9_MASK
54195. DCIO_DEBUG9__DCIO_DEBUG9__SHIFT
54196. DCIO_DEBUGA__DCIO_DEBUGA_MASK
54197. DCIO_DEBUGA__DCIO_DEBUGA__SHIFT
54198. DCIO_DEBUGB__DCIO_DEBUGB_MASK
54199. DCIO_DEBUGB__DCIO_DEBUGB__SHIFT
54200. DCIO_DEBUGC__DCIO_DEBUGC_MASK
54201. DCIO_DEBUGC__DCIO_DEBUGC__SHIFT
54202. DCIO_DEBUGD__DCIO_DEBUGD_MASK
54203. DCIO_DEBUGD__DCIO_DEBUGD__SHIFT
54204. DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK
54205. DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT
54206. DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK
54207. DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT
54208. DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK
54209. DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT
54210. DCIO_DEBUG_CONFIG__DCIO_DBG_SEL_MASK
54211. DCIO_DEBUG_CONFIG__DCIO_DBG_SEL__SHIFT
54212. DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK
54213. DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT
54214. DCIO_DEBUG__DCIO_DEBUG_MASK
54215. DCIO_DEBUG__DCIO_DEBUG__SHIFT
54216. DCIO_DIO_EXT_VSYNC_MASK
54217. DCIO_DIO_OTG_EXT_VSYNC_MUX
54218. DCIO_DISPCLK_R_DCIO_GATE_DISABLE
54219. DCIO_DISPCLK_R_DCIO_GATE_ENABLE
54220. DCIO_DISPCLK_R_DCIO_RAMP_DISABLE
54221. DCIO_DISPCLK_R_DCIO_RAMP_ENABLE
54222. DCIO_DPCS_INTERRUPT_DISABLE
54223. DCIO_DPCS_INTERRUPT_ENABLE
54224. DCIO_DPCS_INTERRUPT_MASK
54225. DCIO_DPCS_INTERRUPT_TYPE
54226. DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED
54227. DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED
54228. DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK
54229. DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT
54230. DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK
54231. DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT
54232. DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK
54233. DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT
54234. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK
54235. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT
54236. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK
54237. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT
54238. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK
54239. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT
54240. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK
54241. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT
54242. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK
54243. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT
54244. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK
54245. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT
54246. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK
54247. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT
54248. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK
54249. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT
54250. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK
54251. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT
54252. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK
54253. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT
54254. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK
54255. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT
54256. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK
54257. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT
54258. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK
54259. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT
54260. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK
54261. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT
54262. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK
54263. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT
54264. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK
54265. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT
54266. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK
54267. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT
54268. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK
54269. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT
54270. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK
54271. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT
54272. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK
54273. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT
54274. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK
54275. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT
54276. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK_MASK
54277. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK__SHIFT
54278. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR_MASK
54279. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR__SHIFT
54280. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE_MASK
54281. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE__SHIFT
54282. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK_MASK
54283. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK__SHIFT
54284. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR_MASK
54285. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR__SHIFT
54286. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE_MASK
54287. DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE__SHIFT
54288. DCIO_DPHY_LANE_SEL
54289. DCIO_DPHY_LANE_SEL_LANE0
54290. DCIO_DPHY_LANE_SEL_LANE1
54291. DCIO_DPHY_LANE_SEL_LANE2
54292. DCIO_DPHY_LANE_SEL_LANE3
54293. DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK
54294. DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT
54295. DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK
54296. DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT
54297. DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK
54298. DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT
54299. DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK
54300. DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT
54301. DCIO_DPRX_LOOPBACK_ENABLE_LOOP
54302. DCIO_DPRX_LOOPBACK_ENABLE_NORMAL
54303. DCIO_DSYNC_SOFT_RESET
54304. DCIO_DSYNC_SOFT_RESET_ASSERT
54305. DCIO_DSYNC_SOFT_RESET_DEASSERT
54306. DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE
54307. DCIO_DVO_ALTER_MAPPING_EN_DEFAULT
54308. DCIO_EXT_VSYNC_MASK_NONE
54309. DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE
54310. DCIO_EXT_VSYNC_MASK_PIPE0
54311. DCIO_EXT_VSYNC_MASK_PIPE1
54312. DCIO_EXT_VSYNC_MASK_PIPE2
54313. DCIO_EXT_VSYNC_MASK_PIPE3
54314. DCIO_EXT_VSYNC_MASK_PIPE4
54315. DCIO_EXT_VSYNC_MASK_PIPE5
54316. DCIO_EXT_VSYNC_MUX_CRTC0
54317. DCIO_EXT_VSYNC_MUX_CRTC1
54318. DCIO_EXT_VSYNC_MUX_CRTC2
54319. DCIO_EXT_VSYNC_MUX_CRTC3
54320. DCIO_EXT_VSYNC_MUX_CRTC4
54321. DCIO_EXT_VSYNC_MUX_CRTC5
54322. DCIO_EXT_VSYNC_MUX_GENERICB
54323. DCIO_EXT_VSYNC_MUX_OTG0
54324. DCIO_EXT_VSYNC_MUX_OTG1
54325. DCIO_EXT_VSYNC_MUX_OTG2
54326. DCIO_EXT_VSYNC_MUX_OTG3
54327. DCIO_EXT_VSYNC_MUX_OTG4
54328. DCIO_EXT_VSYNC_MUX_OTG5
54329. DCIO_EXT_VSYNC_MUX_SWAPLOCKB
54330. DCIO_GENERICA_SEL_DACA_FIELD_NUMBER
54331. DCIO_GENERICA_SEL_DACA_PIXCLK
54332. DCIO_GENERICA_SEL_DACA_STEREOSYNC
54333. DCIO_GENERICA_SEL_DACB_FIELD_NUMBER
54334. DCIO_GENERICA_SEL_DACB_PIXCLK
54335. DCIO_GENERICA_SEL_DVOA_CTL3
54336. DCIO_GENERICA_SEL_DVOA_STEREOSYNC
54337. DCIO_GENERICA_SEL_GENERICA_DCCG
54338. DCIO_GENERICA_SEL_GENERICA_DPRX
54339. DCIO_GENERICA_SEL_GENERICA_SCG
54340. DCIO_GENERICA_SEL_GENERICB_DPRX
54341. DCIO_GENERICA_SEL_P1_PLLCLK
54342. DCIO_GENERICA_SEL_P2_PLLCLK
54343. DCIO_GENERICA_SEL_RESERVED_VALUE13
54344. DCIO_GENERICA_SEL_RESERVED_VALUE14
54345. DCIO_GENERICA_SEL_RESERVED_VALUE15
54346. DCIO_GENERICA_SEL_STEREOSYNC
54347. DCIO_GENERICA_SEL_SYNCEN
54348. DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK
54349. DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2
54350. DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK
54351. DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK
54352. DCIO_GENERICB_SEL_DACA_FIELD_NUMBER
54353. DCIO_GENERICB_SEL_DACA_PIXCLK
54354. DCIO_GENERICB_SEL_DACA_STEREOSYNC
54355. DCIO_GENERICB_SEL_DACB_FIELD_NUMBER
54356. DCIO_GENERICB_SEL_DACB_PIXCLK
54357. DCIO_GENERICB_SEL_DVOA_CTL3
54358. DCIO_GENERICB_SEL_DVOA_STEREOSYNC
54359. DCIO_GENERICB_SEL_GENERICA_SCG
54360. DCIO_GENERICB_SEL_GENERICB_DCCG
54361. DCIO_GENERICB_SEL_P1_PLLCLK
54362. DCIO_GENERICB_SEL_P2_PLLCLK
54363. DCIO_GENERICB_SEL_RESERVED_VALUE13
54364. DCIO_GENERICB_SEL_RESERVED_VALUE14
54365. DCIO_GENERICB_SEL_RESERVED_VALUE15
54366. DCIO_GENERICB_SEL_STEREOSYNC
54367. DCIO_GENERICB_SEL_SYNCEN
54368. DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK
54369. DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2
54370. DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK
54371. DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK
54372. DCIO_GENLK_CLK_GSL_MASK
54373. DCIO_GENLK_CLK_GSL_MASK_NO
54374. DCIO_GENLK_CLK_GSL_MASK_STEREO
54375. DCIO_GENLK_CLK_GSL_MASK_TIMING
54376. DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE
54377. DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1
54378. DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2
54379. DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3
54380. DCIO_GENLK_VSYNC_GSL_MASK
54381. DCIO_GENLK_VSYNC_GSL_MASK_NO
54382. DCIO_GENLK_VSYNC_GSL_MASK_STEREO
54383. DCIO_GENLK_VSYNC_GSL_MASK_TIMING
54384. DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP
54385. DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM
54386. DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE
54387. DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP
54388. DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM
54389. DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE
54390. DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP
54391. DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM
54392. DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE
54393. DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP
54394. DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM
54395. DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE
54396. DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP
54397. DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM
54398. DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE
54399. DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP
54400. DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM
54401. DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE
54402. DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP
54403. DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP
54404. DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM
54405. DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE
54406. DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP
54407. DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM
54408. DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE
54409. DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP
54410. DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM
54411. DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE
54412. DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP
54413. DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM
54414. DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE
54415. DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP
54416. DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM
54417. DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE
54418. DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP
54419. DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM
54420. DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE
54421. DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP
54422. DCIO_GPU_TIMER_START_0_END_27
54423. DCIO_GPU_TIMER_START_10_END_37
54424. DCIO_GPU_TIMER_START_1_END_28
54425. DCIO_GPU_TIMER_START_2_END_29
54426. DCIO_GPU_TIMER_START_3_END_30
54427. DCIO_GPU_TIMER_START_4_END_31
54428. DCIO_GPU_TIMER_START_6_END_33
54429. DCIO_GPU_TIMER_START_8_END_35
54430. DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK
54431. DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT
54432. DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK
54433. DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT
54434. DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK
54435. DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT
54436. DCIO_GSL0_GLOBAL_UNLOCK_SEL
54437. DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC
54438. DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK
54439. DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION
54440. DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A
54441. DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B
54442. DCIO_GSL0_TIMING_SYNC_SEL
54443. DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK
54444. DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC
54445. DCIO_GSL0_TIMING_SYNC_SEL_PIPE
54446. DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A
54447. DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B
54448. DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK
54449. DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT
54450. DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK
54451. DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT
54452. DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK
54453. DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT
54454. DCIO_GSL1_GLOBAL_UNLOCK_SEL
54455. DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC
54456. DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK
54457. DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION
54458. DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A
54459. DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B
54460. DCIO_GSL1_TIMING_SYNC_SEL
54461. DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK
54462. DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC
54463. DCIO_GSL1_TIMING_SYNC_SEL_PIPE
54464. DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A
54465. DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B
54466. DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK
54467. DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT
54468. DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK
54469. DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT
54470. DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK
54471. DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT
54472. DCIO_GSL2_GLOBAL_UNLOCK_SEL
54473. DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC
54474. DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK
54475. DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION
54476. DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A
54477. DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B
54478. DCIO_GSL2_TIMING_SYNC_SEL
54479. DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK
54480. DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC
54481. DCIO_GSL2_TIMING_SYNC_SEL_PIPE
54482. DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A
54483. DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B
54484. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK
54485. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT
54486. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK
54487. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT
54488. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK
54489. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT
54490. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK
54491. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT
54492. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK
54493. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT
54494. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK
54495. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT
54496. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK
54497. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT
54498. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK
54499. DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT
54500. DCIO_GSL_SEL
54501. DCIO_GSL_SEL_GROUP_0
54502. DCIO_GSL_SEL_GROUP_1
54503. DCIO_GSL_SEL_GROUP_2
54504. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK
54505. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT
54506. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK
54507. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT
54508. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK
54509. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT
54510. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK
54511. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT
54512. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK
54513. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT
54514. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK
54515. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT
54516. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK
54517. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT
54518. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK
54519. DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT
54520. DCIO_GSL_VSYNC_SEL
54521. DCIO_GSL_VSYNC_SEL_PIPE0
54522. DCIO_GSL_VSYNC_SEL_PIPE1
54523. DCIO_GSL_VSYNC_SEL_PIPE2
54524. DCIO_GSL_VSYNC_SEL_PIPE3
54525. DCIO_GSL_VSYNC_SEL_PIPE4
54526. DCIO_GSL_VSYNC_SEL_PIPE5
54527. DCIO_HSYNCA_OUTPUT_SEL_DISABLE
54528. DCIO_HSYNCA_OUTPUT_SEL_PPLL1
54529. DCIO_HSYNCA_OUTPUT_SEL_PPLL2
54530. DCIO_HSYNCA_OUTPUT_SEL_RESERVED
54531. DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK
54532. DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT
54533. DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK
54534. DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT
54535. DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK
54536. DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT
54537. DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK
54538. DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT
54539. DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK
54540. DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT
54541. DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK
54542. DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT
54543. DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK
54544. DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT
54545. DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK
54546. DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT
54547. DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK
54548. DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT
54549. DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK
54550. DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT
54551. DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK
54552. DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT
54553. DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK
54554. DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT
54555. DCIO_IMPCAL_CNTL__AUX_IMPCAL_BIASENTST_MASK
54556. DCIO_IMPCAL_CNTL__AUX_IMPCAL_BIASENTST__SHIFT
54557. DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK
54558. DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT
54559. DCIO_IMPCAL_CNTL__AUX_IMPCAL_RESBIASEN_MASK
54560. DCIO_IMPCAL_CNTL__AUX_IMPCAL_RESBIASEN__SHIFT
54561. DCIO_IMPCAL_CNTL__AUX_IMPCAL_SPARE_CONTROL_MASK
54562. DCIO_IMPCAL_CNTL__AUX_IMPCAL_SPARE_CONTROL__SHIFT
54563. DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK
54564. DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT
54565. DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK
54566. DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT
54567. DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK
54568. DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT
54569. DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK
54570. DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT
54571. DCIO_IMPCAL_STEP_DELAY
54572. DCIO_IMPCAL_STEP_DELAY_10us
54573. DCIO_IMPCAL_STEP_DELAY_11us
54574. DCIO_IMPCAL_STEP_DELAY_12us
54575. DCIO_IMPCAL_STEP_DELAY_13us
54576. DCIO_IMPCAL_STEP_DELAY_14us
54577. DCIO_IMPCAL_STEP_DELAY_15us
54578. DCIO_IMPCAL_STEP_DELAY_16us
54579. DCIO_IMPCAL_STEP_DELAY_1us
54580. DCIO_IMPCAL_STEP_DELAY_2us
54581. DCIO_IMPCAL_STEP_DELAY_3us
54582. DCIO_IMPCAL_STEP_DELAY_4us
54583. DCIO_IMPCAL_STEP_DELAY_5us
54584. DCIO_IMPCAL_STEP_DELAY_6us
54585. DCIO_IMPCAL_STEP_DELAY_7us
54586. DCIO_IMPCAL_STEP_DELAY_8us
54587. DCIO_IMPCAL_STEP_DELAY_9us
54588. DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK
54589. DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT
54590. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK
54591. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT
54592. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK
54593. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT
54594. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK
54595. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT
54596. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK
54597. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT
54598. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK
54599. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT
54600. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK
54601. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT
54602. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK
54603. DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT
54604. DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST_MASK
54605. DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST__SHIFT
54606. DCIO_LVTMA_BLON_OFF
54607. DCIO_LVTMA_BLON_ON
54608. DCIO_LVTMA_BLON_POL_INVERT
54609. DCIO_LVTMA_BLON_POL_NON_INVERT
54610. DCIO_LVTMA_DIGON_OFF
54611. DCIO_LVTMA_DIGON_ON
54612. DCIO_LVTMA_DIGON_POL_INVERT
54613. DCIO_LVTMA_DIGON_POL_NON_INVERT
54614. DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN
54615. DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON
54616. DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL
54617. DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON
54618. DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL
54619. DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL
54620. DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE
54621. DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN
54622. DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE
54623. DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE
54624. DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF
54625. DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON
54626. DCIO_LVTMA_SYNCEN_POL_INVERT
54627. DCIO_LVTMA_SYNCEN_POL_NON_INVERT
54628. DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON
54629. DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE
54630. DCIO_MVP_PIXEL_SRC_STATUS_CRTC
54631. DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA
54632. DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE
54633. DCIO_MVP_PIXEL_SRC_STATUS_LB
54634. DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK
54635. DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT
54636. DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK
54637. DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT
54638. DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK
54639. DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT
54640. DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK
54641. DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT
54642. DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK
54643. DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT
54644. DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK
54645. DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT
54646. DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK
54647. DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT
54648. DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK
54649. DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT
54650. DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK
54651. DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT
54652. DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK
54653. DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT
54654. DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK
54655. DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT
54656. DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK
54657. DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT
54658. DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK
54659. DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT
54660. DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK
54661. DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT
54662. DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK
54663. DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT
54664. DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK
54665. DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT
54666. DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK
54667. DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT
54668. DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK
54669. DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT
54670. DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK
54671. DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT
54672. DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK
54673. DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT
54674. DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK
54675. DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT
54676. DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK
54677. DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT
54678. DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK
54679. DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT
54680. DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK
54681. DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT
54682. DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK
54683. DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT
54684. DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK
54685. DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT
54686. DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK
54687. DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT
54688. DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK
54689. DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT
54690. DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK
54691. DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT
54692. DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK
54693. DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT
54694. DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK
54695. DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT
54696. DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK
54697. DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT
54698. DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK
54699. DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT
54700. DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK
54701. DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT
54702. DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK
54703. DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT
54704. DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK
54705. DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT
54706. DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK
54707. DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT
54708. DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK
54709. DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT
54710. DCIO_SWAPLOCK_A_GSL_MASK
54711. DCIO_SWAPLOCK_A_GSL_MASK_NO
54712. DCIO_SWAPLOCK_A_GSL_MASK_STEREO
54713. DCIO_SWAPLOCK_A_GSL_MASK_TIMING
54714. DCIO_SWAPLOCK_B_GSL_MASK
54715. DCIO_SWAPLOCK_B_GSL_MASK_NO
54716. DCIO_SWAPLOCK_B_GSL_MASK_STEREO
54717. DCIO_SWAPLOCK_B_GSL_MASK_TIMING
54718. DCIO_TEST_CLK_SEL_DISPCLK
54719. DCIO_TEST_CLK_SEL_GATED_DISPCLK
54720. DCIO_TEST_CLK_SEL_SCLK
54721. DCIO_TEST_CLK_SEL_SOCCLK
54722. DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK
54723. DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT
54724. DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK
54725. DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT
54726. DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK
54727. DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT
54728. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
54729. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54730. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
54731. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54732. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
54733. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54734. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
54735. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54736. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
54737. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54738. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
54739. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54740. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
54741. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54742. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
54743. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54744. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
54745. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54746. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
54747. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54748. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
54749. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54750. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
54751. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54752. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
54753. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54754. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
54755. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54756. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
54757. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54758. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
54759. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54760. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
54761. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54762. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
54763. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54764. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
54765. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54766. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
54767. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54768. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
54769. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54770. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
54771. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54772. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
54773. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54774. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
54775. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54776. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
54777. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54778. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
54779. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54780. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
54781. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54782. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
54783. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54784. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
54785. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54786. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
54787. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54788. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
54789. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54790. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
54791. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54792. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
54793. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54794. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
54795. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54796. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
54797. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54798. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
54799. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54800. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
54801. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54802. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
54803. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54804. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
54805. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54806. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
54807. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54808. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
54809. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54810. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
54811. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54812. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
54813. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54814. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
54815. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54816. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
54817. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54818. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
54819. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54820. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
54821. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54822. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
54823. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54824. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
54825. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54826. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
54827. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54828. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
54829. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54830. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
54831. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54832. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
54833. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54834. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
54835. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54836. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
54837. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54838. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
54839. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54840. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
54841. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54842. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
54843. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54844. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
54845. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54846. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
54847. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54848. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
54849. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54850. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
54851. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54852. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
54853. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54854. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
54855. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54856. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
54857. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54858. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
54859. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54860. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
54861. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54862. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
54863. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54864. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
54865. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54866. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
54867. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54868. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
54869. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54870. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
54871. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54872. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
54873. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54874. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
54875. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54876. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
54877. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54878. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
54879. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54880. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
54881. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54882. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
54883. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54884. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
54885. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54886. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
54887. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54888. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
54889. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54890. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
54891. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54892. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
54893. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54894. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
54895. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54896. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
54897. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54898. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
54899. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54900. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
54901. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54902. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
54903. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54904. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
54905. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54906. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
54907. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54908. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
54909. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54910. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
54911. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54912. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
54913. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54914. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
54915. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54916. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
54917. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54918. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
54919. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54920. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
54921. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54922. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
54923. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54924. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
54925. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54926. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
54927. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54928. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
54929. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54930. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
54931. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54932. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
54933. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54934. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
54935. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54936. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
54937. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54938. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
54939. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54940. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
54941. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54942. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
54943. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54944. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
54945. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54946. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
54947. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54948. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
54949. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54950. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
54951. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54952. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
54953. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54954. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
54955. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54956. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
54957. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54958. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
54959. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54960. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
54961. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54962. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
54963. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54964. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
54965. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54966. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
54967. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54968. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
54969. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54970. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
54971. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54972. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
54973. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54974. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
54975. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54976. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
54977. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54978. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
54979. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54980. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
54981. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54982. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
54983. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54984. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
54985. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54986. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
54987. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54988. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
54989. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54990. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
54991. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54992. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
54993. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54994. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
54995. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54996. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
54997. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
54998. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
54999. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55000. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
55001. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55002. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
55003. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55004. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
55005. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55006. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
55007. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55008. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
55009. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55010. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
55011. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55012. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
55013. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55014. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
55015. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55016. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
55017. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55018. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
55019. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55020. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
55021. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55022. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
55023. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55024. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
55025. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55026. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
55027. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55028. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
55029. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55030. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
55031. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55032. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
55033. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55034. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
55035. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55036. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
55037. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55038. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
55039. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55040. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
55041. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55042. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
55043. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55044. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
55045. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55046. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
55047. DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55048. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
55049. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55050. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
55051. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55052. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
55053. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55054. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
55055. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55056. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
55057. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55058. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
55059. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55060. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
55061. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55062. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
55063. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55064. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
55065. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55066. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
55067. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55068. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
55069. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55070. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
55071. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55072. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
55073. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55074. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
55075. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55076. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
55077. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55078. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
55079. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55080. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
55081. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55082. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
55083. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55084. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
55085. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55086. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
55087. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55088. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
55089. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55090. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
55091. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55092. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
55093. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55094. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
55095. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55096. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
55097. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55098. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
55099. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55100. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
55101. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55102. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
55103. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55104. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
55105. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55106. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
55107. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55108. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
55109. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55110. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
55111. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55112. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
55113. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55114. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
55115. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55116. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
55117. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55118. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
55119. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55120. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
55121. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55122. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
55123. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55124. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
55125. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55126. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
55127. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55128. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
55129. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55130. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
55131. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55132. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
55133. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55134. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
55135. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55136. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
55137. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55138. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
55139. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55140. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
55141. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55142. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
55143. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55144. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
55145. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55146. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
55147. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55148. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
55149. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55150. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
55151. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55152. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
55153. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55154. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
55155. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55156. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
55157. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55158. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
55159. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55160. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
55161. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55162. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
55163. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55164. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
55165. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55166. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
55167. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55168. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
55169. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55170. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
55171. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55172. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
55173. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55174. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
55175. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55176. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
55177. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55178. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
55179. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55180. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
55181. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55182. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
55183. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55184. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
55185. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55186. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
55187. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55188. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
55189. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55190. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
55191. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55192. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
55193. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55194. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
55195. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55196. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
55197. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55198. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
55199. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55200. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
55201. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55202. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
55203. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55204. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
55205. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55206. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
55207. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55208. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
55209. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55210. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
55211. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55212. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
55213. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55214. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
55215. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55216. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
55217. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55218. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
55219. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55220. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
55221. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55222. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
55223. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55224. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
55225. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55226. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
55227. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55228. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
55229. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55230. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
55231. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55232. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
55233. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55234. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
55235. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55236. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
55237. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55238. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
55239. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55240. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
55241. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55242. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
55243. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55244. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
55245. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55246. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
55247. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55248. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
55249. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55250. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
55251. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55252. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
55253. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55254. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
55255. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55256. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
55257. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55258. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
55259. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55260. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
55261. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55262. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
55263. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55264. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
55265. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55266. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
55267. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55268. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
55269. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55270. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
55271. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55272. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
55273. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55274. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
55275. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55276. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
55277. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55278. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
55279. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55280. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
55281. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55282. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
55283. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55284. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
55285. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55286. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
55287. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55288. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
55289. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55290. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
55291. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55292. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
55293. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55294. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
55295. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55296. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
55297. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55298. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
55299. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55300. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
55301. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55302. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
55303. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55304. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
55305. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55306. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
55307. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55308. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
55309. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55310. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
55311. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55312. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
55313. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55314. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
55315. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55316. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
55317. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55318. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
55319. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55320. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
55321. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55322. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
55323. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55324. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
55325. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55326. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
55327. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55328. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
55329. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55330. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
55331. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55332. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
55333. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55334. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
55335. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55336. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
55337. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55338. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
55339. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55340. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
55341. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55342. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
55343. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55344. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
55345. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55346. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
55347. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55348. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
55349. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55350. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
55351. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55352. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
55353. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55354. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
55355. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55356. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
55357. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55358. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
55359. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55360. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
55361. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55362. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
55363. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55364. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
55365. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55366. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
55367. DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55368. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
55369. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55370. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
55371. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55372. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
55373. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55374. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
55375. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55376. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
55377. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55378. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
55379. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55380. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
55381. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55382. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
55383. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55384. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
55385. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55386. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
55387. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55388. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
55389. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55390. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
55391. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55392. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
55393. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55394. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
55395. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55396. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
55397. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55398. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
55399. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55400. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
55401. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55402. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
55403. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55404. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
55405. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55406. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
55407. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55408. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
55409. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55410. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
55411. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55412. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
55413. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55414. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
55415. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55416. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
55417. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55418. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
55419. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55420. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
55421. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55422. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
55423. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55424. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
55425. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55426. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
55427. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55428. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
55429. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55430. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
55431. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55432. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
55433. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55434. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
55435. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55436. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
55437. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55438. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
55439. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55440. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
55441. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55442. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
55443. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55444. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
55445. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55446. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
55447. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55448. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
55449. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55450. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
55451. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55452. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
55453. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55454. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
55455. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55456. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
55457. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55458. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
55459. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55460. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
55461. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55462. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
55463. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55464. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
55465. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55466. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
55467. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55468. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
55469. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55470. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
55471. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55472. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
55473. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55474. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
55475. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55476. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
55477. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55478. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
55479. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55480. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
55481. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55482. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
55483. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55484. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
55485. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55486. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
55487. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55488. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
55489. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55490. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
55491. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55492. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
55493. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55494. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
55495. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55496. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
55497. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55498. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
55499. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55500. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
55501. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55502. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
55503. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55504. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
55505. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55506. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
55507. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55508. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
55509. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55510. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
55511. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55512. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
55513. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55514. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
55515. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55516. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
55517. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55518. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
55519. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55520. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
55521. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55522. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
55523. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55524. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
55525. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55526. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
55527. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55528. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
55529. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55530. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
55531. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55532. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
55533. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55534. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
55535. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55536. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
55537. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55538. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
55539. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55540. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
55541. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55542. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
55543. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55544. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
55545. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55546. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
55547. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55548. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
55549. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55550. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
55551. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55552. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
55553. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55554. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
55555. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55556. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
55557. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55558. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
55559. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55560. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
55561. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55562. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
55563. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55564. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
55565. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55566. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
55567. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55568. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
55569. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55570. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
55571. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55572. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
55573. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55574. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
55575. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55576. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
55577. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55578. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
55579. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55580. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
55581. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55582. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
55583. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55584. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
55585. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55586. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
55587. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55588. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
55589. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55590. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
55591. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55592. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
55593. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55594. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
55595. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55596. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
55597. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55598. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
55599. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55600. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
55601. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55602. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
55603. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55604. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
55605. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55606. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
55607. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55608. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
55609. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55610. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
55611. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55612. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
55613. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55614. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
55615. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55616. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
55617. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55618. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
55619. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55620. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
55621. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55622. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
55623. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55624. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
55625. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55626. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
55627. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55628. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
55629. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55630. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
55631. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55632. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
55633. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55634. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
55635. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55636. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
55637. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55638. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
55639. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55640. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
55641. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55642. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
55643. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55644. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
55645. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55646. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
55647. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55648. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
55649. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55650. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
55651. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55652. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
55653. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55654. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
55655. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55656. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
55657. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55658. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
55659. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55660. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
55661. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55662. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
55663. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55664. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
55665. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55666. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
55667. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55668. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
55669. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55670. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
55671. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55672. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
55673. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55674. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
55675. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55676. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
55677. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55678. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
55679. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55680. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
55681. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55682. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
55683. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55684. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
55685. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55686. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
55687. DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55688. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
55689. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55690. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
55691. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55692. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
55693. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55694. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
55695. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55696. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
55697. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55698. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
55699. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55700. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
55701. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55702. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
55703. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55704. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
55705. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55706. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
55707. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55708. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
55709. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55710. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
55711. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55712. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
55713. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55714. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
55715. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55716. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
55717. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55718. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
55719. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55720. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
55721. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55722. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
55723. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55724. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
55725. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55726. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
55727. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55728. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
55729. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55730. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
55731. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55732. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
55733. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55734. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
55735. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55736. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
55737. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55738. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
55739. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55740. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
55741. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55742. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
55743. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55744. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
55745. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55746. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
55747. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55748. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
55749. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55750. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
55751. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55752. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
55753. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55754. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
55755. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55756. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
55757. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55758. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
55759. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55760. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
55761. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55762. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
55763. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55764. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
55765. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55766. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
55767. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55768. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
55769. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55770. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
55771. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55772. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
55773. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55774. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
55775. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55776. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
55777. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55778. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
55779. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55780. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
55781. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55782. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
55783. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55784. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
55785. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55786. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
55787. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55788. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
55789. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55790. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
55791. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55792. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
55793. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55794. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
55795. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55796. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
55797. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55798. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
55799. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55800. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
55801. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55802. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
55803. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55804. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
55805. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55806. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
55807. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55808. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
55809. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55810. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
55811. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55812. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
55813. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55814. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
55815. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55816. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
55817. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55818. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
55819. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55820. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
55821. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55822. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
55823. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55824. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
55825. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55826. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
55827. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55828. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
55829. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55830. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
55831. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55832. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
55833. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55834. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
55835. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55836. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
55837. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55838. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
55839. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55840. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
55841. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55842. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
55843. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55844. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
55845. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55846. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
55847. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55848. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
55849. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55850. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
55851. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55852. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
55853. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55854. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
55855. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55856. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
55857. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55858. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
55859. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55860. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
55861. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55862. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
55863. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55864. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
55865. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55866. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
55867. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55868. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
55869. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55870. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
55871. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55872. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
55873. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55874. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
55875. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55876. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
55877. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55878. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
55879. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55880. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
55881. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55882. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
55883. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55884. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
55885. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55886. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
55887. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55888. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
55889. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55890. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
55891. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55892. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
55893. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55894. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
55895. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55896. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
55897. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55898. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
55899. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55900. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
55901. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55902. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
55903. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55904. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
55905. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55906. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
55907. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55908. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
55909. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55910. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
55911. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55912. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
55913. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55914. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
55915. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55916. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
55917. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55918. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
55919. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55920. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
55921. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55922. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
55923. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55924. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
55925. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55926. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
55927. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55928. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
55929. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55930. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
55931. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55932. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
55933. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55934. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
55935. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55936. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
55937. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55938. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
55939. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55940. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
55941. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55942. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
55943. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55944. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
55945. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55946. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
55947. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55948. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
55949. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55950. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
55951. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55952. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
55953. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55954. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
55955. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55956. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
55957. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55958. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
55959. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55960. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
55961. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55962. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
55963. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55964. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
55965. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55966. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
55967. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55968. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
55969. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55970. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
55971. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55972. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
55973. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55974. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
55975. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55976. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
55977. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55978. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
55979. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55980. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
55981. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55982. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
55983. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55984. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
55985. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55986. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
55987. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55988. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
55989. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55990. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
55991. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55992. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
55993. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55994. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
55995. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55996. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
55997. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
55998. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
55999. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56000. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
56001. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56002. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
56003. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56004. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
56005. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56006. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
56007. DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56008. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
56009. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56010. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
56011. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56012. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
56013. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56014. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
56015. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56016. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
56017. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56018. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
56019. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56020. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
56021. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56022. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
56023. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56024. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
56025. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56026. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
56027. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56028. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
56029. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56030. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
56031. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56032. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
56033. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56034. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
56035. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56036. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
56037. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56038. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
56039. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56040. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
56041. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56042. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
56043. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56044. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
56045. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56046. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
56047. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56048. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
56049. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56050. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
56051. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56052. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
56053. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56054. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
56055. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56056. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
56057. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56058. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
56059. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56060. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
56061. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56062. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
56063. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56064. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
56065. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56066. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
56067. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56068. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
56069. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56070. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
56071. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56072. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
56073. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56074. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
56075. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56076. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
56077. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56078. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
56079. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56080. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
56081. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56082. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
56083. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56084. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
56085. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56086. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
56087. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56088. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
56089. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56090. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
56091. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56092. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
56093. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56094. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
56095. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56096. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
56097. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56098. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
56099. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56100. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
56101. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56102. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
56103. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56104. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
56105. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56106. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
56107. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56108. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
56109. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56110. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
56111. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56112. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
56113. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56114. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
56115. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56116. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
56117. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56118. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
56119. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56120. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
56121. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56122. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
56123. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56124. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
56125. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56126. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
56127. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56128. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
56129. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56130. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
56131. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56132. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
56133. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56134. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
56135. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56136. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
56137. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56138. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
56139. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56140. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
56141. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56142. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
56143. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56144. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
56145. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56146. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
56147. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56148. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
56149. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56150. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
56151. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56152. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
56153. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56154. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
56155. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56156. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
56157. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56158. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
56159. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56160. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
56161. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56162. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
56163. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56164. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
56165. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56166. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
56167. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56168. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
56169. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56170. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
56171. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56172. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
56173. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56174. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
56175. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56176. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
56177. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56178. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
56179. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56180. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
56181. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56182. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
56183. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56184. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
56185. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56186. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
56187. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56188. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
56189. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56190. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
56191. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56192. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
56193. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56194. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
56195. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56196. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
56197. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56198. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
56199. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56200. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
56201. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56202. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
56203. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56204. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
56205. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56206. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
56207. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56208. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
56209. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56210. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
56211. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56212. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
56213. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56214. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
56215. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56216. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
56217. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56218. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
56219. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56220. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
56221. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56222. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
56223. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56224. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
56225. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56226. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
56227. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56228. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
56229. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56230. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
56231. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56232. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
56233. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56234. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
56235. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56236. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
56237. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56238. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
56239. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56240. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
56241. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56242. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
56243. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56244. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
56245. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56246. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
56247. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56248. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
56249. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56250. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
56251. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56252. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
56253. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56254. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
56255. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56256. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
56257. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56258. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
56259. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56260. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
56261. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56262. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
56263. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56264. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
56265. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56266. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
56267. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56268. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
56269. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56270. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
56271. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56272. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
56273. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56274. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
56275. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56276. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
56277. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56278. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
56279. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56280. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
56281. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56282. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
56283. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56284. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
56285. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56286. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
56287. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56288. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
56289. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56290. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
56291. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56292. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
56293. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56294. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
56295. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56296. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
56297. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56298. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
56299. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56300. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
56301. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56302. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
56303. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56304. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
56305. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56306. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
56307. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56308. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
56309. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56310. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
56311. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56312. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
56313. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56314. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
56315. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56316. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
56317. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56318. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
56319. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56320. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
56321. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56322. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
56323. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56324. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
56325. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56326. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
56327. DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56328. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
56329. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56330. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
56331. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56332. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
56333. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56334. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
56335. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56336. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
56337. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56338. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
56339. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56340. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
56341. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56342. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
56343. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56344. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
56345. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56346. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
56347. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56348. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
56349. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56350. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
56351. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56352. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
56353. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56354. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
56355. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56356. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
56357. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56358. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
56359. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56360. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
56361. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56362. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
56363. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56364. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
56365. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56366. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
56367. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56368. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
56369. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56370. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
56371. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56372. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
56373. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56374. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
56375. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56376. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
56377. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56378. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
56379. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56380. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
56381. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56382. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
56383. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56384. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
56385. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56386. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
56387. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56388. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
56389. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56390. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
56391. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56392. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
56393. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56394. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
56395. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56396. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
56397. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56398. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
56399. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56400. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
56401. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56402. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
56403. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56404. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
56405. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56406. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
56407. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56408. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
56409. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56410. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
56411. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56412. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
56413. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56414. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
56415. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56416. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
56417. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56418. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
56419. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56420. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
56421. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56422. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
56423. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56424. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
56425. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56426. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
56427. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56428. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
56429. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56430. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
56431. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56432. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
56433. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56434. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
56435. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56436. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
56437. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56438. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
56439. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56440. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
56441. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56442. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
56443. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56444. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
56445. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56446. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
56447. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56448. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
56449. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56450. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
56451. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56452. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
56453. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56454. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
56455. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56456. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
56457. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56458. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
56459. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56460. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
56461. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56462. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
56463. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56464. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
56465. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56466. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
56467. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56468. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
56469. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56470. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
56471. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56472. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
56473. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56474. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
56475. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56476. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
56477. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56478. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
56479. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56480. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
56481. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56482. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
56483. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56484. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
56485. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56486. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
56487. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56488. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
56489. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56490. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
56491. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56492. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
56493. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56494. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
56495. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56496. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
56497. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56498. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
56499. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56500. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
56501. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56502. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
56503. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56504. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
56505. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56506. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
56507. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56508. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
56509. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56510. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
56511. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56512. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
56513. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56514. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
56515. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56516. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
56517. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56518. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
56519. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56520. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
56521. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56522. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
56523. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56524. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
56525. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56526. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
56527. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56528. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
56529. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56530. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
56531. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56532. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
56533. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56534. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
56535. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56536. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
56537. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56538. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
56539. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56540. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
56541. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56542. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
56543. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56544. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
56545. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56546. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
56547. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56548. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
56549. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56550. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
56551. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56552. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
56553. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56554. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
56555. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56556. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
56557. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56558. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
56559. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56560. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
56561. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56562. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
56563. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56564. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
56565. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56566. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
56567. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56568. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
56569. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56570. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
56571. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56572. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
56573. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56574. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
56575. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56576. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
56577. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56578. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
56579. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56580. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
56581. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56582. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
56583. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56584. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
56585. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56586. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
56587. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56588. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
56589. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56590. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
56591. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56592. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
56593. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56594. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
56595. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56596. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
56597. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56598. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
56599. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56600. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
56601. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56602. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
56603. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56604. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
56605. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56606. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
56607. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56608. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
56609. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56610. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
56611. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56612. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
56613. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56614. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
56615. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56616. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
56617. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56618. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
56619. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56620. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
56621. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56622. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
56623. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56624. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
56625. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56626. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
56627. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56628. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
56629. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56630. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
56631. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56632. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
56633. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56634. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
56635. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56636. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
56637. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56638. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
56639. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56640. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
56641. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56642. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
56643. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56644. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
56645. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56646. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
56647. DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56648. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
56649. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56650. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
56651. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56652. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
56653. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56654. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
56655. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56656. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
56657. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56658. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
56659. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56660. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
56661. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56662. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
56663. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56664. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
56665. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56666. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
56667. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56668. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
56669. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56670. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
56671. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56672. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
56673. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56674. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
56675. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56676. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
56677. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56678. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
56679. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56680. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
56681. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56682. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
56683. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56684. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
56685. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56686. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
56687. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56688. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
56689. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56690. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
56691. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56692. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
56693. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56694. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
56695. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56696. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
56697. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56698. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
56699. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56700. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
56701. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56702. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
56703. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56704. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
56705. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56706. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
56707. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56708. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
56709. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56710. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
56711. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56712. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
56713. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56714. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
56715. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56716. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
56717. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56718. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
56719. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56720. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
56721. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56722. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
56723. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56724. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
56725. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56726. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
56727. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56728. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
56729. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56730. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
56731. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56732. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
56733. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56734. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
56735. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56736. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
56737. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56738. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
56739. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56740. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
56741. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56742. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
56743. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56744. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
56745. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56746. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
56747. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56748. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
56749. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56750. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
56751. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56752. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
56753. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56754. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
56755. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56756. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
56757. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56758. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
56759. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56760. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
56761. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56762. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
56763. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56764. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
56765. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56766. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
56767. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56768. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
56769. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56770. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
56771. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56772. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
56773. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56774. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
56775. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56776. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
56777. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56778. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
56779. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56780. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
56781. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56782. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
56783. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56784. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
56785. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56786. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
56787. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56788. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
56789. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56790. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
56791. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56792. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
56793. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56794. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
56795. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56796. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
56797. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56798. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
56799. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56800. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
56801. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56802. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
56803. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56804. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
56805. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56806. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
56807. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56808. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
56809. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56810. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
56811. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56812. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
56813. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56814. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
56815. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56816. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
56817. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56818. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
56819. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56820. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
56821. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56822. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
56823. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56824. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
56825. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56826. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
56827. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56828. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
56829. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56830. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
56831. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56832. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
56833. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56834. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
56835. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56836. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
56837. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56838. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
56839. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56840. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
56841. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56842. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
56843. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56844. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
56845. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56846. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
56847. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56848. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
56849. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56850. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
56851. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56852. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
56853. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56854. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
56855. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56856. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
56857. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56858. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
56859. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56860. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
56861. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56862. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
56863. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56864. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
56865. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56866. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
56867. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56868. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
56869. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56870. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
56871. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56872. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
56873. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56874. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
56875. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56876. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
56877. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56878. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
56879. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56880. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
56881. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56882. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
56883. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56884. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
56885. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56886. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
56887. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56888. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
56889. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56890. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
56891. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56892. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
56893. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56894. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
56895. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56896. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
56897. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56898. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
56899. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56900. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
56901. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56902. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
56903. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56904. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
56905. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56906. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
56907. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56908. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
56909. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56910. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
56911. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56912. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
56913. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56914. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
56915. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56916. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
56917. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56918. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
56919. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56920. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
56921. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56922. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
56923. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56924. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
56925. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56926. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
56927. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56928. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
56929. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56930. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
56931. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56932. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
56933. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56934. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
56935. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56936. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
56937. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56938. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
56939. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56940. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
56941. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56942. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
56943. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56944. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
56945. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56946. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
56947. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56948. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
56949. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56950. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
56951. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56952. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
56953. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56954. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
56955. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56956. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
56957. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56958. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
56959. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56960. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
56961. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56962. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
56963. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56964. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
56965. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56966. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
56967. DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56968. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
56969. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56970. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
56971. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56972. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
56973. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56974. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
56975. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56976. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
56977. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56978. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
56979. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56980. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
56981. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56982. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
56983. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56984. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
56985. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56986. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
56987. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56988. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
56989. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56990. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
56991. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56992. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
56993. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56994. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
56995. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56996. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
56997. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
56998. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
56999. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57000. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
57001. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57002. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
57003. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57004. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
57005. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57006. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
57007. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57008. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
57009. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57010. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
57011. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57012. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
57013. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57014. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
57015. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57016. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
57017. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57018. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
57019. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57020. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
57021. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57022. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
57023. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57024. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
57025. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57026. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
57027. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57028. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
57029. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57030. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
57031. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57032. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
57033. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57034. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
57035. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57036. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
57037. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57038. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
57039. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57040. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
57041. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57042. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
57043. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57044. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
57045. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57046. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
57047. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57048. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
57049. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57050. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
57051. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57052. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
57053. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57054. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
57055. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57056. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
57057. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57058. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
57059. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57060. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
57061. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57062. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
57063. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57064. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
57065. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57066. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
57067. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57068. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
57069. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57070. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
57071. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57072. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
57073. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57074. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
57075. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57076. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
57077. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57078. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
57079. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57080. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
57081. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57082. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
57083. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57084. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
57085. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57086. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
57087. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57088. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
57089. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57090. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
57091. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57092. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
57093. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57094. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
57095. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57096. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
57097. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57098. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
57099. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57100. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
57101. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57102. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
57103. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57104. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
57105. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57106. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
57107. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57108. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
57109. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57110. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
57111. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57112. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
57113. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57114. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
57115. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57116. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
57117. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57118. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
57119. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57120. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
57121. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57122. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
57123. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57124. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
57125. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57126. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
57127. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57128. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
57129. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57130. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
57131. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57132. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
57133. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57134. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
57135. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57136. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
57137. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57138. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
57139. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57140. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
57141. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57142. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
57143. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57144. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
57145. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57146. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
57147. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57148. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
57149. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57150. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
57151. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57152. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
57153. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57154. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
57155. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57156. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
57157. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57158. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
57159. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57160. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
57161. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57162. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
57163. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57164. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
57165. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57166. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
57167. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57168. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
57169. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57170. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
57171. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57172. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
57173. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57174. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
57175. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57176. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
57177. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57178. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
57179. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57180. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
57181. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57182. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
57183. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57184. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
57185. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57186. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
57187. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57188. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
57189. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57190. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
57191. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57192. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
57193. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57194. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
57195. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57196. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
57197. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57198. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
57199. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57200. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
57201. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57202. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
57203. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57204. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
57205. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57206. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
57207. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57208. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
57209. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57210. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
57211. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57212. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
57213. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57214. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
57215. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57216. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
57217. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57218. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
57219. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57220. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
57221. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57222. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
57223. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57224. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
57225. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57226. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
57227. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57228. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
57229. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57230. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
57231. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57232. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
57233. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57234. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
57235. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57236. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
57237. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57238. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
57239. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57240. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
57241. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57242. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
57243. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57244. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
57245. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57246. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
57247. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57248. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
57249. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57250. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
57251. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57252. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
57253. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57254. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
57255. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57256. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
57257. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57258. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
57259. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57260. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
57261. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57262. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
57263. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57264. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
57265. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57266. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
57267. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57268. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
57269. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57270. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
57271. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57272. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
57273. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57274. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
57275. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57276. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
57277. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57278. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
57279. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57280. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
57281. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57282. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
57283. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57284. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
57285. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57286. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
57287. DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
57288. DCIO_UNIPHYA_FBDIV_CLK
57289. DCIO_UNIPHYA_FBDIV_SSC_CLK
57290. DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2
57291. DCIO_UNIPHYA_TEST_REFDIV_CLK
57292. DCIO_UNIPHYB_FBDIV_CLK
57293. DCIO_UNIPHYB_FBDIV_SSC_CLK
57294. DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2
57295. DCIO_UNIPHYB_TEST_REFDIV_CLK
57296. DCIO_UNIPHYC_FBDIV_CLK
57297. DCIO_UNIPHYC_FBDIV_SSC_CLK
57298. DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2
57299. DCIO_UNIPHYC_TEST_REFDIV_CLK
57300. DCIO_UNIPHYD_FBDIV_CLK
57301. DCIO_UNIPHYD_FBDIV_SSC_CLK
57302. DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2
57303. DCIO_UNIPHYD_TEST_REFDIV_CLK
57304. DCIO_UNIPHYE_FBDIV_CLK
57305. DCIO_UNIPHYE_FBDIV_SSC_CLK
57306. DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2
57307. DCIO_UNIPHYE_TEST_REFDIV_CLK
57308. DCIO_UNIPHYF_FBDIV_CLK
57309. DCIO_UNIPHYF_FBDIV_SSC_CLK
57310. DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2
57311. DCIO_UNIPHYF_TEST_REFDIV_CLK
57312. DCIO_UNIPHYG_FBDIV_CLK
57313. DCIO_UNIPHYG_FBDIV_SSC_CLK
57314. DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2
57315. DCIO_UNIPHYG_TEST_REFDIV_CLK
57316. DCIO_UNIPHYLPA_FBDIV_CLK
57317. DCIO_UNIPHYLPA_FBDIV_SSC_CLK
57318. DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2
57319. DCIO_UNIPHYLPA_TEST_REFDIV_CLK
57320. DCIO_UNIPHYLPB_FBDIV_CLK
57321. DCIO_UNIPHYLPB_FBDIV_SSC_CLK
57322. DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2
57323. DCIO_UNIPHYLPB_TEST_REFDIV_CLK
57324. DCIO_UNIPHY_CHANNEL_INVERTED
57325. DCIO_UNIPHY_CHANNEL_NO_INVERSION
57326. DCIO_UNIPHY_CHANNEL_XBAR_SOURCE
57327. DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0
57328. DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1
57329. DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2
57330. DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3
57331. DCIO_UNIPHY_IMPCAL_SEL
57332. DCIO_UNIPHY_IMPCAL_SEL_BINARY
57333. DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE
57334. DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT
57335. DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK
57336. DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION
57337. DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW
57338. DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED
57339. DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED
57340. DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW
57341. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS
57342. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS
57343. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS
57344. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS
57345. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS
57346. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS
57347. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS
57348. DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS
57349. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN_MASK
57350. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN__SHIFT
57351. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN_MASK
57352. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN__SHIFT
57353. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN_MASK
57354. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN__SHIFT
57355. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN_MASK
57356. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN__SHIFT
57357. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN_MASK
57358. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN__SHIFT
57359. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN_MASK
57360. DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN__SHIFT
57361. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYA_USBC_FLIP_EN_SEL_MASK
57362. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYA_USBC_FLIP_EN_SEL__SHIFT
57363. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYB_USBC_FLIP_EN_SEL_MASK
57364. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYB_USBC_FLIP_EN_SEL__SHIFT
57365. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYC_USBC_FLIP_EN_SEL_MASK
57366. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYC_USBC_FLIP_EN_SEL__SHIFT
57367. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYD_USBC_FLIP_EN_SEL_MASK
57368. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYD_USBC_FLIP_EN_SEL__SHIFT
57369. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYE_USBC_FLIP_EN_SEL_MASK
57370. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYE_USBC_FLIP_EN_SEL__SHIFT
57371. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYF_USBC_FLIP_EN_SEL_MASK
57372. DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYF_USBC_FLIP_EN_SEL__SHIFT
57373. DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE
57374. DCIO_VIP_ALTER_MAPPING_EN_DEFAULT
57375. DCIO_VIP_MUX_EN_DVO
57376. DCIO_VIP_MUX_EN_VIP
57377. DCIO_WRCMD_DELAY__DAC_DELAY_MASK
57378. DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT
57379. DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK
57380. DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT
57381. DCIO_WRCMD_DELAY__DPHY_DELAY_MASK
57382. DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT
57383. DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK
57384. DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT
57385. DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK
57386. DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT
57387. DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE_MASK
57388. DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE__SHIFT
57389. DCI_CLK_CNTL2__DCEFCLK_GATE_DIS_MASK
57390. DCI_CLK_CNTL2__DCEFCLK_GATE_DIS__SHIFT
57391. DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY_MASK
57392. DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY__SHIFT
57393. DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY_MASK
57394. DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY__SHIFT
57395. DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK
57396. DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT
57397. DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK
57398. DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT
57399. DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK
57400. DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT
57401. DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS_MASK
57402. DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT
57403. DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS_MASK
57404. DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT
57405. DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS_MASK
57406. DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT
57407. DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS_MASK
57408. DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS__SHIFT
57409. DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS_MASK
57410. DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS__SHIFT
57411. DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK
57412. DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT
57413. DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK
57414. DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT
57415. DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK
57416. DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT
57417. DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK
57418. DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT
57419. DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK
57420. DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT
57421. DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK
57422. DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT
57423. DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK
57424. DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT
57425. DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK
57426. DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT
57427. DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK
57428. DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT
57429. DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS_MASK
57430. DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS__SHIFT
57431. DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS_MASK
57432. DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS__SHIFT
57433. DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS_MASK
57434. DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS__SHIFT
57435. DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS_MASK
57436. DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS__SHIFT
57437. DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK
57438. DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT
57439. DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK
57440. DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT
57441. DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK
57442. DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT
57443. DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK
57444. DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT
57445. DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK
57446. DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT
57447. DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK
57448. DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT
57449. DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK
57450. DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT
57451. DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK
57452. DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT
57453. DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK
57454. DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT
57455. DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK
57456. DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT
57457. DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK
57458. DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT
57459. DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK
57460. DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT
57461. DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK
57462. DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT
57463. DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK
57464. DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT
57465. DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK
57466. DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT
57467. DCI_CLK_CNTL__VPCLK_POL_MASK
57468. DCI_CLK_CNTL__VPCLK_POL__SHIFT
57469. DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK
57470. DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT
57471. DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK
57472. DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT
57473. DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK
57474. DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT
57475. DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK
57476. DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT
57477. DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK
57478. DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT
57479. DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK
57480. DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT
57481. DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK
57482. DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT
57483. DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK
57484. DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT
57485. DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK
57486. DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT
57487. DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK
57488. DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT
57489. DCI_HWID
57490. DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK
57491. DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT
57492. DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK
57493. DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT
57494. DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK
57495. DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT
57496. DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK
57497. DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT
57498. DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK
57499. DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT
57500. DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK
57501. DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT
57502. DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK
57503. DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT
57504. DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK
57505. DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT
57506. DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK
57507. DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT
57508. DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK
57509. DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT
57510. DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK
57511. DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT
57512. DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK
57513. DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT
57514. DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK
57515. DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT
57516. DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK
57517. DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT
57518. DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK
57519. DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT
57520. DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK
57521. DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT
57522. DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK
57523. DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT
57524. DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK
57525. DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT
57526. DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK
57527. DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT
57528. DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK
57529. DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT
57530. DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK
57531. DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT
57532. DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK
57533. DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT
57534. DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK
57535. DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT
57536. DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK
57537. DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT
57538. DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK
57539. DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT
57540. DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK
57541. DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT
57542. DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK
57543. DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT
57544. DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK
57545. DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT
57546. DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK
57547. DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT
57548. DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK
57549. DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT
57550. DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK
57551. DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT
57552. DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK
57553. DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT
57554. DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK
57555. DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT
57556. DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK
57557. DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT
57558. DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK
57559. DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT
57560. DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK
57561. DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT
57562. DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK
57563. DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT
57564. DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK
57565. DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT
57566. DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK
57567. DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT
57568. DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK
57569. DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT
57570. DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK
57571. DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT
57572. DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK
57573. DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT
57574. DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK
57575. DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT
57576. DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK
57577. DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT
57578. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS_MASK
57579. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS__SHIFT
57580. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE_MASK
57581. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE__SHIFT
57582. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS_MASK
57583. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS__SHIFT
57584. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE_MASK
57585. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE__SHIFT
57586. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL_MASK
57587. DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL__SHIFT
57588. DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM_MASK
57589. DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM__SHIFT
57590. DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM_MASK
57591. DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM__SHIFT
57592. DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM_MASK
57593. DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM__SHIFT
57594. DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM_MASK
57595. DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM__SHIFT
57596. DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM_MASK
57597. DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM__SHIFT
57598. DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM_MASK
57599. DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM__SHIFT
57600. DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK
57601. DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT
57602. DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK
57603. DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT
57604. DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK
57605. DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT
57606. DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK
57607. DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT
57608. DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK
57609. DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT
57610. DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK
57611. DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT
57612. DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK
57613. DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT
57614. DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK
57615. DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT
57616. DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK
57617. DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT
57618. DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK
57619. DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT
57620. DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK
57621. DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT
57622. DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK
57623. DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT
57624. DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK
57625. DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT
57626. DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK
57627. DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT
57628. DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK
57629. DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT
57630. DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK
57631. DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT
57632. DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK
57633. DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT
57634. DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK
57635. DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT
57636. DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK
57637. DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT
57638. DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK
57639. DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT
57640. DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK
57641. DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT
57642. DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK
57643. DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT
57644. DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK
57645. DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT
57646. DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK
57647. DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT
57648. DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK
57649. DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT
57650. DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK
57651. DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT
57652. DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK
57653. DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT
57654. DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK
57655. DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT
57656. DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK
57657. DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT
57658. DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK
57659. DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT
57660. DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK
57661. DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT
57662. DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK
57663. DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT
57664. DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK
57665. DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT
57666. DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK
57667. DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT
57668. DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK
57669. DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT
57670. DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK
57671. DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT
57672. DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK
57673. DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT
57674. DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK
57675. DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT
57676. DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK
57677. DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT
57678. DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK
57679. DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT
57680. DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK
57681. DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT
57682. DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK
57683. DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT
57684. DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK
57685. DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT
57686. DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK
57687. DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT
57688. DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK
57689. DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT
57690. DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK
57691. DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT
57692. DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK
57693. DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT
57694. DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK
57695. DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT
57696. DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK
57697. DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT
57698. DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK
57699. DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT
57700. DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK
57701. DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT
57702. DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK
57703. DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT
57704. DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK
57705. DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT
57706. DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK
57707. DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT
57708. DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK
57709. DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT
57710. DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK
57711. DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT
57712. DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK
57713. DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT
57714. DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE_MASK
57715. DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE__SHIFT
57716. DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK
57717. DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT
57718. DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK
57719. DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT
57720. DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK
57721. DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT
57722. DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK
57723. DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT
57724. DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK
57725. DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT
57726. DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK
57727. DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT
57728. DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK
57729. DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT
57730. DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK
57731. DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT
57732. DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK
57733. DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT
57734. DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK
57735. DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT
57736. DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK
57737. DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT
57738. DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK
57739. DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT
57740. DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK
57741. DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT
57742. DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK
57743. DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT
57744. DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK
57745. DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT
57746. DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK
57747. DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT
57748. DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK
57749. DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT
57750. DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK
57751. DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT
57752. DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE_MASK
57753. DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE__SHIFT
57754. DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE_MASK
57755. DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE__SHIFT
57756. DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE_MASK
57757. DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE__SHIFT
57758. DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE_MASK
57759. DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE__SHIFT
57760. DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE_MASK
57761. DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE__SHIFT
57762. DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE_MASK
57763. DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE__SHIFT
57764. DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE_MASK
57765. DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE__SHIFT
57766. DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE_MASK
57767. DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE__SHIFT
57768. DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE_MASK
57769. DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE__SHIFT
57770. DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE_MASK
57771. DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE__SHIFT
57772. DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE_MASK
57773. DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE__SHIFT
57774. DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE_MASK
57775. DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE__SHIFT
57776. DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK
57777. DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT
57778. DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK
57779. DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT
57780. DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK
57781. DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT
57782. DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK
57783. DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT
57784. DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK
57785. DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT
57786. DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE_MASK
57787. DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE__SHIFT
57788. DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE_MASK
57789. DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE__SHIFT
57790. DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK
57791. DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT
57792. DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK
57793. DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT
57794. DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM3_PWR_STATE_MASK
57795. DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM3_PWR_STATE__SHIFT
57796. DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK
57797. DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT
57798. DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK
57799. DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT
57800. DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK
57801. DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT
57802. DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK
57803. DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT
57804. DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK
57805. DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT
57806. DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK
57807. DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT
57808. DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK
57809. DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT
57810. DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK
57811. DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT
57812. DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK
57813. DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT
57814. DCI_MISC__MCIF_WB_URG_LVL_MASK
57815. DCI_MISC__MCIF_WB_URG_LVL__SHIFT
57816. DCI_MISC__MCIF_WB_URG_OVRD_MASK
57817. DCI_MISC__MCIF_WB_URG_OVRD__SHIFT
57818. DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK
57819. DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT
57820. DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK
57821. DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT
57822. DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK
57823. DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT
57824. DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET_MASK
57825. DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET__SHIFT
57826. DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET_MASK
57827. DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET__SHIFT
57828. DCI_SOFT_RESET__DCHUB_SOFT_RESET_MASK
57829. DCI_SOFT_RESET__DCHUB_SOFT_RESET__SHIFT
57830. DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK
57831. DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT
57832. DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK
57833. DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT
57834. DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK
57835. DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT
57836. DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK
57837. DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT
57838. DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK
57839. DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT
57840. DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK
57841. DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT
57842. DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK
57843. DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT
57844. DCI_SOFT_RESET__FBC_SOFT_RESET_MASK
57845. DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT
57846. DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK
57847. DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT
57848. DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK
57849. DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT
57850. DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK
57851. DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT
57852. DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK
57853. DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT
57854. DCI_SOFT_RESET__MCIF_WB_SOFT_RESET_MASK
57855. DCI_SOFT_RESET__MCIF_WB_SOFT_RESET__SHIFT
57856. DCI_SOFT_RESET__VGA_SOFT_RESET_MASK
57857. DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT
57858. DCI_SOFT_RESET__VIP_SOFT_RESET_MASK
57859. DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT
57860. DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK
57861. DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT
57862. DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK
57863. DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT
57864. DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK
57865. DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT
57866. DCLK
57867. DCLKCON_DCLK0_CMP_SHIFT
57868. DCLKCON_DCLK0_DIV_SHIFT
57869. DCLKCON_DCLK1_CMP_SHIFT
57870. DCLKCON_DCLK1_DIV_SHIFT
57871. DCLKCON_DCLK_DIV_MASK
57872. DCLKIN_MARK
57873. DCLKOUT_MARK
57874. DCLK_0D
57875. DCLK_0DS
57876. DCLK_1D
57877. DCLK_2D
57878. DCLK_CM0S_PMU
57879. DCLK_DIR_CNTL_EN
57880. DCLK_DIVIDER_MASK
57881. DCLK_EBC
57882. DCLK_HDMIPHY
57883. DCLK_HDMI_PHY
57884. DCLK_INVERT
57885. DCLK_LCDC
57886. DCLK_LCDC0
57887. DCLK_LCDC1
57888. DCLK_LCDC_SRC
57889. DCLK_M0_PERILP
57890. DCLK_MAX_CLKS
57891. DCLK_SRC_SEL
57892. DCLK_SRC_SEL_MASK
57893. DCLK_STATUS
57894. DCLK_VOP
57895. DCLK_VOP0
57896. DCLK_VOP0_DIV
57897. DCLK_VOP0_FRAC
57898. DCLK_VOP1
57899. DCLK_VOP1_DIV
57900. DCLK_VOP1_FRAC
57901. DCLK_VOPB
57902. DCLK_VOPL
57903. DCLK_VOP_SRC
57904. DCLR0
57905. DCLR1
57906. DCLRKV
57907. DCLRM
57908. DCL_DEBUG
57909. DCM
57910. DCMD
57911. DCMD_BURST16
57912. DCMD_BURST32
57913. DCMD_BURST8
57914. DCMD_ENDIAN
57915. DCMD_ENDIRQEN
57916. DCMD_FAILED
57917. DCMD_FLOWSRC
57918. DCMD_FLOWTRG
57919. DCMD_INCSRCADDR
57920. DCMD_INCTRGADDR
57921. DCMD_LENGTH
57922. DCMD_NOT_FIRED
57923. DCMD_Printf
57924. DCMD_REG
57925. DCMD_RESP_TIMEOUT
57926. DCMD_RETURN_STATUS
57927. DCMD_SLOT
57928. DCMD_STARTIRQEN
57929. DCMD_SUCCESS
57930. DCMD_TIMEOUT
57931. DCMD_TIMEOUT_ACTION
57932. DCMD_TXCMD_OP
57933. DCMD_WIDTH1
57934. DCMD_WIDTH2
57935. DCMD_WIDTH4
57936. DCMI
57937. DCMI_CR
57938. DCMI_CWSIZE
57939. DCMI_CWSTRT
57940. DCMI_DR
57941. DCMI_ESCR
57942. DCMI_ESUR
57943. DCMI_ICR
57944. DCMI_IDR
57945. DCMI_IER
57946. DCMI_MIS
57947. DCMI_RIS
57948. DCMI_SR
57949. DCMLR
57950. DCMPS_CHANGE
57951. DCMPS_CHANGE_DONE
57952. DCMPS_CURRENT_PHASE
57953. DCMPS_ERROR
57954. DCMP_CLOCK_GATE_DISABLE
57955. DCMR
57956. DCMWR
57957. DCMX
57958. DCMXS
57959. DCM_208M
57960. DCM_CFG_mskBSAV
57961. DCM_CFG_mskDLCK
57962. DCM_CFG_mskDLMB
57963. DCM_CFG_mskDSET
57964. DCM_CFG_mskDSZ
57965. DCM_CFG_mskDWAY
57966. DCM_CFG_offBSAV
57967. DCM_CFG_offDLCK
57968. DCM_CFG_offDLMB
57969. DCM_CFG_offDSET
57970. DCM_CFG_offDSZ
57971. DCM_CFG_offDWAY
57972. DCM_DRP_CFG
57973. DCM_DRP_CTL
57974. DCM_DRP_RD_DATA_H
57975. DCM_DRP_RD_DATA_L
57976. DCM_DRP_TRIG
57977. DCM_DRP_WR_DATA_H
57978. DCM_DRP_WR_DATA_L
57979. DCM_HIGH_FREQUENCY_MODE
57980. DCM_HIGH_FREQUENCY_MODE_SET
57981. DCM_LOCKED
57982. DCM_LOW_FREQUENCY_MODE
57983. DCM_Low_FREQUENCY_MODE_SET
57984. DCM_READ_ADDRESS_00
57985. DCM_READ_ADDRESS_51
57986. DCM_RESET
57987. DCM_RX
57988. DCM_SHIFT
57989. DCM_TX
57990. DCM_WRITE_ADDRESS_50
57991. DCM_WRITE_ADDRESS_51
57992. DCN101_CLK_SRC_TOTAL
57993. DCN10STRENC_FROM_STRENC
57994. DCN10TG_FROM_TG
57995. DCN10_CLK_SRC_PLL0
57996. DCN10_CLK_SRC_PLL1
57997. DCN10_CLK_SRC_PLL2
57998. DCN10_CLK_SRC_PLL3
57999. DCN10_CLK_SRC_TOTAL
58000. DCN10_DIG_FE_SOURCE_SELECT_DIGA
58001. DCN10_DIG_FE_SOURCE_SELECT_DIGB
58002. DCN10_DIG_FE_SOURCE_SELECT_DIGC
58003. DCN10_DIG_FE_SOURCE_SELECT_DIGD
58004. DCN10_DIG_FE_SOURCE_SELECT_DIGE
58005. DCN10_DIG_FE_SOURCE_SELECT_DIGF
58006. DCN10_DIG_FE_SOURCE_SELECT_DIGG
58007. DCN10_DIG_FE_SOURCE_SELECT_INVALID
58008. DCN20_CLK_SRC_PLL0
58009. DCN20_CLK_SRC_PLL1
58010. DCN20_CLK_SRC_PLL2
58011. DCN20_CLK_SRC_PLL3
58012. DCN20_CLK_SRC_PLL4
58013. DCN20_CLK_SRC_PLL5
58014. DCN20_CLK_SRC_TOTAL
58015. DCN20_CLK_SRC_TOTAL_DCN21
58016. DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST
58017. DCN20_LINK_ENCODER_REG_FIELD_LIST
58018. DCN20_MAX_DISPLAY_CLOCK_Mhz
58019. DCN20_MAX_PIXEL_CLOCK_Mhz
58020. DCN20_VMID_MASK_SH_LIST
58021. DCN20_VMID_REG_FIELD_LIST
58022. DCN20_VMID_REG_LIST
58023. DCN21_HUBP_REG_COMMON_VARIABLE_LIST
58024. DCN21_HUBP_REG_FIELD_VARIABLE_LIST
58025. DCN2_AUX_REG_LIST
58026. DCN2_HUBP_REG_COMMON_VARIABLE_LIST
58027. DCN2_HUBP_REG_FIELD_VARIABLE_LIST
58028. DCNT
58029. DCNTL_REG
58030. DCNTPERR_F
58031. DCNTPERR_S
58032. DCNTPERR_V
58033. DCNT_S
58034. DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT
58035. DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT
58036. DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT
58037. DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT
58038. DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT
58039. DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT
58040. DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT
58041. DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT
58042. DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT
58043. DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT
58044. DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT
58045. DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT
58046. DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT
58047. DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT
58048. DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT
58049. DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT
58050. DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT
58051. DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT
58052. DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT
58053. DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT
58054. DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT
58055. DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT
58056. DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT
58057. DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT
58058. DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS
58059. DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS
58060. DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt
58061. DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt
58062. DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int
58063. DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int
58064. DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int
58065. DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int
58066. DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int
58067. DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int
58068. DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS
58069. DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS
58070. DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS
58071. DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS
58072. DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT
58073. DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT
58074. DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT
58075. DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT
58076. DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT
58077. DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT
58078. DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT
58079. DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT
58080. DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT
58081. DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT
58082. DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT
58083. DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT
58084. DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT
58085. DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT
58086. DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT
58087. DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT
58088. DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT
58089. DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT
58090. DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT
58091. DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT
58092. DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT
58093. DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT
58094. DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT
58095. DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT
58096. DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT
58097. DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT
58098. DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT
58099. DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT
58100. DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT
58101. DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT
58102. DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT
58103. DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT
58104. DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT
58105. DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT
58106. DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT
58107. DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT
58108. DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT
58109. DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT
58110. DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT
58111. DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT
58112. DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR
58113. DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE
58114. DCN_1_0__CTXID__DC_AUX1_LS_DONE
58115. DCN_1_0__CTXID__DC_AUX1_SW_DONE
58116. DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR
58117. DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE
58118. DCN_1_0__CTXID__DC_AUX2_LS_DONE
58119. DCN_1_0__CTXID__DC_AUX2_SW_DONE
58120. DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR
58121. DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE
58122. DCN_1_0__CTXID__DC_AUX3_LS_DONE
58123. DCN_1_0__CTXID__DC_AUX3_SW_DONE
58124. DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR
58125. DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE
58126. DCN_1_0__CTXID__DC_AUX4_LS_DONE
58127. DCN_1_0__CTXID__DC_AUX4_SW_DONE
58128. DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR
58129. DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE
58130. DCN_1_0__CTXID__DC_AUX5_LS_DONE
58131. DCN_1_0__CTXID__DC_AUX5_SW_DONE
58132. DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR
58133. DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE
58134. DCN_1_0__CTXID__DC_AUX6_LS_DONE
58135. DCN_1_0__CTXID__DC_AUX6_SW_DONE
58136. DCN_1_0__CTXID__DC_D1_FORCE_CNT_W
58137. DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE
58138. DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A
58139. DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B
58140. DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP
58141. DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT
58142. DCN_1_0__CTXID__DC_D1_VBLANK
58143. DCN_1_0__CTXID__DC_D1_VLINE1
58144. DCN_1_0__CTXID__DC_D1_VLINE2
58145. DCN_1_0__CTXID__DC_D2_FORCE_CNT_W
58146. DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE
58147. DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A
58148. DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B
58149. DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP
58150. DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT
58151. DCN_1_0__CTXID__DC_D2_VBLANK
58152. DCN_1_0__CTXID__DC_D2_VLINE1
58153. DCN_1_0__CTXID__DC_D2_VLINE2
58154. DCN_1_0__CTXID__DC_D3_FORCE_CNT_W
58155. DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE
58156. DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A
58157. DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B
58158. DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP
58159. DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT
58160. DCN_1_0__CTXID__DC_D3_VBLANK
58161. DCN_1_0__CTXID__DC_D3_VLINE1
58162. DCN_1_0__CTXID__DC_D3_VLINE2
58163. DCN_1_0__CTXID__DC_D4_FORCE_CNT_W
58164. DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE
58165. DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A
58166. DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B
58167. DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP
58168. DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT
58169. DCN_1_0__CTXID__DC_D4_VBLANK
58170. DCN_1_0__CTXID__DC_D4_VLINE1
58171. DCN_1_0__CTXID__DC_D4_VLINE2
58172. DCN_1_0__CTXID__DC_D5_FORCE_CNT_W
58173. DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE
58174. DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A
58175. DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B
58176. DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP
58177. DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT
58178. DCN_1_0__CTXID__DC_D5_VBLANK
58179. DCN_1_0__CTXID__DC_D5_VLINE1
58180. DCN_1_0__CTXID__DC_D5_VLINE2
58181. DCN_1_0__CTXID__DC_D6_FORCE_CNT_W
58182. DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE
58183. DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A
58184. DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B
58185. DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP
58186. DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT
58187. DCN_1_0__CTXID__DC_D6_VBLANK
58188. DCN_1_0__CTXID__DC_D6_VLINE1
58189. DCN_1_0__CTXID__DC_D6_VLINE2
58190. DCN_1_0__CTXID__DC_D7_VBLANK
58191. DCN_1_0__CTXID__DC_D7_VLINE1
58192. DCN_1_0__CTXID__DC_D7_VLINE2
58193. DCN_1_0__CTXID__DC_D8_VBLANK
58194. DCN_1_0__CTXID__DC_D8_VLINE1
58195. DCN_1_0__CTXID__DC_D8_VLINE2
58196. DCN_1_0__CTXID__DC_DAC_A_AUTO_DET
58197. DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT
58198. DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE
58199. DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT
58200. DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE
58201. DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT
58202. DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE
58203. DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT
58204. DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE
58205. DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT
58206. DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE
58207. DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT
58208. DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE
58209. DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT
58210. DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE
58211. DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT
58212. DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE
58213. DCN_1_0__CTXID__DC_HPD1_INT
58214. DCN_1_0__CTXID__DC_HPD1_RX_INT
58215. DCN_1_0__CTXID__DC_HPD2_INT
58216. DCN_1_0__CTXID__DC_HPD2_RX_INT
58217. DCN_1_0__CTXID__DC_HPD3_INT
58218. DCN_1_0__CTXID__DC_HPD3_RX_INT
58219. DCN_1_0__CTXID__DC_HPD4_INT
58220. DCN_1_0__CTXID__DC_HPD4_RX_INT
58221. DCN_1_0__CTXID__DC_HPD5_INT
58222. DCN_1_0__CTXID__DC_HPD5_RX_INT
58223. DCN_1_0__CTXID__DC_HPD6_INT
58224. DCN_1_0__CTXID__DC_HPD6_RX_INT
58225. DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE
58226. DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST
58227. DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE
58228. DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST
58229. DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE
58230. DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST
58231. DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE
58232. DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST
58233. DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE
58234. DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST
58235. DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE
58236. DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST
58237. DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE
58238. DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST
58239. DCN_1_0__CTXID__DC_I2C_SW_DONE
58240. DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS
58241. DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS
58242. DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT
58243. DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT
58244. DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT
58245. DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT
58246. DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT
58247. DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT
58248. DCN_1_0__CTXID__DMCU_INTERNAL_INT
58249. DCN_1_0__CTXID__DMCU_SCP_INT
58250. DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS
58251. DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS
58252. DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT
58253. DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS
58254. DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS
58255. DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS
58256. DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS
58257. DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS
58258. DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS
58259. DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS
58260. DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS
58261. DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS
58262. DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS
58263. DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS
58264. DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS
58265. DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS
58266. DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS
58267. DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS
58268. DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS
58269. DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST
58270. DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS
58271. DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS
58272. DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR
58273. DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS
58274. DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS
58275. DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR
58276. DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS
58277. DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS
58278. DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR
58279. DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS
58280. DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS
58281. DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR
58282. DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS
58283. DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS
58284. DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR
58285. DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS
58286. DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS
58287. DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR
58288. DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS
58289. DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS
58290. DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR
58291. DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS
58292. DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS
58293. DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR
58294. DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS
58295. DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS
58296. DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT
58297. DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT
58298. DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS
58299. DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS
58300. DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT
58301. DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT
58302. DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT
58303. DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT
58304. DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT
58305. DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT
58306. DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT
58307. DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT
58308. DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS
58309. DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS
58310. DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS
58311. DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS
58312. DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT
58313. DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT
58314. DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT
58315. DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT
58316. DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT
58317. DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT
58318. DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS
58319. DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS
58320. DCN_1_0__CTXID__OTG1_CPU_SS_INT
58321. DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58322. DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58323. DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58324. DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE
58325. DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT
58326. DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL
58327. DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL
58328. DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL
58329. DCN_1_0__CTXID__OTG2_CPU_SS_INT
58330. DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58331. DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58332. DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58333. DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE
58334. DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT
58335. DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL
58336. DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL
58337. DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL
58338. DCN_1_0__CTXID__OTG3_CPU_SS_INT
58339. DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58340. DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58341. DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58342. DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE
58343. DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT
58344. DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL
58345. DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL
58346. DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL
58347. DCN_1_0__CTXID__OTG4_CPU_SS_INT
58348. DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58349. DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58350. DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58351. DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE
58352. DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT
58353. DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL
58354. DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL
58355. DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL
58356. DCN_1_0__CTXID__OTG5_CPU_SS_INT
58357. DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58358. DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58359. DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58360. DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE
58361. DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT
58362. DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL
58363. DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL
58364. DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL
58365. DCN_1_0__CTXID__OTG6_CPU_SS_INT
58366. DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58367. DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58368. DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58369. DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE
58370. DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT
58371. DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL
58372. DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL
58373. DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL
58374. DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT
58375. DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS
58376. DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS
58377. DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS
58378. DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS
58379. DCN_1_0__CTXID__VGA_CRT_INT
58380. DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS
58381. DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS
58382. DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS
58383. DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS
58384. DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT
58385. DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT
58386. DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT
58387. DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT
58388. DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT
58389. DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT
58390. DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT
58391. DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT
58392. DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT
58393. DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT
58394. DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT
58395. DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT
58396. DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT
58397. DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT
58398. DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT
58399. DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT
58400. DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT
58401. DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT
58402. DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT
58403. DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT
58404. DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT
58405. DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT
58406. DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT
58407. DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT
58408. DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS
58409. DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS
58410. DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt
58411. DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt
58412. DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int
58413. DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int
58414. DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int
58415. DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int
58416. DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int
58417. DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int
58418. DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS
58419. DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS
58420. DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS
58421. DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS
58422. DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT
58423. DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT
58424. DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT
58425. DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT
58426. DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT
58427. DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT
58428. DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT
58429. DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT
58430. DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT
58431. DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT
58432. DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT
58433. DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT
58434. DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT
58435. DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT
58436. DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT
58437. DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT
58438. DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT
58439. DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT
58440. DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT
58441. DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT
58442. DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT
58443. DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT
58444. DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT
58445. DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT
58446. DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT
58447. DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT
58448. DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT
58449. DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT
58450. DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT
58451. DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT
58452. DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT
58453. DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT
58454. DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT
58455. DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT
58456. DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT
58457. DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT
58458. DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT
58459. DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT
58460. DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT
58461. DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT
58462. DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR
58463. DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE
58464. DCN_1_0__SRCID__DC_AUX1_LS_DONE
58465. DCN_1_0__SRCID__DC_AUX1_SW_DONE
58466. DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR
58467. DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE
58468. DCN_1_0__SRCID__DC_AUX2_LS_DONE
58469. DCN_1_0__SRCID__DC_AUX2_SW_DONE
58470. DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR
58471. DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE
58472. DCN_1_0__SRCID__DC_AUX3_LS_DONE
58473. DCN_1_0__SRCID__DC_AUX3_SW_DONE
58474. DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR
58475. DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE
58476. DCN_1_0__SRCID__DC_AUX4_LS_DONE
58477. DCN_1_0__SRCID__DC_AUX4_SW_DONE
58478. DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR
58479. DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE
58480. DCN_1_0__SRCID__DC_AUX5_LS_DONE
58481. DCN_1_0__SRCID__DC_AUX5_SW_DONE
58482. DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR
58483. DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE
58484. DCN_1_0__SRCID__DC_AUX6_LS_DONE
58485. DCN_1_0__SRCID__DC_AUX6_SW_DONE
58486. DCN_1_0__SRCID__DC_D1_FORCE_CNT_W
58487. DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE
58488. DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A
58489. DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B
58490. DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP
58491. DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT
58492. DCN_1_0__SRCID__DC_D1_OTG_VREADY
58493. DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP
58494. DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE
58495. DCN_1_0__SRCID__DC_D1_VBLANK
58496. DCN_1_0__SRCID__DC_D1_VLINE1
58497. DCN_1_0__SRCID__DC_D1_VLINE2
58498. DCN_1_0__SRCID__DC_D2_FORCE_CNT_W
58499. DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE
58500. DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A
58501. DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B
58502. DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP
58503. DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT
58504. DCN_1_0__SRCID__DC_D2_OTG_VREADY
58505. DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP
58506. DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE
58507. DCN_1_0__SRCID__DC_D2_VBLANK
58508. DCN_1_0__SRCID__DC_D2_VLINE1
58509. DCN_1_0__SRCID__DC_D2_VLINE2
58510. DCN_1_0__SRCID__DC_D3_FORCE_CNT_W
58511. DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE
58512. DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A
58513. DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B
58514. DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP
58515. DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT
58516. DCN_1_0__SRCID__DC_D3_OTG_VREADY
58517. DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP
58518. DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE
58519. DCN_1_0__SRCID__DC_D3_VBLANK
58520. DCN_1_0__SRCID__DC_D3_VLINE1
58521. DCN_1_0__SRCID__DC_D3_VLINE2
58522. DCN_1_0__SRCID__DC_D4_FORCE_CNT_W
58523. DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE
58524. DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A
58525. DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B
58526. DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP
58527. DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT
58528. DCN_1_0__SRCID__DC_D4_OTG_VREADY
58529. DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP
58530. DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE
58531. DCN_1_0__SRCID__DC_D4_VBLANK
58532. DCN_1_0__SRCID__DC_D4_VLINE1
58533. DCN_1_0__SRCID__DC_D4_VLINE2
58534. DCN_1_0__SRCID__DC_D5_FORCE_CNT_W
58535. DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE
58536. DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A
58537. DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B
58538. DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP
58539. DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT
58540. DCN_1_0__SRCID__DC_D5_OTG_VREADY
58541. DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP
58542. DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE
58543. DCN_1_0__SRCID__DC_D5_VBLANK
58544. DCN_1_0__SRCID__DC_D5_VLINE1
58545. DCN_1_0__SRCID__DC_D5_VLINE2
58546. DCN_1_0__SRCID__DC_D6_FORCE_CNT_W
58547. DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE
58548. DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A
58549. DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B
58550. DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP
58551. DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT
58552. DCN_1_0__SRCID__DC_D6_OTG_VREADY
58553. DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP
58554. DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE
58555. DCN_1_0__SRCID__DC_D6_VBLANK
58556. DCN_1_0__SRCID__DC_D6_VLINE1
58557. DCN_1_0__SRCID__DC_D6_VLINE2
58558. DCN_1_0__SRCID__DC_D7_VBLANK
58559. DCN_1_0__SRCID__DC_D7_VLINE1
58560. DCN_1_0__SRCID__DC_D7_VLINE2
58561. DCN_1_0__SRCID__DC_D8_VBLANK
58562. DCN_1_0__SRCID__DC_D8_VLINE1
58563. DCN_1_0__SRCID__DC_D8_VLINE2
58564. DCN_1_0__SRCID__DC_DAC_A_AUTO_DET
58565. DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT
58566. DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE
58567. DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT
58568. DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE
58569. DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT
58570. DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE
58571. DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT
58572. DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE
58573. DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT
58574. DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE
58575. DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT
58576. DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE
58577. DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT
58578. DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE
58579. DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT
58580. DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE
58581. DCN_1_0__SRCID__DC_HPD1_INT
58582. DCN_1_0__SRCID__DC_HPD1_RX_INT
58583. DCN_1_0__SRCID__DC_HPD2_INT
58584. DCN_1_0__SRCID__DC_HPD2_RX_INT
58585. DCN_1_0__SRCID__DC_HPD3_INT
58586. DCN_1_0__SRCID__DC_HPD3_RX_INT
58587. DCN_1_0__SRCID__DC_HPD4_INT
58588. DCN_1_0__SRCID__DC_HPD4_RX_INT
58589. DCN_1_0__SRCID__DC_HPD5_INT
58590. DCN_1_0__SRCID__DC_HPD5_RX_INT
58591. DCN_1_0__SRCID__DC_HPD6_INT
58592. DCN_1_0__SRCID__DC_HPD6_RX_INT
58593. DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE
58594. DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST
58595. DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE
58596. DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST
58597. DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE
58598. DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST
58599. DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE
58600. DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST
58601. DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE
58602. DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST
58603. DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE
58604. DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST
58605. DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE
58606. DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST
58607. DCN_1_0__SRCID__DC_I2C_SW_DONE
58608. DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS
58609. DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS
58610. DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT
58611. DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT
58612. DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT
58613. DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT
58614. DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT
58615. DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT
58616. DCN_1_0__SRCID__DMCU_INTERNAL_INT
58617. DCN_1_0__SRCID__DMCU_SCP_INT
58618. DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS
58619. DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS
58620. DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT
58621. DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS
58622. DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS
58623. DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS
58624. DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS
58625. DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS
58626. DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS
58627. DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS
58628. DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS
58629. DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS
58630. DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS
58631. DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS
58632. DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS
58633. DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS
58634. DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS
58635. DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS
58636. DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS
58637. DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST
58638. DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS
58639. DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS
58640. DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT
58641. DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT
58642. DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR
58643. DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS
58644. DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS
58645. DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT
58646. DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT
58647. DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR
58648. DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS
58649. DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS
58650. DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT
58651. DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT
58652. DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR
58653. DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS
58654. DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS
58655. DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT
58656. DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT
58657. DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR
58658. DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS
58659. DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS
58660. DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT
58661. DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT
58662. DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR
58663. DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS
58664. DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS
58665. DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT
58666. DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT
58667. DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR
58668. DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS
58669. DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS
58670. DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT
58671. DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT
58672. DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR
58673. DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS
58674. DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS
58675. DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT
58676. DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT
58677. DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR
58678. DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS
58679. DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS
58680. DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT
58681. DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT
58682. DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS
58683. DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS
58684. DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT
58685. DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT
58686. DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT
58687. DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT
58688. DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT
58689. DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT
58690. DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT
58691. DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT
58692. DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS
58693. DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS
58694. DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS
58695. DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS
58696. DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT
58697. DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT
58698. DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT
58699. DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT
58700. DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT
58701. DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT
58702. DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS
58703. DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS
58704. DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT
58705. DCN_1_0__SRCID__OTG0_VSYNC_NOM
58706. DCN_1_0__SRCID__OTG1_CPU_SS_INT
58707. DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58708. DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58709. DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58710. DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT
58711. DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE
58712. DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT
58713. DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL
58714. DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL
58715. DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL
58716. DCN_1_0__SRCID__OTG1_VSYNC_NOM
58717. DCN_1_0__SRCID__OTG2_CPU_SS_INT
58718. DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58719. DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58720. DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58721. DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT
58722. DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE
58723. DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT
58724. DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL
58725. DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL
58726. DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL
58727. DCN_1_0__SRCID__OTG2_VSYNC_NOM
58728. DCN_1_0__SRCID__OTG3_CPU_SS_INT
58729. DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58730. DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58731. DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58732. DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT
58733. DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE
58734. DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT
58735. DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL
58736. DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL
58737. DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL
58738. DCN_1_0__SRCID__OTG3_VSYNC_NOM
58739. DCN_1_0__SRCID__OTG4_CPU_SS_INT
58740. DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58741. DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58742. DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58743. DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT
58744. DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE
58745. DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT
58746. DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL
58747. DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL
58748. DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL
58749. DCN_1_0__SRCID__OTG4_VSYNC_NOM
58750. DCN_1_0__SRCID__OTG5_CPU_SS_INT
58751. DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58752. DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58753. DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58754. DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT
58755. DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE
58756. DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT
58757. DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL
58758. DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL
58759. DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL
58760. DCN_1_0__SRCID__OTG5_VSYNC_NOM
58761. DCN_1_0__SRCID__OTG6_CPU_SS_INT
58762. DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL
58763. DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
58764. DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
58765. DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE
58766. DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT
58767. DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
58768. DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL
58769. DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL
58770. DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT
58771. DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS
58772. DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS
58773. DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS
58774. DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS
58775. DCN_1_0__SRCID__VGA_CRT_INT
58776. DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS
58777. DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS
58778. DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS
58779. DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS
58780. DCN_BASE__INST0_SEG0
58781. DCN_BASE__INST0_SEG1
58782. DCN_BASE__INST0_SEG2
58783. DCN_BASE__INST0_SEG3
58784. DCN_BASE__INST0_SEG4
58785. DCN_BASE__INST0_SEG5
58786. DCN_BASE__INST1_SEG0
58787. DCN_BASE__INST1_SEG1
58788. DCN_BASE__INST1_SEG2
58789. DCN_BASE__INST1_SEG3
58790. DCN_BASE__INST1_SEG4
58791. DCN_BASE__INST1_SEG5
58792. DCN_BASE__INST2_SEG0
58793. DCN_BASE__INST2_SEG1
58794. DCN_BASE__INST2_SEG2
58795. DCN_BASE__INST2_SEG3
58796. DCN_BASE__INST2_SEG4
58797. DCN_BASE__INST2_SEG5
58798. DCN_BASE__INST3_SEG0
58799. DCN_BASE__INST3_SEG1
58800. DCN_BASE__INST3_SEG2
58801. DCN_BASE__INST3_SEG3
58802. DCN_BASE__INST3_SEG4
58803. DCN_BASE__INST3_SEG5
58804. DCN_BASE__INST4_SEG0
58805. DCN_BASE__INST4_SEG1
58806. DCN_BASE__INST4_SEG2
58807. DCN_BASE__INST4_SEG3
58808. DCN_BASE__INST4_SEG4
58809. DCN_BASE__INST4_SEG5
58810. DCN_BASE__INST5_SEG0
58811. DCN_BASE__INST5_SEG1
58812. DCN_BASE__INST5_SEG2
58813. DCN_BASE__INST5_SEG3
58814. DCN_BASE__INST5_SEG4
58815. DCN_BASE__INST5_SEG5
58816. DCN_HUBBUB_REG_FIELD_LIST
58817. DCN_HUBP_REG_FIELD_BASE_LIST
58818. DCN_HUBP_REG_FIELD_LIST
58819. DCN_LINK_ENCODER_REG_FIELD_LIST
58820. DCN_MINIMUM_DISPCLK_Khz
58821. DCN_MINIMUM_DPPCLK_Khz
58822. DCN_PAGE_TABLE_BLOCK_SIZE_4KB
58823. DCN_PAGE_TABLE_BLOCK_SIZE_64KB
58824. DCN_PAGE_TABLE_DEPTH_1_LEVEL
58825. DCN_PAGE_TABLE_DEPTH_2_LEVEL
58826. DCN_PAGE_TABLE_DEPTH_3_LEVEL
58827. DCN_PAGE_TABLE_DEPTH_4_LEVEL
58828. DCN_VERSION_1_0
58829. DCN_VERSION_1_01
58830. DCN_VERSION_2_0
58831. DCN_VERSION_2_1
58832. DCN_VERSION_MAX
58833. DCN_VM_AGP_BASE__AGP_BASE_MASK
58834. DCN_VM_AGP_BASE__AGP_BASE__SHIFT
58835. DCN_VM_AGP_BOT__AGP_BOT_MASK
58836. DCN_VM_AGP_BOT__AGP_BOT__SHIFT
58837. DCN_VM_AGP_TOP__AGP_TOP_MASK
58838. DCN_VM_AGP_TOP__AGP_TOP__SHIFT
58839. DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK
58840. DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT
58841. DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK
58842. DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT
58843. DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK
58844. DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58845. DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK
58846. DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58847. DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58848. DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58849. DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58850. DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58851. DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58852. DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58853. DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58854. DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58855. DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK
58856. DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT
58857. DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK
58858. DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT
58859. DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK
58860. DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58861. DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK
58862. DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58863. DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58864. DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58865. DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58866. DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58867. DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58868. DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58869. DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58870. DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58871. DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK
58872. DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT
58873. DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK
58874. DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT
58875. DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK
58876. DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58877. DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK
58878. DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58879. DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58880. DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58881. DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58882. DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58883. DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58884. DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58885. DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58886. DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58887. DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK
58888. DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT
58889. DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK
58890. DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT
58891. DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK
58892. DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58893. DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK
58894. DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58895. DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58896. DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58897. DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58898. DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58899. DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58900. DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58901. DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58902. DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58903. DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK
58904. DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT
58905. DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK
58906. DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT
58907. DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK
58908. DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58909. DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK
58910. DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58911. DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58912. DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58913. DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58914. DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58915. DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58916. DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58917. DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58918. DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58919. DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK
58920. DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT
58921. DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK
58922. DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT
58923. DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK
58924. DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58925. DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK
58926. DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58927. DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58928. DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58929. DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58930. DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58931. DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58932. DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58933. DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58934. DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58935. DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK
58936. DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT
58937. DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK
58938. DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT
58939. DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK
58940. DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58941. DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK
58942. DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58943. DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58944. DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58945. DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58946. DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58947. DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58948. DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58949. DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58950. DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58951. DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK
58952. DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT
58953. DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK
58954. DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT
58955. DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK
58956. DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58957. DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK
58958. DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58959. DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58960. DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58961. DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58962. DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58963. DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58964. DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58965. DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58966. DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58967. DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK
58968. DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT
58969. DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK
58970. DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT
58971. DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK
58972. DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58973. DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK
58974. DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58975. DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58976. DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58977. DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58978. DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58979. DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58980. DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58981. DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58982. DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58983. DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK
58984. DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT
58985. DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK
58986. DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT
58987. DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK
58988. DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
58989. DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK
58990. DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
58991. DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK
58992. DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58993. DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK
58994. DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58995. DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK
58996. DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
58997. DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK
58998. DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
58999. DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK
59000. DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT
59001. DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK
59002. DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT
59003. DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK
59004. DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
59005. DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK
59006. DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
59007. DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK
59008. DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59009. DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK
59010. DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59011. DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK
59012. DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59013. DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK
59014. DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59015. DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK
59016. DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT
59017. DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK
59018. DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT
59019. DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK
59020. DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
59021. DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK
59022. DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
59023. DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK
59024. DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59025. DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK
59026. DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59027. DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK
59028. DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59029. DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK
59030. DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59031. DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK
59032. DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT
59033. DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK
59034. DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT
59035. DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK
59036. DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
59037. DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK
59038. DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
59039. DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK
59040. DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59041. DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK
59042. DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59043. DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK
59044. DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59045. DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK
59046. DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59047. DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK
59048. DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT
59049. DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK
59050. DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT
59051. DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK
59052. DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
59053. DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK
59054. DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
59055. DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK
59056. DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59057. DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK
59058. DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59059. DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK
59060. DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59061. DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK
59062. DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59063. DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK
59064. DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT
59065. DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK
59066. DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT
59067. DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK
59068. DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
59069. DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK
59070. DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
59071. DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK
59072. DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59073. DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK
59074. DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59075. DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK
59076. DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59077. DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK
59078. DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59079. DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK
59080. DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT
59081. DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK
59082. DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT
59083. DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK
59084. DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT
59085. DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK
59086. DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT
59087. DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK
59088. DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59089. DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK
59090. DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59091. DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK
59092. DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT
59093. DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK
59094. DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT
59095. DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK
59096. DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT
59097. DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK
59098. DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT
59099. DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK
59100. DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT
59101. DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK
59102. DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT
59103. DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK
59104. DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT
59105. DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK
59106. DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT
59107. DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK
59108. DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT
59109. DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK
59110. DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT
59111. DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK
59112. DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT
59113. DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK
59114. DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT
59115. DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK
59116. DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT
59117. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK
59118. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT
59119. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK
59120. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT
59121. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK
59122. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT
59123. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK
59124. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT
59125. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK
59126. DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT
59127. DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK
59128. DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT
59129. DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK
59130. DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT
59131. DCN_VM_FB_OFFSET__FB_OFFSET_MASK
59132. DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT
59133. DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK
59134. DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT
59135. DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK
59136. DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT
59137. DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK
59138. DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT
59139. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
59140. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
59141. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
59142. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
59143. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
59144. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
59145. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
59146. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
59147. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_TMZ_MASK
59148. DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
59149. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
59150. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
59151. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
59152. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
59153. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
59154. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
59155. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
59156. DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
59157. DCOMU
59158. DCONSTAT_DISPLAYLOAD
59159. DCONSTAT_MISSED
59160. DCONSTAT_SCANINT
59161. DCONSTAT_SCANINT_DCON
59162. DCON_IRQ
59163. DCON_REG_BRIGHT
59164. DCON_REG_HRES
59165. DCON_REG_HSYNC_WIDTH
59166. DCON_REG_HTOTAL
59167. DCON_REG_ID
59168. DCON_REG_MEM_OPT_A
59169. DCON_REG_MEM_OPT_B
59170. DCON_REG_MODE
59171. DCON_REG_SCAN_INT
59172. DCON_REG_TIMEOUT
59173. DCON_REG_VRES
59174. DCON_REG_VSYNC_WIDTH
59175. DCON_REG_VTOTAL
59176. DCON_SOURCE_CPU
59177. DCON_SOURCE_DCON
59178. DCOOKIES_H
59179. DCORRECT
59180. DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK
59181. DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT
59182. DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK
59183. DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT
59184. DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK
59185. DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT
59186. DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK
59187. DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT
59188. DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK
59189. DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT
59190. DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK
59191. DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT
59192. DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK
59193. DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT
59194. DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK
59195. DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT
59196. DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK
59197. DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT
59198. DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK
59199. DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT
59200. DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK
59201. DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT
59202. DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK
59203. DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT
59204. DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK
59205. DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT
59206. DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK
59207. DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT
59208. DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK
59209. DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT
59210. DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK
59211. DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT
59212. DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK
59213. DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT
59214. DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK
59215. DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT
59216. DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK
59217. DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT
59218. DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK
59219. DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT
59220. DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK
59221. DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT
59222. DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK
59223. DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT
59224. DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK
59225. DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT
59226. DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK
59227. DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT
59228. DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK
59229. DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT
59230. DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK
59231. DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT
59232. DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK
59233. DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT
59234. DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK
59235. DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT
59236. DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK
59237. DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT
59238. DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK
59239. DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT
59240. DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK
59241. DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT
59242. DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK
59243. DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT
59244. DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK
59245. DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT
59246. DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK
59247. DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT
59248. DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK
59249. DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT
59250. DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK
59251. DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT
59252. DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK
59253. DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT
59254. DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK
59255. DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT
59256. DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK
59257. DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT
59258. DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK
59259. DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT
59260. DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK
59261. DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT
59262. DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK
59263. DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT
59264. DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK
59265. DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT
59266. DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK
59267. DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT
59268. DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK
59269. DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT
59270. DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK
59271. DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT
59272. DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK
59273. DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT
59274. DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK
59275. DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT
59276. DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK
59277. DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT
59278. DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK
59279. DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT
59280. DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK
59281. DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT
59282. DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK
59283. DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT
59284. DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK
59285. DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT
59286. DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK
59287. DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT
59288. DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK
59289. DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT
59290. DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK
59291. DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT
59292. DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK
59293. DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT
59294. DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK
59295. DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT
59296. DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK
59297. DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT
59298. DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK
59299. DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT
59300. DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK
59301. DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT
59302. DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK
59303. DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT
59304. DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK
59305. DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT
59306. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK
59307. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT
59308. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK
59309. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT
59310. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK
59311. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT
59312. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK
59313. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT
59314. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK
59315. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT
59316. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK
59317. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT
59318. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK
59319. DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT
59320. DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK
59321. DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT
59322. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK
59323. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT
59324. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK
59325. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT
59326. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK
59327. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT
59328. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK
59329. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT
59330. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK
59331. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT
59332. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK
59333. DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT
59334. DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK
59335. DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT
59336. DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK
59337. DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT
59338. DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS_MASK
59339. DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS__SHIFT
59340. DCO_DBG_BLOCK_SEL
59341. DCO_DBG_BLOCK_SEL_ABM
59342. DCO_DBG_BLOCK_SEL_AUDIO_OUT
59343. DCO_DBG_BLOCK_SEL_AUX0
59344. DCO_DBG_BLOCK_SEL_AUX1
59345. DCO_DBG_BLOCK_SEL_AUX2
59346. DCO_DBG_BLOCK_SEL_AUX3
59347. DCO_DBG_BLOCK_SEL_AUX4
59348. DCO_DBG_BLOCK_SEL_AUX5
59349. DCO_DBG_BLOCK_SEL_DAC
59350. DCO_DBG_BLOCK_SEL_DCO
59351. DCO_DBG_BLOCK_SEL_DIGA
59352. DCO_DBG_BLOCK_SEL_DIGB
59353. DCO_DBG_BLOCK_SEL_DIGC
59354. DCO_DBG_BLOCK_SEL_DIGD
59355. DCO_DBG_BLOCK_SEL_DIGE
59356. DCO_DBG_BLOCK_SEL_DIGF
59357. DCO_DBG_BLOCK_SEL_DIGFE_A
59358. DCO_DBG_BLOCK_SEL_DIGFE_B
59359. DCO_DBG_BLOCK_SEL_DIGFE_C
59360. DCO_DBG_BLOCK_SEL_DIGFE_D
59361. DCO_DBG_BLOCK_SEL_DIGFE_E
59362. DCO_DBG_BLOCK_SEL_DIGFE_F
59363. DCO_DBG_BLOCK_SEL_DIGFE_G
59364. DCO_DBG_BLOCK_SEL_DIGG
59365. DCO_DBG_BLOCK_SEL_DIGLPA
59366. DCO_DBG_BLOCK_SEL_DIGLPB
59367. DCO_DBG_BLOCK_SEL_DIGLPFEA
59368. DCO_DBG_BLOCK_SEL_DIGLPFEB
59369. DCO_DBG_BLOCK_SEL_DPA
59370. DCO_DBG_BLOCK_SEL_DPB
59371. DCO_DBG_BLOCK_SEL_DPC
59372. DCO_DBG_BLOCK_SEL_DPD
59373. DCO_DBG_BLOCK_SEL_DPE
59374. DCO_DBG_BLOCK_SEL_DPF
59375. DCO_DBG_BLOCK_SEL_DPFE_A
59376. DCO_DBG_BLOCK_SEL_DPFE_B
59377. DCO_DBG_BLOCK_SEL_DPFE_C
59378. DCO_DBG_BLOCK_SEL_DPFE_D
59379. DCO_DBG_BLOCK_SEL_DPFE_E
59380. DCO_DBG_BLOCK_SEL_DPFE_F
59381. DCO_DBG_BLOCK_SEL_DPFE_G
59382. DCO_DBG_BLOCK_SEL_DPG
59383. DCO_DBG_BLOCK_SEL_DPLPA
59384. DCO_DBG_BLOCK_SEL_DPLPB
59385. DCO_DBG_BLOCK_SEL_DPLPFEA
59386. DCO_DBG_BLOCK_SEL_DPLPFEB
59387. DCO_DBG_BLOCK_SEL_DVO
59388. DCO_DBG_BLOCK_SEL_FMT0
59389. DCO_DBG_BLOCK_SEL_FMT1
59390. DCO_DBG_BLOCK_SEL_FMT2
59391. DCO_DBG_BLOCK_SEL_FMT3
59392. DCO_DBG_BLOCK_SEL_FMT4
59393. DCO_DBG_BLOCK_SEL_FMT5
59394. DCO_DBG_BLOCK_SEL_MVP
59395. DCO_DBG_BLOCK_SEL_PERFMON_DCO
59396. DCO_DBG_CLOCK_SEL
59397. DCO_DBG_CLOCK_SEL_AM0CLK
59398. DCO_DBG_CLOCK_SEL_AM1CLK
59399. DCO_DBG_CLOCK_SEL_AM2CLK
59400. DCO_DBG_CLOCK_SEL_DACCLK
59401. DCO_DBG_CLOCK_SEL_DISPCLK
59402. DCO_DBG_CLOCK_SEL_DVOCLK
59403. DCO_DBG_CLOCK_SEL_MVPCLK
59404. DCO_DBG_CLOCK_SEL_REFCLK
59405. DCO_DBG_CLOCK_SEL_RESERVED
59406. DCO_DBG_CLOCK_SEL_SCLK
59407. DCO_DBG_CLOCK_SEL_SYMCLKA
59408. DCO_DBG_CLOCK_SEL_SYMCLKB
59409. DCO_DBG_CLOCK_SEL_SYMCLKC
59410. DCO_DBG_CLOCK_SEL_SYMCLKD
59411. DCO_DBG_CLOCK_SEL_SYMCLKE
59412. DCO_DBG_CLOCK_SEL_SYMCLKF
59413. DCO_DBG_CLOCK_SEL_SYMCLKG
59414. DCO_DBG_CLOCK_SEL_SYMCLKLPA
59415. DCO_DBG_CLOCK_SEL_SYMCLKLPB
59416. DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK
59417. DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT
59418. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK
59419. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT
59420. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK
59421. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT
59422. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK
59423. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT
59424. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK
59425. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT
59426. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK
59427. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT
59428. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK
59429. DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT
59430. DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK
59431. DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT
59432. DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK
59433. DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT
59434. DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR_MASK
59435. DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR__SHIFT
59436. DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE_MASK
59437. DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE__SHIFT
59438. DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS_MASK
59439. DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS__SHIFT
59440. DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE
59441. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE_MASK
59442. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT
59443. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK
59444. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT
59445. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK_MASK
59446. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK__SHIFT
59447. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS_MASK
59448. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT
59449. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE_MASK
59450. DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT
59451. DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL
59452. DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE
59453. DCO_HWID
59454. DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK
59455. DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT
59456. DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK
59457. DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT
59458. DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK
59459. DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT
59460. DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK
59461. DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT
59462. DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK
59463. DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT
59464. DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK
59465. DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT
59466. DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK
59467. DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT
59468. DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK
59469. DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT
59470. DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK
59471. DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT
59472. DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK
59473. DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT
59474. DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK
59475. DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT
59476. DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK
59477. DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT
59478. DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS_MASK
59479. DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS__SHIFT
59480. DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS_MASK
59481. DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS__SHIFT
59482. DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK
59483. DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT
59484. DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK
59485. DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT
59486. DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK
59487. DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT
59488. DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK
59489. DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT
59490. DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK
59491. DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT
59492. DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK
59493. DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT
59494. DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS_MASK
59495. DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS__SHIFT
59496. DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK
59497. DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT
59498. DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK
59499. DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT
59500. DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK
59501. DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT
59502. DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK
59503. DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT
59504. DCO_MAX
59505. DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE_MASK
59506. DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE__SHIFT
59507. DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE_MASK
59508. DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT
59509. DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK
59510. DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT
59511. DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK
59512. DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT
59513. DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK
59514. DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT
59515. DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK
59516. DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT
59517. DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK
59518. DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT
59519. DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK
59520. DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT
59521. DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK
59522. DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT
59523. DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK
59524. DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT
59525. DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK
59526. DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT
59527. DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK
59528. DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT
59529. DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK
59530. DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT
59531. DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK
59532. DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT
59533. DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK
59534. DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT
59535. DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK
59536. DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT
59537. DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK
59538. DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT
59539. DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK
59540. DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT
59541. DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK
59542. DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT
59543. DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK
59544. DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT
59545. DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK
59546. DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT
59547. DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK
59548. DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT
59549. DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK
59550. DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT
59551. DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK
59552. DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT
59553. DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK
59554. DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT
59555. DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK
59556. DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT
59557. DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK
59558. DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT
59559. DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK
59560. DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT
59561. DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK
59562. DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT
59563. DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK
59564. DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT
59565. DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK
59566. DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT
59567. DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK
59568. DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT
59569. DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK
59570. DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT
59571. DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK
59572. DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT
59573. DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK
59574. DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT
59575. DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK
59576. DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT
59577. DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK
59578. DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT
59579. DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK
59580. DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT
59581. DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK
59582. DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT
59583. DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK
59584. DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT
59585. DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK
59586. DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT
59587. DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK
59588. DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT
59589. DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK
59590. DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT
59591. DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK
59592. DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT
59593. DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK
59594. DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT
59595. DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK
59596. DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT
59597. DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK
59598. DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT
59599. DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK
59600. DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT
59601. DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS_MASK
59602. DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS__SHIFT
59603. DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK
59604. DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT
59605. DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK
59606. DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT
59607. DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK
59608. DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT
59609. DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK
59610. DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT
59611. DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK
59612. DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT
59613. DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK
59614. DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT
59615. DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK
59616. DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT
59617. DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK
59618. DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT
59619. DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK
59620. DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT
59621. DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK
59622. DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT
59623. DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK
59624. DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT
59625. DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK
59626. DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT
59627. DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK
59628. DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT
59629. DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK
59630. DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT
59631. DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK
59632. DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT
59633. DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK
59634. DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT
59635. DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK
59636. DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT
59637. DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK
59638. DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT
59639. DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK
59640. DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT
59641. DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK
59642. DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT
59643. DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE_MASK
59644. DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE__SHIFT
59645. DCO_MIN
59646. DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK
59647. DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT
59648. DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK
59649. DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT
59650. DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR_MASK
59651. DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR__SHIFT
59652. DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE_MASK
59653. DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE__SHIFT
59654. DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS_MASK
59655. DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS__SHIFT
59656. DCO_SCRATCH0__DCO_SCRATCH0_MASK
59657. DCO_SCRATCH0__DCO_SCRATCH0__SHIFT
59658. DCO_SCRATCH1__DCO_SCRATCH1_MASK
59659. DCO_SCRATCH1__DCO_SCRATCH1__SHIFT
59660. DCO_SCRATCH2__DCO_SCRATCH2_MASK
59661. DCO_SCRATCH2__DCO_SCRATCH2__SHIFT
59662. DCO_SCRATCH3__DCO_SCRATCH3_MASK
59663. DCO_SCRATCH3__DCO_SCRATCH3__SHIFT
59664. DCO_SCRATCH4__DCO_SCRATCH4_MASK
59665. DCO_SCRATCH4__DCO_SCRATCH4__SHIFT
59666. DCO_SCRATCH5__DCO_SCRATCH5_MASK
59667. DCO_SCRATCH5__DCO_SCRATCH5__SHIFT
59668. DCO_SCRATCH6__DCO_SCRATCH6_MASK
59669. DCO_SCRATCH6__DCO_SCRATCH6__SHIFT
59670. DCO_SCRATCH7__DCO_SCRATCH7_MASK
59671. DCO_SCRATCH7__DCO_SCRATCH7__SHIFT
59672. DCO_SOFT_RESET__ABM_SOFT_RESET_MASK
59673. DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT
59674. DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK
59675. DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT
59676. DCO_SOFT_RESET__DACA_SOFT_RESET_MASK
59677. DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT
59678. DCO_SOFT_RESET__DACB_SOFT_RESET_MASK
59679. DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT
59680. DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK
59681. DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT
59682. DCO_SOFT_RESET__DVO_ENABLE_RST_MASK
59683. DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT
59684. DCO_SOFT_RESET__DVO_SOFT_RESET_MASK
59685. DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT
59686. DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK
59687. DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT
59688. DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK
59689. DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT
59690. DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK
59691. DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT
59692. DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK
59693. DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT
59694. DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK
59695. DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT
59696. DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK
59697. DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT
59698. DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK
59699. DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT
59700. DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK
59701. DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT
59702. DCO_SOFT_RESET__MVP_SOFT_RESET_MASK
59703. DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT
59704. DCO_SOFT_RESET__SOFT_RESET_DVO_MASK
59705. DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT
59706. DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK
59707. DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT
59708. DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK
59709. DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT
59710. DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK
59711. DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT
59712. DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK
59713. DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT
59714. DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK
59715. DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT
59716. DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK
59717. DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT
59718. DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK
59719. DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT
59720. DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK
59721. DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT
59722. DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
59723. DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
59724. DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
59725. DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
59726. DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK
59727. DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT
59728. DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK
59729. DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT
59730. DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK
59731. DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT
59732. DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK
59733. DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT
59734. DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK
59735. DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT
59736. DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK
59737. DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT
59738. DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK
59739. DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT
59740. DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK
59741. DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT
59742. DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK
59743. DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT
59744. DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK
59745. DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT
59746. DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK
59747. DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT
59748. DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK
59749. DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT
59750. DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK
59751. DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT
59752. DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK
59753. DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT
59754. DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK
59755. DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT
59756. DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK
59757. DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT
59758. DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK
59759. DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT
59760. DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK
59761. DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT
59762. DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK
59763. DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT
59764. DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK
59765. DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT
59766. DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK
59767. DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT
59768. DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK
59769. DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT
59770. DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK
59771. DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT
59772. DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK
59773. DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT
59774. DCP0_CUR_COLOR1__CUR_COLOR1_BLUE_MASK
59775. DCP0_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT
59776. DCP0_CUR_COLOR1__CUR_COLOR1_GREEN_MASK
59777. DCP0_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT
59778. DCP0_CUR_COLOR1__CUR_COLOR1_RED_MASK
59779. DCP0_CUR_COLOR1__CUR_COLOR1_RED__SHIFT
59780. DCP0_CUR_COLOR2__CUR_COLOR2_BLUE_MASK
59781. DCP0_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT
59782. DCP0_CUR_COLOR2__CUR_COLOR2_GREEN_MASK
59783. DCP0_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT
59784. DCP0_CUR_COLOR2__CUR_COLOR2_RED_MASK
59785. DCP0_CUR_COLOR2__CUR_COLOR2_RED__SHIFT
59786. DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK
59787. DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT
59788. DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK
59789. DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT
59790. DCP0_CUR_CONTROL__CURSOR_EN_MASK
59791. DCP0_CUR_CONTROL__CURSOR_EN__SHIFT
59792. DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK
59793. DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT
59794. DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK
59795. DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT
59796. DCP0_CUR_CONTROL__CURSOR_MODE_MASK
59797. DCP0_CUR_CONTROL__CURSOR_MODE__SHIFT
59798. DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK
59799. DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
59800. DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK
59801. DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT
59802. DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK
59803. DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT
59804. DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK
59805. DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT
59806. DCP0_CUR_POSITION__CURSOR_X_POSITION_MASK
59807. DCP0_CUR_POSITION__CURSOR_X_POSITION__SHIFT
59808. DCP0_CUR_POSITION__CURSOR_Y_POSITION_MASK
59809. DCP0_CUR_POSITION__CURSOR_Y_POSITION__SHIFT
59810. DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK
59811. DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT
59812. DCP0_CUR_SIZE__CURSOR_HEIGHT_MASK
59813. DCP0_CUR_SIZE__CURSOR_HEIGHT__SHIFT
59814. DCP0_CUR_SIZE__CURSOR_WIDTH_MASK
59815. DCP0_CUR_SIZE__CURSOR_WIDTH__SHIFT
59816. DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK
59817. DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT
59818. DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK
59819. DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT
59820. DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK
59821. DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT
59822. DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK
59823. DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT
59824. DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK
59825. DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT
59826. DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK
59827. DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT
59828. DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
59829. DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT
59830. DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK
59831. DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT
59832. DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK
59833. DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT
59834. DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK
59835. DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT
59836. DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
59837. DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
59838. DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
59839. DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
59840. DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
59841. DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
59842. DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
59843. DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
59844. DCP0_DCP_CRC_LAST__DCP_CRC_LAST_MASK
59845. DCP0_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
59846. DCP0_DCP_CRC_MASK__DCP_CRC_MASK_MASK
59847. DCP0_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
59848. DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
59849. DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
59850. DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
59851. DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
59852. DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
59853. DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
59854. DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
59855. DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
59856. DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
59857. DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
59858. DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
59859. DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
59860. DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
59861. DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
59862. DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
59863. DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
59864. DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
59865. DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
59866. DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
59867. DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
59868. DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK
59869. DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT
59870. DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
59871. DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
59872. DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
59873. DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
59874. DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
59875. DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
59876. DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
59877. DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
59878. DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
59879. DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
59880. DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
59881. DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
59882. DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
59883. DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
59884. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
59885. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
59886. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
59887. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
59888. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
59889. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
59890. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
59891. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
59892. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
59893. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
59894. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
59895. DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
59896. DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
59897. DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
59898. DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
59899. DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
59900. DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
59901. DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
59902. DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
59903. DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
59904. DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
59905. DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
59906. DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
59907. DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
59908. DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
59909. DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
59910. DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
59911. DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
59912. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
59913. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
59914. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
59915. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
59916. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
59917. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
59918. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
59919. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
59920. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
59921. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
59922. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
59923. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
59924. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
59925. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
59926. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
59927. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
59928. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
59929. DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
59930. DCP0_DC_LUT_CONTROL__DC_LUT_INC_B_MASK
59931. DCP0_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
59932. DCP0_DC_LUT_CONTROL__DC_LUT_INC_G_MASK
59933. DCP0_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
59934. DCP0_DC_LUT_CONTROL__DC_LUT_INC_R_MASK
59935. DCP0_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
59936. DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
59937. DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
59938. DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
59939. DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
59940. DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
59941. DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
59942. DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
59943. DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
59944. DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
59945. DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
59946. DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
59947. DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
59948. DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
59949. DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
59950. DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
59951. DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
59952. DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
59953. DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
59954. DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
59955. DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
59956. DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
59957. DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
59958. DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
59959. DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
59960. DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
59961. DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
59962. DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
59963. DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
59964. DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
59965. DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
59966. DCP0_DENORM_CONTROL__DENORM_14BIT_OUT_MASK
59967. DCP0_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
59968. DCP0_DENORM_CONTROL__DENORM_MODE_MASK
59969. DCP0_DENORM_CONTROL__DENORM_MODE__SHIFT
59970. DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
59971. DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
59972. DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
59973. DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
59974. DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
59975. DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
59976. DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
59977. DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
59978. DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
59979. DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
59980. DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
59981. DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
59982. DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
59983. DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
59984. DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
59985. DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
59986. DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
59987. DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
59988. DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
59989. DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
59990. DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
59991. DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
59992. DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
59993. DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
59994. DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
59995. DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
59996. DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
59997. DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
59998. DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
59999. DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
60000. DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
60001. DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
60002. DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
60003. DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
60004. DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
60005. DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
60006. DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
60007. DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
60008. DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
60009. DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
60010. DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
60011. DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
60012. DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
60013. DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
60014. DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
60015. DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
60016. DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
60017. DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
60018. DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
60019. DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
60020. DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
60021. DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
60022. DCP0_GRPH_CONTROL__GRPH_DEPTH_MASK
60023. DCP0_GRPH_CONTROL__GRPH_DEPTH__SHIFT
60024. DCP0_GRPH_CONTROL__GRPH_DIM_TYPE_MASK
60025. DCP0_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT
60026. DCP0_GRPH_CONTROL__GRPH_FORMAT_MASK
60027. DCP0_GRPH_CONTROL__GRPH_FORMAT__SHIFT
60028. DCP0_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
60029. DCP0_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
60030. DCP0_GRPH_CONTROL__GRPH_NUM_PIPES_MASK
60031. DCP0_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT
60032. DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK
60033. DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT
60034. DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
60035. DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
60036. DCP0_GRPH_CONTROL__GRPH_SE_ENABLE_MASK
60037. DCP0_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT
60038. DCP0_GRPH_CONTROL__GRPH_SW_MODE_MASK
60039. DCP0_GRPH_CONTROL__GRPH_SW_MODE__SHIFT
60040. DCP0_GRPH_CONTROL__GRPH_Z_MASK
60041. DCP0_GRPH_CONTROL__GRPH_Z__SHIFT
60042. DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
60043. DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
60044. DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
60045. DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
60046. DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
60047. DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
60048. DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
60049. DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
60050. DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
60051. DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
60052. DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
60053. DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
60054. DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
60055. DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
60056. DCP0_GRPH_ENABLE__GRPH_ENABLE_MASK
60057. DCP0_GRPH_ENABLE__GRPH_ENABLE__SHIFT
60058. DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
60059. DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
60060. DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
60061. DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
60062. DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
60063. DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
60064. DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
60065. DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
60066. DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
60067. DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
60068. DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
60069. DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
60070. DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
60071. DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
60072. DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
60073. DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
60074. DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
60075. DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
60076. DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
60077. DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
60078. DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
60079. DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
60080. DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
60081. DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
60082. DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
60083. DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
60084. DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
60085. DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
60086. DCP0_GRPH_PITCH__GRPH_PITCH_MASK
60087. DCP0_GRPH_PITCH__GRPH_PITCH__SHIFT
60088. DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
60089. DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
60090. DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
60091. DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
60092. DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
60093. DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
60094. DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
60095. DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
60096. DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
60097. DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
60098. DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
60099. DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
60100. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
60101. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
60102. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
60103. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
60104. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
60105. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
60106. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
60107. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
60108. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
60109. DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
60110. DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
60111. DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
60112. DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
60113. DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
60114. DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
60115. DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
60116. DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
60117. DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
60118. DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
60119. DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
60120. DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
60121. DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
60122. DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
60123. DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
60124. DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
60125. DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
60126. DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
60127. DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
60128. DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
60129. DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
60130. DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
60131. DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
60132. DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
60133. DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
60134. DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
60135. DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
60136. DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
60137. DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
60138. DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
60139. DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
60140. DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
60141. DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
60142. DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
60143. DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
60144. DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
60145. DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
60146. DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
60147. DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
60148. DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
60149. DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
60150. DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
60151. DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
60152. DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
60153. DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
60154. DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK
60155. DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT
60156. DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK
60157. DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT
60158. DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK
60159. DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT
60160. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
60161. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
60162. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
60163. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
60164. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
60165. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
60166. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
60167. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
60168. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
60169. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
60170. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
60171. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
60172. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
60173. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
60174. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
60175. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
60176. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
60177. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
60178. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
60179. DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
60180. DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK
60181. DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT
60182. DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK
60183. DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT
60184. DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK
60185. DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT
60186. DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK
60187. DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT
60188. DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK
60189. DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT
60190. DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
60191. DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
60192. DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
60193. DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
60194. DCP0_GRPH_X_END__GRPH_X_END_MASK
60195. DCP0_GRPH_X_END__GRPH_X_END__SHIFT
60196. DCP0_GRPH_X_START__GRPH_X_START_MASK
60197. DCP0_GRPH_X_START__GRPH_X_START__SHIFT
60198. DCP0_GRPH_Y_END__GRPH_Y_END_MASK
60199. DCP0_GRPH_Y_END__GRPH_Y_END__SHIFT
60200. DCP0_GRPH_Y_START__GRPH_Y_START_MASK
60201. DCP0_GRPH_Y_START__GRPH_Y_START__SHIFT
60202. DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
60203. DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
60204. DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
60205. DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
60206. DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
60207. DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
60208. DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
60209. DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
60210. DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
60211. DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
60212. DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
60213. DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
60214. DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
60215. DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
60216. DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
60217. DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
60218. DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
60219. DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
60220. DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
60221. DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
60222. DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
60223. DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
60224. DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
60225. DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
60226. DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
60227. DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
60228. DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
60229. DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
60230. DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
60231. DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
60232. DCP0_KEY_CONTROL__KEY_MODE_MASK
60233. DCP0_KEY_CONTROL__KEY_MODE__SHIFT
60234. DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK
60235. DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT
60236. DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK
60237. DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT
60238. DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK
60239. DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT
60240. DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK
60241. DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT
60242. DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK
60243. DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT
60244. DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK
60245. DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT
60246. DCP0_KEY_RANGE_RED__KEY_RED_HIGH_MASK
60247. DCP0_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT
60248. DCP0_KEY_RANGE_RED__KEY_RED_LOW_MASK
60249. DCP0_KEY_RANGE_RED__KEY_RED_LOW__SHIFT
60250. DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
60251. DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
60252. DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
60253. DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
60254. DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
60255. DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
60256. DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
60257. DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
60258. DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
60259. DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
60260. DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
60261. DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
60262. DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
60263. DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
60264. DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
60265. DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
60266. DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
60267. DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
60268. DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
60269. DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
60270. DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
60271. DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
60272. DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
60273. DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
60274. DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
60275. DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
60276. DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
60277. DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
60278. DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
60279. DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
60280. DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
60281. DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
60282. DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
60283. DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
60284. DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
60285. DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
60286. DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
60287. DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
60288. DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
60289. DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
60290. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
60291. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
60292. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
60293. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
60294. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
60295. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
60296. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
60297. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
60298. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
60299. DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
60300. DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
60301. DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
60302. DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
60303. DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
60304. DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
60305. DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
60306. DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
60307. DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
60308. DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
60309. DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
60310. DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
60311. DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
60312. DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
60313. DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
60314. DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
60315. DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
60316. DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
60317. DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
60318. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
60319. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
60320. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
60321. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
60322. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
60323. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
60324. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
60325. DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
60326. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
60327. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
60328. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
60329. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
60330. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
60331. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
60332. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
60333. DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
60334. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
60335. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
60336. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
60337. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
60338. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
60339. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
60340. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
60341. DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
60342. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
60343. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
60344. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
60345. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
60346. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
60347. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
60348. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
60349. DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
60350. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
60351. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
60352. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
60353. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
60354. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
60355. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
60356. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
60357. DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
60358. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
60359. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
60360. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
60361. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
60362. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
60363. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
60364. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
60365. DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
60366. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
60367. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
60368. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
60369. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
60370. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
60371. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
60372. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
60373. DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
60374. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
60375. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
60376. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
60377. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
60378. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
60379. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
60380. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
60381. DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
60382. DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
60383. DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
60384. DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
60385. DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
60386. DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
60387. DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
60388. DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
60389. DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
60390. DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
60391. DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
60392. DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
60393. DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
60394. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
60395. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
60396. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
60397. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
60398. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
60399. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
60400. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
60401. DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
60402. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
60403. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
60404. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
60405. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
60406. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
60407. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
60408. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
60409. DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
60410. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
60411. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
60412. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
60413. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
60414. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
60415. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
60416. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
60417. DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
60418. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
60419. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
60420. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
60421. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
60422. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
60423. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
60424. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
60425. DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
60426. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
60427. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
60428. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
60429. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
60430. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
60431. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
60432. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
60433. DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
60434. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
60435. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
60436. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
60437. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
60438. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
60439. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
60440. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
60441. DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
60442. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
60443. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
60444. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
60445. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
60446. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
60447. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
60448. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
60449. DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
60450. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
60451. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
60452. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
60453. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
60454. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
60455. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
60456. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
60457. DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
60458. DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
60459. DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
60460. DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
60461. DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
60462. DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
60463. DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
60464. DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
60465. DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
60466. DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
60467. DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
60468. DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
60469. DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
60470. DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
60471. DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
60472. DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
60473. DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
60474. DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
60475. DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
60476. DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK
60477. DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT
60478. DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK
60479. DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT
60480. DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK
60481. DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT
60482. DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK
60483. DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT
60484. DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK
60485. DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT
60486. DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK
60487. DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT
60488. DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK
60489. DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT
60490. DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK
60491. DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT
60492. DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK
60493. DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT
60494. DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK
60495. DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT
60496. DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK
60497. DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT
60498. DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK
60499. DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT
60500. DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK
60501. DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT
60502. DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK
60503. DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT
60504. DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK
60505. DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT
60506. DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK
60507. DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT
60508. DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK
60509. DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT
60510. DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK
60511. DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT
60512. DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK
60513. DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT
60514. DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK
60515. DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT
60516. DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK
60517. DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT
60518. DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK
60519. DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT
60520. DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK
60521. DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT
60522. DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK
60523. DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT
60524. DCP1_CUR_COLOR1__CUR_COLOR1_BLUE_MASK
60525. DCP1_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT
60526. DCP1_CUR_COLOR1__CUR_COLOR1_GREEN_MASK
60527. DCP1_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT
60528. DCP1_CUR_COLOR1__CUR_COLOR1_RED_MASK
60529. DCP1_CUR_COLOR1__CUR_COLOR1_RED__SHIFT
60530. DCP1_CUR_COLOR2__CUR_COLOR2_BLUE_MASK
60531. DCP1_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT
60532. DCP1_CUR_COLOR2__CUR_COLOR2_GREEN_MASK
60533. DCP1_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT
60534. DCP1_CUR_COLOR2__CUR_COLOR2_RED_MASK
60535. DCP1_CUR_COLOR2__CUR_COLOR2_RED__SHIFT
60536. DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK
60537. DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT
60538. DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK
60539. DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT
60540. DCP1_CUR_CONTROL__CURSOR_EN_MASK
60541. DCP1_CUR_CONTROL__CURSOR_EN__SHIFT
60542. DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK
60543. DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT
60544. DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK
60545. DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT
60546. DCP1_CUR_CONTROL__CURSOR_MODE_MASK
60547. DCP1_CUR_CONTROL__CURSOR_MODE__SHIFT
60548. DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK
60549. DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
60550. DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK
60551. DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT
60552. DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK
60553. DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT
60554. DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK
60555. DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT
60556. DCP1_CUR_POSITION__CURSOR_X_POSITION_MASK
60557. DCP1_CUR_POSITION__CURSOR_X_POSITION__SHIFT
60558. DCP1_CUR_POSITION__CURSOR_Y_POSITION_MASK
60559. DCP1_CUR_POSITION__CURSOR_Y_POSITION__SHIFT
60560. DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK
60561. DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT
60562. DCP1_CUR_SIZE__CURSOR_HEIGHT_MASK
60563. DCP1_CUR_SIZE__CURSOR_HEIGHT__SHIFT
60564. DCP1_CUR_SIZE__CURSOR_WIDTH_MASK
60565. DCP1_CUR_SIZE__CURSOR_WIDTH__SHIFT
60566. DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK
60567. DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT
60568. DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK
60569. DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT
60570. DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK
60571. DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT
60572. DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK
60573. DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT
60574. DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK
60575. DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT
60576. DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK
60577. DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT
60578. DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
60579. DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT
60580. DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK
60581. DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT
60582. DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK
60583. DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT
60584. DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK
60585. DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT
60586. DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
60587. DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
60588. DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
60589. DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
60590. DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
60591. DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
60592. DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
60593. DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
60594. DCP1_DCP_CRC_LAST__DCP_CRC_LAST_MASK
60595. DCP1_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
60596. DCP1_DCP_CRC_MASK__DCP_CRC_MASK_MASK
60597. DCP1_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
60598. DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
60599. DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
60600. DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
60601. DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
60602. DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
60603. DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
60604. DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
60605. DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
60606. DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
60607. DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
60608. DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
60609. DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
60610. DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
60611. DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
60612. DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
60613. DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
60614. DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
60615. DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
60616. DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
60617. DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
60618. DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK
60619. DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT
60620. DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
60621. DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
60622. DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
60623. DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
60624. DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
60625. DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
60626. DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
60627. DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
60628. DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
60629. DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
60630. DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
60631. DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
60632. DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
60633. DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
60634. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
60635. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
60636. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
60637. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
60638. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
60639. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
60640. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
60641. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
60642. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
60643. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
60644. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
60645. DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
60646. DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
60647. DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
60648. DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
60649. DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
60650. DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
60651. DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
60652. DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
60653. DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
60654. DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
60655. DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
60656. DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
60657. DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
60658. DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
60659. DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
60660. DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
60661. DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
60662. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
60663. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
60664. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
60665. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
60666. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
60667. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
60668. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
60669. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
60670. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
60671. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
60672. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
60673. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
60674. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
60675. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
60676. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
60677. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
60678. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
60679. DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
60680. DCP1_DC_LUT_CONTROL__DC_LUT_INC_B_MASK
60681. DCP1_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
60682. DCP1_DC_LUT_CONTROL__DC_LUT_INC_G_MASK
60683. DCP1_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
60684. DCP1_DC_LUT_CONTROL__DC_LUT_INC_R_MASK
60685. DCP1_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
60686. DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
60687. DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
60688. DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
60689. DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
60690. DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
60691. DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
60692. DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
60693. DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
60694. DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
60695. DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
60696. DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
60697. DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
60698. DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
60699. DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
60700. DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
60701. DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
60702. DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
60703. DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
60704. DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
60705. DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
60706. DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
60707. DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
60708. DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
60709. DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
60710. DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
60711. DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
60712. DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
60713. DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
60714. DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
60715. DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
60716. DCP1_DENORM_CONTROL__DENORM_14BIT_OUT_MASK
60717. DCP1_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
60718. DCP1_DENORM_CONTROL__DENORM_MODE_MASK
60719. DCP1_DENORM_CONTROL__DENORM_MODE__SHIFT
60720. DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
60721. DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
60722. DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
60723. DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
60724. DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
60725. DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
60726. DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
60727. DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
60728. DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
60729. DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
60730. DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
60731. DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
60732. DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
60733. DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
60734. DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
60735. DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
60736. DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
60737. DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
60738. DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
60739. DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
60740. DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
60741. DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
60742. DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
60743. DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
60744. DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
60745. DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
60746. DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
60747. DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
60748. DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
60749. DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
60750. DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
60751. DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
60752. DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
60753. DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
60754. DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
60755. DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
60756. DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
60757. DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
60758. DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
60759. DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
60760. DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
60761. DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
60762. DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
60763. DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
60764. DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
60765. DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
60766. DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
60767. DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
60768. DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
60769. DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
60770. DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
60771. DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
60772. DCP1_GRPH_CONTROL__GRPH_DEPTH_MASK
60773. DCP1_GRPH_CONTROL__GRPH_DEPTH__SHIFT
60774. DCP1_GRPH_CONTROL__GRPH_DIM_TYPE_MASK
60775. DCP1_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT
60776. DCP1_GRPH_CONTROL__GRPH_FORMAT_MASK
60777. DCP1_GRPH_CONTROL__GRPH_FORMAT__SHIFT
60778. DCP1_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
60779. DCP1_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
60780. DCP1_GRPH_CONTROL__GRPH_NUM_PIPES_MASK
60781. DCP1_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT
60782. DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK
60783. DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT
60784. DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
60785. DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
60786. DCP1_GRPH_CONTROL__GRPH_SE_ENABLE_MASK
60787. DCP1_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT
60788. DCP1_GRPH_CONTROL__GRPH_SW_MODE_MASK
60789. DCP1_GRPH_CONTROL__GRPH_SW_MODE__SHIFT
60790. DCP1_GRPH_CONTROL__GRPH_Z_MASK
60791. DCP1_GRPH_CONTROL__GRPH_Z__SHIFT
60792. DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
60793. DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
60794. DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
60795. DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
60796. DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
60797. DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
60798. DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
60799. DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
60800. DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
60801. DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
60802. DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
60803. DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
60804. DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
60805. DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
60806. DCP1_GRPH_ENABLE__GRPH_ENABLE_MASK
60807. DCP1_GRPH_ENABLE__GRPH_ENABLE__SHIFT
60808. DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
60809. DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
60810. DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
60811. DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
60812. DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
60813. DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
60814. DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
60815. DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
60816. DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
60817. DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
60818. DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
60819. DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
60820. DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
60821. DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
60822. DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
60823. DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
60824. DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
60825. DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
60826. DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
60827. DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
60828. DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
60829. DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
60830. DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
60831. DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
60832. DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
60833. DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
60834. DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
60835. DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
60836. DCP1_GRPH_PITCH__GRPH_PITCH_MASK
60837. DCP1_GRPH_PITCH__GRPH_PITCH__SHIFT
60838. DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
60839. DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
60840. DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
60841. DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
60842. DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
60843. DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
60844. DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
60845. DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
60846. DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
60847. DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
60848. DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
60849. DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
60850. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
60851. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
60852. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
60853. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
60854. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
60855. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
60856. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
60857. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
60858. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
60859. DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
60860. DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
60861. DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
60862. DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
60863. DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
60864. DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
60865. DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
60866. DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
60867. DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
60868. DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
60869. DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
60870. DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
60871. DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
60872. DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
60873. DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
60874. DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
60875. DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
60876. DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
60877. DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
60878. DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
60879. DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
60880. DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
60881. DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
60882. DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
60883. DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
60884. DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
60885. DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
60886. DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
60887. DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
60888. DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
60889. DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
60890. DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
60891. DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
60892. DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
60893. DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
60894. DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
60895. DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
60896. DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
60897. DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
60898. DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
60899. DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
60900. DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
60901. DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
60902. DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
60903. DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
60904. DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK
60905. DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT
60906. DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK
60907. DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT
60908. DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK
60909. DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT
60910. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
60911. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
60912. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
60913. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
60914. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
60915. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
60916. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
60917. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
60918. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
60919. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
60920. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
60921. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
60922. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
60923. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
60924. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
60925. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
60926. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
60927. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
60928. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
60929. DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
60930. DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK
60931. DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT
60932. DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK
60933. DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT
60934. DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK
60935. DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT
60936. DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK
60937. DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT
60938. DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK
60939. DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT
60940. DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
60941. DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
60942. DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
60943. DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
60944. DCP1_GRPH_X_END__GRPH_X_END_MASK
60945. DCP1_GRPH_X_END__GRPH_X_END__SHIFT
60946. DCP1_GRPH_X_START__GRPH_X_START_MASK
60947. DCP1_GRPH_X_START__GRPH_X_START__SHIFT
60948. DCP1_GRPH_Y_END__GRPH_Y_END_MASK
60949. DCP1_GRPH_Y_END__GRPH_Y_END__SHIFT
60950. DCP1_GRPH_Y_START__GRPH_Y_START_MASK
60951. DCP1_GRPH_Y_START__GRPH_Y_START__SHIFT
60952. DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
60953. DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
60954. DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
60955. DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
60956. DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
60957. DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
60958. DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
60959. DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
60960. DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
60961. DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
60962. DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
60963. DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
60964. DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
60965. DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
60966. DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
60967. DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
60968. DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
60969. DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
60970. DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
60971. DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
60972. DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
60973. DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
60974. DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
60975. DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
60976. DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
60977. DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
60978. DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
60979. DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
60980. DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
60981. DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
60982. DCP1_KEY_CONTROL__KEY_MODE_MASK
60983. DCP1_KEY_CONTROL__KEY_MODE__SHIFT
60984. DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK
60985. DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT
60986. DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK
60987. DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT
60988. DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK
60989. DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT
60990. DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK
60991. DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT
60992. DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK
60993. DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT
60994. DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK
60995. DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT
60996. DCP1_KEY_RANGE_RED__KEY_RED_HIGH_MASK
60997. DCP1_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT
60998. DCP1_KEY_RANGE_RED__KEY_RED_LOW_MASK
60999. DCP1_KEY_RANGE_RED__KEY_RED_LOW__SHIFT
61000. DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
61001. DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
61002. DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
61003. DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
61004. DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
61005. DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
61006. DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
61007. DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
61008. DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
61009. DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
61010. DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
61011. DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
61012. DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
61013. DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
61014. DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
61015. DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
61016. DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
61017. DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
61018. DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
61019. DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
61020. DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
61021. DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
61022. DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
61023. DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
61024. DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
61025. DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
61026. DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
61027. DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
61028. DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
61029. DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
61030. DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
61031. DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
61032. DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
61033. DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
61034. DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
61035. DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
61036. DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
61037. DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
61038. DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
61039. DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
61040. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
61041. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
61042. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
61043. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
61044. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
61045. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
61046. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
61047. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
61048. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
61049. DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
61050. DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
61051. DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
61052. DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
61053. DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
61054. DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
61055. DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
61056. DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
61057. DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
61058. DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
61059. DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
61060. DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
61061. DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
61062. DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
61063. DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
61064. DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
61065. DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
61066. DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
61067. DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
61068. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
61069. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
61070. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
61071. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
61072. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
61073. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
61074. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
61075. DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
61076. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
61077. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
61078. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
61079. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
61080. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
61081. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
61082. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
61083. DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
61084. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
61085. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
61086. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
61087. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
61088. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
61089. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
61090. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
61091. DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
61092. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
61093. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
61094. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
61095. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
61096. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
61097. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
61098. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
61099. DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
61100. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
61101. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
61102. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
61103. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
61104. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
61105. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
61106. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
61107. DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
61108. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
61109. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
61110. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
61111. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
61112. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
61113. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
61114. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
61115. DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
61116. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
61117. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
61118. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
61119. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
61120. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
61121. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
61122. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
61123. DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
61124. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
61125. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
61126. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
61127. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
61128. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
61129. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
61130. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
61131. DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
61132. DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
61133. DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
61134. DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
61135. DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
61136. DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
61137. DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
61138. DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
61139. DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
61140. DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
61141. DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
61142. DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
61143. DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
61144. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
61145. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
61146. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
61147. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
61148. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
61149. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
61150. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
61151. DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
61152. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
61153. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
61154. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
61155. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
61156. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
61157. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
61158. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
61159. DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
61160. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
61161. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
61162. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
61163. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
61164. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
61165. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
61166. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
61167. DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
61168. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
61169. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
61170. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
61171. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
61172. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
61173. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
61174. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
61175. DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
61176. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
61177. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
61178. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
61179. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
61180. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
61181. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
61182. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
61183. DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
61184. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
61185. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
61186. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
61187. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
61188. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
61189. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
61190. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
61191. DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
61192. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
61193. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
61194. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
61195. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
61196. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
61197. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
61198. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
61199. DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
61200. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
61201. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
61202. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
61203. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
61204. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
61205. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
61206. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
61207. DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
61208. DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
61209. DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
61210. DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
61211. DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
61212. DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
61213. DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
61214. DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
61215. DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
61216. DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
61217. DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
61218. DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
61219. DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
61220. DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
61221. DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
61222. DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
61223. DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
61224. DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
61225. DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
61226. DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK
61227. DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT
61228. DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK
61229. DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT
61230. DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK
61231. DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT
61232. DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK
61233. DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT
61234. DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK
61235. DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT
61236. DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK
61237. DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT
61238. DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK
61239. DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT
61240. DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK
61241. DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT
61242. DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK
61243. DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT
61244. DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK
61245. DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT
61246. DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK
61247. DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT
61248. DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK
61249. DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT
61250. DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK
61251. DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT
61252. DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK
61253. DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT
61254. DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK
61255. DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT
61256. DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK
61257. DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT
61258. DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK
61259. DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT
61260. DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK
61261. DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT
61262. DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK
61263. DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT
61264. DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK
61265. DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT
61266. DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK
61267. DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT
61268. DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK
61269. DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT
61270. DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK
61271. DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT
61272. DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK
61273. DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT
61274. DCP2_CUR_COLOR1__CUR_COLOR1_BLUE_MASK
61275. DCP2_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT
61276. DCP2_CUR_COLOR1__CUR_COLOR1_GREEN_MASK
61277. DCP2_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT
61278. DCP2_CUR_COLOR1__CUR_COLOR1_RED_MASK
61279. DCP2_CUR_COLOR1__CUR_COLOR1_RED__SHIFT
61280. DCP2_CUR_COLOR2__CUR_COLOR2_BLUE_MASK
61281. DCP2_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT
61282. DCP2_CUR_COLOR2__CUR_COLOR2_GREEN_MASK
61283. DCP2_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT
61284. DCP2_CUR_COLOR2__CUR_COLOR2_RED_MASK
61285. DCP2_CUR_COLOR2__CUR_COLOR2_RED__SHIFT
61286. DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK
61287. DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT
61288. DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK
61289. DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT
61290. DCP2_CUR_CONTROL__CURSOR_EN_MASK
61291. DCP2_CUR_CONTROL__CURSOR_EN__SHIFT
61292. DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK
61293. DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT
61294. DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK
61295. DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT
61296. DCP2_CUR_CONTROL__CURSOR_MODE_MASK
61297. DCP2_CUR_CONTROL__CURSOR_MODE__SHIFT
61298. DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK
61299. DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
61300. DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK
61301. DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT
61302. DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK
61303. DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT
61304. DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK
61305. DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT
61306. DCP2_CUR_POSITION__CURSOR_X_POSITION_MASK
61307. DCP2_CUR_POSITION__CURSOR_X_POSITION__SHIFT
61308. DCP2_CUR_POSITION__CURSOR_Y_POSITION_MASK
61309. DCP2_CUR_POSITION__CURSOR_Y_POSITION__SHIFT
61310. DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK
61311. DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT
61312. DCP2_CUR_SIZE__CURSOR_HEIGHT_MASK
61313. DCP2_CUR_SIZE__CURSOR_HEIGHT__SHIFT
61314. DCP2_CUR_SIZE__CURSOR_WIDTH_MASK
61315. DCP2_CUR_SIZE__CURSOR_WIDTH__SHIFT
61316. DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK
61317. DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT
61318. DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK
61319. DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT
61320. DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK
61321. DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT
61322. DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK
61323. DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT
61324. DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK
61325. DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT
61326. DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK
61327. DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT
61328. DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
61329. DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT
61330. DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK
61331. DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT
61332. DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK
61333. DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT
61334. DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK
61335. DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT
61336. DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
61337. DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
61338. DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
61339. DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
61340. DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
61341. DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
61342. DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
61343. DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
61344. DCP2_DCP_CRC_LAST__DCP_CRC_LAST_MASK
61345. DCP2_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
61346. DCP2_DCP_CRC_MASK__DCP_CRC_MASK_MASK
61347. DCP2_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
61348. DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
61349. DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
61350. DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
61351. DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
61352. DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
61353. DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
61354. DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
61355. DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
61356. DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
61357. DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
61358. DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
61359. DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
61360. DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
61361. DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
61362. DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
61363. DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
61364. DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
61365. DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
61366. DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
61367. DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
61368. DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK
61369. DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT
61370. DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
61371. DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
61372. DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
61373. DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
61374. DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
61375. DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
61376. DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
61377. DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
61378. DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
61379. DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
61380. DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
61381. DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
61382. DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
61383. DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
61384. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
61385. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
61386. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
61387. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
61388. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
61389. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
61390. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
61391. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
61392. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
61393. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
61394. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
61395. DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
61396. DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
61397. DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
61398. DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
61399. DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
61400. DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
61401. DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
61402. DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
61403. DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
61404. DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
61405. DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
61406. DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
61407. DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
61408. DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
61409. DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
61410. DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
61411. DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
61412. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
61413. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
61414. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
61415. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
61416. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
61417. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
61418. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
61419. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
61420. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
61421. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
61422. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
61423. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
61424. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
61425. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
61426. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
61427. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
61428. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
61429. DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
61430. DCP2_DC_LUT_CONTROL__DC_LUT_INC_B_MASK
61431. DCP2_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
61432. DCP2_DC_LUT_CONTROL__DC_LUT_INC_G_MASK
61433. DCP2_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
61434. DCP2_DC_LUT_CONTROL__DC_LUT_INC_R_MASK
61435. DCP2_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
61436. DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
61437. DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
61438. DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
61439. DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
61440. DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
61441. DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
61442. DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
61443. DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
61444. DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
61445. DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
61446. DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
61447. DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
61448. DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
61449. DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
61450. DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
61451. DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
61452. DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
61453. DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
61454. DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
61455. DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
61456. DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
61457. DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
61458. DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
61459. DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
61460. DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
61461. DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
61462. DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
61463. DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
61464. DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
61465. DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
61466. DCP2_DENORM_CONTROL__DENORM_14BIT_OUT_MASK
61467. DCP2_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
61468. DCP2_DENORM_CONTROL__DENORM_MODE_MASK
61469. DCP2_DENORM_CONTROL__DENORM_MODE__SHIFT
61470. DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
61471. DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
61472. DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
61473. DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
61474. DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
61475. DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
61476. DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
61477. DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
61478. DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
61479. DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
61480. DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
61481. DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
61482. DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
61483. DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
61484. DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
61485. DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
61486. DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
61487. DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
61488. DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
61489. DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
61490. DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
61491. DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
61492. DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
61493. DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
61494. DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
61495. DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
61496. DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
61497. DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
61498. DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
61499. DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
61500. DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
61501. DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
61502. DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
61503. DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
61504. DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
61505. DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
61506. DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
61507. DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
61508. DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
61509. DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
61510. DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
61511. DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
61512. DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
61513. DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
61514. DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
61515. DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
61516. DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
61517. DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
61518. DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
61519. DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
61520. DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
61521. DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
61522. DCP2_GRPH_CONTROL__GRPH_DEPTH_MASK
61523. DCP2_GRPH_CONTROL__GRPH_DEPTH__SHIFT
61524. DCP2_GRPH_CONTROL__GRPH_DIM_TYPE_MASK
61525. DCP2_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT
61526. DCP2_GRPH_CONTROL__GRPH_FORMAT_MASK
61527. DCP2_GRPH_CONTROL__GRPH_FORMAT__SHIFT
61528. DCP2_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
61529. DCP2_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
61530. DCP2_GRPH_CONTROL__GRPH_NUM_PIPES_MASK
61531. DCP2_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT
61532. DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK
61533. DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT
61534. DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
61535. DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
61536. DCP2_GRPH_CONTROL__GRPH_SE_ENABLE_MASK
61537. DCP2_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT
61538. DCP2_GRPH_CONTROL__GRPH_SW_MODE_MASK
61539. DCP2_GRPH_CONTROL__GRPH_SW_MODE__SHIFT
61540. DCP2_GRPH_CONTROL__GRPH_Z_MASK
61541. DCP2_GRPH_CONTROL__GRPH_Z__SHIFT
61542. DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
61543. DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
61544. DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
61545. DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
61546. DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
61547. DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
61548. DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
61549. DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
61550. DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
61551. DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
61552. DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
61553. DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
61554. DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
61555. DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
61556. DCP2_GRPH_ENABLE__GRPH_ENABLE_MASK
61557. DCP2_GRPH_ENABLE__GRPH_ENABLE__SHIFT
61558. DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
61559. DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
61560. DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
61561. DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
61562. DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
61563. DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
61564. DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
61565. DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
61566. DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
61567. DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
61568. DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
61569. DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
61570. DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
61571. DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
61572. DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
61573. DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
61574. DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
61575. DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
61576. DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
61577. DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
61578. DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
61579. DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
61580. DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
61581. DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
61582. DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
61583. DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
61584. DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
61585. DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
61586. DCP2_GRPH_PITCH__GRPH_PITCH_MASK
61587. DCP2_GRPH_PITCH__GRPH_PITCH__SHIFT
61588. DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
61589. DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
61590. DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
61591. DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
61592. DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
61593. DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
61594. DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
61595. DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
61596. DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
61597. DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
61598. DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
61599. DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
61600. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
61601. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
61602. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
61603. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
61604. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
61605. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
61606. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
61607. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
61608. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
61609. DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
61610. DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
61611. DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
61612. DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
61613. DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
61614. DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
61615. DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
61616. DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
61617. DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
61618. DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
61619. DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
61620. DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
61621. DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
61622. DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
61623. DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
61624. DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
61625. DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
61626. DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
61627. DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
61628. DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
61629. DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
61630. DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
61631. DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
61632. DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
61633. DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
61634. DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
61635. DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
61636. DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
61637. DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
61638. DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
61639. DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
61640. DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
61641. DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
61642. DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
61643. DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
61644. DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
61645. DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
61646. DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
61647. DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
61648. DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
61649. DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
61650. DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
61651. DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
61652. DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
61653. DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
61654. DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK
61655. DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT
61656. DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK
61657. DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT
61658. DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK
61659. DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT
61660. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
61661. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
61662. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
61663. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
61664. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
61665. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
61666. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
61667. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
61668. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
61669. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
61670. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
61671. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
61672. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
61673. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
61674. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
61675. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
61676. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
61677. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
61678. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
61679. DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
61680. DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK
61681. DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT
61682. DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK
61683. DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT
61684. DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK
61685. DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT
61686. DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK
61687. DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT
61688. DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK
61689. DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT
61690. DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
61691. DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
61692. DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
61693. DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
61694. DCP2_GRPH_X_END__GRPH_X_END_MASK
61695. DCP2_GRPH_X_END__GRPH_X_END__SHIFT
61696. DCP2_GRPH_X_START__GRPH_X_START_MASK
61697. DCP2_GRPH_X_START__GRPH_X_START__SHIFT
61698. DCP2_GRPH_Y_END__GRPH_Y_END_MASK
61699. DCP2_GRPH_Y_END__GRPH_Y_END__SHIFT
61700. DCP2_GRPH_Y_START__GRPH_Y_START_MASK
61701. DCP2_GRPH_Y_START__GRPH_Y_START__SHIFT
61702. DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
61703. DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
61704. DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
61705. DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
61706. DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
61707. DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
61708. DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
61709. DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
61710. DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
61711. DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
61712. DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
61713. DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
61714. DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
61715. DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
61716. DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
61717. DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
61718. DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
61719. DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
61720. DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
61721. DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
61722. DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
61723. DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
61724. DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
61725. DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
61726. DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
61727. DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
61728. DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
61729. DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
61730. DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
61731. DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
61732. DCP2_KEY_CONTROL__KEY_MODE_MASK
61733. DCP2_KEY_CONTROL__KEY_MODE__SHIFT
61734. DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK
61735. DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT
61736. DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK
61737. DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT
61738. DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK
61739. DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT
61740. DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK
61741. DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT
61742. DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK
61743. DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT
61744. DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK
61745. DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT
61746. DCP2_KEY_RANGE_RED__KEY_RED_HIGH_MASK
61747. DCP2_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT
61748. DCP2_KEY_RANGE_RED__KEY_RED_LOW_MASK
61749. DCP2_KEY_RANGE_RED__KEY_RED_LOW__SHIFT
61750. DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
61751. DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
61752. DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
61753. DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
61754. DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
61755. DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
61756. DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
61757. DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
61758. DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
61759. DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
61760. DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
61761. DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
61762. DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
61763. DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
61764. DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
61765. DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
61766. DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
61767. DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
61768. DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
61769. DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
61770. DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
61771. DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
61772. DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
61773. DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
61774. DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
61775. DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
61776. DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
61777. DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
61778. DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
61779. DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
61780. DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
61781. DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
61782. DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
61783. DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
61784. DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
61785. DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
61786. DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
61787. DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
61788. DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
61789. DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
61790. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
61791. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
61792. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
61793. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
61794. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
61795. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
61796. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
61797. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
61798. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
61799. DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
61800. DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
61801. DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
61802. DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
61803. DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
61804. DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
61805. DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
61806. DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
61807. DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
61808. DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
61809. DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
61810. DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
61811. DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
61812. DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
61813. DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
61814. DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
61815. DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
61816. DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
61817. DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
61818. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
61819. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
61820. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
61821. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
61822. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
61823. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
61824. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
61825. DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
61826. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
61827. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
61828. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
61829. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
61830. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
61831. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
61832. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
61833. DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
61834. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
61835. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
61836. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
61837. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
61838. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
61839. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
61840. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
61841. DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
61842. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
61843. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
61844. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
61845. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
61846. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
61847. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
61848. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
61849. DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
61850. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
61851. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
61852. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
61853. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
61854. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
61855. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
61856. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
61857. DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
61858. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
61859. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
61860. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
61861. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
61862. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
61863. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
61864. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
61865. DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
61866. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
61867. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
61868. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
61869. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
61870. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
61871. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
61872. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
61873. DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
61874. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
61875. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
61876. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
61877. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
61878. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
61879. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
61880. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
61881. DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
61882. DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
61883. DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
61884. DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
61885. DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
61886. DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
61887. DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
61888. DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
61889. DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
61890. DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
61891. DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
61892. DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
61893. DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
61894. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
61895. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
61896. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
61897. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
61898. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
61899. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
61900. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
61901. DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
61902. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
61903. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
61904. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
61905. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
61906. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
61907. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
61908. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
61909. DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
61910. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
61911. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
61912. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
61913. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
61914. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
61915. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
61916. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
61917. DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
61918. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
61919. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
61920. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
61921. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
61922. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
61923. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
61924. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
61925. DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
61926. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
61927. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
61928. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
61929. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
61930. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
61931. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
61932. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
61933. DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
61934. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
61935. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
61936. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
61937. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
61938. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
61939. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
61940. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
61941. DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
61942. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
61943. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
61944. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
61945. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
61946. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
61947. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
61948. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
61949. DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
61950. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
61951. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
61952. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
61953. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
61954. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
61955. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
61956. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
61957. DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
61958. DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
61959. DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
61960. DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
61961. DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
61962. DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
61963. DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
61964. DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
61965. DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
61966. DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
61967. DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
61968. DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
61969. DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
61970. DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
61971. DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
61972. DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
61973. DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
61974. DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
61975. DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
61976. DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK
61977. DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT
61978. DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK
61979. DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT
61980. DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK
61981. DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT
61982. DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK
61983. DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT
61984. DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK
61985. DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT
61986. DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK
61987. DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT
61988. DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK
61989. DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT
61990. DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK
61991. DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT
61992. DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK
61993. DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT
61994. DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK
61995. DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT
61996. DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK
61997. DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT
61998. DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK
61999. DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT
62000. DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK
62001. DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT
62002. DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK
62003. DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT
62004. DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK
62005. DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT
62006. DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK
62007. DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT
62008. DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK
62009. DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT
62010. DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK
62011. DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT
62012. DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK
62013. DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT
62014. DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK
62015. DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT
62016. DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK
62017. DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT
62018. DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK
62019. DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT
62020. DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK
62021. DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT
62022. DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK
62023. DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT
62024. DCP3_CUR_COLOR1__CUR_COLOR1_BLUE_MASK
62025. DCP3_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT
62026. DCP3_CUR_COLOR1__CUR_COLOR1_GREEN_MASK
62027. DCP3_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT
62028. DCP3_CUR_COLOR1__CUR_COLOR1_RED_MASK
62029. DCP3_CUR_COLOR1__CUR_COLOR1_RED__SHIFT
62030. DCP3_CUR_COLOR2__CUR_COLOR2_BLUE_MASK
62031. DCP3_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT
62032. DCP3_CUR_COLOR2__CUR_COLOR2_GREEN_MASK
62033. DCP3_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT
62034. DCP3_CUR_COLOR2__CUR_COLOR2_RED_MASK
62035. DCP3_CUR_COLOR2__CUR_COLOR2_RED__SHIFT
62036. DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK
62037. DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT
62038. DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK
62039. DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT
62040. DCP3_CUR_CONTROL__CURSOR_EN_MASK
62041. DCP3_CUR_CONTROL__CURSOR_EN__SHIFT
62042. DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK
62043. DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT
62044. DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK
62045. DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT
62046. DCP3_CUR_CONTROL__CURSOR_MODE_MASK
62047. DCP3_CUR_CONTROL__CURSOR_MODE__SHIFT
62048. DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK
62049. DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
62050. DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK
62051. DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT
62052. DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK
62053. DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT
62054. DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK
62055. DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT
62056. DCP3_CUR_POSITION__CURSOR_X_POSITION_MASK
62057. DCP3_CUR_POSITION__CURSOR_X_POSITION__SHIFT
62058. DCP3_CUR_POSITION__CURSOR_Y_POSITION_MASK
62059. DCP3_CUR_POSITION__CURSOR_Y_POSITION__SHIFT
62060. DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK
62061. DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT
62062. DCP3_CUR_SIZE__CURSOR_HEIGHT_MASK
62063. DCP3_CUR_SIZE__CURSOR_HEIGHT__SHIFT
62064. DCP3_CUR_SIZE__CURSOR_WIDTH_MASK
62065. DCP3_CUR_SIZE__CURSOR_WIDTH__SHIFT
62066. DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK
62067. DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT
62068. DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK
62069. DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT
62070. DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK
62071. DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT
62072. DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK
62073. DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT
62074. DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK
62075. DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT
62076. DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK
62077. DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT
62078. DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
62079. DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT
62080. DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK
62081. DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT
62082. DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK
62083. DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT
62084. DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK
62085. DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT
62086. DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
62087. DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
62088. DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
62089. DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
62090. DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
62091. DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
62092. DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
62093. DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
62094. DCP3_DCP_CRC_LAST__DCP_CRC_LAST_MASK
62095. DCP3_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
62096. DCP3_DCP_CRC_MASK__DCP_CRC_MASK_MASK
62097. DCP3_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
62098. DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
62099. DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
62100. DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
62101. DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
62102. DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
62103. DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
62104. DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
62105. DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
62106. DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
62107. DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
62108. DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
62109. DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
62110. DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
62111. DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
62112. DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
62113. DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
62114. DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
62115. DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
62116. DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
62117. DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
62118. DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK
62119. DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT
62120. DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
62121. DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
62122. DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
62123. DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
62124. DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
62125. DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
62126. DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
62127. DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
62128. DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
62129. DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
62130. DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
62131. DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
62132. DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
62133. DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
62134. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
62135. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
62136. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
62137. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
62138. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
62139. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
62140. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
62141. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
62142. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
62143. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
62144. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
62145. DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
62146. DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
62147. DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
62148. DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
62149. DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
62150. DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
62151. DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
62152. DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
62153. DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
62154. DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
62155. DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
62156. DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
62157. DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
62158. DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
62159. DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
62160. DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
62161. DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
62162. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
62163. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
62164. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
62165. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
62166. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
62167. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
62168. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
62169. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
62170. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
62171. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
62172. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
62173. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
62174. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
62175. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
62176. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
62177. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
62178. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
62179. DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
62180. DCP3_DC_LUT_CONTROL__DC_LUT_INC_B_MASK
62181. DCP3_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
62182. DCP3_DC_LUT_CONTROL__DC_LUT_INC_G_MASK
62183. DCP3_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
62184. DCP3_DC_LUT_CONTROL__DC_LUT_INC_R_MASK
62185. DCP3_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
62186. DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
62187. DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
62188. DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
62189. DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
62190. DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
62191. DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
62192. DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
62193. DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
62194. DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
62195. DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
62196. DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
62197. DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
62198. DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
62199. DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
62200. DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
62201. DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
62202. DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
62203. DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
62204. DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
62205. DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
62206. DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
62207. DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
62208. DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
62209. DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
62210. DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
62211. DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
62212. DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
62213. DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
62214. DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
62215. DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
62216. DCP3_DENORM_CONTROL__DENORM_14BIT_OUT_MASK
62217. DCP3_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
62218. DCP3_DENORM_CONTROL__DENORM_MODE_MASK
62219. DCP3_DENORM_CONTROL__DENORM_MODE__SHIFT
62220. DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
62221. DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
62222. DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
62223. DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
62224. DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
62225. DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
62226. DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
62227. DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
62228. DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
62229. DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
62230. DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
62231. DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
62232. DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
62233. DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
62234. DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
62235. DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
62236. DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
62237. DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
62238. DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
62239. DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
62240. DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
62241. DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
62242. DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
62243. DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
62244. DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
62245. DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
62246. DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
62247. DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
62248. DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
62249. DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
62250. DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
62251. DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
62252. DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
62253. DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
62254. DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
62255. DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
62256. DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
62257. DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
62258. DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
62259. DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
62260. DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
62261. DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
62262. DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
62263. DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
62264. DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
62265. DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
62266. DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
62267. DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
62268. DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
62269. DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
62270. DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
62271. DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
62272. DCP3_GRPH_CONTROL__GRPH_DEPTH_MASK
62273. DCP3_GRPH_CONTROL__GRPH_DEPTH__SHIFT
62274. DCP3_GRPH_CONTROL__GRPH_DIM_TYPE_MASK
62275. DCP3_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT
62276. DCP3_GRPH_CONTROL__GRPH_FORMAT_MASK
62277. DCP3_GRPH_CONTROL__GRPH_FORMAT__SHIFT
62278. DCP3_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
62279. DCP3_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
62280. DCP3_GRPH_CONTROL__GRPH_NUM_PIPES_MASK
62281. DCP3_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT
62282. DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK
62283. DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT
62284. DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
62285. DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
62286. DCP3_GRPH_CONTROL__GRPH_SE_ENABLE_MASK
62287. DCP3_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT
62288. DCP3_GRPH_CONTROL__GRPH_SW_MODE_MASK
62289. DCP3_GRPH_CONTROL__GRPH_SW_MODE__SHIFT
62290. DCP3_GRPH_CONTROL__GRPH_Z_MASK
62291. DCP3_GRPH_CONTROL__GRPH_Z__SHIFT
62292. DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
62293. DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
62294. DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
62295. DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
62296. DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
62297. DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
62298. DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
62299. DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
62300. DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
62301. DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
62302. DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
62303. DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
62304. DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
62305. DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
62306. DCP3_GRPH_ENABLE__GRPH_ENABLE_MASK
62307. DCP3_GRPH_ENABLE__GRPH_ENABLE__SHIFT
62308. DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
62309. DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
62310. DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
62311. DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
62312. DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
62313. DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
62314. DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
62315. DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
62316. DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
62317. DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
62318. DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
62319. DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
62320. DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
62321. DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
62322. DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
62323. DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
62324. DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
62325. DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
62326. DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
62327. DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
62328. DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
62329. DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
62330. DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
62331. DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
62332. DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
62333. DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
62334. DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
62335. DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
62336. DCP3_GRPH_PITCH__GRPH_PITCH_MASK
62337. DCP3_GRPH_PITCH__GRPH_PITCH__SHIFT
62338. DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
62339. DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
62340. DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
62341. DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
62342. DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
62343. DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
62344. DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
62345. DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
62346. DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
62347. DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
62348. DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
62349. DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
62350. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
62351. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
62352. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
62353. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
62354. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
62355. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
62356. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
62357. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
62358. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
62359. DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
62360. DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
62361. DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
62362. DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
62363. DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
62364. DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
62365. DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
62366. DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
62367. DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
62368. DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
62369. DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
62370. DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
62371. DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
62372. DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
62373. DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
62374. DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
62375. DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
62376. DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
62377. DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
62378. DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
62379. DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
62380. DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
62381. DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
62382. DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
62383. DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
62384. DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
62385. DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
62386. DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
62387. DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
62388. DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
62389. DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
62390. DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
62391. DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
62392. DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
62393. DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
62394. DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
62395. DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
62396. DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
62397. DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
62398. DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
62399. DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
62400. DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
62401. DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
62402. DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
62403. DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
62404. DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK
62405. DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT
62406. DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK
62407. DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT
62408. DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK
62409. DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT
62410. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
62411. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
62412. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
62413. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
62414. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
62415. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
62416. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
62417. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
62418. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
62419. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
62420. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
62421. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
62422. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
62423. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
62424. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
62425. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
62426. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
62427. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
62428. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
62429. DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
62430. DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK
62431. DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT
62432. DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK
62433. DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT
62434. DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK
62435. DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT
62436. DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK
62437. DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT
62438. DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK
62439. DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT
62440. DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
62441. DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
62442. DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
62443. DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
62444. DCP3_GRPH_X_END__GRPH_X_END_MASK
62445. DCP3_GRPH_X_END__GRPH_X_END__SHIFT
62446. DCP3_GRPH_X_START__GRPH_X_START_MASK
62447. DCP3_GRPH_X_START__GRPH_X_START__SHIFT
62448. DCP3_GRPH_Y_END__GRPH_Y_END_MASK
62449. DCP3_GRPH_Y_END__GRPH_Y_END__SHIFT
62450. DCP3_GRPH_Y_START__GRPH_Y_START_MASK
62451. DCP3_GRPH_Y_START__GRPH_Y_START__SHIFT
62452. DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
62453. DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
62454. DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
62455. DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
62456. DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
62457. DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
62458. DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
62459. DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
62460. DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
62461. DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
62462. DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
62463. DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
62464. DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
62465. DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
62466. DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
62467. DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
62468. DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
62469. DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
62470. DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
62471. DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
62472. DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
62473. DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
62474. DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
62475. DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
62476. DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
62477. DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
62478. DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
62479. DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
62480. DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
62481. DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
62482. DCP3_KEY_CONTROL__KEY_MODE_MASK
62483. DCP3_KEY_CONTROL__KEY_MODE__SHIFT
62484. DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK
62485. DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT
62486. DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK
62487. DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT
62488. DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK
62489. DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT
62490. DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK
62491. DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT
62492. DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK
62493. DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT
62494. DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK
62495. DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT
62496. DCP3_KEY_RANGE_RED__KEY_RED_HIGH_MASK
62497. DCP3_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT
62498. DCP3_KEY_RANGE_RED__KEY_RED_LOW_MASK
62499. DCP3_KEY_RANGE_RED__KEY_RED_LOW__SHIFT
62500. DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
62501. DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
62502. DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
62503. DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
62504. DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
62505. DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
62506. DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
62507. DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
62508. DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
62509. DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
62510. DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
62511. DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
62512. DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
62513. DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
62514. DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
62515. DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
62516. DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
62517. DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
62518. DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
62519. DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
62520. DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
62521. DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
62522. DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
62523. DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
62524. DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
62525. DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
62526. DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
62527. DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
62528. DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
62529. DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
62530. DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
62531. DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
62532. DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
62533. DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
62534. DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
62535. DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
62536. DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
62537. DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
62538. DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
62539. DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
62540. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
62541. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
62542. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
62543. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
62544. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
62545. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
62546. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
62547. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
62548. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
62549. DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
62550. DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
62551. DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
62552. DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
62553. DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
62554. DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
62555. DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
62556. DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
62557. DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
62558. DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
62559. DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
62560. DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
62561. DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
62562. DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
62563. DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
62564. DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
62565. DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
62566. DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
62567. DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
62568. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
62569. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
62570. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
62571. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
62572. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
62573. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
62574. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
62575. DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
62576. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
62577. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
62578. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
62579. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
62580. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
62581. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
62582. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
62583. DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
62584. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
62585. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
62586. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
62587. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
62588. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
62589. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
62590. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
62591. DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
62592. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
62593. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
62594. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
62595. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
62596. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
62597. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
62598. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
62599. DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
62600. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
62601. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
62602. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
62603. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
62604. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
62605. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
62606. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
62607. DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
62608. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
62609. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
62610. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
62611. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
62612. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
62613. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
62614. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
62615. DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
62616. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
62617. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
62618. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
62619. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
62620. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
62621. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
62622. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
62623. DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
62624. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
62625. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
62626. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
62627. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
62628. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
62629. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
62630. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
62631. DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
62632. DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
62633. DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
62634. DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
62635. DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
62636. DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
62637. DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
62638. DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
62639. DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
62640. DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
62641. DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
62642. DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
62643. DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
62644. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
62645. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
62646. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
62647. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
62648. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
62649. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
62650. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
62651. DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
62652. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
62653. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
62654. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
62655. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
62656. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
62657. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
62658. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
62659. DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
62660. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
62661. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
62662. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
62663. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
62664. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
62665. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
62666. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
62667. DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
62668. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
62669. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
62670. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
62671. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
62672. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
62673. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
62674. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
62675. DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
62676. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
62677. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
62678. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
62679. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
62680. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
62681. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
62682. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
62683. DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
62684. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
62685. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
62686. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
62687. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
62688. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
62689. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
62690. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
62691. DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
62692. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
62693. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
62694. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
62695. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
62696. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
62697. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
62698. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
62699. DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
62700. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
62701. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
62702. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
62703. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
62704. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
62705. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
62706. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
62707. DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
62708. DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
62709. DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
62710. DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
62711. DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
62712. DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
62713. DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
62714. DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
62715. DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
62716. DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
62717. DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
62718. DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
62719. DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
62720. DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
62721. DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
62722. DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
62723. DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
62724. DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
62725. DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
62726. DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK
62727. DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT
62728. DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK
62729. DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT
62730. DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK
62731. DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT
62732. DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK
62733. DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT
62734. DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK
62735. DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT
62736. DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK
62737. DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT
62738. DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK
62739. DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT
62740. DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK
62741. DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT
62742. DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK
62743. DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT
62744. DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK
62745. DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT
62746. DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK
62747. DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT
62748. DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK
62749. DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT
62750. DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK
62751. DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT
62752. DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK
62753. DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT
62754. DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK
62755. DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT
62756. DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK
62757. DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT
62758. DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK
62759. DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT
62760. DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK
62761. DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT
62762. DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK
62763. DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT
62764. DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK
62765. DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT
62766. DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK
62767. DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT
62768. DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK
62769. DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT
62770. DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK
62771. DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT
62772. DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK
62773. DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT
62774. DCP4_CUR_COLOR1__CUR_COLOR1_BLUE_MASK
62775. DCP4_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT
62776. DCP4_CUR_COLOR1__CUR_COLOR1_GREEN_MASK
62777. DCP4_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT
62778. DCP4_CUR_COLOR1__CUR_COLOR1_RED_MASK
62779. DCP4_CUR_COLOR1__CUR_COLOR1_RED__SHIFT
62780. DCP4_CUR_COLOR2__CUR_COLOR2_BLUE_MASK
62781. DCP4_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT
62782. DCP4_CUR_COLOR2__CUR_COLOR2_GREEN_MASK
62783. DCP4_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT
62784. DCP4_CUR_COLOR2__CUR_COLOR2_RED_MASK
62785. DCP4_CUR_COLOR2__CUR_COLOR2_RED__SHIFT
62786. DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK
62787. DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT
62788. DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK
62789. DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT
62790. DCP4_CUR_CONTROL__CURSOR_EN_MASK
62791. DCP4_CUR_CONTROL__CURSOR_EN__SHIFT
62792. DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK
62793. DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT
62794. DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK
62795. DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT
62796. DCP4_CUR_CONTROL__CURSOR_MODE_MASK
62797. DCP4_CUR_CONTROL__CURSOR_MODE__SHIFT
62798. DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK
62799. DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
62800. DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK
62801. DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT
62802. DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK
62803. DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT
62804. DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK
62805. DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT
62806. DCP4_CUR_POSITION__CURSOR_X_POSITION_MASK
62807. DCP4_CUR_POSITION__CURSOR_X_POSITION__SHIFT
62808. DCP4_CUR_POSITION__CURSOR_Y_POSITION_MASK
62809. DCP4_CUR_POSITION__CURSOR_Y_POSITION__SHIFT
62810. DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK
62811. DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT
62812. DCP4_CUR_SIZE__CURSOR_HEIGHT_MASK
62813. DCP4_CUR_SIZE__CURSOR_HEIGHT__SHIFT
62814. DCP4_CUR_SIZE__CURSOR_WIDTH_MASK
62815. DCP4_CUR_SIZE__CURSOR_WIDTH__SHIFT
62816. DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK
62817. DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT
62818. DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK
62819. DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT
62820. DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK
62821. DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT
62822. DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK
62823. DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT
62824. DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK
62825. DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT
62826. DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK
62827. DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT
62828. DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
62829. DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT
62830. DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK
62831. DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT
62832. DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK
62833. DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT
62834. DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK
62835. DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT
62836. DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
62837. DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
62838. DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
62839. DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
62840. DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
62841. DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
62842. DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
62843. DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
62844. DCP4_DCP_CRC_LAST__DCP_CRC_LAST_MASK
62845. DCP4_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
62846. DCP4_DCP_CRC_MASK__DCP_CRC_MASK_MASK
62847. DCP4_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
62848. DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
62849. DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
62850. DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
62851. DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
62852. DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
62853. DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
62854. DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
62855. DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
62856. DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
62857. DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
62858. DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
62859. DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
62860. DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
62861. DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
62862. DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
62863. DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
62864. DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
62865. DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
62866. DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
62867. DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
62868. DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK
62869. DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT
62870. DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
62871. DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
62872. DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
62873. DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
62874. DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
62875. DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
62876. DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
62877. DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
62878. DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
62879. DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
62880. DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
62881. DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
62882. DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
62883. DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
62884. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
62885. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
62886. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
62887. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
62888. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
62889. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
62890. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
62891. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
62892. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
62893. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
62894. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
62895. DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
62896. DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
62897. DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
62898. DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
62899. DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
62900. DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
62901. DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
62902. DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
62903. DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
62904. DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
62905. DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
62906. DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
62907. DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
62908. DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
62909. DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
62910. DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
62911. DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
62912. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
62913. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
62914. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
62915. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
62916. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
62917. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
62918. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
62919. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
62920. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
62921. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
62922. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
62923. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
62924. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
62925. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
62926. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
62927. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
62928. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
62929. DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
62930. DCP4_DC_LUT_CONTROL__DC_LUT_INC_B_MASK
62931. DCP4_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
62932. DCP4_DC_LUT_CONTROL__DC_LUT_INC_G_MASK
62933. DCP4_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
62934. DCP4_DC_LUT_CONTROL__DC_LUT_INC_R_MASK
62935. DCP4_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
62936. DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
62937. DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
62938. DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
62939. DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
62940. DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
62941. DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
62942. DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
62943. DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
62944. DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
62945. DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
62946. DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
62947. DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
62948. DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
62949. DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
62950. DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
62951. DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
62952. DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
62953. DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
62954. DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
62955. DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
62956. DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
62957. DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
62958. DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
62959. DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
62960. DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
62961. DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
62962. DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
62963. DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
62964. DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
62965. DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
62966. DCP4_DENORM_CONTROL__DENORM_14BIT_OUT_MASK
62967. DCP4_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
62968. DCP4_DENORM_CONTROL__DENORM_MODE_MASK
62969. DCP4_DENORM_CONTROL__DENORM_MODE__SHIFT
62970. DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
62971. DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
62972. DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
62973. DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
62974. DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
62975. DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
62976. DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
62977. DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
62978. DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
62979. DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
62980. DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
62981. DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
62982. DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
62983. DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
62984. DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
62985. DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
62986. DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
62987. DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
62988. DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
62989. DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
62990. DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
62991. DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
62992. DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
62993. DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
62994. DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
62995. DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
62996. DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
62997. DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
62998. DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
62999. DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
63000. DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
63001. DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
63002. DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
63003. DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
63004. DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
63005. DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
63006. DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
63007. DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
63008. DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
63009. DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
63010. DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
63011. DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
63012. DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
63013. DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
63014. DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
63015. DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
63016. DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
63017. DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
63018. DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
63019. DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
63020. DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
63021. DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
63022. DCP4_GRPH_CONTROL__GRPH_DEPTH_MASK
63023. DCP4_GRPH_CONTROL__GRPH_DEPTH__SHIFT
63024. DCP4_GRPH_CONTROL__GRPH_DIM_TYPE_MASK
63025. DCP4_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT
63026. DCP4_GRPH_CONTROL__GRPH_FORMAT_MASK
63027. DCP4_GRPH_CONTROL__GRPH_FORMAT__SHIFT
63028. DCP4_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
63029. DCP4_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
63030. DCP4_GRPH_CONTROL__GRPH_NUM_PIPES_MASK
63031. DCP4_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT
63032. DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK
63033. DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT
63034. DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
63035. DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
63036. DCP4_GRPH_CONTROL__GRPH_SE_ENABLE_MASK
63037. DCP4_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT
63038. DCP4_GRPH_CONTROL__GRPH_SW_MODE_MASK
63039. DCP4_GRPH_CONTROL__GRPH_SW_MODE__SHIFT
63040. DCP4_GRPH_CONTROL__GRPH_Z_MASK
63041. DCP4_GRPH_CONTROL__GRPH_Z__SHIFT
63042. DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
63043. DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
63044. DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
63045. DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
63046. DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
63047. DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
63048. DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
63049. DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
63050. DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
63051. DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
63052. DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
63053. DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
63054. DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
63055. DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
63056. DCP4_GRPH_ENABLE__GRPH_ENABLE_MASK
63057. DCP4_GRPH_ENABLE__GRPH_ENABLE__SHIFT
63058. DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
63059. DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
63060. DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
63061. DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
63062. DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
63063. DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
63064. DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
63065. DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
63066. DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
63067. DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
63068. DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
63069. DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
63070. DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
63071. DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
63072. DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
63073. DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
63074. DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
63075. DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
63076. DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
63077. DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
63078. DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
63079. DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
63080. DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
63081. DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
63082. DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
63083. DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
63084. DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
63085. DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
63086. DCP4_GRPH_PITCH__GRPH_PITCH_MASK
63087. DCP4_GRPH_PITCH__GRPH_PITCH__SHIFT
63088. DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
63089. DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
63090. DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
63091. DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
63092. DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
63093. DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
63094. DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
63095. DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
63096. DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
63097. DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
63098. DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
63099. DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
63100. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
63101. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
63102. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
63103. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
63104. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
63105. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
63106. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
63107. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
63108. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
63109. DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
63110. DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
63111. DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
63112. DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
63113. DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
63114. DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
63115. DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
63116. DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
63117. DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
63118. DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
63119. DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
63120. DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
63121. DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
63122. DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
63123. DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
63124. DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
63125. DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
63126. DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
63127. DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
63128. DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
63129. DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
63130. DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
63131. DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
63132. DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
63133. DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
63134. DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
63135. DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
63136. DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
63137. DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
63138. DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
63139. DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
63140. DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
63141. DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
63142. DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
63143. DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
63144. DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
63145. DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
63146. DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
63147. DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
63148. DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
63149. DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
63150. DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
63151. DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
63152. DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
63153. DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
63154. DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK
63155. DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT
63156. DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK
63157. DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT
63158. DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK
63159. DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT
63160. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
63161. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
63162. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
63163. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
63164. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
63165. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
63166. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
63167. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
63168. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
63169. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
63170. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
63171. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
63172. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
63173. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
63174. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
63175. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
63176. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
63177. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
63178. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
63179. DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
63180. DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK
63181. DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT
63182. DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK
63183. DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT
63184. DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK
63185. DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT
63186. DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK
63187. DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT
63188. DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK
63189. DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT
63190. DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
63191. DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
63192. DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
63193. DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
63194. DCP4_GRPH_X_END__GRPH_X_END_MASK
63195. DCP4_GRPH_X_END__GRPH_X_END__SHIFT
63196. DCP4_GRPH_X_START__GRPH_X_START_MASK
63197. DCP4_GRPH_X_START__GRPH_X_START__SHIFT
63198. DCP4_GRPH_Y_END__GRPH_Y_END_MASK
63199. DCP4_GRPH_Y_END__GRPH_Y_END__SHIFT
63200. DCP4_GRPH_Y_START__GRPH_Y_START_MASK
63201. DCP4_GRPH_Y_START__GRPH_Y_START__SHIFT
63202. DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
63203. DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
63204. DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
63205. DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
63206. DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
63207. DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
63208. DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
63209. DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
63210. DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
63211. DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
63212. DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
63213. DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
63214. DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
63215. DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
63216. DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
63217. DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
63218. DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
63219. DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
63220. DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
63221. DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
63222. DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
63223. DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
63224. DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
63225. DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
63226. DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
63227. DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
63228. DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
63229. DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
63230. DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
63231. DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
63232. DCP4_KEY_CONTROL__KEY_MODE_MASK
63233. DCP4_KEY_CONTROL__KEY_MODE__SHIFT
63234. DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK
63235. DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT
63236. DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK
63237. DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT
63238. DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK
63239. DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT
63240. DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK
63241. DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT
63242. DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK
63243. DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT
63244. DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK
63245. DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT
63246. DCP4_KEY_RANGE_RED__KEY_RED_HIGH_MASK
63247. DCP4_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT
63248. DCP4_KEY_RANGE_RED__KEY_RED_LOW_MASK
63249. DCP4_KEY_RANGE_RED__KEY_RED_LOW__SHIFT
63250. DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
63251. DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
63252. DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
63253. DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
63254. DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
63255. DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
63256. DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
63257. DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
63258. DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
63259. DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
63260. DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
63261. DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
63262. DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
63263. DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
63264. DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
63265. DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
63266. DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
63267. DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
63268. DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
63269. DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
63270. DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
63271. DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
63272. DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
63273. DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
63274. DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
63275. DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
63276. DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
63277. DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
63278. DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
63279. DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
63280. DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
63281. DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
63282. DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
63283. DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
63284. DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
63285. DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
63286. DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
63287. DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
63288. DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
63289. DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
63290. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
63291. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
63292. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
63293. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
63294. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
63295. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
63296. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
63297. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
63298. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
63299. DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
63300. DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
63301. DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
63302. DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
63303. DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
63304. DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
63305. DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
63306. DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
63307. DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
63308. DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
63309. DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
63310. DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
63311. DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
63312. DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
63313. DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
63314. DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
63315. DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
63316. DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
63317. DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
63318. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
63319. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
63320. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
63321. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
63322. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
63323. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
63324. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
63325. DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
63326. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
63327. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
63328. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
63329. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
63330. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
63331. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
63332. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
63333. DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
63334. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
63335. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
63336. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
63337. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
63338. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
63339. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
63340. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
63341. DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
63342. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
63343. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
63344. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
63345. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
63346. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
63347. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
63348. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
63349. DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
63350. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
63351. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
63352. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
63353. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
63354. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
63355. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
63356. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
63357. DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
63358. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
63359. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
63360. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
63361. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
63362. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
63363. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
63364. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
63365. DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
63366. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
63367. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
63368. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
63369. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
63370. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
63371. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
63372. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
63373. DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
63374. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
63375. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
63376. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
63377. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
63378. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
63379. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
63380. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
63381. DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
63382. DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
63383. DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
63384. DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
63385. DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
63386. DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
63387. DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
63388. DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
63389. DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
63390. DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
63391. DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
63392. DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
63393. DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
63394. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
63395. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
63396. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
63397. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
63398. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
63399. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
63400. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
63401. DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
63402. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
63403. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
63404. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
63405. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
63406. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
63407. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
63408. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
63409. DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
63410. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
63411. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
63412. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
63413. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
63414. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
63415. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
63416. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
63417. DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
63418. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
63419. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
63420. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
63421. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
63422. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
63423. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
63424. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
63425. DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
63426. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
63427. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
63428. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
63429. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
63430. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
63431. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
63432. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
63433. DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
63434. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
63435. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
63436. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
63437. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
63438. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
63439. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
63440. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
63441. DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
63442. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
63443. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
63444. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
63445. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
63446. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
63447. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
63448. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
63449. DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
63450. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
63451. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
63452. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
63453. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
63454. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
63455. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
63456. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
63457. DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
63458. DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
63459. DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
63460. DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
63461. DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
63462. DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
63463. DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
63464. DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
63465. DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
63466. DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
63467. DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
63468. DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
63469. DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
63470. DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
63471. DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
63472. DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
63473. DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
63474. DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
63475. DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
63476. DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK
63477. DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT
63478. DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK
63479. DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT
63480. DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK
63481. DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT
63482. DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK
63483. DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT
63484. DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK
63485. DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT
63486. DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK
63487. DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT
63488. DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK
63489. DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT
63490. DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK
63491. DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT
63492. DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK
63493. DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT
63494. DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK
63495. DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT
63496. DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK
63497. DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT
63498. DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK
63499. DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT
63500. DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK
63501. DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT
63502. DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK
63503. DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT
63504. DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK
63505. DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT
63506. DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK
63507. DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT
63508. DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK
63509. DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT
63510. DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK
63511. DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT
63512. DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK
63513. DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT
63514. DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK
63515. DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT
63516. DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK
63517. DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT
63518. DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK
63519. DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT
63520. DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK
63521. DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT
63522. DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK
63523. DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT
63524. DCP5_CUR_COLOR1__CUR_COLOR1_BLUE_MASK
63525. DCP5_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT
63526. DCP5_CUR_COLOR1__CUR_COLOR1_GREEN_MASK
63527. DCP5_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT
63528. DCP5_CUR_COLOR1__CUR_COLOR1_RED_MASK
63529. DCP5_CUR_COLOR1__CUR_COLOR1_RED__SHIFT
63530. DCP5_CUR_COLOR2__CUR_COLOR2_BLUE_MASK
63531. DCP5_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT
63532. DCP5_CUR_COLOR2__CUR_COLOR2_GREEN_MASK
63533. DCP5_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT
63534. DCP5_CUR_COLOR2__CUR_COLOR2_RED_MASK
63535. DCP5_CUR_COLOR2__CUR_COLOR2_RED__SHIFT
63536. DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK
63537. DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT
63538. DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK
63539. DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT
63540. DCP5_CUR_CONTROL__CURSOR_EN_MASK
63541. DCP5_CUR_CONTROL__CURSOR_EN__SHIFT
63542. DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK
63543. DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT
63544. DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK
63545. DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT
63546. DCP5_CUR_CONTROL__CURSOR_MODE_MASK
63547. DCP5_CUR_CONTROL__CURSOR_MODE__SHIFT
63548. DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK
63549. DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
63550. DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK
63551. DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT
63552. DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK
63553. DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT
63554. DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK
63555. DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT
63556. DCP5_CUR_POSITION__CURSOR_X_POSITION_MASK
63557. DCP5_CUR_POSITION__CURSOR_X_POSITION__SHIFT
63558. DCP5_CUR_POSITION__CURSOR_Y_POSITION_MASK
63559. DCP5_CUR_POSITION__CURSOR_Y_POSITION__SHIFT
63560. DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK
63561. DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT
63562. DCP5_CUR_SIZE__CURSOR_HEIGHT_MASK
63563. DCP5_CUR_SIZE__CURSOR_HEIGHT__SHIFT
63564. DCP5_CUR_SIZE__CURSOR_WIDTH_MASK
63565. DCP5_CUR_SIZE__CURSOR_WIDTH__SHIFT
63566. DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK
63567. DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT
63568. DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK
63569. DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT
63570. DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK
63571. DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT
63572. DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK
63573. DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT
63574. DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK
63575. DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT
63576. DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK
63577. DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT
63578. DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
63579. DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT
63580. DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK
63581. DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT
63582. DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK
63583. DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT
63584. DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK
63585. DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT
63586. DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
63587. DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
63588. DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
63589. DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
63590. DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
63591. DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
63592. DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
63593. DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
63594. DCP5_DCP_CRC_LAST__DCP_CRC_LAST_MASK
63595. DCP5_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
63596. DCP5_DCP_CRC_MASK__DCP_CRC_MASK_MASK
63597. DCP5_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
63598. DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
63599. DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
63600. DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
63601. DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
63602. DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
63603. DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
63604. DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
63605. DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
63606. DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
63607. DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
63608. DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
63609. DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
63610. DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
63611. DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
63612. DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
63613. DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
63614. DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
63615. DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
63616. DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
63617. DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
63618. DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK
63619. DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT
63620. DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
63621. DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
63622. DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
63623. DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
63624. DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
63625. DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
63626. DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
63627. DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
63628. DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
63629. DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
63630. DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
63631. DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
63632. DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
63633. DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
63634. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
63635. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
63636. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
63637. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
63638. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
63639. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
63640. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
63641. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
63642. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
63643. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
63644. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
63645. DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
63646. DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
63647. DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
63648. DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
63649. DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
63650. DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
63651. DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
63652. DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
63653. DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
63654. DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
63655. DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
63656. DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
63657. DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
63658. DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
63659. DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
63660. DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
63661. DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
63662. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
63663. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
63664. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
63665. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
63666. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
63667. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
63668. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
63669. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
63670. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
63671. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
63672. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
63673. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
63674. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
63675. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
63676. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
63677. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
63678. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
63679. DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
63680. DCP5_DC_LUT_CONTROL__DC_LUT_INC_B_MASK
63681. DCP5_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
63682. DCP5_DC_LUT_CONTROL__DC_LUT_INC_G_MASK
63683. DCP5_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
63684. DCP5_DC_LUT_CONTROL__DC_LUT_INC_R_MASK
63685. DCP5_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
63686. DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
63687. DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
63688. DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
63689. DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
63690. DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
63691. DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
63692. DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
63693. DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
63694. DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
63695. DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
63696. DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
63697. DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
63698. DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
63699. DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
63700. DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
63701. DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
63702. DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
63703. DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
63704. DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
63705. DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
63706. DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
63707. DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
63708. DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
63709. DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
63710. DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
63711. DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
63712. DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
63713. DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
63714. DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
63715. DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
63716. DCP5_DENORM_CONTROL__DENORM_14BIT_OUT_MASK
63717. DCP5_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
63718. DCP5_DENORM_CONTROL__DENORM_MODE_MASK
63719. DCP5_DENORM_CONTROL__DENORM_MODE__SHIFT
63720. DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
63721. DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
63722. DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
63723. DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
63724. DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
63725. DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
63726. DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
63727. DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
63728. DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
63729. DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
63730. DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
63731. DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
63732. DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
63733. DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
63734. DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
63735. DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
63736. DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
63737. DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
63738. DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
63739. DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
63740. DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
63741. DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
63742. DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
63743. DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
63744. DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
63745. DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
63746. DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
63747. DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
63748. DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
63749. DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
63750. DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
63751. DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
63752. DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
63753. DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
63754. DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
63755. DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
63756. DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
63757. DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
63758. DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
63759. DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
63760. DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
63761. DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
63762. DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
63763. DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
63764. DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
63765. DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
63766. DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
63767. DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
63768. DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
63769. DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
63770. DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
63771. DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
63772. DCP5_GRPH_CONTROL__GRPH_DEPTH_MASK
63773. DCP5_GRPH_CONTROL__GRPH_DEPTH__SHIFT
63774. DCP5_GRPH_CONTROL__GRPH_DIM_TYPE_MASK
63775. DCP5_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT
63776. DCP5_GRPH_CONTROL__GRPH_FORMAT_MASK
63777. DCP5_GRPH_CONTROL__GRPH_FORMAT__SHIFT
63778. DCP5_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
63779. DCP5_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
63780. DCP5_GRPH_CONTROL__GRPH_NUM_PIPES_MASK
63781. DCP5_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT
63782. DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK
63783. DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT
63784. DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
63785. DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
63786. DCP5_GRPH_CONTROL__GRPH_SE_ENABLE_MASK
63787. DCP5_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT
63788. DCP5_GRPH_CONTROL__GRPH_SW_MODE_MASK
63789. DCP5_GRPH_CONTROL__GRPH_SW_MODE__SHIFT
63790. DCP5_GRPH_CONTROL__GRPH_Z_MASK
63791. DCP5_GRPH_CONTROL__GRPH_Z__SHIFT
63792. DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
63793. DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
63794. DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
63795. DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
63796. DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
63797. DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
63798. DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
63799. DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
63800. DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
63801. DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
63802. DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
63803. DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
63804. DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
63805. DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
63806. DCP5_GRPH_ENABLE__GRPH_ENABLE_MASK
63807. DCP5_GRPH_ENABLE__GRPH_ENABLE__SHIFT
63808. DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
63809. DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
63810. DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
63811. DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
63812. DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
63813. DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
63814. DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
63815. DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
63816. DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
63817. DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
63818. DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
63819. DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
63820. DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
63821. DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
63822. DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
63823. DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
63824. DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
63825. DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
63826. DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
63827. DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
63828. DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
63829. DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
63830. DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
63831. DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
63832. DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
63833. DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
63834. DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
63835. DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
63836. DCP5_GRPH_PITCH__GRPH_PITCH_MASK
63837. DCP5_GRPH_PITCH__GRPH_PITCH__SHIFT
63838. DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
63839. DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
63840. DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
63841. DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
63842. DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
63843. DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
63844. DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
63845. DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
63846. DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
63847. DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
63848. DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
63849. DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
63850. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
63851. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
63852. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
63853. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
63854. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
63855. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
63856. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
63857. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
63858. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
63859. DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
63860. DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
63861. DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
63862. DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
63863. DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
63864. DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
63865. DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
63866. DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
63867. DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
63868. DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
63869. DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
63870. DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
63871. DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
63872. DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
63873. DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
63874. DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
63875. DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
63876. DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
63877. DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
63878. DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
63879. DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
63880. DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
63881. DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
63882. DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
63883. DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
63884. DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
63885. DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
63886. DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
63887. DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
63888. DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
63889. DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
63890. DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
63891. DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
63892. DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
63893. DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
63894. DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
63895. DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
63896. DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
63897. DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
63898. DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
63899. DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
63900. DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
63901. DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
63902. DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
63903. DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
63904. DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK
63905. DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT
63906. DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK
63907. DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT
63908. DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK
63909. DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT
63910. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
63911. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
63912. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
63913. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
63914. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
63915. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
63916. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
63917. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
63918. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
63919. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
63920. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
63921. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
63922. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
63923. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
63924. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
63925. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
63926. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
63927. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
63928. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
63929. DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
63930. DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK
63931. DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT
63932. DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK
63933. DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT
63934. DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK
63935. DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT
63936. DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK
63937. DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT
63938. DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK
63939. DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT
63940. DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
63941. DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
63942. DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
63943. DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
63944. DCP5_GRPH_X_END__GRPH_X_END_MASK
63945. DCP5_GRPH_X_END__GRPH_X_END__SHIFT
63946. DCP5_GRPH_X_START__GRPH_X_START_MASK
63947. DCP5_GRPH_X_START__GRPH_X_START__SHIFT
63948. DCP5_GRPH_Y_END__GRPH_Y_END_MASK
63949. DCP5_GRPH_Y_END__GRPH_Y_END__SHIFT
63950. DCP5_GRPH_Y_START__GRPH_Y_START_MASK
63951. DCP5_GRPH_Y_START__GRPH_Y_START__SHIFT
63952. DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
63953. DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
63954. DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
63955. DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
63956. DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
63957. DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
63958. DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
63959. DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
63960. DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
63961. DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
63962. DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
63963. DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
63964. DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
63965. DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
63966. DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
63967. DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
63968. DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
63969. DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
63970. DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
63971. DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
63972. DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
63973. DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
63974. DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
63975. DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
63976. DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
63977. DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
63978. DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
63979. DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
63980. DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
63981. DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
63982. DCP5_KEY_CONTROL__KEY_MODE_MASK
63983. DCP5_KEY_CONTROL__KEY_MODE__SHIFT
63984. DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK
63985. DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT
63986. DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK
63987. DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT
63988. DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK
63989. DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT
63990. DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK
63991. DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT
63992. DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK
63993. DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT
63994. DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK
63995. DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT
63996. DCP5_KEY_RANGE_RED__KEY_RED_HIGH_MASK
63997. DCP5_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT
63998. DCP5_KEY_RANGE_RED__KEY_RED_LOW_MASK
63999. DCP5_KEY_RANGE_RED__KEY_RED_LOW__SHIFT
64000. DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
64001. DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
64002. DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
64003. DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
64004. DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
64005. DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
64006. DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
64007. DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
64008. DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
64009. DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
64010. DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
64011. DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
64012. DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
64013. DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
64014. DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
64015. DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
64016. DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
64017. DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
64018. DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
64019. DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
64020. DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
64021. DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
64022. DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
64023. DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
64024. DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
64025. DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
64026. DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
64027. DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
64028. DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
64029. DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
64030. DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
64031. DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
64032. DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
64033. DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
64034. DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
64035. DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
64036. DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
64037. DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
64038. DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
64039. DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
64040. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
64041. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
64042. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
64043. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
64044. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
64045. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
64046. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
64047. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
64048. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
64049. DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
64050. DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
64051. DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
64052. DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
64053. DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
64054. DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
64055. DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
64056. DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
64057. DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
64058. DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
64059. DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
64060. DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
64061. DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
64062. DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
64063. DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
64064. DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
64065. DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
64066. DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
64067. DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
64068. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
64069. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
64070. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
64071. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
64072. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
64073. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
64074. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
64075. DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
64076. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
64077. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
64078. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
64079. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
64080. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
64081. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
64082. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
64083. DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
64084. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
64085. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
64086. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
64087. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
64088. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
64089. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
64090. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
64091. DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
64092. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
64093. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
64094. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
64095. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
64096. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
64097. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
64098. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
64099. DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
64100. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
64101. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
64102. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
64103. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
64104. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
64105. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
64106. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
64107. DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
64108. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
64109. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
64110. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
64111. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
64112. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
64113. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
64114. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
64115. DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
64116. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
64117. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
64118. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
64119. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
64120. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
64121. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
64122. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
64123. DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
64124. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
64125. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
64126. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
64127. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
64128. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
64129. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
64130. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
64131. DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
64132. DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
64133. DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
64134. DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
64135. DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
64136. DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
64137. DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
64138. DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
64139. DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
64140. DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
64141. DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
64142. DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
64143. DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
64144. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
64145. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
64146. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
64147. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
64148. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
64149. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
64150. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
64151. DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
64152. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
64153. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
64154. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
64155. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
64156. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
64157. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
64158. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
64159. DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
64160. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
64161. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
64162. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
64163. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
64164. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
64165. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
64166. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
64167. DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
64168. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
64169. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
64170. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
64171. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
64172. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
64173. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
64174. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
64175. DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
64176. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
64177. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
64178. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
64179. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
64180. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
64181. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
64182. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
64183. DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
64184. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
64185. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
64186. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
64187. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
64188. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
64189. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
64190. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
64191. DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
64192. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
64193. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
64194. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
64195. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
64196. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
64197. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
64198. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
64199. DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
64200. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
64201. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
64202. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
64203. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
64204. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
64205. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
64206. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
64207. DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
64208. DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
64209. DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
64210. DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
64211. DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
64212. DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
64213. DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
64214. DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
64215. DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
64216. DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
64217. DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
64218. DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
64219. DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
64220. DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
64221. DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
64222. DCPCFG
64223. DCPCR
64224. DCPCR_CA2B
64225. DCPCR_CAB
64226. DCPCR_CD2F
64227. DCPCR_CDF
64228. DCPCR_CODE
64229. DCPCR_DC2E
64230. DCPCR_DCE
64231. DCPCTR
64232. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR_MASK
64233. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT
64234. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK_MASK
64235. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK__SHIFT
64236. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR_MASK
64237. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR__SHIFT
64238. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK_MASK
64239. DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK__SHIFT
64240. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK
64241. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT
64242. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK
64243. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT
64244. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK
64245. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT
64246. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK
64247. DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT
64248. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK
64249. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT
64250. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK
64251. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT
64252. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK
64253. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT
64254. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK
64255. DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT
64256. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK
64257. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT
64258. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK
64259. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT
64260. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK
64261. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT
64262. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK
64263. DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT
64264. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK
64265. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT
64266. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK
64267. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT
64268. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK
64269. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT
64270. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK
64271. DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT
64272. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK
64273. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT
64274. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK
64275. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT
64276. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK
64277. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT
64278. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK
64279. DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT
64280. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK
64281. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT
64282. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK
64283. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT
64284. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK
64285. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT
64286. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK
64287. DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT
64288. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK
64289. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT
64290. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK
64291. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT
64292. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK
64293. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT
64294. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK
64295. DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT
64296. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK
64297. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT
64298. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK
64299. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT
64300. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK
64301. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT
64302. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK
64303. DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT
64304. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK
64305. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT
64306. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK
64307. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT
64308. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK
64309. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT
64310. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK
64311. DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT
64312. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK
64313. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT
64314. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK
64315. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT
64316. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK
64317. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT
64318. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK
64319. DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT
64320. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK
64321. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT
64322. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK
64323. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT
64324. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK
64325. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT
64326. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK
64327. DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT
64328. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK
64329. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT
64330. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK
64331. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT
64332. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK
64333. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT
64334. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK
64335. DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT
64336. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK
64337. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT
64338. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK
64339. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT
64340. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK
64341. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT
64342. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK
64343. DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT
64344. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK
64345. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT
64346. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK
64347. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT
64348. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK
64349. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT
64350. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK
64351. DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT
64352. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK
64353. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT
64354. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK
64355. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT
64356. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK
64357. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT
64358. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK
64359. DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT
64360. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK
64361. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT
64362. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK
64363. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT
64364. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK
64365. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT
64366. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK
64367. DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT
64368. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK
64369. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT
64370. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK
64371. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT
64372. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK
64373. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT
64374. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK
64375. DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT
64376. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK
64377. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT
64378. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK
64379. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT
64380. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK
64381. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT
64382. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK
64383. DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT
64384. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK
64385. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT
64386. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK
64387. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT
64388. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK
64389. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT
64390. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK
64391. DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT
64392. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK
64393. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT
64394. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK
64395. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT
64396. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK
64397. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT
64398. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK
64399. DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT
64400. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK
64401. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT
64402. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK
64403. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT
64404. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK
64405. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT
64406. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK
64407. DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT
64408. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK
64409. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT
64410. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK
64411. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT
64412. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK
64413. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT
64414. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK
64415. DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT
64416. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK
64417. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT
64418. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK
64419. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT
64420. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK
64421. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT
64422. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK
64423. DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT
64424. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK
64425. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT
64426. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK
64427. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT
64428. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK
64429. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT
64430. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK
64431. DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT
64432. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK
64433. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT
64434. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK
64435. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT
64436. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK
64437. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT
64438. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK
64439. DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT
64440. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK
64441. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT
64442. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK
64443. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT
64444. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK
64445. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT
64446. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK
64447. DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT
64448. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK
64449. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT
64450. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK
64451. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT
64452. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK
64453. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT
64454. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK
64455. DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT
64456. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK
64457. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT
64458. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK
64459. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT
64460. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK
64461. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT
64462. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK
64463. DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT
64464. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK
64465. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT
64466. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK
64467. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT
64468. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK
64469. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT
64470. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK
64471. DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT
64472. DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK
64473. DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT
64474. DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK
64475. DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT
64476. DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK
64477. DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT
64478. DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK
64479. DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT
64480. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK
64481. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT
64482. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK
64483. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT
64484. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK
64485. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT
64486. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK
64487. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT
64488. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK
64489. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT
64490. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK
64491. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT
64492. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK
64493. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT
64494. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK
64495. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT
64496. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK
64497. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT
64498. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK
64499. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT
64500. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK
64501. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT
64502. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK
64503. DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT
64504. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK
64505. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT
64506. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK
64507. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT
64508. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK
64509. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT
64510. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK
64511. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT
64512. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK
64513. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT
64514. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK
64515. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT
64516. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK
64517. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT
64518. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK
64519. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT
64520. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK
64521. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT
64522. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK
64523. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT
64524. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK
64525. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT
64526. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK
64527. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT
64528. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK
64529. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT
64530. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK
64531. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT
64532. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK
64533. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT
64534. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK
64535. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT
64536. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK
64537. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT
64538. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK
64539. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT
64540. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK
64541. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT
64542. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK
64543. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT
64544. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK
64545. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT
64546. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK
64547. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT
64548. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK
64549. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT
64550. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK
64551. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT
64552. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK
64553. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT
64554. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK
64555. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT
64556. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK
64557. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT
64558. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK
64559. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT
64560. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK
64561. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT
64562. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK
64563. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT
64564. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK
64565. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT
64566. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK
64567. DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT
64568. DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK
64569. DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT
64570. DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK
64571. DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT
64572. DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK
64573. DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT
64574. DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK
64575. DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT
64576. DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK
64577. DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT
64578. DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK
64579. DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT
64580. DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK
64581. DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT
64582. DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK
64583. DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT
64584. DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK
64585. DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT
64586. DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK
64587. DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT
64588. DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK
64589. DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT
64590. DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK
64591. DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT
64592. DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK
64593. DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT
64594. DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK
64595. DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT
64596. DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK
64597. DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT
64598. DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK
64599. DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT
64600. DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK
64601. DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT
64602. DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK
64603. DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT
64604. DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK
64605. DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT
64606. DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK
64607. DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT
64608. DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK
64609. DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT
64610. DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK
64611. DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT
64612. DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK
64613. DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT
64614. DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK
64615. DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT
64616. DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK
64617. DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT
64618. DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK
64619. DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT
64620. DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED_MASK
64621. DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT
64622. DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED_MASK
64623. DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT
64624. DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK
64625. DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT
64626. DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK
64627. DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT
64628. DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK
64629. DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT
64630. DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK
64631. DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT
64632. DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK
64633. DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT
64634. DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK
64635. DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT
64636. DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK
64637. DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT
64638. DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK
64639. DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT
64640. DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK
64641. DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT
64642. DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK
64643. DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT
64644. DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK
64645. DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT
64646. DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK
64647. DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT
64648. DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK
64649. DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT
64650. DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK
64651. DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT
64652. DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK
64653. DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT
64654. DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK
64655. DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT
64656. DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK
64657. DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT
64658. DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK
64659. DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT
64660. DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK
64661. DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT
64662. DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK
64663. DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT
64664. DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK
64665. DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT
64666. DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK
64667. DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT
64668. DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK
64669. DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT
64670. DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK
64671. DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT
64672. DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK
64673. DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT
64674. DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK
64675. DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT
64676. DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK
64677. DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT
64678. DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK
64679. DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT
64680. DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK
64681. DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT
64682. DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK
64683. DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT
64684. DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK
64685. DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT
64686. DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK
64687. DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT
64688. DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK
64689. DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT
64690. DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK
64691. DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT
64692. DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK
64693. DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT
64694. DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK
64695. DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT
64696. DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK
64697. DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT
64698. DCPIN
64699. DCPMAXP
64700. DCPP
64701. DCPU_CLK_DISABLE_SHIFT
64702. DCPU_IS_SLAVE
64703. DCPU_MSG_RAM
64704. DCPU_MSG_RAM_START
64705. DCPU_NEXT_MASTER
64706. DCPU_RESET_MASK
64707. DCPU_RESET_SHIFT
64708. DCPU_RET_ERROR_BIT
64709. DCPU_RET_ERR_CHKSUM
64710. DCPU_RET_ERR_COMMAND
64711. DCPU_RET_ERR_HEADER
64712. DCPU_RET_ERR_INVAL
64713. DCPU_RET_ERR_TIMEDOUT
64714. DCPU_RET_SUCCESS
64715. DCPU_SSTEP
64716. DCPU_WANT_MASTER
64717. DCP_ALIGNMENT
64718. DCP_ALPHA_ROUND_TRUNC_MODE
64719. DCP_ALPHA_ROUND_TRUNC_MODE_ROUND
64720. DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC
64721. DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED
64722. DCP_BIT_DEPTH_REDUCTION_MODE_DITHER
64723. DCP_BIT_DEPTH_REDUCTION_MODE_INVALID
64724. DCP_BIT_DEPTH_REDUCTION_MODE_ROUND
64725. DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE
64726. DCP_BUF_SZ
64727. DCP_CHAN_CRYPTO
64728. DCP_CHAN_HASH_SHA
64729. DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK
64730. DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT
64731. DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK
64732. DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT
64733. DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK
64734. DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT
64735. DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK
64736. DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT
64737. DCP_CRC_ENABLE
64738. DCP_CRC_ENABLE_FALSE
64739. DCP_CRC_ENABLE_TRUE
64740. DCP_CRC_LAST__DCP_CRC_LAST_MASK
64741. DCP_CRC_LAST__DCP_CRC_LAST__SHIFT
64742. DCP_CRC_LINE_SEL
64743. DCP_CRC_LINE_SEL_BOTH
64744. DCP_CRC_LINE_SEL_EVEN
64745. DCP_CRC_LINE_SEL_ODD
64746. DCP_CRC_LINE_SEL_RESERVED
64747. DCP_CRC_MASK__DCP_CRC_MASK_MASK
64748. DCP_CRC_MASK__DCP_CRC_MASK__SHIFT
64749. DCP_CRC_SOURCE_SEL
64750. DCP_CRC_SOURCE_SEL_INPUT_H32
64751. DCP_CRC_SOURCE_SEL_INPUT_L32
64752. DCP_CRC_SOURCE_SEL_OUTPUT_CNTL
64753. DCP_CRC_SOURCE_SEL_OUTPUT_PIX
64754. DCP_CUR2_INV_TRANS_CLAMP
64755. DCP_CUR2_INV_TRANS_CLAMP_FALSE
64756. DCP_CUR2_INV_TRANS_CLAMP_TRUE
64757. DCP_CURSOR2_2X_MAGNIFY
64758. DCP_CURSOR2_2X_MAGNIFY_FALSE
64759. DCP_CURSOR2_2X_MAGNIFY_TRUE
64760. DCP_CURSOR2_DEGAMMA_MODE
64761. DCP_CURSOR2_DEGAMMA_MODE_BYPASS
64762. DCP_CURSOR2_DEGAMMA_MODE_RESERVED
64763. DCP_CURSOR2_DEGAMMA_MODE_ROMA
64764. DCP_CURSOR2_DEGAMMA_MODE_ROMB
64765. DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE
64766. DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE
64767. DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE
64768. DCP_CURSOR2_EN
64769. DCP_CURSOR2_EN_FALSE
64770. DCP_CURSOR2_EN_TRUE
64771. DCP_CURSOR2_FORCE_MC_ON
64772. DCP_CURSOR2_FORCE_MC_ON_FALSE
64773. DCP_CURSOR2_FORCE_MC_ON_TRUE
64774. DCP_CURSOR2_MODE
64775. DCP_CURSOR2_MODE_24BPP_1BIT
64776. DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI
64777. DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI
64778. DCP_CURSOR2_MODE_MONO_2BPP
64779. DCP_CURSOR2_STEREO_EN
64780. DCP_CURSOR2_STEREO_EN_FALSE
64781. DCP_CURSOR2_STEREO_EN_TRUE
64782. DCP_CURSOR2_STEREO_OFFSET_YNX
64783. DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION
64784. DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION
64785. DCP_CURSOR2_UPDATE_LOCK
64786. DCP_CURSOR2_UPDATE_LOCK_FALSE
64787. DCP_CURSOR2_UPDATE_LOCK_TRUE
64788. DCP_CURSOR2_UPDATE_PENDING
64789. DCP_CURSOR2_UPDATE_PENDING_FALSE
64790. DCP_CURSOR2_UPDATE_PENDING_TRUE
64791. DCP_CURSOR2_UPDATE_STEREO_MODE
64792. DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH
64793. DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY
64794. DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY
64795. DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED
64796. DCP_CURSOR2_UPDATE_TAKEN
64797. DCP_CURSOR2_UPDATE_TAKEN_FALSE
64798. DCP_CURSOR2_UPDATE_TAKEN_TRUE
64799. DCP_CURSOR2_URGENT_CONTROL
64800. DCP_CURSOR2_URGENT_CONTROL_MODE_0
64801. DCP_CURSOR2_URGENT_CONTROL_MODE_1
64802. DCP_CURSOR2_URGENT_CONTROL_MODE_2
64803. DCP_CURSOR2_URGENT_CONTROL_MODE_3
64804. DCP_CURSOR2_URGENT_CONTROL_MODE_4
64805. DCP_CURSOR_2X_MAGNIFY
64806. DCP_CURSOR_2X_MAGNIFY_FALSE
64807. DCP_CURSOR_2X_MAGNIFY_TRUE
64808. DCP_CURSOR_ALPHA_BLND_ENA
64809. DCP_CURSOR_ALPHA_BLND_ENA_FALSE
64810. DCP_CURSOR_ALPHA_BLND_ENA_TRUE
64811. DCP_CURSOR_DEGAMMA_MODE
64812. DCP_CURSOR_DEGAMMA_MODE_BYPASS
64813. DCP_CURSOR_DEGAMMA_MODE_RESERVED
64814. DCP_CURSOR_DEGAMMA_MODE_ROMA
64815. DCP_CURSOR_DEGAMMA_MODE_ROMB
64816. DCP_CURSOR_DISABLE_MULTIPLE_UPDATE
64817. DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE
64818. DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE
64819. DCP_CURSOR_EN
64820. DCP_CURSOR_EN_FALSE
64821. DCP_CURSOR_EN_TRUE
64822. DCP_CURSOR_FORCE_MC_ON
64823. DCP_CURSOR_FORCE_MC_ON_FALSE
64824. DCP_CURSOR_FORCE_MC_ON_TRUE
64825. DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM
64826. DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE
64827. DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO
64828. DCP_CURSOR_MODE
64829. DCP_CURSOR_MODE_24BPP_1BIT
64830. DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI
64831. DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI
64832. DCP_CURSOR_MODE_MONO_2BPP
64833. DCP_CURSOR_STEREO_EN
64834. DCP_CURSOR_STEREO_EN_FALSE
64835. DCP_CURSOR_STEREO_EN_TRUE
64836. DCP_CURSOR_STEREO_OFFSET_YNX
64837. DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION
64838. DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION
64839. DCP_CURSOR_UPDATE_LOCK
64840. DCP_CURSOR_UPDATE_LOCK_FALSE
64841. DCP_CURSOR_UPDATE_LOCK_TRUE
64842. DCP_CURSOR_UPDATE_PENDING
64843. DCP_CURSOR_UPDATE_PENDING_FALSE
64844. DCP_CURSOR_UPDATE_PENDING_TRUE
64845. DCP_CURSOR_UPDATE_STEREO_MODE
64846. DCP_CURSOR_UPDATE_STEREO_MODE_BOTH
64847. DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY
64848. DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY
64849. DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED
64850. DCP_CURSOR_UPDATE_TAKEN
64851. DCP_CURSOR_UPDATE_TAKEN_FALSE
64852. DCP_CURSOR_UPDATE_TAKEN_TRUE
64853. DCP_CURSOR_URGENT_CONTROL
64854. DCP_CURSOR_URGENT_CONTROL_MODE_0
64855. DCP_CURSOR_URGENT_CONTROL_MODE_1
64856. DCP_CURSOR_URGENT_CONTROL_MODE_2
64857. DCP_CURSOR_URGENT_CONTROL_MODE_3
64858. DCP_CURSOR_URGENT_CONTROL_MODE_4
64859. DCP_CUR_INV_TRANS_CLAMP
64860. DCP_CUR_INV_TRANS_CLAMP_FALSE
64861. DCP_CUR_INV_TRANS_CLAMP_TRUE
64862. DCP_CUR_REQUEST_FILTER_DIS
64863. DCP_CUR_REQUEST_FILTER_DIS_FALSE
64864. DCP_CUR_REQUEST_FILTER_DIS_TRUE
64865. DCP_DC_LUT_AUTOFILL
64866. DCP_DC_LUT_AUTOFILL_DONE
64867. DCP_DC_LUT_AUTOFILL_DONE_FALSE
64868. DCP_DC_LUT_AUTOFILL_DONE_TRUE
64869. DCP_DC_LUT_AUTOFILL_FALSE
64870. DCP_DC_LUT_AUTOFILL_TRUE
64871. DCP_DC_LUT_DATA_B_FLOAT_POINT_EN
64872. DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE
64873. DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE
64874. DCP_DC_LUT_DATA_B_FORMAT
64875. DCP_DC_LUT_DATA_B_FORMAT_S1P10
64876. DCP_DC_LUT_DATA_B_FORMAT_U0P10
64877. DCP_DC_LUT_DATA_B_FORMAT_U0P12
64878. DCP_DC_LUT_DATA_B_FORMAT_U1P11
64879. DCP_DC_LUT_DATA_B_SIGNED_EN
64880. DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE
64881. DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE
64882. DCP_DC_LUT_DATA_G_FLOAT_POINT_EN
64883. DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE
64884. DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE
64885. DCP_DC_LUT_DATA_G_FORMAT
64886. DCP_DC_LUT_DATA_G_FORMAT_S1P10
64887. DCP_DC_LUT_DATA_G_FORMAT_U0P10
64888. DCP_DC_LUT_DATA_G_FORMAT_U0P12
64889. DCP_DC_LUT_DATA_G_FORMAT_U1P11
64890. DCP_DC_LUT_DATA_G_SIGNED_EN
64891. DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE
64892. DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE
64893. DCP_DC_LUT_DATA_R_FLOAT_POINT_EN
64894. DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE
64895. DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE
64896. DCP_DC_LUT_DATA_R_FORMAT
64897. DCP_DC_LUT_DATA_R_FORMAT_S1P10
64898. DCP_DC_LUT_DATA_R_FORMAT_U0P10
64899. DCP_DC_LUT_DATA_R_FORMAT_U0P12
64900. DCP_DC_LUT_DATA_R_FORMAT_U1P11
64901. DCP_DC_LUT_DATA_R_SIGNED_EN
64902. DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE
64903. DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE
64904. DCP_DC_LUT_INC_B
64905. DCP_DC_LUT_INC_B_128
64906. DCP_DC_LUT_INC_B_16
64907. DCP_DC_LUT_INC_B_2
64908. DCP_DC_LUT_INC_B_256
64909. DCP_DC_LUT_INC_B_32
64910. DCP_DC_LUT_INC_B_4
64911. DCP_DC_LUT_INC_B_512
64912. DCP_DC_LUT_INC_B_64
64913. DCP_DC_LUT_INC_B_8
64914. DCP_DC_LUT_INC_B_NA
64915. DCP_DC_LUT_INC_G
64916. DCP_DC_LUT_INC_G_128
64917. DCP_DC_LUT_INC_G_16
64918. DCP_DC_LUT_INC_G_2
64919. DCP_DC_LUT_INC_G_256
64920. DCP_DC_LUT_INC_G_32
64921. DCP_DC_LUT_INC_G_4
64922. DCP_DC_LUT_INC_G_512
64923. DCP_DC_LUT_INC_G_64
64924. DCP_DC_LUT_INC_G_8
64925. DCP_DC_LUT_INC_G_NA
64926. DCP_DC_LUT_INC_R
64927. DCP_DC_LUT_INC_R_128
64928. DCP_DC_LUT_INC_R_16
64929. DCP_DC_LUT_INC_R_2
64930. DCP_DC_LUT_INC_R_256
64931. DCP_DC_LUT_INC_R_32
64932. DCP_DC_LUT_INC_R_4
64933. DCP_DC_LUT_INC_R_512
64934. DCP_DC_LUT_INC_R_64
64935. DCP_DC_LUT_INC_R_8
64936. DCP_DC_LUT_INC_R_NA
64937. DCP_DC_LUT_RW_MODE
64938. DCP_DC_LUT_RW_MODE_256_ENTRY
64939. DCP_DC_LUT_RW_MODE_PWL
64940. DCP_DC_LUT_VGA_ACCESS_ENABLE
64941. DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE
64942. DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE
64943. DCP_DEBUG2__DCP_DEBUG2_MASK
64944. DCP_DEBUG2__DCP_DEBUG2__SHIFT
64945. DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK
64946. DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT
64947. DCP_DEBUG_SG__DCP_DEBUG_SG_MASK
64948. DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT
64949. DCP_DEBUG__DCP_DEBUG_MASK
64950. DCP_DEBUG__DCP_DEBUG__SHIFT
64951. DCP_DENORM_14BIT_OUT
64952. DCP_DENORM_14BIT_OUT_FALSE
64953. DCP_DENORM_14BIT_OUT_TRUE
64954. DCP_DENORM_MODE
64955. DCP_DENORM_MODE_10BIT
64956. DCP_DENORM_MODE_11BIT
64957. DCP_DENORM_MODE_12BIT
64958. DCP_DENORM_MODE_6BIT
64959. DCP_DENORM_MODE_8BIT
64960. DCP_DENORM_MODE_RESERVED0
64961. DCP_DENORM_MODE_RESERVED1
64962. DCP_DENORM_MODE_UNITY
64963. DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK
64964. DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT
64965. DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK
64966. DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT
64967. DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK
64968. DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT
64969. DCP_FRAME_RANDOM_ENABLE
64970. DCP_FRAME_RANDOM_ENABLE_FALSE
64971. DCP_FRAME_RANDOM_ENABLE_TRUE
64972. DCP_GRPH_ADDRESS_TRANSLATION_ENABLE
64973. DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE
64974. DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE
64975. DCP_GRPH_ALPHA_CROSSBAR
64976. DCP_GRPH_ALPHA_CROSSBAR_FROM_A
64977. DCP_GRPH_ALPHA_CROSSBAR_FROM_B
64978. DCP_GRPH_ALPHA_CROSSBAR_FROM_G
64979. DCP_GRPH_ALPHA_CROSSBAR_FROM_R
64980. DCP_GRPH_ARRAY_MODE
64981. DCP_GRPH_ARRAY_MODE_0
64982. DCP_GRPH_ARRAY_MODE_1
64983. DCP_GRPH_ARRAY_MODE_12
64984. DCP_GRPH_ARRAY_MODE_13
64985. DCP_GRPH_ARRAY_MODE_2
64986. DCP_GRPH_ARRAY_MODE_3
64987. DCP_GRPH_ARRAY_MODE_4
64988. DCP_GRPH_ARRAY_MODE_7
64989. DCP_GRPH_BANK_HEIGHT
64990. DCP_GRPH_BANK_HEIGHT_1
64991. DCP_GRPH_BANK_HEIGHT_2
64992. DCP_GRPH_BANK_HEIGHT_4
64993. DCP_GRPH_BANK_HEIGHT_8
64994. DCP_GRPH_BANK_WIDTH
64995. DCP_GRPH_BANK_WIDTH_1
64996. DCP_GRPH_BANK_WIDTH_2
64997. DCP_GRPH_BANK_WIDTH_4
64998. DCP_GRPH_BANK_WIDTH_8
64999. DCP_GRPH_BLUE_CROSSBAR
65000. DCP_GRPH_BLUE_CROSSBAR_FROM_A
65001. DCP_GRPH_BLUE_CROSSBAR_FROM_B
65002. DCP_GRPH_BLUE_CROSSBAR_FROM_G
65003. DCP_GRPH_BLUE_CROSSBAR_FROM_R
65004. DCP_GRPH_COLOR_EXPANSION_MODE
65005. DCP_GRPH_COLOR_EXPANSION_MODE_DEXP
65006. DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP
65007. DCP_GRPH_DEGAMMA_MODE
65008. DCP_GRPH_DEGAMMA_MODE_BYPASS
65009. DCP_GRPH_DEGAMMA_MODE_RESERVED
65010. DCP_GRPH_DEGAMMA_MODE_ROMA
65011. DCP_GRPH_DEGAMMA_MODE_ROMB
65012. DCP_GRPH_DEPTH
65013. DCP_GRPH_DEPTH_16BPP
65014. DCP_GRPH_DEPTH_32BPP
65015. DCP_GRPH_DEPTH_64BPP
65016. DCP_GRPH_DEPTH_8BPP
65017. DCP_GRPH_DFQ_MIN_FREE_ENTRIES
65018. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1
65019. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2
65020. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3
65021. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4
65022. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5
65023. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6
65024. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7
65025. DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8
65026. DCP_GRPH_DFQ_RESET
65027. DCP_GRPH_DFQ_RESET_ACK
65028. DCP_GRPH_DFQ_RESET_ACK_FALSE
65029. DCP_GRPH_DFQ_RESET_ACK_TRUE
65030. DCP_GRPH_DFQ_RESET_FALSE
65031. DCP_GRPH_DFQ_RESET_TRUE
65032. DCP_GRPH_DFQ_SIZE
65033. DCP_GRPH_DFQ_SIZE_DEEP1
65034. DCP_GRPH_DFQ_SIZE_DEEP2
65035. DCP_GRPH_DFQ_SIZE_DEEP3
65036. DCP_GRPH_DFQ_SIZE_DEEP4
65037. DCP_GRPH_DFQ_SIZE_DEEP5
65038. DCP_GRPH_DFQ_SIZE_DEEP6
65039. DCP_GRPH_DFQ_SIZE_DEEP7
65040. DCP_GRPH_DFQ_SIZE_DEEP8
65041. DCP_GRPH_ENABLE
65042. DCP_GRPH_ENABLE_FALSE
65043. DCP_GRPH_ENABLE_TRUE
65044. DCP_GRPH_ENDIAN_SWAP
65045. DCP_GRPH_ENDIAN_SWAP_8IN16
65046. DCP_GRPH_ENDIAN_SWAP_8IN32
65047. DCP_GRPH_ENDIAN_SWAP_8IN64
65048. DCP_GRPH_ENDIAN_SWAP_NONE
65049. DCP_GRPH_FLIP_RATE
65050. DCP_GRPH_FLIP_RATE_1FRAME
65051. DCP_GRPH_FLIP_RATE_2FRAME
65052. DCP_GRPH_FLIP_RATE_3FRAME
65053. DCP_GRPH_FLIP_RATE_4FRAME
65054. DCP_GRPH_FLIP_RATE_5FRAME
65055. DCP_GRPH_FLIP_RATE_6FRAME
65056. DCP_GRPH_FLIP_RATE_7FRAME
65057. DCP_GRPH_FLIP_RATE_8FRAME
65058. DCP_GRPH_FLIP_RATE_ENABLE
65059. DCP_GRPH_FLIP_RATE_ENABLE_FALSE
65060. DCP_GRPH_FLIP_RATE_ENABLE_TRUE
65061. DCP_GRPH_FORMAT
65062. DCP_GRPH_FORMAT_16BPP
65063. DCP_GRPH_FORMAT_32BPP
65064. DCP_GRPH_FORMAT_64BPP
65065. DCP_GRPH_FORMAT_8BPP
65066. DCP_GRPH_GAMUT_REMAP_MODE
65067. DCP_GRPH_GAMUT_REMAP_MODE_BYPASS
65068. DCP_GRPH_GAMUT_REMAP_MODE_RESERVED
65069. DCP_GRPH_GAMUT_REMAP_MODE_ROMA
65070. DCP_GRPH_GAMUT_REMAP_MODE_ROMB
65071. DCP_GRPH_GREEN_CROSSBAR
65072. DCP_GRPH_GREEN_CROSSBAR_FROM_A
65073. DCP_GRPH_GREEN_CROSSBAR_FROM_B
65074. DCP_GRPH_GREEN_CROSSBAR_FROM_G
65075. DCP_GRPH_GREEN_CROSSBAR_FROM_R
65076. DCP_GRPH_INPUT_GAMMA_MODE
65077. DCP_GRPH_INPUT_GAMMA_MODE_BYPASS
65078. DCP_GRPH_INPUT_GAMMA_MODE_LUT
65079. DCP_GRPH_KEYER_ALPHA_SEL
65080. DCP_GRPH_KEYER_ALPHA_SEL_FALSE
65081. DCP_GRPH_KEYER_ALPHA_SEL_TRUE
65082. DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN
65083. DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE
65084. DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE
65085. DCP_GRPH_LUT_10BIT_BYPASS_EN
65086. DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE
65087. DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE
65088. DCP_GRPH_MACRO_TILE_ASPECT
65089. DCP_GRPH_MACRO_TILE_ASPECT_1
65090. DCP_GRPH_MACRO_TILE_ASPECT_2
65091. DCP_GRPH_MACRO_TILE_ASPECT_4
65092. DCP_GRPH_MACRO_TILE_ASPECT_8
65093. DCP_GRPH_MICRO_TILE_MODE
65094. DCP_GRPH_MICRO_TILE_MODE_0
65095. DCP_GRPH_MICRO_TILE_MODE_1
65096. DCP_GRPH_MICRO_TILE_MODE_2
65097. DCP_GRPH_MICRO_TILE_MODE_3
65098. DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE
65099. DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE
65100. DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE
65101. DCP_GRPH_MODE_UPDATE_PENDING
65102. DCP_GRPH_MODE_UPDATE_PENDING_FALSE
65103. DCP_GRPH_MODE_UPDATE_PENDING_TRUE
65104. DCP_GRPH_MODE_UPDATE_TAKEN
65105. DCP_GRPH_MODE_UPDATE_TAKEN_FALSE
65106. DCP_GRPH_MODE_UPDATE_TAKEN_TRUE
65107. DCP_GRPH_NUM_BANKS
65108. DCP_GRPH_NUM_BANKS_16BANK
65109. DCP_GRPH_NUM_BANKS_1BANK
65110. DCP_GRPH_NUM_BANKS_2BANK
65111. DCP_GRPH_NUM_BANKS_4BANK
65112. DCP_GRPH_NUM_BANKS_8BANK
65113. DCP_GRPH_NUM_PIPES
65114. DCP_GRPH_NUM_PIPES_1PIPE
65115. DCP_GRPH_NUM_PIPES_2PIPE
65116. DCP_GRPH_NUM_PIPES_4PIPE
65117. DCP_GRPH_NUM_PIPES_8PIPE
65118. DCP_GRPH_PFLIP_INT_CLEAR
65119. DCP_GRPH_PFLIP_INT_CLEAR_FALSE
65120. DCP_GRPH_PFLIP_INT_CLEAR_TRUE
65121. DCP_GRPH_PFLIP_INT_MASK
65122. DCP_GRPH_PFLIP_INT_MASK_FALSE
65123. DCP_GRPH_PFLIP_INT_MASK_TRUE
65124. DCP_GRPH_PFLIP_INT_TYPE
65125. DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL
65126. DCP_GRPH_PFLIP_INT_TYPE_PULSE
65127. DCP_GRPH_PRESCALE_BYPASS
65128. DCP_GRPH_PRESCALE_BYPASS_FALSE
65129. DCP_GRPH_PRESCALE_BYPASS_TRUE
65130. DCP_GRPH_PRESCALE_B_SIGN
65131. DCP_GRPH_PRESCALE_B_SIGN_SIGNED
65132. DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED
65133. DCP_GRPH_PRESCALE_G_SIGN
65134. DCP_GRPH_PRESCALE_G_SIGN_SIGNED
65135. DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED
65136. DCP_GRPH_PRESCALE_R_SIGN
65137. DCP_GRPH_PRESCALE_R_SIGN_SIGNED
65138. DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED
65139. DCP_GRPH_PRESCALE_SELECT
65140. DCP_GRPH_PRESCALE_SELECT_FIXED
65141. DCP_GRPH_PRESCALE_SELECT_FLOATING
65142. DCP_GRPH_PRIMARY_DFQ_ENABLE
65143. DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE
65144. DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE
65145. DCP_GRPH_PRIVILEGED_ACCESS_ENABLE
65146. DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE
65147. DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE
65148. DCP_GRPH_RED_CROSSBAR
65149. DCP_GRPH_RED_CROSSBAR_FROM_A
65150. DCP_GRPH_RED_CROSSBAR_FROM_B
65151. DCP_GRPH_RED_CROSSBAR_FROM_G
65152. DCP_GRPH_RED_CROSSBAR_FROM_R
65153. DCP_GRPH_REGAMMA_MODE
65154. DCP_GRPH_REGAMMA_MODE_BYPASS
65155. DCP_GRPH_REGAMMA_MODE_PROGA
65156. DCP_GRPH_REGAMMA_MODE_PROGB
65157. DCP_GRPH_REGAMMA_MODE_SRGB
65158. DCP_GRPH_REGAMMA_MODE_XVYCC
65159. DCP_GRPH_ROTATION_ANGLE
65160. DCP_GRPH_ROTATION_ANGLE_0
65161. DCP_GRPH_ROTATION_ANGLE_180
65162. DCP_GRPH_ROTATION_ANGLE_270
65163. DCP_GRPH_ROTATION_ANGLE_90
65164. DCP_GRPH_SECONDARY_DFQ_ENABLE
65165. DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE
65166. DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE
65167. DCP_GRPH_STEREOSYNC_FLIP_EN
65168. DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE
65169. DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE
65170. DCP_GRPH_STEREOSYNC_FLIP_MODE
65171. DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP
65172. DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0
65173. DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1
65174. DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET
65175. DCP_GRPH_STEREOSYNC_SELECT_DISABLE
65176. DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE
65177. DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE
65178. DCP_GRPH_SURFACE_COUNTER_EN
65179. DCP_GRPH_SURFACE_COUNTER_EN_DISABLE
65180. DCP_GRPH_SURFACE_COUNTER_EN_ENABLE
65181. DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED
65182. DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO
65183. DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES
65184. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT
65185. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0
65186. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1
65187. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10
65188. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11
65189. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2
65190. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3
65191. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4
65192. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5
65193. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6
65194. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7
65195. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8
65196. DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9
65197. DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE
65198. DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE
65199. DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE
65200. DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK
65201. DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE
65202. DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE
65203. DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN
65204. DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE
65205. DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE
65206. DCP_GRPH_SURFACE_UPDATE_PENDING
65207. DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE
65208. DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE
65209. DCP_GRPH_SURFACE_UPDATE_TAKEN
65210. DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE
65211. DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE
65212. DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE
65213. DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE
65214. DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE
65215. DCP_GRPH_SW_MODE
65216. DCP_GRPH_SW_MODE_0
65217. DCP_GRPH_SW_MODE_2
65218. DCP_GRPH_SW_MODE_22
65219. DCP_GRPH_SW_MODE_23
65220. DCP_GRPH_SW_MODE_26
65221. DCP_GRPH_SW_MODE_27
65222. DCP_GRPH_SW_MODE_3
65223. DCP_GRPH_SW_MODE_30
65224. DCP_GRPH_SW_MODE_31
65225. DCP_GRPH_TILE_SPLIT
65226. DCP_GRPH_TILE_SPLIT_128B
65227. DCP_GRPH_TILE_SPLIT_1B
65228. DCP_GRPH_TILE_SPLIT_256B
65229. DCP_GRPH_TILE_SPLIT_2B
65230. DCP_GRPH_TILE_SPLIT_4B
65231. DCP_GRPH_TILE_SPLIT_512B
65232. DCP_GRPH_TILE_SPLIT_64B
65233. DCP_GRPH_UPDATE_LOCK
65234. DCP_GRPH_UPDATE_LOCK_FALSE
65235. DCP_GRPH_UPDATE_LOCK_TRUE
65236. DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN
65237. DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE
65238. DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE
65239. DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE
65240. DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE
65241. DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM
65242. DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK
65243. DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE
65244. DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE
65245. DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK
65246. DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE
65247. DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE
65248. DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK
65249. DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE
65250. DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE
65251. DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
65252. DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE
65253. DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE
65254. DCP_GRPH_XDMA_DRR_MODE_ENABLE
65255. DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE
65256. DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE
65257. DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK
65258. DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE
65259. DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE
65260. DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK
65261. DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE
65262. DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE
65263. DCP_GRPH_XDMA_FLIP_TYPE_CLEAR
65264. DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE
65265. DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE
65266. DCP_GRPH_XDMA_MULTIFLIP_ENABLE
65267. DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE
65268. DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE
65269. DCP_GRPH_XDMA_SUPER_AA_EN
65270. DCP_GRPH_XDMA_SUPER_AA_EN_FALSE
65271. DCP_GRPH_XDMA_SUPER_AA_EN_TRUE
65272. DCP_GSL0_EN
65273. DCP_GSL0_EN_FALSE
65274. DCP_GSL0_EN_TRUE
65275. DCP_GSL1_EN
65276. DCP_GSL1_EN_FALSE
65277. DCP_GSL1_EN_TRUE
65278. DCP_GSL2_EN
65279. DCP_GSL2_EN_FALSE
65280. DCP_GSL2_EN_TRUE
65281. DCP_GSL_CONTROL__DCP_GSL0_EN_MASK
65282. DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT
65283. DCP_GSL_CONTROL__DCP_GSL1_EN_MASK
65284. DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT
65285. DCP_GSL_CONTROL__DCP_GSL2_EN_MASK
65286. DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT
65287. DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK
65288. DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT
65289. DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK
65290. DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT
65291. DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK
65292. DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT
65293. DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK
65294. DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT
65295. DCP_GSL_CONTROL__DCP_GSL_MODE_MASK
65296. DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT
65297. DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK
65298. DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT
65299. DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK
65300. DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK
65301. DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT
65302. DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT
65303. DCP_GSL_DELAY_SURFACE_UPDATE_PENDING
65304. DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE
65305. DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE
65306. DCP_GSL_MASTER_EN
65307. DCP_GSL_MASTER_EN_FALSE
65308. DCP_GSL_MASTER_EN_TRUE
65309. DCP_GSL_SYNC_SOURCE
65310. DCP_GSL_SYNC_SOURCE_FLIP
65311. DCP_GSL_SYNC_SOURCE_PHASE0
65312. DCP_GSL_SYNC_SOURCE_PHASE1
65313. DCP_GSL_SYNC_SOURCE_RESET
65314. DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC
65315. DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS
65316. DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN
65317. DCP_GSL_XDMA_GROUP
65318. DCP_GSL_XDMA_GROUP_HSYNC0
65319. DCP_GSL_XDMA_GROUP_HSYNC1
65320. DCP_GSL_XDMA_GROUP_HSYNC2
65321. DCP_GSL_XDMA_GROUP_UNDERFLOW_EN
65322. DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE
65323. DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE
65324. DCP_GSL_XDMA_GROUP_VSYNC
65325. DCP_HIGHPASS_RANDOM_ENABLE
65326. DCP_HIGHPASS_RANDOM_ENABLE_FALSE
65327. DCP_HIGHPASS_RANDOM_ENABLE_TRUE
65328. DCP_INPUT_CSC_GRPH_MODE
65329. DCP_INPUT_CSC_GRPH_MODE_BYPASS
65330. DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF
65331. DCP_INPUT_CSC_GRPH_MODE_RESERVED
65332. DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF
65333. DCP_KEY_MODE
65334. DCP_KEY_MODE_ALPHA0
65335. DCP_KEY_MODE_ALPHA1
65336. DCP_KEY_MODE_IN_RANGE_ALPHA0
65337. DCP_KEY_MODE_IN_RANGE_ALPHA1
65338. DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK
65339. DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT
65340. DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK
65341. DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT
65342. DCP_MAXP_MASK
65343. DCP_MAX_CHANS
65344. DCP_OUTPUT_CSC_GRPH_MODE
65345. DCP_OUTPUT_CSC_GRPH_MODE_BYPASS
65346. DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF
65347. DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0
65348. DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1
65349. DCP_OUTPUT_CSC_GRPH_MODE_RGB
65350. DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF
65351. DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601
65352. DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709
65353. DCP_OUT_ROUND_TRUNC_MODE
65354. DCP_OUT_ROUND_TRUNC_MODE_ROUND_10
65355. DCP_OUT_ROUND_TRUNC_MODE_ROUND_11
65356. DCP_OUT_ROUND_TRUNC_MODE_ROUND_12
65357. DCP_OUT_ROUND_TRUNC_MODE_ROUND_13
65358. DCP_OUT_ROUND_TRUNC_MODE_ROUND_14
65359. DCP_OUT_ROUND_TRUNC_MODE_ROUND_8
65360. DCP_OUT_ROUND_TRUNC_MODE_ROUND_9
65361. DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED
65362. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10
65363. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11
65364. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12
65365. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13
65366. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14
65367. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8
65368. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9
65369. DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED
65370. DCP_OUT_TRUNC_ROUND_DEPTH_10BIT
65371. DCP_OUT_TRUNC_ROUND_DEPTH_11BIT
65372. DCP_OUT_TRUNC_ROUND_DEPTH_12BIT
65373. DCP_OUT_TRUNC_ROUND_DEPTH_13BIT
65374. DCP_OUT_TRUNC_ROUND_DEPTH_14BIT
65375. DCP_OUT_TRUNC_ROUND_DEPTH_8BIT
65376. DCP_OUT_TRUNC_ROUND_DEPTH_9BIT
65377. DCP_OUT_TRUNC_ROUND_MODE_ROUND
65378. DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE
65379. DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK
65380. DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT
65381. DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK
65382. DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT
65383. DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK
65384. DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT
65385. DCP_REG
65386. DCP_RGB_RANDOM_ENABLE
65387. DCP_RGB_RANDOM_ENABLE_FALSE
65388. DCP_RGB_RANDOM_ENABLE_TRUE
65389. DCP_SHA_PAY_SZ
65390. DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK
65391. DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT
65392. DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK
65393. DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT
65394. DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK
65395. DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT
65396. DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK
65397. DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT
65398. DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK
65399. DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT
65400. DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK
65401. DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT
65402. DCP_SPATIAL_DITHER_DEPTH
65403. DCP_SPATIAL_DITHER_DEPTH_24BPP
65404. DCP_SPATIAL_DITHER_DEPTH_30BPP
65405. DCP_SPATIAL_DITHER_DEPTH_36BPP
65406. DCP_SPATIAL_DITHER_DEPTH_UNDEFINED
65407. DCP_SPATIAL_DITHER_EN
65408. DCP_SPATIAL_DITHER_EN_FALSE
65409. DCP_SPATIAL_DITHER_EN_TRUE
65410. DCP_SPATIAL_DITHER_MODE
65411. DCP_SPATIAL_DITHER_MODE_AAAA
65412. DCP_SPATIAL_DITHER_MODE_AABBAABB
65413. DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC
65414. DCP_SPATIAL_DITHER_MODE_A_AA_A
65415. DCP_SPATIAL_DITHER_MODE_BYPASS
65416. DCP_SPATIAL_DITHER_MODE_INVALID
65417. DCP_SPATIAL_DITHER_MODE_RESERVED
65418. DCP_SPATIAL_DITHER_MODE_ROMA
65419. DCP_SPATIAL_DITHER_MODE_ROMB
65420. DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK
65421. DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT
65422. DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK
65423. DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT
65424. DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK
65425. DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT
65426. DCP_TEST_DEBUG_WRITE_EN
65427. DCP_TEST_DEBUG_WRITE_EN_FALSE
65428. DCP_TEST_DEBUG_WRITE_EN_TRUE
65429. DCP_TILING_CONFIG
65430. DCP_TYPE
65431. DCR
65432. DCR0
65433. DCR1
65434. DCR10
65435. DCR11
65436. DCR12
65437. DCR13
65438. DCR14
65439. DCR15
65440. DCR1_EPN_DIR0
65441. DCR1_EPN_DMACNT
65442. DCR1_EPN_REQEN
65443. DCR2
65444. DCR2_EPN_LMPKT
65445. DCR2_EPN_MPKT
65446. DCR3
65447. DCR4
65448. DCR5
65449. DCR6
65450. DCR7
65451. DCR8
65452. DCR9
65453. DCRC_EN
65454. DCRN_405_CPC0_CR0
65455. DCRN_405_CPC0_CR1
65456. DCRN_405_CPC0_PSR
65457. DCRN_AHBPLB4_EAR
65458. DCRN_AHBPLB4_ESR
65459. DCRN_CMU_ADDR
65460. DCRN_CMU_DATA
65461. DCRN_CONF_BASE
65462. DCRN_CONF_EIR_RS
65463. DCRN_CONF_FIR_RWC
65464. DCRN_CONF_RPERR0
65465. DCRN_CONF_RPERR1
65466. DCRN_CPC0_CR0
65467. DCRN_CPC0_CR1
65468. DCRN_CPC0_CUST0
65469. DCRN_CPC0_CUST1
65470. DCRN_CPC0_ER
65471. DCRN_CPC0_FR
65472. DCRN_CPC0_GPIO
65473. DCRN_CPC0_JTAGID
65474. DCRN_CPC0_MIRQ0
65475. DCRN_CPC0_MIRQ1
65476. DCRN_CPC0_PLB
65477. DCRN_CPC0_PLLMR
65478. DCRN_CPC0_PLLMR0
65479. DCRN_CPC0_PLLMR1
65480. DCRN_CPC0_SR
65481. DCRN_CPC0_STRP0
65482. DCRN_CPC0_STRP1
65483. DCRN_CPC0_STRP2
65484. DCRN_CPC0_STRP3
65485. DCRN_CPC0_SYS0
65486. DCRN_CPC0_SYS1
65487. DCRN_CPC0_UCR
65488. DCRN_CPR0_ADDR
65489. DCRN_CPR0_CFGADDR
65490. DCRN_CPR0_CFGDATA
65491. DCRN_CPR0_CLKUPD
65492. DCRN_CPR0_CONFIG_ADDR
65493. DCRN_CPR0_CONFIG_DATA
65494. DCRN_CPR0_DATA
65495. DCRN_CPR0_MALD
65496. DCRN_CPR0_OPBD
65497. DCRN_CPR0_PERD
65498. DCRN_CPR0_PLLC
65499. DCRN_CPR0_PLLD
65500. DCRN_CPR0_PRIMAD
65501. DCRN_CPR0_PRIMBD
65502. DCRN_CW_BASE
65503. DCRN_CW_LFIR
65504. DCRN_CW_LFIR_AND
65505. DCRN_CW_LFIR_MASK
65506. DCRN_CW_LFIR_MASK_AND
65507. DCRN_CW_LFIR_MASK_OR
65508. DCRN_CW_LFIR_OR
65509. DCRN_CW_MCER0
65510. DCRN_CW_MCER1
65511. DCRN_CW_MCER_ACTION0
65512. DCRN_CW_MCER_ACTION1
65513. DCRN_CW_MCER_AND0
65514. DCRN_CW_MCER_AND1
65515. DCRN_CW_MCER_MASK0
65516. DCRN_CW_MCER_MASK1
65517. DCRN_CW_MCER_MASK_AND0
65518. DCRN_CW_MCER_MASK_AND1
65519. DCRN_CW_MCER_MASK_OR0
65520. DCRN_CW_MCER_MASK_OR1
65521. DCRN_CW_MCER_OR0
65522. DCRN_CW_MCER_OR1
65523. DCRN_CW_MCER_WOF0
65524. DCRN_CW_MCER_WOF1
65525. DCRN_DDR34_BASE
65526. DCRN_DDR34_CFGR0
65527. DCRN_DDR34_CFGR1
65528. DCRN_DDR34_CFGR2
65529. DCRN_DDR34_CFGR3
65530. DCRN_DDR34_ECCERR_ADDR_PORT0
65531. DCRN_DDR34_ECCERR_ADDR_PORT1
65532. DCRN_DDR34_ECCERR_ADDR_PORT2
65533. DCRN_DDR34_ECCERR_ADDR_PORT3
65534. DCRN_DDR34_ECCERR_COUNT_PORT0
65535. DCRN_DDR34_ECCERR_COUNT_PORT1
65536. DCRN_DDR34_ECCERR_COUNT_PORT2
65537. DCRN_DDR34_ECCERR_COUNT_PORT3
65538. DCRN_DDR34_ECCERR_PORT0
65539. DCRN_DDR34_ECCERR_PORT1
65540. DCRN_DDR34_ECCERR_PORT2
65541. DCRN_DDR34_ECCERR_PORT3
65542. DCRN_DDR34_ECC_CHECK_PORT0
65543. DCRN_DDR34_ECC_CHECK_PORT1
65544. DCRN_DDR34_ECC_CHECK_PORT2
65545. DCRN_DDR34_ECC_CHECK_PORT3
65546. DCRN_DDR34_MCOPT1
65547. DCRN_DDR34_MCOPT2
65548. DCRN_DDR34_MCSTAT
65549. DCRN_DDR34_PHYSTAT
65550. DCRN_DDR34_SCRUB_CNTL
65551. DCRN_DDR34_SCRUB_END_ADDR
65552. DCRN_DDR34_SCRUB_INT
65553. DCRN_DDR34_SCRUB_START_ADDR
65554. DCRN_EBC0_CFGADDR
65555. DCRN_EBC0_CFGDATA
65556. DCRN_I2O0_IBAH
65557. DCRN_I2O0_IBAL
65558. DCRN_L2C0_ADDR
65559. DCRN_L2C0_CFG
65560. DCRN_L2C0_CMD
65561. DCRN_L2C0_DATA
65562. DCRN_L2C0_REVID
65563. DCRN_L2C0_SNP0
65564. DCRN_L2C0_SNP1
65565. DCRN_L2C0_SR
65566. DCRN_L2CDCRAI
65567. DCRN_L2CDCRDI
65568. DCRN_MAL0_CFG
65569. DCRN_MQ0_B0BAS
65570. DCRN_MQ0_B1BAS
65571. DCRN_MQ0_B2BAS
65572. DCRN_MQ0_B3BAS
65573. DCRN_MQ0_BAUH
65574. DCRN_MQ0_CF2H
65575. DCRN_MQ0_CFBHL
65576. DCRN_MQ0_XORBA
65577. DCRN_PLB4A0_ACR
65578. DCRN_PLB4AHB_BASE
65579. DCRN_PLB4AHB_ESR
65580. DCRN_PLB4AHB_SELAR
65581. DCRN_PLB4AHB_SEUAR
65582. DCRN_PLB4OPB0_BASE
65583. DCRN_PLB4OPB1_BASE
65584. DCRN_PLB4OPB2_BASE
65585. DCRN_PLB4OPB3_BASE
65586. DCRN_PLB4PLB6_BASE
65587. DCRN_PLB4PLB6_EARH
65588. DCRN_PLB4PLB6_EARL
65589. DCRN_PLB4PLB6_ESR
65590. DCRN_PLB4_P0ACR
65591. DCRN_PLB4_P0EARH
65592. DCRN_PLB4_P0EARL
65593. DCRN_PLB4_P0ESRH
65594. DCRN_PLB4_P0ESRHS
65595. DCRN_PLB4_P0ESRL
65596. DCRN_PLB4_P0ESRLS
65597. DCRN_PLB4_P1ACR
65598. DCRN_PLB4_P1EARH
65599. DCRN_PLB4_P1EARL
65600. DCRN_PLB4_P1ESRH
65601. DCRN_PLB4_P1ESRHS
65602. DCRN_PLB4_P1ESRL
65603. DCRN_PLB4_P1ESRLS
65604. DCRN_PLB4_PCBC
65605. DCRN_PLB4_PCBI
65606. DCRN_PLB6MCIF_BASE
65607. DCRN_PLB6MCIF_BEARH
65608. DCRN_PLB6MCIF_BEARL
65609. DCRN_PLB6MCIF_BESR0
65610. DCRN_PLB6MCIF_BESR1
65611. DCRN_PLB6PLB4_BASE
65612. DCRN_PLB6PLB4_EARH
65613. DCRN_PLB6PLB4_EARL
65614. DCRN_PLB6PLB4_ESR
65615. DCRN_PLB6_BASE
65616. DCRN_PLB6_CR0
65617. DCRN_PLB6_ERR
65618. DCRN_PLB6_HD
65619. DCRN_PLB6_SHD
65620. DCRN_SDR0_CONFIG_ADDR
65621. DCRN_SDR0_CONFIG_DATA
65622. DCRN_SDR0_SRST
65623. DCRN_SDR0_SRST_I2ODMA
65624. DCRN_SDR0_UART0
65625. DCRN_SDR0_UART1
65626. DCRN_SDR0_UART2
65627. DCRN_SDR0_UART3
65628. DCRN_SDRAM0_CFGADDR
65629. DCRN_SDRAM0_CFGDATA
65630. DCRN_SDR_ICINTSTAT
65631. DCRN_SRAM0_BEAR
65632. DCRN_SRAM0_BESR0
65633. DCRN_SRAM0_BESR1
65634. DCRN_SRAM0_CID
65635. DCRN_SRAM0_DPC
65636. DCRN_SRAM0_PMEG
65637. DCRN_SRAM0_REVID
65638. DCRN_SRAM0_SB0CR
65639. DCRN_SRAM0_SB1CR
65640. DCRN_SRAM0_SB2CR
65641. DCRN_SRAM0_SB3CR
65642. DCRO_PEGPL_460SX_OMR1MSKL_UOT
65643. DCRO_PEGPL_476FPE_OMR1MSKL_UOT
65644. DCRO_PEGPL_CFG
65645. DCRO_PEGPL_CFGBAH
65646. DCRO_PEGPL_CFGBAL
65647. DCRO_PEGPL_CFGMSK
65648. DCRO_PEGPL_EARH
65649. DCRO_PEGPL_EARL
65650. DCRO_PEGPL_EATR
65651. DCRO_PEGPL_ESR
65652. DCRO_PEGPL_MSGBAH
65653. DCRO_PEGPL_MSGBAL
65654. DCRO_PEGPL_MSGMSK
65655. DCRO_PEGPL_OMR1BAH
65656. DCRO_PEGPL_OMR1BAL
65657. DCRO_PEGPL_OMR1MSKH
65658. DCRO_PEGPL_OMR1MSKL
65659. DCRO_PEGPL_OMR1MSKL_UOT
65660. DCRO_PEGPL_OMR2BAH
65661. DCRO_PEGPL_OMR2BAL
65662. DCRO_PEGPL_OMR2MSKH
65663. DCRO_PEGPL_OMR2MSKL
65664. DCRO_PEGPL_OMR3BAH
65665. DCRO_PEGPL_OMR3BAL
65666. DCRO_PEGPL_OMR3MSKH
65667. DCRO_PEGPL_OMR3MSKL
65668. DCRO_PEGPL_OMR3MSKL_IO
65669. DCRO_PEGPL_OMRxMSKL_VAL
65670. DCRO_PEGPL_REGBAH
65671. DCRO_PEGPL_REGBAL
65672. DCRO_PEGPL_REGMSK
65673. DCRO_PEGPL_SPECIAL
65674. DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE_MASK
65675. DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE__SHIFT
65676. DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY_MASK
65677. DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY__SHIFT
65678. DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY_MASK
65679. DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY__SHIFT
65680. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE_MASK
65681. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE__SHIFT
65682. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE_MASK
65683. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE__SHIFT
65684. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE_MASK
65685. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE__SHIFT
65686. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE_MASK
65687. DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE__SHIFT
65688. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE_MASK
65689. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE__SHIFT
65690. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE_MASK
65691. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE__SHIFT
65692. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE_MASK
65693. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE__SHIFT
65694. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE_MASK
65695. DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE__SHIFT
65696. DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS_MASK
65697. DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS__SHIFT
65698. DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS_MASK
65699. DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS__SHIFT
65700. DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65701. DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65702. DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65703. DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65704. DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65705. DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65706. DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65707. DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65708. DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65709. DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65710. DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65711. DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65712. DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65713. DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65714. DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65715. DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65716. DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65717. DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65718. DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65719. DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65720. DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65721. DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65722. DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65723. DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65724. DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65725. DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65726. DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65727. DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65728. DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65729. DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65730. DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65731. DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65732. DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65733. DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65734. DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65735. DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65736. DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65737. DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65738. DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65739. DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65740. DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65741. DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65742. DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65743. DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65744. DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65745. DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65746. DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65747. DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65748. DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65749. DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65750. DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65751. DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65752. DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65753. DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65754. DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65755. DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65756. DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65757. DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65758. DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65759. DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65760. DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65761. DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65762. DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65763. DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65764. DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65765. DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65766. DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65767. DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65768. DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65769. DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65770. DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65771. DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65772. DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65773. DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65774. DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65775. DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65776. DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65777. DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65778. DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65779. DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65780. DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65781. DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65782. DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65783. DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65784. DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65785. DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65786. DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65787. DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65788. DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65789. DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65790. DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65791. DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65792. DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65793. DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65794. DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65795. DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65796. DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65797. DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65798. DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65799. DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65800. DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65801. DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65802. DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65803. DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65804. DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65805. DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65806. DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65807. DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65808. DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65809. DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65810. DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65811. DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65812. DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65813. DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65814. DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65815. DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65816. DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65817. DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65818. DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65819. DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65820. DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65821. DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65822. DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65823. DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65824. DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65825. DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65826. DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65827. DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65828. DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65829. DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65830. DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65831. DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65832. DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65833. DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65834. DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65835. DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65836. DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65837. DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65838. DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65839. DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65840. DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65841. DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65842. DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65843. DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65844. DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65845. DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65846. DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65847. DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65848. DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65849. DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65850. DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65851. DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65852. DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65853. DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65854. DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65855. DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65856. DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65857. DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65858. DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65859. DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65860. DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65861. DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65862. DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65863. DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65864. DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65865. DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65866. DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65867. DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65868. DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65869. DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65870. DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65871. DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65872. DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65873. DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65874. DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65875. DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65876. DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65877. DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65878. DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65879. DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65880. DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65881. DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65882. DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65883. DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65884. DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65885. DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65886. DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65887. DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65888. DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65889. DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65890. DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65891. DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65892. DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65893. DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65894. DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65895. DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65896. DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65897. DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65898. DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65899. DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65900. DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65901. DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65902. DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65903. DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65904. DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65905. DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65906. DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65907. DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65908. DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65909. DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65910. DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65911. DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65912. DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65913. DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65914. DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65915. DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65916. DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65917. DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65918. DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65919. DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65920. DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65921. DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65922. DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65923. DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65924. DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65925. DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65926. DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65927. DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65928. DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65929. DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65930. DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65931. DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65932. DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65933. DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65934. DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65935. DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65936. DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65937. DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65938. DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65939. DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65940. DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65941. DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65942. DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65943. DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65944. DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65945. DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65946. DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65947. DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65948. DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65949. DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65950. DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65951. DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65952. DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65953. DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65954. DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65955. DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65956. DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65957. DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65958. DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65959. DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65960. DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65961. DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65962. DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65963. DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65964. DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65965. DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65966. DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65967. DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65968. DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65969. DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65970. DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65971. DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65972. DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65973. DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65974. DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65975. DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65976. DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65977. DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65978. DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65979. DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65980. DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65981. DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65982. DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65983. DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65984. DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65985. DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65986. DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65987. DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65988. DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65989. DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65990. DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65991. DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65992. DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65993. DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65994. DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65995. DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65996. DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65997. DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
65998. DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
65999. DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66000. DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66001. DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66002. DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66003. DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66004. DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66005. DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66006. DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66007. DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66008. DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66009. DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66010. DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66011. DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66012. DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66013. DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66014. DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66015. DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66016. DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66017. DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66018. DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66019. DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66020. DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66021. DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66022. DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66023. DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66024. DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66025. DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66026. DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66027. DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66028. DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66029. DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66030. DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66031. DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66032. DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66033. DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66034. DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66035. DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66036. DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66037. DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66038. DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66039. DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66040. DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66041. DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66042. DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66043. DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66044. DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66045. DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66046. DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66047. DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66048. DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66049. DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66050. DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66051. DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66052. DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66053. DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66054. DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66055. DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66056. DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66057. DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66058. DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66059. DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66060. DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66061. DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66062. DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66063. DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66064. DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66065. DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66066. DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66067. DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66068. DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66069. DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66070. DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66071. DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66072. DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66073. DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66074. DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66075. DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66076. DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66077. DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66078. DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66079. DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66080. DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66081. DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66082. DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66083. DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66084. DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66085. DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66086. DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66087. DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66088. DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66089. DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66090. DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66091. DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66092. DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66093. DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66094. DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66095. DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66096. DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66097. DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66098. DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66099. DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66100. DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66101. DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66102. DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66103. DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66104. DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66105. DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66106. DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66107. DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66108. DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66109. DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66110. DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66111. DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66112. DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66113. DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66114. DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66115. DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66116. DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66117. DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66118. DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66119. DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66120. DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66121. DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66122. DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66123. DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66124. DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66125. DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66126. DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66127. DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66128. DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66129. DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66130. DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66131. DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66132. DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66133. DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66134. DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66135. DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66136. DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66137. DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66138. DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66139. DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66140. DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66141. DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66142. DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66143. DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66144. DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66145. DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66146. DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66147. DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66148. DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66149. DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66150. DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66151. DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66152. DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66153. DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66154. DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66155. DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66156. DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66157. DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66158. DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66159. DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66160. DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66161. DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66162. DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66163. DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66164. DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66165. DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66166. DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66167. DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66168. DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66169. DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66170. DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66171. DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66172. DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66173. DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66174. DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66175. DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66176. DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66177. DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66178. DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66179. DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66180. DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66181. DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66182. DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66183. DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66184. DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66185. DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66186. DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66187. DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66188. DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66189. DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66190. DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66191. DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66192. DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66193. DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66194. DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66195. DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66196. DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66197. DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66198. DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66199. DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66200. DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66201. DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66202. DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66203. DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66204. DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66205. DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66206. DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66207. DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66208. DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66209. DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66210. DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66211. DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66212. DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66213. DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66214. DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66215. DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66216. DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66217. DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66218. DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66219. DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66220. DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66221. DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66222. DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66223. DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66224. DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66225. DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66226. DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66227. DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66228. DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66229. DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66230. DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66231. DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66232. DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66233. DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66234. DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66235. DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66236. DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66237. DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66238. DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66239. DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66240. DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66241. DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66242. DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66243. DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66244. DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66245. DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66246. DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66247. DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66248. DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66249. DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66250. DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66251. DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66252. DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66253. DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66254. DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66255. DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66256. DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66257. DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66258. DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66259. DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66260. DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66261. DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66262. DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66263. DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66264. DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66265. DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66266. DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66267. DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66268. DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66269. DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66270. DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66271. DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66272. DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66273. DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66274. DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66275. DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66276. DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66277. DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66278. DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66279. DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66280. DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66281. DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66282. DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66283. DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66284. DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66285. DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66286. DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66287. DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66288. DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66289. DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66290. DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66291. DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66292. DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66293. DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66294. DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66295. DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66296. DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66297. DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66298. DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66299. DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66300. DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66301. DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66302. DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66303. DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66304. DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66305. DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66306. DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66307. DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66308. DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66309. DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66310. DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66311. DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66312. DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66313. DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66314. DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66315. DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66316. DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66317. DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66318. DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66319. DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66320. DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66321. DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66322. DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66323. DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66324. DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66325. DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66326. DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66327. DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66328. DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66329. DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66330. DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66331. DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66332. DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66333. DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66334. DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66335. DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66336. DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66337. DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66338. DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66339. DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66340. DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66341. DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66342. DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66343. DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66344. DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66345. DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66346. DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66347. DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66348. DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66349. DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66350. DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66351. DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66352. DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66353. DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66354. DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66355. DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66356. DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66357. DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66358. DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66359. DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66360. DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66361. DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66362. DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66363. DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66364. DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66365. DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66366. DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66367. DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66368. DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66369. DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66370. DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66371. DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66372. DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66373. DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66374. DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66375. DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66376. DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66377. DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66378. DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66379. DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66380. DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66381. DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66382. DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66383. DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66384. DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66385. DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66386. DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66387. DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66388. DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66389. DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66390. DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66391. DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66392. DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66393. DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66394. DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66395. DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66396. DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66397. DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66398. DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66399. DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66400. DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66401. DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66402. DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66403. DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66404. DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66405. DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66406. DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66407. DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66408. DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66409. DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66410. DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66411. DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66412. DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66413. DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66414. DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66415. DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66416. DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66417. DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66418. DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66419. DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66420. DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66421. DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66422. DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66423. DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66424. DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66425. DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66426. DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66427. DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66428. DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66429. DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66430. DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66431. DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66432. DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66433. DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66434. DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66435. DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66436. DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66437. DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66438. DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66439. DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66440. DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66441. DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66442. DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66443. DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66444. DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66445. DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66446. DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66447. DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66448. DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66449. DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66450. DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66451. DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66452. DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66453. DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66454. DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66455. DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66456. DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66457. DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66458. DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK
66459. DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT
66460. DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET_MASK
66461. DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET__SHIFT
66462. DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET_MASK
66463. DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET__SHIFT
66464. DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET_MASK
66465. DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET__SHIFT
66466. DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET_MASK
66467. DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET__SHIFT
66468. DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET_MASK
66469. DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET__SHIFT
66470. DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET_MASK
66471. DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET__SHIFT
66472. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET_MASK
66473. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET__SHIFT
66474. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET_MASK
66475. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET__SHIFT
66476. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET_MASK
66477. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET__SHIFT
66478. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET_MASK
66479. DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET__SHIFT
66480. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV_MASK
66481. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV__SHIFT
66482. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL_MASK
66483. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL__SHIFT
66484. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV_MASK
66485. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV__SHIFT
66486. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL_MASK
66487. DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL__SHIFT
66488. DCR_ABORT
66489. DCR_ACCESS_PROLOG
66490. DCR_AUTOFD
66491. DCR_BLK_SIZE
66492. DCR_BPE
66493. DCR_CLEAR_EOF
66494. DCR_DATA_EN
66495. DCR_DATA_FIFO_RESET
66496. DCR_DATA_THRES
66497. DCR_DATA_WRITE
66498. DCR_DEN
66499. DCR_DIR
66500. DCR_DMA_EN
66501. DCR_DPE
66502. DCR_DRST
66503. DCR_FCT_CLR
66504. DCR_FSHL
66505. DCR_FSIZE_MASK
66506. DCR_HOST_INVALID
66507. DCR_HOST_MMIO
66508. DCR_HOST_NATIVE
66509. DCR_IFPOE
66510. DCR_INIT_VAL
66511. DCR_IPE
66512. DCR_IRQ
66513. DCR_KSSL
66514. DCR_MAP_OK
66515. DCR_MCE
66516. DCR_MCHL
66517. DCR_MCSL
66518. DCR_MS
66519. DCR_NORMAL
66520. DCR_OBS
66521. DCR_P2V
66522. DCR_RPE
66523. DCR_RX
66524. DCR_RXDONE
66525. DCR_RXRESET
66526. DCR_SELECT
66527. DCR_SI
66528. DCR_SIZE
66529. DCR_STROBE
66530. DCR_SW_ABT
66531. DCR_TCE
66532. DCR_TCHL
66533. DCR_TCSL
66534. DCR_TDCHL
66535. DCR_TDCSL
66536. DCR_TX
66537. DCR_TXDONE
66538. DCR_TXRESET
66539. DCR_TYPE_AP
66540. DCR_TYPE_MU_BSS
66541. DCR_TYPE_MU_ESS
66542. DCR_TYPE_MU_IBSS
66543. DCR_TYPE_MU_PIBSS
66544. DCR_TYPE_SNIFFER
66545. DCR_TYPE_WLAP
66546. DCR_V2P
66547. DCR_VAL
66548. DCR_nINIT
66549. DCR_writew
66550. DCSAR
66551. DCSB0
66552. DCSB1
66553. DCSB_CS_ENABLE
66554. DCSM0
66555. DCSM1
66556. DCSR
66557. DCSR_BIU
66558. DCSR_BUSERR
66559. DCSR_CLRCMPST
66560. DCSR_CMPST
66561. DCSR_DONEA
66562. DCSR_DONEB
66563. DCSR_ENDINTR
66564. DCSR_EORINTR
66565. DCSR_EORIRQEN
66566. DCSR_EORJMPEN
66567. DCSR_EORSTOPEN
66568. DCSR_ERROR
66569. DCSR_IE
66570. DCSR_NODESC
66571. DCSR_REQPEND
66572. DCSR_RUN
66573. DCSR_SETCMPST
66574. DCSR_STARTINTR
66575. DCSR_STOPIRQEN
66576. DCSR_STOPSTATE
66577. DCSR_STRTA
66578. DCSR_STRTB
66579. DCSSBLK_MINORS_PER_DISK
66580. DCSSBLK_NAME
66581. DCSSBLK_PARM_LEN
66582. DCSS_BUS_ID_SIZE
66583. DCSS_FINDSEGA
66584. DCSS_FINDSEGX
66585. DCSS_LOADNSRX
66586. DCSS_LOADSHRX
66587. DCSS_PURGESEG
66588. DCSS_SEGEXTX
66589. DCST_DEBUG_PORT
66590. DCSUB
66591. DCS_BLOCK_DEV_SCAN
66592. DCS_BRIGHTNESS
66593. DCS_CFG_R
66594. DCS_CHANNEL_NUMBER_POS
66595. DCS_CTRL_DISPLAY
66596. DCS_DEV_ADD
66597. DCS_DEV_RMV
66598. DCS_DISC_DONE
66599. DCS_ENABLE
66600. DCS_GET_ID1
66601. DCS_GET_ID2
66602. DCS_GET_ID3
66603. DCS_LW_TX_LP
66604. DCS_PART_INFO
66605. DCS_PIXEL_FORMAT_12BPP
66606. DCS_PIXEL_FORMAT_12bpp
66607. DCS_PIXEL_FORMAT_16BPP
66608. DCS_PIXEL_FORMAT_16bpp
66609. DCS_PIXEL_FORMAT_18BPP
66610. DCS_PIXEL_FORMAT_18bpp
66611. DCS_PIXEL_FORMAT_24BPP
66612. DCS_PIXEL_FORMAT_24bpp
66613. DCS_PIXEL_FORMAT_3BPP
66614. DCS_PIXEL_FORMAT_3bpp
66615. DCS_PIXEL_FORMAT_8BPP
66616. DCS_PIXEL_FORMAT_8bpp
66617. DCS_POWER_MODE_DISPLAY
66618. DCS_POWER_MODE_DISPLAY_NORMAL_MODE
66619. DCS_POWER_MODE_IDLE_MODE
66620. DCS_POWER_MODE_PARTIAL_MODE
66621. DCS_POWER_MODE_RESERVED_MASK
66622. DCS_POWER_MODE_SLEEP_MODE
66623. DCS_PT_DEV_ADDR
66624. DCS_PT_DEV_INFO
66625. DCS_RAID_GRP_INFO
66626. DCS_READ_NUM_ERRORS
66627. DCS_SR_0P_TX_LP
66628. DCS_SW_0P_TX_LP
66629. DCS_SW_1P_TX_LP
66630. DCTCP_MAX_ALPHA
66631. DCTL
66632. DCTL_CGNPINNAK
66633. DCTL_CGOUTNAK
66634. DCTL_GNPINNAKSTS
66635. DCTL_GOUTNAKSTS
66636. DCTL_PWRONPRGDONE
66637. DCTL_RMTWKUPSIG
66638. DCTL_SERVICE_INTERVAL_SUPPORTED
66639. DCTL_SFTDISCON
66640. DCTL_SGNPINNAK
66641. DCTL_SGOUTNAK
66642. DCTL_TSTCTL_MASK
66643. DCTL_TSTCTL_SHIFT
66644. DCTL_data
66645. DCT_ANTENNA_A
66646. DCT_ANTENNA_B
66647. DCT_CFG_SEL
66648. DCT_FLAG_ABORT_MGMT
66649. DCT_FLAG_ACK_REQD
66650. DCT_FLAG_CTS_REQUIRED
66651. DCT_FLAG_DUR_SET
66652. DCT_FLAG_EXT_HC_NO_SIFS_PIFS
66653. DCT_FLAG_EXT_HC_PIFS
66654. DCT_FLAG_EXT_HC_SIFS
66655. DCT_FLAG_EXT_MODE_CCK
66656. DCT_FLAG_EXT_MODE_OFDM
66657. DCT_FLAG_EXT_QOS_ENABLED
66658. DCT_FLAG_EXT_SECURITY_CCM
66659. DCT_FLAG_EXT_SECURITY_CKIP
66660. DCT_FLAG_EXT_SECURITY_MASK
66661. DCT_FLAG_EXT_SECURITY_NO
66662. DCT_FLAG_EXT_SECURITY_TKIP
66663. DCT_FLAG_EXT_SECURITY_WEP
66664. DCT_FLAG_LONG_PREAMBLE
66665. DCT_FLAG_NO_WEP
66666. DCT_FLAG_RTS_REQD
66667. DCT_FLAG_SHORT_PREAMBLE
66668. DCT_FLAG_TSF_REQD
66669. DCT_SEL_HI
66670. DCT_SEL_LO
66671. DCT_WEP_INDEX_USE_IMMEDIATE
66672. DCT_WEP_KEY_128Bit
66673. DCT_WEP_KEY_128bitIV
66674. DCT_WEP_KEY_64Bit
66675. DCT_WEP_KEY_FIELD_LENGTH
66676. DCT_WEP_KEY_INDEX_MASK
66677. DCT_WEP_KEY_NOT_IMMIDIATE
66678. DCT_WEP_KEY_SIZE_MASK
66679. DCU10_PRODUCT_ID
66680. DCU10_VENDOR_ID
66681. DCUNIT_CLOCK_GATE_DISABLE
66682. DCU_BGND
66683. DCU_BGND_B
66684. DCU_BGND_G
66685. DCU_BGND_R
66686. DCU_CP
66687. DCU_CTRLDESCLN
66688. DCU_CV
66689. DCU_DC
66690. DCU_DCFB_MAX
66691. DCU_DCU_MODE
66692. DCU_DISP_SIZE
66693. DCU_DISP_SIZE_DELTA_X
66694. DCU_DISP_SIZE_DELTA_Y
66695. DCU_DIV_RATIO
66696. DCU_DM
66697. DCU_HPE
66698. DCU_HSYN_PARA
66699. DCU_HSYN_PARA_BP
66700. DCU_HSYN_PARA_FP
66701. DCU_HSYN_PARA_PW
66702. DCU_IC
66703. DCU_IM
66704. DCU_INT_MASK
66705. DCU_INT_MASK_CRCOVERFLOW
66706. DCU_INT_MASK_CRCREADY
66707. DCU_INT_MASK_DMATRANS
66708. DCU_INT_MASK_IPMERROR
66709. DCU_INT_MASK_LSBFVS
66710. DCU_INT_MASK_LYRTRANS
66711. DCU_INT_MASK_P1EMPTY
66712. DCU_INT_MASK_P1FIFOHI
66713. DCU_INT_MASK_P1FIFOLO
66714. DCU_INT_MASK_P2EMPTY
66715. DCU_INT_MASK_P2FIFOHI
66716. DCU_INT_MASK_P2FIFOLO
66717. DCU_INT_MASK_P3EMPTY
66718. DCU_INT_MASK_P3FIFOHI
66719. DCU_INT_MASK_P3FIFOLO
66720. DCU_INT_MASK_P4EMPTY
66721. DCU_INT_MASK_P4FIFOHI
66722. DCU_INT_MASK_P4FIFOLO
66723. DCU_INT_MASK_PROGEND
66724. DCU_INT_MASK_UNDRUN
66725. DCU_INT_MASK_VBLANK
66726. DCU_INT_MASK_VSYNC
66727. DCU_INT_STATUS
66728. DCU_INT_STATUS_CRCOVERFLOW
66729. DCU_INT_STATUS_CRCREADY
66730. DCU_INT_STATUS_DMATRANS
66731. DCU_INT_STATUS_IPMERROR
66732. DCU_INT_STATUS_LSBFVS
66733. DCU_INT_STATUS_LYRTRANS
66734. DCU_INT_STATUS_P1EMPTY
66735. DCU_INT_STATUS_P1FIFOHI
66736. DCU_INT_STATUS_P1FIFOLO
66737. DCU_INT_STATUS_P2EMPTY
66738. DCU_INT_STATUS_P2FIFOHI
66739. DCU_INT_STATUS_P2FIFOLO
66740. DCU_INT_STATUS_P3EMPTY
66741. DCU_INT_STATUS_P3FIFOHI
66742. DCU_INT_STATUS_P3FIFOLO
66743. DCU_INT_STATUS_P4EMPTY
66744. DCU_INT_STATUS_P4FIFOHI
66745. DCU_INT_STATUS_P4FIFOLO
66746. DCU_INT_STATUS_PROGEND
66747. DCU_INT_STATUS_UNDRUN
66748. DCU_INT_STATUS_VBLANK
66749. DCU_INT_STATUS_VSYNC
66750. DCU_LAYER_AB_CHROMA_KEYING
66751. DCU_LAYER_AB_NONE
66752. DCU_LAYER_AB_WHOLE_FRAME
66753. DCU_LAYER_BB_ON
66754. DCU_LAYER_BG_BCOLOR
66755. DCU_LAYER_BPP
66756. DCU_LAYER_CKMAX_B
66757. DCU_LAYER_CKMAX_G
66758. DCU_LAYER_CKMAX_R
66759. DCU_LAYER_CKMIN_B
66760. DCU_LAYER_CKMIN_G
66761. DCU_LAYER_CKMIN_R
66762. DCU_LAYER_DATA_SEL_CLUT
66763. DCU_LAYER_EN
66764. DCU_LAYER_FG_FCOLOR
66765. DCU_LAYER_HEIGHT
66766. DCU_LAYER_LUOFFS
66767. DCU_LAYER_POST_SKIP
66768. DCU_LAYER_POSX
66769. DCU_LAYER_POSY
66770. DCU_LAYER_PRE_SKIP
66771. DCU_LAYER_RLE_EN
66772. DCU_LAYER_SAFETY_EN
66773. DCU_LAYER_TILE_EN
66774. DCU_LAYER_TILE_HOR
66775. DCU_LAYER_TILE_VER
66776. DCU_LAYER_TRANS
66777. DCU_LAYER_WIDTH
66778. DCU_ME
66779. DCU_MODE_BLEND_ITER
66780. DCU_MODE_COLORBAR
66781. DCU_MODE_DCU_MODE
66782. DCU_MODE_DCU_MODE_MASK
66783. DCU_MODE_NORMAL
66784. DCU_MODE_OFF
66785. DCU_MODE_RASTER_EN
66786. DCU_MODE_TEST
66787. DCU_PE
66788. DCU_PM
66789. DCU_PR
66790. DCU_PW
66791. DCU_RE
66792. DCU_SL
66793. DCU_SPE
66794. DCU_SYN_POL
66795. DCU_SYN_POL_INV_HS_LOW
66796. DCU_SYN_POL_INV_PXCK
66797. DCU_SYN_POL_INV_VS_LOW
66798. DCU_SYN_POL_NEG
66799. DCU_THRESHOLD
66800. DCU_THRESHOLD_LS_BF_VS
66801. DCU_THRESHOLD_OUT_BUF_HIGH
66802. DCU_THRESHOLD_OUT_BUF_LOW
66803. DCU_UPDATE_MODE
66804. DCU_UPDATE_MODE_MODE
66805. DCU_UPDATE_MODE_READREG
66806. DCU_VM
66807. DCU_VR
66808. DCU_VSYN_PARA
66809. DCU_VSYN_PARA_BP
66810. DCU_VSYN_PARA_FP
66811. DCU_VSYN_PARA_PW
66812. DCU_VW
66813. DCU_WE
66814. DCWR_COPY
66815. DCWR_WRITE
66816. DCW_CCM_KEY128Bit_SIZE
66817. DCW_CMD_CONTROL
66818. DCW_CMD_INTRG
66819. DCW_CMD_READ
66820. DCW_CMD_SENSE
66821. DCW_CMD_SENSE_ID
66822. DCW_CMD_WRITE
66823. DCW_FLAGS_CC
66824. DCW_INTRG_FLAGS_CRIT
66825. DCW_INTRG_FLAGS_MPM
66826. DCW_INTRG_FLAGS_PPR
66827. DCW_INTRG_FORMAT_DEFAULT
66828. DCW_INTRG_RCQ_PRIMARY
66829. DCW_INTRG_RCQ_SECONDARY
66830. DCW_INTRG_RCQ_UNSPECIFIED
66831. DCW_INTRG_RC_TIMEOUT
66832. DCW_INTRG_RC_UNSPECIFIED
66833. DCW_WEP_KEY128Bit_SIZE
66834. DCW_WEP_KEY64Bit_SIZE
66835. DCW_WEP_KEY_INDEX_MASK
66836. DCW_WEP_KEY_INVALID_SIZE
66837. DCW_WEP_KEY_SEC_TYPE_CCM
66838. DCW_WEP_KEY_SEC_TYPE_MASK
66839. DCW_WEP_KEY_SEC_TYPE_TKIP
66840. DCW_WEP_KEY_SEC_TYPE_WEP
66841. DCYSUSM
66842. DCYSUSM_DECAYTIME_MASK
66843. DCYSUSM_PHASE1_MASK
66844. DCYSUSM_SUSTAINLEVEL_MASK
66845. DCYSUSV
66846. DCYSUSV_CHANNELENABLE_MASK
66847. DCYSUSV_DECAYTIME_MASK
66848. DCYSUSV_PHASE1_MASK
66849. DCYSUSV_SUSTAINLEVEL_MASK
66850. DC_25PT
66851. DC_37PT
66852. DC_38PT
66853. DC_50PT
66854. DC_62PT
66855. DC_64PT
66856. DC_75PT
66857. DC_8051_CSRS
66858. DC_87PT
66859. DC_88PT
66860. DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK
66861. DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT
66862. DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK
66863. DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT
66864. DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK
66865. DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT
66866. DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK
66867. DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT
66868. DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK
66869. DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT
66870. DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK
66871. DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT
66872. DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK
66873. DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT
66874. DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK
66875. DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT
66876. DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK
66877. DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT
66878. DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK
66879. DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT
66880. DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK
66881. DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT
66882. DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK
66883. DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT
66884. DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK
66885. DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT
66886. DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK
66887. DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT
66888. DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK
66889. DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT
66890. DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK
66891. DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT
66892. DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK
66893. DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT
66894. DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK
66895. DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT
66896. DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK
66897. DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT
66898. DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK
66899. DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT
66900. DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK
66901. DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT
66902. DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK
66903. DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT
66904. DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK
66905. DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT
66906. DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK
66907. DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT
66908. DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK
66909. DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT
66910. DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK
66911. DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT
66912. DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK
66913. DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT
66914. DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK
66915. DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT
66916. DC_ABM1_CNTL__ABM1_EN_MASK
66917. DC_ABM1_CNTL__ABM1_EN__SHIFT
66918. DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK
66919. DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT
66920. DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK
66921. DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT
66922. DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK
66923. DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT
66924. DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK
66925. DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT
66926. DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK
66927. DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT
66928. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK
66929. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT
66930. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK
66931. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT
66932. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK
66933. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT
66934. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK
66935. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT
66936. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK
66937. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT
66938. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK
66939. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT
66940. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK
66941. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT
66942. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK
66943. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT
66944. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK
66945. DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT
66946. DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK
66947. DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT
66948. DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK
66949. DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT
66950. DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK
66951. DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT
66952. DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK
66953. DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT
66954. DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK
66955. DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT
66956. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK
66957. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT
66958. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK
66959. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT
66960. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK
66961. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT
66962. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK
66963. DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT
66964. DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK
66965. DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT
66966. DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK
66967. DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT
66968. DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK
66969. DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT
66970. DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK
66971. DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT
66972. DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK
66973. DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT
66974. DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK
66975. DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT
66976. DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK
66977. DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT
66978. DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK
66979. DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT
66980. DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK
66981. DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT
66982. DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK
66983. DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT
66984. DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK
66985. DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT
66986. DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK
66987. DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT
66988. DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK
66989. DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT
66990. DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK
66991. DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT
66992. DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK
66993. DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT
66994. DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK
66995. DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT
66996. DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK
66997. DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT
66998. DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK
66999. DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT
67000. DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK
67001. DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT
67002. DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK
67003. DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT
67004. DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK
67005. DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT
67006. DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK
67007. DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT
67008. DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK
67009. DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT
67010. DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK
67011. DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT
67012. DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK
67013. DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT
67014. DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK
67015. DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT
67016. DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK
67017. DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT
67018. DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK
67019. DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT
67020. DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK
67021. DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT
67022. DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK
67023. DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT
67024. DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK
67025. DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT
67026. DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
67027. DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
67028. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
67029. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
67030. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
67031. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
67032. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK
67033. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT
67034. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK
67035. DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT
67036. DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK
67037. DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT
67038. DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK
67039. DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT
67040. DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK
67041. DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT
67042. DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK
67043. DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT
67044. DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK
67045. DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT
67046. DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK
67047. DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT
67048. DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK
67049. DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT
67050. DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK
67051. DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT
67052. DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK
67053. DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT
67054. DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK
67055. DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT
67056. DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK
67057. DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT
67058. DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK
67059. DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT
67060. DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK
67061. DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT
67062. DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK
67063. DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT
67064. DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK
67065. DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT
67066. DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK
67067. DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT
67068. DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
67069. DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
67070. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
67071. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
67072. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
67073. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
67074. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK
67075. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT
67076. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK
67077. DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT
67078. DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK
67079. DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT
67080. DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK
67081. DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT
67082. DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK
67083. DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT
67084. DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK
67085. DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT
67086. DC_ACPI_CM_POWER_STATE_D0
67087. DC_ACPI_CM_POWER_STATE_D1
67088. DC_ACPI_CM_POWER_STATE_D2
67089. DC_ACPI_CM_POWER_STATE_D3
67090. DC_ADDRESS
67091. DC_ADDR_SURF_MICRO_TILING_DISPLAY
67092. DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY
67093. DC_ARB_CFG
67094. DC_ARRAY_1D_TILED_THICK
67095. DC_ARRAY_1D_TILED_THIN1
67096. DC_ARRAY_2D_TILED_THICK
67097. DC_ARRAY_2D_TILED_THIN1
67098. DC_ARRAY_2D_TILED_X_THICK
67099. DC_ARRAY_3D_TILED_THICK
67100. DC_ARRAY_3D_TILED_THIN1
67101. DC_ARRAY_3D_TILED_X_THICK
67102. DC_ARRAY_LINEAR_ALLIGNED
67103. DC_ARRAY_LINEAR_GENERAL
67104. DC_ARRAY_PRT_2D_TILED_THICK
67105. DC_ARRAY_PRT_2D_TILED_THIN1
67106. DC_ARRAY_PRT_3D_TILED_THICK
67107. DC_ARRAY_PRT_3D_TILED_THIN1
67108. DC_ARRAY_PRT_TILED_THICK
67109. DC_ARRAY_PRT_TILED_THIN1
67110. DC_BALANCE_RESET
67111. DC_BALANCE_RESET_VLV
67112. DC_BIOS_TYPES_H
67113. DC_BORDER_COLOR
67114. DC_BUFLEN
67115. DC_BUFSTAT
67116. DC_BUF_SIZE
67117. DC_CAC_VALUE
67118. DC_CAL
67119. DC_CANCELLED_DELAY
67120. DC_CB_ST_OFFSET
67121. DC_CDBGMOD_ACK
67122. DC_CDBGMOD_ACK_1NAK
67123. DC_CDBGMOD_ACK_NAK
67124. DC_CFIFO_DIAG
67125. DC_CFWT
67126. DC_CHIPID
67127. DC_CLBUF
67128. DC_CLES
67129. DC_CLKAON
67130. DC_CLOCK_TYPE_DISPCLK
67131. DC_CLOCK_TYPE_DPPCLK
67132. DC_CLR_KEY
67133. DC_CLR_KEY_CLR_KEY_EN
67134. DC_CLR_KEY_MASK
67135. DC_CLR_KEY_X
67136. DC_CLR_KEY_Y
67137. DC_CMD_CONT_SYNCPT_VSYNC
67138. DC_CMD_DISPLAY_COMMAND
67139. DC_CMD_DISPLAY_COMMAND_OPTION0
67140. DC_CMD_DISPLAY_POWER_CONTROL
67141. DC_CMD_DISPLAY_WINDOW_HEADER
67142. DC_CMD_GENERAL_INCR_SYNCPT
67143. DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
67144. DC_CMD_GENERAL_INCR_SYNCPT_ERROR
67145. DC_CMD_IHUB_COMMON_MISC_CTL
67146. DC_CMD_INT_ENABLE
67147. DC_CMD_INT_MASK
67148. DC_CMD_INT_POLARITY
67149. DC_CMD_INT_STATUS
67150. DC_CMD_INT_TYPE
67151. DC_CMD_REG_ACT_CONTROL
67152. DC_CMD_SIGNAL_RAISE
67153. DC_CMD_SIGNAL_RAISE1
67154. DC_CMD_SIGNAL_RAISE2
67155. DC_CMD_SIGNAL_RAISE3
67156. DC_CMD_STATE_ACCESS
67157. DC_CMD_STATE_CONTROL
67158. DC_CMD_WIN_A_INCR_SYNCPT
67159. DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
67160. DC_CMD_WIN_A_INCR_SYNCPT_ERROR
67161. DC_CMD_WIN_B_INCR_SYNCPT
67162. DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
67163. DC_CMD_WIN_B_INCR_SYNCPT_ERROR
67164. DC_CMD_WIN_C_INCR_SYNCPT
67165. DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
67166. DC_CMD_WIN_C_INCR_SYNCPT_ERROR
67167. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1_MASK
67168. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1__SHIFT
67169. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2_MASK
67170. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2__SHIFT
67171. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3_MASK
67172. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3__SHIFT
67173. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4_MASK
67174. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4__SHIFT
67175. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5_MASK
67176. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5__SHIFT
67177. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6_MASK
67178. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6__SHIFT
67179. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7_MASK
67180. DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7__SHIFT
67181. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67182. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67183. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl_MASK
67184. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67185. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val_MASK
67186. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67187. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67188. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67189. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67190. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67191. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare_MASK
67192. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare__SHIFT
67193. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0_MASK
67194. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67195. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1_MASK
67196. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67197. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2_MASK
67198. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67199. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3_MASK
67200. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67201. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid_MASK
67202. DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid__SHIFT
67203. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare_MASK
67204. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare__SHIFT
67205. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67206. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67207. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated_MASK
67208. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67209. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid_MASK
67210. DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid__SHIFT
67211. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_bbweight_MASK
67212. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_bbweight__SHIFT
67213. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_byp_init_val_MASK
67214. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_byp_init_val__SHIFT
67215. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK
67216. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT
67217. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK
67218. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT
67219. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_dac_safeval_sel_MASK
67220. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT
67221. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_freq_lock_timer_MASK
67222. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT
67223. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_icostart_sel_MASK
67224. DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_icostart_sel__SHIFT
67225. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67226. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67227. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare_MASK
67228. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare__SHIFT
67229. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated_MASK
67230. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67231. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid_MASK
67232. DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid__SHIFT
67233. DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay_MASK
67234. DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67235. DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask_MASK
67236. DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67237. DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en_MASK
67238. DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67239. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67240. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67241. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67242. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67243. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67244. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67245. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67246. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67247. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67248. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67249. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67250. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67251. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67252. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67253. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67254. DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67255. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67256. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67257. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67258. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67259. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67260. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67261. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67262. DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67263. DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare_MASK
67264. DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare__SHIFT
67265. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis_MASK
67266. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis__SHIFT
67267. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en_MASK
67268. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67269. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67270. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67271. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67272. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67273. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67274. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67275. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67276. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67277. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67278. DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67279. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK
67280. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT
67281. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67282. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67283. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67284. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67285. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67286. DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67287. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1_MASK
67288. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1__SHIFT
67289. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2_MASK
67290. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2__SHIFT
67291. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3_MASK
67292. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3__SHIFT
67293. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4_MASK
67294. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4__SHIFT
67295. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5_MASK
67296. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5__SHIFT
67297. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6_MASK
67298. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6__SHIFT
67299. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7_MASK
67300. DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7__SHIFT
67301. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67302. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67303. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl_MASK
67304. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67305. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val_MASK
67306. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67307. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67308. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67309. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67310. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67311. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare_MASK
67312. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare__SHIFT
67313. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0_MASK
67314. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67315. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1_MASK
67316. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67317. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2_MASK
67318. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67319. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3_MASK
67320. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67321. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid_MASK
67322. DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid__SHIFT
67323. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare_MASK
67324. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare__SHIFT
67325. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67326. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67327. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated_MASK
67328. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67329. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid_MASK
67330. DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid__SHIFT
67331. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_bbweight_MASK
67332. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_bbweight__SHIFT
67333. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_byp_init_val_MASK
67334. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_byp_init_val__SHIFT
67335. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK
67336. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT
67337. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK
67338. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT
67339. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_dac_safeval_sel_MASK
67340. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT
67341. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_freq_lock_timer_MASK
67342. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT
67343. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_icostart_sel_MASK
67344. DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_icostart_sel__SHIFT
67345. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67346. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67347. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare_MASK
67348. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare__SHIFT
67349. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated_MASK
67350. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67351. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid_MASK
67352. DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid__SHIFT
67353. DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay_MASK
67354. DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67355. DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask_MASK
67356. DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67357. DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en_MASK
67358. DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67359. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67360. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67361. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67362. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67363. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67364. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67365. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67366. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67367. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67368. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67369. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67370. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67371. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67372. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67373. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67374. DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67375. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67376. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67377. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67378. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67379. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67380. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67381. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67382. DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67383. DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare_MASK
67384. DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare__SHIFT
67385. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis_MASK
67386. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis__SHIFT
67387. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en_MASK
67388. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67389. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67390. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67391. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67392. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67393. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67394. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67395. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67396. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67397. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67398. DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67399. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK
67400. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT
67401. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67402. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67403. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67404. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67405. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67406. DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67407. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1_MASK
67408. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1__SHIFT
67409. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2_MASK
67410. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2__SHIFT
67411. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3_MASK
67412. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3__SHIFT
67413. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4_MASK
67414. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4__SHIFT
67415. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5_MASK
67416. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5__SHIFT
67417. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6_MASK
67418. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6__SHIFT
67419. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7_MASK
67420. DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7__SHIFT
67421. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67422. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67423. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl_MASK
67424. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67425. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val_MASK
67426. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67427. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67428. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67429. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67430. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67431. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare_MASK
67432. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare__SHIFT
67433. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0_MASK
67434. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67435. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1_MASK
67436. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67437. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2_MASK
67438. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67439. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3_MASK
67440. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67441. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid_MASK
67442. DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid__SHIFT
67443. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare_MASK
67444. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare__SHIFT
67445. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67446. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67447. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated_MASK
67448. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67449. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid_MASK
67450. DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid__SHIFT
67451. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_bbweight_MASK
67452. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_bbweight__SHIFT
67453. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_byp_init_val_MASK
67454. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_byp_init_val__SHIFT
67455. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK
67456. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT
67457. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK
67458. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT
67459. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_dac_safeval_sel_MASK
67460. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT
67461. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_freq_lock_timer_MASK
67462. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT
67463. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_icostart_sel_MASK
67464. DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_icostart_sel__SHIFT
67465. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67466. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67467. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare_MASK
67468. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare__SHIFT
67469. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated_MASK
67470. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67471. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid_MASK
67472. DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid__SHIFT
67473. DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay_MASK
67474. DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67475. DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask_MASK
67476. DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67477. DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en_MASK
67478. DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67479. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67480. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67481. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67482. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67483. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67484. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67485. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67486. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67487. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67488. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67489. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67490. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67491. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67492. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67493. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67494. DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67495. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67496. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67497. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67498. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67499. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67500. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67501. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67502. DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67503. DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare_MASK
67504. DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare__SHIFT
67505. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis_MASK
67506. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis__SHIFT
67507. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en_MASK
67508. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67509. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67510. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67511. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67512. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67513. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67514. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67515. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67516. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67517. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67518. DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67519. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK
67520. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT
67521. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67522. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67523. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67524. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67525. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67526. DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67527. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1_MASK
67528. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1__SHIFT
67529. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2_MASK
67530. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2__SHIFT
67531. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3_MASK
67532. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3__SHIFT
67533. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4_MASK
67534. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4__SHIFT
67535. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5_MASK
67536. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5__SHIFT
67537. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6_MASK
67538. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6__SHIFT
67539. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7_MASK
67540. DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7__SHIFT
67541. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67542. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67543. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl_MASK
67544. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67545. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val_MASK
67546. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67547. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67548. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67549. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67550. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67551. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare_MASK
67552. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare__SHIFT
67553. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0_MASK
67554. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67555. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1_MASK
67556. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67557. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2_MASK
67558. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67559. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3_MASK
67560. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67561. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid_MASK
67562. DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid__SHIFT
67563. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare_MASK
67564. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare__SHIFT
67565. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67566. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67567. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated_MASK
67568. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67569. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid_MASK
67570. DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid__SHIFT
67571. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_bbweight_MASK
67572. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_bbweight__SHIFT
67573. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_byp_init_val_MASK
67574. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_byp_init_val__SHIFT
67575. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK
67576. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT
67577. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK
67578. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT
67579. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_dac_safeval_sel_MASK
67580. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT
67581. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_freq_lock_timer_MASK
67582. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT
67583. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_icostart_sel_MASK
67584. DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_icostart_sel__SHIFT
67585. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67586. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67587. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare_MASK
67588. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare__SHIFT
67589. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated_MASK
67590. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67591. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid_MASK
67592. DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid__SHIFT
67593. DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay_MASK
67594. DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67595. DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask_MASK
67596. DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67597. DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en_MASK
67598. DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67599. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67600. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67601. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67602. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67603. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67604. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67605. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67606. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67607. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67608. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67609. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67610. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67611. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67612. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67613. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67614. DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67615. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67616. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67617. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67618. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67619. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67620. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67621. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67622. DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67623. DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare_MASK
67624. DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare__SHIFT
67625. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis_MASK
67626. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis__SHIFT
67627. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en_MASK
67628. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67629. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67630. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67631. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67632. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67633. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67634. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67635. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67636. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67637. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67638. DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67639. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK
67640. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT
67641. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67642. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67643. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67644. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67645. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67646. DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67647. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1_MASK
67648. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1__SHIFT
67649. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2_MASK
67650. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2__SHIFT
67651. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3_MASK
67652. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3__SHIFT
67653. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4_MASK
67654. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4__SHIFT
67655. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5_MASK
67656. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5__SHIFT
67657. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6_MASK
67658. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6__SHIFT
67659. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7_MASK
67660. DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7__SHIFT
67661. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67662. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67663. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl_MASK
67664. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67665. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val_MASK
67666. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67667. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67668. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67669. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67670. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67671. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare_MASK
67672. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare__SHIFT
67673. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0_MASK
67674. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67675. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1_MASK
67676. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67677. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2_MASK
67678. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67679. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3_MASK
67680. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67681. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid_MASK
67682. DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid__SHIFT
67683. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare_MASK
67684. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare__SHIFT
67685. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67686. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67687. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated_MASK
67688. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67689. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid_MASK
67690. DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid__SHIFT
67691. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67692. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67693. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare_MASK
67694. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare__SHIFT
67695. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated_MASK
67696. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67697. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid_MASK
67698. DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid__SHIFT
67699. DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay_MASK
67700. DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67701. DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask_MASK
67702. DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67703. DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en_MASK
67704. DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67705. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67706. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67707. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67708. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67709. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67710. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67711. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67712. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67713. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67714. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67715. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67716. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67717. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67718. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67719. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67720. DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67721. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67722. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67723. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67724. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67725. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67726. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67727. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67728. DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67729. DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare_MASK
67730. DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare__SHIFT
67731. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis_MASK
67732. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis__SHIFT
67733. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en_MASK
67734. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67735. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67736. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67737. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67738. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67739. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67740. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67741. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67742. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67743. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67744. DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67745. DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67746. DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67747. DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67748. DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67749. DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67750. DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67751. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1_MASK
67752. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1__SHIFT
67753. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2_MASK
67754. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2__SHIFT
67755. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3_MASK
67756. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3__SHIFT
67757. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4_MASK
67758. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4__SHIFT
67759. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5_MASK
67760. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5__SHIFT
67761. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6_MASK
67762. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6__SHIFT
67763. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7_MASK
67764. DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7__SHIFT
67765. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67766. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67767. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl_MASK
67768. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67769. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val_MASK
67770. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67771. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67772. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67773. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67774. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67775. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare_MASK
67776. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare__SHIFT
67777. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0_MASK
67778. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67779. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1_MASK
67780. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67781. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2_MASK
67782. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67783. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3_MASK
67784. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67785. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid_MASK
67786. DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid__SHIFT
67787. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare_MASK
67788. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare__SHIFT
67789. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67790. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67791. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated_MASK
67792. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67793. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid_MASK
67794. DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid__SHIFT
67795. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67796. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67797. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare_MASK
67798. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare__SHIFT
67799. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated_MASK
67800. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67801. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid_MASK
67802. DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid__SHIFT
67803. DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay_MASK
67804. DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67805. DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask_MASK
67806. DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67807. DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en_MASK
67808. DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67809. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67810. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67811. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67812. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67813. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67814. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67815. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67816. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67817. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67818. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67819. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67820. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67821. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67822. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67823. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67824. DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67825. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67826. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67827. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67828. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67829. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67830. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67831. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67832. DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67833. DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare_MASK
67834. DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare__SHIFT
67835. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis_MASK
67836. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis__SHIFT
67837. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en_MASK
67838. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67839. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67840. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67841. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67842. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67843. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67844. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67845. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67846. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67847. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67848. DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67849. DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67850. DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67851. DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67852. DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67853. DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67854. DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67855. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1_MASK
67856. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1__SHIFT
67857. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2_MASK
67858. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2__SHIFT
67859. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3_MASK
67860. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3__SHIFT
67861. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4_MASK
67862. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4__SHIFT
67863. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5_MASK
67864. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5__SHIFT
67865. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6_MASK
67866. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6__SHIFT
67867. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7_MASK
67868. DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7__SHIFT
67869. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67870. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67871. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl_MASK
67872. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67873. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val_MASK
67874. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67875. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67876. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67877. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67878. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67879. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare_MASK
67880. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare__SHIFT
67881. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0_MASK
67882. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67883. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1_MASK
67884. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67885. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2_MASK
67886. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67887. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3_MASK
67888. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67889. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid_MASK
67890. DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid__SHIFT
67891. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare_MASK
67892. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare__SHIFT
67893. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67894. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67895. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated_MASK
67896. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated__SHIFT
67897. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid_MASK
67898. DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid__SHIFT
67899. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
67900. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
67901. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare_MASK
67902. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare__SHIFT
67903. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated_MASK
67904. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated__SHIFT
67905. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid_MASK
67906. DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid__SHIFT
67907. DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay_MASK
67908. DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
67909. DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask_MASK
67910. DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask__SHIFT
67911. DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en_MASK
67912. DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
67913. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l_MASK
67914. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
67915. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l_MASK
67916. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
67917. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l_MASK
67918. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
67919. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l_MASK
67920. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
67921. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l_MASK
67922. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
67923. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l_MASK
67924. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
67925. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l_MASK
67926. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
67927. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l_MASK
67928. DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
67929. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
67930. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
67931. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
67932. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
67933. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
67934. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
67935. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
67936. DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
67937. DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare_MASK
67938. DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare__SHIFT
67939. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis_MASK
67940. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis__SHIFT
67941. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en_MASK
67942. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en__SHIFT
67943. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
67944. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
67945. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
67946. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
67947. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
67948. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
67949. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
67950. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
67951. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
67952. DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
67953. DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
67954. DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
67955. DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
67956. DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
67957. DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
67958. DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
67959. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1_MASK
67960. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1__SHIFT
67961. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2_MASK
67962. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2__SHIFT
67963. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3_MASK
67964. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3__SHIFT
67965. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4_MASK
67966. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4__SHIFT
67967. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5_MASK
67968. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5__SHIFT
67969. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6_MASK
67970. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6__SHIFT
67971. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7_MASK
67972. DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7__SHIFT
67973. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en_MASK
67974. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT
67975. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl_MASK
67976. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
67977. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val_MASK
67978. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val__SHIFT
67979. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl_MASK
67980. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
67981. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val_MASK
67982. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT
67983. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare_MASK
67984. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare__SHIFT
67985. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0_MASK
67986. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0__SHIFT
67987. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1_MASK
67988. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1__SHIFT
67989. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2_MASK
67990. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2__SHIFT
67991. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3_MASK
67992. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3__SHIFT
67993. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid_MASK
67994. DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid__SHIFT
67995. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare_MASK
67996. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare__SHIFT
67997. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK
67998. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT
67999. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated_MASK
68000. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated__SHIFT
68001. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid_MASK
68002. DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid__SHIFT
68003. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK
68004. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT
68005. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare_MASK
68006. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare__SHIFT
68007. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated_MASK
68008. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated__SHIFT
68009. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid_MASK
68010. DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid__SHIFT
68011. DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay_MASK
68012. DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
68013. DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask_MASK
68014. DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask__SHIFT
68015. DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en_MASK
68016. DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en__SHIFT
68017. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l_MASK
68018. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT
68019. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l_MASK
68020. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT
68021. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l_MASK
68022. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT
68023. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l_MASK
68024. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT
68025. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l_MASK
68026. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT
68027. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l_MASK
68028. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT
68029. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l_MASK
68030. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT
68031. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l_MASK
68032. DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT
68033. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
68034. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
68035. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
68036. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
68037. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
68038. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
68039. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
68040. DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
68041. DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare_MASK
68042. DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare__SHIFT
68043. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis_MASK
68044. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis__SHIFT
68045. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en_MASK
68046. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en__SHIFT
68047. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK
68048. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT
68049. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK
68050. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT
68051. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK
68052. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT
68053. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK
68054. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT
68055. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK
68056. DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT
68057. DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK
68058. DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT
68059. DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK
68060. DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT
68061. DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK
68062. DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT
68063. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp_MASK
68064. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68065. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant_MASK
68066. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68067. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp_MASK
68068. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68069. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant_MASK
68070. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68071. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68072. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68073. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res_MASK
68074. DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68075. DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3_MASK
68076. DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68077. DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock_MASK
68078. DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock__SHIFT
68079. DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis_MASK
68080. DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis__SHIFT
68081. DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis_MASK
68082. DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68083. DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio_MASK
68084. DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio__SHIFT
68085. DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel_MASK
68086. DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel__SHIFT
68087. DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis_MASK
68088. DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis__SHIFT
68089. DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate_MASK
68090. DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate__SHIFT
68091. DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl_MASK
68092. DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl__SHIFT
68093. DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en_MASK
68094. DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en__SHIFT
68095. DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data_MASK
68096. DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data__SHIFT
68097. DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac_MASK
68098. DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac__SHIFT
68099. DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int_MASK
68100. DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int__SHIFT
68101. DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac_MASK
68102. DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac__SHIFT
68103. DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int_MASK
68104. DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int__SHIFT
68105. DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom_MASK
68106. DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom__SHIFT
68107. DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac_MASK
68108. DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac__SHIFT
68109. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1_MASK
68110. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1__SHIFT
68111. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel_MASK
68112. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel__SHIFT
68113. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en_MASK
68114. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en__SHIFT
68115. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en_MASK
68116. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en__SHIFT
68117. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div_MASK
68118. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div__SHIFT
68119. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en_MASK
68120. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en__SHIFT
68121. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution_MASK
68122. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution__SHIFT
68123. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div_MASK
68124. DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div__SHIFT
68125. DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel_MASK
68126. DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel__SHIFT
68127. DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel_MASK
68128. DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel__SHIFT
68129. DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis_MASK
68130. DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis__SHIFT
68131. DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk_MASK
68132. DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk__SHIFT
68133. DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en_MASK
68134. DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en__SHIFT
68135. DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis_MASK
68136. DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis__SHIFT
68137. DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset_MASK
68138. DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset__SHIFT
68139. DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en_MASK
68140. DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en__SHIFT
68141. DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel_MASK
68142. DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel__SHIFT
68143. DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en_MASK
68144. DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en__SHIFT
68145. DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel_MASK
68146. DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel__SHIFT
68147. DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock_MASK
68148. DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock__SHIFT
68149. DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg_MASK
68150. DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg__SHIFT
68151. DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis_MASK
68152. DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis__SHIFT
68153. DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps_MASK
68154. DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps__SHIFT
68155. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div_MASK
68156. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div__SHIFT
68157. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel_MASK
68158. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel__SHIFT
68159. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div_MASK
68160. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div__SHIFT
68161. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel_MASK
68162. DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel__SHIFT
68163. DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer_MASK
68164. DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer__SHIFT
68165. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK
68166. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT
68167. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK
68168. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT
68169. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK
68170. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT
68171. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK
68172. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT
68173. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK
68174. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT
68175. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK
68176. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT
68177. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK
68178. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT
68179. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK
68180. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT
68181. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK
68182. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT
68183. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK
68184. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT
68185. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK
68186. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT
68187. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK
68188. DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT
68189. DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac_MASK
68190. DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac__SHIFT
68191. DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en_MASK
68192. DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en__SHIFT
68193. DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2_MASK
68194. DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2__SHIFT
68195. DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2_MASK
68196. DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2__SHIFT
68197. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel_MASK
68198. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel__SHIFT
68199. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi_MASK
68200. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi__SHIFT
68201. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo_MASK
68202. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo__SHIFT
68203. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode_MASK
68204. DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode__SHIFT
68205. DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel_MASK
68206. DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel__SHIFT
68207. DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver_MASK
68208. DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver__SHIFT
68209. DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump_MASK
68210. DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump__SHIFT
68211. DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x_MASK
68212. DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x__SHIFT
68213. DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x_MASK
68214. DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x__SHIFT
68215. DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on_MASK
68216. DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on__SHIFT
68217. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp_MASK
68218. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68219. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant_MASK
68220. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68221. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp_MASK
68222. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68223. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant_MASK
68224. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68225. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68226. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68227. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res_MASK
68228. DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68229. DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3_MASK
68230. DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68231. DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock_MASK
68232. DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock__SHIFT
68233. DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis_MASK
68234. DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis__SHIFT
68235. DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis_MASK
68236. DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68237. DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio_MASK
68238. DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio__SHIFT
68239. DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel_MASK
68240. DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel__SHIFT
68241. DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis_MASK
68242. DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis__SHIFT
68243. DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate_MASK
68244. DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate__SHIFT
68245. DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl_MASK
68246. DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl__SHIFT
68247. DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en_MASK
68248. DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en__SHIFT
68249. DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data_MASK
68250. DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data__SHIFT
68251. DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac_MASK
68252. DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac__SHIFT
68253. DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int_MASK
68254. DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int__SHIFT
68255. DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac_MASK
68256. DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac__SHIFT
68257. DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int_MASK
68258. DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int__SHIFT
68259. DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom_MASK
68260. DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom__SHIFT
68261. DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac_MASK
68262. DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac__SHIFT
68263. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1_MASK
68264. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1__SHIFT
68265. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel_MASK
68266. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel__SHIFT
68267. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en_MASK
68268. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en__SHIFT
68269. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en_MASK
68270. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en__SHIFT
68271. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div_MASK
68272. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div__SHIFT
68273. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en_MASK
68274. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en__SHIFT
68275. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution_MASK
68276. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution__SHIFT
68277. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div_MASK
68278. DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div__SHIFT
68279. DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel_MASK
68280. DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel__SHIFT
68281. DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel_MASK
68282. DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel__SHIFT
68283. DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis_MASK
68284. DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis__SHIFT
68285. DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk_MASK
68286. DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk__SHIFT
68287. DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en_MASK
68288. DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en__SHIFT
68289. DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis_MASK
68290. DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis__SHIFT
68291. DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset_MASK
68292. DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset__SHIFT
68293. DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en_MASK
68294. DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en__SHIFT
68295. DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel_MASK
68296. DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel__SHIFT
68297. DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en_MASK
68298. DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en__SHIFT
68299. DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel_MASK
68300. DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel__SHIFT
68301. DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock_MASK
68302. DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock__SHIFT
68303. DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg_MASK
68304. DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg__SHIFT
68305. DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis_MASK
68306. DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis__SHIFT
68307. DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps_MASK
68308. DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps__SHIFT
68309. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div_MASK
68310. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div__SHIFT
68311. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel_MASK
68312. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel__SHIFT
68313. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div_MASK
68314. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div__SHIFT
68315. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel_MASK
68316. DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel__SHIFT
68317. DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer_MASK
68318. DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer__SHIFT
68319. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK
68320. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT
68321. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK
68322. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT
68323. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK
68324. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT
68325. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK
68326. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT
68327. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK
68328. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT
68329. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK
68330. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT
68331. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK
68332. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT
68333. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK
68334. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT
68335. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK
68336. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT
68337. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK
68338. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT
68339. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK
68340. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT
68341. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK
68342. DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT
68343. DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac_MASK
68344. DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac__SHIFT
68345. DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en_MASK
68346. DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en__SHIFT
68347. DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2_MASK
68348. DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2__SHIFT
68349. DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2_MASK
68350. DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2__SHIFT
68351. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel_MASK
68352. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel__SHIFT
68353. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi_MASK
68354. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi__SHIFT
68355. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo_MASK
68356. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo__SHIFT
68357. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode_MASK
68358. DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode__SHIFT
68359. DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel_MASK
68360. DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel__SHIFT
68361. DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver_MASK
68362. DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver__SHIFT
68363. DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump_MASK
68364. DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump__SHIFT
68365. DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x_MASK
68366. DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x__SHIFT
68367. DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x_MASK
68368. DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x__SHIFT
68369. DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on_MASK
68370. DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on__SHIFT
68371. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp_MASK
68372. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68373. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant_MASK
68374. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68375. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp_MASK
68376. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68377. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant_MASK
68378. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68379. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68380. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68381. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res_MASK
68382. DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68383. DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3_MASK
68384. DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68385. DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock_MASK
68386. DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock__SHIFT
68387. DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis_MASK
68388. DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis__SHIFT
68389. DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis_MASK
68390. DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68391. DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio_MASK
68392. DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio__SHIFT
68393. DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel_MASK
68394. DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel__SHIFT
68395. DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis_MASK
68396. DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis__SHIFT
68397. DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate_MASK
68398. DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate__SHIFT
68399. DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl_MASK
68400. DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl__SHIFT
68401. DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en_MASK
68402. DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en__SHIFT
68403. DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data_MASK
68404. DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data__SHIFT
68405. DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac_MASK
68406. DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac__SHIFT
68407. DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int_MASK
68408. DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int__SHIFT
68409. DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac_MASK
68410. DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac__SHIFT
68411. DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int_MASK
68412. DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int__SHIFT
68413. DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom_MASK
68414. DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom__SHIFT
68415. DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac_MASK
68416. DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac__SHIFT
68417. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1_MASK
68418. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1__SHIFT
68419. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel_MASK
68420. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel__SHIFT
68421. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en_MASK
68422. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en__SHIFT
68423. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en_MASK
68424. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en__SHIFT
68425. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div_MASK
68426. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div__SHIFT
68427. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en_MASK
68428. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en__SHIFT
68429. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution_MASK
68430. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution__SHIFT
68431. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div_MASK
68432. DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div__SHIFT
68433. DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel_MASK
68434. DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel__SHIFT
68435. DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel_MASK
68436. DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel__SHIFT
68437. DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis_MASK
68438. DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis__SHIFT
68439. DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk_MASK
68440. DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk__SHIFT
68441. DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en_MASK
68442. DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en__SHIFT
68443. DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis_MASK
68444. DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis__SHIFT
68445. DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset_MASK
68446. DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset__SHIFT
68447. DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en_MASK
68448. DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en__SHIFT
68449. DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel_MASK
68450. DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel__SHIFT
68451. DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en_MASK
68452. DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en__SHIFT
68453. DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel_MASK
68454. DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel__SHIFT
68455. DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock_MASK
68456. DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock__SHIFT
68457. DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg_MASK
68458. DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg__SHIFT
68459. DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis_MASK
68460. DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis__SHIFT
68461. DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps_MASK
68462. DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps__SHIFT
68463. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div_MASK
68464. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div__SHIFT
68465. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel_MASK
68466. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel__SHIFT
68467. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div_MASK
68468. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div__SHIFT
68469. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel_MASK
68470. DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel__SHIFT
68471. DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer_MASK
68472. DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer__SHIFT
68473. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK
68474. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT
68475. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK
68476. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT
68477. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK
68478. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT
68479. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK
68480. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT
68481. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK
68482. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT
68483. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK
68484. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT
68485. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK
68486. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT
68487. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK
68488. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT
68489. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK
68490. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT
68491. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK
68492. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT
68493. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK
68494. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT
68495. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK
68496. DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT
68497. DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac_MASK
68498. DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac__SHIFT
68499. DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en_MASK
68500. DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en__SHIFT
68501. DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2_MASK
68502. DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2__SHIFT
68503. DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2_MASK
68504. DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2__SHIFT
68505. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel_MASK
68506. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel__SHIFT
68507. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi_MASK
68508. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi__SHIFT
68509. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo_MASK
68510. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo__SHIFT
68511. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode_MASK
68512. DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode__SHIFT
68513. DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel_MASK
68514. DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel__SHIFT
68515. DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver_MASK
68516. DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver__SHIFT
68517. DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump_MASK
68518. DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump__SHIFT
68519. DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x_MASK
68520. DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x__SHIFT
68521. DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x_MASK
68522. DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x__SHIFT
68523. DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on_MASK
68524. DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on__SHIFT
68525. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp_MASK
68526. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68527. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant_MASK
68528. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68529. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp_MASK
68530. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68531. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant_MASK
68532. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68533. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68534. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68535. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res_MASK
68536. DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68537. DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3_MASK
68538. DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68539. DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock_MASK
68540. DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock__SHIFT
68541. DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis_MASK
68542. DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis__SHIFT
68543. DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis_MASK
68544. DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68545. DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio_MASK
68546. DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio__SHIFT
68547. DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel_MASK
68548. DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel__SHIFT
68549. DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis_MASK
68550. DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis__SHIFT
68551. DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate_MASK
68552. DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate__SHIFT
68553. DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl_MASK
68554. DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl__SHIFT
68555. DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en_MASK
68556. DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en__SHIFT
68557. DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data_MASK
68558. DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data__SHIFT
68559. DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac_MASK
68560. DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac__SHIFT
68561. DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int_MASK
68562. DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int__SHIFT
68563. DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac_MASK
68564. DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac__SHIFT
68565. DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int_MASK
68566. DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int__SHIFT
68567. DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom_MASK
68568. DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom__SHIFT
68569. DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac_MASK
68570. DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac__SHIFT
68571. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1_MASK
68572. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1__SHIFT
68573. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel_MASK
68574. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel__SHIFT
68575. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en_MASK
68576. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en__SHIFT
68577. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en_MASK
68578. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en__SHIFT
68579. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div_MASK
68580. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div__SHIFT
68581. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en_MASK
68582. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en__SHIFT
68583. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution_MASK
68584. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution__SHIFT
68585. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div_MASK
68586. DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div__SHIFT
68587. DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel_MASK
68588. DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel__SHIFT
68589. DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel_MASK
68590. DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel__SHIFT
68591. DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis_MASK
68592. DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis__SHIFT
68593. DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk_MASK
68594. DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk__SHIFT
68595. DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en_MASK
68596. DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en__SHIFT
68597. DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis_MASK
68598. DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis__SHIFT
68599. DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset_MASK
68600. DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset__SHIFT
68601. DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en_MASK
68602. DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en__SHIFT
68603. DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel_MASK
68604. DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel__SHIFT
68605. DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en_MASK
68606. DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en__SHIFT
68607. DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel_MASK
68608. DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel__SHIFT
68609. DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock_MASK
68610. DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock__SHIFT
68611. DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg_MASK
68612. DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg__SHIFT
68613. DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis_MASK
68614. DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis__SHIFT
68615. DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps_MASK
68616. DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps__SHIFT
68617. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div_MASK
68618. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div__SHIFT
68619. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel_MASK
68620. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel__SHIFT
68621. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div_MASK
68622. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div__SHIFT
68623. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel_MASK
68624. DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel__SHIFT
68625. DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer_MASK
68626. DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer__SHIFT
68627. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK
68628. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT
68629. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK
68630. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT
68631. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK
68632. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT
68633. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK
68634. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT
68635. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK
68636. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT
68637. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK
68638. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT
68639. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK
68640. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT
68641. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK
68642. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT
68643. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK
68644. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT
68645. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK
68646. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT
68647. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK
68648. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT
68649. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK
68650. DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT
68651. DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac_MASK
68652. DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac__SHIFT
68653. DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en_MASK
68654. DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en__SHIFT
68655. DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2_MASK
68656. DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2__SHIFT
68657. DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2_MASK
68658. DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2__SHIFT
68659. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel_MASK
68660. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel__SHIFT
68661. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi_MASK
68662. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi__SHIFT
68663. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo_MASK
68664. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo__SHIFT
68665. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode_MASK
68666. DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode__SHIFT
68667. DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel_MASK
68668. DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel__SHIFT
68669. DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver_MASK
68670. DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver__SHIFT
68671. DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump_MASK
68672. DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump__SHIFT
68673. DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x_MASK
68674. DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x__SHIFT
68675. DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x_MASK
68676. DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x__SHIFT
68677. DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on_MASK
68678. DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on__SHIFT
68679. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp_MASK
68680. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68681. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant_MASK
68682. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68683. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp_MASK
68684. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68685. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant_MASK
68686. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68687. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68688. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68689. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res_MASK
68690. DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68691. DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3_MASK
68692. DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68693. DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock_MASK
68694. DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock__SHIFT
68695. DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis_MASK
68696. DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis__SHIFT
68697. DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis_MASK
68698. DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68699. DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio_MASK
68700. DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio__SHIFT
68701. DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel_MASK
68702. DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel__SHIFT
68703. DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis_MASK
68704. DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis__SHIFT
68705. DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate_MASK
68706. DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate__SHIFT
68707. DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl_MASK
68708. DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl__SHIFT
68709. DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en_MASK
68710. DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en__SHIFT
68711. DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data_MASK
68712. DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data__SHIFT
68713. DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac_MASK
68714. DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac__SHIFT
68715. DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int_MASK
68716. DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int__SHIFT
68717. DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac_MASK
68718. DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac__SHIFT
68719. DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int_MASK
68720. DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int__SHIFT
68721. DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom_MASK
68722. DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom__SHIFT
68723. DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac_MASK
68724. DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac__SHIFT
68725. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1_MASK
68726. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1__SHIFT
68727. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel_MASK
68728. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel__SHIFT
68729. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en_MASK
68730. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en__SHIFT
68731. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en_MASK
68732. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en__SHIFT
68733. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div_MASK
68734. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div__SHIFT
68735. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en_MASK
68736. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en__SHIFT
68737. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution_MASK
68738. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution__SHIFT
68739. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div_MASK
68740. DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div__SHIFT
68741. DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel_MASK
68742. DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel__SHIFT
68743. DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel_MASK
68744. DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel__SHIFT
68745. DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis_MASK
68746. DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis__SHIFT
68747. DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk_MASK
68748. DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk__SHIFT
68749. DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en_MASK
68750. DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en__SHIFT
68751. DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis_MASK
68752. DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis__SHIFT
68753. DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset_MASK
68754. DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset__SHIFT
68755. DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en_MASK
68756. DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en__SHIFT
68757. DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel_MASK
68758. DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel__SHIFT
68759. DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en_MASK
68760. DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en__SHIFT
68761. DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel_MASK
68762. DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel__SHIFT
68763. DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock_MASK
68764. DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock__SHIFT
68765. DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg_MASK
68766. DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg__SHIFT
68767. DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis_MASK
68768. DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis__SHIFT
68769. DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps_MASK
68770. DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps__SHIFT
68771. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div_MASK
68772. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div__SHIFT
68773. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel_MASK
68774. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel__SHIFT
68775. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div_MASK
68776. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div__SHIFT
68777. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel_MASK
68778. DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel__SHIFT
68779. DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer_MASK
68780. DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer__SHIFT
68781. DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac_MASK
68782. DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac__SHIFT
68783. DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en_MASK
68784. DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en__SHIFT
68785. DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2_MASK
68786. DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2__SHIFT
68787. DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2_MASK
68788. DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2__SHIFT
68789. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel_MASK
68790. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel__SHIFT
68791. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi_MASK
68792. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi__SHIFT
68793. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo_MASK
68794. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo__SHIFT
68795. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode_MASK
68796. DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode__SHIFT
68797. DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel_MASK
68798. DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel__SHIFT
68799. DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver_MASK
68800. DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver__SHIFT
68801. DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump_MASK
68802. DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump__SHIFT
68803. DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x_MASK
68804. DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x__SHIFT
68805. DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x_MASK
68806. DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x__SHIFT
68807. DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on_MASK
68808. DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on__SHIFT
68809. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp_MASK
68810. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68811. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant_MASK
68812. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68813. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp_MASK
68814. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68815. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant_MASK
68816. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68817. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68818. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68819. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res_MASK
68820. DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68821. DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3_MASK
68822. DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68823. DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock_MASK
68824. DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock__SHIFT
68825. DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis_MASK
68826. DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis__SHIFT
68827. DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis_MASK
68828. DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68829. DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio_MASK
68830. DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio__SHIFT
68831. DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel_MASK
68832. DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel__SHIFT
68833. DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis_MASK
68834. DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis__SHIFT
68835. DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate_MASK
68836. DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate__SHIFT
68837. DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl_MASK
68838. DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl__SHIFT
68839. DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en_MASK
68840. DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en__SHIFT
68841. DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data_MASK
68842. DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data__SHIFT
68843. DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac_MASK
68844. DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac__SHIFT
68845. DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int_MASK
68846. DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int__SHIFT
68847. DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac_MASK
68848. DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac__SHIFT
68849. DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int_MASK
68850. DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int__SHIFT
68851. DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom_MASK
68852. DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom__SHIFT
68853. DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac_MASK
68854. DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac__SHIFT
68855. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1_MASK
68856. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1__SHIFT
68857. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel_MASK
68858. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel__SHIFT
68859. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en_MASK
68860. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en__SHIFT
68861. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en_MASK
68862. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en__SHIFT
68863. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div_MASK
68864. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div__SHIFT
68865. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en_MASK
68866. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en__SHIFT
68867. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution_MASK
68868. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution__SHIFT
68869. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div_MASK
68870. DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div__SHIFT
68871. DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel_MASK
68872. DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel__SHIFT
68873. DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel_MASK
68874. DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel__SHIFT
68875. DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis_MASK
68876. DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis__SHIFT
68877. DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk_MASK
68878. DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk__SHIFT
68879. DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en_MASK
68880. DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en__SHIFT
68881. DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis_MASK
68882. DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis__SHIFT
68883. DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset_MASK
68884. DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset__SHIFT
68885. DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en_MASK
68886. DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en__SHIFT
68887. DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel_MASK
68888. DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel__SHIFT
68889. DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en_MASK
68890. DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en__SHIFT
68891. DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel_MASK
68892. DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel__SHIFT
68893. DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock_MASK
68894. DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock__SHIFT
68895. DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg_MASK
68896. DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg__SHIFT
68897. DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis_MASK
68898. DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis__SHIFT
68899. DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps_MASK
68900. DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps__SHIFT
68901. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div_MASK
68902. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div__SHIFT
68903. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel_MASK
68904. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel__SHIFT
68905. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div_MASK
68906. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div__SHIFT
68907. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel_MASK
68908. DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel__SHIFT
68909. DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer_MASK
68910. DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer__SHIFT
68911. DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac_MASK
68912. DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac__SHIFT
68913. DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en_MASK
68914. DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en__SHIFT
68915. DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2_MASK
68916. DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2__SHIFT
68917. DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2_MASK
68918. DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2__SHIFT
68919. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel_MASK
68920. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel__SHIFT
68921. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi_MASK
68922. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi__SHIFT
68923. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo_MASK
68924. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo__SHIFT
68925. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode_MASK
68926. DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode__SHIFT
68927. DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel_MASK
68928. DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel__SHIFT
68929. DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver_MASK
68930. DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver__SHIFT
68931. DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump_MASK
68932. DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump__SHIFT
68933. DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x_MASK
68934. DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x__SHIFT
68935. DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x_MASK
68936. DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x__SHIFT
68937. DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on_MASK
68938. DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on__SHIFT
68939. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp_MASK
68940. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
68941. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant_MASK
68942. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
68943. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp_MASK
68944. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
68945. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant_MASK
68946. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
68947. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
68948. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
68949. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res_MASK
68950. DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
68951. DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3_MASK
68952. DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3__SHIFT
68953. DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock_MASK
68954. DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock__SHIFT
68955. DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis_MASK
68956. DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis__SHIFT
68957. DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis_MASK
68958. DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis__SHIFT
68959. DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio_MASK
68960. DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio__SHIFT
68961. DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel_MASK
68962. DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel__SHIFT
68963. DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis_MASK
68964. DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis__SHIFT
68965. DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate_MASK
68966. DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate__SHIFT
68967. DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl_MASK
68968. DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl__SHIFT
68969. DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en_MASK
68970. DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en__SHIFT
68971. DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data_MASK
68972. DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data__SHIFT
68973. DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac_MASK
68974. DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac__SHIFT
68975. DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int_MASK
68976. DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int__SHIFT
68977. DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac_MASK
68978. DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac__SHIFT
68979. DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int_MASK
68980. DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int__SHIFT
68981. DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom_MASK
68982. DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom__SHIFT
68983. DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac_MASK
68984. DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac__SHIFT
68985. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1_MASK
68986. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1__SHIFT
68987. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel_MASK
68988. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel__SHIFT
68989. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en_MASK
68990. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en__SHIFT
68991. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en_MASK
68992. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en__SHIFT
68993. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div_MASK
68994. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div__SHIFT
68995. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en_MASK
68996. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en__SHIFT
68997. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution_MASK
68998. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution__SHIFT
68999. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div_MASK
69000. DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div__SHIFT
69001. DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel_MASK
69002. DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel__SHIFT
69003. DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel_MASK
69004. DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel__SHIFT
69005. DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis_MASK
69006. DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis__SHIFT
69007. DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk_MASK
69008. DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk__SHIFT
69009. DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en_MASK
69010. DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en__SHIFT
69011. DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis_MASK
69012. DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis__SHIFT
69013. DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset_MASK
69014. DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset__SHIFT
69015. DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en_MASK
69016. DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en__SHIFT
69017. DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel_MASK
69018. DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel__SHIFT
69019. DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en_MASK
69020. DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en__SHIFT
69021. DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel_MASK
69022. DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel__SHIFT
69023. DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock_MASK
69024. DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock__SHIFT
69025. DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg_MASK
69026. DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg__SHIFT
69027. DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis_MASK
69028. DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis__SHIFT
69029. DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps_MASK
69030. DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps__SHIFT
69031. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div_MASK
69032. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div__SHIFT
69033. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel_MASK
69034. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel__SHIFT
69035. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div_MASK
69036. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div__SHIFT
69037. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel_MASK
69038. DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel__SHIFT
69039. DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer_MASK
69040. DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer__SHIFT
69041. DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac_MASK
69042. DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac__SHIFT
69043. DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en_MASK
69044. DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en__SHIFT
69045. DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2_MASK
69046. DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2__SHIFT
69047. DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2_MASK
69048. DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2__SHIFT
69049. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel_MASK
69050. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel__SHIFT
69051. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi_MASK
69052. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi__SHIFT
69053. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo_MASK
69054. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo__SHIFT
69055. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode_MASK
69056. DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode__SHIFT
69057. DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel_MASK
69058. DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel__SHIFT
69059. DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver_MASK
69060. DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver__SHIFT
69061. DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump_MASK
69062. DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump__SHIFT
69063. DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x_MASK
69064. DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x__SHIFT
69065. DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x_MASK
69066. DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x__SHIFT
69067. DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on_MASK
69068. DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on__SHIFT
69069. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp_MASK
69070. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp__SHIFT
69071. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant_MASK
69072. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant__SHIFT
69073. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp_MASK
69074. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp__SHIFT
69075. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant_MASK
69076. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant__SHIFT
69077. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
69078. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
69079. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res_MASK
69080. DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res__SHIFT
69081. DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3_MASK
69082. DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3__SHIFT
69083. DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock_MASK
69084. DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock__SHIFT
69085. DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis_MASK
69086. DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis__SHIFT
69087. DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis_MASK
69088. DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis__SHIFT
69089. DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio_MASK
69090. DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio__SHIFT
69091. DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel_MASK
69092. DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel__SHIFT
69093. DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis_MASK
69094. DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis__SHIFT
69095. DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate_MASK
69096. DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate__SHIFT
69097. DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl_MASK
69098. DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl__SHIFT
69099. DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en_MASK
69100. DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en__SHIFT
69101. DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data_MASK
69102. DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data__SHIFT
69103. DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac_MASK
69104. DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac__SHIFT
69105. DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int_MASK
69106. DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int__SHIFT
69107. DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac_MASK
69108. DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac__SHIFT
69109. DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int_MASK
69110. DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int__SHIFT
69111. DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom_MASK
69112. DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom__SHIFT
69113. DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac_MASK
69114. DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac__SHIFT
69115. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1_MASK
69116. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1__SHIFT
69117. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel_MASK
69118. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel__SHIFT
69119. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en_MASK
69120. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en__SHIFT
69121. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en_MASK
69122. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en__SHIFT
69123. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div_MASK
69124. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div__SHIFT
69125. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en_MASK
69126. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en__SHIFT
69127. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution_MASK
69128. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution__SHIFT
69129. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div_MASK
69130. DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div__SHIFT
69131. DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel_MASK
69132. DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel__SHIFT
69133. DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel_MASK
69134. DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel__SHIFT
69135. DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis_MASK
69136. DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis__SHIFT
69137. DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk_MASK
69138. DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk__SHIFT
69139. DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en_MASK
69140. DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en__SHIFT
69141. DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis_MASK
69142. DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis__SHIFT
69143. DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset_MASK
69144. DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset__SHIFT
69145. DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en_MASK
69146. DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en__SHIFT
69147. DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel_MASK
69148. DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel__SHIFT
69149. DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en_MASK
69150. DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en__SHIFT
69151. DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel_MASK
69152. DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel__SHIFT
69153. DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock_MASK
69154. DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock__SHIFT
69155. DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg_MASK
69156. DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg__SHIFT
69157. DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis_MASK
69158. DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis__SHIFT
69159. DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps_MASK
69160. DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps__SHIFT
69161. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div_MASK
69162. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div__SHIFT
69163. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel_MASK
69164. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel__SHIFT
69165. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div_MASK
69166. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div__SHIFT
69167. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel_MASK
69168. DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel__SHIFT
69169. DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer_MASK
69170. DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer__SHIFT
69171. DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac_MASK
69172. DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac__SHIFT
69173. DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en_MASK
69174. DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en__SHIFT
69175. DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2_MASK
69176. DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2__SHIFT
69177. DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2_MASK
69178. DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2__SHIFT
69179. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel_MASK
69180. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel__SHIFT
69181. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi_MASK
69182. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi__SHIFT
69183. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo_MASK
69184. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo__SHIFT
69185. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode_MASK
69186. DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode__SHIFT
69187. DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel_MASK
69188. DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel__SHIFT
69189. DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver_MASK
69190. DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver__SHIFT
69191. DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump_MASK
69192. DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump__SHIFT
69193. DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x_MASK
69194. DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x__SHIFT
69195. DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x_MASK
69196. DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x__SHIFT
69197. DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on_MASK
69198. DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on__SHIFT
69199. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
69200. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
69201. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
69202. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
69203. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
69204. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
69205. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
69206. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
69207. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
69208. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
69209. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
69210. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
69211. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
69212. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
69213. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
69214. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
69215. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
69216. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
69217. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
69218. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
69219. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
69220. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
69221. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
69222. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
69223. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
69224. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
69225. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
69226. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
69227. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
69228. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
69229. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
69230. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
69231. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
69232. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
69233. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
69234. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
69235. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
69236. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
69237. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
69238. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
69239. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
69240. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
69241. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
69242. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
69243. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
69244. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
69245. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
69246. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
69247. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
69248. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
69249. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
69250. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
69251. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
69252. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
69253. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
69254. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
69255. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
69256. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
69257. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
69258. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
69259. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
69260. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
69261. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
69262. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
69263. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
69264. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
69265. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
69266. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
69267. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
69268. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
69269. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
69270. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
69271. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
69272. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
69273. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
69274. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
69275. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
69276. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
69277. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
69278. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
69279. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
69280. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
69281. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
69282. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
69283. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
69284. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
69285. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
69286. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
69287. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
69288. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
69289. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
69290. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
69291. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
69292. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
69293. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
69294. DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
69295. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
69296. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
69297. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
69298. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
69299. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
69300. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
69301. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
69302. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
69303. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
69304. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
69305. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
69306. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
69307. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
69308. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
69309. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
69310. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
69311. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
69312. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
69313. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
69314. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
69315. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
69316. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
69317. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
69318. DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
69319. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
69320. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
69321. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
69322. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
69323. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
69324. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
69325. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
69326. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
69327. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
69328. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
69329. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
69330. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
69331. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
69332. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
69333. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
69334. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
69335. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
69336. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
69337. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
69338. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
69339. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
69340. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
69341. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
69342. DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
69343. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0_MASK
69344. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
69345. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0_MASK
69346. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
69347. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0_MASK
69348. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
69349. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0_MASK
69350. DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
69351. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10_MASK
69352. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
69353. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10_MASK
69354. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
69355. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10_MASK
69356. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
69357. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10_MASK
69358. DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
69359. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11_MASK
69360. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
69361. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11_MASK
69362. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
69363. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11_MASK
69364. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
69365. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11_MASK
69366. DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
69367. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12_MASK
69368. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
69369. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12_MASK
69370. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
69371. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12_MASK
69372. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
69373. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12_MASK
69374. DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
69375. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1_MASK
69376. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
69377. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1_MASK
69378. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
69379. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1_MASK
69380. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
69381. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1_MASK
69382. DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
69383. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2_MASK
69384. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
69385. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2_MASK
69386. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
69387. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2_MASK
69388. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
69389. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2_MASK
69390. DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
69391. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3_MASK
69392. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
69393. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3_MASK
69394. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
69395. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3_MASK
69396. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
69397. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3_MASK
69398. DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
69399. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4_MASK
69400. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
69401. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4_MASK
69402. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
69403. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4_MASK
69404. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
69405. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4_MASK
69406. DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
69407. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5_MASK
69408. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
69409. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5_MASK
69410. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
69411. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5_MASK
69412. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
69413. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5_MASK
69414. DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
69415. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6_MASK
69416. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
69417. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6_MASK
69418. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
69419. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6_MASK
69420. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
69421. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6_MASK
69422. DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
69423. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7_MASK
69424. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
69425. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7_MASK
69426. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
69427. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7_MASK
69428. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
69429. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7_MASK
69430. DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
69431. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8_MASK
69432. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
69433. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8_MASK
69434. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
69435. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8_MASK
69436. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
69437. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8_MASK
69438. DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
69439. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9_MASK
69440. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
69441. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9_MASK
69442. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
69443. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9_MASK
69444. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
69445. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9_MASK
69446. DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
69447. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
69448. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
69449. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
69450. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
69451. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
69452. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
69453. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
69454. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
69455. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
69456. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
69457. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
69458. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
69459. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
69460. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
69461. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
69462. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
69463. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
69464. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
69465. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
69466. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
69467. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
69468. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
69469. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
69470. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
69471. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
69472. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
69473. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
69474. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
69475. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
69476. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
69477. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
69478. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
69479. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
69480. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
69481. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
69482. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
69483. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
69484. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
69485. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
69486. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
69487. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
69488. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
69489. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
69490. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
69491. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
69492. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
69493. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
69494. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
69495. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
69496. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
69497. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
69498. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
69499. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
69500. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
69501. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
69502. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
69503. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
69504. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
69505. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
69506. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
69507. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
69508. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
69509. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
69510. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
69511. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
69512. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
69513. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
69514. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
69515. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
69516. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
69517. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
69518. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
69519. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
69520. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
69521. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
69522. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
69523. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
69524. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
69525. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
69526. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
69527. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
69528. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
69529. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
69530. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
69531. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
69532. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
69533. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
69534. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
69535. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
69536. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
69537. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
69538. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
69539. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
69540. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
69541. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
69542. DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
69543. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
69544. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
69545. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
69546. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
69547. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
69548. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
69549. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
69550. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
69551. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
69552. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
69553. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
69554. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
69555. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
69556. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
69557. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
69558. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
69559. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
69560. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
69561. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
69562. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
69563. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
69564. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
69565. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
69566. DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
69567. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
69568. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
69569. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
69570. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
69571. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
69572. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
69573. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
69574. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
69575. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
69576. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
69577. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
69578. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
69579. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
69580. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
69581. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
69582. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
69583. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
69584. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
69585. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
69586. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
69587. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
69588. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
69589. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
69590. DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
69591. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0_MASK
69592. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
69593. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0_MASK
69594. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
69595. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0_MASK
69596. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
69597. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0_MASK
69598. DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
69599. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10_MASK
69600. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
69601. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10_MASK
69602. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
69603. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10_MASK
69604. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
69605. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10_MASK
69606. DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
69607. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11_MASK
69608. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
69609. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11_MASK
69610. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
69611. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11_MASK
69612. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
69613. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11_MASK
69614. DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
69615. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12_MASK
69616. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
69617. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12_MASK
69618. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
69619. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12_MASK
69620. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
69621. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12_MASK
69622. DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
69623. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1_MASK
69624. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
69625. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1_MASK
69626. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
69627. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1_MASK
69628. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
69629. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1_MASK
69630. DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
69631. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2_MASK
69632. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
69633. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2_MASK
69634. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
69635. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2_MASK
69636. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
69637. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2_MASK
69638. DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
69639. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3_MASK
69640. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
69641. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3_MASK
69642. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
69643. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3_MASK
69644. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
69645. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3_MASK
69646. DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
69647. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4_MASK
69648. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
69649. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4_MASK
69650. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
69651. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4_MASK
69652. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
69653. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4_MASK
69654. DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
69655. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5_MASK
69656. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
69657. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5_MASK
69658. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
69659. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5_MASK
69660. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
69661. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5_MASK
69662. DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
69663. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6_MASK
69664. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
69665. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6_MASK
69666. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
69667. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6_MASK
69668. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
69669. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6_MASK
69670. DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
69671. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7_MASK
69672. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
69673. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7_MASK
69674. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
69675. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7_MASK
69676. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
69677. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7_MASK
69678. DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
69679. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8_MASK
69680. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
69681. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8_MASK
69682. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
69683. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8_MASK
69684. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
69685. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8_MASK
69686. DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
69687. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9_MASK
69688. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
69689. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9_MASK
69690. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
69691. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9_MASK
69692. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
69693. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9_MASK
69694. DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
69695. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
69696. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
69697. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
69698. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
69699. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
69700. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
69701. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
69702. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
69703. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
69704. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
69705. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
69706. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
69707. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
69708. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
69709. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
69710. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
69711. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
69712. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
69713. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
69714. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
69715. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
69716. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
69717. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
69718. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
69719. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
69720. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
69721. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
69722. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
69723. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
69724. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
69725. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
69726. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
69727. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
69728. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
69729. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
69730. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
69731. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
69732. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
69733. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
69734. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
69735. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
69736. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
69737. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
69738. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
69739. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
69740. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
69741. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
69742. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
69743. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
69744. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
69745. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
69746. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
69747. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
69748. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
69749. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
69750. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
69751. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
69752. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
69753. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
69754. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
69755. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
69756. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
69757. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
69758. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
69759. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
69760. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
69761. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
69762. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
69763. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
69764. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
69765. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
69766. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
69767. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
69768. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
69769. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
69770. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
69771. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
69772. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
69773. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
69774. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
69775. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
69776. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
69777. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
69778. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
69779. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
69780. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
69781. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
69782. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
69783. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
69784. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
69785. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
69786. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
69787. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
69788. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
69789. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
69790. DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
69791. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
69792. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
69793. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
69794. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
69795. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
69796. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
69797. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
69798. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
69799. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
69800. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
69801. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
69802. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
69803. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
69804. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
69805. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
69806. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
69807. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
69808. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
69809. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
69810. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
69811. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
69812. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
69813. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
69814. DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
69815. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
69816. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
69817. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
69818. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
69819. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
69820. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
69821. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
69822. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
69823. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
69824. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
69825. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
69826. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
69827. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
69828. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
69829. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
69830. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
69831. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
69832. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
69833. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
69834. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
69835. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
69836. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
69837. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
69838. DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
69839. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0_MASK
69840. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
69841. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0_MASK
69842. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
69843. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0_MASK
69844. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
69845. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0_MASK
69846. DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
69847. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10_MASK
69848. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
69849. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10_MASK
69850. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
69851. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10_MASK
69852. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
69853. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10_MASK
69854. DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
69855. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11_MASK
69856. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
69857. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11_MASK
69858. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
69859. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11_MASK
69860. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
69861. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11_MASK
69862. DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
69863. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12_MASK
69864. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
69865. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12_MASK
69866. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
69867. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12_MASK
69868. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
69869. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12_MASK
69870. DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
69871. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1_MASK
69872. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
69873. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1_MASK
69874. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
69875. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1_MASK
69876. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
69877. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1_MASK
69878. DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
69879. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2_MASK
69880. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
69881. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2_MASK
69882. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
69883. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2_MASK
69884. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
69885. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2_MASK
69886. DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
69887. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3_MASK
69888. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
69889. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3_MASK
69890. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
69891. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3_MASK
69892. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
69893. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3_MASK
69894. DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
69895. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4_MASK
69896. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
69897. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4_MASK
69898. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
69899. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4_MASK
69900. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
69901. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4_MASK
69902. DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
69903. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5_MASK
69904. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
69905. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5_MASK
69906. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
69907. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5_MASK
69908. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
69909. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5_MASK
69910. DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
69911. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6_MASK
69912. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
69913. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6_MASK
69914. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
69915. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6_MASK
69916. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
69917. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6_MASK
69918. DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
69919. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7_MASK
69920. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
69921. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7_MASK
69922. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
69923. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7_MASK
69924. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
69925. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7_MASK
69926. DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
69927. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8_MASK
69928. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
69929. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8_MASK
69930. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
69931. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8_MASK
69932. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
69933. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8_MASK
69934. DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
69935. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9_MASK
69936. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
69937. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9_MASK
69938. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
69939. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9_MASK
69940. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
69941. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9_MASK
69942. DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
69943. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
69944. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
69945. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
69946. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
69947. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
69948. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
69949. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
69950. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
69951. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
69952. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
69953. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
69954. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
69955. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
69956. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
69957. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
69958. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
69959. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
69960. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
69961. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
69962. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
69963. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
69964. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
69965. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
69966. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
69967. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
69968. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
69969. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
69970. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
69971. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
69972. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
69973. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
69974. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
69975. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
69976. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
69977. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
69978. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
69979. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
69980. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
69981. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
69982. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
69983. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
69984. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
69985. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
69986. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
69987. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
69988. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
69989. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
69990. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
69991. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
69992. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
69993. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
69994. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
69995. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
69996. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
69997. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
69998. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
69999. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
70000. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
70001. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
70002. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
70003. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
70004. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
70005. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
70006. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
70007. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
70008. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
70009. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
70010. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
70011. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
70012. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
70013. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
70014. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
70015. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
70016. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
70017. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
70018. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
70019. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
70020. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
70021. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
70022. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
70023. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
70024. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
70025. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
70026. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
70027. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
70028. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
70029. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
70030. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
70031. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
70032. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
70033. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
70034. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
70035. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
70036. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
70037. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
70038. DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
70039. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
70040. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
70041. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
70042. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
70043. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
70044. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
70045. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
70046. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
70047. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
70048. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
70049. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
70050. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
70051. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
70052. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
70053. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
70054. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
70055. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
70056. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
70057. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
70058. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
70059. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
70060. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
70061. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
70062. DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
70063. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
70064. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
70065. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
70066. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
70067. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
70068. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
70069. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
70070. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
70071. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
70072. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
70073. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
70074. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
70075. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
70076. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
70077. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
70078. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
70079. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
70080. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
70081. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
70082. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
70083. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
70084. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
70085. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
70086. DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
70087. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0_MASK
70088. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
70089. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0_MASK
70090. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
70091. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0_MASK
70092. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
70093. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0_MASK
70094. DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
70095. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10_MASK
70096. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
70097. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10_MASK
70098. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
70099. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10_MASK
70100. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
70101. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10_MASK
70102. DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
70103. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11_MASK
70104. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
70105. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11_MASK
70106. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
70107. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11_MASK
70108. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
70109. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11_MASK
70110. DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
70111. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12_MASK
70112. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
70113. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12_MASK
70114. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
70115. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12_MASK
70116. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
70117. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12_MASK
70118. DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
70119. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1_MASK
70120. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
70121. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1_MASK
70122. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
70123. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1_MASK
70124. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
70125. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1_MASK
70126. DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
70127. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2_MASK
70128. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
70129. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2_MASK
70130. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
70131. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2_MASK
70132. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
70133. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2_MASK
70134. DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
70135. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3_MASK
70136. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
70137. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3_MASK
70138. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
70139. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3_MASK
70140. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
70141. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3_MASK
70142. DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
70143. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4_MASK
70144. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
70145. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4_MASK
70146. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
70147. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4_MASK
70148. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
70149. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4_MASK
70150. DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
70151. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5_MASK
70152. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
70153. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5_MASK
70154. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
70155. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5_MASK
70156. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
70157. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5_MASK
70158. DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
70159. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6_MASK
70160. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
70161. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6_MASK
70162. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
70163. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6_MASK
70164. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
70165. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6_MASK
70166. DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
70167. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7_MASK
70168. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
70169. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7_MASK
70170. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
70171. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7_MASK
70172. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
70173. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7_MASK
70174. DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
70175. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8_MASK
70176. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
70177. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8_MASK
70178. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
70179. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8_MASK
70180. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
70181. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8_MASK
70182. DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
70183. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9_MASK
70184. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
70185. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9_MASK
70186. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
70187. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9_MASK
70188. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
70189. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9_MASK
70190. DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
70191. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
70192. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
70193. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
70194. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
70195. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
70196. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
70197. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
70198. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
70199. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
70200. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
70201. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
70202. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
70203. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
70204. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
70205. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
70206. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
70207. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
70208. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
70209. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
70210. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
70211. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
70212. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
70213. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
70214. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
70215. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
70216. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
70217. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
70218. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
70219. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
70220. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
70221. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
70222. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
70223. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
70224. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
70225. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
70226. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
70227. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
70228. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
70229. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
70230. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
70231. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
70232. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
70233. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
70234. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
70235. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
70236. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
70237. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
70238. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
70239. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
70240. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
70241. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
70242. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
70243. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
70244. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
70245. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
70246. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
70247. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
70248. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
70249. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
70250. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
70251. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
70252. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
70253. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
70254. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
70255. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
70256. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
70257. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
70258. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
70259. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
70260. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
70261. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
70262. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
70263. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
70264. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
70265. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
70266. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
70267. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
70268. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
70269. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
70270. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
70271. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
70272. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
70273. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
70274. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
70275. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
70276. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
70277. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
70278. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
70279. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
70280. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
70281. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
70282. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
70283. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
70284. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
70285. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
70286. DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
70287. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
70288. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
70289. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
70290. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
70291. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
70292. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
70293. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
70294. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
70295. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
70296. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
70297. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
70298. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
70299. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
70300. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
70301. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
70302. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
70303. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
70304. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
70305. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
70306. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
70307. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
70308. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
70309. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
70310. DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
70311. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
70312. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
70313. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
70314. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
70315. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
70316. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
70317. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
70318. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
70319. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
70320. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
70321. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
70322. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
70323. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
70324. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
70325. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
70326. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
70327. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
70328. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
70329. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
70330. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
70331. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
70332. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
70333. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
70334. DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
70335. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0_MASK
70336. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
70337. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0_MASK
70338. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
70339. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0_MASK
70340. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
70341. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0_MASK
70342. DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
70343. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10_MASK
70344. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
70345. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10_MASK
70346. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
70347. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10_MASK
70348. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
70349. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10_MASK
70350. DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
70351. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11_MASK
70352. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
70353. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11_MASK
70354. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
70355. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11_MASK
70356. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
70357. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11_MASK
70358. DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
70359. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12_MASK
70360. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
70361. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12_MASK
70362. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
70363. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12_MASK
70364. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
70365. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12_MASK
70366. DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
70367. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1_MASK
70368. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
70369. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1_MASK
70370. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
70371. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1_MASK
70372. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
70373. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1_MASK
70374. DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
70375. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2_MASK
70376. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
70377. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2_MASK
70378. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
70379. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2_MASK
70380. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
70381. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2_MASK
70382. DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
70383. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3_MASK
70384. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
70385. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3_MASK
70386. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
70387. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3_MASK
70388. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
70389. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3_MASK
70390. DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
70391. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4_MASK
70392. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
70393. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4_MASK
70394. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
70395. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4_MASK
70396. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
70397. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4_MASK
70398. DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
70399. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5_MASK
70400. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
70401. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5_MASK
70402. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
70403. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5_MASK
70404. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
70405. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5_MASK
70406. DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
70407. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6_MASK
70408. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
70409. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6_MASK
70410. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
70411. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6_MASK
70412. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
70413. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6_MASK
70414. DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
70415. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7_MASK
70416. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
70417. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7_MASK
70418. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
70419. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7_MASK
70420. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
70421. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7_MASK
70422. DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
70423. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8_MASK
70424. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
70425. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8_MASK
70426. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
70427. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8_MASK
70428. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
70429. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8_MASK
70430. DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
70431. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9_MASK
70432. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
70433. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9_MASK
70434. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
70435. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9_MASK
70436. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
70437. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9_MASK
70438. DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
70439. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
70440. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
70441. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
70442. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
70443. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
70444. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
70445. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
70446. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
70447. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
70448. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
70449. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
70450. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
70451. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
70452. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
70453. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
70454. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
70455. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
70456. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
70457. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
70458. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
70459. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
70460. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
70461. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
70462. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
70463. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
70464. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
70465. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
70466. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
70467. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
70468. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
70469. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
70470. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
70471. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
70472. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
70473. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
70474. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
70475. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
70476. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
70477. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
70478. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
70479. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
70480. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
70481. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
70482. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
70483. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
70484. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
70485. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
70486. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
70487. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
70488. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
70489. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
70490. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
70491. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
70492. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
70493. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
70494. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
70495. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
70496. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
70497. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
70498. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
70499. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
70500. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
70501. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
70502. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
70503. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
70504. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
70505. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
70506. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
70507. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
70508. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
70509. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
70510. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
70511. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
70512. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
70513. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
70514. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
70515. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
70516. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
70517. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
70518. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
70519. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
70520. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
70521. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
70522. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
70523. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
70524. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
70525. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
70526. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
70527. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
70528. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
70529. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
70530. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
70531. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
70532. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
70533. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
70534. DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
70535. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
70536. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
70537. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
70538. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
70539. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
70540. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
70541. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
70542. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
70543. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
70544. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
70545. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
70546. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
70547. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
70548. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
70549. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
70550. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
70551. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
70552. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
70553. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
70554. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
70555. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
70556. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
70557. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
70558. DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
70559. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
70560. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
70561. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
70562. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
70563. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
70564. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
70565. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
70566. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
70567. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
70568. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
70569. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
70570. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
70571. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
70572. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
70573. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
70574. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
70575. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
70576. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
70577. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
70578. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
70579. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
70580. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
70581. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
70582. DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
70583. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0_MASK
70584. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
70585. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0_MASK
70586. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
70587. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0_MASK
70588. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
70589. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0_MASK
70590. DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
70591. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10_MASK
70592. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
70593. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10_MASK
70594. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
70595. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10_MASK
70596. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
70597. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10_MASK
70598. DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
70599. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11_MASK
70600. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
70601. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11_MASK
70602. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
70603. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11_MASK
70604. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
70605. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11_MASK
70606. DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
70607. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12_MASK
70608. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
70609. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12_MASK
70610. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
70611. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12_MASK
70612. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
70613. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12_MASK
70614. DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
70615. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1_MASK
70616. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
70617. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1_MASK
70618. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
70619. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1_MASK
70620. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
70621. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1_MASK
70622. DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
70623. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2_MASK
70624. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
70625. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2_MASK
70626. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
70627. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2_MASK
70628. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
70629. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2_MASK
70630. DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
70631. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3_MASK
70632. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
70633. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3_MASK
70634. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
70635. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3_MASK
70636. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
70637. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3_MASK
70638. DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
70639. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4_MASK
70640. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
70641. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4_MASK
70642. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
70643. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4_MASK
70644. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
70645. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4_MASK
70646. DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
70647. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5_MASK
70648. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
70649. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5_MASK
70650. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
70651. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5_MASK
70652. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
70653. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5_MASK
70654. DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
70655. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6_MASK
70656. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
70657. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6_MASK
70658. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
70659. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6_MASK
70660. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
70661. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6_MASK
70662. DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
70663. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7_MASK
70664. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
70665. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7_MASK
70666. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
70667. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7_MASK
70668. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
70669. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7_MASK
70670. DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
70671. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8_MASK
70672. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
70673. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8_MASK
70674. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
70675. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8_MASK
70676. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
70677. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8_MASK
70678. DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
70679. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9_MASK
70680. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
70681. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9_MASK
70682. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
70683. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9_MASK
70684. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
70685. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9_MASK
70686. DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
70687. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
70688. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
70689. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
70690. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
70691. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
70692. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
70693. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
70694. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
70695. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
70696. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
70697. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
70698. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
70699. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
70700. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
70701. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
70702. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
70703. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
70704. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
70705. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
70706. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
70707. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
70708. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
70709. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
70710. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
70711. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
70712. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
70713. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
70714. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
70715. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
70716. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
70717. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
70718. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
70719. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
70720. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
70721. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
70722. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
70723. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
70724. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
70725. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
70726. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
70727. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
70728. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
70729. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
70730. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
70731. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
70732. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
70733. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
70734. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
70735. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
70736. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
70737. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
70738. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
70739. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
70740. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
70741. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
70742. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
70743. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
70744. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
70745. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
70746. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
70747. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
70748. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
70749. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
70750. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
70751. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
70752. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
70753. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
70754. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
70755. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
70756. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
70757. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
70758. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
70759. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
70760. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
70761. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
70762. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
70763. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
70764. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
70765. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
70766. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
70767. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
70768. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
70769. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
70770. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
70771. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
70772. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
70773. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
70774. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
70775. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
70776. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
70777. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
70778. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
70779. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
70780. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
70781. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
70782. DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
70783. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
70784. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
70785. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
70786. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
70787. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
70788. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
70789. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
70790. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
70791. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
70792. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
70793. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
70794. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
70795. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
70796. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
70797. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
70798. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
70799. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
70800. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
70801. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
70802. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
70803. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
70804. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
70805. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
70806. DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
70807. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
70808. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
70809. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
70810. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
70811. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
70812. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
70813. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
70814. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
70815. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
70816. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
70817. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
70818. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
70819. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
70820. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
70821. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
70822. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
70823. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
70824. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
70825. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
70826. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
70827. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
70828. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
70829. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
70830. DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
70831. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0_MASK
70832. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
70833. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0_MASK
70834. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
70835. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0_MASK
70836. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
70837. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0_MASK
70838. DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
70839. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10_MASK
70840. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
70841. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10_MASK
70842. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
70843. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10_MASK
70844. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
70845. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10_MASK
70846. DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
70847. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11_MASK
70848. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
70849. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11_MASK
70850. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
70851. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11_MASK
70852. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
70853. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11_MASK
70854. DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
70855. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12_MASK
70856. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
70857. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12_MASK
70858. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
70859. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12_MASK
70860. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
70861. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12_MASK
70862. DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
70863. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1_MASK
70864. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
70865. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1_MASK
70866. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
70867. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1_MASK
70868. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
70869. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1_MASK
70870. DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
70871. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2_MASK
70872. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
70873. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2_MASK
70874. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
70875. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2_MASK
70876. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
70877. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2_MASK
70878. DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
70879. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3_MASK
70880. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
70881. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3_MASK
70882. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
70883. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3_MASK
70884. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
70885. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3_MASK
70886. DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
70887. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4_MASK
70888. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
70889. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4_MASK
70890. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
70891. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4_MASK
70892. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
70893. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4_MASK
70894. DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
70895. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5_MASK
70896. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
70897. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5_MASK
70898. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
70899. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5_MASK
70900. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
70901. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5_MASK
70902. DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
70903. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6_MASK
70904. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
70905. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6_MASK
70906. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
70907. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6_MASK
70908. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
70909. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6_MASK
70910. DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
70911. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7_MASK
70912. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
70913. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7_MASK
70914. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
70915. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7_MASK
70916. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
70917. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7_MASK
70918. DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
70919. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8_MASK
70920. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
70921. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8_MASK
70922. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
70923. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8_MASK
70924. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
70925. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8_MASK
70926. DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
70927. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9_MASK
70928. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
70929. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9_MASK
70930. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
70931. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9_MASK
70932. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
70933. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9_MASK
70934. DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
70935. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
70936. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
70937. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
70938. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
70939. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK
70940. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT
70941. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK
70942. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT
70943. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK
70944. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT
70945. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK
70946. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT
70947. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK
70948. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT
70949. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK
70950. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT
70951. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
70952. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
70953. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK
70954. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT
70955. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK
70956. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT
70957. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK
70958. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT
70959. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
70960. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
70961. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
70962. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
70963. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK
70964. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT
70965. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK
70966. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT
70967. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK
70968. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT
70969. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK
70970. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT
70971. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK
70972. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT
70973. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK
70974. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT
70975. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
70976. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
70977. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK
70978. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT
70979. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK
70980. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT
70981. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK
70982. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT
70983. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
70984. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
70985. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
70986. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
70987. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK
70988. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT
70989. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK
70990. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT
70991. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK
70992. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT
70993. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK
70994. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT
70995. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK
70996. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT
70997. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK
70998. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT
70999. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
71000. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
71001. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK
71002. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT
71003. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK
71004. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT
71005. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK
71006. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT
71007. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
71008. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
71009. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
71010. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
71011. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK
71012. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT
71013. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK
71014. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT
71015. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK
71016. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT
71017. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK
71018. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT
71019. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK
71020. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT
71021. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK
71022. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT
71023. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
71024. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
71025. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK
71026. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT
71027. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK
71028. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT
71029. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK
71030. DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT
71031. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
71032. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
71033. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
71034. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
71035. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK
71036. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT
71037. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
71038. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
71039. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
71040. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
71041. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK
71042. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT
71043. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
71044. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
71045. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
71046. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
71047. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK
71048. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT
71049. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
71050. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
71051. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
71052. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
71053. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK
71054. DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT
71055. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel_MASK
71056. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT
71057. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK
71058. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT
71059. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK
71060. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT
71061. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel_MASK
71062. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT
71063. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK
71064. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT
71065. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK
71066. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT
71067. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel_MASK
71068. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT
71069. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK
71070. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT
71071. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK
71072. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT
71073. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel_MASK
71074. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT
71075. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK
71076. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT
71077. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK
71078. DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT
71079. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0_MASK
71080. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
71081. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0_MASK
71082. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
71083. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0_MASK
71084. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
71085. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0_MASK
71086. DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
71087. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10_MASK
71088. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
71089. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10_MASK
71090. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
71091. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10_MASK
71092. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
71093. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10_MASK
71094. DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
71095. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11_MASK
71096. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
71097. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11_MASK
71098. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
71099. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11_MASK
71100. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
71101. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11_MASK
71102. DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
71103. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12_MASK
71104. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
71105. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12_MASK
71106. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
71107. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12_MASK
71108. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
71109. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12_MASK
71110. DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
71111. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1_MASK
71112. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
71113. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1_MASK
71114. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
71115. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1_MASK
71116. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
71117. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1_MASK
71118. DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
71119. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2_MASK
71120. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
71121. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2_MASK
71122. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
71123. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2_MASK
71124. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
71125. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2_MASK
71126. DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
71127. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3_MASK
71128. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
71129. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3_MASK
71130. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
71131. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3_MASK
71132. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
71133. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3_MASK
71134. DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
71135. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4_MASK
71136. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
71137. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4_MASK
71138. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
71139. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4_MASK
71140. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
71141. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4_MASK
71142. DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
71143. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5_MASK
71144. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
71145. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5_MASK
71146. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
71147. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5_MASK
71148. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
71149. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5_MASK
71150. DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
71151. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6_MASK
71152. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
71153. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6_MASK
71154. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
71155. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6_MASK
71156. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
71157. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6_MASK
71158. DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
71159. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7_MASK
71160. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
71161. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7_MASK
71162. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
71163. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7_MASK
71164. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
71165. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7_MASK
71166. DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
71167. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8_MASK
71168. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
71169. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8_MASK
71170. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
71171. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8_MASK
71172. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
71173. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8_MASK
71174. DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
71175. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9_MASK
71176. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
71177. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9_MASK
71178. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
71179. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9_MASK
71180. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
71181. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9_MASK
71182. DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
71183. DC_COM_CRC_CHECKSUM
71184. DC_COM_CRC_CHECKSUM_LATCHED
71185. DC_COM_CRC_CONTROL
71186. DC_COM_CRC_CONTROL_ACTIVE_DATA
71187. DC_COM_CRC_CONTROL_ALWAYS
71188. DC_COM_CRC_CONTROL_ENABLE
71189. DC_COM_CRC_CONTROL_FULL_FRAME
71190. DC_COM_CRC_CONTROL_WAIT
71191. DC_COM_DSC_TOP_CTL
71192. DC_COM_GPIO_CTRL
71193. DC_COM_GPIO_DEBOUNCE_COUNTER
71194. DC_COM_HSPI_CS_DC
71195. DC_COM_HSPI_WRITE_DATA_AB
71196. DC_COM_HSPI_WRITE_DATA_CD
71197. DC_COM_PIN_INPUT_DATA
71198. DC_COM_PIN_INPUT_ENABLE
71199. DC_COM_PIN_MISC_CONTROL
71200. DC_COM_PIN_OUTPUT_DATA
71201. DC_COM_PIN_OUTPUT_ENABLE
71202. DC_COM_PIN_OUTPUT_POLARITY
71203. DC_COM_PIN_OUTPUT_SELECT
71204. DC_COM_PIN_PM0_CONTROL
71205. DC_COM_PIN_PM0_DUTY_CYCLE
71206. DC_COM_PIN_PM1_CONTROL
71207. DC_COM_PIN_PM1_DUTY_CYCLE
71208. DC_COM_RG_UNDERFLOW
71209. DC_COM_SCRATCH_REGISTER_A
71210. DC_COM_SCRATCH_REGISTER_B
71211. DC_COM_SPI_CONTROL
71212. DC_COM_SPI_START_BYTE
71213. DC_CTRL1
71214. DC_CTRL2
71215. DC_CTRL3
71216. DC_CTRL4
71217. DC_CTRL5
71218. DC_CTRL6
71219. DC_CTRLFUNC
71220. DC_CTRL_DIS
71221. DC_CTRL_FLUSH_STATUS
71222. DC_CTRL_INV_MODE_FLUSH
71223. DC_CTRL_RGN_OP_INV
71224. DC_CTRL_RGN_OP_MSK
71225. DC_CURSOR_COLOR
71226. DC_CURSOR_X
71227. DC_CURSOR_Y
71228. DC_CURS_ST_OFFSET
71229. DC_DATACOUNT_MASK
71230. DC_DATAPORT
71231. DC_DBLBUF
71232. DC_DC8051_CFG_CSR_ACCESS_SEL
71233. DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK
71234. DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK
71235. DC_DC8051_CFG_EXT_DEV_0
71236. DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK
71237. DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT
71238. DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT
71239. DC_DC8051_CFG_EXT_DEV_1
71240. DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK
71241. DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT
71242. DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK
71243. DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK
71244. DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK
71245. DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT
71246. DC_DC8051_CFG_HOST_CMD_0
71247. DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK
71248. DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT
71249. DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK
71250. DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK
71251. DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
71252. DC_DC8051_CFG_HOST_CMD_1
71253. DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK
71254. DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK
71255. DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT
71256. DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK
71257. DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT
71258. DC_DC8051_CFG_LOCAL_GUID
71259. DC_DC8051_CFG_MODE
71260. DC_DC8051_CFG_RAM_ACCESS_CTRL
71261. DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK
71262. DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT
71263. DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK
71264. DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK
71265. DC_DC8051_CFG_RAM_ACCESS_RD_DATA
71266. DC_DC8051_CFG_RAM_ACCESS_SETUP
71267. DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK
71268. DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK
71269. DC_DC8051_CFG_RAM_ACCESS_STATUS
71270. DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK
71271. DC_DC8051_CFG_RAM_ACCESS_WR_DATA
71272. DC_DC8051_CFG_RST
71273. DC_DC8051_CFG_RST_CRAM_SMASK
71274. DC_DC8051_CFG_RST_DRAM_SMASK
71275. DC_DC8051_CFG_RST_IRAM_SMASK
71276. DC_DC8051_CFG_RST_M8051W_SMASK
71277. DC_DC8051_CFG_RST_SFR_SMASK
71278. DC_DC8051_DBG_ERR_INFO_SET_BY_8051
71279. DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK
71280. DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT
71281. DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK
71282. DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT
71283. DC_DC8051_ERR_CLR
71284. DC_DC8051_ERR_EN
71285. DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK
71286. DC_DC8051_ERR_FLG
71287. DC_DC8051_ERR_FLG_CRAM_MBE_SMASK
71288. DC_DC8051_ERR_FLG_CRAM_SBE_SMASK
71289. DC_DC8051_ERR_FLG_DRAM_MBE_SMASK
71290. DC_DC8051_ERR_FLG_DRAM_SBE_SMASK
71291. DC_DC8051_ERR_FLG_INVALID_CSR_ADDR_SMASK
71292. DC_DC8051_ERR_FLG_IRAM_MBE_SMASK
71293. DC_DC8051_ERR_FLG_IRAM_SBE_SMASK
71294. DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK
71295. DC_DC8051_ERR_FLG_SET_BY_8051_SMASK
71296. DC_DC8051_ERR_FLG_UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES_SMASK
71297. DC_DC8051_STS_CUR_STATE
71298. DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK
71299. DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT
71300. DC_DC8051_STS_CUR_STATE_PORT_MASK
71301. DC_DC8051_STS_CUR_STATE_PORT_SHIFT
71302. DC_DC8051_STS_LOCAL_FM_SECURITY
71303. DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK
71304. DC_DC8051_STS_REMOTE_FM_SECURITY
71305. DC_DC8051_STS_REMOTE_GUID
71306. DC_DC8051_STS_REMOTE_NODE_TYPE
71307. DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK
71308. DC_DC8051_STS_REMOTE_PORT_NO
71309. DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK
71310. DC_DDBGMODIN_ACK
71311. DC_DDBGMODIN_ACK_1NAK
71312. DC_DDBGMODIN_ACK_NAK
71313. DC_DDBGMODOUT_ACK_NYET
71314. DC_DDBGMODOUT_ACK_NYET_1NAK
71315. DC_DDBGMODOUT_ACK_NYET_NAK
71316. DC_DDC_TYPES_H_
71317. DC_DEBUG
71318. DC_DECODE_INTERRUPT_POLARITY
71319. DC_DECODE_PP_CLOCK_TYPE
71320. DC_DEFAULT_LOG_MASK
71321. DC_DEPTH_MICRO_TILING
71322. DC_DEVEN
71323. DC_DFIFO_DIAG
71324. DC_DFLT
71325. DC_DFWT
71326. DC_DIFFERED_DELAY
71327. DC_DISABLE
71328. DC_DISPLAY_CFG
71329. DC_DISPLAY_CFG_A18M
71330. DC_DISPLAY_CFG_A20M
71331. DC_DISPLAY_CFG_DCEN
71332. DC_DISPLAY_CFG_DISP_MODE_16BPP
71333. DC_DISPLAY_CFG_DISP_MODE_24BPP
71334. DC_DISPLAY_CFG_DISP_MODE_8BPP
71335. DC_DISPLAY_CFG_GDEN
71336. DC_DISPLAY_CFG_PALB
71337. DC_DISPLAY_CFG_TGEN
71338. DC_DISPLAY_CFG_TRUP
71339. DC_DISPLAY_CFG_VDEN
71340. DC_DISPLAY_CFG_VISL
71341. DC_DISPLAY_MICRO_TILING
71342. DC_DISP_ACTIVE
71343. DC_DISP_BACK_PORCH
71344. DC_DISP_BLEND_BACKGROUND_COLOR
71345. DC_DISP_BLEND_CURSOR_CONTROL
71346. DC_DISP_BORDER_COLOR
71347. DC_DISP_COLOR_KEY0_LOWER
71348. DC_DISP_COLOR_KEY0_UPPER
71349. DC_DISP_COLOR_KEY1_LOWER
71350. DC_DISP_COLOR_KEY1_UPPER
71351. DC_DISP_CONF1
71352. DC_DISP_CONF2
71353. DC_DISP_CORE_SOR_SET_CONTROL
71354. DC_DISP_CURSOR_BACKGROUND
71355. DC_DISP_CURSOR_FOREGROUND
71356. DC_DISP_CURSOR_POSITION
71357. DC_DISP_CURSOR_POSITION_NS
71358. DC_DISP_CURSOR_START_ADDR
71359. DC_DISP_CURSOR_START_ADDR_HI
71360. DC_DISP_CURSOR_START_ADDR_NS
71361. DC_DISP_DAC_CRT_CTRL
71362. DC_DISP_DATA_ENABLE_OPTIONS
71363. DC_DISP_DC_MCCIF_FIFOCTRL
71364. DC_DISP_DC_PIXEL_COUNT
71365. DC_DISP_DISP_CLOCK_CONTROL
71366. DC_DISP_DISP_COLOR_CONTROL
71367. DC_DISP_DISP_INTERFACE_CONTROL
71368. DC_DISP_DISP_MEM_HIGH_PRIORITY
71369. DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
71370. DC_DISP_DISP_MISC_CONTROL
71371. DC_DISP_DISP_SIGNAL_OPTIONS0
71372. DC_DISP_DISP_SIGNAL_OPTIONS1
71373. DC_DISP_DISP_TIMING_OPTIONS
71374. DC_DISP_DISP_WIN_OPTIONS
71375. DC_DISP_DI_CONTROL
71376. DC_DISP_FRONT_PORCH
71377. DC_DISP_H_PULSE0_CONTROL
71378. DC_DISP_H_PULSE0_POSITION_A
71379. DC_DISP_H_PULSE0_POSITION_B
71380. DC_DISP_H_PULSE0_POSITION_C
71381. DC_DISP_H_PULSE0_POSITION_D
71382. DC_DISP_H_PULSE1_CONTROL
71383. DC_DISP_H_PULSE1_POSITION_A
71384. DC_DISP_H_PULSE1_POSITION_B
71385. DC_DISP_H_PULSE1_POSITION_C
71386. DC_DISP_H_PULSE1_POSITION_D
71387. DC_DISP_H_PULSE2_CONTROL
71388. DC_DISP_H_PULSE2_POSITION_A
71389. DC_DISP_H_PULSE2_POSITION_B
71390. DC_DISP_H_PULSE2_POSITION_C
71391. DC_DISP_H_PULSE2_POSITION_D
71392. DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER
71393. DC_DISP_INIT_SEQ_CONTROL
71394. DC_DISP_INTERLACE_CONTROL
71395. DC_DISP_LCD_SPI_OPTIONS
71396. DC_DISP_M0_CONTROL
71397. DC_DISP_M1_CONTROL
71398. DC_DISP_MCCIF_DISPLAY0A_HYST
71399. DC_DISP_MCCIF_DISPLAY0B_HYST
71400. DC_DISP_MCCIF_DISPLAY1A_HYST
71401. DC_DISP_MCCIF_DISPLAY1B_HYST
71402. DC_DISP_PP_CONTROL
71403. DC_DISP_PP_SELECT_A
71404. DC_DISP_PP_SELECT_B
71405. DC_DISP_PP_SELECT_C
71406. DC_DISP_PP_SELECT_D
71407. DC_DISP_REF_TO_SYNC
71408. DC_DISP_SD_BL_CONTROL
71409. DC_DISP_SD_BL_PARAMETERS
71410. DC_DISP_SD_BL_TF
71411. DC_DISP_SD_CONTROL
71412. DC_DISP_SD_CSC_COEFF
71413. DC_DISP_SD_FLICKER_CONTROL
71414. DC_DISP_SD_HISTOGRAM
71415. DC_DISP_SD_HW_K_VALUES
71416. DC_DISP_SD_LUT
71417. DC_DISP_SD_MAN_K_VALUES
71418. DC_DISP_SERIAL_INTERFACE_OPTIONS
71419. DC_DISP_SHIFT_CLOCK_OPTIONS
71420. DC_DISP_SPI_INIT_SEQ_DATA_A
71421. DC_DISP_SPI_INIT_SEQ_DATA_B
71422. DC_DISP_SPI_INIT_SEQ_DATA_C
71423. DC_DISP_SPI_INIT_SEQ_DATA_D
71424. DC_DISP_SYNC_WIDTH
71425. DC_DISP_V_PULSE0_CONTROL
71426. DC_DISP_V_PULSE0_POSITION_A
71427. DC_DISP_V_PULSE0_POSITION_B
71428. DC_DISP_V_PULSE0_POSITION_C
71429. DC_DISP_V_PULSE1_CONTROL
71430. DC_DISP_V_PULSE1_POSITION_A
71431. DC_DISP_V_PULSE1_POSITION_B
71432. DC_DISP_V_PULSE1_POSITION_C
71433. DC_DISP_V_PULSE2_CONTROL
71434. DC_DISP_V_PULSE2_POSITION_A
71435. DC_DISP_V_PULSE3_CONTROL
71436. DC_DISP_V_PULSE3_POSITION_A
71437. DC_DMABURSTCOUNT
71438. DC_DMACLKON
71439. DC_DMACMD
71440. DC_DMACONF
71441. DC_DMAEP
71442. DC_DMAHW
71443. DC_DMAINTEN
71444. DC_DMAINTREASON
71445. DC_DMATXCOUNT
71446. DC_DMCUB_INT_TYPE
71447. DC_DMCUB_TIMER_WINDOW
71448. DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK
71449. DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT
71450. DC_DP_INFOFRAME_TYPE_PPS
71451. DC_DP_TYPES_H
71452. DC_DSC_H_
71453. DC_DSEN
71454. DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK
71455. DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT
71456. DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK
71457. DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT
71458. DC_DVODATA_CONFIG__VIP_MUX_EN_MASK
71459. DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT
71460. DC_DV_ACC
71461. DC_DV_ACCESS
71462. DC_DV_CTL
71463. DC_DV_CTL_CLEAR_DV_RAM
71464. DC_DV_CTL_DV_LINE_SIZE
71465. DC_DV_CTL_DV_LINE_SIZE_1K
71466. DC_DV_CTL_DV_LINE_SIZE_2K
71467. DC_DV_CTL_DV_LINE_SIZE_4K
71468. DC_DV_CTL_DV_LINE_SIZE_8K
71469. DC_DV_TOP
71470. DC_DV_TOP_DV_TOP_EN
71471. DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK
71472. DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT
71473. DC_EDC_RESTORE_CNT__COUNT_ME1_MASK
71474. DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT
71475. DC_EDC_STATE_CNT__COUNT_ME1_MASK
71476. DC_EDC_STATE_CNT__COUNT_ME1__SHIFT
71477. DC_EDID_BLOCK_SIZE
71478. DC_EDID_CONNECTOR_ANALOG
71479. DC_EDID_CONNECTOR_DIGITAL
71480. DC_EDID_CONNECTOR_DISPLAYPORT
71481. DC_EDID_CONNECTOR_DVI
71482. DC_EDID_CONNECTOR_HDMIA
71483. DC_EDID_CONNECTOR_MDDI
71484. DC_EDID_CONNECTOR_UNKNOWN
71485. DC_EE1
71486. DC_EE2
71487. DC_ENDPIDX
71488. DC_ENDPTYP_BULK
71489. DC_ENDPTYP_INTERRUPT
71490. DC_ENDPTYP_ISOC
71491. DC_ENTRIES
71492. DC_EP0SETUP
71493. DC_EPDIR
71494. DC_EPENABLE
71495. DC_EPINDEX
71496. DC_EPMAXPKTSZ
71497. DC_EPTYPE
71498. DC_ERR
71499. DC_ERROR
71500. DC_ERROR_UNEXPECTED
71501. DC_EVT_EOF
71502. DC_EVT_EOFIELD
71503. DC_EVT_EOL
71504. DC_EVT_NEW_ADDR
71505. DC_EVT_NEW_ADDR_R_0
71506. DC_EVT_NEW_ADDR_R_1
71507. DC_EVT_NEW_ADDR_W_0
71508. DC_EVT_NEW_ADDR_W_1
71509. DC_EVT_NEW_CHAN
71510. DC_EVT_NEW_CHAN_R_0
71511. DC_EVT_NEW_CHAN_R_1
71512. DC_EVT_NEW_CHAN_W_0
71513. DC_EVT_NEW_CHAN_W_1
71514. DC_EVT_NEW_DATA
71515. DC_EVT_NEW_DATA_R_0
71516. DC_EVT_NEW_DATA_R_1
71517. DC_EVT_NEW_DATA_W_0
71518. DC_EVT_NEW_DATA_W_1
71519. DC_EVT_NF
71520. DC_EVT_NFIELD
71521. DC_EVT_NL
71522. DC_EXCEED_DONGLE_CAP
71523. DC_FAIL_ATTACH_SURFACES
71524. DC_FAIL_BANDWIDTH_VALIDATE
71525. DC_FAIL_CLK_BELOW_CFG_REQUIRED
71526. DC_FAIL_CLK_BELOW_MIN
71527. DC_FAIL_CLK_EXCEED_MAX
71528. DC_FAIL_CONTROLLER_VALIDATE
71529. DC_FAIL_DETACH_SURFACES
71530. DC_FAIL_DP_LINK_TRAINING
71531. DC_FAIL_DSC_VALIDATE
71532. DC_FAIL_ENC_VALIDATE
71533. DC_FAIL_SCALING
71534. DC_FAIL_SURFACE_VALIDATE
71535. DC_FAIL_UNSUPPORTED_1
71536. DC_FBC_MASK
71537. DC_FB_ACTIVE
71538. DC_FB_ST_OFFSET
71539. DC_FEATURE_MASK
71540. DC_FILTER_VAL
71541. DC_FILT_COEFF1
71542. DC_FILT_COEFF2
71543. DC_FLINE
71544. DC_FP_H_TIMING
71545. DC_FP_V_TIMING
71546. DC_FRAMENUM
71547. DC_GCFG_CH4S
71548. DC_GCFG_CIM_MASK
71549. DC_GCFG_CIM_POS
71550. DC_GCFG_CKWR
71551. DC_GCFG_CMPE
71552. DC_GCFG_CURE
71553. DC_GCFG_DAC_RS_MASK
71554. DC_GCFG_DAC_RS_POS
71555. DC_GCFG_DCLK_DIV_1
71556. DC_GCFG_DCLK_MASK
71557. DC_GCFG_DDCK
71558. DC_GCFG_DECE
71559. DC_GCFG_DFHPEL_MASK
71560. DC_GCFG_DFHPEL_POS
71561. DC_GCFG_DFHPSL_MASK
71562. DC_GCFG_DFHPSL_POS
71563. DC_GCFG_DFLE
71564. DC_GCFG_DIAG
71565. DC_GCFG_DPCK
71566. DC_GCFG_FDTY
71567. DC_GCFG_LDBL
71568. DC_GCFG_PLNO
71569. DC_GCFG_PPC
71570. DC_GCFG_RTPM
71571. DC_GCFG_SSLC
71572. DC_GCFG_VCLK_DIV
71573. DC_GCFG_VIDE
71574. DC_GCFG_VRDY
71575. DC_GEN
71576. DC_GENERAL_CFG
71577. DC_GENERAL_CFG_CMPE
71578. DC_GENERAL_CFG_CURE
71579. DC_GENERAL_CFG_DECE
71580. DC_GENERAL_CFG_DFHPEL_SHIFT
71581. DC_GENERAL_CFG_DFHPSL_SHIFT
71582. DC_GENERAL_CFG_DFLE
71583. DC_GENERAL_CFG_FDTY
71584. DC_GENERAL_CFG_ICNE
71585. DC_GENERAL_CFG_VDSE
71586. DC_GENERAL_CFG_VGAE
71587. DC_GENERAL_CFG_VIDE
71588. DC_GENERAL_CFG_YUVM
71589. DC_GENERICA__GENERICA_EN_MASK
71590. DC_GENERICA__GENERICA_EN__SHIFT
71591. DC_GENERICA__GENERICA_SEL_MASK
71592. DC_GENERICA__GENERICA_SEL__SHIFT
71593. DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK
71594. DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT
71595. DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK
71596. DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT
71597. DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK
71598. DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT
71599. DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK
71600. DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT
71601. DC_GENERICB__GENERICB_EN_MASK
71602. DC_GENERICB__GENERICB_EN__SHIFT
71603. DC_GENERICB__GENERICB_SEL_MASK
71604. DC_GENERICB__GENERICB_SEL__SHIFT
71605. DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK
71606. DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT
71607. DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK
71608. DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT
71609. DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK
71610. DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT
71611. DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK
71612. DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT
71613. DC_GENLK_CTL
71614. DC_GENLK_CTL_ALPHA_FLICK_EN
71615. DC_GENLK_CTL_FLICK_EN
71616. DC_GENLK_CTL_FLICK_SEL_MASK
71617. DC_GENLK_CTL_GENLK_EN
71618. DC_GEN_SYNC_1_6_SYNC
71619. DC_GEN_SYNC_PRIORITY_1
71620. DC_GFX_PITCH
71621. DC_GFX_SCALE
71622. DC_GLINTENA
71623. DC_GLIU0_MEM_OFFSET
71624. DC_GOSUSP
71625. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK
71626. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT
71627. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK
71628. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT
71629. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK
71630. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT
71631. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK
71632. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT
71633. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK
71634. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT
71635. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK
71636. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT
71637. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK
71638. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT
71639. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK
71640. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT
71641. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK
71642. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT
71643. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK
71644. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT
71645. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK
71646. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT
71647. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK
71648. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT
71649. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK
71650. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT
71651. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK
71652. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT
71653. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK
71654. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT
71655. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK
71656. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT
71657. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK
71658. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT
71659. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK
71660. DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT
71661. DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK
71662. DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT
71663. DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK
71664. DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT
71665. DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK
71666. DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT
71667. DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL_MASK
71668. DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL__SHIFT
71669. DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN_MASK
71670. DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN__SHIFT
71671. DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL_MASK
71672. DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL__SHIFT
71673. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK
71674. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT
71675. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_0P9_MASK
71676. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_0P9__SHIFT
71677. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_1P1_MASK
71678. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_1P1__SHIFT
71679. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_0P9_MASK
71680. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_0P9__SHIFT
71681. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_1P1_MASK
71682. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_1P1__SHIFT
71683. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK
71684. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT
71685. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_0P9_MASK
71686. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_0P9__SHIFT
71687. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_1P1_MASK
71688. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_1P1__SHIFT
71689. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_0P9_MASK
71690. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_0P9__SHIFT
71691. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_1P1_MASK
71692. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_1P1__SHIFT
71693. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK
71694. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT
71695. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_0P9_MASK
71696. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_0P9__SHIFT
71697. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_1P1_MASK
71698. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_1P1__SHIFT
71699. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_0P9_MASK
71700. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_0P9__SHIFT
71701. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_1P1_MASK
71702. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_1P1__SHIFT
71703. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK
71704. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT
71705. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_0P9_MASK
71706. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_0P9__SHIFT
71707. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_1P1_MASK
71708. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_1P1__SHIFT
71709. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_0P9_MASK
71710. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_0P9__SHIFT
71711. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_1P1_MASK
71712. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_1P1__SHIFT
71713. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK
71714. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT
71715. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_0P9_MASK
71716. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_0P9__SHIFT
71717. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_1P1_MASK
71718. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_1P1__SHIFT
71719. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_0P9_MASK
71720. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_0P9__SHIFT
71721. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_1P1_MASK
71722. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_1P1__SHIFT
71723. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK
71724. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT
71725. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_0P9_MASK
71726. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_0P9__SHIFT
71727. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_1P1_MASK
71728. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_1P1__SHIFT
71729. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_0P9_MASK
71730. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_0P9__SHIFT
71731. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_1P1_MASK
71732. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_1P1__SHIFT
71733. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK
71734. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT
71735. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL_MASK
71736. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL__SHIFT
71737. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK
71738. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT
71739. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK
71740. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT
71741. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK
71742. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT
71743. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK
71744. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT
71745. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK
71746. DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT
71747. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK
71748. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT
71749. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK
71750. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT
71751. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK
71752. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT
71753. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK
71754. DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT
71755. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_COMPSEL_MASK
71756. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_COMPSEL__SHIFT
71757. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN_MASK
71758. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN__SHIFT
71759. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL_MASK
71760. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL__SHIFT
71761. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN_MASK
71762. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN__SHIFT
71763. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE_MASK
71764. DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE__SHIFT
71765. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK
71766. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT
71767. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL_MASK
71768. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL__SHIFT
71769. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK
71770. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT
71771. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK
71772. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT
71773. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK
71774. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT
71775. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK
71776. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT
71777. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK
71778. DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT
71779. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX1_BIASCRTEN_MASK
71780. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX1_BIASCRTEN__SHIFT
71781. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX2_BIASCRTEN_MASK
71782. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX2_BIASCRTEN__SHIFT
71783. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX3_BIASCRTEN_MASK
71784. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX3_BIASCRTEN__SHIFT
71785. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX4_BIASCRTEN_MASK
71786. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX4_BIASCRTEN__SHIFT
71787. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX5_BIASCRTEN_MASK
71788. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX5_BIASCRTEN__SHIFT
71789. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX6_BIASCRTEN_MASK
71790. DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX6_BIASCRTEN__SHIFT
71791. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK
71792. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT
71793. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK
71794. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT
71795. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK
71796. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT
71797. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK
71798. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT
71799. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK
71800. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT
71801. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK
71802. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT
71803. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK
71804. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT
71805. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK
71806. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT
71807. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK
71808. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT
71809. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK
71810. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT
71811. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK
71812. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT
71813. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK
71814. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT
71815. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK
71816. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT
71817. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK
71818. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT
71819. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK
71820. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT
71821. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK
71822. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT
71823. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK
71824. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT
71825. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK
71826. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT
71827. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK
71828. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT
71829. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK
71830. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT
71831. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK
71832. DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT
71833. DC_GPIO_AUX_CTRL_2__DC_IO_AUX1_SPARE_MASK
71834. DC_GPIO_AUX_CTRL_2__DC_IO_AUX1_SPARE__SHIFT
71835. DC_GPIO_AUX_CTRL_2__DC_IO_AUX2_SPARE_MASK
71836. DC_GPIO_AUX_CTRL_2__DC_IO_AUX2_SPARE__SHIFT
71837. DC_GPIO_AUX_CTRL_2__DC_IO_AUX3_SPARE_MASK
71838. DC_GPIO_AUX_CTRL_2__DC_IO_AUX3_SPARE__SHIFT
71839. DC_GPIO_AUX_CTRL_2__DC_IO_AUX4_SPARE_MASK
71840. DC_GPIO_AUX_CTRL_2__DC_IO_AUX4_SPARE__SHIFT
71841. DC_GPIO_AUX_CTRL_2__DC_IO_AUX5_SPARE_MASK
71842. DC_GPIO_AUX_CTRL_2__DC_IO_AUX5_SPARE__SHIFT
71843. DC_GPIO_AUX_CTRL_2__DC_IO_AUX6_SPARE_MASK
71844. DC_GPIO_AUX_CTRL_2__DC_IO_AUX6_SPARE__SHIFT
71845. DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK
71846. DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT
71847. DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK
71848. DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT
71849. DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK
71850. DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT
71851. DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK
71852. DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT
71853. DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK
71854. DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT
71855. DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK
71856. DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT
71857. DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK
71858. DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT
71859. DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK
71860. DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT
71861. DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK
71862. DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT
71863. DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK
71864. DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT
71865. DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK
71866. DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT
71867. DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK
71868. DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT
71869. DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK
71870. DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT
71871. DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK
71872. DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT
71873. DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK
71874. DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT
71875. DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK
71876. DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT
71877. DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK
71878. DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT
71879. DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK
71880. DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT
71881. DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK
71882. DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT
71883. DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK
71884. DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT
71885. DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK
71886. DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT
71887. DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK
71888. DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT
71889. DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK
71890. DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT
71891. DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK
71892. DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT
71893. DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK
71894. DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT
71895. DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK
71896. DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT
71897. DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK
71898. DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT
71899. DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK
71900. DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT
71901. DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK
71902. DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT
71903. DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK
71904. DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT
71905. DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK
71906. DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT
71907. DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK
71908. DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT
71909. DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK
71910. DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT
71911. DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK
71912. DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT
71913. DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK
71914. DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT
71915. DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK
71916. DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT
71917. DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK
71918. DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT
71919. DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK
71920. DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT
71921. DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK
71922. DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT
71923. DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK
71924. DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT
71925. DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK
71926. DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT
71927. DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK
71928. DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT
71929. DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK
71930. DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT
71931. DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK
71932. DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT
71933. DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK
71934. DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT
71935. DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK
71936. DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT
71937. DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK
71938. DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT
71939. DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK
71940. DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT
71941. DC_GPIO_AUX_CTRL_6__AUX1_PAD_RXSEL_MASK
71942. DC_GPIO_AUX_CTRL_6__AUX1_PAD_RXSEL__SHIFT
71943. DC_GPIO_AUX_CTRL_6__AUX2_PAD_RXSEL_MASK
71944. DC_GPIO_AUX_CTRL_6__AUX2_PAD_RXSEL__SHIFT
71945. DC_GPIO_AUX_CTRL_6__AUX3_PAD_RXSEL_MASK
71946. DC_GPIO_AUX_CTRL_6__AUX3_PAD_RXSEL__SHIFT
71947. DC_GPIO_AUX_CTRL_6__AUX4_PAD_RXSEL_MASK
71948. DC_GPIO_AUX_CTRL_6__AUX4_PAD_RXSEL__SHIFT
71949. DC_GPIO_AUX_CTRL_6__AUX5_PAD_RXSEL_MASK
71950. DC_GPIO_AUX_CTRL_6__AUX5_PAD_RXSEL__SHIFT
71951. DC_GPIO_AUX_CTRL_6__AUX6_PAD_RXSEL_MASK
71952. DC_GPIO_AUX_CTRL_6__AUX6_PAD_RXSEL__SHIFT
71953. DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK
71954. DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT
71955. DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK
71956. DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT
71957. DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK
71958. DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT
71959. DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK
71960. DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT
71961. DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK
71962. DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT
71963. DC_GPIO_DDC1_MASK__AUX1_POL_MASK
71964. DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT
71965. DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK
71966. DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT
71967. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK
71968. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT
71969. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK
71970. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT
71971. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV1_MASK
71972. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV1__SHIFT
71973. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK
71974. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT
71975. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK
71976. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT
71977. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK
71978. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT
71979. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK
71980. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT
71981. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV1_MASK
71982. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV1__SHIFT
71983. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK
71984. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT
71985. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK
71986. DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT
71987. DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK
71988. DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT
71989. DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK
71990. DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT
71991. DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK
71992. DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT
71993. DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK
71994. DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT
71995. DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK
71996. DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT
71997. DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK
71998. DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT
71999. DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK
72000. DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT
72001. DC_GPIO_DDC2_MASK__AUX2_POL_MASK
72002. DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT
72003. DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK
72004. DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT
72005. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK
72006. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT
72007. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK
72008. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT
72009. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV1_MASK
72010. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV1__SHIFT
72011. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK
72012. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT
72013. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK
72014. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT
72015. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK
72016. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT
72017. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK
72018. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT
72019. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV1_MASK
72020. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV1__SHIFT
72021. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK
72022. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT
72023. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK
72024. DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT
72025. DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK
72026. DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT
72027. DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK
72028. DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT
72029. DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK
72030. DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT
72031. DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK
72032. DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT
72033. DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK
72034. DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT
72035. DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK
72036. DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT
72037. DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK
72038. DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT
72039. DC_GPIO_DDC3_MASK__AUX3_POL_MASK
72040. DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT
72041. DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK
72042. DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT
72043. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK
72044. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT
72045. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK
72046. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT
72047. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV1_MASK
72048. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV1__SHIFT
72049. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK
72050. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT
72051. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK
72052. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT
72053. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK
72054. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT
72055. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK
72056. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT
72057. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV1_MASK
72058. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV1__SHIFT
72059. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK
72060. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT
72061. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK
72062. DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT
72063. DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK
72064. DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT
72065. DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK
72066. DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT
72067. DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK
72068. DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT
72069. DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK
72070. DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT
72071. DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK
72072. DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT
72073. DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK
72074. DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT
72075. DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK
72076. DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT
72077. DC_GPIO_DDC4_MASK__AUX4_POL_MASK
72078. DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT
72079. DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK
72080. DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT
72081. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK
72082. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT
72083. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK
72084. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT
72085. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV1_MASK
72086. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV1__SHIFT
72087. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK
72088. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT
72089. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK
72090. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT
72091. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK
72092. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT
72093. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK
72094. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT
72095. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV1_MASK
72096. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV1__SHIFT
72097. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK
72098. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT
72099. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK
72100. DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT
72101. DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK
72102. DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT
72103. DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK
72104. DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT
72105. DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK
72106. DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT
72107. DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK
72108. DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT
72109. DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK
72110. DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT
72111. DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK
72112. DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT
72113. DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK
72114. DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT
72115. DC_GPIO_DDC5_MASK__AUX5_POL_MASK
72116. DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT
72117. DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK
72118. DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT
72119. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK
72120. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT
72121. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK
72122. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT
72123. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV1_MASK
72124. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV1__SHIFT
72125. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK
72126. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT
72127. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK
72128. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT
72129. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK
72130. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT
72131. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK
72132. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT
72133. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV1_MASK
72134. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV1__SHIFT
72135. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK
72136. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT
72137. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK
72138. DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT
72139. DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK
72140. DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT
72141. DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK
72142. DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT
72143. DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK
72144. DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT
72145. DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK
72146. DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT
72147. DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK
72148. DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT
72149. DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK
72150. DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT
72151. DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK
72152. DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT
72153. DC_GPIO_DDC6_MASK__AUX6_POL_MASK
72154. DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT
72155. DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK
72156. DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT
72157. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK
72158. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT
72159. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK
72160. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT
72161. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV1_MASK
72162. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV1__SHIFT
72163. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK
72164. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT
72165. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK
72166. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT
72167. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK
72168. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT
72169. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK
72170. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT
72171. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV1_MASK
72172. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV1__SHIFT
72173. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK
72174. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT
72175. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK
72176. DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT
72177. DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK
72178. DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT
72179. DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK
72180. DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT
72181. DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK
72182. DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT
72183. DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK
72184. DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT
72185. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK
72186. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT
72187. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK
72188. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT
72189. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_BIASCRTEN_MASK
72190. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_BIASCRTEN__SHIFT
72191. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_COMPSEL_MASK
72192. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_COMPSEL__SHIFT
72193. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL0P9_MASK
72194. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL0P9__SHIFT
72195. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL1P1_MASK
72196. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL1P1__SHIFT
72197. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL_MASK
72198. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL__SHIFT
72199. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RESBIASEN_MASK
72200. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RESBIASEN__SHIFT
72201. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL0P9_MASK
72202. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL0P9__SHIFT
72203. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL1P1_MASK
72204. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL1P1__SHIFT
72205. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RXSEL_MASK
72206. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RXSEL__SHIFT
72207. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SLEWN_MASK
72208. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SLEWN__SHIFT
72209. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPARE_MASK
72210. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPARE__SHIFT
72211. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCEN_MASK
72212. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCEN__SHIFT
72213. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL_MASK
72214. DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL__SHIFT
72215. DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK
72216. DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT
72217. DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK
72218. DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT
72219. DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK
72220. DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT
72221. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK
72222. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT
72223. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV1_MASK
72224. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV1__SHIFT
72225. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK
72226. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT
72227. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK
72228. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT
72229. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK
72230. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT
72231. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK
72232. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT
72233. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV1_MASK
72234. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV1__SHIFT
72235. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK
72236. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT
72237. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK
72238. DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT
72239. DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK
72240. DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT
72241. DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK
72242. DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT
72243. DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK
72244. DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT
72245. DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK
72246. DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT
72247. DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK
72248. DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT
72249. DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK
72250. DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT
72251. DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK
72252. DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT
72253. DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK
72254. DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT
72255. DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK
72256. DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT
72257. DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK
72258. DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT
72259. DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK
72260. DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT
72261. DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK
72262. DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT
72263. DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK
72264. DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT
72265. DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK
72266. DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT
72267. DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK
72268. DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT
72269. DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK
72270. DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT
72271. DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK
72272. DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT
72273. DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK
72274. DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT
72275. DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK
72276. DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT
72277. DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK
72278. DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT
72279. DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK
72280. DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT
72281. DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK
72282. DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT
72283. DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK
72284. DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT
72285. DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK
72286. DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT
72287. DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK
72288. DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT
72289. DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK
72290. DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT
72291. DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK
72292. DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT
72293. DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK
72294. DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT
72295. DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK
72296. DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT
72297. DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK
72298. DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT
72299. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK
72300. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT
72301. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK
72302. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT
72303. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK
72304. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT
72305. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK
72306. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT
72307. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK
72308. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT
72309. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK
72310. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT
72311. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK
72312. DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT
72313. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK
72314. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT
72315. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK
72316. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT
72317. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV1_MASK
72318. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV1__SHIFT
72319. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK
72320. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT
72321. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK
72322. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT
72323. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK
72324. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT
72325. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV1_MASK
72326. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV1__SHIFT
72327. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK
72328. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT
72329. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK
72330. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT
72331. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK
72332. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT
72333. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV1_MASK
72334. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV1__SHIFT
72335. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK
72336. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT
72337. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK
72338. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT
72339. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK
72340. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT
72341. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV1_MASK
72342. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV1__SHIFT
72343. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK
72344. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT
72345. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK
72346. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT
72347. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK
72348. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT
72349. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV1_MASK
72350. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV1__SHIFT
72351. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK
72352. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT
72353. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK
72354. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT
72355. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK
72356. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT
72357. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV1_MASK
72358. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV1__SHIFT
72359. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK
72360. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT
72361. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK
72362. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT
72363. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK
72364. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT
72365. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV1_MASK
72366. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV1__SHIFT
72367. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK
72368. DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT
72369. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK
72370. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT
72371. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK
72372. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT
72373. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK
72374. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT
72375. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK
72376. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT
72377. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK
72378. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT
72379. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK
72380. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT
72381. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK
72382. DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT
72383. DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK
72384. DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT
72385. DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK
72386. DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT
72387. DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK
72388. DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT
72389. DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK
72390. DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT
72391. DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK
72392. DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT
72393. DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK
72394. DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT
72395. DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK
72396. DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT
72397. DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK
72398. DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT
72399. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK
72400. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT
72401. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK
72402. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT
72403. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK
72404. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT
72405. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV1_MASK
72406. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV1__SHIFT
72407. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK
72408. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT
72409. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK
72410. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT
72411. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK
72412. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT
72413. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK
72414. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT
72415. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV1_MASK
72416. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV1__SHIFT
72417. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK
72418. DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT
72419. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK
72420. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT
72421. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK
72422. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT
72423. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK
72424. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT
72425. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV1_MASK
72426. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV1__SHIFT
72427. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK
72428. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT
72429. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK
72430. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT
72431. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK
72432. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT
72433. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK
72434. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT
72435. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV1_MASK
72436. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV1__SHIFT
72437. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK
72438. DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT
72439. DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK
72440. DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT
72441. DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK
72442. DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT
72443. DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK
72444. DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT
72445. DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK
72446. DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT
72447. DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK
72448. DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT
72449. DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK
72450. DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT
72451. DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK
72452. DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT
72453. DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK
72454. DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT
72455. DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK
72456. DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT
72457. DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK
72458. DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT
72459. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_0P9_MASK
72460. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_0P9__SHIFT
72461. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_1P1_MASK
72462. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_1P1__SHIFT
72463. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_FALLSLEWSEL_MASK
72464. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT
72465. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_0P9_MASK
72466. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_0P9__SHIFT
72467. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_1P1_MASK
72468. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_1P1__SHIFT
72469. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCEN_MASK
72470. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCEN__SHIFT
72471. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCSEL_MASK
72472. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCSEL__SHIFT
72473. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_0P9_MASK
72474. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_0P9__SHIFT
72475. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_1P1_MASK
72476. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_1P1__SHIFT
72477. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_FALLSLEWSEL_MASK
72478. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT
72479. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_0P9_MASK
72480. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_0P9__SHIFT
72481. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_1P1_MASK
72482. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_1P1__SHIFT
72483. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCEN_MASK
72484. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCEN__SHIFT
72485. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCSEL_MASK
72486. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCSEL__SHIFT
72487. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_0P9_MASK
72488. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_0P9__SHIFT
72489. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_1P1_MASK
72490. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_1P1__SHIFT
72491. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_FALLSLEWSEL_MASK
72492. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT
72493. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_0P9_MASK
72494. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_0P9__SHIFT
72495. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_1P1_MASK
72496. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_1P1__SHIFT
72497. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCEN_MASK
72498. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCEN__SHIFT
72499. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCSEL_MASK
72500. DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCSEL__SHIFT
72501. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_BIASCRTEN_MASK
72502. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_BIASCRTEN__SHIFT
72503. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_SLEWN_MASK
72504. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_SLEWN__SHIFT
72505. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_BIASCRTEN_MASK
72506. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_BIASCRTEN__SHIFT
72507. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_SLEWN_MASK
72508. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_SLEWN__SHIFT
72509. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_BIASCRTEN_MASK
72510. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_BIASCRTEN__SHIFT
72511. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_SLEWN_MASK
72512. DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_SLEWN__SHIFT
72513. DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK
72514. DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT
72515. DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK
72516. DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT
72517. DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK
72518. DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT
72519. DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK
72520. DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT
72521. DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK
72522. DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT
72523. DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK
72524. DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT
72525. DC_GPIO_HPD_EN__HPD12_SPARE0_MASK
72526. DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT
72527. DC_GPIO_HPD_EN__HPD12_SPARE1_MASK
72528. DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT
72529. DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK
72530. DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT
72531. DC_GPIO_HPD_EN__HPD1_SEL0_MASK
72532. DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT
72533. DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK
72534. DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT
72535. DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK
72536. DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT
72537. DC_GPIO_HPD_EN__HPD34_SPARE0_MASK
72538. DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT
72539. DC_GPIO_HPD_EN__HPD34_SPARE1_MASK
72540. DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT
72541. DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK
72542. DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT
72543. DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK
72544. DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT
72545. DC_GPIO_HPD_EN__HPD56_SPARE0_MASK
72546. DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT
72547. DC_GPIO_HPD_EN__HPD56_SPARE1_MASK
72548. DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT
72549. DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK
72550. DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT
72551. DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK
72552. DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT
72553. DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK
72554. DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT
72555. DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK
72556. DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT
72557. DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK
72558. DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT
72559. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK
72560. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT
72561. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK
72562. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT
72563. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV1_MASK
72564. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV1__SHIFT
72565. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK
72566. DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT
72567. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK
72568. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT
72569. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK
72570. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT
72571. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV1_MASK
72572. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV1__SHIFT
72573. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK
72574. DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT
72575. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK
72576. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT
72577. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK
72578. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT
72579. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV1_MASK
72580. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV1__SHIFT
72581. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK
72582. DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT
72583. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK
72584. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT
72585. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK
72586. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT
72587. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV1_MASK
72588. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV1__SHIFT
72589. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK
72590. DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT
72591. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK
72592. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT
72593. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK
72594. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT
72595. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV1_MASK
72596. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV1__SHIFT
72597. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK
72598. DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT
72599. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK
72600. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT
72601. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK
72602. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT
72603. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV1_MASK
72604. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV1__SHIFT
72605. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK
72606. DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT
72607. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK
72608. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT
72609. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK
72610. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT
72611. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV1_MASK
72612. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV1__SHIFT
72613. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV_MASK
72614. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV__SHIFT
72615. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK
72616. DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT
72617. DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK
72618. DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT
72619. DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK
72620. DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT
72621. DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK
72622. DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT
72623. DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK
72624. DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT
72625. DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK
72626. DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT
72627. DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK
72628. DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT
72629. DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK
72630. DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT
72631. DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK
72632. DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT
72633. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_BIASCRTEN_MASK
72634. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_BIASCRTEN__SHIFT
72635. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_COMPSEL_MASK
72636. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_COMPSEL__SHIFT
72637. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL0P9_MASK
72638. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL0P9__SHIFT
72639. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL1P1_MASK
72640. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL1P1__SHIFT
72641. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_DATA_PD_EN_MASK
72642. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_DATA_PD_EN__SHIFT
72643. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_FALLSLEWSEL_MASK
72644. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_FALLSLEWSEL__SHIFT
72645. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RESBIASEN_MASK
72646. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RESBIASEN__SHIFT
72647. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL0P9_MASK
72648. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL0P9__SHIFT
72649. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL1P1_MASK
72650. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL1P1__SHIFT
72651. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RXSEL_MASK
72652. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RXSEL__SHIFT
72653. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SLEWN_MASK
72654. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SLEWN__SHIFT
72655. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPARE_MASK
72656. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPARE__SHIFT
72657. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCEN_MASK
72658. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCEN__SHIFT
72659. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCSEL_MASK
72660. DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCSEL__SHIFT
72661. DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK
72662. DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT
72663. DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK
72664. DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT
72665. DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK
72666. DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT
72667. DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK
72668. DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT
72669. DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK
72670. DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT
72671. DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK
72672. DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT
72673. DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK
72674. DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT
72675. DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK
72676. DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT
72677. DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK
72678. DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT
72679. DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK
72680. DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT
72681. DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK
72682. DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT
72683. DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK
72684. DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT
72685. DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK
72686. DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT
72687. DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK
72688. DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT
72689. DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK
72690. DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT
72691. DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK
72692. DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT
72693. DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK
72694. DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT
72695. DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK
72696. DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT
72697. DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK
72698. DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT
72699. DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK
72700. DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT
72701. DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK
72702. DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT
72703. DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK
72704. DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT
72705. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK
72706. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT
72707. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK
72708. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT
72709. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK
72710. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT
72711. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK
72712. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT
72713. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK
72714. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT
72715. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK
72716. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT
72717. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK
72718. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT
72719. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK
72720. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT
72721. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK
72722. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT
72723. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK
72724. DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT
72725. DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK
72726. DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT
72727. DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK
72728. DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT
72729. DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK
72730. DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT
72731. DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK
72732. DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT
72733. DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK
72734. DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT
72735. DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK
72736. DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT
72737. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK
72738. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT
72739. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK
72740. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT
72741. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK
72742. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT
72743. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK
72744. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT
72745. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK
72746. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT
72747. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK
72748. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT
72749. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK
72750. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT
72751. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK
72752. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT
72753. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK
72754. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT
72755. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK
72756. DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT
72757. DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK
72758. DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT
72759. DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK
72760. DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT
72761. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_MASK
72762. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK
72763. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT
72764. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK
72765. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT
72766. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH__SHIFT
72767. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_MASK
72768. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK
72769. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT
72770. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK
72771. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT
72772. DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH__SHIFT
72773. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK
72774. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT
72775. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK
72776. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT
72777. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK
72778. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT
72779. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK
72780. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT
72781. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK
72782. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT
72783. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK
72784. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT
72785. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK
72786. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT
72787. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK
72788. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT
72789. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK
72790. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT
72791. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK
72792. DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT
72793. DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK
72794. DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT
72795. DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK
72796. DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT
72797. DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK
72798. DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT
72799. DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK
72800. DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT
72801. DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK
72802. DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT
72803. DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK
72804. DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT
72805. DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK
72806. DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT
72807. DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK
72808. DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT
72809. DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK
72810. DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT
72811. DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK
72812. DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT
72813. DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK
72814. DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT
72815. DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK
72816. DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT
72817. DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK
72818. DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT
72819. DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK
72820. DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT
72821. DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK
72822. DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT
72823. DC_GPIO_PIN
72824. DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK
72825. DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT
72826. DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK
72827. DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT
72828. DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK
72829. DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT
72830. DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK
72831. DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT
72832. DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK
72833. DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT
72834. DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK
72835. DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT
72836. DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK
72837. DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT
72838. DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK
72839. DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT
72840. DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK
72841. DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT
72842. DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK
72843. DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT
72844. DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK
72845. DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT
72846. DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK
72847. DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT
72848. DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK
72849. DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT
72850. DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK
72851. DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT
72852. DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK
72853. DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT
72854. DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK
72855. DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT
72856. DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK
72857. DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT
72858. DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK
72859. DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT
72860. DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK
72861. DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT
72862. DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK
72863. DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT
72864. DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK
72865. DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT
72866. DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK
72867. DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT
72868. DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK
72869. DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT
72870. DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK
72871. DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT
72872. DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK
72873. DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT
72874. DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK
72875. DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT
72876. DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK
72877. DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT
72878. DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK
72879. DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT
72880. DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK
72881. DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT
72882. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK
72883. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT
72884. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK
72885. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT
72886. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV1_MASK
72887. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV1__SHIFT
72888. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK
72889. DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT
72890. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK
72891. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT
72892. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK
72893. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT
72894. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV1_MASK
72895. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV1__SHIFT
72896. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK
72897. DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT
72898. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK
72899. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT
72900. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK
72901. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT
72902. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV1_MASK
72903. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV1__SHIFT
72904. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK
72905. DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT
72906. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK
72907. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT
72908. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK
72909. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT
72910. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV1_MASK
72911. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV1__SHIFT
72912. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK
72913. DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT
72914. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK
72915. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT
72916. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK
72917. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT
72918. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV1_MASK
72919. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV1__SHIFT
72920. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK
72921. DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT
72922. DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK
72923. DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT
72924. DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK
72925. DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT
72926. DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK
72927. DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT
72928. DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK
72929. DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT
72930. DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK
72931. DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT
72932. DC_GPIO_RECEIVER_EN0__DC_GPIO_BLON_RECEN_MASK
72933. DC_GPIO_RECEIVER_EN0__DC_GPIO_BLON_RECEN__SHIFT
72934. DC_GPIO_RECEIVER_EN0__DC_GPIO_DDC2DATA_RECEN_MASK
72935. DC_GPIO_RECEIVER_EN0__DC_GPIO_DDC2DATA_RECEN__SHIFT
72936. DC_GPIO_RECEIVER_EN0__DC_GPIO_DIGON_RECEN_MASK
72937. DC_GPIO_RECEIVER_EN0__DC_GPIO_DIGON_RECEN__SHIFT
72938. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICA_RECEN_MASK
72939. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICA_RECEN__SHIFT
72940. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICB_RECEN_MASK
72941. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICB_RECEN__SHIFT
72942. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICC_RECEN_MASK
72943. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICC_RECEN__SHIFT
72944. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICD_RECEN_MASK
72945. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICD_RECEN__SHIFT
72946. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICE_RECEN_MASK
72947. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICE_RECEN__SHIFT
72948. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICF_RECEN_MASK
72949. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICF_RECEN__SHIFT
72950. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICG_RECEN_MASK
72951. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICG_RECEN__SHIFT
72952. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_CLK_RECEN_MASK
72953. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_CLK_RECEN__SHIFT
72954. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_VSYNC_RECEN_MASK
72955. DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_VSYNC_RECEN__SHIFT
72956. DC_GPIO_RECEIVER_EN0__DC_GPIO_HPD1_RECEN_MASK
72957. DC_GPIO_RECEIVER_EN0__DC_GPIO_HPD1_RECEN__SHIFT
72958. DC_GPIO_RECEIVER_EN0__DC_GPIO_HSYNCA_RECEN_MASK
72959. DC_GPIO_RECEIVER_EN0__DC_GPIO_HSYNCA_RECEN__SHIFT
72960. DC_GPIO_RECEIVER_EN0__DC_GPIO_RX_HPD_RECEN_MASK
72961. DC_GPIO_RECEIVER_EN0__DC_GPIO_RX_HPD_RECEN__SHIFT
72962. DC_GPIO_RECEIVER_EN0__DC_GPIO_VSYNCA_RECEN_MASK
72963. DC_GPIO_RECEIVER_EN0__DC_GPIO_VSYNCA_RECEN__SHIFT
72964. DC_GPIO_RECEIVER_EN0__VIPPAD_SCL_RECEN_MASK
72965. DC_GPIO_RECEIVER_EN0__VIPPAD_SCL_RECEN__SHIFT
72966. DC_GPIO_RECEIVER_EN0__VIPPAD_SDA_RECEN_MASK
72967. DC_GPIO_RECEIVER_EN0__VIPPAD_SDA_RECEN__SHIFT
72968. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1CLK_RECEN_MASK
72969. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1CLK_RECEN__SHIFT
72970. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1DATA_RECEN_MASK
72971. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1DATA_RECEN__SHIFT
72972. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC2CLK_RECEN_MASK
72973. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC2CLK_RECEN__SHIFT
72974. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3CLK_RECEN_MASK
72975. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3CLK_RECEN__SHIFT
72976. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3DATA_RECEN_MASK
72977. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3DATA_RECEN__SHIFT
72978. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4CLK_RECEN_MASK
72979. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4CLK_RECEN__SHIFT
72980. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4DATA_RECEN_MASK
72981. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4DATA_RECEN__SHIFT
72982. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5CLK_RECEN_MASK
72983. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5CLK_RECEN__SHIFT
72984. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5DATA_RECEN_MASK
72985. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5DATA_RECEN__SHIFT
72986. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6CLK_RECEN_MASK
72987. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6CLK_RECEN__SHIFT
72988. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6DATA_RECEN_MASK
72989. DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6DATA_RECEN__SHIFT
72990. DC_GPIO_RECEIVER_EN1__DC_GPIO_ENA_BL_RECEN_MASK
72991. DC_GPIO_RECEIVER_EN1__DC_GPIO_ENA_BL_RECEN__SHIFT
72992. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD2_RECEN_MASK
72993. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD2_RECEN__SHIFT
72994. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD3_RECEN_MASK
72995. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD3_RECEN__SHIFT
72996. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD4_RECEN_MASK
72997. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD4_RECEN__SHIFT
72998. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD5_RECEN_MASK
72999. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD5_RECEN__SHIFT
73000. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD6_RECEN_MASK
73001. DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD6_RECEN__SHIFT
73002. DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_A_RECEN_MASK
73003. DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_A_RECEN__SHIFT
73004. DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_B_RECEN_MASK
73005. DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_B_RECEN__SHIFT
73006. DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK
73007. DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT
73008. DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK
73009. DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT
73010. DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK
73011. DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT
73012. DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK
73013. DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT
73014. DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK
73015. DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT
73016. DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK
73017. DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT
73018. DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK
73019. DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT
73020. DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK
73021. DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT
73022. DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK
73023. DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT
73024. DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK
73025. DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT
73026. DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK
73027. DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT
73028. DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK
73029. DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT
73030. DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK
73031. DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT
73032. DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK
73033. DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT
73034. DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK
73035. DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT
73036. DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK
73037. DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT
73038. DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK
73039. DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT
73040. DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK
73041. DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT
73042. DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK
73043. DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT
73044. DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK
73045. DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT
73046. DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK
73047. DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT
73048. DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK
73049. DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT
73050. DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK
73051. DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT
73052. DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK
73053. DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT
73054. DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK
73055. DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT
73056. DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK
73057. DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT
73058. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK
73059. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT
73060. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK
73061. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT
73062. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_OPTC_HSYNC_MASK_MASK
73063. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_OPTC_HSYNC_MASK__SHIFT
73064. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK
73065. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT
73066. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV1_MASK
73067. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV1__SHIFT
73068. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK
73069. DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT
73070. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK
73071. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT
73072. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK
73073. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT
73074. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_OPTC_VSYNC_MASK_MASK
73075. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_OPTC_VSYNC_MASK__SHIFT
73076. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK
73077. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT
73078. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV1_MASK
73079. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV1__SHIFT
73080. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK
73081. DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT
73082. DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK
73083. DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT
73084. DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK
73085. DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT
73086. DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK
73087. DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT
73088. DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK
73089. DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT
73090. DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK
73091. DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT
73092. DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK
73093. DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT
73094. DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK
73095. DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT
73096. DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK
73097. DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT
73098. DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK
73099. DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT
73100. DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK
73101. DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT
73102. DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK
73103. DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT
73104. DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK
73105. DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT
73106. DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN_MASK
73107. DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN__SHIFT
73108. DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN_MASK
73109. DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN__SHIFT
73110. DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN_MASK
73111. DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN__SHIFT
73112. DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN_MASK
73113. DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN__SHIFT
73114. DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN_MASK
73115. DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN__SHIFT
73116. DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN_MASK
73117. DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN__SHIFT
73118. DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN_MASK
73119. DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN__SHIFT
73120. DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN_MASK
73121. DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN__SHIFT
73122. DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN_MASK
73123. DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN__SHIFT
73124. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK
73125. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT
73126. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK
73127. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT
73128. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK
73129. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT
73130. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK
73131. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT
73132. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK
73133. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT
73134. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK
73135. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT
73136. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK
73137. DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT
73138. DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK
73139. DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT
73140. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK
73141. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT
73142. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK
73143. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT
73144. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK
73145. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT
73146. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK
73147. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT
73148. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK
73149. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT
73150. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK
73151. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT
73152. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK
73153. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT
73154. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK
73155. DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT
73156. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK
73157. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT
73158. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK
73159. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT
73160. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK
73161. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT
73162. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK
73163. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT
73164. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK
73165. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT
73166. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK
73167. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT
73168. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK
73169. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT
73170. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK
73171. DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT
73172. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK
73173. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT
73174. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK
73175. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT
73176. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK
73177. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT
73178. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK
73179. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT
73180. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK
73181. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT
73182. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK
73183. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT
73184. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP_MASK
73185. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP__SHIFT
73186. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP_MASK
73187. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP__SHIFT
73188. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP_MASK
73189. DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP__SHIFT
73190. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK
73191. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT
73192. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK
73193. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT
73194. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK
73195. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT
73196. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK
73197. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT
73198. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK
73199. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT
73200. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK
73201. DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT
73202. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK
73203. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT
73204. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK
73205. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT
73206. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK
73207. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT
73208. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK
73209. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT
73210. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK
73211. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT
73212. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK
73213. DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT
73214. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK
73215. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT
73216. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK
73217. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT
73218. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK
73219. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT
73220. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK
73221. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT
73222. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK
73223. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT
73224. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK
73225. DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT
73226. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK
73227. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT
73228. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK
73229. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT
73230. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK
73231. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT
73232. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK
73233. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT
73234. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK
73235. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT
73236. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK
73237. DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT
73238. DC_HBUFFER_DELAY
73239. DC_HDC
73240. DC_HDC_MASK
73241. DC_HDC_SHIFT
73242. DC_HDMI_INFOFRAME_TYPE_AUDIO
73243. DC_HDMI_INFOFRAME_TYPE_AVI
73244. DC_HDMI_INFOFRAME_TYPE_SPD
73245. DC_HDMI_INFOFRAME_TYPE_VENDOR
73246. DC_HFILT_COUNT
73247. DC_HOSTREQ
73248. DC_HOST_COMM_SETTINGS
73249. DC_HOT_PLUG_DETECT1_CONTROL
73250. DC_HOT_PLUG_DETECT1_INTERRUPT
73251. DC_HOT_PLUG_DETECT1_INT_CONTROL
73252. DC_HOT_PLUG_DETECT1_INT_STATUS
73253. DC_HOT_PLUG_DETECT2_CONTROL
73254. DC_HOT_PLUG_DETECT2_INTERRUPT
73255. DC_HOT_PLUG_DETECT2_INT_CONTROL
73256. DC_HOT_PLUG_DETECT2_INT_STATUS
73257. DC_HOT_PLUG_DETECT3_CONTROL
73258. DC_HOT_PLUG_DETECT3_INT_CONTROL
73259. DC_HOT_PLUG_DETECT3_INT_STATUS
73260. DC_HOT_PLUG_DETECTx_EN
73261. DC_HOT_PLUG_DETECTx_INT_ACK
73262. DC_HOT_PLUG_DETECTx_INT_EN
73263. DC_HOT_PLUG_DETECTx_INT_POLARITY
73264. DC_HOT_PLUG_DETECTx_INT_STATUS
73265. DC_HOT_PLUG_DETECTx_SENSE
73266. DC_HPD1_CONTROL
73267. DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK
73268. DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT
73269. DC_HPD1_CONTROL__DC_HPD1_EN_MASK
73270. DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT
73271. DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK
73272. DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT
73273. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK
73274. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT
73275. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK
73276. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT
73277. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK
73278. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT
73279. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK
73280. DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT
73281. DC_HPD1_INTERRUPT
73282. DC_HPD1_INT_CONTROL
73283. DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK
73284. DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT
73285. DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
73286. DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT
73287. DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
73288. DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT
73289. DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK
73290. DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT
73291. DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK
73292. DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT
73293. DC_HPD1_INT_STATUS
73294. DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK
73295. DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT
73296. DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK
73297. DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT
73298. DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK
73299. DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT
73300. DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK
73301. DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT
73302. DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK
73303. DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73304. DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73305. DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73306. DC_HPD1_RX_INTERRUPT
73307. DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK
73308. DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT
73309. DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK
73310. DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT
73311. DC_HPD2_CONTROL
73312. DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK
73313. DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT
73314. DC_HPD2_CONTROL__DC_HPD2_EN_MASK
73315. DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT
73316. DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK
73317. DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT
73318. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK
73319. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT
73320. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK
73321. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT
73322. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK
73323. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT
73324. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK
73325. DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT
73326. DC_HPD2_INTERRUPT
73327. DC_HPD2_INT_CONTROL
73328. DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK
73329. DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT
73330. DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK
73331. DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT
73332. DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
73333. DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT
73334. DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK
73335. DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT
73336. DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK
73337. DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT
73338. DC_HPD2_INT_STATUS
73339. DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK
73340. DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT
73341. DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK
73342. DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT
73343. DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK
73344. DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT
73345. DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK
73346. DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT
73347. DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK
73348. DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73349. DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73350. DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73351. DC_HPD2_RX_INTERRUPT
73352. DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK
73353. DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT
73354. DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK
73355. DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT
73356. DC_HPD3_CONTROL
73357. DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK
73358. DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT
73359. DC_HPD3_CONTROL__DC_HPD3_EN_MASK
73360. DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT
73361. DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK
73362. DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT
73363. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK
73364. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT
73365. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK
73366. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT
73367. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK
73368. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT
73369. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK
73370. DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT
73371. DC_HPD3_INTERRUPT
73372. DC_HPD3_INT_CONTROL
73373. DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK
73374. DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT
73375. DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK
73376. DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT
73377. DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
73378. DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT
73379. DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK
73380. DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT
73381. DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK
73382. DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT
73383. DC_HPD3_INT_STATUS
73384. DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK
73385. DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT
73386. DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK
73387. DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT
73388. DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK
73389. DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT
73390. DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK
73391. DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT
73392. DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK
73393. DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73394. DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73395. DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73396. DC_HPD3_RX_INTERRUPT
73397. DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK
73398. DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT
73399. DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK
73400. DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT
73401. DC_HPD4_CONTROL
73402. DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK
73403. DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT
73404. DC_HPD4_CONTROL__DC_HPD4_EN_MASK
73405. DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT
73406. DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK
73407. DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT
73408. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK
73409. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT
73410. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK
73411. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT
73412. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK
73413. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT
73414. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK
73415. DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT
73416. DC_HPD4_INTERRUPT
73417. DC_HPD4_INT_CONTROL
73418. DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK
73419. DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT
73420. DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK
73421. DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT
73422. DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
73423. DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT
73424. DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK
73425. DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT
73426. DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK
73427. DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT
73428. DC_HPD4_INT_STATUS
73429. DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK
73430. DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT
73431. DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK
73432. DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT
73433. DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK
73434. DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT
73435. DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK
73436. DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT
73437. DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK
73438. DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73439. DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73440. DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73441. DC_HPD4_RX_INTERRUPT
73442. DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK
73443. DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT
73444. DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK
73445. DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT
73446. DC_HPD5_CONTROL
73447. DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK
73448. DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT
73449. DC_HPD5_CONTROL__DC_HPD5_EN_MASK
73450. DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT
73451. DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK
73452. DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT
73453. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK
73454. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT
73455. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK
73456. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT
73457. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK
73458. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT
73459. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK
73460. DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT
73461. DC_HPD5_INTERRUPT
73462. DC_HPD5_INT_CONTROL
73463. DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK
73464. DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT
73465. DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK
73466. DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT
73467. DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
73468. DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT
73469. DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK
73470. DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT
73471. DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK
73472. DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT
73473. DC_HPD5_INT_STATUS
73474. DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK
73475. DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT
73476. DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK
73477. DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT
73478. DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK
73479. DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT
73480. DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK
73481. DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT
73482. DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK
73483. DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73484. DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73485. DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73486. DC_HPD5_RX_INTERRUPT
73487. DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK
73488. DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT
73489. DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK
73490. DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT
73491. DC_HPD6_CONTROL
73492. DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK
73493. DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT
73494. DC_HPD6_CONTROL__DC_HPD6_EN_MASK
73495. DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT
73496. DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK
73497. DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT
73498. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK
73499. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT
73500. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK
73501. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT
73502. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK
73503. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT
73504. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK
73505. DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT
73506. DC_HPD6_INTERRUPT
73507. DC_HPD6_INT_CONTROL
73508. DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK
73509. DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT
73510. DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK
73511. DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT
73512. DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
73513. DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT
73514. DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK
73515. DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT
73516. DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK
73517. DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT
73518. DC_HPD6_INT_STATUS
73519. DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK
73520. DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT
73521. DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK
73522. DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT
73523. DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK
73524. DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT
73525. DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK
73526. DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT
73527. DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK
73528. DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73529. DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73530. DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73531. DC_HPD6_RX_INTERRUPT
73532. DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK
73533. DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT
73534. DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK
73535. DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT
73536. DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
73537. DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
73538. DC_HPD_CONTROL__DC_HPD_EN_MASK
73539. DC_HPD_CONTROL__DC_HPD_EN__SHIFT
73540. DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
73541. DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
73542. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
73543. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
73544. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
73545. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
73546. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
73547. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
73548. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
73549. DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
73550. DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
73551. DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
73552. DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
73553. DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
73554. DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
73555. DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
73556. DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
73557. DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
73558. DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
73559. DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
73560. DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
73561. DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
73562. DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
73563. DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
73564. DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
73565. DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
73566. DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
73567. DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
73568. DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
73569. DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
73570. DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
73571. DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
73572. DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
73573. DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
73574. DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
73575. DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
73576. DC_HPDx_CONNECTION_TIMER
73577. DC_HPDx_CONTROL
73578. DC_HPDx_EN
73579. DC_HPDx_INT_ACK
73580. DC_HPDx_INT_CONTROL
73581. DC_HPDx_INT_EN
73582. DC_HPDx_INT_POLARITY
73583. DC_HPDx_INT_STATUS
73584. DC_HPDx_INT_STATUS_REG
73585. DC_HPDx_RX_INT_ACK
73586. DC_HPDx_RX_INT_EN
73587. DC_HPDx_RX_INT_STATUS
73588. DC_HPDx_RX_INT_TIMER
73589. DC_HPDx_SENSE
73590. DC_HPDx_SENSE_DELAYED
73591. DC_HU
73592. DC_HU_MASK
73593. DC_HU_SHIFT
73594. DC_HW_TYPES_H
73595. DC_H_ACTIVE_TIMING
73596. DC_H_BLANK_TIMING
73597. DC_H_SYNC_TIMING
73598. DC_H_TIMING_1
73599. DC_H_TIMING_2
73600. DC_H_TIMING_3
73601. DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK
73602. DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT
73603. DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK
73604. DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT
73605. DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK
73606. DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT
73607. DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK
73608. DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT
73609. DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK
73610. DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT
73611. DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK
73612. DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT
73613. DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK
73614. DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT
73615. DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
73616. DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK
73617. DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL
73618. DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT
73619. DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK
73620. DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT
73621. DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK
73622. DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT
73623. DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK
73624. DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT
73625. DC_I2C_CONTROL__DC_I2C_GO_MASK
73626. DC_I2C_CONTROL__DC_I2C_GO__SHIFT
73627. DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK
73628. DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT
73629. DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK
73630. DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT
73631. DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK
73632. DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT
73633. DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK
73634. DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT
73635. DC_I2C_DATA__DC_I2C_DATA_MASK
73636. DC_I2C_DATA__DC_I2C_DATA_RW_MASK
73637. DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT
73638. DC_I2C_DATA__DC_I2C_DATA__SHIFT
73639. DC_I2C_DATA__DC_I2C_INDEX_MASK
73640. DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK
73641. DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT
73642. DC_I2C_DATA__DC_I2C_INDEX__SHIFT
73643. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK
73644. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73645. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK
73646. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT
73647. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK
73648. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT
73649. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK
73650. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT
73651. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK
73652. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT
73653. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK
73654. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT
73655. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK
73656. DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT
73657. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK
73658. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT
73659. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK
73660. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT
73661. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK
73662. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT
73663. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK
73664. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT
73665. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK
73666. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT
73667. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK
73668. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT
73669. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK
73670. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT
73671. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK
73672. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT
73673. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK
73674. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT
73675. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK
73676. DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT
73677. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK
73678. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT
73679. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK
73680. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT
73681. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK
73682. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT
73683. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK
73684. DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT
73685. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK
73686. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73687. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK
73688. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT
73689. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK
73690. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT
73691. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK
73692. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT
73693. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK
73694. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT
73695. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK
73696. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT
73697. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK
73698. DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT
73699. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK
73700. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT
73701. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK
73702. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT
73703. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK
73704. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT
73705. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK
73706. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT
73707. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK
73708. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT
73709. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK
73710. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT
73711. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK
73712. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT
73713. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK
73714. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT
73715. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK
73716. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT
73717. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK
73718. DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT
73719. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK
73720. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT
73721. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK
73722. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT
73723. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK
73724. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT
73725. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK
73726. DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT
73727. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK
73728. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73729. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK
73730. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT
73731. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK
73732. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT
73733. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK
73734. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT
73735. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK
73736. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT
73737. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK
73738. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT
73739. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK
73740. DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT
73741. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK
73742. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT
73743. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK
73744. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT
73745. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK
73746. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT
73747. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK
73748. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT
73749. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK
73750. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT
73751. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK
73752. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT
73753. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK
73754. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT
73755. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK
73756. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT
73757. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK
73758. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT
73759. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK
73760. DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT
73761. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK
73762. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT
73763. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK
73764. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT
73765. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK
73766. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT
73767. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK
73768. DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT
73769. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK
73770. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73771. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK
73772. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT
73773. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK
73774. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT
73775. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK
73776. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT
73777. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK
73778. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT
73779. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK
73780. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT
73781. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK
73782. DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT
73783. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK
73784. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT
73785. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK
73786. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT
73787. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK
73788. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT
73789. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK
73790. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT
73791. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK
73792. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT
73793. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK
73794. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT
73795. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK
73796. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT
73797. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK
73798. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT
73799. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK
73800. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT
73801. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK
73802. DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT
73803. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK
73804. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT
73805. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK
73806. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT
73807. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK
73808. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT
73809. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK
73810. DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT
73811. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK
73812. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73813. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK
73814. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT
73815. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK
73816. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT
73817. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK
73818. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT
73819. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK
73820. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT
73821. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK
73822. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT
73823. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK
73824. DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT
73825. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK
73826. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT
73827. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK
73828. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT
73829. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK
73830. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT
73831. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK
73832. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT
73833. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK
73834. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT
73835. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK
73836. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT
73837. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK
73838. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT
73839. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK
73840. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT
73841. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK
73842. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT
73843. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK
73844. DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT
73845. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK
73846. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT
73847. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK
73848. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT
73849. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK
73850. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT
73851. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK
73852. DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT
73853. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK
73854. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73855. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK
73856. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT
73857. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK
73858. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT
73859. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK
73860. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT
73861. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK
73862. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT
73863. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK
73864. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT
73865. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK
73866. DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT
73867. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK
73868. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT
73869. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK
73870. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT
73871. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK
73872. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT
73873. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK
73874. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT
73875. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK
73876. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT
73877. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK
73878. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT
73879. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK
73880. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT
73881. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK
73882. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT
73883. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_SEND_RESET_LENGTH_MASK
73884. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_SEND_RESET_LENGTH__SHIFT
73885. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK
73886. DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT
73887. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK
73888. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT
73889. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK
73890. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT
73891. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK
73892. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT
73893. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK
73894. DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT
73895. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK
73896. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT
73897. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK
73898. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT
73899. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK
73900. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT
73901. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK
73902. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT
73903. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK
73904. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT
73905. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK
73906. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT
73907. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK
73908. DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT
73909. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK
73910. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT
73911. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK
73912. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT
73913. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK
73914. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT
73915. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK
73916. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT
73917. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK
73918. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT
73919. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK
73920. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT
73921. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK
73922. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT
73923. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK
73924. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT
73925. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK
73926. DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT
73927. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK
73928. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT
73929. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK
73930. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT
73931. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK
73932. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT
73933. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK
73934. DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT
73935. DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK
73936. DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT
73937. DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK
73938. DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT
73939. DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK
73940. DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT
73941. DC_I2C_HW_DONE_INTERRUPT
73942. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK
73943. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT
73944. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK
73945. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT
73946. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK
73947. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT
73948. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK
73949. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT
73950. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK
73951. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT
73952. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK
73953. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT
73954. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK
73955. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT
73956. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK
73957. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT
73958. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK
73959. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT
73960. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK
73961. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT
73962. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK
73963. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT
73964. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK
73965. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT
73966. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK
73967. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT
73968. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK
73969. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT
73970. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK
73971. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT
73972. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK
73973. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT
73974. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK
73975. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT
73976. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK
73977. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT
73978. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK
73979. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT
73980. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK
73981. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT
73982. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK
73983. DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT
73984. DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK
73985. DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT
73986. DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK
73987. DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT
73988. DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK
73989. DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT
73990. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK
73991. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT
73992. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK
73993. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT
73994. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK
73995. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT
73996. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK
73997. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT
73998. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK
73999. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT
74000. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK
74001. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT
74002. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK
74003. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT
74004. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK
74005. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT
74006. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK
74007. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT
74008. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK
74009. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT
74010. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK
74011. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT
74012. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK
74013. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT
74014. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK
74015. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT
74016. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK
74017. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT
74018. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK
74019. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT
74020. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK
74021. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT
74022. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK
74023. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT
74024. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK
74025. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT
74026. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK
74027. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT
74028. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK
74029. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT
74030. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK
74031. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT
74032. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK
74033. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT
74034. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK
74035. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT
74036. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK
74037. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT
74038. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK
74039. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT
74040. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK
74041. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT
74042. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK
74043. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT
74044. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK
74045. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT
74046. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK
74047. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT
74048. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK
74049. DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT
74050. DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY
74051. DC_I2C_STATUS__DC_I2C_STATUS_IDLE
74052. DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
74053. DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW
74054. DC_I2C_SW_DONE_INTERRUPT
74055. DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK
74056. DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT
74057. DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK
74058. DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT
74059. DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK
74060. DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT
74061. DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK
74062. DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT
74063. DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK
74064. DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT
74065. DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK
74066. DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT
74067. DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK
74068. DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT
74069. DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK
74070. DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT
74071. DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK
74072. DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT
74073. DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK
74074. DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT
74075. DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK
74076. DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT
74077. DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK
74078. DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT
74079. DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK
74080. DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT
74081. DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK
74082. DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT
74083. DC_I2C_TRANSACTION0__DC_I2C_START0_MASK
74084. DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT
74085. DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK
74086. DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT
74087. DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK
74088. DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT
74089. DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK
74090. DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT
74091. DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK
74092. DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT
74093. DC_I2C_TRANSACTION1__DC_I2C_START1_MASK
74094. DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT
74095. DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK
74096. DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT
74097. DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK
74098. DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT
74099. DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK
74100. DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT
74101. DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK
74102. DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT
74103. DC_I2C_TRANSACTION2__DC_I2C_START2_MASK
74104. DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT
74105. DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK
74106. DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT
74107. DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK
74108. DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT
74109. DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK
74110. DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT
74111. DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK
74112. DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT
74113. DC_I2C_TRANSACTION3__DC_I2C_START3_MASK
74114. DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT
74115. DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK
74116. DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT
74117. DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK
74118. DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT
74119. DC_ICON_COLOR
74120. DC_ICON_ST_OFFSET
74121. DC_ICON_X
74122. DC_ICON_Y
74123. DC_IEBRST
74124. DC_IEDMA
74125. DC_IEHS_STA
74126. DC_IEP0SETUP
74127. DC_IEPRX
74128. DC_IEPRXTX
74129. DC_IEPSOF
74130. DC_IEPTX
74131. DC_IERESM
74132. DC_IESOF
74133. DC_IESUSP
74134. DC_IEVBUS
74135. DC_IH_SRC_ID_END
74136. DC_IH_SRC_ID_START
74137. DC_INC_VM_HELPER_H_
74138. DC_INTCONF
74139. DC_INTENABLE
74140. DC_INTERFACE_H_
74141. DC_INTERRUPT
74142. DC_INTLVL
74143. DC_INTPOL
74144. DC_INTPULSEWIDTH
74145. DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK
74146. DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT
74147. DC_IRQ
74148. DC_IRQ_FILT_CTL
74149. DC_IRQ_FILT_CTL_H_FILT_SEL
74150. DC_IRQ_MASK
74151. DC_IRQ_SOURCE_DC1UNDERFLOW
74152. DC_IRQ_SOURCE_DC1_VLINE0
74153. DC_IRQ_SOURCE_DC1_VLINE1
74154. DC_IRQ_SOURCE_DC2UNDERFLOW
74155. DC_IRQ_SOURCE_DC2_VLINE0
74156. DC_IRQ_SOURCE_DC2_VLINE1
74157. DC_IRQ_SOURCE_DC3UNDERFLOW
74158. DC_IRQ_SOURCE_DC3_VLINE0
74159. DC_IRQ_SOURCE_DC3_VLINE1
74160. DC_IRQ_SOURCE_DC4UNDERFLOW
74161. DC_IRQ_SOURCE_DC4_VLINE0
74162. DC_IRQ_SOURCE_DC4_VLINE1
74163. DC_IRQ_SOURCE_DC5UNDERFLOW
74164. DC_IRQ_SOURCE_DC5_VLINE0
74165. DC_IRQ_SOURCE_DC5_VLINE1
74166. DC_IRQ_SOURCE_DC6UNDERFLOW
74167. DC_IRQ_SOURCE_DC6_VLINE0
74168. DC_IRQ_SOURCE_DC6_VLINE1
74169. DC_IRQ_SOURCE_DMCU_SCP
74170. DC_IRQ_SOURCE_DPSINK1
74171. DC_IRQ_SOURCE_DPSINK2
74172. DC_IRQ_SOURCE_DPSINK3
74173. DC_IRQ_SOURCE_DPSINK4
74174. DC_IRQ_SOURCE_DPSINK5
74175. DC_IRQ_SOURCE_DPSINK6
74176. DC_IRQ_SOURCE_GPIOPAD0
74177. DC_IRQ_SOURCE_GPIOPAD1
74178. DC_IRQ_SOURCE_GPIOPAD10
74179. DC_IRQ_SOURCE_GPIOPAD11
74180. DC_IRQ_SOURCE_GPIOPAD12
74181. DC_IRQ_SOURCE_GPIOPAD13
74182. DC_IRQ_SOURCE_GPIOPAD14
74183. DC_IRQ_SOURCE_GPIOPAD15
74184. DC_IRQ_SOURCE_GPIOPAD16
74185. DC_IRQ_SOURCE_GPIOPAD17
74186. DC_IRQ_SOURCE_GPIOPAD18
74187. DC_IRQ_SOURCE_GPIOPAD19
74188. DC_IRQ_SOURCE_GPIOPAD2
74189. DC_IRQ_SOURCE_GPIOPAD20
74190. DC_IRQ_SOURCE_GPIOPAD21
74191. DC_IRQ_SOURCE_GPIOPAD22
74192. DC_IRQ_SOURCE_GPIOPAD23
74193. DC_IRQ_SOURCE_GPIOPAD24
74194. DC_IRQ_SOURCE_GPIOPAD25
74195. DC_IRQ_SOURCE_GPIOPAD26
74196. DC_IRQ_SOURCE_GPIOPAD27
74197. DC_IRQ_SOURCE_GPIOPAD28
74198. DC_IRQ_SOURCE_GPIOPAD29
74199. DC_IRQ_SOURCE_GPIOPAD3
74200. DC_IRQ_SOURCE_GPIOPAD30
74201. DC_IRQ_SOURCE_GPIOPAD4
74202. DC_IRQ_SOURCE_GPIOPAD5
74203. DC_IRQ_SOURCE_GPIOPAD6
74204. DC_IRQ_SOURCE_GPIOPAD7
74205. DC_IRQ_SOURCE_GPIOPAD8
74206. DC_IRQ_SOURCE_GPIOPAD9
74207. DC_IRQ_SOURCE_HPD1
74208. DC_IRQ_SOURCE_HPD1RX
74209. DC_IRQ_SOURCE_HPD2
74210. DC_IRQ_SOURCE_HPD2RX
74211. DC_IRQ_SOURCE_HPD3
74212. DC_IRQ_SOURCE_HPD3RX
74213. DC_IRQ_SOURCE_HPD4
74214. DC_IRQ_SOURCE_HPD4RX
74215. DC_IRQ_SOURCE_HPD5
74216. DC_IRQ_SOURCE_HPD5RX
74217. DC_IRQ_SOURCE_HPD6
74218. DC_IRQ_SOURCE_HPD6RX
74219. DC_IRQ_SOURCE_I2C_DDC1
74220. DC_IRQ_SOURCE_I2C_DDC2
74221. DC_IRQ_SOURCE_I2C_DDC3
74222. DC_IRQ_SOURCE_I2C_DDC4
74223. DC_IRQ_SOURCE_I2C_DDC5
74224. DC_IRQ_SOURCE_I2C_DDC6
74225. DC_IRQ_SOURCE_INVALID
74226. DC_IRQ_SOURCE_PFLIP1
74227. DC_IRQ_SOURCE_PFLIP2
74228. DC_IRQ_SOURCE_PFLIP3
74229. DC_IRQ_SOURCE_PFLIP4
74230. DC_IRQ_SOURCE_PFLIP5
74231. DC_IRQ_SOURCE_PFLIP6
74232. DC_IRQ_SOURCE_PFLIP_FIRST
74233. DC_IRQ_SOURCE_PFLIP_LAST
74234. DC_IRQ_SOURCE_PFLIP_UNDERLAY0
74235. DC_IRQ_SOURCE_TIMER
74236. DC_IRQ_SOURCE_VBIOS_SW
74237. DC_IRQ_SOURCE_VBLANK1
74238. DC_IRQ_SOURCE_VBLANK2
74239. DC_IRQ_SOURCE_VBLANK3
74240. DC_IRQ_SOURCE_VBLANK4
74241. DC_IRQ_SOURCE_VBLANK5
74242. DC_IRQ_SOURCE_VBLANK6
74243. DC_IRQ_SOURCE_VUPDATE1
74244. DC_IRQ_SOURCE_VUPDATE2
74245. DC_IRQ_SOURCE_VUPDATE3
74246. DC_IRQ_SOURCE_VUPDATE4
74247. DC_IRQ_SOURCE_VUPDATE5
74248. DC_IRQ_SOURCE_VUPDATE6
74249. DC_IRQ_STATUS
74250. DC_IRQ_VIP_VSYNC_IRQ_STATUS
74251. DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK
74252. DC_LB_DISP1_END_ADR_MASK
74253. DC_LB_DISP1_END_ADR_SHIFT
74254. DC_LB_MEMORY_CONFIG
74255. DC_LB_MEMORY_SPLIT
74256. DC_LB_MEMORY_SPLIT_D1HALF_D2HALF
74257. DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q
74258. DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q
74259. DC_LB_MEMORY_SPLIT_D1_ONLY
74260. DC_LB_MEMORY_SPLIT_MASK
74261. DC_LB_MEMORY_SPLIT_SHIFT
74262. DC_LB_MEMORY_SPLIT_SHIFT_MODE
74263. DC_LCB_CFG_ALLOW_LINK_UP
74264. DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT
74265. DC_LCB_CFG_CLK_CNTR
74266. DC_LCB_CFG_CNT_FOR_SKIP_STALL
74267. DC_LCB_CFG_CRC_MODE
74268. DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT
74269. DC_LCB_CFG_IGNORE_LOST_RCLK
74270. DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK
74271. DC_LCB_CFG_LANE_WIDTH
74272. DC_LCB_CFG_LINK_KILL_EN
74273. DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK
74274. DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
74275. DC_LCB_CFG_LN_DCLK
74276. DC_LCB_CFG_LOOPBACK
74277. DC_LCB_CFG_LOOPBACK_VAL_SHIFT
74278. DC_LCB_CFG_REINIT_AS_SLAVE
74279. DC_LCB_CFG_RUN
74280. DC_LCB_CFG_RUN_EN_SHIFT
74281. DC_LCB_CFG_RX_FIFOS_RADR
74282. DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
74283. DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
74284. DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT
74285. DC_LCB_CFG_TX_FIFOS_RADR
74286. DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT
74287. DC_LCB_CFG_TX_FIFOS_RESET
74288. DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT
74289. DC_LCB_CSRS
74290. DC_LCB_ERR_CLR
74291. DC_LCB_ERR_EN
74292. DC_LCB_ERR_FLG
74293. DC_LCB_ERR_FLG_ALL_LNS_FAILED_REINIT_TEST_SMASK
74294. DC_LCB_ERR_FLG_CRC_ERR_CNT_HIT_LIMIT_SMASK
74295. DC_LCB_ERR_FLG_CREDIT_RETURN_FLIT_MBE_SMASK
74296. DC_LCB_ERR_FLG_CSR_PARITY_ERR_SMASK
74297. DC_LCB_ERR_FLG_FLIT_INPUT_BUF_MBE_SMASK
74298. DC_LCB_ERR_FLG_FLIT_INPUT_BUF_OFLW_SMASK
74299. DC_LCB_ERR_FLG_FLIT_INPUT_BUF_SBE_SMASK
74300. DC_LCB_ERR_FLG_HOLD_REINIT_SMASK
74301. DC_LCB_ERR_FLG_ILLEGAL_FLIT_ENCODING_SMASK
74302. DC_LCB_ERR_FLG_ILLEGAL_NULL_LTP_SMASK
74303. DC_LCB_ERR_FLG_INVALID_CSR_ADDR_SMASK
74304. DC_LCB_ERR_FLG_LOST_REINIT_STALL_OR_TOS_SMASK
74305. DC_LCB_ERR_FLG_NEG_EDGE_LINK_TRANSFER_ACTIVE_SMASK
74306. DC_LCB_ERR_FLG_RCLK_STOPPED_SMASK
74307. DC_LCB_ERR_FLG_REDUNDANT_FLIT_PARITY_ERR_SMASK
74308. DC_LCB_ERR_FLG_REINIT_FOR_LN_DEGRADE_SMASK
74309. DC_LCB_ERR_FLG_REINIT_FROM_PEER_SMASK
74310. DC_LCB_ERR_FLG_REPLAY_BUF_MBE_SMASK
74311. DC_LCB_ERR_FLG_REPLAY_BUF_SBE_SMASK
74312. DC_LCB_ERR_FLG_RST_FOR_FAILED_DESKEW_SMASK
74313. DC_LCB_ERR_FLG_RST_FOR_INCOMPLT_RND_TRIP_SMASK
74314. DC_LCB_ERR_FLG_RST_FOR_LINK_TIMEOUT_SMASK
74315. DC_LCB_ERR_FLG_RX_LESS_THAN_FOUR_LNS_SMASK
74316. DC_LCB_ERR_FLG_SEQ_CRC_ERR_SMASK
74317. DC_LCB_ERR_FLG_TX_LESS_THAN_FOUR_LNS_SMASK
74318. DC_LCB_ERR_FLG_UNEXPECTED_REPLAY_MARKER_SMASK
74319. DC_LCB_ERR_FLG_UNEXPECTED_ROUND_TRIP_MARKER_SMASK
74320. DC_LCB_ERR_FLG_VL_ACK_INPUT_BUF_OFLW_SMASK
74321. DC_LCB_ERR_FLG_VL_ACK_INPUT_PARITY_ERR_SMASK
74322. DC_LCB_ERR_FLG_VL_ACK_INPUT_WRONG_CRC_MODE_SMASK
74323. DC_LCB_ERR_INFO_CRC_ERR_LN0
74324. DC_LCB_ERR_INFO_CRC_ERR_LN1
74325. DC_LCB_ERR_INFO_CRC_ERR_LN2
74326. DC_LCB_ERR_INFO_CRC_ERR_LN3
74327. DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN
74328. DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT
74329. DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT
74330. DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT
74331. DC_LCB_ERR_INFO_MISC_FLG_CNT
74332. DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT
74333. DC_LCB_ERR_INFO_RX_REPLAY_CNT
74334. DC_LCB_ERR_INFO_SBE_CNT
74335. DC_LCB_ERR_INFO_SEQ_CRC_CNT
74336. DC_LCB_ERR_INFO_TOTAL_CRC_ERR
74337. DC_LCB_ERR_INFO_TX_REPLAY_CNT
74338. DC_LCB_PG_DBG_FLIT_CRDTS_CNT
74339. DC_LCB_PG_STS_PAUSE_COMPLETE_CNT
74340. DC_LCB_PG_STS_TX_MBE_CNT
74341. DC_LCB_PG_STS_TX_SBE_CNT
74342. DC_LCB_PRF_ACCEPTED_LTP_CNT
74343. DC_LCB_PRF_CLK_CNTR
74344. DC_LCB_PRF_GOOD_LTP_CNT
74345. DC_LCB_PRF_RX_FLIT_CNT
74346. DC_LCB_PRF_TX_FLIT_CNT
74347. DC_LCB_STS_LINK_TRANSFER_ACTIVE
74348. DC_LCB_STS_ROUND_TRIP_LTP_CNT
74349. DC_LES
74350. DC_LINE_CNT
74351. DC_LINE_DELTA
74352. DC_LINE_SIZE
74353. DC_LINK_H_
74354. DC_LOG2BETA
74355. DC_LOGGER
74356. DC_LOGGER_INIT
74357. DC_LOG_ALL_GAMMA
74358. DC_LOG_ALL_TF_CHANNELS
74359. DC_LOG_BACKLIGHT
74360. DC_LOG_BANDWIDTH_CALCS
74361. DC_LOG_BANDWIDTH_VALIDATION
74362. DC_LOG_BIOS
74363. DC_LOG_DC
74364. DC_LOG_DEBUG
74365. DC_LOG_DETECTION_DP_CAPS
74366. DC_LOG_DETECTION_EDID_PARSER
74367. DC_LOG_DML
74368. DC_LOG_DSC
74369. DC_LOG_DTN
74370. DC_LOG_DWB
74371. DC_LOG_ERROR
74372. DC_LOG_EVENT_DETECTION
74373. DC_LOG_EVENT_LINK_LOSS
74374. DC_LOG_EVENT_LINK_TRAINING
74375. DC_LOG_EVENT_MODE_SET
74376. DC_LOG_EVENT_UNDERFLOW
74377. DC_LOG_FEATURE_OVERRIDE
74378. DC_LOG_GAMMA
74379. DC_LOG_HW_AUDIO
74380. DC_LOG_HW_HOTPLUG
74381. DC_LOG_HW_HPD_IRQ
74382. DC_LOG_HW_LINK_TRAINING
74383. DC_LOG_HW_RESUME_S3
74384. DC_LOG_HW_SET_MODE
74385. DC_LOG_I2C_AUX
74386. DC_LOG_IF_TRACE
74387. DC_LOG_MST
74388. DC_LOG_PERF_TRACE
74389. DC_LOG_RESOURCE
74390. DC_LOG_RETIMER_REDRIVER
74391. DC_LOG_SCALER
74392. DC_LOG_SURFACE
74393. DC_LOG_SYNC
74394. DC_LOG_WARNING
74395. DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK
74396. DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT
74397. DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK
74398. DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT
74399. DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK
74400. DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT
74401. DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK
74402. DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT
74403. DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK
74404. DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT
74405. DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK
74406. DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT
74407. DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK
74408. DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT
74409. DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK
74410. DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT
74411. DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK
74412. DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT
74413. DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK
74414. DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT
74415. DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK
74416. DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT
74417. DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK
74418. DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT
74419. DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK
74420. DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT
74421. DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK
74422. DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT
74423. DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK
74424. DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT
74425. DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK
74426. DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT
74427. DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK
74428. DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT
74429. DC_LUT_CONTROL__DC_LUT_INC_B_MASK
74430. DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT
74431. DC_LUT_CONTROL__DC_LUT_INC_G_MASK
74432. DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT
74433. DC_LUT_CONTROL__DC_LUT_INC_R_MASK
74434. DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT
74435. DC_LUT_PWL_DATA__DC_LUT_BASE_MASK
74436. DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT
74437. DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK
74438. DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT
74439. DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK
74440. DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT
74441. DC_LUT_RW_MODE__DC_LUT_ERROR_MASK
74442. DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK
74443. DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT
74444. DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT
74445. DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK
74446. DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT
74447. DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK
74448. DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT
74449. DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK
74450. DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT
74451. DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK
74452. DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT
74453. DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK
74454. DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT
74455. DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK
74456. DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT
74457. DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK
74458. DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT
74459. DC_MAP_CONF_PTR
74460. DC_MAP_CONF_VAL
74461. DC_MAX_AUDIO_DESC_COUNT
74462. DC_MAX_EDID_BUFFER_SIZE
74463. DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK
74464. DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT
74465. DC_MEM_GLOBAL_PWR_REQ_DIS
74466. DC_MEM_GLOBAL_PWR_REQ_DISABLE
74467. DC_MEM_GLOBAL_PWR_REQ_ENABLE
74468. DC_MIN_LOG_MASK
74469. DC_MODE
74470. DC_MULTIPLE_DELAY
74471. DC_MULTI_MON_PP_MCLK_SWITCH_MASK
74472. DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK
74473. DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT
74474. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK
74475. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT
74476. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK
74477. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT
74478. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK
74479. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT
74480. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK
74481. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT
74482. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK
74483. DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT
74484. DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK
74485. DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT
74486. DC_NOEMPKT
74487. DC_NOTIFY_DELAY
74488. DC_NO_CLOCK_SOURCE_RESOURCE
74489. DC_NO_CONTROLLER_RESOURCE
74490. DC_NO_DP_LINK_BANDWIDTH
74491. DC_NO_DSC_RESOURCE
74492. DC_NO_STREAM_ENC_RESOURCE
74493. DC_OCFG_2IND
74494. DC_OCFG_2PXE
74495. DC_OCFG_2XCK
74496. DC_OCFG_34ADD
74497. DC_OCFG_555
74498. DC_OCFG_8BPP
74499. DC_OCFG_CFRW
74500. DC_OCFG_CKSL
74501. DC_OCFG_DIAG
74502. DC_OCFG_DITE
74503. DC_OCFG_FRME
74504. DC_OCFG_FRMS
74505. DC_OCFG_PCKE
74506. DC_OCFG_PDEH
74507. DC_OCFG_PDEL
74508. DC_OCFG_PRMP
74509. DC_OK
74510. DC_OUTPUT_CFG
74511. DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK
74512. DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT
74513. DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK
74514. DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT
74515. DC_PAL_ADDRESS
74516. DC_PAL_COUNT
74517. DC_PAL_DATA
74518. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
74519. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
74520. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
74521. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
74522. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
74523. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
74524. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
74525. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
74526. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
74527. DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
74528. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
74529. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
74530. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
74531. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
74532. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
74533. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
74534. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
74535. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
74536. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
74537. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
74538. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
74539. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
74540. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
74541. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
74542. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
74543. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
74544. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
74545. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
74546. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
74547. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
74548. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
74549. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
74550. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
74551. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
74552. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
74553. DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
74554. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
74555. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
74556. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
74557. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
74558. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
74559. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
74560. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
74561. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
74562. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
74563. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
74564. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
74565. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
74566. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
74567. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
74568. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
74569. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
74570. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
74571. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
74572. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
74573. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
74574. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
74575. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
74576. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
74577. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
74578. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
74579. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
74580. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
74581. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
74582. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
74583. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
74584. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
74585. DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
74586. DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
74587. DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
74588. DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
74589. DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
74590. DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
74591. DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
74592. DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
74593. DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
74594. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
74595. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
74596. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
74597. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
74598. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
74599. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
74600. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
74601. DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
74602. DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
74603. DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
74604. DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK
74605. DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT
74606. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
74607. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
74608. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
74609. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
74610. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
74611. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
74612. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
74613. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
74614. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
74615. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
74616. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
74617. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
74618. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
74619. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
74620. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
74621. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
74622. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
74623. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
74624. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
74625. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
74626. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
74627. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
74628. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
74629. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
74630. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
74631. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
74632. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
74633. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
74634. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
74635. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
74636. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
74637. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
74638. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
74639. DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
74640. DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
74641. DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
74642. DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK
74643. DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT
74644. DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK
74645. DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT
74646. DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK
74647. DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT
74648. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
74649. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
74650. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
74651. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
74652. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
74653. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
74654. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
74655. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
74656. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
74657. DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
74658. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
74659. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
74660. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
74661. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
74662. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
74663. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
74664. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
74665. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
74666. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
74667. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
74668. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
74669. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
74670. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
74671. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
74672. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
74673. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
74674. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
74675. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
74676. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
74677. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
74678. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
74679. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
74680. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
74681. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
74682. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
74683. DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
74684. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
74685. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
74686. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
74687. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
74688. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
74689. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
74690. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
74691. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
74692. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
74693. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
74694. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
74695. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
74696. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
74697. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
74698. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
74699. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
74700. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
74701. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
74702. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
74703. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
74704. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
74705. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
74706. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
74707. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
74708. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
74709. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
74710. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
74711. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
74712. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
74713. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
74714. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
74715. DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
74716. DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
74717. DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
74718. DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
74719. DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
74720. DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
74721. DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
74722. DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
74723. DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
74724. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
74725. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
74726. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
74727. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
74728. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
74729. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
74730. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
74731. DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
74732. DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
74733. DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
74734. DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK
74735. DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT
74736. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
74737. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
74738. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
74739. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
74740. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
74741. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
74742. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
74743. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
74744. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
74745. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
74746. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
74747. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
74748. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
74749. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
74750. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
74751. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
74752. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
74753. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
74754. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
74755. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
74756. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
74757. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
74758. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
74759. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
74760. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
74761. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
74762. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
74763. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
74764. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
74765. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
74766. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
74767. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
74768. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
74769. DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
74770. DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
74771. DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
74772. DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK
74773. DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT
74774. DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK
74775. DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT
74776. DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK
74777. DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT
74778. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
74779. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
74780. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
74781. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
74782. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
74783. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
74784. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
74785. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
74786. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
74787. DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
74788. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
74789. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
74790. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
74791. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
74792. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
74793. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
74794. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
74795. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
74796. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
74797. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
74798. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
74799. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
74800. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
74801. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
74802. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
74803. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
74804. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
74805. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
74806. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
74807. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
74808. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
74809. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
74810. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
74811. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
74812. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
74813. DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
74814. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
74815. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
74816. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
74817. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
74818. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
74819. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
74820. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
74821. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
74822. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
74823. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
74824. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
74825. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
74826. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
74827. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
74828. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
74829. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
74830. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
74831. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
74832. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
74833. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
74834. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
74835. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
74836. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
74837. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
74838. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
74839. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
74840. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
74841. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
74842. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
74843. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
74844. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
74845. DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
74846. DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
74847. DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
74848. DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
74849. DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
74850. DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
74851. DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
74852. DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
74853. DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
74854. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
74855. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
74856. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
74857. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
74858. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
74859. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
74860. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
74861. DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
74862. DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
74863. DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
74864. DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK
74865. DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT
74866. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
74867. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
74868. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
74869. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
74870. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
74871. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
74872. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
74873. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
74874. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
74875. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
74876. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
74877. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
74878. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
74879. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
74880. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
74881. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
74882. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
74883. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
74884. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
74885. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
74886. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
74887. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
74888. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
74889. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
74890. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
74891. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
74892. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
74893. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
74894. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
74895. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
74896. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
74897. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
74898. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
74899. DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
74900. DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
74901. DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
74902. DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK
74903. DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT
74904. DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK
74905. DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT
74906. DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK
74907. DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT
74908. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
74909. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
74910. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
74911. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
74912. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
74913. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
74914. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
74915. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
74916. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
74917. DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
74918. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
74919. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
74920. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
74921. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
74922. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
74923. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
74924. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
74925. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
74926. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
74927. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
74928. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
74929. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
74930. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
74931. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
74932. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
74933. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
74934. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
74935. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
74936. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
74937. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
74938. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
74939. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
74940. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
74941. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
74942. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
74943. DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
74944. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
74945. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
74946. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
74947. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
74948. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
74949. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
74950. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
74951. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
74952. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
74953. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
74954. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
74955. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
74956. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
74957. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
74958. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
74959. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
74960. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
74961. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
74962. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
74963. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
74964. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
74965. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
74966. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
74967. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
74968. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
74969. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
74970. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
74971. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
74972. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
74973. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
74974. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
74975. DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
74976. DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
74977. DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
74978. DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
74979. DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
74980. DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
74981. DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
74982. DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
74983. DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
74984. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
74985. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
74986. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
74987. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
74988. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
74989. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
74990. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
74991. DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
74992. DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
74993. DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
74994. DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK
74995. DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT
74996. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
74997. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
74998. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
74999. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75000. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75001. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75002. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75003. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75004. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75005. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75006. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75007. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75008. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75009. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75010. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75011. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75012. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75013. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75014. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75015. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75016. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75017. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75018. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75019. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75020. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75021. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75022. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75023. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75024. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75025. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75026. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75027. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75028. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75029. DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75030. DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75031. DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75032. DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK
75033. DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT
75034. DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK
75035. DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75036. DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK
75037. DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT
75038. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75039. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75040. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75041. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75042. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75043. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75044. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75045. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75046. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75047. DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75048. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75049. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75050. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75051. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75052. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
75053. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
75054. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75055. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75056. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75057. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75058. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75059. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75060. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75061. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75062. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75063. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75064. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75065. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75066. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
75067. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
75068. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75069. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75070. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75071. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75072. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75073. DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75074. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75075. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75076. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75077. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75078. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75079. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75080. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75081. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75082. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75083. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75084. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75085. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75086. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75087. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75088. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75089. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75090. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75091. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75092. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75093. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75094. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75095. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75096. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75097. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75098. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75099. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75100. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75101. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75102. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75103. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75104. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75105. DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75106. DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75107. DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75108. DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75109. DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75110. DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75111. DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75112. DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75113. DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75114. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75115. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75116. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75117. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75118. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75119. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75120. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75121. DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75122. DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75123. DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75124. DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK
75125. DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT
75126. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75127. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75128. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75129. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75130. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75131. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75132. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75133. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75134. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75135. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75136. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75137. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75138. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75139. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75140. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75141. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75142. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75143. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75144. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75145. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75146. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75147. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75148. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75149. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75150. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75151. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75152. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75153. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75154. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75155. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75156. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75157. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75158. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75159. DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75160. DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75161. DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75162. DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK
75163. DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT
75164. DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK
75165. DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75166. DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK
75167. DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT
75168. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75169. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75170. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75171. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75172. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75173. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75174. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75175. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75176. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75177. DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75178. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75179. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75180. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75181. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75182. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75183. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75184. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75185. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75186. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75187. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75188. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75189. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75190. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75191. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75192. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75193. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75194. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75195. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75196. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75197. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75198. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75199. DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75200. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75201. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75202. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75203. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75204. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75205. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75206. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75207. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75208. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75209. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75210. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75211. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75212. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75213. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75214. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75215. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75216. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75217. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75218. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75219. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75220. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75221. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75222. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75223. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75224. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75225. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75226. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75227. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75228. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75229. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75230. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75231. DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75232. DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75233. DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75234. DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75235. DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75236. DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75237. DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75238. DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75239. DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75240. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75241. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75242. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75243. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75244. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75245. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75246. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75247. DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75248. DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75249. DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75250. DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK
75251. DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT
75252. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75253. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75254. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75255. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75256. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75257. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75258. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75259. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75260. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75261. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75262. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75263. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75264. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75265. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75266. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75267. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75268. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75269. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75270. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75271. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75272. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75273. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75274. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75275. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75276. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75277. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75278. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75279. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75280. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75281. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75282. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75283. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75284. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75285. DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75286. DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75287. DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75288. DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK
75289. DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT
75290. DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK
75291. DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75292. DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK
75293. DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT
75294. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75295. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75296. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75297. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75298. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75299. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75300. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75301. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75302. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75303. DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75304. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75305. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75306. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75307. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75308. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75309. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75310. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75311. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75312. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75313. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75314. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75315. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75316. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75317. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75318. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75319. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75320. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75321. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75322. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75323. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75324. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75325. DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75326. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75327. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75328. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75329. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75330. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75331. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75332. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75333. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75334. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75335. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75336. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75337. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75338. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75339. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75340. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75341. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75342. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75343. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75344. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75345. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75346. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75347. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75348. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75349. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75350. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75351. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75352. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75353. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75354. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75355. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75356. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75357. DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75358. DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75359. DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75360. DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75361. DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75362. DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75363. DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75364. DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75365. DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75366. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75367. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75368. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75369. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75370. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75371. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75372. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75373. DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75374. DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75375. DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75376. DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK
75377. DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT
75378. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75379. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75380. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75381. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75382. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75383. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75384. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75385. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75386. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75387. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75388. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75389. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75390. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75391. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75392. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75393. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75394. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75395. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75396. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75397. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75398. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75399. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75400. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75401. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75402. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75403. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75404. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75405. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75406. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75407. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75408. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75409. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75410. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75411. DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75412. DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75413. DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75414. DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK
75415. DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT
75416. DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK
75417. DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75418. DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK
75419. DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT
75420. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75421. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75422. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75423. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75424. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75425. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75426. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75427. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75428. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75429. DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75430. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75431. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75432. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75433. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75434. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75435. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75436. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75437. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75438. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75439. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75440. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75441. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75442. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75443. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75444. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75445. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75446. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75447. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75448. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75449. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75450. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75451. DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75452. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75453. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75454. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75455. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75456. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75457. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75458. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75459. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75460. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75461. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75462. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75463. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75464. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75465. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75466. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75467. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75468. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75469. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75470. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75471. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75472. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75473. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75474. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75475. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75476. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75477. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75478. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75479. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75480. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75481. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75482. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75483. DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75484. DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75485. DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75486. DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75487. DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75488. DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75489. DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75490. DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75491. DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75492. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75493. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75494. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75495. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75496. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75497. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75498. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75499. DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75500. DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75501. DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75502. DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK
75503. DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT
75504. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75505. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75506. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75507. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75508. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75509. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75510. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75511. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75512. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75513. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75514. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75515. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75516. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75517. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75518. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75519. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75520. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75521. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75522. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75523. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75524. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75525. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75526. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75527. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75528. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75529. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75530. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75531. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75532. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75533. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75534. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75535. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75536. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75537. DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75538. DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75539. DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75540. DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK
75541. DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT
75542. DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK
75543. DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75544. DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK
75545. DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT
75546. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75547. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75548. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75549. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75550. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75551. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75552. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75553. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75554. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75555. DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75556. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75557. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75558. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75559. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75560. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75561. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75562. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75563. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75564. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75565. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75566. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75567. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75568. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75569. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75570. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75571. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75572. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75573. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75574. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75575. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75576. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75577. DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75578. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75579. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75580. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75581. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75582. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75583. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75584. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75585. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75586. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75587. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75588. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75589. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75590. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75591. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75592. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75593. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75594. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75595. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75596. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75597. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75598. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75599. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75600. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75601. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75602. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75603. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75604. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75605. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75606. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75607. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75608. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75609. DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75610. DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75611. DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75612. DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75613. DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75614. DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75615. DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75616. DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75617. DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75618. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75619. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75620. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75621. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75622. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75623. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75624. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75625. DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75626. DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75627. DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75628. DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK
75629. DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT
75630. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75631. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75632. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75633. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75634. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75635. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75636. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75637. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75638. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75639. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75640. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75641. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75642. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75643. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75644. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75645. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75646. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75647. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75648. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75649. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75650. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75651. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75652. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75653. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75654. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75655. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75656. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75657. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75658. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75659. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75660. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75661. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75662. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75663. DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75664. DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75665. DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75666. DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK
75667. DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT
75668. DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK
75669. DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75670. DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK
75671. DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT
75672. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75673. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75674. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75675. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75676. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75677. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75678. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75679. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75680. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75681. DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75682. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75683. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75684. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75685. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75686. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75687. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75688. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75689. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75690. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75691. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75692. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75693. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75694. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75695. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75696. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75697. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75698. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75699. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75700. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75701. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75702. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75703. DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75704. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75705. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75706. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75707. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75708. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75709. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75710. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75711. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75712. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75713. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75714. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75715. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75716. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75717. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75718. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75719. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75720. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75721. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75722. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75723. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75724. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75725. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75726. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75727. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75728. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75729. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75730. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75731. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75732. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75733. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75734. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75735. DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75736. DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75737. DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75738. DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75739. DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75740. DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75741. DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75742. DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75743. DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75744. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75745. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75746. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75747. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75748. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75749. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75750. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75751. DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75752. DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75753. DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75754. DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK
75755. DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT
75756. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75757. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75758. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75759. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75760. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75761. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75762. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75763. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75764. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75765. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75766. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75767. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75768. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75769. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75770. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75771. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75772. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75773. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75774. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75775. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75776. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75777. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75778. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75779. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75780. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75781. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75782. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75783. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75784. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75785. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75786. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75787. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75788. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75789. DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75790. DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75791. DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75792. DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK
75793. DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT
75794. DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK
75795. DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75796. DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK
75797. DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT
75798. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75799. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75800. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75801. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75802. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75803. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75804. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75805. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75806. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75807. DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75808. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75809. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75810. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75811. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75812. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75813. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75814. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75815. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75816. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75817. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75818. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75819. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75820. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75821. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75822. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75823. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75824. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75825. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75826. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75827. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75828. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75829. DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75830. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75831. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75832. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75833. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75834. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75835. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75836. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75837. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75838. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75839. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75840. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75841. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75842. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75843. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75844. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75845. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75846. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75847. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75848. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75849. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75850. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75851. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75852. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75853. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75854. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75855. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75856. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75857. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75858. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75859. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75860. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75861. DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75862. DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75863. DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75864. DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75865. DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75866. DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75867. DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75868. DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75869. DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
75870. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
75871. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
75872. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
75873. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
75874. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
75875. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
75876. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
75877. DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
75878. DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
75879. DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
75880. DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK
75881. DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT
75882. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
75883. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
75884. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
75885. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
75886. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
75887. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
75888. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
75889. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
75890. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
75891. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
75892. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
75893. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
75894. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
75895. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
75896. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
75897. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
75898. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
75899. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
75900. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
75901. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
75902. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
75903. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
75904. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
75905. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
75906. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
75907. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
75908. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
75909. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
75910. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
75911. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
75912. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
75913. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
75914. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
75915. DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
75916. DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
75917. DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
75918. DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK
75919. DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT
75920. DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK
75921. DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT
75922. DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK
75923. DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT
75924. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
75925. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
75926. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
75927. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
75928. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
75929. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
75930. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
75931. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
75932. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
75933. DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
75934. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
75935. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
75936. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
75937. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
75938. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
75939. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
75940. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
75941. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
75942. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
75943. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
75944. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
75945. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
75946. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
75947. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
75948. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
75949. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
75950. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
75951. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
75952. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
75953. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
75954. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
75955. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
75956. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
75957. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
75958. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
75959. DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
75960. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
75961. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
75962. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
75963. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
75964. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
75965. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
75966. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
75967. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
75968. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
75969. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
75970. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
75971. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
75972. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
75973. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
75974. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
75975. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
75976. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
75977. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
75978. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
75979. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
75980. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
75981. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
75982. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
75983. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
75984. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
75985. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
75986. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
75987. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
75988. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
75989. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
75990. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
75991. DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
75992. DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
75993. DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
75994. DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
75995. DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
75996. DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
75997. DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
75998. DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
75999. DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76000. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76001. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76002. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76003. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76004. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76005. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76006. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76007. DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76008. DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76009. DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76010. DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK
76011. DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT
76012. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76013. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76014. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76015. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76016. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76017. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76018. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76019. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76020. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76021. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76022. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76023. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76024. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76025. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76026. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76027. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76028. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76029. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76030. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76031. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76032. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76033. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76034. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76035. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76036. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76037. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76038. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76039. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76040. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76041. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76042. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76043. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76044. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76045. DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76046. DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76047. DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76048. DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK
76049. DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT
76050. DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK
76051. DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76052. DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK
76053. DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT
76054. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76055. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76056. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76057. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76058. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76059. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76060. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76061. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76062. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76063. DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76064. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76065. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76066. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76067. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76068. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76069. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76070. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76071. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76072. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76073. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76074. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76075. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76076. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76077. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76078. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76079. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76080. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76081. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76082. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76083. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76084. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76085. DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76086. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76087. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76088. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76089. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76090. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76091. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76092. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76093. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76094. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76095. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76096. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76097. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76098. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76099. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76100. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76101. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76102. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76103. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76104. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76105. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76106. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76107. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76108. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76109. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76110. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76111. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76112. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76113. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76114. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76115. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76116. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76117. DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76118. DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76119. DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76120. DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76121. DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76122. DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76123. DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76124. DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76125. DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76126. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76127. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76128. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76129. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76130. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76131. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76132. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76133. DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76134. DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76135. DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76136. DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK
76137. DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT
76138. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76139. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76140. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76141. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76142. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76143. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76144. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76145. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76146. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76147. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76148. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76149. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76150. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76151. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76152. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76153. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76154. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76155. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76156. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76157. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76158. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76159. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76160. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76161. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76162. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76163. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76164. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76165. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76166. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76167. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76168. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76169. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76170. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76171. DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76172. DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76173. DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76174. DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK
76175. DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT
76176. DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK
76177. DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76178. DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK
76179. DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT
76180. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76181. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76182. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76183. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76184. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76185. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76186. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76187. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76188. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76189. DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76190. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76191. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76192. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76193. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76194. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76195. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76196. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76197. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76198. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76199. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76200. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76201. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76202. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76203. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76204. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76205. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76206. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76207. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76208. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76209. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76210. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76211. DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76212. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76213. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76214. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76215. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76216. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76217. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76218. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76219. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76220. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76221. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76222. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76223. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76224. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76225. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76226. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76227. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76228. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76229. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76230. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76231. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76232. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76233. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76234. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76235. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76236. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76237. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76238. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76239. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76240. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76241. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76242. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76243. DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76244. DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76245. DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76246. DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76247. DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76248. DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76249. DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76250. DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76251. DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76252. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76253. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76254. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76255. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76256. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76257. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76258. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76259. DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76260. DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76261. DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76262. DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK
76263. DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT
76264. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76265. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76266. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76267. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76268. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76269. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76270. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76271. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76272. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76273. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76274. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76275. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76276. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76277. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76278. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76279. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76280. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76281. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76282. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76283. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76284. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76285. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76286. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76287. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76288. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76289. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76290. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76291. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76292. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76293. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76294. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76295. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76296. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76297. DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76298. DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76299. DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76300. DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK
76301. DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT
76302. DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK
76303. DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76304. DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK
76305. DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT
76306. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76307. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76308. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76309. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76310. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76311. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76312. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76313. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76314. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76315. DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76316. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76317. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76318. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76319. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76320. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76321. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76322. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76323. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76324. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76325. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76326. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76327. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76328. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76329. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76330. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76331. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76332. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76333. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76334. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76335. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76336. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76337. DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76338. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76339. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76340. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76341. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76342. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76343. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76344. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76345. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76346. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76347. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76348. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76349. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76350. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76351. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76352. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76353. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76354. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76355. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76356. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76357. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76358. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76359. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76360. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76361. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76362. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76363. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76364. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76365. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76366. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76367. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76368. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76369. DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76370. DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76371. DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76372. DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76373. DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76374. DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76375. DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76376. DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76377. DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76378. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76379. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76380. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76381. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76382. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76383. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76384. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76385. DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76386. DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76387. DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76388. DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK
76389. DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT
76390. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76391. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76392. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76393. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76394. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76395. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76396. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76397. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76398. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76399. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76400. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76401. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76402. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76403. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76404. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76405. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76406. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76407. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76408. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76409. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76410. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76411. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76412. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76413. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76414. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76415. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76416. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76417. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76418. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76419. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76420. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76421. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76422. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76423. DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76424. DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76425. DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76426. DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK
76427. DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT
76428. DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK
76429. DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76430. DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK
76431. DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT
76432. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76433. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76434. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76435. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76436. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76437. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76438. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76439. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76440. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76441. DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76442. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76443. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76444. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76445. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76446. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76447. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76448. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76449. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76450. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76451. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76452. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76453. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76454. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76455. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76456. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76457. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76458. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76459. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76460. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76461. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76462. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76463. DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76464. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76465. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76466. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76467. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76468. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76469. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76470. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76471. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76472. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76473. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76474. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76475. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76476. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76477. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76478. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76479. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76480. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76481. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76482. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76483. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76484. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76485. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76486. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76487. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76488. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76489. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76490. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76491. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76492. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76493. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76494. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76495. DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76496. DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76497. DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76498. DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76499. DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76500. DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76501. DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76502. DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76503. DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76504. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76505. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76506. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76507. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76508. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76509. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76510. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76511. DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76512. DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76513. DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76514. DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK
76515. DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT
76516. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76517. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76518. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76519. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76520. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76521. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76522. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76523. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76524. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76525. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76526. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76527. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76528. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76529. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76530. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76531. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76532. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76533. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76534. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76535. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76536. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76537. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76538. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76539. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76540. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76541. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76542. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76543. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76544. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76545. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76546. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76547. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76548. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76549. DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76550. DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76551. DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76552. DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK
76553. DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT
76554. DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK
76555. DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76556. DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK
76557. DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT
76558. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76559. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76560. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76561. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76562. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76563. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76564. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76565. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76566. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76567. DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76568. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76569. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76570. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76571. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76572. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76573. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76574. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76575. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76576. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76577. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76578. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76579. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76580. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76581. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76582. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76583. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76584. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76585. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76586. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76587. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76588. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76589. DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76590. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76591. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76592. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76593. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76594. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76595. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76596. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76597. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76598. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76599. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76600. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76601. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76602. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76603. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76604. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76605. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76606. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76607. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76608. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76609. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76610. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76611. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76612. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76613. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76614. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76615. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76616. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76617. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76618. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76619. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76620. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76621. DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76622. DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76623. DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76624. DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76625. DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76626. DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76627. DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76628. DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76629. DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76630. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76631. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76632. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76633. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76634. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76635. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76636. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76637. DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76638. DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76639. DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76640. DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE_MASK
76641. DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE__SHIFT
76642. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76643. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76644. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76645. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76646. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76647. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76648. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76649. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76650. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76651. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76652. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76653. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76654. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76655. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76656. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76657. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76658. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76659. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76660. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76661. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76662. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76663. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76664. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76665. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76666. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76667. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76668. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76669. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76670. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76671. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76672. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76673. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76674. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76675. DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76676. DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76677. DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76678. DC_PERFMON24_PERFMON_HI__PERFMON_HI_MASK
76679. DC_PERFMON24_PERFMON_HI__PERFMON_HI__SHIFT
76680. DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL_MASK
76681. DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76682. DC_PERFMON24_PERFMON_LOW__PERFMON_LOW_MASK
76683. DC_PERFMON24_PERFMON_LOW__PERFMON_LOW__SHIFT
76684. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76685. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76686. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76687. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76688. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76689. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76690. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76691. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76692. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76693. DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76694. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76695. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76696. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76697. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76698. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76699. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76700. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76701. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76702. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76703. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76704. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76705. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76706. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76707. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76708. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76709. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76710. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76711. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76712. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76713. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76714. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76715. DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76716. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76717. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76718. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76719. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76720. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76721. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76722. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76723. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76724. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76725. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76726. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76727. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76728. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76729. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76730. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76731. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76732. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76733. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76734. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76735. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76736. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76737. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76738. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76739. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76740. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76741. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76742. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76743. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76744. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76745. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76746. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76747. DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76748. DC_PERFMON25_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76749. DC_PERFMON25_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76750. DC_PERFMON25_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76751. DC_PERFMON25_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76752. DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76753. DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76754. DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76755. DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76756. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76757. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76758. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76759. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76760. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76761. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76762. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76763. DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76764. DC_PERFMON25_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76765. DC_PERFMON25_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76766. DC_PERFMON25_PERFMON_CNTL__PERFMON_STATE_MASK
76767. DC_PERFMON25_PERFMON_CNTL__PERFMON_STATE__SHIFT
76768. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76769. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76770. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76771. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76772. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76773. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76774. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76775. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76776. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76777. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76778. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76779. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76780. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76781. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76782. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76783. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76784. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76785. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76786. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76787. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76788. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76789. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76790. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76791. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76792. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76793. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76794. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76795. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76796. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76797. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76798. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76799. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76800. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76801. DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76802. DC_PERFMON25_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76803. DC_PERFMON25_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76804. DC_PERFMON25_PERFMON_HI__PERFMON_HI_MASK
76805. DC_PERFMON25_PERFMON_HI__PERFMON_HI__SHIFT
76806. DC_PERFMON25_PERFMON_HI__PERFMON_READ_SEL_MASK
76807. DC_PERFMON25_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76808. DC_PERFMON25_PERFMON_LOW__PERFMON_LOW_MASK
76809. DC_PERFMON25_PERFMON_LOW__PERFMON_LOW__SHIFT
76810. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76811. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76812. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76813. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76814. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76815. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76816. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76817. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76818. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76819. DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76820. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76821. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76822. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76823. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76824. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76825. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76826. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76827. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76828. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76829. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76830. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76831. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76832. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76833. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76834. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76835. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76836. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76837. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76838. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76839. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76840. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76841. DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76842. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76843. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76844. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76845. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76846. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76847. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76848. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76849. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76850. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76851. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76852. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76853. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76854. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76855. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76856. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76857. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76858. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76859. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76860. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76861. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76862. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76863. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76864. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76865. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76866. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76867. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76868. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76869. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76870. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76871. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76872. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76873. DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
76874. DC_PERFMON26_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
76875. DC_PERFMON26_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
76876. DC_PERFMON26_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
76877. DC_PERFMON26_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
76878. DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
76879. DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
76880. DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
76881. DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
76882. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
76883. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
76884. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
76885. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
76886. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
76887. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
76888. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
76889. DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
76890. DC_PERFMON26_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
76891. DC_PERFMON26_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
76892. DC_PERFMON26_PERFMON_CNTL__PERFMON_STATE_MASK
76893. DC_PERFMON26_PERFMON_CNTL__PERFMON_STATE__SHIFT
76894. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
76895. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
76896. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
76897. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
76898. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
76899. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
76900. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
76901. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
76902. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
76903. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
76904. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
76905. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
76906. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
76907. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
76908. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
76909. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
76910. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
76911. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
76912. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
76913. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
76914. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
76915. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
76916. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
76917. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
76918. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
76919. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
76920. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
76921. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
76922. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
76923. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
76924. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
76925. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
76926. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
76927. DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
76928. DC_PERFMON26_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
76929. DC_PERFMON26_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
76930. DC_PERFMON26_PERFMON_HI__PERFMON_HI_MASK
76931. DC_PERFMON26_PERFMON_HI__PERFMON_HI__SHIFT
76932. DC_PERFMON26_PERFMON_HI__PERFMON_READ_SEL_MASK
76933. DC_PERFMON26_PERFMON_HI__PERFMON_READ_SEL__SHIFT
76934. DC_PERFMON26_PERFMON_LOW__PERFMON_LOW_MASK
76935. DC_PERFMON26_PERFMON_LOW__PERFMON_LOW__SHIFT
76936. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
76937. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
76938. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
76939. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
76940. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
76941. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
76942. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
76943. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
76944. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
76945. DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
76946. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
76947. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
76948. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
76949. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
76950. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
76951. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
76952. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
76953. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
76954. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
76955. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
76956. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
76957. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
76958. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
76959. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
76960. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
76961. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
76962. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
76963. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
76964. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
76965. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
76966. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
76967. DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
76968. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
76969. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
76970. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
76971. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
76972. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
76973. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
76974. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
76975. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
76976. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
76977. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
76978. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
76979. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
76980. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
76981. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
76982. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
76983. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
76984. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
76985. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
76986. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
76987. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
76988. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
76989. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
76990. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
76991. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
76992. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
76993. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
76994. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
76995. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
76996. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
76997. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
76998. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
76999. DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77000. DC_PERFMON27_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77001. DC_PERFMON27_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77002. DC_PERFMON27_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77003. DC_PERFMON27_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77004. DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77005. DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77006. DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77007. DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77008. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77009. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77010. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77011. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77012. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77013. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77014. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77015. DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77016. DC_PERFMON27_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77017. DC_PERFMON27_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77018. DC_PERFMON27_PERFMON_CNTL__PERFMON_STATE_MASK
77019. DC_PERFMON27_PERFMON_CNTL__PERFMON_STATE__SHIFT
77020. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77021. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77022. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77023. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77024. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77025. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77026. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77027. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77028. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77029. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77030. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77031. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77032. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77033. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77034. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77035. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77036. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77037. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77038. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77039. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77040. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77041. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77042. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77043. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77044. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77045. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77046. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77047. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77048. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77049. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77050. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77051. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77052. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77053. DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77054. DC_PERFMON27_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77055. DC_PERFMON27_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77056. DC_PERFMON27_PERFMON_HI__PERFMON_HI_MASK
77057. DC_PERFMON27_PERFMON_HI__PERFMON_HI__SHIFT
77058. DC_PERFMON27_PERFMON_HI__PERFMON_READ_SEL_MASK
77059. DC_PERFMON27_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77060. DC_PERFMON27_PERFMON_LOW__PERFMON_LOW_MASK
77061. DC_PERFMON27_PERFMON_LOW__PERFMON_LOW__SHIFT
77062. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77063. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77064. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77065. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77066. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77067. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77068. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77069. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77070. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77071. DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77072. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77073. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77074. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77075. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77076. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77077. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77078. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77079. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77080. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77081. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77082. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77083. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77084. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77085. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77086. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77087. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77088. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77089. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77090. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77091. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77092. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77093. DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77094. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77095. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77096. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77097. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77098. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77099. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77100. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77101. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77102. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77103. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77104. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77105. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77106. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77107. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77108. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77109. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77110. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77111. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77112. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77113. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77114. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77115. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77116. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77117. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77118. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77119. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77120. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77121. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77122. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77123. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77124. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77125. DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77126. DC_PERFMON28_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77127. DC_PERFMON28_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77128. DC_PERFMON28_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77129. DC_PERFMON28_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77130. DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77131. DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77132. DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77133. DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77134. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77135. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77136. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77137. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77138. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77139. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77140. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77141. DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77142. DC_PERFMON28_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77143. DC_PERFMON28_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77144. DC_PERFMON28_PERFMON_CNTL__PERFMON_STATE_MASK
77145. DC_PERFMON28_PERFMON_CNTL__PERFMON_STATE__SHIFT
77146. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77147. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77148. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77149. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77150. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77151. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77152. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77153. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77154. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77155. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77156. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77157. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77158. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77159. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77160. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77161. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77162. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77163. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77164. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77165. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77166. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77167. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77168. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77169. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77170. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77171. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77172. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77173. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77174. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77175. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77176. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77177. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77178. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77179. DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77180. DC_PERFMON28_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77181. DC_PERFMON28_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77182. DC_PERFMON28_PERFMON_HI__PERFMON_HI_MASK
77183. DC_PERFMON28_PERFMON_HI__PERFMON_HI__SHIFT
77184. DC_PERFMON28_PERFMON_HI__PERFMON_READ_SEL_MASK
77185. DC_PERFMON28_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77186. DC_PERFMON28_PERFMON_LOW__PERFMON_LOW_MASK
77187. DC_PERFMON28_PERFMON_LOW__PERFMON_LOW__SHIFT
77188. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77189. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77190. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77191. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77192. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77193. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77194. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77195. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77196. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77197. DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77198. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77199. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77200. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77201. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77202. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77203. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77204. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77205. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77206. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77207. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77208. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77209. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77210. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77211. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77212. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77213. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77214. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77215. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77216. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77217. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77218. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77219. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77220. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77221. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77222. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77223. DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77224. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77225. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77226. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77227. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77228. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77229. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77230. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77231. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77232. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77233. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77234. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77235. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77236. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77237. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77238. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77239. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77240. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77241. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77242. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77243. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77244. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77245. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77246. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77247. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77248. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77249. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77250. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77251. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77252. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77253. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77254. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77255. DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77256. DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77257. DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77258. DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77259. DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77260. DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77261. DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77262. DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77263. DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77264. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77265. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77266. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77267. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77268. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77269. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77270. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77271. DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77272. DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77273. DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77274. DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK
77275. DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT
77276. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77277. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77278. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77279. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77280. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77281. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77282. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77283. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77284. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77285. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77286. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77287. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77288. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77289. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77290. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77291. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77292. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77293. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77294. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77295. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77296. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77297. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77298. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77299. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77300. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77301. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77302. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77303. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77304. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77305. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77306. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77307. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77308. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77309. DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77310. DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77311. DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77312. DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK
77313. DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT
77314. DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK
77315. DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77316. DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK
77317. DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT
77318. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77319. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77320. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77321. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77322. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77323. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77324. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77325. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77326. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77327. DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77328. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77329. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77330. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77331. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77332. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77333. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77334. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77335. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77336. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77337. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77338. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77339. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77340. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77341. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77342. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77343. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77344. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77345. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77346. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77347. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77348. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77349. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77350. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77351. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77352. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77353. DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77354. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77355. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77356. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77357. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77358. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77359. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77360. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77361. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77362. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77363. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77364. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77365. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77366. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77367. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77368. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77369. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77370. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77371. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77372. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77373. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77374. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77375. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77376. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77377. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77378. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77379. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77380. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77381. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77382. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77383. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77384. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77385. DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77386. DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77387. DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77388. DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77389. DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77390. DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77391. DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77392. DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77393. DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77394. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77395. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77396. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77397. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77398. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77399. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77400. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77401. DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77402. DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77403. DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77404. DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK
77405. DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT
77406. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77407. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77408. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77409. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77410. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77411. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77412. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77413. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77414. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77415. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77416. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77417. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77418. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77419. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77420. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77421. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77422. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77423. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77424. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77425. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77426. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77427. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77428. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77429. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77430. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77431. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77432. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77433. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77434. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77435. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77436. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77437. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77438. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77439. DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77440. DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77441. DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77442. DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK
77443. DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT
77444. DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK
77445. DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77446. DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK
77447. DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT
77448. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77449. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77450. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77451. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77452. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77453. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77454. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77455. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77456. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77457. DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77458. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77459. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77460. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77461. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77462. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77463. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77464. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77465. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77466. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77467. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77468. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77469. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77470. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77471. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77472. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77473. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77474. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77475. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77476. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77477. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77478. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77479. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77480. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77481. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77482. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77483. DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77484. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77485. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77486. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77487. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77488. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77489. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77490. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77491. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77492. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77493. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77494. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77495. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77496. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77497. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77498. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77499. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77500. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77501. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77502. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77503. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77504. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77505. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77506. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77507. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77508. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77509. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77510. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77511. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77512. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77513. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77514. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77515. DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77516. DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77517. DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77518. DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77519. DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77520. DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77521. DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77522. DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77523. DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77524. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77525. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77526. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77527. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77528. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77529. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77530. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77531. DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77532. DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77533. DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77534. DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK
77535. DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT
77536. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77537. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77538. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77539. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77540. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77541. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77542. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77543. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77544. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77545. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77546. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77547. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77548. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77549. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77550. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77551. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77552. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77553. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77554. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77555. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77556. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77557. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77558. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77559. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77560. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77561. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77562. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77563. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77564. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77565. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77566. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77567. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77568. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77569. DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77570. DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77571. DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77572. DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK
77573. DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT
77574. DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK
77575. DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77576. DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK
77577. DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT
77578. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77579. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77580. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77581. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77582. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77583. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77584. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77585. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77586. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77587. DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77588. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77589. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77590. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77591. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77592. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77593. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77594. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77595. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77596. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77597. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77598. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77599. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77600. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77601. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77602. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77603. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77604. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77605. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77606. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77607. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77608. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77609. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77610. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77611. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77612. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77613. DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77614. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77615. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77616. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77617. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77618. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77619. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77620. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77621. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77622. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77623. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77624. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77625. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77626. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77627. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77628. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77629. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77630. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77631. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77632. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77633. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77634. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77635. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77636. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77637. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77638. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77639. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77640. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77641. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77642. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77643. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77644. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77645. DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77646. DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77647. DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77648. DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77649. DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77650. DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77651. DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77652. DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77653. DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77654. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77655. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77656. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77657. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77658. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77659. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77660. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77661. DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77662. DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77663. DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77664. DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK
77665. DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT
77666. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77667. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77668. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77669. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77670. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77671. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77672. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77673. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77674. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77675. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77676. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77677. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77678. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77679. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77680. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77681. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77682. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77683. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77684. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77685. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77686. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77687. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77688. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77689. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77690. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77691. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77692. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77693. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77694. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77695. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77696. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77697. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77698. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77699. DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77700. DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77701. DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77702. DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK
77703. DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT
77704. DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK
77705. DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77706. DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK
77707. DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT
77708. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77709. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77710. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77711. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77712. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77713. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77714. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77715. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77716. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77717. DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77718. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77719. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77720. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77721. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77722. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77723. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77724. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77725. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77726. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77727. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77728. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77729. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77730. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77731. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77732. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77733. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77734. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77735. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77736. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77737. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77738. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77739. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77740. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77741. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77742. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77743. DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77744. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77745. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77746. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77747. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77748. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77749. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77750. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77751. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77752. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77753. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77754. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77755. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77756. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77757. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77758. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77759. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77760. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77761. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77762. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77763. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77764. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77765. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77766. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77767. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77768. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77769. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77770. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77771. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77772. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77773. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77774. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77775. DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77776. DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77777. DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77778. DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77779. DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77780. DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77781. DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77782. DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77783. DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77784. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77785. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77786. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77787. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77788. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77789. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77790. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77791. DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77792. DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77793. DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77794. DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK
77795. DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT
77796. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77797. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77798. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77799. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77800. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77801. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77802. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77803. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77804. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77805. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77806. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77807. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77808. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77809. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77810. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77811. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77812. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77813. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77814. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77815. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77816. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77817. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77818. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77819. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77820. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77821. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77822. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77823. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77824. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77825. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77826. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77827. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77828. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77829. DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77830. DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77831. DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77832. DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK
77833. DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT
77834. DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK
77835. DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77836. DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK
77837. DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT
77838. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77839. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77840. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77841. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77842. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77843. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77844. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77845. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77846. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77847. DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77848. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77849. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77850. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77851. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77852. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77853. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77854. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77855. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77856. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77857. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77858. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77859. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77860. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77861. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77862. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77863. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77864. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77865. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77866. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77867. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77868. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77869. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
77870. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
77871. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
77872. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
77873. DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
77874. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
77875. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
77876. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
77877. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
77878. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
77879. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
77880. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
77881. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
77882. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
77883. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
77884. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
77885. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
77886. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
77887. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
77888. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
77889. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
77890. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
77891. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
77892. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
77893. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
77894. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
77895. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
77896. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
77897. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
77898. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
77899. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
77900. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
77901. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
77902. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
77903. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
77904. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
77905. DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
77906. DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
77907. DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
77908. DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
77909. DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
77910. DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
77911. DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
77912. DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
77913. DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
77914. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
77915. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
77916. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
77917. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
77918. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
77919. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
77920. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
77921. DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
77922. DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
77923. DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
77924. DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK
77925. DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT
77926. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
77927. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
77928. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
77929. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
77930. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
77931. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
77932. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
77933. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
77934. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
77935. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
77936. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
77937. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
77938. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
77939. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
77940. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
77941. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
77942. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
77943. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
77944. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
77945. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
77946. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
77947. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
77948. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
77949. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
77950. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
77951. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
77952. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
77953. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
77954. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
77955. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
77956. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
77957. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
77958. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
77959. DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
77960. DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
77961. DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
77962. DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK
77963. DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT
77964. DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK
77965. DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT
77966. DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK
77967. DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT
77968. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
77969. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
77970. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
77971. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
77972. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
77973. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
77974. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
77975. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
77976. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
77977. DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
77978. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
77979. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
77980. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
77981. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
77982. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
77983. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
77984. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
77985. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
77986. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
77987. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
77988. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
77989. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
77990. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
77991. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
77992. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
77993. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
77994. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
77995. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
77996. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
77997. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
77998. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
77999. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
78000. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
78001. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
78002. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
78003. DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
78004. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
78005. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
78006. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
78007. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
78008. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
78009. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
78010. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
78011. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
78012. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
78013. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
78014. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
78015. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
78016. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
78017. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
78018. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
78019. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
78020. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
78021. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
78022. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
78023. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
78024. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
78025. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
78026. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
78027. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
78028. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
78029. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
78030. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
78031. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
78032. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
78033. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
78034. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
78035. DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
78036. DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
78037. DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
78038. DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
78039. DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
78040. DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
78041. DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
78042. DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
78043. DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
78044. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
78045. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
78046. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
78047. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
78048. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
78049. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
78050. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
78051. DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
78052. DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
78053. DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
78054. DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK
78055. DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT
78056. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
78057. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
78058. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
78059. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
78060. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
78061. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
78062. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
78063. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
78064. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
78065. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
78066. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
78067. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
78068. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
78069. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
78070. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
78071. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
78072. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
78073. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
78074. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
78075. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
78076. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
78077. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
78078. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
78079. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
78080. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
78081. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
78082. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
78083. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
78084. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
78085. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
78086. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
78087. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
78088. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
78089. DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
78090. DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
78091. DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
78092. DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK
78093. DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT
78094. DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK
78095. DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT
78096. DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK
78097. DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT
78098. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK
78099. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT
78100. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK
78101. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT
78102. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
78103. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
78104. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK
78105. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT
78106. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK
78107. DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT
78108. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
78109. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
78110. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
78111. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
78112. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
78113. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
78114. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
78115. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
78116. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
78117. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
78118. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
78119. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
78120. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
78121. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
78122. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
78123. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
78124. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
78125. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
78126. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
78127. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
78128. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
78129. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
78130. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
78131. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
78132. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
78133. DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
78134. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
78135. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
78136. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
78137. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
78138. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
78139. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
78140. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
78141. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
78142. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
78143. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
78144. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
78145. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
78146. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
78147. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
78148. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
78149. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
78150. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
78151. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
78152. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
78153. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
78154. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
78155. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
78156. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
78157. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
78158. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
78159. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
78160. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
78161. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
78162. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
78163. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
78164. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
78165. DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
78166. DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
78167. DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
78168. DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
78169. DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
78170. DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK
78171. DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT
78172. DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK
78173. DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT
78174. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
78175. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
78176. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
78177. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
78178. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
78179. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
78180. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
78181. DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
78182. DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
78183. DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
78184. DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK
78185. DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT
78186. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
78187. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
78188. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
78189. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
78190. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
78191. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
78192. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
78193. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
78194. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
78195. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
78196. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
78197. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
78198. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
78199. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
78200. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
78201. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
78202. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
78203. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
78204. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
78205. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
78206. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
78207. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
78208. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
78209. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
78210. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
78211. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
78212. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
78213. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
78214. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
78215. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
78216. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
78217. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
78218. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
78219. DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
78220. DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
78221. DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
78222. DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK
78223. DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT
78224. DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK
78225. DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT
78226. DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK
78227. DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT
78228. DC_PERF_CNTR
78229. DC_PERF_CNTR_LCB
78230. DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK
78231. DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT
78232. DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK
78233. DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT
78234. DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK
78235. DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT
78236. DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK
78237. DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT
78238. DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK
78239. DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT
78240. DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK
78241. DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT
78242. DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK
78243. DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT
78244. DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK
78245. DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT
78246. DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK
78247. DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT
78248. DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK
78249. DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT
78250. DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK
78251. DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT
78252. DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK
78253. DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT
78254. DC_PLANE_TYPE_DCE_RGB
78255. DC_PLANE_TYPE_DCE_UNDERLAY
78256. DC_PLANE_TYPE_DCN_UNIVERSAL
78257. DC_PLANE_TYPE_INVALID
78258. DC_PLANE_UPDATE_TIMES_MAX
78259. DC_POWER_STATE_OFF
78260. DC_POWER_STATE_ON
78261. DC_POWER_STATE_STANDBY
78262. DC_POWER_STATE_SUSPEND
78263. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK
78264. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT
78265. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK
78266. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT
78267. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK
78268. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT
78269. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK
78270. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT
78271. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK
78272. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT
78273. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK
78274. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT
78275. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK
78276. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT
78277. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK
78278. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT
78279. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK
78280. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT
78281. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK
78282. DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT
78283. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY_MASK
78284. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY__SHIFT
78285. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS_MASK
78286. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS__SHIFT
78287. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY_MASK
78288. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY__SHIFT
78289. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK
78290. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS__SHIFT
78291. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY_MASK
78292. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY__SHIFT
78293. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS_MASK
78294. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS__SHIFT
78295. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK
78296. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT
78297. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK
78298. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT
78299. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK
78300. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT
78301. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK
78302. DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT
78303. DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY_MASK
78304. DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY__SHIFT
78305. DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS_MASK
78306. DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS__SHIFT
78307. DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY_MASK
78308. DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY__SHIFT
78309. DC_RD
78310. DC_RD_HIT
78311. DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK
78312. DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT
78313. DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK
78314. DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT
78315. DC_REG_COUNT
78316. DC_RESV
78317. DC_RL_CH
78318. DC_ROTATED_MICRO_TILING
78319. DC_RSVD_0
78320. DC_RSVD_1
78321. DC_RSVD_2
78322. DC_RSVD_3
78323. DC_RSVD_4
78324. DC_RSVD_5
78325. DC_RTC_ALARM
78326. DC_RTC_CMD_MASK
78327. DC_RTC_CONTROL
78328. DC_RTC_GO_BUSY
78329. DC_RTC_INTENABLE
78330. DC_RTC_INTFLAG_CLEAR
78331. DC_RTC_REFERENCE
78332. DC_RTC_TIME
78333. DC_SCRATCH
78334. DC_SC_VL_VAL
78335. DC_SESSION
78336. DC_SFRESET
78337. DC_SFWT
78338. DC_SIZE
78339. DC_SLES
78340. DC_SMU_INTERRUPT_ENABLE
78341. DC_SNDRSU
78342. DC_SS_LINE_CMP
78343. DC_STALL
78344. DC_STAT
78345. DC_STATE_DEBUG
78346. DC_STATE_DEBUG_MASK_CORES
78347. DC_STATE_DEBUG_MASK_MEMORY_UP
78348. DC_STATE_DISABLE
78349. DC_STATE_EN
78350. DC_STATE_EN_DC9
78351. DC_STATE_EN_UPTO_DC5
78352. DC_STATE_EN_UPTO_DC5_DC6_MASK
78353. DC_STATE_EN_UPTO_DC6
78354. DC_STATUS
78355. DC_STREAM_H_
78356. DC_STREAM_TIME_DELAY
78357. DC_STUTTER_CNTL
78358. DC_STUTTER_ENABLE_A
78359. DC_STUTTER_ENABLE_B
78360. DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED
78361. DC_SW_256B_S
78362. DC_SW_256_D
78363. DC_SW_256_R
78364. DC_SW_4KB_D
78365. DC_SW_4KB_D_X
78366. DC_SW_4KB_R
78367. DC_SW_4KB_R_X
78368. DC_SW_4KB_S
78369. DC_SW_4KB_S_X
78370. DC_SW_64KB_D
78371. DC_SW_64KB_D_T
78372. DC_SW_64KB_D_X
78373. DC_SW_64KB_R
78374. DC_SW_64KB_R_X
78375. DC_SW_64KB_S
78376. DC_SW_64KB_S_T
78377. DC_SW_64KB_S_X
78378. DC_SW_LINEAR
78379. DC_SW_MAX
78380. DC_SW_UNKNOWN
78381. DC_SW_VAR_D
78382. DC_SW_VAR_D_X
78383. DC_SW_VAR_R
78384. DC_SW_VAR_R_X
78385. DC_SW_VAR_S
78386. DC_SW_VAR_S_X
78387. DC_SYNC_INFO
78388. DC_TAG_VALID
78389. DC_TCFG_BKRT
78390. DC_TCFG_BLKE
78391. DC_TCFG_BLNK
78392. DC_TCFG_CDCE
78393. DC_TCFG_CHSP
78394. DC_TCFG_CVSP
78395. DC_TCFG_DDCI
78396. DC_TCFG_DDCK
78397. DC_TCFG_DNA
78398. DC_TCFG_FCEN
78399. DC_TCFG_FHSP
78400. DC_TCFG_FPPE
78401. DC_TCFG_FVSP
78402. DC_TCFG_HSYE
78403. DC_TCFG_INTL
78404. DC_TCFG_PLNR
78405. DC_TCFG_PSD_MASK
78406. DC_TCFG_PSD_POS
78407. DC_TCFG_PXDB
78408. DC_TCFG_SENS
78409. DC_TCFG_TGEN
78410. DC_TCFG_VIEN
78411. DC_TCFG_VINT
78412. DC_TCFG_VNA
78413. DC_TCFG_VSYE
78414. DC_TESTMODE
78415. DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK
78416. DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT
78417. DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK
78418. DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT
78419. DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK
78420. DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT
78421. DC_THIN_MICRO_TILING
78422. DC_TIMING_CFG
78423. DC_TIMING_STANDARD_CEA770
78424. DC_TIMING_STANDARD_CEA861
78425. DC_TIMING_STANDARD_CVT
78426. DC_TIMING_STANDARD_CVT_RB
78427. DC_TIMING_STANDARD_DMT
78428. DC_TIMING_STANDARD_EXPLICIT
78429. DC_TIMING_STANDARD_GTF
78430. DC_TIMING_STANDARD_HDMI
78431. DC_TIMING_STANDARD_MAX
78432. DC_TIMING_STANDARD_TV_NTSC
78433. DC_TIMING_STANDARD_TV_NTSC_J
78434. DC_TIMING_STANDARD_TV_PAL
78435. DC_TIMING_STANDARD_TV_PAL_CN
78436. DC_TIMING_STANDARD_TV_PAL_M
78437. DC_TIMING_STANDARD_TV_SECAM
78438. DC_TIMING_STANDARD_UNDEFINED
78439. DC_TIMING_STANDARD_USER_OVERRIDE
78440. DC_TOP_CSRS
78441. DC_TRIPLEBUFFER_DISABLE
78442. DC_TRIPLEBUFFER_ENABLE
78443. DC_TYPES_H_
78444. DC_UNLOCK
78445. DC_UNLOCKDEV
78446. DC_UNLOCK_CODE
78447. DC_UNLOCK_LOCK
78448. DC_UNLOCK_UNLOCK
78449. DC_VBI_EVEN_CTL
78450. DC_VBI_HOR
78451. DC_VBI_LN_EVEN
78452. DC_VBI_LN_ODD
78453. DC_VBI_ODD_CTL
78454. DC_VBI_PITCH
78455. DC_VBUSSTAT
78456. DC_VENDP
78457. DC_VER
78458. DC_VFILT_COUNT
78459. DC_VIDEO_POWER_AFTER_RESET
78460. DC_VIDEO_POWER_HIBERNATE
78461. DC_VIDEO_POWER_MAXIMUM
78462. DC_VIDEO_POWER_OFF
78463. DC_VIDEO_POWER_ON
78464. DC_VIDEO_POWER_SHUTDOWN
78465. DC_VIDEO_POWER_STANDBY
78466. DC_VIDEO_POWER_SUSPEND
78467. DC_VIDEO_POWER_ULPS
78468. DC_VIDEO_POWER_UNSPECIFIED
78469. DC_VID_DS_DELTA
78470. DC_VID_EVEN_U_ST_OFFSET
78471. DC_VID_EVEN_V_ST_OFFSET
78472. DC_VID_EVEN_Y_ST_OFFSET
78473. DC_VID_ST_OFFSET
78474. DC_VID_U_ST_OFFSET
78475. DC_VID_V_ST_OFFSET
78476. DC_VID_YUV_PITCH
78477. DC_VID_Y_ST_OFFSET
78478. DC_V_ACTIVE_EVEN_TIMING
78479. DC_V_ACTIVE_TIMING
78480. DC_V_BLANK_EVEN_TIMING
78481. DC_V_BLANK_TIMING
78482. DC_V_LINE_CNT
78483. DC_V_SYNC_EVEN_TIMING
78484. DC_V_SYNC_TIMING
78485. DC_V_TIMING_1
78486. DC_V_TIMING_2
78487. DC_V_TIMING_3
78488. DC_WINBUF_ADDR_H_OFFSET
78489. DC_WINBUF_ADDR_H_OFFSET_NS
78490. DC_WINBUF_ADDR_V_OFFSET
78491. DC_WINBUF_ADDR_V_OFFSET_NS
78492. DC_WINBUF_AD_UFLOW_STATUS
78493. DC_WINBUF_BD_UFLOW_STATUS
78494. DC_WINBUF_CDE_CONTROL
78495. DC_WINBUF_CD_UFLOW_STATUS
78496. DC_WINBUF_CROPPED_POINT
78497. DC_WINBUF_START_ADDR
78498. DC_WINBUF_START_ADDR_HI
78499. DC_WINBUF_START_ADDR_NS
78500. DC_WINBUF_START_ADDR_U
78501. DC_WINBUF_START_ADDR_U_NS
78502. DC_WINBUF_START_ADDR_V
78503. DC_WINBUF_START_ADDR_V_NS
78504. DC_WINBUF_SURFACE_KIND
78505. DC_WINBUF_SURFACE_KIND_BLOCK
78506. DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT
78507. DC_WINBUF_SURFACE_KIND_PITCH
78508. DC_WINBUF_SURFACE_KIND_TILED
78509. DC_WINBUF_UFLOW_STATUS
78510. DC_WIN_BLEND_1WIN
78511. DC_WIN_BLEND_2WIN_X
78512. DC_WIN_BLEND_2WIN_Y
78513. DC_WIN_BLEND_3WIN_XY
78514. DC_WIN_BLEND_LAYER_CONTROL
78515. DC_WIN_BLEND_MATCH_SELECT
78516. DC_WIN_BLEND_NOKEY
78517. DC_WIN_BLEND_NOMATCH_SELECT
78518. DC_WIN_BUFFER_ADDR_MODE
78519. DC_WIN_BUFFER_ADDR_MODE_LINEAR
78520. DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
78521. DC_WIN_BUFFER_ADDR_MODE_TILE
78522. DC_WIN_BUFFER_ADDR_MODE_TILE_UV
78523. DC_WIN_BUFFER_CONTROL
78524. DC_WIN_BUF_STRIDE
78525. DC_WIN_BYTE_SWAP
78526. DC_WIN_COLOR_DEPTH
78527. DC_WIN_CORE_ACT_CONTROL
78528. DC_WIN_CORE_IHUB_LINEBUF_CONFIG
78529. DC_WIN_CORE_IHUB_THREAD_GROUP
78530. DC_WIN_CORE_IHUB_WGRP_FETCH_METER
78531. DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA
78532. DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB
78533. DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG
78534. DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER
78535. DC_WIN_CORE_WINDOWGROUP_SET_CONTROL
78536. DC_WIN_CROPPED_SIZE
78537. DC_WIN_CSC_KUB
78538. DC_WIN_CSC_KUG
78539. DC_WIN_CSC_KUR
78540. DC_WIN_CSC_KVB
78541. DC_WIN_CSC_KVG
78542. DC_WIN_CSC_KVR
78543. DC_WIN_CSC_KYRGB
78544. DC_WIN_CSC_YOF
78545. DC_WIN_DDA_INC
78546. DC_WIN_DV_CONTROL
78547. DC_WIN_HP_FETCH_CONTROL
78548. DC_WIN_H_FILTER_P
78549. DC_WIN_H_INITIAL_DDA
78550. DC_WIN_LINE_STRIDE
78551. DC_WIN_PLANAR_STORAGE
78552. DC_WIN_POSITION
78553. DC_WIN_PRECOMP_WGRP_PARAMS
78554. DC_WIN_PRESCALED_SIZE
78555. DC_WIN_SET_PARAMS
78556. DC_WIN_SIZE
78557. DC_WIN_UV_BUF_STRIDE
78558. DC_WIN_V_FILTER_P
78559. DC_WIN_V_INITIAL_DDA
78560. DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER
78561. DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE
78562. DC_WIN_WINDOW_SET_CONTROL
78563. DC_WIN_WIN_OPTIONS
78564. DC_WKUPCS
78565. DC_WR
78566. DC_WR_CH_ADDR
78567. DC_WR_CH_CONF
78568. DC_WR_CH_CONF_DISP_ID_ASYNC
78569. DC_WR_CH_CONF_DISP_ID_PARALLEL
78570. DC_WR_CH_CONF_DISP_ID_SERIAL
78571. DC_WR_CH_CONF_FIELD_MODE
78572. DC_WR_CH_CONF_PROG_DISP_ID
78573. DC_WR_CH_CONF_PROG_DI_ID
78574. DC_WR_CH_CONF_PROG_TYPE_MASK
78575. DC_WR_CH_CONF_PROG_TYPE_NORMAL
78576. DC_WR_CH_CONF_WORD_SIZE_16
78577. DC_WR_CH_CONF_WORD_SIZE_24
78578. DC_WR_CH_CONF_WORD_SIZE_32
78579. DC_WR_CH_CONF_WORD_SIZE_8
78580. DC_WR_HIT
78581. DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK
78582. DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT
78583. DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK
78584. DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT
78585. DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK
78586. DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT
78587. DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK
78588. DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT
78589. DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK
78590. DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT
78591. DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK
78592. DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT
78593. DC_ZERO
78594. DC__ABM_PRESENT
78595. DC__ABM_PRESENT__0
78596. DC__AFMT_MEM_PG
78597. DC__AFMT_MEM_PG__0
78598. DC__AVSYNC_PRESENT
78599. DC__AVSYNC_PRESENT__0
78600. DC__AZ_MEM_PG
78601. DC__AZ_MEM_PG__1
78602. DC__BLON_TYPE
78603. DC__BLON_TYPE__DEDICATED
78604. DC__BPHYC_PLL_PRESENT
78605. DC__BPHYC_PLL_PRESENT__0
78606. DC__BPHYC_UNIPHY_PRESENT
78607. DC__BPHYC_UNIPHY_PRESENT__0
78608. DC__CM_MEM_PG
78609. DC__CM_MEM_PG__0
78610. DC__DACA_PRESENT
78611. DC__DACA_PRESENT__0
78612. DC__DACB_PRESENT
78613. DC__DACB_PRESENT__0
78614. DC__DAC_RESYNC_FIFO_SIZE
78615. DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT
78616. DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT
78617. DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT
78618. DC__DAC_RESYNC_FIFO_SIZE__12
78619. DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT
78620. DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT
78621. DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT
78622. DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT
78623. DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT
78624. DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT
78625. DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT
78626. DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT
78627. DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT
78628. DC__DAC_RESYNC_FIFO_SIZE__MAX
78629. DC__DAC_RESYNC_FIFO_SIZE__MAX__16
78630. DC__DCHUBP_DPP_SF_PIXEL_CREDITS
78631. DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9
78632. DC__DENTIST_INTERFACE_PRESENT
78633. DC__DENTIST_INTERFACE_PRESENT__1
78634. DC__DIGITAL_BYPASS_PRESENT
78635. DC__DIGITAL_BYPASS_PRESENT__0
78636. DC__DIG_FEATURES__DP_MST_PRESENT
78637. DC__DIG_FEATURES__DP_MST_PRESENT__1
78638. DC__DIG_FEATURES__DP_PRESENT
78639. DC__DIG_FEATURES__DP_PRESENT__1
78640. DC__DIG_FEATURES__HDMI_PRESENT
78641. DC__DIG_FEATURES__HDMI_PRESENT__1
78642. DC__DIG_LP_FEATURES__DP_MST_PRESENT
78643. DC__DIG_LP_FEATURES__DP_MST_PRESENT__0
78644. DC__DIG_LP_FEATURES__DP_PRESENT
78645. DC__DIG_LP_FEATURES__DP_PRESENT__1
78646. DC__DIG_LP_FEATURES__HDMI_PRESENT
78647. DC__DIG_LP_FEATURES__HDMI_PRESENT__0
78648. DC__DIG_RESYNC_FIFO_SIZE
78649. DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT
78650. DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT
78651. DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT
78652. DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT
78653. DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT
78654. DC__DIG_RESYNC_FIFO_SIZE__14
78655. DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT
78656. DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT
78657. DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT
78658. DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT
78659. DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT
78660. DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT
78661. DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT
78662. DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT
78663. DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT
78664. DC__DIG_RESYNC_FIFO_SIZE__MAX
78665. DC__DIG_RESYNC_FIFO_SIZE__MAX__16
78666. DC__DISPLAY_WB_PRESENT
78667. DC__DISPLAY_WB_PRESENT__1
78668. DC__DMCU_MEM1P1024X32BQS_MEM_PG
78669. DC__DMCU_MEM1P1024X32BQS_MEM_PG__1
78670. DC__DPDEBUG_PRESENT
78671. DC__DPDEBUG_PRESENT__0
78672. DC__DPP_MPC_SF_PIXEL_CREDITS
78673. DC__DPP_MPC_SF_PIXEL_CREDITS__9
78674. DC__DP_MEM_PG
78675. DC__DP_MEM_PG__0
78676. DC__DSCL_MEM_PG
78677. DC__DSCL_MEM_PG__0
78678. DC__DSI_MEM_PG
78679. DC__DSI_MEM_PG__0
78680. DC__DSI_PRESENT
78681. DC__DSI_PRESENT__0
78682. DC__DTMTEST_PRESENT
78683. DC__DTMTEST_PRESENT__0
78684. DC__DVO_17BIT_MAPPING
78685. DC__DVO_17BIT_MAPPING__0
78686. DC__DVO_PRESENT
78687. DC__DVO_PRESENT__0
78688. DC__DVO_RESYNC_FIFO_SIZE
78689. DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT
78690. DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT
78691. DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT
78692. DC__DVO_RESYNC_FIFO_SIZE__12
78693. DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT
78694. DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT
78695. DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT
78696. DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT
78697. DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT
78698. DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT
78699. DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT
78700. DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT
78701. DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT
78702. DC__DVO_RESYNC_FIFO_SIZE__MAX
78703. DC__DVO_RESYNC_FIFO_SIZE__MAX__16
78704. DC__DWB_CSC_PRESENT
78705. DC__DWB_CSC_PRESENT__0
78706. DC__DWB_LUMA_SCL_PRESENT
78707. DC__DWB_LUMA_SCL_PRESENT__0
78708. DC__FMT_MEM_PG
78709. DC__FMT_MEM_PG__0
78710. DC__FMT_SRC_SEL_PRESENT
78711. DC__FMT_SRC_SEL_PRESENT__0
78712. DC__GENERICA_PRESENT
78713. DC__GENERICA_PRESENT__1
78714. DC__GENERICB_PRESENT
78715. DC__GENERICB_PRESENT__1
78716. DC__GENERICC_PRESENT
78717. DC__GENERICC_PRESENT__0
78718. DC__GENERICD_PRESENT
78719. DC__GENERICD_PRESENT__0
78720. DC__GENERICE_PRESENT
78721. DC__GENERICE_PRESENT__0
78722. DC__GENERICF_PRESENT
78723. DC__GENERICF_PRESENT__0
78724. DC__GENERICG_PRESENT
78725. DC__GENERICG_PRESENT__0
78726. DC__HCID_HWMAJVER
78727. DC__HCID_HWMAJVER__1
78728. DC__HCID_HWMINVER
78729. DC__HCID_HWMINVER__0
78730. DC__HCID_HWREV
78731. DC__HCID_HWREV__0
78732. DC__HDMI_MEM_PG
78733. DC__HDMI_MEM_PG__0
78734. DC__HUBBUB_RET_ROB_MEM_PG
78735. DC__HUBBUB_RET_ROB_MEM_PG__0
78736. DC__HUBBUB_RET_ZERO_MEM_PG
78737. DC__HUBBUB_RET_ZERO_MEM_PG__0
78738. DC__HUBBUB_SDP_TAG_EXT_MEM_PG
78739. DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0
78740. DC__HUBBUB_SDP_TAG_INT_MEM_PG
78741. DC__HUBBUB_SDP_TAG_INT_MEM_PG__0
78742. DC__HUBPREQ_DPTE_MEM_PG
78743. DC__HUBPREQ_DPTE_MEM_PG__0
78744. DC__HUBPREQ_META_MEM_PG
78745. DC__HUBPREQ_META_MEM_PG__0
78746. DC__HUBPREQ_MPTE_MEM_PG
78747. DC__HUBPREQ_MPTE_MEM_PG__0
78748. DC__HUBPRET_CUR_CDC_MEM_PG
78749. DC__HUBPRET_CUR_CDC_MEM_PG__0
78750. DC__HUBPRET_CUR_ROB_MEM_PG
78751. DC__HUBPRET_CUR_ROB_MEM_PG__0
78752. DC__HUBPRET_DET_MEM_PG
78753. DC__HUBPRET_DET_MEM_PG__0
78754. DC__HUBPRET_PIX_CDC_MEM_PG
78755. DC__HUBPRET_PIX_CDC_MEM_PG__0
78756. DC__I2C_MEM_PG
78757. DC__I2C_MEM_PG__0
78758. DC__I2S0_AND_SPDIF0_PRESENT
78759. DC__I2S0_AND_SPDIF0_PRESENT__0
78760. DC__I2S1_PRESENT
78761. DC__I2S1_PRESENT__0
78762. DC__MEM_CDC_PRESENT
78763. DC__MEM_CDC_PRESENT__1
78764. DC__MEM_PG
78765. DC__MEM_PG__1
78766. DC__MPC_OPP_SF_PIXEL_CREDITS
78767. DC__MPC_OPP_SF_PIXEL_CREDITS__8
78768. DC__MVP_PRESENT
78769. DC__MVP_PRESENT__0
78770. DC__NB_STUTTER_MODE_PRESENT
78771. DC__NB_STUTTER_MODE_PRESENT__0
78772. DC__NUM_ABM
78773. DC__NUM_ABM__0_PRESENT
78774. DC__NUM_ABM__1
78775. DC__NUM_ABM__MAX
78776. DC__NUM_ABM__MAX__2
78777. DC__NUM_AUDIO_ENDPOINTS
78778. DC__NUM_AUDIO_ENDPOINTS__0_PRESENT
78779. DC__NUM_AUDIO_ENDPOINTS__1_PRESENT
78780. DC__NUM_AUDIO_ENDPOINTS__2_PRESENT
78781. DC__NUM_AUDIO_ENDPOINTS__3_PRESENT
78782. DC__NUM_AUDIO_ENDPOINTS__4_PRESENT
78783. DC__NUM_AUDIO_ENDPOINTS__5_PRESENT
78784. DC__NUM_AUDIO_ENDPOINTS__6
78785. DC__NUM_AUDIO_ENDPOINTS__MAX
78786. DC__NUM_AUDIO_ENDPOINTS__MAX__8
78787. DC__NUM_AUDIO_INPUT_ENDPOINTS
78788. DC__NUM_AUDIO_INPUT_ENDPOINTS__0
78789. DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX
78790. DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8
78791. DC__NUM_AUDIO_INPUT_STREAMS
78792. DC__NUM_AUDIO_INPUT_STREAMS__0
78793. DC__NUM_AUDIO_INPUT_STREAMS__MAX
78794. DC__NUM_AUDIO_INPUT_STREAMS__MAX__8
78795. DC__NUM_AUDIO_PLL
78796. DC__NUM_AUDIO_PLL__0
78797. DC__NUM_AUDIO_PLL__MAX
78798. DC__NUM_AUDIO_PLL__MAX__2
78799. DC__NUM_AUDIO_STREAMS
78800. DC__NUM_AUDIO_STREAMS__0_PRESENT
78801. DC__NUM_AUDIO_STREAMS__1_PRESENT
78802. DC__NUM_AUDIO_STREAMS__2_PRESENT
78803. DC__NUM_AUDIO_STREAMS__3_PRESENT
78804. DC__NUM_AUDIO_STREAMS__4
78805. DC__NUM_AUDIO_STREAMS__MAX
78806. DC__NUM_AUDIO_STREAMS__MAX__8
78807. DC__NUM_AUX
78808. DC__NUM_AUX__0_PRESENT
78809. DC__NUM_AUX__1_PRESENT
78810. DC__NUM_AUX__2_PRESENT
78811. DC__NUM_AUX__3_PRESENT
78812. DC__NUM_AUX__4
78813. DC__NUM_AUX__MAX
78814. DC__NUM_AUX__MAX__6
78815. DC__NUM_CASCADED_PLL
78816. DC__NUM_CASCADED_PLL__0
78817. DC__NUM_CASCADED_PLL__MAX
78818. DC__NUM_CASCADED_PLL__MAX__3
78819. DC__NUM_CURSOR
78820. DC__NUM_CURSOR__0_PRESENT
78821. DC__NUM_CURSOR__1
78822. DC__NUM_CURSOR__MAX
78823. DC__NUM_CURSOR__MAX__2
78824. DC__NUM_CWB
78825. DC__NUM_CWB__0
78826. DC__NUM_CWB__MAX
78827. DC__NUM_CWB__MAX__2
78828. DC__NUM_DBG_REGS
78829. DC__NUM_DBG_REGS__36
78830. DC__NUM_DDC_PAIRS
78831. DC__NUM_DDC_PAIRS__0_PRESENT
78832. DC__NUM_DDC_PAIRS__1_PRESENT
78833. DC__NUM_DDC_PAIRS__2_PRESENT
78834. DC__NUM_DDC_PAIRS__3_PRESENT
78835. DC__NUM_DDC_PAIRS__4
78836. DC__NUM_DDC_PAIRS__MAX
78837. DC__NUM_DDC_PAIRS__MAX__6
78838. DC__NUM_DIG
78839. DC__NUM_DIG_LP
78840. DC__NUM_DIG_LP__0
78841. DC__NUM_DIG_LP__MAX
78842. DC__NUM_DIG_LP__MAX__2
78843. DC__NUM_DIG__0_PRESENT
78844. DC__NUM_DIG__1_PRESENT
78845. DC__NUM_DIG__2_PRESENT
78846. DC__NUM_DIG__3_PRESENT
78847. DC__NUM_DIG__4
78848. DC__NUM_DIG__MAX
78849. DC__NUM_DIG__MAX__6
78850. DC__NUM_DPP
78851. DC__NUM_DPP__0_PRESENT
78852. DC__NUM_DPP__1_PRESENT
78853. DC__NUM_DPP__2_PRESENT
78854. DC__NUM_DPP__3_PRESENT
78855. DC__NUM_DPP__4
78856. DC__NUM_DPP__MAX
78857. DC__NUM_DPP__MAX__8
78858. DC__NUM_DSC
78859. DC__NUM_DSC__0
78860. DC__NUM_DSC__MAX
78861. DC__NUM_DSC__MAX__6
78862. DC__NUM_DWB
78863. DC__NUM_DWB__0_PRESENT
78864. DC__NUM_DWB__1_PRESENT
78865. DC__NUM_DWB__2
78866. DC__NUM_DWB__MAX
78867. DC__NUM_DWB__MAX__2
78868. DC__NUM_HPD
78869. DC__NUM_HPD__0_PRESENT
78870. DC__NUM_HPD__1_PRESENT
78871. DC__NUM_HPD__2_PRESENT
78872. DC__NUM_HPD__3_PRESENT
78873. DC__NUM_HPD__4
78874. DC__NUM_HPD__MAX
78875. DC__NUM_HPD__MAX__6
78876. DC__NUM_OF_DCRX_PORTS
78877. DC__NUM_OF_DCRX_PORTS__0
78878. DC__NUM_OF_DCRX_PORTS__MAX
78879. DC__NUM_OF_DCRX_PORTS__MAX__1
78880. DC__NUM_OF_DCRX_SD
78881. DC__NUM_OF_DCRX_SD__0
78882. DC__NUM_OPP
78883. DC__NUM_OPP__0_PRESENT
78884. DC__NUM_OPP__1_PRESENT
78885. DC__NUM_OPP__2_PRESENT
78886. DC__NUM_OPP__3_PRESENT
78887. DC__NUM_OPP__4
78888. DC__NUM_OPP__MAX
78889. DC__NUM_OPP__MAX__6
78890. DC__NUM_OTG
78891. DC__NUM_OTG__0_PRESENT
78892. DC__NUM_OTG__1_PRESENT
78893. DC__NUM_OTG__2_PRESENT
78894. DC__NUM_OTG__3_PRESENT
78895. DC__NUM_OTG__4
78896. DC__NUM_OTG__MAX
78897. DC__NUM_OTG__MAX__6
78898. DC__NUM_PHY
78899. DC__NUM_PHY_LP
78900. DC__NUM_PHY_LP__0
78901. DC__NUM_PHY_LP__MAX
78902. DC__NUM_PHY_LP__MAX__2
78903. DC__NUM_PHY__0_PRESENT
78904. DC__NUM_PHY__1_PRESENT
78905. DC__NUM_PHY__2_PRESENT
78906. DC__NUM_PHY__3_PRESENT
78907. DC__NUM_PHY__4
78908. DC__NUM_PHY__MAX
78909. DC__NUM_PHY__MAX__7
78910. DC__NUM_PIPES
78911. DC__NUM_PIPES_UNDERLAY
78912. DC__NUM_PIPES_UNDERLAY__0
78913. DC__NUM_PIPES_UNDERLAY__MAX
78914. DC__NUM_PIPES_UNDERLAY__MAX__2
78915. DC__NUM_PIPES__0_PRESENT
78916. DC__NUM_PIPES__1_PRESENT
78917. DC__NUM_PIPES__2_PRESENT
78918. DC__NUM_PIPES__3_PRESENT
78919. DC__NUM_PIPES__4
78920. DC__NUM_PIPES__MAX
78921. DC__NUM_PIPES__MAX__6
78922. DC__NUM_PIXEL_PLL
78923. DC__NUM_PIXEL_PLL__0_PRESENT
78924. DC__NUM_PIXEL_PLL__1
78925. DC__NUM_PIXEL_PLL__MAX
78926. DC__NUM_PIXEL_PLL__MAX__4
78927. DC__NUM_RBBMIF_DECODES
78928. DC__NUM_RBBMIF_DECODES__30
78929. DC__NUM_VCE_ENGINE
78930. DC__NUM_VCE_ENGINE__0_PRESENT
78931. DC__NUM_VCE_ENGINE__1
78932. DC__NUM_VCE_ENGINE__MAX
78933. DC__NUM_VCE_ENGINE__MAX__2
78934. DC__OBUF_MEM_PG
78935. DC__OBUF_MEM_PG__0
78936. DC__ODM_MEM_PG
78937. DC__ODM_MEM_PG__0
78938. DC__ODM_PRESENT
78939. DC__ODM_PRESENT__0
78940. DC__OPP_OPTC_SF_PIXEL_CREDITS
78941. DC__OPP_OPTC_SF_PIXEL_CREDITS__8
78942. DC__OTG_CRC_PRESENT
78943. DC__OTG_CRC_PRESENT__1
78944. DC__OTG_EXTERNAL_SYNC_PRESENT
78945. DC__OTG_EXTERNAL_SYNC_PRESENT__0
78946. DC__PHY_BROADCAST_PRESENT
78947. DC__PHY_BROADCAST_PRESENT__0
78948. DC__PIPE_10BIT
78949. DC__PIPE_10BIT__0
78950. DC__PIPE_10BIT__MAX
78951. DC__PIPE_10BIT__MAX__1
78952. DC__PIXCLK_FROM_PHYPLL
78953. DC__PIXCLK_FROM_PHYPLL__1
78954. DC__POWER_GATE_PRESENT
78955. DC__POWER_GATE_PRESENT__1
78956. DC__PRESENT
78957. DC__PRESENT__1
78958. DC__REPEATER_PROJECT_MAX
78959. DC__REPEATER_PROJECT_MAX__8
78960. DC__ROMSTRAP_PRESENT
78961. DC__ROMSTRAP_PRESENT__0
78962. DC__SFR_SFT_ROUND_TRIP_DELAY
78963. DC__SFR_SFT_ROUND_TRIP_DELAY__5
78964. DC__SPDIF1_PRESENT
78965. DC__SPDIF1_PRESENT__0
78966. DC__SURFACE_422_CAPABLE
78967. DC__SURFACE_422_CAPABLE__0
78968. DC__SYNC_CELL
78969. DC__SYNC_CELL_AMCLK_NUM_LATCHES
78970. DC__SYNC_CELL_AMCLK_NUM_LATCHES__6
78971. DC__SYNC_CELL_BYTECLK_NUM_LATCHES
78972. DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6
78973. DC__SYNC_CELL_DB_CLK_NUM_LATCHES
78974. DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6
78975. DC__SYNC_CELL_DCEFCLK_NUM_LATCHES
78976. DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6
78977. DC__SYNC_CELL_DISPCLK_NUM_LATCHES
78978. DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6
78979. DC__SYNC_CELL_DPPCLK_NUM_LATCHES
78980. DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6
78981. DC__SYNC_CELL_DPREFCLK_NUM_LATCHES
78982. DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6
78983. DC__SYNC_CELL_DSICLK_NUM_LATCHES
78984. DC__SYNC_CELL_DSICLK_NUM_LATCHES__6
78985. DC__SYNC_CELL_DVOCLK_NUM_LATCHES
78986. DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6
78987. DC__SYNC_CELL_ESCCLK_NUM_LATCHES
78988. DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6
78989. DC__SYNC_CELL_MVPCLK_NUM_LATCHES
78990. DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6
78991. DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES
78992. DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6
78993. DC__SYNC_CELL_PIXCLK_NUM_LATCHES
78994. DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6
78995. DC__SYNC_CELL_REFCLK_NUM_LATCHES
78996. DC__SYNC_CELL_REFCLK_NUM_LATCHES__6
78997. DC__SYNC_CELL_SCLK_NUM_LATCHES
78998. DC__SYNC_CELL_SCLK_NUM_LATCHES__6
78999. DC__SYNC_CELL_SYMCLK_NUM_LATCHES
79000. DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6
79001. DC__SYNC_CELL__VID_SYNC_GF14LPP
79002. DC__TMDS_LINK
79003. DC__TMDS_LINK__TMDS_LINK_DUAL
79004. DC__TOP_BLKS__DCCG
79005. DC__TOP_BLKS__DCHUBBUB
79006. DC__TOP_BLKS__DCHUBP
79007. DC__TOP_BLKS__DCIO
79008. DC__TOP_BLKS__DIO
79009. DC__TOP_BLKS__DMU
79010. DC__TOP_BLKS__DPP
79011. DC__TOP_BLKS__HDA
79012. DC__TOP_BLKS__MAX
79013. DC__TOP_BLKS__MAX__13
79014. DC__TOP_BLKS__MMHUBBUB
79015. DC__TOP_BLKS__MPC
79016. DC__TOP_BLKS__OPP
79017. DC__TOP_BLKS__OPTC
79018. DC__TOP_BLKS__WB
79019. DC__UNIPHYA_PRESENT
79020. DC__UNIPHYA_PRESENT__1
79021. DC__UNIPHYB_PRESENT
79022. DC__UNIPHYB_PRESENT__1
79023. DC__UNIPHYC_PRESENT
79024. DC__UNIPHYC_PRESENT__1
79025. DC__UNIPHYD_PRESENT
79026. DC__UNIPHYD_PRESENT__1
79027. DC__UNIPHYE_PRESENT
79028. DC__UNIPHYE_PRESENT__0
79029. DC__UNIPHYF_PRESENT
79030. DC__UNIPHYF_PRESENT__0
79031. DC__UNIPHYG_PRESENT
79032. DC__UNIPHYG_PRESENT__0
79033. DC__UNIPHY_STAGGER_CH_PRESENT
79034. DC__UNIPHY_STAGGER_CH_PRESENT__1
79035. DC__UNIPHY_VOLTAGE_MODE
79036. DC__UNIPHY_VOLTAGE_MODE__1
79037. DC__USE_NEW_VSS
79038. DC__USE_NEW_VSS__1
79039. DC__VGA_MEM_PG
79040. DC__VGA_MEM_PG__0
79041. DC__VIP_PRESENT
79042. DC__VIP_PRESENT__0
79043. DC__VOLTAGE_STATES
79044. DC__WBIF_MEM_PG
79045. DC__WBIF_MEM_PG__1
79046. DC__WBSCL_MEM1P1024X64QS_MEM_PG
79047. DC__WBSCL_MEM1P1024X64QS_MEM_PG__1
79048. DC__WBSCL_MEM1P528X64QS_MEM_PG
79049. DC__WBSCL_MEM1P528X64QS_MEM_PG__1
79050. DC__WBSCL_PIXBW
79051. DC__WBSCL_PIXBW__8
79052. DC__XDMA_PRESENT
79053. DC__XDMA_PRESENT__0
79054. DD
79055. DD1IER
79056. DD1IER_ADC
79057. DD1IER_BUF
79058. DD1IER_FRM
79059. DD1IER_HBK
79060. DD1IER_RINT
79061. DD1IER_TVR
79062. DD1IER_VBK
79063. DD1SRCR
79064. DD1SRCR_ADC
79065. DD1SRCR_BUF
79066. DD1SRCR_FRM
79067. DD1SRCR_HBK
79068. DD1SRCR_RINT
79069. DD1SRCR_TVR
79070. DD1SRCR_VBK
79071. DD1SSR
79072. DD1SSR_ADC
79073. DD1SSR_BUF
79074. DD1SSR_FRM
79075. DD1SSR_HBK
79076. DD1SSR_RINT
79077. DD1SSR_TVR
79078. DD1SSR_VBK
79079. DD1_INIT
79080. DD1_STREAM_A
79081. DD1_STREAM_B
79082. DD2bin
79083. DDA2_CONFIG
79084. DDA2_ON_OFF
79085. DDAC
79086. DDADR
79087. DDADR_DESCADDR
79088. DDADR_STOP
79089. DDAR_BS
79090. DDAR_DW
79091. DDAR_E
79092. DDAR_RW
79093. DDAR_Ser0UDCRc
79094. DDAR_Ser0UDCTr
79095. DDAR_Ser1SDLCRc
79096. DDAR_Ser1SDLCTr
79097. DDAR_Ser1UARTRc
79098. DDAR_Ser1UARTTr
79099. DDAR_Ser2ICPRc
79100. DDAR_Ser2ICPTr
79101. DDAR_Ser3UARTRc
79102. DDAR_Ser3UARTTr
79103. DDAR_Ser4MCP0Rc
79104. DDAR_Ser4MCP0Tr
79105. DDAR_Ser4MCP1Rc
79106. DDAR_Ser4MCP1Tr
79107. DDAR_Ser4SSPRc
79108. DDAR_Ser4SSPTr
79109. DDA_CONFIG
79110. DDA_ON_OFF
79111. DDB0_FIELDA
79112. DDB0_FIELDB
79113. DDB0_FIELDD
79114. DDB0_FIELDW
79115. DDB2_FIELDB
79116. DDBBISTDN
79117. DDBBISTEN
79118. DDBBISTFAIL
79119. DDBG
79120. DDBRIDGE_VERSION
79121. DDBUNIT_CLOCK_GATE_DISABLE
79122. DDB_CI_EXTERNAL_SONY
79123. DDB_CI_EXTERNAL_XO2
79124. DDB_CI_EXTERNAL_XO2_B
79125. DDB_CI_INTERNAL
79126. DDB_CONN_CLOSE_FAILURE
79127. DDB_DEVICE_ANY
79128. DDB_DEVID
79129. DDB_DMA_BLOCK_SIZE
79130. DDB_DS_DISCOVERY
79131. DDB_DS_LOGIN_IN_PROCESS
79132. DDB_DS_NO_CONNECTION_ACTIVE
79133. DDB_DS_SESSION_ACTIVE
79134. DDB_DS_SESSION_FAILED
79135. DDB_DS_UNASSIGNED
79136. DDB_ENTRY_END_SHIFT
79137. DDB_ENTRY_MASK
79138. DDB_FIELDB
79139. DDB_FIELDD
79140. DDB_FIELDW
79141. DDB_IPADDR_LEN
79142. DDB_ISNS
79143. DDB_LINK_SHIFT
79144. DDB_LINK_TAG
79145. DDB_MAX_ADAPTER
79146. DDB_MAX_I2C
79147. DDB_MAX_INPUT
79148. DDB_MAX_LINK
79149. DDB_MAX_OUTPUT
79150. DDB_MAX_PORT
79151. DDB_NAME
79152. DDB_NONE
79153. DDB_NOT_LOGGED_IN
79154. DDB_NO_LINK
79155. DDB_OCTOPUS
79156. DDB_OCTOPUS_CI
79157. DDB_OCTOPUS_MAX
79158. DDB_OCTOPUS_MAX_CT
79159. DDB_OCTOPUS_MCI
79160. DDB_OPT_AUTO_SENDTGTS_DISABLE
79161. DDB_OPT_DISC_SESSION
79162. DDB_OPT_IPV4
79163. DDB_OPT_IPV6
79164. DDB_OPT_IPV6_DEVICE
79165. DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL
79166. DDB_OPT_IPV6_NULL_LINK_LOCAL
79167. DDB_OPT_TARGET
79168. DDB_PORT_CI
79169. DDB_PORT_LOOP
79170. DDB_PORT_NONE
79171. DDB_PORT_TUNER
79172. DDB_STATE_DEAD
79173. DDB_STATE_MISSING
79174. DDB_STATE_ONLINE
79175. DDB_TARG_FLAGS
79176. DDB_TARG_FLAGS2
79177. DDB_TP_CONN_TYPE
79178. DDB_TUNER_ATSC_ST
79179. DDB_TUNER_DUMMY
79180. DDB_TUNER_DVBC2T2I_SONY
79181. DDB_TUNER_DVBC2T2I_SONY_P
79182. DDB_TUNER_DVBC2T2_SONY
79183. DDB_TUNER_DVBC2T2_SONY_P
79184. DDB_TUNER_DVBCT2_SONY
79185. DDB_TUNER_DVBCT2_SONY_P
79186. DDB_TUNER_DVBCT_ST
79187. DDB_TUNER_DVBCT_TR
79188. DDB_TUNER_DVBS_ST
79189. DDB_TUNER_DVBS_STV0910
79190. DDB_TUNER_DVBS_STV0910_P
79191. DDB_TUNER_DVBS_STV0910_PR
79192. DDB_TUNER_DVBS_ST_AA
79193. DDB_TUNER_ISDBT_SONY
79194. DDB_TUNER_ISDBT_SONY_P
79195. DDB_TUNER_MCI
79196. DDB_TUNER_MCI_SX8
79197. DDB_TUNER_MXL5XX
79198. DDB_TUNER_NONE
79199. DDB_TUNER_XO2
79200. DDB_TYPE
79201. DDB_TYPE_INITIATOR
79202. DDB_TYPE_PM_PORT
79203. DDB_TYPE_TARGET
79204. DDB_TYPE_UNUSED
79205. DDB_VALID_COOKIE
79206. DDC
79207. DDC0_MARK
79208. DDC1B_CLK
79209. DDC1B_DATA
79210. DDC1_CLK
79211. DDC1_DATA
79212. DDC1_MARK
79213. DDC2_CLK
79214. DDC2_DATA
79215. DDC2_MARK
79216. DDC3_MARK
79217. DDC5V_DELAY_0_MS
79218. DDC5V_DELAY_100_MS
79219. DDC5V_DELAY_200_MS
79220. DDC5V_DELAY_50_MS
79221. DDCB_ACFUNC_APP
79222. DDCB_ACFUNC_SLU
79223. DDCB_ASIV_LENGTH
79224. DDCB_ASIV_LENGTH_ATS
79225. DDCB_ASV_LENGTH
79226. DDCB_COMPLETED_BE32
79227. DDCB_FETCHED_BE32
79228. DDCB_FIXUPS
79229. DDCB_HSI_COMPLETED
79230. DDCB_HSI_FETCHED
79231. DDCB_INTR_BE32
79232. DDCB_LENGTH
79233. DDCB_NEXT_BE32
79234. DDCB_OPT_ECHO_COPY_ALL
79235. DDCB_OPT_ECHO_COPY_NONE
79236. DDCB_OPT_ECHO_FORCE_102
79237. DDCB_OPT_ECHO_FORCE_104
79238. DDCB_OPT_ECHO_FORCE_108
79239. DDCB_OPT_ECHO_FORCE_110
79240. DDCB_OPT_ECHO_FORCE_120
79241. DDCB_OPT_ECHO_FORCE_140
79242. DDCB_OPT_ECHO_FORCE_180
79243. DDCB_OPT_ECHO_FORCE_NO
79244. DDCB_PRESET_PRE
79245. DDCB_PURGE_BE32
79246. DDCB_RETC_COMPLETE
79247. DDCB_RETC_ERROR
79248. DDCB_RETC_FAULT
79249. DDCB_RETC_FORCED_ERROR
79250. DDCB_RETC_IDLE
79251. DDCB_RETC_PENDING
79252. DDCB_RETC_RES0
79253. DDCB_RETC_RES1
79254. DDCB_RETC_TERM
79255. DDCB_RETC_UNEXEC
79256. DDCB_SHI_INTR
79257. DDCB_SHI_NEXT
79258. DDCB_SHI_PURGE
79259. DDCL_HWID
79260. DDCM_ACK_MASK
79261. DDCM_ACK_OFFSET
79262. DDCM_CLK_DIV_MASK
79263. DDCM_CLK_DIV_OFFSET
79264. DDCM_CS_STATUS
79265. DDCM_DATA0
79266. DDCM_DATA1
79267. DDCM_DATA2
79268. DDCM_DATA3
79269. DDCM_DATA4
79270. DDCM_DATA5
79271. DDCM_DATA6
79272. DDCM_DATA7
79273. DDCM_ODRAIN
79274. DDCM_PGLEN_MASK
79275. DDCM_PGLEN_OFFSET
79276. DDCM_READ_DATA_ACK
79277. DDCM_READ_DATA_NO_ACK
79278. DDCM_SCL_STATE
79279. DDCM_SCL_STRECH
79280. DDCM_SDA_STATE
79281. DDCM_SIF_MODE_MASK
79282. DDCM_SIF_MODE_OFFSET
79283. DDCM_SM0EN
79284. DDCM_START
79285. DDCM_STOP
79286. DDCM_TRI
79287. DDCM_WRITE_DATA
79288. DDC_ADDR
79289. DDC_ADDR2
79290. DDC_BUS_DDI_B
79291. DDC_BUS_DDI_C
79292. DDC_BUS_DDI_D
79293. DDC_BUS_DDI_F
79294. DDC_BUS_FREQ_H
79295. DDC_BUS_FREQ_L
79296. DDC_CI_ADDR
79297. DDC_CMD_CLEAR_FIFO
79298. DDC_CMD_MASK
79299. DDC_CMD_SEQUENTIAL_READ
79300. DDC_CRT2
79301. DDC_CTL
79302. DDC_DDCMCTL0
79303. DDC_DDCMCTL1
79304. DDC_DDCMD0
79305. DDC_DDCMD1
79306. DDC_DOUT_CNT_MASK
79307. DDC_DRIVE_EN
79308. DDC_DVI
79309. DDC_ENAB
79310. DDC_GPIO
79311. DDC_GPIO_I2C_REG_LIST
79312. DDC_GPIO_I2C_REG_LIST_ENTRY
79313. DDC_GPIO_REG_LIST
79314. DDC_GPIO_REG_LIST_ENTRY
79315. DDC_GPIO_VGA_REG_LIST
79316. DDC_GPIO_VGA_REG_LIST_ENTRY
79317. DDC_I2C_COMMAND_ENGINE
79318. DDC_I2C_REG_LIST
79319. DDC_I2C_REG_LIST_DCN2
79320. DDC_LCD
79321. DDC_MASK
79322. DDC_MASK_SH_LIST
79323. DDC_MASK_SH_LIST_COMMON
79324. DDC_MASK_SH_LIST_DCN2
79325. DDC_MASK_TGUI
79326. DDC_MIN
79327. DDC_MMIO_REG
79328. DDC_MONID
79329. DDC_NONE_DETECTED
79330. DDC_READ
79331. DDC_REG
79332. DDC_REG_LIST
79333. DDC_REG_LIST_DCN2
79334. DDC_RESULT_FAILED_BUFFER_OVERFLOW
79335. DDC_RESULT_FAILED_CHANNEL_BUSY
79336. DDC_RESULT_FAILED_HPD_DISCON
79337. DDC_RESULT_FAILED_INCOMPLETE
79338. DDC_RESULT_FAILED_INVALID_OPERATION
79339. DDC_RESULT_FAILED_NACK
79340. DDC_RESULT_FAILED_OPERATION
79341. DDC_RESULT_FAILED_PROTOCOL_ERROR
79342. DDC_RESULT_FAILED_TIMEOUT
79343. DDC_RESULT_SUCESSFULL
79344. DDC_RESULT_UNKNOWN
79345. DDC_SCL
79346. DDC_SCL_DRIVE_TGUI
79347. DDC_SCL_IN
79348. DDC_SCL_OUT
79349. DDC_SCL_READ_MASK
79350. DDC_SCL_TGUI
79351. DDC_SCL_WRITE_MASK
79352. DDC_SDA
79353. DDC_SDA_DRIVE_TGUI
79354. DDC_SDA_IN
79355. DDC_SDA_OUT
79356. DDC_SDA_READ_MASK
79357. DDC_SDA_TGUI
79358. DDC_SDA_WRITE_MASK
79359. DDC_SEGMENT_ADDR
79360. DDC_SERVICE_TYPE_CONNECTOR
79361. DDC_SERVICE_TYPE_DISPLAY_PORT_MST
79362. DDC_TRANSACTION_TYPE_I2C
79363. DDC_TRANSACTION_TYPE_I2C_OVER_AUX
79364. DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
79365. DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER
79366. DDC_TRANSACTION_TYPE_NONE
79367. DDC_VGA
79368. DDC_VGA_REG_LIST
79369. DDC_WRITE
79370. DDDR_SEL
79371. DDEBUG
79372. DDEBUG_STRING_SIZE
79373. DDE_ALIGN
79374. DDE_BUFFER_ALIGN
79375. DDE_BUFFER_LAST_MULT
79376. DDE_BUFFER_SIZE_MULT
79377. DDE_P
79378. DDE_SIZE
79379. DDI0_SELECT
79380. DDI1_SELECT
79381. DDIA_CNTL
79382. DDIA_HDMI_EN
79383. DDID_VMID_CNTL
79384. DDID_VMID_PIPE
79385. DDIE_TRAINING_OVERRIDE_ENABLE
79386. DDIE_TRAINING_OVERRIDE_VALUE
79387. DDIR
79388. DDI_A_4_LANES
79389. DDI_BUF_BALANCE_LEG_ENABLE
79390. DDI_BUF_CTL
79391. DDI_BUF_CTL_ENABLE
79392. DDI_BUF_EMP_MASK
79393. DDI_BUF_IS_IDLE
79394. DDI_BUF_PORT_REVERSAL
79395. DDI_BUF_TRANS_HI
79396. DDI_BUF_TRANS_LO
79397. DDI_BUF_TRANS_SELECT
79398. DDI_CLK_SEL
79399. DDI_CLK_SEL_MASK
79400. DDI_CLK_SEL_MG
79401. DDI_CLK_SEL_NONE
79402. DDI_CLK_SEL_TBT_162
79403. DDI_CLK_SEL_TBT_270
79404. DDI_CLK_SEL_TBT_540
79405. DDI_CLK_SEL_TBT_810
79406. DDI_DMA_SYNC_FORCPU
79407. DDI_DMA_SYNC_FORDEV
79408. DDI_INIT_DISPLAY_DETECTED
79409. DDI_MASK
79410. DDI_PORT
79411. DDI_PORT_B
79412. DDI_PORT_C
79413. DDI_PORT_D
79414. DDI_PORT_E
79415. DDI_PORT_NONE
79416. DDI_PORT_WIDTH
79417. DDI_PORT_WIDTH_MASK
79418. DDI_PORT_WIDTH_SHIFT
79419. DDI_POWERGATING_ARG
79420. DDI_TRAINING_OVERRIDE_ENABLE
79421. DDI_TRAINING_OVERRIDE_VALUE
79422. DDK750_CHIP_H__
79423. DDK750_DISPLAY_H__
79424. DDK750_DVI_H__
79425. DDK750_HWI2C_H__
79426. DDK750_H__
79427. DDK750_MODE_H__
79428. DDK750_POWER_H__
79429. DDK750_REG_H__
79430. DDK750_SII164_H__
79431. DDLTR
79432. DDLTR_CODE
79433. DDLTR_DLAR2
79434. DDLTR_DLAY1
79435. DDLTR_DLAY2
79436. DDLY_MASK
79437. DDLY_SHIFT
79438. DDL_CURSOR_SHIFT
79439. DDL_LEN_MAX
79440. DDL_PLANE_SHIFT
79441. DDL_PRECISION_HIGH
79442. DDL_PRECISION_LOW
79443. DDL_SPRITE_SHIFT
79444. DDMA_CFG_DBE
79445. DDMA_CFG_DED
79446. DDMA_CFG_DFN
79447. DDMA_CFG_DP
79448. DDMA_CFG_EN
79449. DDMA_CFG_PPR
79450. DDMA_CFG_SBE
79451. DDMA_CFG_SED
79452. DDMA_CFG_SP
79453. DDMA_CFG_SYNC
79454. DDMA_CONFIG_AF
79455. DDMA_CONFIG_AH
79456. DDMA_CONFIG_AL
79457. DDMA_CONF_BENAB
79458. DDMA_CONF_DIR
79459. DDMA_CONF_RIRQ
79460. DDMA_CONF_SENAB
79461. DDMA_EN
79462. DDMA_ENABLE
79463. DDMA_FLAGS_IE
79464. DDMA_FLAGS_NOIE
79465. DDMA_IRQ_IN
79466. DDMA_POLLING_COUNT
79467. DDMA_STAT_DB
79468. DDMA_STAT_H
79469. DDMA_STAT_V
79470. DDMA_THROTTLE_EN
79471. DDPT_BASE_BOUNDS
79472. DDPT_INV_STAG
79473. DDPT_INV_VERS
79474. DDPT_STAG_NOT_ASSOC
79475. DDPT_TO_WRAP
79476. DDPU_INV_MO
79477. DDPU_INV_MSN_NOBUF
79478. DDPU_INV_MSN_RANGE
79479. DDPU_INV_QN
79480. DDPU_INV_VERS
79481. DDPU_MSG_TOOBIG
79482. DDP_CATASTROPHIC
79483. DDP_CATASTROPHIC_LOCAL
79484. DDP_COMPONENT_AAL0
79485. DDP_COMPONENT_AAL1
79486. DDP_COMPONENT_BLS
79487. DDP_COMPONENT_COLOR0
79488. DDP_COMPONENT_COLOR1
79489. DDP_COMPONENT_DPI0
79490. DDP_COMPONENT_DPI1
79491. DDP_COMPONENT_DSI0
79492. DDP_COMPONENT_DSI1
79493. DDP_COMPONENT_DSI2
79494. DDP_COMPONENT_DSI3
79495. DDP_COMPONENT_GAMMA
79496. DDP_COMPONENT_ID_MAX
79497. DDP_COMPONENT_OD0
79498. DDP_COMPONENT_OD1
79499. DDP_COMPONENT_OVL0
79500. DDP_COMPONENT_OVL1
79501. DDP_COMPONENT_PWM0
79502. DDP_COMPONENT_PWM1
79503. DDP_COMPONENT_PWM2
79504. DDP_COMPONENT_RDMA0
79505. DDP_COMPONENT_RDMA1
79506. DDP_COMPONENT_RDMA2
79507. DDP_COMPONENT_UFOE
79508. DDP_COMPONENT_WDMA0
79509. DDP_COMPONENT_WDMA1
79510. DDP_ECODE_CATASTROPHIC
79511. DDP_ECODE_T_BASE_BOUNDS
79512. DDP_ECODE_T_INVALID_STAG
79513. DDP_ECODE_T_STAG_NOT_ASSOC
79514. DDP_ECODE_T_TO_WRAP
79515. DDP_ECODE_T_VERSION
79516. DDP_ECODE_UT_INVALID_MO
79517. DDP_ECODE_UT_INVALID_MSN_NOBUF
79518. DDP_ECODE_UT_INVALID_MSN_RANGE
79519. DDP_ECODE_UT_INVALID_QN
79520. DDP_ECODE_UT_MSG_TOOLONG
79521. DDP_ECODE_UT_VERSION
79522. DDP_ETYPE_CATASTROPHIC
79523. DDP_ETYPE_RSVD
79524. DDP_ETYPE_TAGGED_BUF
79525. DDP_ETYPE_UNTAGGED_BUF
79526. DDP_FLAG_LAST
79527. DDP_FLAG_TAGGED
79528. DDP_HDR_FLAG
79529. DDP_LEN_FLAG
79530. DDP_LLP
79531. DDP_LOCAL_CATA
79532. DDP_MASK_RESERVED
79533. DDP_MASK_VERSION
79534. DDP_MAXHOPS
79535. DDP_MAXSZ
79536. DDP_PGIDX_MAX
79537. DDP_PGSZ_BASE_SHIFT
79538. DDP_TAGGED_BOUNDS
79539. DDP_TAGGED_BUFFER
79540. DDP_TAGGED_ERR
79541. DDP_TAGGED_INV_DDP_VER
79542. DDP_TAGGED_INV_STAG
79543. DDP_TAGGED_TO_WRAP
79544. DDP_TAGGED_UNASSOC_STAG
79545. DDP_THRESHOLD
79546. DDP_UNTAGGED_BUFFER
79547. DDP_UNTAGGED_ERR
79548. DDP_UNTAGGED_INV_DDP_VER
79549. DDP_UNTAGGED_INV_MO
79550. DDP_UNTAGGED_INV_MSN_NO_BUF
79551. DDP_UNTAGGED_INV_MSN_RANGE
79552. DDP_UNTAGGED_INV_QN
79553. DDP_UNTAGGED_INV_TOO_LONG
79554. DDP_VERSION
79555. DDQ_DATA
79556. DDR
79557. DDR0_02
79558. DDR0_08
79559. DDR0_10
79560. DDR0_14
79561. DDR0_42
79562. DDR0_43
79563. DDR0_BASE_MSK
79564. DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR_MASK
79565. DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR__SHIFT
79566. DDR0_FUSE_SSB_XFER__START_STATUS_XFER_MASK
79567. DDR0_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT
79568. DDR0_GATE
79569. DDR0_PHYS_ADDR
79570. DDR1_BASE_MSK
79571. DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR_MASK
79572. DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR__SHIFT
79573. DDR1_FUSE_SSB_XFER__START_STATUS_XFER_MASK
79574. DDR1_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT
79575. DDR1_GATE
79576. DDR2
79577. DDR2_DDQS_MASK
79578. DDR2_DDQS_SHIFT
79579. DDR2_LPMODEN_BIT
79580. DDR2_MCLKSTOPEN_BIT
79581. DDR2_SDRCR_OFFSET
79582. DDR2_SRPD_BIT
79583. DDR32TO16EN
79584. DDR34_SCRUB_CNTL_CE_STOP
79585. DDR34_SCRUB_CNTL_RANK_EN
79586. DDR34_SCRUB_CNTL_SCRUB
79587. DDR34_SCRUB_CNTL_STOP
79588. DDR34_SCRUB_CNTL_UE_STOP
79589. DDR3BUPCR_OFS
79590. DDR3_1066E
79591. DDR3_1066F
79592. DDR3_1066G
79593. DDR3_1333F
79594. DDR3_1333G
79595. DDR3_1333H
79596. DDR3_1333J
79597. DDR3_1600G
79598. DDR3_1600H
79599. DDR3_1600J
79600. DDR3_1600K
79601. DDR3_1866J
79602. DDR3_1866K
79603. DDR3_1866L
79604. DDR3_1866M
79605. DDR3_2133K
79606. DDR3_2133L
79607. DDR3_2133M
79608. DDR3_2133N
79609. DDR3_800D
79610. DDR3_800E
79611. DDR3_DEFAULT
79612. DDR3_MODE
79613. DDR3_MR0CF
79614. DDR40_PHY_CONTROL_REGS_0_PLL_STATUS
79615. DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL
79616. DDR4_DRAM_WIDTH
79617. DDR50_MODE
79618. DDR50_PHASE
79619. DDR50_QUERY_SWITCH_OK
79620. DDR50_RX_PHASE
79621. DDR50_SUPPORT
79622. DDR50_SUPPORT_MASK
79623. DDR50_SWITCH_BUSY
79624. DDR50_TX_PHASE
79625. DDRC1
79626. DDRC1LP
79627. DDRC2
79628. DDRC2LP
79629. DDRCAPB
79630. DDRCAPBLP
79631. DDRCONFIG_ER
79632. DDRCTL_EWDTH_16
79633. DDRCTL_EWDTH_32
79634. DDRCTL_EWDTH_64
79635. DDRCTL_WDTH_16
79636. DDRCTL_WDTH_32
79637. DDRC_ACT_CMD
79638. DDRC_CFG
79639. DDRC_CLOCKSTOP_MASK
79640. DDRC_CTL
79641. DDRC_CTRL_REG1_OFFS
79642. DDRC_DEBUG
79643. DDRC_DRAM_PARAM_REG3_OFFS
79644. DDRC_EVENT_CTRL
79645. DDRC_FLUX_RCMD
79646. DDRC_FLUX_RD
79647. DDRC_FLUX_WCMD
79648. DDRC_FLUX_WR
79649. DDRC_INDIRECT_WRITE
79650. DDRC_INT_CLEAR
79651. DDRC_INT_MASK
79652. DDRC_INT_STATUS
79653. DDRC_MSTR_CFG_MASK
79654. DDRC_MSTR_CFG_SHIFT
79655. DDRC_MSTR_CFG_X16_MASK
79656. DDRC_MSTR_CFG_X32_MASK
79657. DDRC_MSTR_CFG_X4_MASK
79658. DDRC_MSTR_CFG_X8_MASK
79659. DDRC_NR_COUNTERS
79660. DDRC_PERF_CTRL
79661. DDRC_PERF_CTRL_EN
79662. DDRC_PRE_CMD
79663. DDRC_RNK_CHG
79664. DDRC_RW_CHG
79665. DDRC_SELFREFRESH_MASK
79666. DDRC_SWCTL
79667. DDRDEEPSLEEPOK_ER
79668. DDREC
79669. DDRECC
79670. DDRMON_CH0_COUNT_NUM
79671. DDRMON_CH0_DFI_ACCESS_NUM
79672. DDRMON_CH1_COUNT_NUM
79673. DDRMON_CH1_DFI_ACCESS_NUM
79674. DDRMON_CTRL
79675. DDRMPLL1
79676. DDRPERFM
79677. DDRPERFM_R
79678. DDRPHYC
79679. DDRPHYCAPB
79680. DDRPHYCAPBLP
79681. DDRPHYCLP
79682. DDRPHY_LOCK_CTRL
79683. DDRSCH_RESET
79684. DDR_100_OPP
79685. DDR_1BIT
79686. DDR_25_OPP
79687. DDR_2BIT
79688. DDR_4BIT
79689. DDR_4PHASE
79690. DDR_50_OPP
79691. DDR_APIN
79692. DDR_APIN_SHIFT
79693. DDR_BANK8
79694. DDR_BANK8_SHIFT
79695. DDR_BAR_ID
79696. DDR_BASE_CS_HIGH_MASK
79697. DDR_BASE_CS_LOW_MASK
79698. DDR_BASE_CS_OFF
79699. DDR_CAP_AXI_ID_FILTER
79700. DDR_CAP_AXI_ID_FILTER_ENHANCED
79701. DDR_CLK_SRC
79702. DDR_COL_SZ
79703. DDR_COL_SZ_SHIFT
79704. DDR_CONFIG_POR_VAL
79705. DDR_CPUHP_CB_NAME
79706. DDR_CSEND_REG
79707. DDR_CS_MAP
79708. DDR_CS_MAP_SHIFT
79709. DDR_DDR2_MODE
79710. DDR_DDR2_MODE_SHIFT
79711. DDR_DENSITY_128Mb
79712. DDR_DENSITY_16Gb
79713. DDR_DENSITY_1Gb
79714. DDR_DENSITY_256Mb
79715. DDR_DENSITY_2Gb
79716. DDR_DENSITY_32Gb
79717. DDR_DENSITY_4Gb
79718. DDR_DENSITY_512Mb
79719. DDR_DENSITY_64Mb
79720. DDR_DENSITY_8Gb
79721. DDR_DISABLE_DLL_MASK
79722. DDR_DISABLE_DLL_SHIFT
79723. DDR_DMIPSPLLCFG_6368_REG
79724. DDR_DMIPSPLLCFG_REG
79725. DDR_DMIPSPLLDIV_6368_REG
79726. DDR_ECC_DATA_POISON_SUPPORT
79727. DDR_ECC_INTR_SUPPORT
79728. DDR_EDE_MBE
79729. DDR_EDE_MME
79730. DDR_EDE_MSE
79731. DDR_EDE_SBE
79732. DDR_EDI_MBED
79733. DDR_EDI_MSED
79734. DDR_EDI_SBED
79735. DDR_EIE_MBEE
79736. DDR_EIE_MSEE
79737. DDR_EIE_SBEE
79738. DDR_EN
79739. DDR_FIX_RX_CMD
79740. DDR_FIX_RX_CMD_14_DELAY
79741. DDR_FIX_RX_CMD_POS_EDGE
79742. DDR_FIX_RX_DAT
79743. DDR_FIX_RX_DAT_14_DELAY
79744. DDR_FIX_RX_DAT_EDGE
79745. DDR_FIX_TX_CMD_14_AHEAD
79746. DDR_FIX_TX_CMD_DAT
79747. DDR_FIX_TX_CMD_NEG_EDGE
79748. DDR_FIX_TX_DAT_12_TSU
79749. DDR_FIX_TX_DAT_14_TSU
79750. DDR_FORCE_CKE_RST_N
79751. DDR_GET_VAL
79752. DDR_HZ
79753. DDR_IO_WIDTH_16
79754. DDR_IO_WIDTH_32
79755. DDR_IO_WIDTH_4
79756. DDR_IO_WIDTH_8
79757. DDR_MASK
79758. DDR_MAX_BANKGRP_SHIFT
79759. DDR_MAX_BANK_SHIFT
79760. DDR_MAX_COL_REG
79761. DDR_MAX_COL_REG_SHIFT
79762. DDR_MAX_COL_SHIFT
79763. DDR_MAX_CS_REG
79764. DDR_MAX_CS_REG_SHIFT
79765. DDR_MAX_ROW_REG
79766. DDR_MAX_ROW_REG_SHIFT
79767. DDR_MAX_ROW_SHIFT
79768. DDR_MC_CH0_MAX_OFFSET
79769. DDR_MC_CH0_SECTION
79770. DDR_MC_CH1_MAX_OFFSET
79771. DDR_MC_CH1_SECTION
79772. DDR_MISC_CH0_MAX_OFFSET
79773. DDR_MISC_CH0_SECTION
79774. DDR_MISC_CH1_MAX_OFFSET
79775. DDR_MISC_CH1_SECTION
79776. DDR_MR0
79777. DDR_MR1
79778. DDR_MR10
79779. DDR_MR11
79780. DDR_MR16
79781. DDR_MR17
79782. DDR_MR18
79783. DDR_MR2
79784. DDR_MR3
79785. DDR_MR4
79786. DDR_MR5
79787. DDR_MR6
79788. DDR_MR7
79789. DDR_MR8
79790. DDR_MR9
79791. DDR_OPERATION_BASE
79792. DDR_PAD_MODE
79793. DDR_PERF_DEV_NAME
79794. DDR_PHYS_BASE
79795. DDR_PHY_CH0_MAX_OFFSET
79796. DDR_PHY_CH0_SECTION
79797. DDR_PHY_CH1_MAX_OFFSET
79798. DDR_PHY_CH1_SECTION
79799. DDR_PHY_CKE
79800. DDR_PHY_CTRL_1_SHDW_MASK
79801. DDR_PHY_CTRL_1_SHDW_SHIFT
79802. DDR_PHY_NO_CHANNEL
79803. DDR_PHY_RST_N
79804. DDR_PHY_STATUS_REG
79805. DDR_PWR_STATE_OFFHIGHLAT
79806. DDR_PWR_STATE_OFFLOWLAT
79807. DDR_PWR_STATE_ON
79808. DDR_PWR_STATE_UNCHANGED
79809. DDR_QOSCE_MASK
79810. DDR_QOSUE_MASK
79811. DDR_QOS_IRQ_DB_OFST
79812. DDR_QOS_IRQ_EN_OFST
79813. DDR_QOS_IRQ_STAT_OFST
79814. DDR_REDUC
79815. DDR_REDUC_SHIFT
79816. DDR_REF
79817. DDR_SIZE_CS_MASK
79818. DDR_SIZE_CS_OFF
79819. DDR_SIZE_CS_SHIFT
79820. DDR_SIZE_ENABLED
79821. DDR_SIZE_MASK
79822. DDR_START
79823. DDR_START_SHIFT
79824. DDR_TERM_MASK
79825. DDR_TERM_SHIFT
79826. DDR_TYPE_DDR2
79827. DDR_TYPE_DDR3
79828. DDR_TYPE_LPDDR2_NVM
79829. DDR_TYPE_LPDDR2_S2
79830. DDR_TYPE_LPDDR2_S4
79831. DDR_VAR_RX_CMD
79832. DDR_VAR_RX_DAT
79833. DDR_VAR_SDCLK_POL_SWAP
79834. DDR_VAR_TX_CMD_DAT
79835. DDR_VIRT_BASE
79836. DDR_VOLTAGE_RAMPING
79837. DDR_VOLTAGE_STABLE
79838. DDR_WIDTH
79839. DDR_WINDOW_CPU0_BASE
79840. DDR_WINDOW_CPU1_BASE
79841. DDR_WINDOW_CPU_SZ
79842. DDSF_FORCED
79843. DDSF_NO_RESYNC
79844. DDS_1M
79845. DDS_3M
79846. DDS_ENT_AMP_LSB
79847. DDS_ENT_MAIN_LSB
79848. DDS_ENT_POST_LSB
79849. DDS_ENT_PRE_LSB
79850. DDS_ENT_PRE_XTRA_LSB
79851. DDS_NUMERATOR
79852. DDS_RATE
79853. DDS_REG_MAP
79854. DDS_ROWS
79855. DDS_VAL
79856. DDUMP
79857. DDVID
79858. DDV_MAJOR
79859. DD_ACK
79860. DD_ATTR
79861. DD_CFG
79862. DD_CFG_IEND
79863. DD_CFG_LIR
79864. DD_CFG_XHIE
79865. DD_CFG_XLIE
79866. DD_CFG_YHIE
79867. DD_CFG_YLIE
79868. DD_CFG_ZHIE
79869. DD_CFG_ZLIE
79870. DD_DEV_ASSIGN
79871. DD_DEV_ENTRY
79872. DD_MEDIA
79873. DD_PROBLEM
79874. DD_SETUP_ATLE_DMA_MODE
79875. DD_SETUP_DMALENBYTES
79876. DD_SETUP_ISO_EP
79877. DD_SETUP_NEXT_DD_VALID
79878. DD_SETUP_PACKETLEN
79879. DD_SRC
79880. DD_SRC_IA
79881. DD_SRC_XH
79882. DD_SRC_XL
79883. DD_SRC_YH
79884. DD_SRC_YL
79885. DD_SRC_ZH
79886. DD_SRC_ZL
79887. DD_STATUS_CURDMACNT
79888. DD_STATUS_DD_RETIRED
79889. DD_STATUS_LSB_EX
79890. DD_STATUS_MLEN
79891. DD_STATUS_MSB_EX
79892. DD_STATUS_PKT_VAL
79893. DD_STATUS_STS_BS
79894. DD_STATUS_STS_DOR
79895. DD_STATUS_STS_DUR
79896. DD_STATUS_STS_MASK
79897. DD_STATUS_STS_NC
79898. DD_STATUS_STS_NS
79899. DD_STATUS_STS_SE
79900. DD_THSE_H
79901. DD_THSE_L
79902. DD_THSI_H
79903. DD_THSI_L
79904. DE
79905. DE2_BLD_BASE
79906. DE2_CH_BASE
79907. DE2_CH_SIZE
79908. DE2_MIXER_UNIT_SIZE
79909. DE2_UI_SCALER_UNIT_SIZE
79910. DE2_VI_SCALER_UNIT_BASE
79911. DE2_VI_SCALER_UNIT_SIZE
79912. DE3_BLD_BASE
79913. DE3_CH_BASE
79914. DE3_CH_SIZE
79915. DE3_MIXER_UNIT_SIZE
79916. DE3_UI_SCALER_UNIT_SIZE
79917. DE3_VI_SCALER_UNIT_BASE
79918. DE3_VI_SCALER_UNIT_SIZE
79919. DE4X5_ALIGN
79920. DE4X5_ALIGN128
79921. DE4X5_ALIGN16
79922. DE4X5_ALIGN32
79923. DE4X5_ALIGN4
79924. DE4X5_ALIGN64
79925. DE4X5_ALIGN8
79926. DE4X5_APROM
79927. DE4X5_AUTOSENSE_MS
79928. DE4X5_BMR
79929. DE4X5_BROM
79930. DE4X5_CACHE_ALIGN
79931. DE4X5_CLASS_CODE
79932. DE4X5_CLR_MCA
79933. DE4X5_CLR_STATS
79934. DE4X5_DDR
79935. DE4X5_DUMP
79936. DE4X5_EISA_IO_PORTS
79937. DE4X5_EISA_TOTAL_SIZE
79938. DE4X5_FDR
79939. DE4X5_GEP
79940. DE4X5_GET_HWADDR
79941. DE4X5_GET_MCA
79942. DE4X5_GET_OMR
79943. DE4X5_GET_REG
79944. DE4X5_GET_STATS
79945. DE4X5_GPT
79946. DE4X5_HASH_BITS
79947. DE4X5_HASH_TABLE_LEN
79948. DE4X5_IMR
79949. DE4X5_INIT
79950. DE4X5_MAX_MII
79951. DE4X5_MAX_PHY
79952. DE4X5_MCA_EN
79953. DE4X5_MFC
79954. DE4X5_MII
79955. DE4X5_NAME_LENGTH
79956. DE4X5_NDA
79957. DE4X5_OMR
79958. DE4X5_PCI_TOTAL_SIZE
79959. DE4X5_PKT_BIN_SZ
79960. DE4X5_PKT_STAT_SZ
79961. DE4X5_RESTORE_STATE
79962. DE4X5_RPD
79963. DE4X5_RRBA
79964. DE4X5_RUN
79965. DE4X5_SAVE_STATE
79966. DE4X5_SAY_BOO
79967. DE4X5_SET_HWADDR
79968. DE4X5_SET_MCA
79969. DE4X5_SET_OMR
79970. DE4X5_SICR
79971. DE4X5_SIGNATURE
79972. DE4X5_SIGR
79973. DE4X5_SISR
79974. DE4X5_SROM
79975. DE4X5_STRLEN
79976. DE4X5_STRR
79977. DE4X5_STS
79978. DE4X5_TPD
79979. DE4X5_TRBA
79980. DEACTIVATE
79981. DEACTIVATE_BYPASS
79982. DEACTIVATE_EMPTY
79983. DEACTIVATE_FULL
79984. DEACTIVATE_REMOTE_FREES
79985. DEACTIVATE_TO_HEAD
79986. DEACTIVATE_TO_TAIL
79987. DEACT_EVENT_COUNT
79988. DEACT_STATE_COUNT
79989. DEAD
79990. DEADLINE_DEBUGFS_DDIR_ATTRS
79991. DEADLINE_MODEL_MATCH_FUNC
79992. DEADLINE_MODEL_MATCH_REV
79993. DEADLINE_MODE_IS_ON
79994. DEADLINE_QUEUE_DDIR_ATTRS
79995. DEAGULT_FIFO_THRES
79996. DEALLOC_DIST_MASK
79997. DEALLOC_DONE
79998. DEALLOC_FILL_MP
79999. DEALLOC_FMR
80000. DEALLOC_MP_FULL
80001. DEALLOC_MP_LOWER
80002. DEALLOC_PD
80003. DEALLOC_UCONTEXT
80004. DEASSERT_CLEAR
80005. DEASSERT_NONE
80006. DEASSERT_SET
80007. DEAUTHENTIC_TYPE
80008. DEAUTH_RX_EVENT
80009. DEAUTH_TX_EVENT
80010. DEB
80011. DEB1
80012. DEB2
80013. DEB3
80014. DEBC
80015. DEBC_printk
80016. DEBG
80017. DEBG1
80018. DEBIADDR_ATTR
80019. DEBIADDR_CICONTROL
80020. DEBIADDR_CIVERSION
80021. DEBIADDR_IO
80022. DEBIADDR_IR
80023. DEBICICAM
80024. DEBICICTL
80025. DEBINOSWAP
80026. DEBISWAB
80027. DEBISWAP
80028. DEBI_AD
80029. DEBI_COMMAND
80030. DEBI_CONFIG
80031. DEBI_DONE_LINE
80032. DEBI_PAGE
80033. DEBI_READ
80034. DEBI_WRITE
80035. DEBOUNCE
80036. DEBOUNCE_CNT
80037. DEBOUNCE_CNTR_STAT
80038. DEBOUNCE_COUNT
80039. DEBOUNCE_PERIOD_NSEC
80040. DEBOUNCE_TIME
80041. DEBOUNCE_TIMEOUT_SHIFT
80042. DEBOUNCE_VAL
80043. DEBOUNCE_VAL_SHIFT
80044. DEBPRINT
80045. DEBPRINTK
80046. DEBPROTO
80047. DEBSTATUS
80048. DEBUG
80049. DEBUG00
80050. DEBUG01
80051. DEBUG0_HSYNC
80052. DEBUG0_VSYNC
80053. DEBUG2
80054. DEBUG2_3
80055. DEBUG3
80056. DEBUG4
80057. DEBUG5
80058. DEBUG7
80059. DEBUG9
80060. DEBUGBUS
80061. DEBUGCAUSE_BREAKN_BIT
80062. DEBUGCAUSE_BREAK_BIT
80063. DEBUGCAUSE_DBNUM_MASK
80064. DEBUGCAUSE_DBNUM_SHIFT
80065. DEBUGCAUSE_DBREAK_BIT
80066. DEBUGCAUSE_DEBUGINT_BIT
80067. DEBUGCAUSE_IBREAK_BIT
80068. DEBUGCAUSE_ICOUNT_BIT
80069. DEBUGCCW
80070. DEBUGCTLMSR_BTF
80071. DEBUGCTLMSR_BTF_SHIFT
80072. DEBUGCTLMSR_BTINT
80073. DEBUGCTLMSR_BTS
80074. DEBUGCTLMSR_BTS_OFF_OS
80075. DEBUGCTLMSR_BTS_OFF_USR
80076. DEBUGCTLMSR_FREEZE_IN_SMM
80077. DEBUGCTLMSR_FREEZE_IN_SMM_BIT
80078. DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
80079. DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI
80080. DEBUGCTLMSR_LBR
80081. DEBUGCTLMSR_TR
80082. DEBUGCTL_RESERVED_BITS
80083. DEBUGDATA
80084. DEBUGFLAGS
80085. DEBUGFS
80086. DEBUGFS_ADD
80087. DEBUGFS_ADD_BOOL
80088. DEBUGFS_ADD_COUNTER
80089. DEBUGFS_ADD_FILE
80090. DEBUGFS_ADD_MODE
80091. DEBUGFS_ADD_PREFIX
80092. DEBUGFS_ADD_W
80093. DEBUGFS_AXI
80094. DEBUGFS_BUF_SIZE
80095. DEBUGFS_DECLARE_FILE
80096. DEBUGFS_DECLARE_RO_FILE
80097. DEBUGFS_DECLARE_RW_FILE
80098. DEBUGFS_DECLARE_WO_FILE
80099. DEBUGFS_DEFAULT_MODE
80100. DEBUGFS_DEFAULT_PATH
80101. DEBUGFS_DEL
80102. DEBUGFS_DEVSTATS_ADD
80103. DEBUGFS_DEVSTATS_FILE
80104. DEBUGFS_FIELD_ATTR
80105. DEBUGFS_FILE
80106. DEBUGFS_FILENAME
80107. DEBUGFS_FILE_OPS
80108. DEBUGFS_FORMAT_BUFFER_SIZE
80109. DEBUGFS_FSDATA_IS_REAL_FOPS_BIT
80110. DEBUGFS_FWSTATS_ADD
80111. DEBUGFS_FWSTATS_DEL
80112. DEBUGFS_FWSTATS_FILE
80113. DEBUGFS_FWSTATS_FILE_ARRAY
80114. DEBUGFS_GLOBAL
80115. DEBUGFS_HW_REG_FILE
80116. DEBUGFS_HW_TALLY_FILE
80117. DEBUGFS_MAGIC
80118. DEBUGFS_NAMELEN
80119. DEBUGFS_OPS
80120. DEBUGFS_POOL_COUNTER_ADD
80121. DEBUGFS_POOL_COUNTER_RESET
80122. DEBUGFS_QUEUE_DUMP
80123. DEBUGFS_RAS
80124. DEBUGFS_READONLY_FILE
80125. DEBUGFS_READONLY_FILE_FN
80126. DEBUGFS_READONLY_FILE_OPS
80127. DEBUGFS_READ_FILE_OPS
80128. DEBUGFS_READ_FUNC
80129. DEBUGFS_READ_WRITE_FILE_OPS
80130. DEBUGFS_REG32
80131. DEBUGFS_REGS_NUM
80132. DEBUGFS_REG_ATTR
80133. DEBUGFS_SEQ_FILE_OPEN
80134. DEBUGFS_SEQ_FILE_OPS
80135. DEBUGFS_STATS_ADD
80136. DEBUGFS_STRUCT
80137. DEBUGFS_S_IRUSR
80138. DEBUGFS_S_ISDIR
80139. DEBUGFS_S_IWUSR
80140. DEBUGFS_WRITE_BUF_SIZE
80141. DEBUGFS_WRITE_FILE_OPS
80142. DEBUGFS_WRITE_FUNC
80143. DEBUGFS_XOPS
80144. DEBUGGER_BOILERPLATE
80145. DEBUGGER_MULTI_THREADED
80146. DEBUGGER_SINGLE_THREADED
80147. DEBUGGER_THREADING
80148. DEBUGGING
80149. DEBUGGING_CMD
80150. DEBUGGING_ON
80151. DEBUGLOG
80152. DEBUGP
80153. DEBUGSS_CAUSE
80154. DEBUGT
80155. DEBUGUNIX_ADDR
80156. DEBUG_ABORT
80157. DEBUG_ACX
80158. DEBUG_ADDRESSES
80159. DEBUG_ADHOC
80160. DEBUG_ALL
80161. DEBUG_ALLOC
80162. DEBUG_AM33XXUART1_FLAGS
80163. DEBUG_AMBASSADOR
80164. DEBUG_ANY
80165. DEBUG_AP
80166. DEBUG_ARP_TABLE
80167. DEBUG_AUGMENT_LOWEST_MATCH_CHECK
80168. DEBUG_AUGMENT_PROPAGATE_CHECK
80169. DEBUG_AUTOCONF
80170. DEBUG_AWAIT_COMPLETION_LINE
80171. DEBUG_BACKLIGHT
80172. DEBUG_BADNESS
80173. DEBUG_BATTERY_POLLING
80174. DEBUG_BIT_0
80175. DEBUG_BIT_0_OE
80176. DEBUG_BIT_0_STATE
80177. DEBUG_BIT_1
80178. DEBUG_BIT_1_OE
80179. DEBUG_BIT_1_STATE
80180. DEBUG_BIT_2
80181. DEBUG_BIT_2_OE
80182. DEBUG_BIT_2_STATE
80183. DEBUG_BLANK
80184. DEBUG_BOOT
80185. DEBUG_BP_TRAP
80186. DEBUG_BYPASS
80187. DEBUG_CACHE
80188. DEBUG_CACHE_DIR
80189. DEBUG_CCIO_INIT
80190. DEBUG_CCIO_RES
80191. DEBUG_CCIO_RUN
80192. DEBUG_CCIO_RUN_SG
80193. DEBUG_CFG
80194. DEBUG_CFM
80195. DEBUG_CHANNEL
80196. DEBUG_CHECK_RANGE
80197. DEBUG_CLOCK
80198. DEBUG_CLOSE
80199. DEBUG_CMD
80200. DEBUG_CMDLINE
80201. DEBUG_CNT
80202. DEBUG_COMPAT_SIG
80203. DEBUG_COMPAT_SIG_LEVEL
80204. DEBUG_COMPLETION_QUEUE_FULL_COUNT
80205. DEBUG_CONFIG
80206. DEBUG_CONNECT
80207. DEBUG_CORE
80208. DEBUG_CORE_FUNC
80209. DEBUG_COUNT
80210. DEBUG_CP
80211. DEBUG_CRIT_EXCEPTION
80212. DEBUG_CRYPT
80213. DEBUG_DATA
80214. DEBUG_DATA__DEBUG_DATA_MASK
80215. DEBUG_DATA__DEBUG_DATA__SHIFT
80216. DEBUG_DBG
80217. DEBUG_DEBUG_EXCEPTION
80218. DEBUG_DEFAULT
80219. DEBUG_DEFAULTS
80220. DEBUG_DEFAULT_FLAGS
80221. DEBUG_DEFAULT_LEVEL
80222. DEBUG_DEFERRED_IO
80223. DEBUG_DEQUEUE_MESSAGE_LINE
80224. DEBUG_DESC
80225. DEBUG_DIR_ROOT
80226. DEBUG_DISCON
80227. DEBUG_DISCONTIG
80228. DEBUG_DMA
80229. DEBUG_DMASOUND
80230. DEBUG_DMB_TRAP
80231. DEBUG_DRIVER
80232. DEBUG_DRIVER_INIT_FUNCTIONS
80233. DEBUG_DSP_BLOWFISH
80234. DEBUG_DSP_CLOCK
80235. DEBUG_DSP_CMX
80236. DEBUG_DSP_CORE
80237. DEBUG_DSP_CTRL
80238. DEBUG_DSP_DELAY
80239. DEBUG_DSP_DTMF
80240. DEBUG_DSP_DTMFCOEFF
80241. DEBUG_DSP_TONE
80242. DEBUG_DUMP_CONFIG
80243. DEBUG_DUMP_DATA_MAX_LEN
80244. DEBUG_DUMP_LIMIT
80245. DEBUG_DUMP_PATCH
80246. DEBUG_DUMP_REGS
80247. DEBUG_DZ
80248. DEBUG_ECM
80249. DEBUG_ECN
80250. DEBUG_EN
80251. DEBUG_ENTRIES
80252. DEBUG_ENTRY_ASSERT_IRQS_OFF
80253. DEBUG_ERR
80254. DEBUG_ESS
80255. DEBUG_EVENT
80256. DEBUG_EXCEPTION_PROLOG
80257. DEBUG_EXITS
80258. DEBUG_EXPR
80259. DEBUG_EXTRA
80260. DEBUG_EXTRA2
80261. DEBUG_FBTFT_INIT_FUNCTIONS
80262. DEBUG_FB_BLANK
80263. DEBUG_FB_COPYAREA
80264. DEBUG_FB_FILLRECT
80265. DEBUG_FB_IMAGEBLIT
80266. DEBUG_FB_READ
80267. DEBUG_FB_SETCOLREG
80268. DEBUG_FB_WRITE
80269. DEBUG_FEATURE
80270. DEBUG_FENCE_IDLE
80271. DEBUG_FENCE_NOTIFY
80272. DEBUG_FID
80273. DEBUG_FIFO_ACCESS
80274. DEBUG_FILE_NUM
80275. DEBUG_FILTERS
80276. DEBUG_FIRSTVADDR
80277. DEBUG_FLAG
80278. DEBUG_FLAGS
80279. DEBUG_FLOW
80280. DEBUG_FLUSH
80281. DEBUG_FLUSH_ALL
80282. DEBUG_FOPS
80283. DEBUG_FOPS_RO
80284. DEBUG_FREE_GPIOS
80285. DEBUG_FREQ
80286. DEBUG_FW
80287. DEBUG_GROUP
80288. DEBUG_H
80289. DEBUG_HARD
80290. DEBUG_HARD_HEADER
80291. DEBUG_HDLC
80292. DEBUG_HEAD_CODE
80293. DEBUG_HELP_STRING_SIZE
80294. DEBUG_HEXDUMP
80295. DEBUG_HFCMULTI_CRC
80296. DEBUG_HFCMULTI_DTMF
80297. DEBUG_HFCMULTI_FIFO
80298. DEBUG_HFCMULTI_FILL
80299. DEBUG_HFCMULTI_INIT
80300. DEBUG_HFCMULTI_LOCK
80301. DEBUG_HFCMULTI_MODE
80302. DEBUG_HFCMULTI_MSG
80303. DEBUG_HFCMULTI_PLXSD
80304. DEBUG_HFCMULTI_STATE
80305. DEBUG_HFCMULTI_SYNC
80306. DEBUG_HORIZON
80307. DEBUG_HW
80308. DEBUG_HW_BCHANNEL
80309. DEBUG_HW_BFIFO
80310. DEBUG_HW_DCHANNEL
80311. DEBUG_HW_DFIFO
80312. DEBUG_HW_FIRMWARE_FIFO
80313. DEBUG_HW_OPEN
80314. DEBUG_IC
80315. DEBUG_IF
80316. DEBUG_INDEX__DEBUG_INDEX_MASK
80317. DEBUG_INDEX__DEBUG_INDEX__SHIFT
80318. DEBUG_INFO
80319. DEBUG_INIT
80320. DEBUG_INITIALISE
80321. DEBUG_INIT_DISPLAY
80322. DEBUG_INT
80323. DEBUG_INTERRUPT
80324. DEBUG_INTERRUPT_ROUTING
80325. DEBUG_INTR
80326. DEBUG_INTR_A
80327. DEBUG_INTR_B
80328. DEBUG_IO
80329. DEBUG_IOSAPIC
80330. DEBUG_IOSAPIC_IRT
80331. DEBUG_IPI
80332. DEBUG_IRING
80333. DEBUG_IRQ
80334. DEBUG_IRQS
80335. DEBUG_ISO
80336. DEBUG_ITC_SYNC
80337. DEBUG_L1
80338. DEBUG_L1OIP_INIT
80339. DEBUG_L1OIP_MGR
80340. DEBUG_L1OIP_MSG
80341. DEBUG_L1OIP_SOCKET
80342. DEBUG_L1_FSM
80343. DEBUG_L2
80344. DEBUG_L2_CTRL
80345. DEBUG_L2_FSM
80346. DEBUG_L2_RECV
80347. DEBUG_L2_TEI
80348. DEBUG_L2_TEIFSM
80349. DEBUG_LARGE_SG_ENTRIES
80350. DEBUG_LASTVADDR
80351. DEBUG_LAST_STEPS
80352. DEBUG_LBA
80353. DEBUG_LBA_CFG
80354. DEBUG_LBA_PAT
80355. DEBUG_LBA_PORT
80356. DEBUG_LED_ON_TRANSFER
80357. DEBUG_LEVEL
80358. DEBUG_LEVEL_1
80359. DEBUG_LEVEL_1_BIT
80360. DEBUG_LEVEL_2
80361. DEBUG_LEVEL_2_BIT
80362. DEBUG_LEVEL_3
80363. DEBUG_LEVEL_3_BIT
80364. DEBUG_LEVEL_4
80365. DEBUG_LEVEL_4_BIT
80366. DEBUG_LEVEL_5
80367. DEBUG_LEVEL_6
80368. DEBUG_LEVEL_7
80369. DEBUG_LEVEL_BH
80370. DEBUG_LEVEL_DATA
80371. DEBUG_LEVEL_ERROR
80372. DEBUG_LEVEL_INFO
80373. DEBUG_LEVEL_ISR
80374. DEBUG_LINK
80375. DEBUG_LLDATA
80376. DEBUG_LL_DA8XX
80377. DEBUG_LL_DAVINCI
80378. DEBUG_LL_OMAP1
80379. DEBUG_LL_OMAP7XX
80380. DEBUG_LL_PHYS_BASE
80381. DEBUG_LL_PHYS_BASE_RS1
80382. DEBUG_LL_UART_BASE
80383. DEBUG_LL_UART_OFFSET
80384. DEBUG_LL_UART_OFFSET_RS1
80385. DEBUG_LL_UART_PHYS_CRX
80386. DEBUG_LL_VIRT_BASE
80387. DEBUG_LOCKCMD
80388. DEBUG_LOCKS_WARN_ON
80389. DEBUG_LOCK_VERSION
80390. DEBUG_LOG_FRAME
80391. DEBUG_LOG_MSG
80392. DEBUG_LOW
80393. DEBUG_LOWER
80394. DEBUG_LRES_VERSION
80395. DEBUG_MAC80211
80396. DEBUG_MACE_PCI
80397. DEBUG_MAILBOX
80398. DEBUG_MANAGER
80399. DEBUG_MARKER
80400. DEBUG_MASK
80401. DEBUG_MASTER
80402. DEBUG_MAX
80403. DEBUG_MAX_BURST
80404. DEBUG_MAX_LEVEL
80405. DEBUG_MAX_NAME_LEN
80406. DEBUG_MAX_VIEWS
80407. DEBUG_MCMD
80408. DEBUG_MDIO
80409. DEBUG_MEDIA
80410. DEBUG_MEM_MAX_SIZE_DWORDS
80411. DEBUG_MEM_OP_READ
80412. DEBUG_MEM_OP_WRITE
80413. DEBUG_MEM_OP_WRITE_BYTES
80414. DEBUG_MEM_STATUS_FAILED
80415. DEBUG_MEM_STATUS_HIDDEN
80416. DEBUG_MEM_STATUS_LENGTH
80417. DEBUG_MEM_STATUS_LOCKED
80418. DEBUG_MEM_STATUS_SUCCESS
80419. DEBUG_MESSAGES
80420. DEBUG_METADATA_FLAGS
80421. DEBUG_MIDI
80422. DEBUG_MII
80423. DEBUG_MKDIRTY
80424. DEBUG_MMU_EMU
80425. DEBUG_MODE
80426. DEBUG_MODE_SELECTION
80427. DEBUG_MODULE
80428. DEBUG_MONI_1
80429. DEBUG_MONI_2
80430. DEBUG_MON_LCDD_MARK
80431. DEBUG_MON_VIO_MARK
80432. DEBUG_MSG
80433. DEBUG_MSG_QUEUE_FULL_COUNT
80434. DEBUG_MSG_THREAD
80435. DEBUG_NCQ
80436. DEBUG_NEGO
80437. DEBUG_NETLINK
80438. DEBUG_NODIRECT
80439. DEBUG_NONE
80440. DEBUG_NORMAL
80441. DEBUG_NO_WRITE
80442. DEBUG_NVRAM
80443. DEBUG_OFF
80444. DEBUG_OFF_LEVEL
80445. DEBUG_OMAP2UART1_FLAGS
80446. DEBUG_OMAP2UART2_FLAGS
80447. DEBUG_OMAP2UART3_FLAGS
80448. DEBUG_OMAP3UART3_FLAGS
80449. DEBUG_OMAP3UART4_FLAGS
80450. DEBUG_OMAP4UART3_FLAGS
80451. DEBUG_OMAP4UART4_FLAGS
80452. DEBUG_OMAPUART_FLAGS
80453. DEBUG_OMAP_GPMC_HWMOD_FLAGS
80454. DEBUG_ON
80455. DEBUG_OPEN
80456. DEBUG_OUT
80457. DEBUG_OUTPUT
80458. DEBUG_PARPORT
80459. DEBUG_PARPORT_IP32
80460. DEBUG_PARSE
80461. DEBUG_PARSE_HEADER
80462. DEBUG_PARSE_LINE
80463. DEBUG_PARSE_MSGID
80464. DEBUG_PASSUP
80465. DEBUG_PAT
80466. DEBUG_PCI
80467. DEBUG_PCICFG
80468. DEBUG_PCM
80469. DEBUG_PHASE
80470. DEBUG_PHASES
80471. DEBUG_PKT
80472. DEBUG_PKT_BYTES
80473. DEBUG_PLAY_REC
80474. DEBUG_POINTER
80475. DEBUG_POLL
80476. DEBUG_PRINT_FINAL_SETTINGS
80477. DEBUG_PRINT_INITIAL_SETTINGS
80478. DEBUG_PRINT_L1
80479. DEBUG_PRINT_L2
80480. DEBUG_PRINT_L3
80481. DEBUG_PRINT_L4
80482. DEBUG_PRINT_NVRAM
80483. DEBUG_PRINT_T
80484. DEBUG_PROBE
80485. DEBUG_PROLOG_ENTRY
80486. DEBUG_PROM
80487. DEBUG_PROM_INIT
80488. DEBUG_PROM_MAPS
80489. DEBUG_PROM_TREE
80490. DEBUG_PROTO
80491. DEBUG_PS
80492. DEBUG_PS2
80493. DEBUG_PSC
80494. DEBUG_PSM
80495. DEBUG_PVC
80496. DEBUG_PW
80497. DEBUG_Q40INT
80498. DEBUG_QLA1280
80499. DEBUG_QLA1280_INTR
80500. DEBUG_QMGR
80501. DEBUG_QUEUE
80502. DEBUG_QUEUES
80503. DEBUG_QUEUE_FUNC
80504. DEBUG_RANGE_CHECK
80505. DEBUG_READ
80506. DEBUG_REALMODE
80507. DEBUG_RECORD
80508. DEBUG_REG
80509. DEBUG_REG_ACCESS_NUM
80510. DEBUG_REG_ACCESS_REG
80511. DEBUG_REG_ACCESS_TYPE
80512. DEBUG_REG_ADDR
80513. DEBUG_REG_DMN
80514. DEBUG_REPORT_EVENT_ID
80515. DEBUG_REQUEST_GPIOS
80516. DEBUG_REQUEST_GPIOS_MATCH
80517. DEBUG_RESET
80518. DEBUG_RESET_DISPLAY
80519. DEBUG_RESET_FULL
80520. DEBUG_RESET_I830
80521. DEBUG_RESET_RENDER
80522. DEBUG_RESOURCES
80523. DEBUG_RESULT
80524. DEBUG_RINGS
80525. DEBUG_RMT
80526. DEBUG_RW
80527. DEBUG_RWSEMS_WARN_ON
80528. DEBUG_RX
80529. DEBUG_SBA
80530. DEBUG_SBA_INIT
80531. DEBUG_SBA_RESOURCE
80532. DEBUG_SBA_RUN
80533. DEBUG_SBA_RUN_SG
80534. DEBUG_SCAN
80535. DEBUG_SCATTER
80536. DEBUG_SCRIPT
80537. DEBUG_SDIO
80538. DEBUG_SEND_ERR
80539. DEBUG_SERVICE_CALLBACK_LINE
80540. DEBUG_SET_ADDR_WIN
80541. DEBUG_SHIFT
80542. DEBUG_SIG
80543. DEBUG_SIG_LEVEL
80544. DEBUG_SLEEP
80545. DEBUG_SLOT_HANDLER_COUNT
80546. DEBUG_SLOT_HANDLER_LINE
80547. DEBUG_SMP
80548. DEBUG_SMT
80549. DEBUG_SMTF
80550. DEBUG_SMU
80551. DEBUG_SOCKET
80552. DEBUG_SPI
80553. DEBUG_SPINLOCK_BUG_ON
80554. DEBUG_SPRINTF_MAX_ARGS
80555. DEBUG_SROM
80556. DEBUG_STATE
80557. DEBUG_STATS_CQE_CNT
80558. DEBUG_STATS_INTR_REARM
80559. DEBUG_STATS_NAPI_POLL
80560. DEBUG_STATS_RX_BUFF_CNT
80561. DEBUG_STATS_TXQ_POST
80562. DEBUG_STIFB_REGS
80563. DEBUG_STREAM
80564. DEBUG_STREAM_DUMP
80565. DEBUG_SUPERIO_INIT
80566. DEBUG_SUSPEND
80567. DEBUG_SYSFS
80568. DEBUG_TAGS
80569. DEBUG_TARGET
80570. DEBUG_TESTMODE
80571. DEBUG_TI81XXUART1_FLAGS
80572. DEBUG_TI81XXUART2_FLAGS
80573. DEBUG_TI81XXUART3_FLAGS
80574. DEBUG_TICK_SYNC
80575. DEBUG_TIMER
80576. DEBUG_TIME_EACH_UPDATE
80577. DEBUG_TIME_FIRST_UPDATE
80578. DEBUG_TIMING
80579. DEBUG_TIMING_BIT
80580. DEBUG_TINY
80581. DEBUG_TLB
80582. DEBUG_TRACE
80583. DEBUG_TRANSCMD
80584. DEBUG_TX
80585. DEBUG_UNALIGNED_TRAP
80586. DEBUG_UPDATE_DISPLAY
80587. DEBUG_UPPER
80588. DEBUG_USBREQ
80589. DEBUG_VALUE
80590. DEBUG_VALUES
80591. DEBUG_VAR
80592. DEBUG_VARIABLE
80593. DEBUG_VECTOR_VADDR
80594. DEBUG_VERBOSE
80595. DEBUG_VERIFY_GPIOS
80596. DEBUG_VERSION
80597. DEBUG_WAIT_SLEEP
80598. DEBUG_WAIT_TIMEOUT
80599. DEBUG_WARN
80600. DEBUG_WRAPPER
80601. DEBUG_WRITE
80602. DEBUG_WRITE_REGISTER
80603. DEBUG_WRITE_VMEM
80604. DEBUG_bytes
80605. DEBUG_print
80606. DEB_ADDCMD
80607. DEB_ANY
80608. DEB_CAP
80609. DEB_D
80610. DEB_EE
80611. DEB_EN
80612. DEB_ERRORS
80613. DEB_I2C
80614. DEB_INIT
80615. DEB_INT
80616. DEB_INTS
80617. DEB_MULTI
80618. DEB_OPEN
80619. DEB_OUT_SYSLOG
80620. DEB_PROBE
80621. DEB_RESET
80622. DEB_RXADDR
80623. DEB_RXFRAME
80624. DEB_S
80625. DEB_SERIOUS
80626. DEB_STARTTX
80627. DEB_STATUS
80628. DEB_STRUCT
80629. DEB_TDR
80630. DEB_TXADDR
80631. DEB_VBI
80632. DECAY
80633. DECAY_BITS
80634. DECAY_MASK
80635. DECAY_SHIFT
80636. DECCTR
80637. DECCYCLE
80638. DECIM0_IN
80639. DECIM0_OUT
80640. DECIMAL
80641. DECIMAL_FACTORING
80642. DECIMATED_DIMENSION
80643. DECIMATION_ENAB
80644. DECIMM0_IN
80645. DECIMM0_OUT
80646. DECIMM1_IN
80647. DECIMM1_OUT
80648. DECIMM2_IN
80649. DECIMM2_OUT
80650. DECIMM3_IN
80651. DECIMM3_OUT
80652. DECIS
80653. DECI_KELVIN_TO_CELSIUS
80654. DECI_KELVIN_TO_MILLICELSIUS
80655. DECI_KELVIN_TO_MILLICELSIUS_WITH_OFFSET
80656. DECLARE
80657. DECLARE_2681_FIELD
80658. DECLARE_6x6_KEYMAP
80659. DECLARE_9x9_KEYMAP
80660. DECLARE_ACPI_CROS_LAPTOP
80661. DECLARE_ACPI_FWNODE_OPS
80662. DECLARE_AD5064_CHANNELS
80663. DECLARE_AD5065_CHANNELS
80664. DECLARE_AD5449_CHANNELS
80665. DECLARE_AD5624R_CHANNELS
80666. DECLARE_AD5676_CHANNELS
80667. DECLARE_AD5679_CHANNELS
80668. DECLARE_AD5686_CHANNELS
80669. DECLARE_AD5693_CHANNELS
80670. DECLARE_AD5764_CHANNELS
80671. DECLARE_AD7787_CHANNELS
80672. DECLARE_AD7791_CHANNELS
80673. DECLARE_AD7793_CHANNELS
80674. DECLARE_AD7795_CHANNELS
80675. DECLARE_AD7797_CHANNELS
80676. DECLARE_AD7799_CHANNELS
80677. DECLARE_AD7923_CHANNELS
80678. DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS
80679. DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS
80680. DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS
80681. DECLARE_ADAU17X1_DSP_MUX_CTRL
80682. DECLARE_ADDR_MATCH
80683. DECLARE_AMD_DEV
80684. DECLARE_ANON_TRANSPORT_CLASS
80685. DECLARE_APQ_GPIO_PINS
80686. DECLARE_ARGS
80687. DECLARE_ARRAY_ALLOCATOR
80688. DECLARE_ATTRIBUTE
80689. DECLARE_BASIC_PRINT_TYPE_FUNC
80690. DECLARE_BITMAP
80691. DECLARE_BTRFS_SETGET_BITS
80692. DECLARE_BUILTIN_FIRMWARE
80693. DECLARE_BUILTIN_FIRMWARE_SIZE
80694. DECLARE_BUTTON
80695. DECLARE_COMPLETION
80696. DECLARE_COMPLETION_ONSTACK
80697. DECLARE_COMPLETION_ONSTACK_MAP
80698. DECLARE_COUNTER
80699. DECLARE_CRC8_TABLE
80700. DECLARE_CROS_LAPTOP
80701. DECLARE_CRYPTO_WAIT
80702. DECLARE_CS5536_MODULE
80703. DECLARE_DEFERRABLE_WORK
80704. DECLARE_DELAYED_WORK
80705. DECLARE_DM_KCOPYD_THROTTLE_WITH_MODULE_PARM
80706. DECLARE_DPM_WATCHDOG_ON_STACK
80707. DECLARE_DYN_IN
80708. DECLARE_DYN_OUT
80709. DECLARE_EARLY_PER_CPU
80710. DECLARE_EARLY_PER_CPU_READ_MOSTLY
80711. DECLARE_EVENT_CLASS
80712. DECLARE_EVENT_CLASS_NOP
80713. DECLARE_EVENT_CLASS_SCHEDSTAT
80714. DECLARE_EVENT_NOP
80715. DECLARE_EVT
80716. DECLARE_EVT_SHOW
80717. DECLARE_EVT_STORE
80718. DECLARE_EWMA
80719. DECLARE_EXPORT
80720. DECLARE_FAULT_ATTR
80721. DECLARE_FIFO
80722. DECLARE_GENERIC_PCI_DEV
80723. DECLARE_GLOBALS_HERE
80724. DECLARE_HASHTABLE
80725. DECLARE_HEAP
80726. DECLARE_ICH_DEV
80727. DECLARE_INIT_PER_CPU
80728. DECLARE_INTC_DESC
80729. DECLARE_INTC_DESC_ACK
80730. DECLARE_IO
80731. DECLARE_IPQ_GPIO_PINS
80732. DECLARE_IRQ
80733. DECLARE_KFIFO
80734. DECLARE_KFIFO_PTR
80735. DECLARE_LOAD_FUNC
80736. DECLARE_LTC2632_CHANNELS
80737. DECLARE_MASK_VAL
80738. DECLARE_MSM_GPIO_PIN
80739. DECLARE_MSM_GPIO_PINS
80740. DECLARE_NAPI_STRUCT
80741. DECLARE_NET_DEVICE_STATS
80742. DECLARE_NV_DEV
80743. DECLARE_PCI_FIXUP_CLASS_EARLY
80744. DECLARE_PCI_FIXUP_CLASS_ENABLE
80745. DECLARE_PCI_FIXUP_CLASS_FINAL
80746. DECLARE_PCI_FIXUP_CLASS_HEADER
80747. DECLARE_PCI_FIXUP_CLASS_RESUME
80748. DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY
80749. DECLARE_PCI_FIXUP_CLASS_SUSPEND
80750. DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE
80751. DECLARE_PCI_FIXUP_EARLY
80752. DECLARE_PCI_FIXUP_ENABLE
80753. DECLARE_PCI_FIXUP_FINAL
80754. DECLARE_PCI_FIXUP_HEADER
80755. DECLARE_PCI_FIXUP_RESUME
80756. DECLARE_PCI_FIXUP_RESUME_EARLY
80757. DECLARE_PCI_FIXUP_SECTION
80758. DECLARE_PCI_FIXUP_SUSPEND
80759. DECLARE_PCI_FIXUP_SUSPEND_LATE
80760. DECLARE_PDC2026X_DEV
80761. DECLARE_PDCNEW_DEV
80762. DECLARE_PERIPHERAL_CLOCK
80763. DECLARE_PER_CPU
80764. DECLARE_PER_CPU_ALIGNED
80765. DECLARE_PER_CPU_DECRYPTED
80766. DECLARE_PER_CPU_FIRST
80767. DECLARE_PER_CPU_PAGE_ALIGNED
80768. DECLARE_PER_CPU_READ_MOSTLY
80769. DECLARE_PER_CPU_SECTION
80770. DECLARE_PER_CPU_SHARED_ALIGNED
80771. DECLARE_PIIX_DEV
80772. DECLARE_PRIMITIVE
80773. DECLARE_QCA_GPIO_PINS
80774. DECLARE_RDMA_OBJ_SIZE
80775. DECLARE_REFO_CLOCK
80776. DECLARE_RESORT_RB
80777. DECLARE_RESORT_RB_INTLIST
80778. DECLARE_RESORT_RB_MACHINE_THREADS
80779. DECLARE_RTL_COND
80780. DECLARE_RWSEM
80781. DECLARE_SII_DEV
80782. DECLARE_SNMP_STAT
80783. DECLARE_SOCKADDR
80784. DECLARE_SPACE_INFO_UPDATE
80785. DECLARE_STATIC_KEY_FALSE
80786. DECLARE_STATIC_KEY_TRUE
80787. DECLARE_SWAITQUEUE
80788. DECLARE_SWAIT_QUEUE_HEAD
80789. DECLARE_SWAIT_QUEUE_HEAD_ONSTACK
80790. DECLARE_TASKLET
80791. DECLARE_TASKLET_DISABLED
80792. DECLARE_TASK_FUNC
80793. DECLARE_TCS
80794. DECLARE_TEST_OK
80795. DECLARE_TI_ADS7950_12_CHANNELS
80796. DECLARE_TI_ADS7950_16_CHANNELS
80797. DECLARE_TI_ADS7950_4_CHANNELS
80798. DECLARE_TI_ADS7950_8_CHANNELS
80799. DECLARE_TLC4541_CHANNELS
80800. DECLARE_TLV_CONTAINER
80801. DECLARE_TLV_DB_LINEAR
80802. DECLARE_TLV_DB_MINMAX
80803. DECLARE_TLV_DB_MINMAX_MUTE
80804. DECLARE_TLV_DB_RANGE
80805. DECLARE_TLV_DB_SCALE
80806. DECLARE_TRACE
80807. DECLARE_TRACE_CONDITION
80808. DECLARE_TRACE_NOARGS
80809. DECLARE_TRANSPORT_CLASS
80810. DECLARE_UAC3_FEATURE_UNIT_DESCRIPTOR
80811. DECLARE_UAC3_POWER_DOMAIN_DESCRIPTOR
80812. DECLARE_UAC_AC_HEADER_DESCRIPTOR
80813. DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR
80814. DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC
80815. DECLARE_USB_FUNCTION
80816. DECLARE_USB_FUNCTION_INIT
80817. DECLARE_USB_MIDI_OUT_JACK_DESCRIPTOR
80818. DECLARE_USB_MS_ENDPOINT_DESCRIPTOR
80819. DECLARE_UVC_EXTENSION_UNIT_DESCRIPTOR
80820. DECLARE_UVC_FRAME_MJPEG
80821. DECLARE_UVC_FRAME_UNCOMPRESSED
80822. DECLARE_UVC_HEADER_DESCRIPTOR
80823. DECLARE_UVC_INPUT_HEADER_DESCRIPTOR
80824. DECLARE_UVC_OUTPUT_HEADER_DESCRIPTOR
80825. DECLARE_UVC_SELECTOR_UNIT_DESCRIPTOR
80826. DECLARE_UVERBS_GLOBAL_METHODS
80827. DECLARE_UVERBS_NAMED_METHOD
80828. DECLARE_UVERBS_NAMED_METHOD_DESTROY
80829. DECLARE_UVERBS_NAMED_OBJECT
80830. DECLARE_UVERBS_OBJECT
80831. DECLARE_UVERBS_WRITE
80832. DECLARE_UVERBS_WRITE_EX
80833. DECLARE_VAL_CONTEXT
80834. DECLARE_VVAR
80835. DECLARE_WAITQUEUE
80836. DECLARE_WAIT_QUEUE_HEAD
80837. DECLARE_WAIT_QUEUE_HEAD_ONSTACK
80838. DECLARE_WORK
80839. DECL_CHAIN
80840. DECL_NAME_LENGTH
80841. DECL_NAME_POINTER
80842. DECNET_IOCTL_BASE
80843. DECODE
80844. DECODED_BUF_SIZE
80845. DECODE_CHANNEL_ID
80846. DECODE_CMD_AA
80847. DECODE_CMD_BB
80848. DECODE_CMD_CC
80849. DECODE_CMD_DD
80850. DECODE_CODE_ERR
80851. DECODE_CTXID
80852. DECODE_DISP_ERR
80853. DECODE_ERROR_LIMIT
80854. DECODE_FAIL_PKT_0
80855. DECODE_FAIL_PKT_N
80856. DECODE_FORMAT_UNCOMPRESSED_10_BIT
80857. DECODE_FORMAT_UNCOMPRESSED_12_BIT
80858. DECODE_FORMAT_UNCOMPRESSED_14_BIT
80859. DECODE_FORMAT_UNCOMPRESSED_6_BIT
80860. DECODE_FORMAT_UNCOMPRESSED_8_BIT
80861. DECODE_HEAD
80862. DECODE_INSN_I10
80863. DECODE_INSN_I16
80864. DECODE_INSN_I18
80865. DECODE_INSN_I7
80866. DECODE_INSN_I8
80867. DECODE_INSN_I9a
80868. DECODE_INSN_I9b
80869. DECODE_INSN_RA
80870. DECODE_INSN_RB
80871. DECODE_INSN_RC
80872. DECODE_INSN_RT
80873. DECODE_INSN_U10
80874. DECODE_INSN_U14
80875. DECODE_INSN_U16
80876. DECODE_INSN_U18
80877. DECODE_INSN_U7
80878. DECODE_INSN_U8
80879. DECODE_INSN_U9a
80880. DECODE_INSN_U9b
80881. DECODE_MODE_NEC
80882. DECODE_MODE_RAW
80883. DECODE_OK
80884. DECODE_STR_LEN
80885. DECODE_TAIL
80886. DECODE_TYPE_BITS
80887. DECODE_TYPE_CUSTOM
80888. DECODE_TYPE_EMULATE
80889. DECODE_TYPE_END
80890. DECODE_TYPE_MASK
80891. DECODE_TYPE_OR
80892. DECODE_TYPE_REJECT
80893. DECODE_TYPE_SIMULATE
80894. DECODE_TYPE_TABLE
80895. DECOMP0_ENABLE
80896. DECOMP1_ENABLE
80897. DECOMP2_ENABLE
80898. DECOMP3_ENABLE
80899. DECOMP4_ENABLE
80900. DECOMP5_ENABLE
80901. DECOMPOSE
80902. DECOMPRESSOR_H
80903. DECOMPRESS_BUNZIP2_H
80904. DECOMPRESS_FRONTEND_INIT
80905. DECOMPRESS_GENERIC_H
80906. DECOMPRESS_UNLZ4_H
80907. DECOMPRESS_UNLZMA_H
80908. DECOMPRESS_UNLZO_H
80909. DECOMPRESS_UNXZ_H
80910. DECOMPR_MM_H
80911. DECOMP_BUSY_TIMEOUT
80912. DECOMP_CHECK_ENABLE
80913. DECOMP_ERROR
80914. DECOMP_FATALERROR
80915. DECON_BLENDCON
80916. DECON_BLENDERQx
80917. DECON_CMU
80918. DECON_CMU_ALL_CLKGATE_ENABLE
80919. DECON_CMU_MEM_CLKGATE_ENABLE
80920. DECON_CMU_SE_CLKGATE_ENABLE
80921. DECON_CMU_SFR_CLKGATE_ENABLE
80922. DECON_CRCCTRL
80923. DECON_CRCRDATA
80924. DECON_CRFMID
80925. DECON_ENHANCER_CTRL
80926. DECON_FRAMEFIFO_REG0
80927. DECON_FRAMEFIFO_REG7
80928. DECON_FRAMEFIFO_REG8
80929. DECON_FRAMEFIFO_STATUS
80930. DECON_FRAME_SIZE
80931. DECON_LINECNT_OP_THRESHOLD
80932. DECON_LOCALxSIZE
80933. DECON_OPE_VIDW0xADD0
80934. DECON_OPE_VIDW0xADD1
80935. DECON_QOSCTRL
80936. DECON_QOSLUT07_00
80937. DECON_QOSLUT15_08
80938. DECON_SHADOWCON
80939. DECON_TRIGCON
80940. DECON_TRIGSKIP
80941. DECON_UPDATE
80942. DECON_UPDATE_SCHEME
80943. DECON_UPDATE_SLAVE_SYNC
80944. DECON_UPDATE_STANDALONE_F
80945. DECON_VCLKCON0
80946. DECON_VIDCON0
80947. DECON_VIDCON1
80948. DECON_VIDCON2
80949. DECON_VIDCON3
80950. DECON_VIDCON4
80951. DECON_VIDINTCON0
80952. DECON_VIDINTCON1
80953. DECON_VIDINTCON2
80954. DECON_VIDINTCON3
80955. DECON_VIDOSDxA
80956. DECON_VIDOSDxB
80957. DECON_VIDOSDxC
80958. DECON_VIDOSDxD
80959. DECON_VIDOSDxE
80960. DECON_VIDOSDxH
80961. DECON_VIDOUTCON0
80962. DECON_VIDTCON0
80963. DECON_VIDTCON00
80964. DECON_VIDTCON01
80965. DECON_VIDTCON1
80966. DECON_VIDTCON10
80967. DECON_VIDTCON11
80968. DECON_VIDTCON2
80969. DECON_VIDW0xADD0B0
80970. DECON_VIDW0xADD0B1
80971. DECON_VIDW0xADD0B2
80972. DECON_VIDW0xADD1B0
80973. DECON_VIDW0xADD1B1
80974. DECON_VIDW0xADD1B2
80975. DECON_VIDW0xADD2
80976. DECON_W013DSTREOCON
80977. DECON_W233DSTREOCON
80978. DECON_WINCONx
80979. DECON_WINxMAP
80980. DECON_WxKEYALPHA
80981. DECON_WxKEYCON0
80982. DECON_WxKEYCON1
80983. DECORR_DEN0
80984. DECORR_RQD0ENABLE
80985. DECORSR_JR0
80986. DECORSR_VALID
80987. DECO_BLOCK_NUMBER
80988. DECO_JQCR_FOUR
80989. DECO_JQCR_WHL
80990. DECO_OP_STATUS_HI_ERR_MASK
80991. DECO_RESET
80992. DECO_RESET_0
80993. DECO_RESET_1
80994. DECO_RESET_2
80995. DECO_RESET_3
80996. DECO_RESET_4
80997. DECO_STAT_HOST_ERR
80998. DECREMENT
80999. DECREMENTER_DEFAULT_MAX
81000. DECREMENTER_EXCEPTION
81001. DECROUND
81002. DECRYPT
81003. DECRYPT_128
81004. DECRYPT_128_2
81005. DECRYPT_192
81006. DECRYPT_192_2
81007. DECRYPT_256
81008. DECRYPT_256_2
81009. DECRYPT_256_TWO_ROUNDS_2
81010. DECRYPT_TWO_ROUNDS
81011. DECRYPT_TWO_ROUNDS_2
81012. DECRYPT_TWO_ROUNDS_LAST
81013. DECRYPT_TWO_ROUNDS_LAST_2
81014. DECTYPES
81015. DECT_POWER_ON
81016. DEC_8190_ALIGN_MASK
81017. DEC_CNFG_CORRECT
81018. DEC_CPU_INR_FPU
81019. DEC_CPU_INR_SW0
81020. DEC_CPU_INR_SW1
81021. DEC_CPU_IRQ_ALL
81022. DEC_CPU_IRQ_BASE
81023. DEC_CPU_IRQ_MASK
81024. DEC_CPU_IRQ_NR
81025. DEC_DIR_INODE_NLINK
81026. DEC_EMPTY_EN
81027. DEC_ERR_RET
81028. DEC_EXITS
81029. DEC_IRQ_AB_RECV
81030. DEC_IRQ_AB_RXDMA
81031. DEC_IRQ_AB_RXERR
81032. DEC_IRQ_AB_TXDMA
81033. DEC_IRQ_AB_TXERR
81034. DEC_IRQ_AB_XMIT
81035. DEC_IRQ_ASC
81036. DEC_IRQ_ASC_DMA
81037. DEC_IRQ_ASC_ERR
81038. DEC_IRQ_ASC_MERR
81039. DEC_IRQ_BUS
81040. DEC_IRQ_CASCADE
81041. DEC_IRQ_DZ11
81042. DEC_IRQ_FLOPPY
81043. DEC_IRQ_FLOPPY_ERR
81044. DEC_IRQ_FPU
81045. DEC_IRQ_HALT
81046. DEC_IRQ_ISDN
81047. DEC_IRQ_ISDN_ERR
81048. DEC_IRQ_ISDN_RXDMA
81049. DEC_IRQ_ISDN_TXDMA
81050. DEC_IRQ_LANCE
81051. DEC_IRQ_LANCE_MERR
81052. DEC_IRQ_PSU
81053. DEC_IRQ_RTC
81054. DEC_IRQ_SCC0
81055. DEC_IRQ_SCC0A_RXDMA
81056. DEC_IRQ_SCC0A_RXERR
81057. DEC_IRQ_SCC0A_TXDMA
81058. DEC_IRQ_SCC0A_TXERR
81059. DEC_IRQ_SCC1
81060. DEC_IRQ_SCC1A_RXDMA
81061. DEC_IRQ_SCC1A_RXERR
81062. DEC_IRQ_SCC1A_TXDMA
81063. DEC_IRQ_SCC1A_TXERR
81064. DEC_IRQ_SII
81065. DEC_IRQ_TC0
81066. DEC_IRQ_TC1
81067. DEC_IRQ_TC2
81068. DEC_IRQ_TC5
81069. DEC_IRQ_TC6
81070. DEC_IRQ_TIMER
81071. DEC_IRQ_VIDEO
81072. DEC_IS_DYNALLOC
81073. DEC_IS_MULTI
81074. DEC_IS_PREALLOC
81075. DEC_IS_SINGLE
81076. DEC_MAX_ASIC_INTS
81077. DEC_MAX_CPU_INTS
81078. DEC_MULTI_STREAM_CAPABILITY
81079. DEC_NR_INTS
81080. DEC_PROF
81081. DEC_RETURN_FAMILY_TEST
81082. DEC_START1
81083. DEC_START1_MUX
81084. DEC_START2
81085. DEC_START2_MUX
81086. DEC_STAT
81087. DEC_STATUS
81088. DEC_STATUS_A_ECC_FAIL
81089. DEC_STATUS_ERR_COUNT_MASK
81090. DEC_STATUS_ERR_COUNT_SHIFT
81091. DEC_STAT_BUF
81092. DEC_STAT_BUF_CORR_SEC_FLAG_MASK
81093. DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT
81094. DEC_STAT_BUF_FAIL_SEC_FLAG_MASK
81095. DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT
81096. DEC_STAT_BUF_MAX_CORR_CNT_MASK
81097. DEC_STAT_BUF_MAX_CORR_CNT_SHIFT
81098. DEC_STAT_RESULT
81099. DEC_VIF
81100. DEC_VP9_STATIC_BUFFER_SIZE
81101. DEDICATED_KEY_VAL
81102. DEDICATED_OFFSET
81103. DED_ERR_MASK
81104. DED_WEIGHT
81105. DEEMPH_COEF1
81106. DEEMPH_COEF2
81107. DEEMPH_COEFF1
81108. DEEMPH_COEFF2
81109. DEEMPH_DENOM1
81110. DEEMPH_DENOM2
81111. DEEMPH_GAIN
81112. DEEMPH_GAIN_CTL
81113. DEEMPH_NUMER1
81114. DEEMPH_NUMER2
81115. DEEMPH_SHIFT
81116. DEEPSLEEPOK
81117. DEEPSLEEP_INIT
81118. DEEPSLEEP_SLEEPCOUNT
81119. DEEPSLEEP_SLEEPCOUNT_MASK
81120. DEEPSLEEP_SLEEPENABLE_BIT
81121. DEEPSLEEP_TO_EXECUTE
81122. DEEPSLEEP_TO_EXECUTEOK
81123. DEEP_COLOR_EN
81124. DEEP_COLOR_MODE_MASK
81125. DEEP_SLEEP
81126. DEEP_SLEEP_CLK_SEL
81127. DEEP_SLEEP_CLK_SEL_MASK
81128. DEEP_SLEEP_CNTL
81129. DEEP_SLEEP_CNTL2
81130. DEEP_SLEEP_IDLE_TIME
81131. DEEP_SLEEP_OFF
81132. DEEP_SLEEP_ON
81133. DEEP_SLEEP_OUT_N
81134. DEF
81135. DEF3OP
81136. DEF3OPNEG
81137. DEFAULT
81138. DEFAULTBCNT
81139. DEFAULTIOBASE
81140. DEFAULTQUEUE_G
81141. DEFAULTQUEUE_M
81142. DEFAULTQUEUE_S
81143. DEFAULTSYNC
81144. DEFAULTTIME2RETAIN
81145. DEFAULTTIME2WAIT
81146. DEFAULT_11A_TXP_IDX
81147. DEFAULT_2RXQ_RIR0
81148. DEFAULT_80003ES2LAN_TIPG_IPGR2
81149. DEFAULT_82542_TIPG_IPGR1
81150. DEFAULT_82542_TIPG_IPGR2
81151. DEFAULT_82542_TIPG_IPGT
81152. DEFAULT_82543_TIPG_IPGR1
81153. DEFAULT_82543_TIPG_IPGR2
81154. DEFAULT_82543_TIPG_IPGT_COPPER
81155. DEFAULT_82543_TIPG_IPGT_FIBER
81156. DEFAULT_8RXQ_RIR0
81157. DEFAULT_A0_BOARD_BASIC_CAPABILITIES
81158. DEFAULT_ACA_CUR_MAX
81159. DEFAULT_ACA_CUR_MIN
81160. DEFAULT_ACOMP_ATIME
81161. DEFAULT_ACOMP_GAIN
81162. DEFAULT_ACOMP_RTIME
81163. DEFAULT_ACOMP_THRESHOLD
81164. DEFAULT_ADDEND
81165. DEFAULT_ADDR_MASK
81166. DEFAULT_AD_HOC_CHANNEL
81167. DEFAULT_AD_HOC_CHANNEL_A
81168. DEFAULT_AE_GROUP
81169. DEFAULT_AGP_APER_SIZE
81170. DEFAULT_AID_MODE
81171. DEFAULT_ALARM_SEL
81172. DEFAULT_ALSA_IDX
81173. DEFAULT_ALT
81174. DEFAULT_APERTURE_SIZE
81175. DEFAULT_APERTURE_STRING
81176. DEFAULT_ARM64_GUEST_STACK_VADDR_MIN
81177. DEFAULT_ASYNC_TIMEOUT
81178. DEFAULT_AUTH_PAYLOAD_TIMEOUT
81179. DEFAULT_AUTORESUME
81180. DEFAULT_AUTOSUSPEND_DELAY
81181. DEFAULT_AUX_MAX_DATA_SIZE
81182. DEFAULT_AUX_PAGES
81183. DEFAULT_B0_BOARD_BASIC_CAPABILITIES
81184. DEFAULT_BACK_TO_BACK_IPG
81185. DEFAULT_BAND
81186. DEFAULT_BANK_SWITCH_TIMEOUT
81187. DEFAULT_BASE
81188. DEFAULT_BATTERY_OVERCURRENT
81189. DEFAULT_BAUD
81190. DEFAULT_BAUD_DIV
81191. DEFAULT_BAUD_RATE
81192. DEFAULT_BCN_AVG_FACTOR
81193. DEFAULT_BCN_MISS_TIMEOUT
81194. DEFAULT_BEACONINTERVAL
81195. DEFAULT_BEACON_ESSID
81196. DEFAULT_BEACON_INTERVAL
81197. DEFAULT_BELL_DURATION
81198. DEFAULT_BELL_PITCH
81199. DEFAULT_BG_SCAN_PERIOD
81200. DEFAULT_BITPERSAMPLE
81201. DEFAULT_BITRATE
81202. DEFAULT_BITS_PER_CHAR
81203. DEFAULT_BLK_SZ
81204. DEFAULT_BL_NAME
81205. DEFAULT_BMI_DISP_TH
81206. DEFAULT_BOUNCE_INTERVAL
81207. DEFAULT_BPF_LEN
81208. DEFAULT_BPP
81209. DEFAULT_BRIGHTNESS
81210. DEFAULT_BRIGHTNESS_NTSC
81211. DEFAULT_BSS_SECTION_ALIGNMENT
81212. DEFAULT_BUFFER_BYTES
81213. DEFAULT_BUFFER_BYTES_MULTICH
81214. DEFAULT_BUFFER_SECTORS
81215. DEFAULT_BUFFER_SIZE
81216. DEFAULT_BUFF_SIZE
81217. DEFAULT_BUFSIZE
81218. DEFAULT_BUF_POOL_SIZE
81219. DEFAULT_BULK_ALTSETTING
81220. DEFAULT_BULK_IN_DELAY
81221. DEFAULT_BURST_CAP_SIZE
81222. DEFAULT_B_MAX_DSL
81223. DEFAULT_CACHED_DEV_ERROR_LIMIT
81224. DEFAULT_CACHELINE
81225. DEFAULT_CACHE_OVERRIDE
81226. DEFAULT_CAPTURE_STILL_FRAMERATE
81227. DEFAULT_CAPTURE_STILL_HEIGHT
81228. DEFAULT_CAPTURE_STILL_WIDTH
81229. DEFAULT_CAPTURE_VIDEO_FRAMERATE
81230. DEFAULT_CAPTURE_VIDEO_HEIGHT
81231. DEFAULT_CAPTURE_VIDEO_WIDTH
81232. DEFAULT_CARDBUS_IO_SIZE
81233. DEFAULT_CARDBUS_MEM_SIZE
81234. DEFAULT_CATASTROPHIC_ERR
81235. DEFAULT_CDMM_BASE_ADDR
81236. DEFAULT_CDP_CUR_MAX
81237. DEFAULT_CDP_CUR_MIN
81238. DEFAULT_CFG
81239. DEFAULT_CGC_EN
81240. DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT
81241. DEFAULT_CHECK_POLL
81242. DEFAULT_CIFS_CALLED_NAME
81243. DEFAULT_CKSEL
81244. DEFAULT_CLK_FREQ
81245. DEFAULT_CLK_HZ
81246. DEFAULT_CLK_RATE_HZ
81247. DEFAULT_CLK_SPEED
81248. DEFAULT_CLUSTER_NAME
81249. DEFAULT_CMD
81250. DEFAULT_CMD6_TIMEOUT_MS
81251. DEFAULT_CMD_QLEN
81252. DEFAULT_CMD_Q_SIZE
81253. DEFAULT_CNT_THRSHLD
81254. DEFAULT_CODEL_LIMIT
81255. DEFAULT_COLORSPACE_MODE
81256. DEFAULT_COMADJ
81257. DEFAULT_COMMAND_LINE
81258. DEFAULT_CONN_INFO_MAX_AGE
81259. DEFAULT_CONN_INFO_MIN_AGE
81260. DEFAULT_CONSTANT_VOLT
81261. DEFAULT_CONTRAST
81262. DEFAULT_CONTRAST_NTSC
81263. DEFAULT_CORE_CNTRL
81264. DEFAULT_CORE_TIMER_INTERRUPT
81265. DEFAULT_COUNT
81266. DEFAULT_COUNT_WIDTH
81267. DEFAULT_COW
81268. DEFAULT_COW_THRESHOLD
81269. DEFAULT_CPC_BASE_ADDR
81270. DEFAULT_CPU_TIME_MAX_PERCENT
81271. DEFAULT_CP_HQD_PERSISTENT_STATE
81272. DEFAULT_CSC_EQ
81273. DEFAULT_CSC_RANGE
81274. DEFAULT_CURSOR_BLINK_MS
81275. DEFAULT_CURSOR_BLINK_RATE
81276. DEFAULT_C_MIN
81277. DEFAULT_DATA_AVG_FACTOR
81278. DEFAULT_DATA_LEB
81279. DEFAULT_DATA_MEM
81280. DEFAULT_DATA_SECTION_ALIGNMENT
81281. DEFAULT_DBI_ATU_OFFSET
81282. DEFAULT_DCLK_FREQ
81283. DEFAULT_DCP_CUR_MAX
81284. DEFAULT_DCP_CUR_MIN
81285. DEFAULT_DEBOUNCE
81286. DEFAULT_DEBOUNCE_MSEC
81287. DEFAULT_DEBUG
81288. DEFAULT_DEBUG_LEVEL
81289. DEFAULT_DEBUG_LEVEL_SHIFT
81290. DEFAULT_DEBUG_MASK
81291. DEFAULT_DELAY
81292. DEFAULT_DESTID
81293. DEFAULT_DIB0070_I2C_ADDRESS
81294. DEFAULT_DIB0090_I2C_ADDRESS
81295. DEFAULT_DIB3000MC_I2C_ADDRESS
81296. DEFAULT_DIB3000P_I2C_ADDRESS
81297. DEFAULT_DIB7000M_I2C_ADDRESS
81298. DEFAULT_DIB7000P_I2C_ADDRESS
81299. DEFAULT_DIB8000_I2C_ADDRESS
81300. DEFAULT_DIB9000_I2C_ADDRESS
81301. DEFAULT_DISCARD_GRANULARITY
81302. DEFAULT_DISCRETE_PSET
81303. DEFAULT_DISP_LIMIT
81304. DEFAULT_DL_512_FIRST
81305. DEFAULT_DMA_CAM_NUM_OF_ENTRIES
81306. DEFAULT_DMA_COHERENT_POOL_SIZE
81307. DEFAULT_DMA_COMM_Q_HIGH
81308. DEFAULT_DMA_COMM_Q_LOW
81309. DEFAULT_DMA_CR1
81310. DEFAULT_DMA_DBG_CNT_MODE
81311. DEFAULT_DMA_DESCRIPTOR_SPACING
81312. DEFAULT_DMA_ERR
81313. DEFAULT_DMA_HIGH_WATER
81314. DEFAULT_DMA_HINT_REG
81315. DEFAULT_DMA_LOW_WATER
81316. DEFAULT_DMA_PBL
81317. DEFAULT_DMA_SOS_EMERGENCY
81318. DEFAULT_DMA_WATCHDOG
81319. DEFAULT_DOMAIN_ADDRESS_WIDTH
81320. DEFAULT_DPU_LINE_WIDTH
81321. DEFAULT_DPU_OUTPUT_LINE_WIDTH
81322. DEFAULT_DRUM_FLAGS
81323. DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT
81324. DEFAULT_DRXK_MPEG_LOCK_TIMEOUT
81325. DEFAULT_DUMP_EVENT_LOG_ENTRIES
81326. DEFAULT_DURATION_JIFFIES
81327. DEFAULT_D_MAX
81328. DEFAULT_ECSIPR_INIT
81329. DEFAULT_ECSR_INIT
81330. DEFAULT_EDCA
81331. DEFAULT_EESR_ERR_CHECK
81332. DEFAULT_EMPTY_SCAN_SIZE
81333. DEFAULT_ENABLE_ISOC
81334. DEFAULT_ENCODING
81335. DEFAULT_ENCODING_SA
81336. DEFAULT_ENCRYPT
81337. DEFAULT_EOT
81338. DEFAULT_EXPIRATION
81339. DEFAULT_F2_WATERMARK
81340. DEFAULT_FALSE
81341. DEFAULT_FANOUT
81342. DEFAULT_FAST_CHARGE_TIMER
81343. DEFAULT_FB_SIZE
81344. DEFAULT_FCPAUSE
81345. DEFAULT_FCRAMRATIO
81346. DEFAULT_FCRAM_REFRESH_MAX
81347. DEFAULT_FCRAM_REFRESH_MIN
81348. DEFAULT_FCRTH
81349. DEFAULT_FCRTL
81350. DEFAULT_FDR_INIT
81351. DEFAULT_FDT_VERSION
81352. DEFAULT_FETCH_TYPE
81353. DEFAULT_FETCH_TYPE_STR
81354. DEFAULT_FIFO_0_LEN
81355. DEFAULT_FIFO_1_7_LEN
81356. DEFAULT_FIFO_F_D_RFD
81357. DEFAULT_FIFO_F_D_RFF
81358. DEFAULT_FIFO_SIZE
81359. DEFAULT_FIFO_TX_STARVE
81360. DEFAULT_FIFO_TX_STARVE_OFF
81361. DEFAULT_FIFO_TX_THR
81362. DEFAULT_FILTER
81363. DEFAULT_FIPER1_PERIOD
81364. DEFAULT_FIPER2_PERIOD
81365. DEFAULT_FLOW_ID
81366. DEFAULT_FM_CTL1_DISP_TH
81367. DEFAULT_FM_CTL2_DISP_TH
81368. DEFAULT_FRAG_SIZE
81369. DEFAULT_FRAG_THRESHOLD
81370. DEFAULT_FRAME_LEN
81371. DEFAULT_FRAME_LENGTH
81372. DEFAULT_FRAME_RATE
81373. DEFAULT_FREQ
81374. DEFAULT_FREQUENCY
81375. DEFAULT_FR_THRES_8K
81376. DEFAULT_FS_BURST_CAP_SIZE
81377. DEFAULT_FS_OVERFLOWGID
81378. DEFAULT_FS_OVERFLOWUID
81379. DEFAULT_FTS
81380. DEFAULT_FUNC_FILTER
81381. DEFAULT_FW_8051_NAME_ASIC
81382. DEFAULT_FW_8051_NAME_FPGA
81383. DEFAULT_FW_FABRIC_NAME
81384. DEFAULT_FW_PCIE_NAME
81385. DEFAULT_FW_SBUS_NAME
81386. DEFAULT_GAIN
81387. DEFAULT_GAMMA
81388. DEFAULT_GC_LEB
81389. DEFAULT_GMAC_RXQ_ORDER
81390. DEFAULT_GMAC_TXQ_ORDER
81391. DEFAULT_GPIOTIMERVAL
81392. DEFAULT_GPIO_OFFTIME
81393. DEFAULT_GPIO_ONTIME
81394. DEFAULT_GPIO_RESET
81395. DEFAULT_GPIO_RESET_DELAY
81396. DEFAULT_GPIO_SET
81397. DEFAULT_GR_BURST_SIZE
81398. DEFAULT_GR_LWM
81399. DEFAULT_GUEST_KERNEL_ID
81400. DEFAULT_GUEST_PHY_PAGES
81401. DEFAULT_GUEST_STACK_VADDR_MIN
81402. DEFAULT_GUEST_TEST_MEM
81403. DEFAULT_HACTIVE_NTSC
81404. DEFAULT_HACTIVE_PAL
81405. DEFAULT_HALFDUP_COLL_WINDOW
81406. DEFAULT_HALFDUP_RETRANSMIT
81407. DEFAULT_HASH
81408. DEFAULT_HASH_DIST_FQID_SHIFT
81409. DEFAULT_HASH_KEY_EXTRACT_FIELDS
81410. DEFAULT_HASH_KEY_IPv4_ADDR
81411. DEFAULT_HASH_KEY_L4_PORT
81412. DEFAULT_HASH_SHA256_LEN
81413. DEFAULT_HASH_SHIFT
81414. DEFAULT_HASH_SIZE
81415. DEFAULT_HASH_TYPE
81416. DEFAULT_HDELAY_NTSC
81417. DEFAULT_HDELAY_PAL
81418. DEFAULT_HDLC_ADDR
81419. DEFAULT_HDLC_HEAD
81420. DEFAULT_HEADROOM
81421. DEFAULT_HEARTBEAT
81422. DEFAULT_HEIGHT
81423. DEFAULT_HMCS
81424. DEFAULT_HOLDD
81425. DEFAULT_HOPCOUNT
81426. DEFAULT_HOST_CLOCK
81427. DEFAULT_HOTPLUG_BUS_SIZE
81428. DEFAULT_HOTPLUG_IO_SIZE
81429. DEFAULT_HOTPLUG_MEM_SIZE
81430. DEFAULT_HS_BURST_CAP_SIZE
81431. DEFAULT_HT20_TXPWR_DIFF
81432. DEFAULT_HT_TYPE0_CFG_BASE
81433. DEFAULT_HT_TYPE1_CFG_BASE
81434. DEFAULT_HUE_NTSC
81435. DEFAULT_HW_GEN_MODULATION_TYPE
81436. DEFAULT_HW_GEN_TX_RATE
81437. DEFAULT_HYDRATION_BATCH_SIZE
81438. DEFAULT_HYDRATION_THRESHOLD
81439. DEFAULT_I2C_HW_SPEED
81440. DEFAULT_I2C_HW_SPEED_100KHZ
81441. DEFAULT_I2C_REG_CR
81442. DEFAULT_I2C_SCL
81443. DEFAULT_I2C_SDA
81444. DEFAULT_ICV_LEN
81445. DEFAULT_IDLE_PERIOD
81446. DEFAULT_IDLE_THRESHOLD
81447. DEFAULT_IDX_LEB
81448. DEFAULT_IMMR_VALUE
81449. DEFAULT_INITIATOR_ID
81450. DEFAULT_INLINE_XATTR_ADDRS
81451. DEFAULT_INPUT_CLOCK
81452. DEFAULT_INPUT_OVP_THRESHOLD
81453. DEFAULT_INTERLEAVE_SECTORS
81454. DEFAULT_INTERRUPTNUMBER
81455. DEFAULT_INTR
81456. DEFAULT_INT_MOD_CNT
81457. DEFAULT_IN_FMTIDX
81458. DEFAULT_IN_HEIGHT
81459. DEFAULT_IN_MAX
81460. DEFAULT_IN_VFMT
81461. DEFAULT_IN_WIDTH
81462. DEFAULT_IOBASEADDR
81463. DEFAULT_IOFENCE_MARGIN
81464. DEFAULT_IOFENCE_TICK
81465. DEFAULT_IO_BASE
81466. DEFAULT_IO_DELAY_TYPE
81467. DEFAULT_IO_ERROR_LIMIT
81468. DEFAULT_IO_OUTPUT_CTRL_MSK
81469. DEFAULT_IPG
81470. DEFAULT_IPG0
81471. DEFAULT_IPG1
81472. DEFAULT_IPG2
81473. DEFAULT_IRQS
81474. DEFAULT_ISOC_ALTSETTING
81475. DEFAULT_ITCT_HW
81476. DEFAULT_ITERATIONS
81477. DEFAULT_ITR
81478. DEFAULT_I_MAX
81479. DEFAULT_I_TDPS
81480. DEFAULT_JAMSIZE
81481. DEFAULT_JHEADS_CNT
81482. DEFAULT_JNL_PERCENT
81483. DEFAULT_JOURNAL_IOPRIO
81484. DEFAULT_JOURNAL_SIZE_FACTOR
81485. DEFAULT_JOURNAL_WATERMARK
81486. DEFAULT_JUMBO
81487. DEFAULT_KDETH_QP
81488. DEFAULT_KEYPAD_TYPE
81489. DEFAULT_KG_DISP_TH
81490. DEFAULT_KPREC
81491. DEFAULT_KRCVQS
81492. DEFAULT_LAT_THRESHOLD
81493. DEFAULT_LCDMODE
81494. DEFAULT_LCD_BWIDTH
81495. DEFAULT_LCD_CHARSET
81496. DEFAULT_LCD_HEIGHT
81497. DEFAULT_LCD_HWIDTH
81498. DEFAULT_LCD_PIN_BL
81499. DEFAULT_LCD_PIN_E
81500. DEFAULT_LCD_PIN_RS
81501. DEFAULT_LCD_PIN_RW
81502. DEFAULT_LCD_PIN_SCL
81503. DEFAULT_LCD_PIN_SDA
81504. DEFAULT_LCD_PROTO
81505. DEFAULT_LCD_TYPE
81506. DEFAULT_LCD_WIDTH
81507. DEFAULT_LCT_EXTEND
81508. DEFAULT_LCT_LONG
81509. DEFAULT_LCT_MEDIUM
81510. DEFAULT_LCT_SHORT
81511. DEFAULT_LC_EXTENDED
81512. DEFAULT_LC_LONG
81513. DEFAULT_LC_MEDIUM
81514. DEFAULT_LC_SHORT
81515. DEFAULT_LED_NAME
81516. DEFAULT_LEM_ALARM
81517. DEFAULT_LEM_CUTOFF
81518. DEFAULT_LFC_PTVVAL
81519. DEFAULT_LIMITER_DEV
81520. DEFAULT_LIMITER_RTIME
81521. DEFAULT_LINKDOWN_TIMEOUT
81522. DEFAULT_LINK_SPEED
81523. DEFAULT_LIST_FILTER
81524. DEFAULT_LOCK_TIMEOUT
81525. DEFAULT_LOG_DEBUG
81526. DEFAULT_LOG_INFO
81527. DEFAULT_LONG_RETRY_LIMIT
81528. DEFAULT_LOOP_COUNT
81529. DEFAULT_LPD
81530. DEFAULT_LR_CONTEXT_RENDER_SIZE
81531. DEFAULT_LSAVE_CNT
81532. DEFAULT_MAC_LEARN
81533. DEFAULT_MAIR_EL1
81534. DEFAULT_MAJOR_ROOT
81535. DEFAULT_MAPPING
81536. DEFAULT_MAP_BASE
81537. DEFAULT_MAP_BASE32
81538. DEFAULT_MAP_WINDOW
81539. DEFAULT_MAP_WINDOW_64
81540. DEFAULT_MAP_WINDOW_USER64
81541. DEFAULT_MARGIN
81542. DEFAULT_MAXIMUM_FRAME
81543. DEFAULT_MAX_ABS_MT_ORIENTATION
81544. DEFAULT_MAX_ABS_MT_PRESSURE
81545. DEFAULT_MAX_ABS_MT_TOUCH
81546. DEFAULT_MAX_ABS_MT_TRACKING_ID
81547. DEFAULT_MAX_BIT_RATE
81548. DEFAULT_MAX_FRAME_LENGTH
81549. DEFAULT_MAX_ITER
81550. DEFAULT_MAX_JNL
81551. DEFAULT_MAX_JOURNAL_SECTORS
81552. DEFAULT_MAX_MAP_COUNT
81553. DEFAULT_MAX_NUM_RSS_QUEUES
81554. DEFAULT_MAX_RCU_BLIMIT
81555. DEFAULT_MAX_RDMA_SIZE
81556. DEFAULT_MAX_REQ_SIZE
81557. DEFAULT_MAX_REQ_SIZE_1
81558. DEFAULT_MAX_REQ_SIZE_2
81559. DEFAULT_MAX_RP_SIZE
81560. DEFAULT_MAX_RSP_SIZE
81561. DEFAULT_MAX_SAMPLE_RATE
81562. DEFAULT_MAX_SCAN_AGE
81563. DEFAULT_MAX_SECTORS
81564. DEFAULT_MAX_TEMP
81565. DEFAULT_MB_HIGH_WATER
81566. DEFAULT_MB_HIGH_WATER_5705
81567. DEFAULT_MB_HIGH_WATER_57765
81568. DEFAULT_MB_HIGH_WATER_5906
81569. DEFAULT_MB_HIGH_WATER_JUMBO
81570. DEFAULT_MB_HIGH_WATER_JUMBO_57765
81571. DEFAULT_MB_HIGH_WATER_JUMBO_5780
81572. DEFAULT_MB_MACRX_LOW_WATER
81573. DEFAULT_MB_MACRX_LOW_WATER_5705
81574. DEFAULT_MB_MACRX_LOW_WATER_57765
81575. DEFAULT_MB_MACRX_LOW_WATER_5906
81576. DEFAULT_MB_MACRX_LOW_WATER_JUMBO
81577. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
81578. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
81579. DEFAULT_MB_RDMA_LOW_WATER
81580. DEFAULT_MB_RDMA_LOW_WATER_5705
81581. DEFAULT_MB_RDMA_LOW_WATER_JUMBO
81582. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
81583. DEFAULT_MCLK_RATE
81584. DEFAULT_MCP_PSET
81585. DEFAULT_MEMSIZE
81586. DEFAULT_MEM_BASE
81587. DEFAULT_MER_83
81588. DEFAULT_MER_93
81589. DEFAULT_MFD
81590. DEFAULT_MGN_LIFETIME
81591. DEFAULT_MGN_LIFETIME_RES_64us
81592. DEFAULT_MICD_TIMEOUT
81593. DEFAULT_MIDI_TYPE
81594. DEFAULT_MIGRATION_THRESHOLD
81595. DEFAULT_MINOR_ROOT
81596. DEFAULT_MIN_ABS_MT_TRACKING_ID
81597. DEFAULT_MIN_AVAIL_SIZE
81598. DEFAULT_MIN_IB_AVAIL_SIZE
81599. DEFAULT_MIN_IFG_ENFORCEMENT
81600. DEFAULT_MIN_SYNCHRONISATION_NS
81601. DEFAULT_MIN_SYSTEM_VOLT
81602. DEFAULT_MIRROR
81603. DEFAULT_MNT_OPTS
81604. DEFAULT_MODE
81605. DEFAULT_MODEDB_INDEX
81606. DEFAULT_MODEM_MODE
81607. DEFAULT_MODE_1360
81608. DEFAULT_MODE_848
81609. DEFAULT_MODE_856
81610. DEFAULT_MONITOR_DELAY
81611. DEFAULT_MPUI_CONFIG
81612. DEFAULT_MRU
81613. DEFAULT_MSDU_LIFETIME
81614. DEFAULT_MSDU_LIFETIME_RES_64us
81615. DEFAULT_MSG
81616. DEFAULT_MSG_ENABLE
81617. DEFAULT_MSG_LEVEL
81618. DEFAULT_MSG_SEVERITY
81619. DEFAULT_MTU
81620. DEFAULT_MTU_SIZE
81621. DEFAULT_MTYPE
81622. DEFAULT_MUTE
81623. DEFAULT_NAPI_WEIGHT
81624. DEFAULT_NAQP
81625. DEFAULT_NETLOGIC_IO_BASE
81626. DEFAULT_NEW_RSB_COUNT
81627. DEFAULT_NFILTERS
81628. DEFAULT_NGPIO
81629. DEFAULT_NODE
81630. DEFAULT_NON_BACK_TO_BACK_IPG1
81631. DEFAULT_NON_BACK_TO_BACK_IPG2
81632. DEFAULT_NOWAYOUT
81633. DEFAULT_NR_REG_BANKS
81634. DEFAULT_NSERVERS
81635. DEFAULT_NS_MAX
81636. DEFAULT_NUM_FWCHAIN_ELEMTS
81637. DEFAULT_NUM_IVECS
81638. DEFAULT_NUM_LANES
81639. DEFAULT_NUM_NIC_PORTS_23XX
81640. DEFAULT_NUM_NIC_PORTS_66XX
81641. DEFAULT_NUM_NIC_PORTS_68XX
81642. DEFAULT_NUM_NIC_PORTS_68XX_210NV
81643. DEFAULT_NUM_STATIONS
81644. DEFAULT_NUM_VF_ENABLED
81645. DEFAULT_NVM_FILE_FAMILY_8000C
81646. DEFAULT_N_BUFFERS
81647. DEFAULT_OFFSET
81648. DEFAULT_OSPATH
81649. DEFAULT_OUTSTANDING_COMMANDS
81650. DEFAULT_OUT_FMTIDX
81651. DEFAULT_OUT_HEIGHT
81652. DEFAULT_OUT_VFMT
81653. DEFAULT_OUT_WIDTH
81654. DEFAULT_OV
81655. DEFAULT_OVERFLOWGID
81656. DEFAULT_OVERFLOWUID
81657. DEFAULT_PADDING
81658. DEFAULT_PARPORT
81659. DEFAULT_PAUSE_QUANT
81660. DEFAULT_PAUSE_QUANTA
81661. DEFAULT_PAUSE_TIME
81662. DEFAULT_PCI_CONFIG_BASE
81663. DEFAULT_PDR
81664. DEFAULT_PERIOD
81665. DEFAULT_PERS
81666. DEFAULT_PHAD_QVGA
81667. DEFAULT_PHASE
81668. DEFAULT_PHY_DEV_ADDR
81669. DEFAULT_PID_FILE
81670. DEFAULT_PILOT_DEVIATION
81671. DEFAULT_PILOT_FREQUENCY
81672. DEFAULT_PING_RATE
81673. DEFAULT_PIN_NUMBER
81674. DEFAULT_PITCH
81675. DEFAULT_PITCH_OFFSET
81676. DEFAULT_PIXEL_RAM_SIZE
81677. DEFAULT_PKEY
81678. DEFAULT_PKTGEN_UDP_PORT
81679. DEFAULT_PLATFORM_CONFIG_NAME
81680. DEFAULT_PLCR_DISP_TH
81681. DEFAULT_PLLA_RATE
81682. DEFAULT_PMR_VALUE
81683. DEFAULT_POLL
81684. DEFAULT_POLLING_INTERVAL
81685. DEFAULT_POLLMASK
81686. DEFAULT_POLL_DELAY
81687. DEFAULT_POLL_PERIOD
81688. DEFAULT_PORT
81689. DEFAULT_PORT_IRQ_ENABLE_MASK
81690. DEFAULT_POWER_LEVEL
81691. DEFAULT_POWER_OFF_DELAY
81692. DEFAULT_POWER_STATE
81693. DEFAULT_POW_GRP
81694. DEFAULT_PPP_HEAD
81695. DEFAULT_PPR
81696. DEFAULT_PPS_CHANNEL
81697. DEFAULT_PRB_RETIRE_TOV
81698. DEFAULT_PREAMBLE_LEN
81699. DEFAULT_PREEMPHASIS
81700. DEFAULT_PRESSURE
81701. DEFAULT_PRETIMEOUT
81702. DEFAULT_PREVIEW_STILL_FRAMERATE
81703. DEFAULT_PREVIEW_STILL_HEIGHT
81704. DEFAULT_PREVIEW_STILL_WIDTH
81705. DEFAULT_PREVIEW_VIDEO_FRAMERATE
81706. DEFAULT_PREVIEW_VIDEO_HEIGHT
81707. DEFAULT_PREVIEW_VIDEO_WIDTH
81708. DEFAULT_PRE_TIME_OUT
81709. DEFAULT_PRI
81710. DEFAULT_PRIO
81711. DEFAULT_PRIORITY
81712. DEFAULT_PRIO_LVL
81713. DEFAULT_PRNG_KEY
81714. DEFAULT_PRNG_KSZ
81715. DEFAULT_PROC_FREQ
81716. DEFAULT_PROC_MAP_PARSE_TIMEOUT
81717. DEFAULT_PROFILE
81718. DEFAULT_PROTOCOL
81719. DEFAULT_PROT_CFG_20
81720. DEFAULT_PROT_CFG_40
81721. DEFAULT_PROT_CFG_CCK
81722. DEFAULT_PROT_CFG_OFDM
81723. DEFAULT_PRS_DISP_TH
81724. DEFAULT_PSR_VALUE
81725. DEFAULT_PTE_MASK
81726. DEFAULT_P_KEY
81727. DEFAULT_Q
81728. DEFAULT_Q0_INT_BIT
81729. DEFAULT_Q1_INT_BIT
81730. DEFAULT_QLEN
81731. DEFAULT_QMI_DEQ_DISP_TH
81732. DEFAULT_QMI_ENQ_DISP_TH
81733. DEFAULT_QUEUE_LENGTH
81734. DEFAULT_RADIO_SENSOR_OFFSET
81735. DEFAULT_RADV
81736. DEFAULT_RATE
81737. DEFAULT_RATELIMIT_BURST
81738. DEFAULT_RATELIMIT_INTERVAL
81739. DEFAULT_RBDR_CNT
81740. DEFAULT_RCU_BLIMIT
81741. DEFAULT_RCU_QHIMARK
81742. DEFAULT_RCU_QLOMARK
81743. DEFAULT_RCVHDRSIZE
81744. DEFAULT_RCVHDR_ENTSIZE
81745. DEFAULT_RCV_DESCRIPTORS_10G
81746. DEFAULT_RCV_DESCRIPTORS_1G
81747. DEFAULT_RCV_DESCRIPTORS_VF
81748. DEFAULT_RC_INTERVAL
81749. DEFAULT_RDS_DEVIATION
81750. DEFAULT_RDS_PI
81751. DEFAULT_RDS_PS_REPEAT_COUNT
81752. DEFAULT_RDS_PTY
81753. DEFAULT_RDTR
81754. DEFAULT_READY_WAIT_JIFFIES
81755. DEFAULT_REBOOT_MODE
81756. DEFAULT_RECOVER_CALLBACKS
81757. DEFAULT_RECOVER_TIMER
81758. DEFAULT_REFRESH
81759. DEFAULT_REFRESH_RATE
81760. DEFAULT_REGSIZE
81761. DEFAULT_REGSPACING
81762. DEFAULT_REPLY_QUEUE
81763. DEFAULT_RESET_DELAY_MS
81764. DEFAULT_RESET_ON_INIT
81765. DEFAULT_RETRY_DATA
81766. DEFAULT_RETRY_IO_COUNT
81767. DEFAULT_RETRY_QUOTA_FLUSH_COUNT
81768. DEFAULT_RETRY_RTS
81769. DEFAULT_RFTHR
81770. DEFAULT_RING_LEN
81771. DEFAULT_ROOT_DEV
81772. DEFAULT_ROOT_DEVICE
81773. DEFAULT_RPTR_BLOCK_SIZE
81774. DEFAULT_RP_PERCENT
81775. DEFAULT_RSBTBL_SIZE
81776. DEFAULT_RSSI
81777. DEFAULT_RSSI_OFFSET
81778. DEFAULT_RSS_CONTEXT_GROUP
81779. DEFAULT_RTC_INT_FREQ
81780. DEFAULT_RTC_SHIFT
81781. DEFAULT_RTS_THRESHOLD
81782. DEFAULT_RT_REGION_LEN
81783. DEFAULT_RUNTIME
81784. DEFAULT_RXC
81785. DEFAULT_RXCLK_SRC
81786. DEFAULT_RXCOAL_MAXF_INT
81787. DEFAULT_RXCOAL_TICK_INT
81788. DEFAULT_RXCOAL_TICK_INT_CLRTCKS
81789. DEFAULT_RXCOL_TICKS
81790. DEFAULT_RXCOUNT
81791. DEFAULT_RXD
81792. DEFAULT_RXIC
81793. DEFAULT_RXMAX_FRAMES
81794. DEFAULT_RXQ_PRIORITY
81795. DEFAULT_RXQ_TYPE
81796. DEFAULT_RXT
81797. DEFAULT_RXTIME
81798. DEFAULT_RX_BUF_COUNT
81799. DEFAULT_RX_BUF_ORDER
81800. DEFAULT_RX_CNTRL0
81801. DEFAULT_RX_COALESCE
81802. DEFAULT_RX_COALESCE_NSECS
81803. DEFAULT_RX_CSUM_ENABLE
81804. DEFAULT_RX_LFC_THR
81805. DEFAULT_RX_MULT
81806. DEFAULT_RX_PREPEND
81807. DEFAULT_RX_QUEUE_SIZE
81808. DEFAULT_RX_Q_PRIORITY
81809. DEFAULT_RX_RING_SIZE
81810. DEFAULT_SAK_LEN
81811. DEFAULT_SAMPLERATE
81812. DEFAULT_SAMPLE_PERIOD_NS
81813. DEFAULT_SAMPLE_RATE_48K
81814. DEFAULT_SAMPLE_TIME
81815. DEFAULT_SAMPLE_TOLERANCE
81816. DEFAULT_SAMPLE_WIDTH
81817. DEFAULT_SAMPLE_WINDOW
81818. DEFAULT_SATA_SPD_SEL
81819. DEFAULT_SATA_TXAMP
81820. DEFAULT_SATA_TXBOOST_GAIN
81821. DEFAULT_SATA_TXCN1
81822. DEFAULT_SATA_TXCN2
81823. DEFAULT_SATA_TXCP1
81824. DEFAULT_SATA_TXEYEDIRECTION
81825. DEFAULT_SATA_TXEYETUNING
81826. DEFAULT_SATURATION
81827. DEFAULT_SATURATION_RATIO
81828. DEFAULT_SAT_U_NTSC
81829. DEFAULT_SAT_V_NTSC
81830. DEFAULT_SCALE_COOKIE
81831. DEFAULT_SCALE_MODE
81832. DEFAULT_SCAN_SECS
81833. DEFAULT_SCLK_CSIS_FREQ
81834. DEFAULT_SCL_RATE
81835. DEFAULT_SCRATCH_BUF_SIZE
81836. DEFAULT_SC_BOTTOM_MAX
81837. DEFAULT_SC_BOTTOM_RIGHT
81838. DEFAULT_SC_RIGHT_MAX
81839. DEFAULT_SC_TOP_LEFT
81840. DEFAULT_SDIO_DRIVE_STRENGTH
81841. DEFAULT_SDP_CUR_MAX
81842. DEFAULT_SDP_CUR_MAX_SS
81843. DEFAULT_SDP_CUR_MIN
81844. DEFAULT_SDP_CUR_MIN_SS
81845. DEFAULT_SECS
81846. DEFAULT_SECTION_ALIGNMENT
81847. DEFAULT_SECTORS_PER_BITMAP_BIT
81848. DEFAULT_SEC_DESC_LEN
81849. DEFAULT_SEEKS
81850. DEFAULT_SEND_SCI
81851. DEFAULT_SENSOR_CLK_FREQ
81852. DEFAULT_SEPARATOR
81853. DEFAULT_SERIAL_PORT
81854. DEFAULT_SERVER_REGION_LEN
81855. DEFAULT_SE_GROUP
81856. DEFAULT_SGPIO_BITS
81857. DEFAULT_SHORT_RETRY_LIMIT
81858. DEFAULT_SH_MEM_BASES
81859. DEFAULT_SH_MEM_CONFIG
81860. DEFAULT_SINGLE
81861. DEFAULT_SLOPPY_SCTP
81862. DEFAULT_SLOPPY_TCP
81863. DEFAULT_SLOT
81864. DEFAULT_SLOT_TIME
81865. DEFAULT_SM750LE_CHIP_CLOCK
81866. DEFAULT_SM750_CHIP_CLOCK
81867. DEFAULT_SOFT_TO_HARD_MARGIN
81868. DEFAULT_SOURCE
81869. DEFAULT_SOURCE_HIGH
81870. DEFAULT_SOURCE_LOW
81871. DEFAULT_SOURCE_LOW_HIGH
81872. DEFAULT_SPEAKER_LOCATION
81873. DEFAULT_SPEED_MAX_DTR
81874. DEFAULT_SPIN_TIME
81875. DEFAULT_SPI_DMA_BUF_LEN
81876. DEFAULT_SPLIT_TIMEOUT
81877. DEFAULT_SRCU_EXP_HOLDOFF
81878. DEFAULT_SRC_CLK
81879. DEFAULT_SRPT_SRQ_SIZE
81880. DEFAULT_SSID
81881. DEFAULT_SSP_REG_CPSR
81882. DEFAULT_SSP_REG_CR0
81883. DEFAULT_SSP_REG_CR0_ST
81884. DEFAULT_SSP_REG_CR0_ST_PL023
81885. DEFAULT_SSP_REG_CR1
81886. DEFAULT_SSP_REG_CR1_ST
81887. DEFAULT_SSP_REG_CR1_ST_PL023
81888. DEFAULT_SSP_REG_DMACR
81889. DEFAULT_SSP_REG_IMSC
81890. DEFAULT_STACK
81891. DEFAULT_STACK_PGS
81892. DEFAULT_STATE
81893. DEFAULT_STAT_COAL_TICKS
81894. DEFAULT_SUB_JOB_SIZE_KB
81895. DEFAULT_SWBA_RESPONSE
81896. DEFAULT_SW_BUFFERING
81897. DEFAULT_SX_OFF
81898. DEFAULT_SX_PER
81899. DEFAULT_SYMBOL_WHITE_LIST
81900. DEFAULT_SYMMETRIC_HASH
81901. DEFAULT_SYNC_MSEC
81902. DEFAULT_SYNC_PERIOD
81903. DEFAULT_SYNC_REFRESH_PERIOD
81904. DEFAULT_SYNC_RETRIES
81905. DEFAULT_SYNC_THRESHOLD
81906. DEFAULT_SYNC_VER
81907. DEFAULT_SYS_FILTER_MESSAGE
81908. DEFAULT_TABLE
81909. DEFAULT_TADV
81910. DEFAULT_TARGET
81911. DEFAULT_TARGET_HIGH
81912. DEFAULT_TARGET_LOW
81913. DEFAULT_TARGET_LOW_HIGH
81914. DEFAULT_TASK_SIZE
81915. DEFAULT_TASK_SIZE32
81916. DEFAULT_TB_FREQ
81917. DEFAULT_TB_MAX
81918. DEFAULT_TB_MIN
81919. DEFAULT_TCAM_ACCESS_RATIO
81920. DEFAULT_TCAM_LATENCY
81921. DEFAULT_TCB
81922. DEFAULT_TCP_PORT
81923. DEFAULT_TCTL_EXT_GCEX_80003ES2LAN
81924. DEFAULT_TC_OFFSET
81925. DEFAULT_TC_WEIGHT
81926. DEFAULT_TD_MIN
81927. DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE
81928. DEFAULT_TEARCHECK_SYNC_THRESH_START
81929. DEFAULT_TEMP
81930. DEFAULT_TESTMODE
81931. DEFAULT_TEST_DONE
81932. DEFAULT_TEXT_SECTION_ALIGNMENT
81933. DEFAULT_THERMAL_GOVERNOR
81934. DEFAULT_THERMAL_REGULATION_TEMP
81935. DEFAULT_THREAD_COUNT
81936. DEFAULT_TIDV
81937. DEFAULT_TILE_MASK
81938. DEFAULT_TIME
81939. DEFAULT_TIMEOUT
81940. DEFAULT_TIMEOUT_INTERVAL
81941. DEFAULT_TIMEOUT_MS
81942. DEFAULT_TIMER
81943. DEFAULT_TIMER_EXPIRE
81944. DEFAULT_TIMER_LIMIT
81945. DEFAULT_TIMEWARN_CS
81946. DEFAULT_TIME_GRAN
81947. DEFAULT_TIPG_IPGT_1000_80003ES2LAN
81948. DEFAULT_TIPG_IPGT_10_100_80003ES2LAN
81949. DEFAULT_TL_MIN
81950. DEFAULT_TMR_PRSC
81951. DEFAULT_TOP_OFF_THRESHOLD_CURRENT
81952. DEFAULT_TOP_OFF_TIMER
81953. DEFAULT_TOSS_SECS
81954. DEFAULT_TOS_VALUE
81955. DEFAULT_TOTAL_TIME_OUT
81956. DEFAULT_TRACER
81957. DEFAULT_TRANSP_BURST_SZ
81958. DEFAULT_TRSCER_ERR_MASK
81959. DEFAULT_TRUE
81960. DEFAULT_TSO_CSUM_ENABLE
81961. DEFAULT_TTL
81962. DEFAULT_TUNE_RNL
81963. DEFAULT_TVMODE
81964. DEFAULT_TXC
81965. DEFAULT_TXCOAL_MAXF_INT
81966. DEFAULT_TXCOAL_TICK_INT
81967. DEFAULT_TXCOAL_TICK_INT_CLRTCKS
81968. DEFAULT_TXCOL_TICKS
81969. DEFAULT_TXCOUNT
81970. DEFAULT_TXD
81971. DEFAULT_TXIC
81972. DEFAULT_TXMAX_FRAMES
81973. DEFAULT_TXPOWER
81974. DEFAULT_TXTAIL
81975. DEFAULT_TXTIME
81976. DEFAULT_TX_BUF_COUNT
81977. DEFAULT_TX_CHECK
81978. DEFAULT_TX_CNTRL0
81979. DEFAULT_TX_COALESCE
81980. DEFAULT_TX_CSUM_ENABLE
81981. DEFAULT_TX_DRV_BRDCT
81982. DEFAULT_TX_DRV_IFIR
81983. DEFAULT_TX_DRV_IPRE_DRIVER
81984. DEFAULT_TX_DRV_POST2
81985. DEFAULT_TX_IPG_LENGTH
81986. DEFAULT_TX_MULT
81987. DEFAULT_TX_PAUSE_TIME
81988. DEFAULT_TX_PAUSE_TIME_EXTD
81989. DEFAULT_TX_QUEUE_LEN
81990. DEFAULT_TX_QUEUE_SIZE
81991. DEFAULT_TX_RATES
81992. DEFAULT_TX_RING_SIZE
81993. DEFAULT_T_ANNOUNCE
81994. DEFAULT_T_DIRECT
81995. DEFAULT_T_JAM
81996. DEFAULT_T_NEXT_9
81997. DEFAULT_T_NON_OP
81998. DEFAULT_T_OUT
81999. DEFAULT_T_STUCK
82000. DEFAULT_UARTCLK
82001. DEFAULT_UAR_PAGE_SHIFT
82002. DEFAULT_UBD
82003. DEFAULT_UCAST_PRIORITY
82004. DEFAULT_UCODE_DATASIZE
82005. DEFAULT_UCODE_TOTALSIZE
82006. DEFAULT_USER_STACK_SIZE
82007. DEFAULT_VACTIVE_NTSC
82008. DEFAULT_VACTIVE_PAL
82009. DEFAULT_VAR_FILTER
82010. DEFAULT_VCO
82011. DEFAULT_VCPU_NUM
82012. DEFAULT_VDELAY_NTSC
82013. DEFAULT_VDELAY_PAL
82014. DEFAULT_VECTOR_SIZE
82015. DEFAULT_VERBOSE_PROBING
82016. DEFAULT_VERSION
82017. DEFAULT_VHT_MCS_SET
82018. DEFAULT_VIDEO_MODE
82019. DEFAULT_VID_BURST_SIZE
82020. DEFAULT_VID_LWM
82021. DEFAULT_VLAN_FILTER_ENABLE
82022. DEFAULT_VLAN_ID
82023. DEFAULT_VLAN_RX_OFFLOAD
82024. DEFAULT_VOL
82025. DEFAULT_V_SEED
82026. DEFAULT_WAITWARN_US
82027. DEFAULT_WIDTH
82028. DEFAULT_WIN
82029. DEFAULT_WINDOW_INDEX
82030. DEFAULT_WRRS_WEIGHT
82031. DEFAULT_XRES
82032. DEFAULT_XY_MAX
82033. DEFAULT_YRES
82034. DEFAULT_ZERO
82035. DEFAULT_ZIO_THRESHOLD
82036. DEFBOOL
82037. DEFCHANNELS
82038. DEFCONTEXT_MNT
82039. DEFCONTEXT_STR
82040. DEFEA_PRODUCT_ID
82041. DEFEA_PROD_ID_1
82042. DEFEA_PROD_ID_2
82043. DEFEA_PROD_ID_3
82044. DEFEA_PROD_ID_4
82045. DEFECHO
82046. DEFECT7374_FSM_FIELD
82047. DEFECT7374_FSM_NON_SS_CONTROL_READ
82048. DEFECT7374_FSM_SS_CONTROL_READ
82049. DEFECT7374_FSM_WAITING_FOR_CONTROL_READ
82050. DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS
82051. DEFECT_7374_PROCESSOR_WAIT_TIME
82052. DEFEN
82053. DEFENSE_TIMER_PERIOD
82054. DEFENUM
82055. DEFER
82056. DEFERD
82057. DEFERRED_ACTION_FIFO_SIZE
82058. DEFERRED_DEVICE_TIMEOUT
82059. DEFERRED_ERROR_VECTOR
82060. DEFERRED_FIQ_IH_BASE
82061. DEFERRED_FIQ_MASK
82062. DEFERRED_SET_SIZE
82063. DEFERRED_SKB_CB
82064. DEFER_COUNT
82065. DEFER_CTRL_EN
82066. DEFER_DEVICE_DOMAIN_INFO
82067. DEFER_ERATT
82068. DEFER_TIME
82069. DEFER_WARN_INTERVAL
82070. DEFINE
82071. DEFINED_NUM_TO_STR
82072. DEFINE_2_MUXREG
82073. DEFINE_ACPI_GLOBALS
82074. DEFINE_ADCxx1C_CHANNELS
82075. DEFINE_AGF_EVENT
82076. DEFINE_AGINODE_EVENT
82077. DEFINE_AG_BTREE_LOOKUP_EVENT
82078. DEFINE_AG_CORRUPT_EVENT
82079. DEFINE_AG_ERROR_EVENT
82080. DEFINE_AG_EVENT
82081. DEFINE_AG_EXTENT_EVENT
82082. DEFINE_AG_RESV_EVENT
82083. DEFINE_AIL_EVENT
82084. DEFINE_ALE_FIELD
82085. DEFINE_ALE_FIELD1
82086. DEFINE_ALLOC_EVENT
82087. DEFINE_AML_GLOBALS
82088. DEFINE_ASAN_LOAD_STORE
82089. DEFINE_ASAN_REPORT_LOAD
82090. DEFINE_ASAN_REPORT_STORE
82091. DEFINE_ASAN_SET_SHADOW
82092. DEFINE_ATTR_EVENT
82093. DEFINE_ATTR_LIST_EVENT
82094. DEFINE_AUDIT_DATA
82095. DEFINE_AUDIT_NET
82096. DEFINE_AUDIT_SK
82097. DEFINE_BADREQ_EVENT
82098. DEFINE_BASIC_PRINT_TYPE_FUNC
82099. DEFINE_BINDER_FUNCTION_RETURN_EVENT
82100. DEFINE_BINDER_LOCK_EVENT
82101. DEFINE_BITOP
82102. DEFINE_BIT_SWITCH_ARG
82103. DEFINE_BMAP_DEFERRED_EVENT
82104. DEFINE_BMAP_EVENT
82105. DEFINE_BMAP_FREE_DEFERRED_EVENT
82106. DEFINE_BPF_PROG_RUN
82107. DEFINE_BPF_PROG_RUN_ARGS
82108. DEFINE_BTREE_CUR_EVENT
82109. DEFINE_BTRFS_LOCK_EVENT
82110. DEFINE_BTRFS_SETGET_BITS
82111. DEFINE_BUF_EVENT
82112. DEFINE_BUF_FLAGS_EVENT
82113. DEFINE_BUF_ITEM_EVENT
82114. DEFINE_BUNDLE_EVENT
82115. DEFINE_BUSY_EVENT
82116. DEFINE_CARD_SWITCH
82117. DEFINE_CB_EVENT
82118. DEFINE_CEPH_FEATURE
82119. DEFINE_CEPH_FEATURE_DEPRECATED
82120. DEFINE_CEPH_FEATURE_RETIRED
82121. DEFINE_CGROUP_MGCTX
82122. DEFINE_CHUNK_EVENT
82123. DEFINE_CLK
82124. DEFINE_CLK_RPM
82125. DEFINE_CLK_RPMH_ARC
82126. DEFINE_CLK_RPMH_BCM
82127. DEFINE_CLK_RPMH_VRM
82128. DEFINE_CLK_RPM_CXO_BRANCH
82129. DEFINE_CLK_RPM_FIXED
82130. DEFINE_CLK_RPM_PXO_BRANCH
82131. DEFINE_CLK_RPM_XO_BUFFER
82132. DEFINE_CLK_SMD_RPM
82133. DEFINE_CLK_SMD_RPM_BRANCH
82134. DEFINE_CLK_SMD_RPM_QDSS
82135. DEFINE_CLK_SMD_RPM_XO_BUFFER
82136. DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL
82137. DEFINE_CLK_STUB
82138. DEFINE_COMPARISON_PRED
82139. DEFINE_CONNECTION_EVENT
82140. DEFINE_CONTROLLER
82141. DEFINE_CONV
82142. DEFINE_CORESIGHT_DEVLIST
82143. DEFINE_CRC32_VX
82144. DEFINE_CSTATE_FORMAT_ATTR
82145. DEFINE_CTL_TABLE_POLL
82146. DEFINE_DA_EVENT
82147. DEFINE_DEBUGFS_ATTRIBUTE
82148. DEFINE_DEFAULT_PDR
82149. DEFINE_DEFER_ERROR_EVENT
82150. DEFINE_DEFER_EVENT
82151. DEFINE_DEFER_PENDING_EVENT
82152. DEFINE_DELAYED_CALL
82153. DEFINE_DIR2_EVENT
82154. DEFINE_DIR2_SPACE_EVENT
82155. DEFINE_DISCARD_EVENT
82156. DEFINE_DMA_BUF_EXPORT_INFO
82157. DEFINE_DMA_UNMAP_ADDR
82158. DEFINE_DMA_UNMAP_LEN
82159. DEFINE_DMI_ATTR_WITH_SHOW
82160. DEFINE_DOUBLE_IO_EVENT
82161. DEFINE_DPU_DEBUGFS_SEQ_FOPS
82162. DEFINE_DQUOT_EVENT
82163. DEFINE_DRM_GEM_CMA_FOPS
82164. DEFINE_DRM_GEM_FOPS
82165. DEFINE_DRM_GEM_SHMEM_FOPS
82166. DEFINE_DUMP_MESSAGE_EVENT
82167. DEFINE_DWARF_REGSTR_TABLE
82168. DEFINE_DYNAMIC_DEBUG_METADATA
82169. DEFINE_EARLY_LSM
82170. DEFINE_EARLY_PER_CPU
82171. DEFINE_EARLY_PER_CPU_READ_MOSTLY
82172. DEFINE_ENTRY
82173. DEFINE_EQUALITY_PRED
82174. DEFINE_ERROR_EVENT
82175. DEFINE_EVENT
82176. DEFINE_EVENT_CONDITION
82177. DEFINE_EVENT_FN
82178. DEFINE_EVENT_NOP
82179. DEFINE_EVENT_PRINT
82180. DEFINE_EVENT_SCHEDSTAT
82181. DEFINE_EVENT_WRITABLE
82182. DEFINE_FIELD
82183. DEFINE_FILESTREAM_EVENT
82184. DEFINE_FIND_HELPER
82185. DEFINE_FIXED_SYMBOL
82186. DEFINE_FLAG
82187. DEFINE_FREE_PT_FN
82188. DEFINE_FRWR_DONE_EVENT
82189. DEFINE_FSMAP_EVENT
82190. DEFINE_FSM_EVENT
82191. DEFINE_FS_CORRUPT_EVENT
82192. DEFINE_GENRADIX
82193. DEFINE_GETFSMAP_EVENT
82194. DEFINE_GSSAPI_EVENT
82195. DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO
82196. DEFINE_HANDLER
82197. DEFINE_HASHTABLE
82198. DEFINE_HD_EVENT
82199. DEFINE_HIST_FIELD_FN
82200. DEFINE_HWASAN_LOAD_STORE
82201. DEFINE_HWx_IRQDISPATCH
82202. DEFINE_IDA
82203. DEFINE_IDR
82204. DEFINE_IMAGE_LE64
82205. DEFINE_IMAGE_OPS
82206. DEFINE_IMAP_EVENT
82207. DEFINE_INFO_ATTRIBUTE
82208. DEFINE_INODE_CORRUPT_EVENT
82209. DEFINE_INODE_ERROR_EVENT
82210. DEFINE_INODE_EVENT
82211. DEFINE_INODE_IREC_EVENT
82212. DEFINE_INSN_CACHE_OPS
82213. DEFINE_INTERFACE_EVENT
82214. DEFINE_IPACK_DEVICE_TABLE
82215. DEFINE_IPL_ATTR_RO
82216. DEFINE_IPL_ATTR_RW
82217. DEFINE_IPL_ATTR_STR_RW
82218. DEFINE_IPL_CCW_ATTR_RW
82219. DEFINE_IREF_EVENT
82220. DEFINE_IRQ_VECTOR_ACTIVATE_EVENT
82221. DEFINE_IRQ_VECTOR_EVENT
82222. DEFINE_IRQ_VECTOR_MOD_EVENT
82223. DEFINE_IRQ_VECTOR_RESERVE_EVENT
82224. DEFINE_IRQ_WORK
82225. DEFINE_ITRUNC_EVENT
82226. DEFINE_KEY_COMBINATION_ENTRY
82227. DEFINE_KFIFO
82228. DEFINE_KLIST
82229. DEFINE_KMEM_EVENT
82230. DEFINE_KTHREAD_DELAYED_WORK
82231. DEFINE_KTHREAD_WORK
82232. DEFINE_KTHREAD_WORKER
82233. DEFINE_KTHREAD_WORKER_ONSTACK
82234. DEFINE_LED_TRIGGER
82235. DEFINE_LED_TRIGGER_GLOBAL
82236. DEFINE_LINK_EVENT
82237. DEFINE_LINK_EVENT_COND
82238. DEFINE_LIST_EVENT
82239. DEFINE_LOCK_EVENT
82240. DEFINE_LOGGRANT_EVENT
82241. DEFINE_LOG_ITEM_EVENT
82242. DEFINE_LOG_RECOVER_BUF_ITEM
82243. DEFINE_LOG_RECOVER_ICREATE_ITEM
82244. DEFINE_LOG_RECOVER_INO_ITEM
82245. DEFINE_LOG_RECOVER_ITEM
82246. DEFINE_LONGS
82247. DEFINE_LSM
82248. DEFINE_MAP_EXTENT_DEFERRED_EVENT
82249. DEFINE_MATCH_WB
82250. DEFINE_MESSAGE_EVENT
82251. DEFINE_MIXER_SWITCH
82252. DEFINE_MIX_REG_INFO
82253. DEFINE_MODULE_EVENT
82254. DEFINE_MONO
82255. DEFINE_MRS_S
82256. DEFINE_MR_EVENT
82257. DEFINE_MSR_S
82258. DEFINE_MUTEX
82259. DEFINE_MUXREG
82260. DEFINE_NAMESPACE_EVENT
82261. DEFINE_NFS4_CLIENTID_EVENT
82262. DEFINE_NFS4_COMMIT_EVENT
82263. DEFINE_NFS4_GETATTR_EVENT
82264. DEFINE_NFS4_IDMAP_EVENT
82265. DEFINE_NFS4_INODE_CALLBACK_EVENT
82266. DEFINE_NFS4_INODE_EVENT
82267. DEFINE_NFS4_INODE_STATEID_CALLBACK_EVENT
82268. DEFINE_NFS4_INODE_STATEID_EVENT
82269. DEFINE_NFS4_LOCK_EVENT
82270. DEFINE_NFS4_LOOKUP_EVENT
82271. DEFINE_NFS4_OPEN_EVENT
82272. DEFINE_NFS4_READ_EVENT
82273. DEFINE_NFS4_SET_DELEGATION_EVENT
82274. DEFINE_NFS4_TEST_STATEID_EVENT
82275. DEFINE_NFS4_WRITE_EVENT
82276. DEFINE_NFSD_ERR_EVENT
82277. DEFINE_NFSD_FILE_EVENT
82278. DEFINE_NFSD_FILE_SEARCH_EVENT
82279. DEFINE_NFSD_IO_EVENT
82280. DEFINE_NFS_DIRECTORY_EVENT
82281. DEFINE_NFS_DIRECTORY_EVENT_DONE
82282. DEFINE_NFS_INODE_EVENT
82283. DEFINE_NFS_INODE_EVENT_DONE
82284. DEFINE_NFS_LOOKUP_EVENT
82285. DEFINE_NFS_LOOKUP_EVENT_DONE
82286. DEFINE_NFS_RENAME_EVENT
82287. DEFINE_NFS_RENAME_EVENT_DONE
82288. DEFINE_NODE_EVENT
82289. DEFINE_NVOL_BIT_OPS
82290. DEFINE_OCFS2_BTREE_EVENT
82291. DEFINE_OCFS2_DENTRY_OPS
82292. DEFINE_OCFS2_FILE_OPS
82293. DEFINE_OCFS2_GET_BLOCK_EVENT
82294. DEFINE_OCFS2_INT_EVENT
82295. DEFINE_OCFS2_INT_INT_EVENT
82296. DEFINE_OCFS2_POINTER_EVENT
82297. DEFINE_OCFS2_REFCOUNT_TREE_OPS_EVENT
82298. DEFINE_OCFS2_STRING_EVENT
82299. DEFINE_OCFS2_TRUNCATE_LOG_OPS_EVENT
82300. DEFINE_OCFS2_UINT_EVENT
82301. DEFINE_OCFS2_UINT_INT_EVENT
82302. DEFINE_OCFS2_UINT_UINT_EVENT
82303. DEFINE_OCFS2_UINT_UINT_UINT_EVENT
82304. DEFINE_OCFS2_ULL_EVENT
82305. DEFINE_OCFS2_ULL_INT_EVENT
82306. DEFINE_OCFS2_ULL_INT_INT_INT_EVENT
82307. DEFINE_OCFS2_ULL_UINT_EVENT
82308. DEFINE_OCFS2_ULL_UINT_UINT_EVENT
82309. DEFINE_OCFS2_ULL_UINT_UINT_UINT_EVENT
82310. DEFINE_OCFS2_ULL_ULL_EVENT
82311. DEFINE_OCFS2_ULL_ULL_UINT_EVENT
82312. DEFINE_OCFS2_ULL_ULL_UINT_UINT_EVENT
82313. DEFINE_OCFS2_ULL_ULL_ULL_EVENT
82314. DEFINE_OCFS2_XATTR_FIND_EVENT
82315. DEFINE_OPERATION_EVENT
82316. DEFINE_OUTPUT_COPY
82317. DEFINE_PAGE_EVENT
82318. DEFINE_PAGE_FAULT_EVENT
82319. DEFINE_PARSE_ID_MODE
82320. DEFINE_PARTS
82321. DEFINE_PCI_CONFIG
82322. DEFINE_PCM_GROUP_LOCK
82323. DEFINE_PERAG_REF_EVENT
82324. DEFINE_PERCPU_RWSEM
82325. DEFINE_PER_CPU
82326. DEFINE_PER_CPU_ALIGNED
82327. DEFINE_PER_CPU_DECRYPTED
82328. DEFINE_PER_CPU_FIRST
82329. DEFINE_PER_CPU_PAGE_ALIGNED
82330. DEFINE_PER_CPU_READ_MOSTLY
82331. DEFINE_PER_CPU_SECTION
82332. DEFINE_PER_CPU_SHARED_ALIGNED
82333. DEFINE_PHYS_EXTENT_DEFERRED_EVENT
82334. DEFINE_PMD_FAULT_EVENT
82335. DEFINE_PMD_INSERT_MAPPING_EVENT
82336. DEFINE_PMD_LOAD_HOLE_EVENT
82337. DEFINE_PNFS_LAYOUT_EVENT
82338. DEFINE_POPULATE
82339. DEFINE_PPGTT_GMA_TO_INDEX
82340. DEFINE_PTE_FAULT_EVENT
82341. DEFINE_QBCM
82342. DEFINE_QNODE
82343. DEFINE_QUIRK_ATTRIBUTE
82344. DEFINE_RAID_ATTRIBUTE
82345. DEFINE_RAPL_FORMAT_ATTR
82346. DEFINE_RATELIMIT_STATE
82347. DEFINE_RAW_SPINLOCK
82348. DEFINE_RB_FUNCS
82349. DEFINE_RB_FUNCS2
82350. DEFINE_RB_INSDEL_FUNCS
82351. DEFINE_RB_INSDEL_FUNCS2
82352. DEFINE_RB_LOOKUP_FUNC
82353. DEFINE_RB_LOOKUP_FUNC2
82354. DEFINE_RCG_DFS
82355. DEFINE_RCU_SYNC
82356. DEFINE_RDCH_EVENT
82357. DEFINE_READPAGE_EVENT
82358. DEFINE_READ_MOSTLY_HASHTABLE
82359. DEFINE_REFCOUNT_DEFERRED_EVENT
82360. DEFINE_REFCOUNT_DOUBLE_EXTENT_AT_EVENT
82361. DEFINE_REFCOUNT_DOUBLE_EXTENT_EVENT
82362. DEFINE_REFCOUNT_EXTENT_AT_EVENT
82363. DEFINE_REFCOUNT_EXTENT_EVENT
82364. DEFINE_REFCOUNT_TRIPLE_EXTENT_EVENT
82365. DEFINE_REG
82366. DEFINE_REGSET
82367. DEFINE_REPAIR_EXTENT_EVENT
82368. DEFINE_REPAIR_RMAP_EVENT
82369. DEFINE_REPLY_EVENT
82370. DEFINE_RESCHED_IPI_EVENT
82371. DEFINE_RESORT_RB
82372. DEFINE_RES_DMA
82373. DEFINE_RES_DMA_NAMED
82374. DEFINE_RES_IO
82375. DEFINE_RES_IO_NAMED
82376. DEFINE_RES_IRQ
82377. DEFINE_RES_IRQ_NAMED
82378. DEFINE_RES_MEM
82379. DEFINE_RES_MEM_NAMED
82380. DEFINE_RES_NAMED
82381. DEFINE_RING_TYPES
82382. DEFINE_RMAPBT_EVENT
82383. DEFINE_RMAP_DEFERRED_EVENT
82384. DEFINE_RMAP_EVENT
82385. DEFINE_RPC_FAILURE
82386. DEFINE_RPC_QUEUED_EVENT
82387. DEFINE_RPC_REPLY_EVENT
82388. DEFINE_RPC_RUNNING_EVENT
82389. DEFINE_RPC_SOCKET_EVENT
82390. DEFINE_RPC_SOCKET_EVENT_DONE
82391. DEFINE_RPC_STATUS_EVENT
82392. DEFINE_RPC_XPRT_EVENT
82393. DEFINE_RPMH_MSG_ONSTACK
82394. DEFINE_RPMPD_CORNER
82395. DEFINE_RPMPD_LEVEL
82396. DEFINE_RPMPD_PAIR
82397. DEFINE_RPMPD_VFC
82398. DEFINE_RPMPD_VFL
82399. DEFINE_RT_MUTEX
82400. DEFINE_RWLOCK
82401. DEFINE_RW_EVENT
82402. DEFINE_RXPRT_EVENT
82403. DEFINE_SBQ_WAIT
82404. DEFINE_SCALAR_TEST
82405. DEFINE_SCALAR_TESTS
82406. DEFINE_SCRUB_BLOCK_ERROR_EVENT
82407. DEFINE_SCRUB_EVENT
82408. DEFINE_SCRUB_FBLOCK_ERROR_EVENT
82409. DEFINE_SCRUB_INO_ERROR_EVENT
82410. DEFINE_SCRUB_SBTREE_EVENT
82411. DEFINE_SEGMENT_EVENT
82412. DEFINE_SEMAPHORE
82413. DEFINE_SENDCOMP_EVENT
82414. DEFINE_SEQLOCK
82415. DEFINE_SHOW_ATTRIBUTE
82416. DEFINE_SIMPLE_ATTRIBUTE
82417. DEFINE_SIMPLE_IO_EVENT
82418. DEFINE_SINGLE_BUF_MAP
82419. DEFINE_SKB_EVENT
82420. DEFINE_SK_EVENT_FILTER
82421. DEFINE_SK_EVENT_FILTER_COND
82422. DEFINE_SLIM_BCAST_TXN
82423. DEFINE_SLIM_EDEST_TXN
82424. DEFINE_SLIM_LDEST_TXN
82425. DEFINE_SMB3_CMD_DONE_EVENT
82426. DEFINE_SMB3_CMD_ERR_EVENT
82427. DEFINE_SMB3_CREDIT_EVENT
82428. DEFINE_SMB3_ENTER_EXIT_EVENT
82429. DEFINE_SMB3_EXIT_ERR_EVENT
82430. DEFINE_SMB3_FD_ERR_EVENT
82431. DEFINE_SMB3_FD_EVENT
82432. DEFINE_SMB3_INF_COMPOUND_DONE_EVENT
82433. DEFINE_SMB3_INF_COMPOUND_ENTER_EVENT
82434. DEFINE_SMB3_INF_COMPOUND_ERR_EVENT
82435. DEFINE_SMB3_INF_ENTER_EVENT
82436. DEFINE_SMB3_INF_ERR_EVENT
82437. DEFINE_SMB3_LEASE_DONE_EVENT
82438. DEFINE_SMB3_LEASE_ERR_EVENT
82439. DEFINE_SMB3_MID_EVENT
82440. DEFINE_SMB3_OPEN_DONE_EVENT
82441. DEFINE_SMB3_OPEN_ENTER_EVENT
82442. DEFINE_SMB3_OPEN_ERR_EVENT
82443. DEFINE_SMB3_RECONNECT_EVENT
82444. DEFINE_SMB3_RW_DONE_EVENT
82445. DEFINE_SMB3_RW_ERR_EVENT
82446. DEFINE_SMB3_TCON_EVENT
82447. DEFINE_SMP_CALL_CACHE_FUNCTION
82448. DEFINE_SNAPPER_MIX
82449. DEFINE_SNAPPER_MONO
82450. DEFINE_SNMP_STAT
82451. DEFINE_SNMP_STAT_ATOMIC
82452. DEFINE_SPECIAL_CHARACTER
82453. DEFINE_SPINLOCK
82454. DEFINE_SPMI_SET_POINTS
82455. DEFINE_SPUFS_ATTRIBUTE
82456. DEFINE_SPUFS_SIMPLE_ATTRIBUTE
82457. DEFINE_SQ_EVENT
82458. DEFINE_SRCU
82459. DEFINE_STAT
82460. DEFINE_STATEID_EVENT
82461. DEFINE_STATIC_KEY_ARRAY_FALSE
82462. DEFINE_STATIC_KEY_ARRAY_TRUE
82463. DEFINE_STATIC_KEY_DEFERRED_FALSE
82464. DEFINE_STATIC_KEY_DEFERRED_TRUE
82465. DEFINE_STATIC_KEY_FALSE
82466. DEFINE_STATIC_KEY_FALSE_RO
82467. DEFINE_STATIC_KEY_TRUE
82468. DEFINE_STATIC_KEY_TRUE_RO
82469. DEFINE_STATIC_PERCPU_RWSEM
82470. DEFINE_STATIC_SRCU
82471. DEFINE_STATUS_SCREEN_DISPLAY
82472. DEFINE_STRARRAY
82473. DEFINE_STRARRAYS
82474. DEFINE_STRARRAY_OFFSET
82475. DEFINE_STRING_TABLE_ENTRY
82476. DEFINE_STRUCT_TEST
82477. DEFINE_STRUCT_TESTS
82478. DEFINE_SVC_DEFERRED_EVENT
82479. DEFINE_SVC_RQST_EVENT
82480. DEFINE_SWAPEXT_EVENT
82481. DEFINE_SWITCH
82482. DEFINE_SWITCH_ARG
82483. DEFINE_TALLY
82484. DEFINE_TEST
82485. DEFINE_TESTOP
82486. DEFINE_TEST_ALLOC
82487. DEFINE_TEST_ARRAY
82488. DEFINE_TEST_DRIVER
82489. DEFINE_TEST_FAIL
82490. DEFINE_TEST_FUNC
82491. DEFINE_TEST_OK
82492. DEFINE_TIMER
82493. DEFINE_TORTURE_RANDOM
82494. DEFINE_TORTURE_RANDOM_PERCPU
82495. DEFINE_TRACE
82496. DEFINE_TRACE_FN
82497. DEFINE_TRACING_MAP_CMP_FN
82498. DEFINE_TRANS_EVENT
82499. DEFINE_TRIGGER
82500. DEFINE_TYPE
82501. DEFINE_UNCORE_FORMAT_ATTR
82502. DEFINE_USNIC_VNIC_RES
82503. DEFINE_USNIC_VNIC_RES_AT
82504. DEFINE_V4L_STUB_FUNC
82505. DEFINE_VEC
82506. DEFINE_VIA_REGSET
82507. DEFINE_VVAR
82508. DEFINE_WAIT
82509. DEFINE_WAIT_BIT
82510. DEFINE_WAIT_FUNC
82511. DEFINE_WAKE_Q
82512. DEFINE_WBC_EVENT
82513. DEFINE_WB_COMPLETION
82514. DEFINE_WD_CLASS
82515. DEFINE_WINDOW_IO
82516. DEFINE_WRCH_EVENT
82517. DEFINE_WRITEBACK_EVENT
82518. DEFINE_WRITEBACK_RANGE_EVENT
82519. DEFINE_WRITEBACK_WORK_EVENT
82520. DEFINE_WW_CLASS
82521. DEFINE_WW_MUTEX
82522. DEFINE_XARRAY
82523. DEFINE_XARRAY_ALLOC
82524. DEFINE_XARRAY_ALLOC1
82525. DEFINE_XARRAY_FLAGS
82526. DEFINE_XEN_FLEX_RING
82527. DEFINE_XEN_FLEX_RING_AND_INTF
82528. DEFINE_XEN_MC_BATCH
82529. DEFINE_XEN_MMU_PGD_EVENT
82530. DEFINE_XEN_MMU_PTEP_MODIFY_PROT
82531. DEFINE_XEN_MMU_SET_PTE
82532. DEFINE_XPRT_EVENT
82533. DEFINE_XSK_RING
82534. DEFINE_ZYNQ_PINCTRL_GRP
82535. DEFINE_ZYNQ_PINMUX_FUNCTION
82536. DEFINE_ZYNQ_PINMUX_FUNCTION_MUX
82537. DEFINT
82538. DEFLATED
82539. DEFLATE_CHK_SEQUENCE
82540. DEFLATE_DEF_LEVEL
82541. DEFLATE_DEF_MEMLEVEL
82542. DEFLATE_DEF_WINBITS
82543. DEFLATE_MAKE_OPT
82544. DEFLATE_MAX_SIZE
82545. DEFLATE_METHOD
82546. DEFLATE_METHOD_VAL
82547. DEFLATE_MIN_SIZE
82548. DEFLATE_OVHD
82549. DEFLATE_SIZE
82550. DEFMASK
82551. DEFMODE_AGA
82552. DEFMODE_AMBER_NTSC
82553. DEFMODE_AMBER_PAL
82554. DEFMODE_EXT
82555. DEFMODE_F30
82556. DEFMODE_NTSC
82557. DEFMODE_PAL
82558. DEFMODE_STE
82559. DEFMODE_TT
82560. DEFMODE_VGA
82561. DEFPINFUNCGRP
82562. DEFR
82563. DEFR10
82564. DEFR10_CODE
82565. DEFR10_DEFE10
82566. DEFR10_DOCF0_RGB
82567. DEFR10_DOCF0_YC
82568. DEFR10_DOCF1_RGB
82569. DEFR10_DOCF1_YC
82570. DEFR10_TSEL_H3_TCON1
82571. DEFR10_VSPF0_RGB
82572. DEFR10_VSPF0_YC
82573. DEFR10_VSPF1_RGB
82574. DEFR10_VSPF1_YC
82575. DEFR10_YCDF0_YCBCR422
82576. DEFR10_YCDF0_YCBCR444
82577. DEFR2
82578. DEFR2_CODE
82579. DEFR2_DEFE2G
82580. DEFR3
82581. DEFR3_CODE
82582. DEFR3_DEFE3
82583. DEFR3_EVDA
82584. DEFR3_EVDM_1
82585. DEFR3_EVDM_2
82586. DEFR3_EVDM_3
82587. DEFR3_VMSM1_ENA
82588. DEFR3_VMSM2_EMA
82589. DEFR4
82590. DEFR4_CODE
82591. DEFR4_LRUO
82592. DEFR4_SPCE
82593. DEFR5
82594. DEFR5_CODE
82595. DEFR5_DEFE5
82596. DEFR5_YCRGB1_DIS
82597. DEFR5_YCRGB1_MASK
82598. DEFR5_YCRGB1_PRI1
82599. DEFR5_YCRGB1_PRI2
82600. DEFR5_YCRGB1_PRI3
82601. DEFR5_YCRGB2_DIS
82602. DEFR5_YCRGB2_MASK
82603. DEFR5_YCRGB2_PRI1
82604. DEFR5_YCRGB2_PRI2
82605. DEFR5_YCRGB2_PRI3
82606. DEFR6
82607. DEFR6_CODE
82608. DEFR6_DEFAULT
82609. DEFR6_MLOS1
82610. DEFR6_ODPM02_CDE
82611. DEFR6_ODPM02_DISP
82612. DEFR6_ODPM02_DSMR
82613. DEFR6_ODPM02_MASK
82614. DEFR6_ODPM12_CDE
82615. DEFR6_ODPM12_DISP
82616. DEFR6_ODPM12_DSMR
82617. DEFR6_ODPM12_MASK
82618. DEFR6_TCNE0
82619. DEFR6_TCNE1
82620. DEFR8
82621. DEFR8_CODE
82622. DEFR8_DEFE8
82623. DEFR8_DRGBS_DU
82624. DEFR8_DRGBS_MASK
82625. DEFR8_VSCS
82626. DEFREF
82627. DEFR_CODE
82628. DEFR_DEFE
82629. DEFR_EXSL
82630. DEFR_EXUP
82631. DEFR_EXVL
82632. DEFR_VCUP
82633. DEFSAMPLERATE
82634. DEFSAMPLESIZE
82635. DEFUN
82636. DEFUN_VOID
82637. DEF_ADDRS_PER_BLOCK
82638. DEF_ADDRS_PER_INODE
82639. DEF_AECH
82640. DEF_AP_COUNTRY_CODE
82641. DEF_ATO
82642. DEF_ATTR
82643. DEF_BASE
82644. DEF_BLUE
82645. DEF_BRIGHT
82646. DEF_BRK_TABLE_VAL
82647. DEF_BURGUNDY_ATTENHP
82648. DEF_BURGUNDY_ATTENLINEOUT
82649. DEF_BURGUNDY_ATTENSPEAKER
82650. DEF_BURGUNDY_GAINCD
82651. DEF_BURGUNDY_GAINLINE
82652. DEF_BURGUNDY_GAINMIC
82653. DEF_BURGUNDY_GAINMODEM
82654. DEF_BURGUNDY_INPSEL21
82655. DEF_BURGUNDY_INPSEL3_IMAC
82656. DEF_BURGUNDY_INPSEL3_PMAC
82657. DEF_BURGUNDY_MASTER_VOLUME
82658. DEF_BURGUNDY_MORE_OUTPUTENABLES
82659. DEF_BURGUNDY_OUTPUTENABLES
82660. DEF_BURGUNDY_OUTPUTSELECTS
82661. DEF_BURGUNDY_VOLCD
82662. DEF_BURGUNDY_VOLLINE
82663. DEF_BURGUNDY_VOLMIC
82664. DEF_BURGUNDY_VOLMODEM
82665. DEF_CAPOFFSET
82666. DEF_CDB_LEN
82667. DEF_CFG_NUM_CQS
82668. DEF_CFG_NUM_FABRICS
82669. DEF_CFG_NUM_FCXP_REQS
82670. DEF_CFG_NUM_IOIM_REQS
82671. DEF_CFG_NUM_ITNIMS
82672. DEF_CFG_NUM_LPORTS
82673. DEF_CFG_NUM_REQQ_ELEMS
82674. DEF_CFG_NUM_RPORTS
82675. DEF_CFG_NUM_RSPQ_ELEMS
82676. DEF_CFG_NUM_SBOOT_LUNS
82677. DEF_CFG_NUM_SBOOT_TGTS
82678. DEF_CFG_NUM_SGPGS
82679. DEF_CFG_NUM_TINS
82680. DEF_CFG_NUM_TSKIM_REQS
82681. DEF_CFG_NUM_UF_BUFS
82682. DEF_CHANNEL
82683. DEF_CHIP_REG
82684. DEF_CLKRC
82685. DEF_CMD_PAYLOAD_SIZE
82686. DEF_CMD_PER_LUN
82687. DEF_COLOR
82688. DEF_COMA
82689. DEF_COMB
82690. DEF_COMPACT_PRIORITY
82691. DEF_CONFIGFS_ATTRIB_SHOW
82692. DEF_CONFIGFS_ATTRIB_STORE_BOOL
82693. DEF_CONFIGFS_ATTRIB_STORE_STUB
82694. DEF_CONFIGFS_ATTRIB_STORE_U32
82695. DEF_CONTRAST
82696. DEF_CPB_SIZE
82697. DEF_CP_INTERVAL
82698. DEF_CSB_FUNC_OFF
82699. DEF_CSB_IGU_INDEX_OFF
82700. DEF_CSB_SEGMENT_OFF
82701. DEF_DEB_FLAGS
82702. DEF_DEPTH
82703. DEF_DETECT_CORRECT_VAL
82704. DEF_DEV_NAME_MAX17211
82705. DEF_DEV_NAME_MAX17215
82706. DEF_DEV_NAME_UNKNOWN
82707. DEF_DEV_SIZE_MB
82708. DEF_DEV_WWN_ASSOC_SHOW
82709. DEF_DIF
82710. DEF_DIRTY_NAT_RATIO_THRESHOLD
82711. DEF_DIR_LEVEL
82712. DEF_DISABLE_INTERVAL
82713. DEF_DISABLE_QUICK_INTERVAL
82714. DEF_DISCARD_URGENT_UTIL
82715. DEF_DISC_AUTH_INT
82716. DEF_DISC_AUTH_STR
82717. DEF_DIV6P1
82718. DEF_DIV6_RO
82719. DEF_DIX
82720. DEF_DST_FMT_ENC
82721. DEF_D_SENSE
82722. DEF_EN
82723. DEF_ERR
82724. DEF_EVERY_NTH
82725. DEF_FAKE_RW
82726. DEF_FDEC
82727. DEF_FIELD
82728. DEF_FIELD_ADDR
82729. DEF_FIELD_ADDR_VAR
82730. DEF_FIFO_DEPTH_WORDS
82731. DEF_FIFO_WIDTH_BITS
82732. DEF_FIXED
82733. DEF_FRAG_THRESHOLD
82734. DEF_FREQUENCY_DOWN_THRESHOLD
82735. DEF_FREQUENCY_STEP
82736. DEF_FREQUENCY_UP_THRESHOLD
82737. DEF_FSOURCE
82738. DEF_FX_ATTACK
82739. DEF_FX_CUTOFF
82740. DEF_FX_RELEASE
82741. DEF_FX_RESONANCE
82742. DEF_FX_VIBDELAY
82743. DEF_FX_VIBDEPTH
82744. DEF_FX_VIBRATE
82745. DEF_GAIN
82746. DEF_GC_FAILED_PINNED_FILES
82747. DEF_GC_THREAD_MAX_SLEEP_TIME
82748. DEF_GC_THREAD_MIN_SLEEP_TIME
82749. DEF_GC_THREAD_NOGC_SLEEP_TIME
82750. DEF_GC_THREAD_URGENT_SLEEP_TIME
82751. DEF_GEN3_MDSEL
82752. DEF_GEN3_OSC
82753. DEF_GEN3_PE
82754. DEF_GEN3_RCKSEL
82755. DEF_GEN3_SD
82756. DEF_GEN3_Z
82757. DEF_GUARD
82758. DEF_HOST_LOCK
82759. DEF_HSTOP
82760. DEF_HSTRT
82761. DEF_HUE
82762. DEF_ID
82763. DEF_IDLE_INTERVAL
82764. DEF_INLINE_RESERVED_SIZE
82765. DEF_INPUT
82766. DEF_INTS
82767. DEF_INT_ERR
82768. DEF_INT_MASK
82769. DEF_INT_TYPE_APIC
82770. DEF_IPID_START
82771. DEF_IPP
82772. DEF_JDELAY
82773. DEF_JUMBO_RX_COAL
82774. DEF_JUMBO_RX_MAX_DESC
82775. DEF_JUMBO_TX_COAL
82776. DEF_JUMBO_TX_MAX_DESC
82777. DEF_JUMBO_TX_RATIO
82778. DEF_KA_INTERVAL
82779. DEF_KA_MAX_PROBE_COUNT
82780. DEF_KA_TIMEOUT
82781. DEF_KEY_LOCK
82782. DEF_LBPRZ
82783. DEF_LBPU
82784. DEF_LBPWS
82785. DEF_LBPWS10
82786. DEF_LL2_MTU
82787. DEF_LOWEST_ALIGNED
82788. DEF_LRSSI_ROAM_FLOOR
82789. DEF_LRSSI_ROAM_THRESHOLD
82790. DEF_LRSSI_SCAN_PERIOD
82791. DEF_LVT_OFF
82792. DEF_MACINTMASK
82793. DEF_MAX_CWND
82794. DEF_MAX_DA_COUNT
82795. DEF_MAX_DISCARD_ISSUE_TIME
82796. DEF_MAX_DISCARD_REQUEST
82797. DEF_MAX_LUNS
82798. DEF_MAX_RECLAIM_PREFREE_SEGMENTS
82799. DEF_MAX_RT_TIME
82800. DEF_MAX_VICTIM_SEARCH
82801. DEF_MEM_LEVEL
82802. DEF_MFG_NAME
82803. DEF_MID_DISCARD_ISSUE_TIME
82804. DEF_MIN_DISCARD_ISSUE_TIME
82805. DEF_MIN_FSYNC_BLOCKS
82806. DEF_MIN_HOT_BLOCKS
82807. DEF_MIN_IPU_UTIL
82808. DEF_MIN_RATE
82809. DEF_MMIO_IN_D
82810. DEF_MMIO_IN_X
82811. DEF_MMIO_OUT_D
82812. DEF_MMIO_OUT_X
82813. DEF_MOD
82814. DEF_MODEI_NTSC_CONT
82815. DEF_MODULE_ATTR
82816. DEF_MOD_STB
82817. DEF_MSS
82818. DEF_NACL_AUTH_INT
82819. DEF_NACL_AUTH_STR
82820. DEF_NAT_CACHE_THRESHOLD
82821. DEF_NDELAY
82822. DEF_NGD_INT_MASK
82823. DEF_NIDS_PER_INODE
82824. DEF_NOT_SUBREG
82825. DEF_NO_LUN_0
82826. DEF_NUM_HOST
82827. DEF_NUM_PARTS
82828. DEF_NUM_TGTS
82829. DEF_NUM_VSI
82830. DEF_NURBS
82831. DEF_OPTS
82832. DEF_OPT_BLKS
82833. DEF_OPT_XFERLEN_EXP
82834. DEF_OUT_FREQ
82835. DEF_PATH_MTU
82836. DEF_PAUSE_OFF_THRES
82837. DEF_PAUSE_THRES
82838. DEF_PCI_AC_NORET
82839. DEF_PCI_AC_RET
82840. DEF_PCI_ERRORS
82841. DEF_PCI_HOOK_mem
82842. DEF_PCI_HOOK_pio
82843. DEF_PHYSBLK_EXP
82844. DEF_PLL
82845. DEF_PORT_IRQ
82846. DEF_PP
82847. DEF_PRIORITY
82848. DEF_PR_REG_ACTIVE
82849. DEF_PTYPE
82850. DEF_QLA_TPG_ATTRIB
82851. DEF_QUANTA
82852. DEF_RAM_THRESHOLD
82853. DEF_RATE
82854. DEF_RA_NID_PAGES
82855. DEF_RCV_BUF
82856. DEF_RDC
82857. DEF_RDC_VAL
82858. DEF_RDMAVTMMAP_H
82859. DEF_RDMAVTPD_H
82860. DEF_RDMAVT_H
82861. DEF_RDMAVT_INCCQ_H
82862. DEF_RDMAVT_INCMR_H
82863. DEF_RDMAVT_INCQP_H
82864. DEF_RDMA_VT_H
82865. DEF_RECLAIM_PREFREE_SEGMENTS
82866. DEF_RED
82867. DEF_RELAX
82868. DEF_REMOVABLE
82869. DEF_RETRY_MS
82870. DEF_RTS_THRESHOLD
82871. DEF_RVTAH_H
82872. DEF_RVTCQ_H
82873. DEF_RVTMAD_H
82874. DEF_RVTMCAST_H
82875. DEF_RVTMR_H
82876. DEF_RVTQP_H
82877. DEF_RVTSRQ_H
82878. DEF_RXINTMASK
82879. DEF_RXL
82880. DEF_RXL_DELTA
82881. DEF_RXQS_PER_INTF
82882. DEF_RX_ACCEPT
82883. DEF_RX_COAL
82884. DEF_RX_MAX_DESC
82885. DEF_RX_QUEUE_ENTRIES
82886. DEF_RX_RINGS
82887. DEF_RX_SLOTS
82888. DEF_SAMPLING_DOWN_FACTOR
82889. DEF_SATURATION
82890. DEF_SB_ID
82891. DEF_SB_IGU_ID
82892. DEF_SCALE
82893. DEF_SCAN_FOR_ROAM_INTVL
82894. DEF_SCAN_MAX_TIME
82895. DEF_SCAN_MIN_TIME
82896. DEF_SCSI_LEVEL
82897. DEF_SCSI_QCMD
82898. DEF_SECTOR_SIZE
82899. DEF_SEED
82900. DEF_SHORT_RETRY_LIMIT
82901. DEF_SND_BUF
82902. DEF_SND_SEQ_SCALE
82903. DEF_SORT_NAME_KEY
82904. DEF_SPU_TIMESLICE
82905. DEF_SRC_FMT_ENC
82906. DEF_SRPT_SQ_SIZE
82907. DEF_STAT
82908. DEF_STATISTICS
82909. DEF_STRICT
82910. DEF_STROBE_PROG
82911. DEF_SUBMIT_QUEUES
82912. DEF_SWS_TIMER
82913. DEF_TALITOS1_DONE
82914. DEF_TALITOS1_INTERRUPT
82915. DEF_TALITOS2_DONE
82916. DEF_TALITOS2_INTERRUPT
82917. DEF_THREADS_CNT
82918. DEF_TIMEOUT
82919. DEF_TIMER
82920. DEF_TOS
82921. DEF_TPG_ATTRIB
82922. DEF_TPG_AUTH_INT
82923. DEF_TPG_AUTH_STR
82924. DEF_TPG_PARAM
82925. DEF_TRACE
82926. DEF_TRAFFIC_CLASS
82927. DEF_TSB_FUNC_OFF
82928. DEF_TSB_IGU_INDEX_OFF
82929. DEF_TSB_SEGMENT_OFF
82930. DEF_TTL
82931. DEF_TX0_ACM
82932. DEF_TX0_AIFS
82933. DEF_TX0_CW_MAX_CCK
82934. DEF_TX0_CW_MAX_OFDM
82935. DEF_TX0_CW_MIN_CCK
82936. DEF_TX0_CW_MIN_OFDM
82937. DEF_TX0_TXOP_LIMIT_CCK
82938. DEF_TX0_TXOP_LIMIT_OFDM
82939. DEF_TX1_ACM
82940. DEF_TX1_AIFS
82941. DEF_TX1_CW_MAX_CCK
82942. DEF_TX1_CW_MAX_OFDM
82943. DEF_TX1_CW_MIN_CCK
82944. DEF_TX1_CW_MIN_OFDM
82945. DEF_TX1_TXOP_LIMIT_CCK
82946. DEF_TX1_TXOP_LIMIT_OFDM
82947. DEF_TX2_ACM
82948. DEF_TX2_AIFS
82949. DEF_TX2_CW_MAX_CCK
82950. DEF_TX2_CW_MAX_OFDM
82951. DEF_TX2_CW_MIN_CCK
82952. DEF_TX2_CW_MIN_OFDM
82953. DEF_TX2_TXOP_LIMIT_CCK
82954. DEF_TX2_TXOP_LIMIT_OFDM
82955. DEF_TX3_ACM
82956. DEF_TX3_AIFS
82957. DEF_TX3_CW_MAX_CCK
82958. DEF_TX3_CW_MAX_OFDM
82959. DEF_TX3_CW_MIN_CCK
82960. DEF_TX3_CW_MIN_OFDM
82961. DEF_TX3_TXOP_LIMIT_CCK
82962. DEF_TX3_TXOP_LIMIT_OFDM
82963. DEF_TXQS_PER_INTF
82964. DEF_TX_COAL
82965. DEF_TX_MAX_DESC
82966. DEF_TX_QUEUE_ENTRIES
82967. DEF_TX_RATIO
82968. DEF_TX_SLOTS
82969. DEF_TX_WM
82970. DEF_TYPE
82971. DEF_UMOUNT_DISCARD_TIMEOUT
82972. DEF_UNMAP_ALIGNMENT
82973. DEF_UNMAP_GRANULARITY
82974. DEF_UNMAP_MAX_BLOCKS
82975. DEF_UNMAP_MAX_DESC
82976. DEF_USB_BLOCK
82977. DEF_USB_FUNC_OFF
82978. DEF_USB_IGU_INDEX_OFF
82979. DEF_USB_SEGMENT_OFF
82980. DEF_UUID_CTL
82981. DEF_VID_CAPTURE
82982. DEF_VID_OUTPUT
82983. DEF_VIRTUAL_GB
82984. DEF_VPD_USE_HOSTNO
82985. DEF_VSTOP
82986. DEF_VSTRT
82987. DEF_WBITS
82988. DEF_WRITESAME_LENGTH
82989. DEF_XSB_FUNC_OFF
82990. DEF_XSB_IGU_INDEX_OFF
82991. DEF_XSB_SEGMENT_OFF
82992. DEFbit
82993. DEG180
82994. DEG270
82995. DEG360
82996. DEG90
82997. DEGAMMA_BYPASS
82998. DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK
82999. DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT
83000. DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK
83001. DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
83002. DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK
83003. DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
83004. DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK
83005. DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT
83006. DEGAMMA_MODE_A
83007. DEGAMMA_MODE_B
83008. DEGAMMA_MODE_BYPASS
83009. DEGAMMA_NONE
83010. DEGAMMA_SRGB
83011. DEGAMMA_SRGB_24
83012. DEGAMMA_XVYCC_222
83013. DEGAMMA_YUV12
83014. DEGAMMA_YUV8_10
83015. DEGLITCH
83016. DEGLITCH_TIME_128MS
83017. DEGLITCH_TIME_16MS
83018. DEGLITCH_TIME_2MS
83019. DEGLITCH_TIME_40MS
83020. DEGLITCH_TIME_4MS
83021. DEGLITCH_TIME_50MS
83022. DEGLITCH_TIME_60MS
83023. DEGLITCH_TIME_8MS
83024. DEGLITCH_TIME_MASK
83025. DEH_SIZE
83026. DEH_Statdata
83027. DEH_Visible
83028. DEIER
83029. DEIIR
83030. DEIMR
83031. DEISR
83032. DEI_RMK_DISABLE
83033. DEL
83034. DELACK_F
83035. DELACK_S
83036. DELACK_V
83037. DELAY
83038. DELAYACCT_PF_BLKIO
83039. DELAYACCT_PF_SWAPIN
83040. DELAYEDACKRESOLUTION_G
83041. DELAYEDACKRESOLUTION_M
83042. DELAYEDACKRESOLUTION_S
83043. DELAYEDALLOC
83044. DELAYED_BMSTART
83045. DELAYED_RESOURCE_CNT
83046. DELAYED_UPDATE_BEACON
83047. DELAYSTARTBLOCK
83048. DELAYS_NUM
83049. DELAY_16
83050. DELAY_18
83051. DELAY_AFTER_RESET
83052. DELAY_ALIGN
83053. DELAY_CALIBRATION_TICKS
83054. DELAY_CONVERSION_CONF_REG
83055. DELAY_DATA_MASK
83056. DELAY_DATA_MASK_SFT
83057. DELAY_DATA_MISO1
83058. DELAY_DATA_MISO2
83059. DELAY_DATA_SFT
83060. DELAY_DEFAULT
83061. DELAY_EN
83062. DELAY_ENABLE
83063. DELAY_INTERVAL_US
83064. DELAY_INT_CFG
83065. DELAY_INT_CFG_RXDLY_INT_EN
83066. DELAY_INT_CFG_RXMAX_PINT
83067. DELAY_INT_CFG_RXMAX_PTIME
83068. DELAY_INT_CFG_TXDLY_INT_EN
83069. DELAY_INT_CFG_TXMAX_PINT
83070. DELAY_INT_CFG_TXMAX_PTIME
83071. DELAY_LOOP_MAX
83072. DELAY_MS_DEFAULT
83073. DELAY_OF_ONE_MILLISEC
83074. DELAY_OUTPUT
83075. DELAY_PHY_PWR_CHG
83076. DELAY_PIN_WAKE
83077. DELAY_SAMPLE
83078. DELAY_SEND
83079. DELAY_TEST
83080. DELAY_TIME
83081. DELAY_TIMER_CONV
83082. DELAY_TRIGGER_BITS
83083. DELAY_TYPE_CLK
83084. DELAY_TYPE_READ
83085. DELAY_US
83086. DELBA_INITIATOR_POS
83087. DELBA_REASON_END_BA
83088. DELBA_REASON_TIMEOUT
83089. DELBA_REASON_UNKNOWN_BA
83090. DELBA_TID_POS
83091. DELCOM
83092. DELCOM_BLUE_LED
83093. DELCOM_GREEN_LED
83094. DELCOM_RED_LED
83095. DELETE
83096. DELETED_FLAG
83097. DELETE_DIRECTORY_REQ
83098. DELETE_DIRECTORY_RSP
83099. DELETE_DT_NODE
83100. DELETE_FILE_REQ
83101. DELETE_FILE_RSP
83102. DELETE_URB
83103. DELIM
83104. DELINK_INT
83105. DELINK_INT_EN
83106. DELIVERED_CTR
83107. DELLEMC_EFI_RCI2_TABLE_GUID
83108. DELL_EVENT_GUID
83109. DELL_IANA_MFR_ID
83110. DELL_INSPIRON_7375
83111. DELL_LAPTOP_KBD_BACKLIGHT_BRIGHTNESS_CHANGED
83112. DELL_LATITUDE_5495
83113. DELL_LATITUDE_D520
83114. DELL_LED_BIOS_GUID
83115. DELL_POWEREDGE_8G_BMC_DEVICE_ID
83116. DELL_POWEREDGE_8G_BMC_DEVICE_REV
83117. DELL_POWEREDGE_8G_BMC_IPMI_VERSION
83118. DELL_PRECISION_490
83119. DELL_PRODUCT_5500_MINICARD
83120. DELL_PRODUCT_5505_MINICARD
83121. DELL_PRODUCT_5510_EXPRESSCARD
83122. DELL_PRODUCT_5520_MINICARD_CINGULAR
83123. DELL_PRODUCT_5520_MINICARD_GENERIC_I
83124. DELL_PRODUCT_5520_MINICARD_GENERIC_L
83125. DELL_PRODUCT_5700_EXPRESSCARD
83126. DELL_PRODUCT_5700_MINICARD
83127. DELL_PRODUCT_5700_MINICARD_SPRINT
83128. DELL_PRODUCT_5700_MINICARD_TELUS
83129. DELL_PRODUCT_5720_MINICARD_SPRINT
83130. DELL_PRODUCT_5720_MINICARD_TELUS
83131. DELL_PRODUCT_5720_MINICARD_VZW
83132. DELL_PRODUCT_5730_MINICARD_SPRINT
83133. DELL_PRODUCT_5730_MINICARD_TELUS
83134. DELL_PRODUCT_5730_MINICARD_VZW
83135. DELL_PRODUCT_5800_MINICARD_VZW
83136. DELL_PRODUCT_5800_V2_MINICARD_VZW
83137. DELL_PRODUCT_5804_MINICARD_ATT
83138. DELL_PRODUCT_5821E
83139. DELL_PRODUCT_5821E_ESIM
83140. DELL_STUDIO
83141. DELL_TB_RX_AGG_BUG
83142. DELL_VENDOR_ID
83143. DELL_WMI_DESCRIPTOR_GUID
83144. DELL_WMI_SMBIOS_CMD
83145. DELL_WMI_SMBIOS_GUID
83146. DELL_XPS
83147. DELPT
83148. DELTA
83149. DELTANEXTU16
83150. DELTA_CD
83151. DELTA_CFG_H
83152. DELTA_CTS
83153. DELTA_DEBUG_H
83154. DELTA_DEFAULT_FRAMEFORMAT
83155. DELTA_DEFAULT_HEIGHT
83156. DELTA_DEFAULT_STREAMFORMAT
83157. DELTA_DEFAULT_WIDTH
83158. DELTA_DEVICE_DESC
83159. DELTA_DSR
83160. DELTA_FLAG_FRAMEINFO
83161. DELTA_FLAG_STREAMINFO
83162. DELTA_FRAMEINFO_FLAG_CROP
83163. DELTA_FRAMEINFO_FLAG_PIXELASPECT
83164. DELTA_FRAME_BSY
83165. DELTA_FRAME_DEC
83166. DELTA_FRAME_FREE
83167. DELTA_FRAME_M2M
83168. DELTA_FRAME_OUT
83169. DELTA_FRAME_RDY
83170. DELTA_FRAME_REF
83171. DELTA_FW_VERSION
83172. DELTA_H
83173. DELTA_HEIGHT_ALIGNMENT
83174. DELTA_HW_AUTOSUSPEND_DELAY_MS
83175. DELTA_IPC_CLOSE
83176. DELTA_IPC_DECODE
83177. DELTA_IPC_H
83178. DELTA_IPC_OPEN
83179. DELTA_IPC_SET_STREAM
83180. DELTA_MAX_AUS
83181. DELTA_MAX_DECODERS
83182. DELTA_MAX_DPB
83183. DELTA_MAX_FORMATS
83184. DELTA_MAX_FRAMES
83185. DELTA_MAX_FRAME_PRIV_SIZE
83186. DELTA_MAX_FRAME_USER
83187. DELTA_MAX_HEIGHT
83188. DELTA_MAX_RESO
83189. DELTA_MAX_WIDTH
83190. DELTA_MEM_H
83191. DELTA_MIN
83192. DELTA_MIN_FRAME_USER
83193. DELTA_MIN_HEIGHT
83194. DELTA_MIN_WIDTH
83195. DELTA_MJPEG_FW_H
83196. DELTA_MJPEG_H
83197. DELTA_MJPEG_MAX_RESO
83198. DELTA_M_FRAC_DEN
83199. DELTA_M_FRAC_NUM
83200. DELTA_M_MAX
83201. DELTA_NAME
83202. DELTA_PEAK_FRAME_SMOOTHING
83203. DELTA_PREFIX
83204. DELTA_RATE_CHECK
83205. DELTA_STATE_EOS
83206. DELTA_STATE_READY
83207. DELTA_STATE_WF_EOS
83208. DELTA_STATE_WF_FORMAT
83209. DELTA_STATE_WF_STREAMINFO
83210. DELTA_STREAMINFO_FLAG_CROP
83211. DELTA_STREAMINFO_FLAG_OTHER
83212. DELTA_STREAMINFO_FLAG_PIXELASPECT
83213. DELTA_SWINGIDX_SIZE
83214. DELTA_TYPE1
83215. DELTA_TYPE2
83216. DELTA_TYPE3
83217. DELTA_TYPE4
83218. DELTA_WIDTH_ALIGNMENT
83219. DELTA_WRAP32
83220. DEL_ADDR
83221. DEL_CMD_Q_JOB
83222. DEL_Q_ACTIVE
83223. DEL_Q_ID_SHIFT
83224. DEL_SW_IDX_SZ
83225. DEL_VLAN_CMD
83226. DEM0
83227. DEM1
83228. DEMAND_DMA_DIRECTION_TX_BIT
83229. DEMAND_MODE
83230. DEMATRIX_CTL
83231. DEMOD
83232. DEMOD_LOCK
83233. DEMOD_LOCKED
83234. DEMOD_MODCOD
83235. DEMOD_MODE
83236. DEMOD_READ
83237. DEMOD_RW
83238. DEMOD_TIMF_GET
83239. DEMOD_TIMF_SET
83240. DEMOD_TIMF_UPDATE
83241. DEMOD_TYPE
83242. DEMOD_TYPE_DRXK
83243. DEMOD_TYPE_SONY_C2T2
83244. DEMOD_TYPE_SONY_C2T2I
83245. DEMOD_TYPE_SONY_CT2
83246. DEMOD_TYPE_SONY_ISDBT
83247. DEMOD_TYPE_STV0367
83248. DEMOD_TYPE_STV090X
83249. DEMOD_TYPE_STV0910
83250. DEMOD_TYPE_ST_ATSC
83251. DEMOD_TYPE_XO2
83252. DEMOD_UNUSED
83253. DEMOD_VES1893
83254. DEMOD_VES1993
83255. DEMOD_WRITE
83256. DEMOTE_PERIOD
83257. DEMOTION_COUNT
83258. DEMOUT_ON_HOSTBUS
83259. DEMP1
83260. DEMP2
83261. DEMPH_MODE_SET
83262. DEMUX_108M
83263. DEMUX_148M5
83264. DEMUX_APB
83265. DEMUX_AXI
83266. DEMUX_CONTROL
83267. DEMUX_PV_STATE_ACTIVE
83268. DEMUX_PV_STATE_DOWN
83269. DEMUX_PV_STATE_DOWNING
83270. DEMUX_PV_STATE_STARTING
83271. DEMUX_TSOUT
83272. DEM_32K
83273. DEM_441
83274. DEM_48K
83275. DEM_MASK
83276. DEN
83277. DENALI_BANK
83278. DENALI_CAP_DMA_64BIT
83279. DENALI_CAP_HW_ECC_FIXUP
83280. DENALI_CTL_112_OFF
83281. DENALI_CTL_22_OFF
83282. DENALI_DEFAULT_OOB_SKIP_BYTES
83283. DENALI_INDEXED_CTRL
83284. DENALI_INDEXED_DATA
83285. DENALI_INVALID_BANK
83286. DENALI_MAP00
83287. DENALI_MAP01
83288. DENALI_MAP10
83289. DENALI_MAP11
83290. DENALI_MAP11_ADDR
83291. DENALI_MAP11_CMD
83292. DENALI_MAP11_DATA
83293. DENALI_NAND_NAME
83294. DENC
83295. DENC_AB_CTRL
83296. DENC_A_REG_1
83297. DENC_A_REG_2
83298. DENC_A_REG_3
83299. DENC_A_REG_4
83300. DENC_A_REG_5
83301. DENC_A_REG_6
83302. DENC_A_REG_7
83303. DENC_A_REG_8
83304. DENC_B_REG_1
83305. DENC_B_REG_2
83306. DENC_B_REG_3
83307. DENC_B_REG_4
83308. DENC_B_REG_5
83309. DENC_B_REG_6
83310. DENC_B_REG_7
83311. DENC_B_REG_8
83312. DENDA
83313. DENDE
83314. DENOISE_ACTRL
83315. DENORMAL
83316. DENORM_CLAMP_CONTROL_10
83317. DENORM_CLAMP_CONTROL_12
83318. DENORM_CLAMP_CONTROL_8
83319. DENORM_CLAMP_CONTROL_UNITY
83320. DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK
83321. DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT
83322. DENORM_CLAMP_CONTROL__DENORM_FACTOR_MASK
83323. DENORM_CLAMP_CONTROL__DENORM_FACTOR__SHIFT
83324. DENORM_CLAMP_CONTROL__DENORM_MODE_MASK
83325. DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT
83326. DENORM_CLAMP_MODE_10
83327. DENORM_CLAMP_MODE_12
83328. DENORM_CLAMP_MODE_8
83329. DENORM_CLAMP_MODE_UNITY
83330. DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK
83331. DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT
83332. DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK
83333. DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT
83334. DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK
83335. DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT
83336. DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK
83337. DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT
83338. DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK
83339. DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT
83340. DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK
83341. DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT
83342. DENORM_CONTROL__DENORM_14BIT_OUT_MASK
83343. DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT
83344. DENORM_CONTROL__DENORM_MODE_MASK
83345. DENORM_CONTROL__DENORM_MODE__SHIFT
83346. DENORM_TRUNCATE
83347. DENTIST_BASE_DID_1
83348. DENTIST_BASE_DID_2
83349. DENTIST_BASE_DID_3
83350. DENTIST_BASE_DID_4
83351. DENTIST_DISPCLK_CNTL
83352. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK
83353. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT
83354. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK
83355. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT
83356. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK
83357. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT
83358. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK
83359. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT
83360. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK
83361. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT
83362. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK
83363. DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT
83364. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK
83365. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT
83366. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK
83367. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT
83368. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK
83369. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT
83370. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK
83371. DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT
83372. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK
83373. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT
83374. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK
83375. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT
83376. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK
83377. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT
83378. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK
83379. DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT
83380. DENTIST_DIVIDER_RANGE_1_START
83381. DENTIST_DIVIDER_RANGE_1_STEP
83382. DENTIST_DIVIDER_RANGE_2_START
83383. DENTIST_DIVIDER_RANGE_2_STEP
83384. DENTIST_DIVIDER_RANGE_3_START
83385. DENTIST_DIVIDER_RANGE_3_STEP
83386. DENTIST_DIVIDER_RANGE_4_START
83387. DENTIST_DIVIDER_RANGE_4_STEP
83388. DENTIST_DIVIDER_RANGE_SCALE_FACTOR
83389. DENTIST_DPREFCLK_WDIVIDER
83390. DENTIST_DPREFCLK_WDIVIDER_MASK
83391. DENTIST_DPREFCLK_WDIVIDER_SHIFT
83392. DENTIST_MAX_DID
83393. DENTRY_D_LOCK_NESTED
83394. DENTRY_D_LOCK_NORMAL
83395. DENTRY_REMOVE
83396. DENTRY_SIZE
83397. DENTRY_SIZE_BITS
83398. DENT_BIT_SHIFT
83399. DENY
83400. DENY_ATTACH
83401. DENY_LOAD
83402. DEN_4Gb
83403. DEN_8Gb
83404. DEN_NEGATIVE
83405. DEP
83406. DEPEVT_PARAMETER_CMD
83407. DEPEVT_STATUS_BUSERR
83408. DEPEVT_STATUS_CONTROL_DATA
83409. DEPEVT_STATUS_CONTROL_PHASE
83410. DEPEVT_STATUS_CONTROL_STATUS
83411. DEPEVT_STATUS_IOC
83412. DEPEVT_STATUS_LST
83413. DEPEVT_STATUS_MISSED_ISOC
83414. DEPEVT_STATUS_SHORT
83415. DEPEVT_STATUS_TRANSFER_ACTIVE
83416. DEPEVT_STREAMEVT_FOUND
83417. DEPEVT_STREAMEVT_NOTFOUND
83418. DEPEVT_TRANSFER_BUS_EXPIRY
83419. DEPEVT_TRANSFER_NO_RESOURCE
83420. DEPOT_STACK_BITS
83421. DEPRECATED
83422. DEPTH
83423. DEPTH4_16
83424. DEPTH4_24_8
83425. DEPTH4_32
83426. DEPTH4_NONE
83427. DEPTH5_16
83428. DEPTH5_24_8
83429. DEPTH5_32
83430. DEPTH5_NONE
83431. DEPTH6_16
83432. DEPTH6_24_8
83433. DEPTH6_32
83434. DEPTH6_NONE
83435. DEPTHX_16
83436. DEPTHX_24_8
83437. DEPTHX_32
83438. DEPTH_16
83439. DEPTH_24
83440. DEPTH_32
83441. DEPTH_32_FLOAT
83442. DEPTH_8_24
83443. DEPTH_8_24_FLOAT
83444. DEPTH_CACHELINE_FREE
83445. DEPTH_FLUSH
83446. DEPTH_FREE
83447. DEPTH_INVALID
83448. DEPTH_MICRO_TILING
83449. DEPTH_NOISE
83450. DEPTH_NONE
83451. DEPTH_ONLY
83452. DEPTH_PENDING_FREE
83453. DEPTH_RSSI
83454. DEPTH_X24_8_32_FLOAT
83455. DEPTH_X8_24
83456. DEPTH_X8_24_FLOAT
83457. DEQUEUE_MOVE
83458. DEQUEUE_NOCLOCK
83459. DEQUEUE_REQUEST_DRAIN
83460. DEQUEUE_REQUEST_INT_ENABLE
83461. DEQUEUE_REQUEST_INT_STATUS
83462. DEQUEUE_REQUEST_RESET
83463. DEQUEUE_SAVE
83464. DEQUEUE_SLEEP
83465. DEREF_REG_PR
83466. DEREGISTER
83467. DEREG_MR
83468. DERRMR
83469. DERRMR_PIPEA_HBLANK
83470. DERRMR_PIPEA_PRI_FLIP_DONE
83471. DERRMR_PIPEA_SCANLINE
83472. DERRMR_PIPEA_SPR_FLIP_DONE
83473. DERRMR_PIPEA_VBLANK
83474. DERRMR_PIPEB_HBLANK
83475. DERRMR_PIPEB_PRI_FLIP_DONE
83476. DERRMR_PIPEB_SCANLINE
83477. DERRMR_PIPEB_SPR_FLIP_DONE
83478. DERRMR_PIPEB_VBLANK
83479. DERRMR_PIPEC_HBLANK
83480. DERRMR_PIPEC_PRI_FLIP_DONE
83481. DERRMR_PIPEC_SCANLINE
83482. DERRMR_PIPEC_SPR_FLIP_DONE
83483. DERRMR_PIPEC_VBLANK
83484. DER_ALIE
83485. DER_CHSTPE
83486. DER_DECIE
83487. DER_DPIE
83488. DER_DTLBERE
83489. DER_DTLBMSE
83490. DER_EBRKE
83491. DER_EXTIE
83492. DER_FPUVIE
83493. DER_IBRKE
83494. DER_ITLBERE
83495. DER_ITLBMSE
83496. DER_LBRKE
83497. DER_MCIE
83498. DER_PRIE
83499. DER_RDDE
83500. DER_RSTE
83501. DER_SEIE
83502. DER_SYSIE
83503. DER_TDDE
83504. DER_TRE
83505. DES3_CBC
83506. DES3_ECB
83507. DES3_EDE_BLOCK_SIZE
83508. DES3_EDE_EXPKEY_WORDS
83509. DES3_EDE_KEY_SIZE
83510. DES3_KEY_SIZE
83511. DES3_LOOP_BODY
83512. DES3_SPEED_VECTORS
83513. DESC8723B_RATE11M
83514. DESC8723B_RATE12M
83515. DESC8723B_RATE18M
83516. DESC8723B_RATE1M
83517. DESC8723B_RATE24M
83518. DESC8723B_RATE2M
83519. DESC8723B_RATE36M
83520. DESC8723B_RATE48M
83521. DESC8723B_RATE54M
83522. DESC8723B_RATE5_5M
83523. DESC8723B_RATE6M
83524. DESC8723B_RATE9M
83525. DESC8723B_RATEMCS0
83526. DESC8723B_RATEMCS1
83527. DESC8723B_RATEMCS10
83528. DESC8723B_RATEMCS11
83529. DESC8723B_RATEMCS12
83530. DESC8723B_RATEMCS13
83531. DESC8723B_RATEMCS14
83532. DESC8723B_RATEMCS15
83533. DESC8723B_RATEMCS2
83534. DESC8723B_RATEMCS3
83535. DESC8723B_RATEMCS4
83536. DESC8723B_RATEMCS5
83537. DESC8723B_RATEMCS6
83538. DESC8723B_RATEMCS7
83539. DESC8723B_RATEMCS8
83540. DESC8723B_RATEMCS9
83541. DESC8723B_RATEVHTSS1MCS0
83542. DESC8723B_RATEVHTSS1MCS1
83543. DESC8723B_RATEVHTSS1MCS2
83544. DESC8723B_RATEVHTSS1MCS3
83545. DESC8723B_RATEVHTSS1MCS4
83546. DESC8723B_RATEVHTSS1MCS5
83547. DESC8723B_RATEVHTSS1MCS6
83548. DESC8723B_RATEVHTSS1MCS7
83549. DESC8723B_RATEVHTSS1MCS8
83550. DESC8723B_RATEVHTSS1MCS9
83551. DESC8723B_RATEVHTSS2MCS0
83552. DESC8723B_RATEVHTSS2MCS1
83553. DESC8723B_RATEVHTSS2MCS2
83554. DESC8723B_RATEVHTSS2MCS3
83555. DESC8723B_RATEVHTSS2MCS4
83556. DESC8723B_RATEVHTSS2MCS5
83557. DESC8723B_RATEVHTSS2MCS6
83558. DESC8723B_RATEVHTSS2MCS7
83559. DESC8723B_RATEVHTSS2MCS8
83560. DESC8723B_RATEVHTSS2MCS9
83561. DESC90_RATE11M
83562. DESC90_RATE12M
83563. DESC90_RATE18M
83564. DESC90_RATE1M
83565. DESC90_RATE24M
83566. DESC90_RATE2M
83567. DESC90_RATE36M
83568. DESC90_RATE48M
83569. DESC90_RATE54M
83570. DESC90_RATE5_5M
83571. DESC90_RATE6M
83572. DESC90_RATE9M
83573. DESC90_RATEMCS0
83574. DESC90_RATEMCS1
83575. DESC90_RATEMCS10
83576. DESC90_RATEMCS11
83577. DESC90_RATEMCS12
83578. DESC90_RATEMCS13
83579. DESC90_RATEMCS14
83580. DESC90_RATEMCS15
83581. DESC90_RATEMCS2
83582. DESC90_RATEMCS3
83583. DESC90_RATEMCS32
83584. DESC90_RATEMCS4
83585. DESC90_RATEMCS5
83586. DESC90_RATEMCS6
83587. DESC90_RATEMCS7
83588. DESC90_RATEMCS8
83589. DESC90_RATEMCS9
83590. DESC92C_RATE11M
83591. DESC92C_RATE12M
83592. DESC92C_RATE18M
83593. DESC92C_RATE1M
83594. DESC92C_RATE24M
83595. DESC92C_RATE2M
83596. DESC92C_RATE36M
83597. DESC92C_RATE48M
83598. DESC92C_RATE54M
83599. DESC92C_RATE5_5M
83600. DESC92C_RATE6M
83601. DESC92C_RATE9M
83602. DESC92C_RATEMCS0
83603. DESC92C_RATEMCS1
83604. DESC92C_RATEMCS10
83605. DESC92C_RATEMCS11
83606. DESC92C_RATEMCS12
83607. DESC92C_RATEMCS13
83608. DESC92C_RATEMCS14
83609. DESC92C_RATEMCS15
83610. DESC92C_RATEMCS15_SG
83611. DESC92C_RATEMCS2
83612. DESC92C_RATEMCS3
83613. DESC92C_RATEMCS32
83614. DESC92C_RATEMCS4
83615. DESC92C_RATEMCS5
83616. DESC92C_RATEMCS6
83617. DESC92C_RATEMCS7
83618. DESC92C_RATEMCS8
83619. DESC92C_RATEMCS9
83620. DESCHEDULE_VPE
83621. DESCLABEL_ARGS
83622. DESCLABEL_FMT
83623. DESCNUM_THRESHOLD
83624. DESCRFMT
83625. DESCRIBE_FLAG
83626. DESCRIPTION0
83627. DESCRIPTION1
83628. DESCRIPTION10
83629. DESCRIPTION11
83630. DESCRIPTION12
83631. DESCRIPTION13
83632. DESCRIPTION14
83633. DESCRIPTION15
83634. DESCRIPTION16
83635. DESCRIPTION17
83636. DESCRIPTION2
83637. DESCRIPTION3
83638. DESCRIPTION4
83639. DESCRIPTION5
83640. DESCRIPTION6
83641. DESCRIPTION7
83642. DESCRIPTION8
83643. DESCRIPTION9
83644. DESCRIPTOR
83645. DESCRIPTOR_AAL5
83646. DESCRIPTOR_AAL5_STREAM
83647. DESCRIPTOR_BRANCH_ALWAYS
83648. DESCRIPTOR_BYTE_2
83649. DESCRIPTOR_CLP
83650. DESCRIPTOR_CMD
83651. DESCRIPTOR_DATA
83652. DESCRIPTOR_FLAG_MSK
83653. DESCRIPTOR_INPUT_LAST
83654. DESCRIPTOR_INPUT_MORE
83655. DESCRIPTOR_IRQ_ALWAYS
83656. DESCRIPTOR_IRQ_ERROR
83657. DESCRIPTOR_KEY_IMMEDIATE
83658. DESCRIPTOR_LOCATION
83659. DESCRIPTOR_MAGIC
83660. DESCRIPTOR_NO_IRQ
83661. DESCRIPTOR_OUTPUT_LAST
83662. DESCRIPTOR_OUTPUT_MORE
83663. DESCRIPTOR_PING
83664. DESCRIPTOR_POLLING_RATE
83665. DESCRIPTOR_STATUS
83666. DESCRIPTOR_SUBUNIT_IDENTIFIER
83667. DESCRIPTOR_TUNER_STATUS
83668. DESCRIPTOR_WAIT
83669. DESCRIPTOR_YY
83670. DESCR_SIZE
83671. DESCS_AREAS
83672. DESCS_IN_PAGE
83673. DESCTYPE_S
83674. DESC_ADDR_HI_MASK
83675. DESC_ADDR_HI_SHIFT
83676. DESC_ADDR_HI_STATUS_LEN
83677. DESC_ADDR_LO
83678. DESC_AEAD_BASE
83679. DESC_AEAD_CTR_RFC3686_LEN
83680. DESC_AEAD_DEC_LEN
83681. DESC_AEAD_ENC_LEN
83682. DESC_AEAD_GIVENC_LEN
83683. DESC_AEAD_NULL_BASE
83684. DESC_AEAD_NULL_DEC_LEN
83685. DESC_AEAD_NULL_ENC_LEN
83686. DESC_AHASH_BASE
83687. DESC_AHASH_DIGEST_LEN
83688. DESC_AHASH_FINAL_LEN
83689. DESC_AHASH_UPDATE_FIRST_LEN
83690. DESC_AHASH_UPDATE_LEN
83691. DESC_ALIGN
83692. DESC_ALIGNMENT
83693. DESC_ALL_CNT
83694. DESC_BTS
83695. DESC_BUFFER1_SZ_MASK
83696. DESC_BUFFER2_SZ_MASK
83697. DESC_BUFFER2_SZ_OFFSET
83698. DESC_BUFF_LEN_OFF
83699. DESC_BUFPTR
83700. DESC_BUF_SIZE
83701. DESC_CACHE_DEPTH_1
83702. DESC_CACHE_DEPTH_2
83703. DESC_CACHE_DEPTH_3
83704. DESC_CACHE_DEPTH_4
83705. DESC_CACHE_DEPTH_SHIFT
83706. DESC_CLEAN_LOW_WATERMARK
83707. DESC_CMDSTS
83708. DESC_COMPLETED
83709. DESC_CONSTR_H
83710. DESC_CTRL_CMASK
83711. DESC_CTRL_EOF
83712. DESC_CTRL_EOT
83713. DESC_CTRL_IOC
83714. DESC_CTRL_LEN
83715. DESC_CTRL_SOF
83716. DESC_DATA_LEN_OFF
83717. DESC_DATA_MASK
83718. DESC_DBG_DECO_STAT_MASK
83719. DESC_DBG_DECO_STAT_SHIFT
83720. DESC_DBG_DECO_STAT_VALID
83721. DESC_DEC
83722. DESC_DER_DECO_STAT_MASK
83723. DESC_DER_DECO_STAT_SHIFT
83724. DESC_DIRECTION_DECRYPT_DECRYPT
83725. DESC_DIRECTION_DECRYPT_ENCRYPT
83726. DESC_DIRECTION_ENCRYPT_ENCRYPT
83727. DESC_DIRECTION_END
83728. DESC_DIRECTION_ILLEGAL
83729. DESC_DMA_MAP_PAGE
83730. DESC_DMA_MAP_SINGLE
83731. DESC_DONE_FLAG
83732. DESC_DS
83733. DESC_EMPTY
83734. DESC_ENC
83735. DESC_EOC
83736. DESC_EOF
83737. DESC_EOP
83738. DESC_EXTSTS
83739. DESC_FLAG_CMD
83740. DESC_FLAG_EOB
83741. DESC_FLAG_EOT
83742. DESC_FLAG_INT
83743. DESC_FLAG_NWD
83744. DESC_FL_FIRST
83745. DESC_FL_FULL
83746. DESC_FL_LAST
83747. DESC_FL_MID
83748. DESC_FRAGS_NUM_OFF
83749. DESC_GCM_BASE
83750. DESC_GCM_DEC_LEN
83751. DESC_GCM_ENC_LEN
83752. DESC_GET
83753. DESC_H
83754. DESC_HASH_MAX_USED_BYTES
83755. DESC_HASH_MAX_USED_LEN
83756. DESC_HDR_DIR_INBOUND
83757. DESC_HDR_DONE
83758. DESC_HDR_DONE_NOTIFY
83759. DESC_HDR_LO_ICCR1_FAIL
83760. DESC_HDR_LO_ICCR1_MASK
83761. DESC_HDR_LO_ICCR1_PASS
83762. DESC_HDR_MODE0_AESU_CBC
83763. DESC_HDR_MODE0_AESU_CTR
83764. DESC_HDR_MODE0_DEU_3DES
83765. DESC_HDR_MODE0_DEU_CBC
83766. DESC_HDR_MODE0_ENCRYPT
83767. DESC_HDR_MODE0_MDEUB_SHA384
83768. DESC_HDR_MODE0_MDEUB_SHA512
83769. DESC_HDR_MODE0_MDEU_CONT
83770. DESC_HDR_MODE0_MDEU_HMAC
83771. DESC_HDR_MODE0_MDEU_INIT
83772. DESC_HDR_MODE0_MDEU_MD5
83773. DESC_HDR_MODE0_MDEU_MD5_HMAC
83774. DESC_HDR_MODE0_MDEU_PAD
83775. DESC_HDR_MODE0_MDEU_SHA1
83776. DESC_HDR_MODE0_MDEU_SHA1_HMAC
83777. DESC_HDR_MODE0_MDEU_SHA224
83778. DESC_HDR_MODE0_MDEU_SHA256
83779. DESC_HDR_MODE0_MDEU_SHA256_HMAC
83780. DESC_HDR_MODE1_MDEUB_SHA384
83781. DESC_HDR_MODE1_MDEUB_SHA384_HMAC
83782. DESC_HDR_MODE1_MDEUB_SHA512
83783. DESC_HDR_MODE1_MDEUB_SHA512_HMAC
83784. DESC_HDR_MODE1_MDEU_CICV
83785. DESC_HDR_MODE1_MDEU_HMAC
83786. DESC_HDR_MODE1_MDEU_INIT
83787. DESC_HDR_MODE1_MDEU_MD5
83788. DESC_HDR_MODE1_MDEU_MD5_HMAC
83789. DESC_HDR_MODE1_MDEU_PAD
83790. DESC_HDR_MODE1_MDEU_SHA1
83791. DESC_HDR_MODE1_MDEU_SHA1_HMAC
83792. DESC_HDR_MODE1_MDEU_SHA224
83793. DESC_HDR_MODE1_MDEU_SHA224_HMAC
83794. DESC_HDR_MODE1_MDEU_SHA256
83795. DESC_HDR_MODE1_MDEU_SHA256_HMAC
83796. DESC_HDR_SEL0_AESU
83797. DESC_HDR_SEL0_AFEU
83798. DESC_HDR_SEL0_CRCU
83799. DESC_HDR_SEL0_DEU
83800. DESC_HDR_SEL0_KEU
83801. DESC_HDR_SEL0_MASK
83802. DESC_HDR_SEL0_MDEUA
83803. DESC_HDR_SEL0_MDEUB
83804. DESC_HDR_SEL0_PKEU
83805. DESC_HDR_SEL0_RNG
83806. DESC_HDR_SEL1_CRCU
83807. DESC_HDR_SEL1_MASK
83808. DESC_HDR_SEL1_MDEUA
83809. DESC_HDR_SEL1_MDEUB
83810. DESC_HDR_TYPE_AESU_CTR_NONSNOOP
83811. DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU
83812. DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU
83813. DESC_HDR_TYPE_IPSEC_ESP
83814. DESC_HW
83815. DESC_ID
83816. DESC_IDLE
83817. DESC_IMMEDIATE_WAKEUP
83818. DESC_INDEX
83819. DESC_INTERRUPT
83820. DESC_IOD
83821. DESC_IVALID
83822. DESC_I_BIT
83823. DESC_I_RINT1
83824. DESC_I_RINT2
83825. DESC_I_RINT3
83826. DESC_I_RINT4
83827. DESC_I_RINT5
83828. DESC_I_RINT8
83829. DESC_I_TINT1
83830. DESC_I_TINT2
83831. DESC_I_TINT3
83832. DESC_I_TINT4
83833. DESC_JOB_IO_LEN
83834. DESC_JOB_IO_LEN_MAX
83835. DESC_JOB_IO_LEN_MIN
83836. DESC_JOB_O_LEN
83837. DESC_L4_CSUM
83838. DESC_LDT
83839. DESC_LEN
83840. DESC_LENGTH
83841. DESC_LENGTH_BITS_NUM
83842. DESC_LEN_MASK
83843. DESC_LEN_SHIFT
83844. DESC_LINK
83845. DESC_LIST_SIZE
83846. DESC_LK
83847. DESC_MAX_MASK
83848. DESC_MAX_USED_BYTES
83849. DESC_MAX_USED_LEN
83850. DESC_MODE
83851. DESC_MORE
83852. DESC_NEEDED
83853. DESC_NTYPE_TYPE2
83854. DESC_NUM
83855. DESC_NUM_ACTIVE_D_BUF_SHIFT
83856. DESC_NXT_DV_REFRESH
83857. DESC_NXT_DV_REUSE
83858. DESC_NXT_SV_REFRESH
83859. DESC_NXT_SV_REUSE
83860. DESC_OP_MODE_CRC32
83861. DESC_OP_MODE_MEMCPY
83862. DESC_OP_MODE_MEMINIT
83863. DESC_OP_MODE_MEMSET
83864. DESC_OP_MODE_MEM_COMPARE
83865. DESC_OP_MODE_NOP
83866. DESC_OP_MODE_RAID6
83867. DESC_OP_MODE_RAID6_REC
83868. DESC_OP_MODE_SHIFT
83869. DESC_OP_MODE_XOR
83870. DESC_OWN
83871. DESC_OWNED_BY_DC21X4
83872. DESC_OWNED_BY_SYSTEM
83873. DESC_PACKET_TYPE_INIT
83874. DESC_PACKET_TYPE_NORMAL
83875. DESC_PAYLOAD_MASK
83876. DESC_PAYLOAD_SHIFT
83877. DESC_PD_COMPLETE
83878. DESC_PER_PAGE
83879. DESC_PKTLEN_M
83880. DESC_PREPARED
83881. DESC_PTR_LNKTBL_JUMP
83882. DESC_PTR_LNKTBL_NEXT
83883. DESC_PTR_LNKTBL_RET
83884. DESC_PTR_MASK
83885. DESC_P_BUFFER_ENABLE
83886. DESC_QI_AEAD_DEC_LEN
83887. DESC_QI_AEAD_ENC_LEN
83888. DESC_QI_AEAD_GIVENC_LEN
83889. DESC_QI_GCM_DEC_LEN
83890. DESC_QI_GCM_ENC_LEN
83891. DESC_QI_RFC4106_DEC_LEN
83892. DESC_QI_RFC4106_ENC_LEN
83893. DESC_QI_RFC4543_DEC_LEN
83894. DESC_QI_RFC4543_ENC_LEN
83895. DESC_Q_BUFFER_ENABLE
83896. DESC_RATE11M
83897. DESC_RATE12M
83898. DESC_RATE18M
83899. DESC_RATE1M
83900. DESC_RATE24M
83901. DESC_RATE2M
83902. DESC_RATE36M
83903. DESC_RATE48M
83904. DESC_RATE54M
83905. DESC_RATE5_5M
83906. DESC_RATE6M
83907. DESC_RATE9M
83908. DESC_RATEMCS0
83909. DESC_RATEMCS1
83910. DESC_RATEMCS10
83911. DESC_RATEMCS11
83912. DESC_RATEMCS12
83913. DESC_RATEMCS13
83914. DESC_RATEMCS14
83915. DESC_RATEMCS15
83916. DESC_RATEMCS15_SG
83917. DESC_RATEMCS16
83918. DESC_RATEMCS17
83919. DESC_RATEMCS18
83920. DESC_RATEMCS19
83921. DESC_RATEMCS2
83922. DESC_RATEMCS20
83923. DESC_RATEMCS21
83924. DESC_RATEMCS22
83925. DESC_RATEMCS23
83926. DESC_RATEMCS24
83927. DESC_RATEMCS25
83928. DESC_RATEMCS26
83929. DESC_RATEMCS27
83930. DESC_RATEMCS28
83931. DESC_RATEMCS29
83932. DESC_RATEMCS3
83933. DESC_RATEMCS30
83934. DESC_RATEMCS31
83935. DESC_RATEMCS32
83936. DESC_RATEMCS4
83937. DESC_RATEMCS5
83938. DESC_RATEMCS6
83939. DESC_RATEMCS7
83940. DESC_RATEMCS8
83941. DESC_RATEMCS9
83942. DESC_RATEVHT1SS_MCS0
83943. DESC_RATEVHT1SS_MCS1
83944. DESC_RATEVHT1SS_MCS2
83945. DESC_RATEVHT1SS_MCS3
83946. DESC_RATEVHT1SS_MCS4
83947. DESC_RATEVHT1SS_MCS5
83948. DESC_RATEVHT1SS_MCS6
83949. DESC_RATEVHT1SS_MCS7
83950. DESC_RATEVHT1SS_MCS8
83951. DESC_RATEVHT1SS_MCS9
83952. DESC_RATEVHT2SS_MCS0
83953. DESC_RATEVHT2SS_MCS1
83954. DESC_RATEVHT2SS_MCS2
83955. DESC_RATEVHT2SS_MCS3
83956. DESC_RATEVHT2SS_MCS4
83957. DESC_RATEVHT2SS_MCS5
83958. DESC_RATEVHT2SS_MCS6
83959. DESC_RATEVHT2SS_MCS7
83960. DESC_RATEVHT2SS_MCS8
83961. DESC_RATEVHT2SS_MCS9
83962. DESC_RATEVHT3SS_MCS0
83963. DESC_RATEVHT3SS_MCS1
83964. DESC_RATEVHT3SS_MCS2
83965. DESC_RATEVHT3SS_MCS3
83966. DESC_RATEVHT3SS_MCS4
83967. DESC_RATEVHT3SS_MCS5
83968. DESC_RATEVHT3SS_MCS6
83969. DESC_RATEVHT3SS_MCS7
83970. DESC_RATEVHT3SS_MCS8
83971. DESC_RATEVHT3SS_MCS9
83972. DESC_RATEVHT4SS_MCS0
83973. DESC_RATEVHT4SS_MCS1
83974. DESC_RATEVHT4SS_MCS2
83975. DESC_RATEVHT4SS_MCS3
83976. DESC_RATEVHT4SS_MCS4
83977. DESC_RATEVHT4SS_MCS5
83978. DESC_RATEVHT4SS_MCS6
83979. DESC_RATEVHT4SS_MCS7
83980. DESC_RATEVHT4SS_MCS8
83981. DESC_RATEVHT4SS_MCS9
83982. DESC_RATEVHTSS1MCS0
83983. DESC_RATEVHTSS1MCS1
83984. DESC_RATEVHTSS1MCS2
83985. DESC_RATEVHTSS1MCS3
83986. DESC_RATEVHTSS1MCS4
83987. DESC_RATEVHTSS1MCS5
83988. DESC_RATEVHTSS1MCS6
83989. DESC_RATEVHTSS1MCS7
83990. DESC_RATEVHTSS1MCS8
83991. DESC_RATEVHTSS1MCS9
83992. DESC_RATEVHTSS2MCS0
83993. DESC_RATEVHTSS2MCS1
83994. DESC_RATEVHTSS2MCS2
83995. DESC_RATEVHTSS2MCS3
83996. DESC_RATEVHTSS2MCS4
83997. DESC_RATEVHTSS2MCS5
83998. DESC_RATEVHTSS2MCS6
83999. DESC_RATEVHTSS2MCS7
84000. DESC_RATEVHTSS2MCS8
84001. DESC_RATEVHTSS2MCS9
84002. DESC_RATEVHTSS3MCS0
84003. DESC_RATEVHTSS3MCS1
84004. DESC_RATEVHTSS3MCS2
84005. DESC_RATEVHTSS3MCS3
84006. DESC_RATEVHTSS3MCS4
84007. DESC_RATEVHTSS3MCS5
84008. DESC_RATEVHTSS3MCS6
84009. DESC_RATEVHTSS3MCS7
84010. DESC_RATEVHTSS3MCS8
84011. DESC_RATEVHTSS3MCS9
84012. DESC_RATEVHTSS4MCS0
84013. DESC_RATEVHTSS4MCS1
84014. DESC_RATEVHTSS4MCS2
84015. DESC_RATEVHTSS4MCS3
84016. DESC_RATEVHTSS4MCS4
84017. DESC_RATEVHTSS4MCS5
84018. DESC_RATEVHTSS4MCS6
84019. DESC_RATEVHTSS4MCS7
84020. DESC_RATEVHTSS4MCS8
84021. DESC_RATEVHTSS4MCS9
84022. DESC_RATE_11M
84023. DESC_RATE_12M
84024. DESC_RATE_18M
84025. DESC_RATE_1M
84026. DESC_RATE_24M
84027. DESC_RATE_2M
84028. DESC_RATE_36M
84029. DESC_RATE_48M
84030. DESC_RATE_54M
84031. DESC_RATE_5_5M
84032. DESC_RATE_6M
84033. DESC_RATE_9M
84034. DESC_RATE_ID_MASK
84035. DESC_RATE_ID_SHIFT
84036. DESC_RATE_MAX
84037. DESC_RATE_MCS0
84038. DESC_RATE_MCS1
84039. DESC_RATE_MCS10
84040. DESC_RATE_MCS11
84041. DESC_RATE_MCS12
84042. DESC_RATE_MCS13
84043. DESC_RATE_MCS14
84044. DESC_RATE_MCS15
84045. DESC_RATE_MCS15_SG
84046. DESC_RATE_MCS2
84047. DESC_RATE_MCS3
84048. DESC_RATE_MCS32
84049. DESC_RATE_MCS4
84050. DESC_RATE_MCS5
84051. DESC_RATE_MCS6
84052. DESC_RATE_MCS7
84053. DESC_RATE_MCS8
84054. DESC_RATE_MCS9
84055. DESC_RD_STATIC_64
84056. DESC_RD_SWAP
84057. DESC_RFC4106_BASE
84058. DESC_RFC4106_DEC_LEN
84059. DESC_RFC4106_ENC_LEN
84060. DESC_RFC4543_BASE
84061. DESC_RFC4543_DEC_LEN
84062. DESC_RFC4543_ENC_LEN
84063. DESC_RFD_RING_SIZE_MASK
84064. DESC_RFD_RING_SIZE_SHIFT
84065. DESC_RING_BUF_SZ
84066. DESC_RING_I_TO_S
84067. DESC_RING_WRAP
84068. DESC_RNG_LEN
84069. DESC_RRD_RING_SIZE_MASK
84070. DESC_RRD_RING_SIZE_SHIFT
84071. DESC_RSA_PRIV_F1_LEN
84072. DESC_RSA_PRIV_F2_LEN
84073. DESC_RSA_PRIV_F3_LEN
84074. DESC_RSA_PUB_LEN
84075. DESC_SG
84076. DESC_SIZE
84077. DESC_SIZE_MASK
84078. DESC_SKCIPHER_BASE
84079. DESC_SKCIPHER_DEC_LEN
84080. DESC_SKCIPHER_ENC_LEN
84081. DESC_SKIP_LEN
84082. DESC_SOP
84083. DESC_STATUS_MASK
84084. DESC_STATUS_SHIFT
84085. DESC_SUBMITTED
84086. DESC_SZ
84087. DESC_TPD_RING_SIZE_MASK
84088. DESC_TPD_RING_SIZE_SHIFT
84089. DESC_TSS
84090. DESC_TYPE
84091. DESC_TYPE_CODE_DATA
84092. DESC_TYPE_HOST
84093. DESC_TYPE_MASK
84094. DESC_TYPE_PAGE
84095. DESC_TYPE_SHIFT
84096. DESC_TYPE_SKB
84097. DESC_TYPE_TEARD
84098. DESC_TYPE_USB
84099. DESC_VALID
84100. DESC_VER_1
84101. DESC_VER_2
84102. DESC_VER_3
84103. DESC_VLD_BUSY
84104. DESC_VLD_FREE
84105. DESC_WAITING
84106. DESC_WRAP
84107. DESC_WR_RD_ENA
84108. DESC_WR_SWAP
84109. DESELECT
84110. DESELECT_CALDAC_BIT
84111. DESELECT_CARD
84112. DESELECT_REF_DAC_BIT
84113. DESEQC2_INT
84114. DESIGNER
84115. DESIGN_CAPACITY
84116. DESIRED_PERF
84117. DESKTOP_EFX_FILE
84118. DESR
84119. DEST
84120. DESTID_DPD
84121. DESTID_SCC
84122. DESTROY_AH
84123. DESTROY_CQ
84124. DESTROY_DISK
84125. DESTROY_IN_PROGRESS
84126. DESTROY_QP
84127. DESTROY_SRQ
84128. DEST_BUFFER
84129. DEST_ID
84130. DEST_MAP_MASK
84131. DEST_MAP_SHIFT
84132. DEST_NUM_RESOURCES
84133. DEST_ONE
84134. DEST_PORT_DROP
84135. DEST_PORT_LOOPBACK
84136. DEST_PORT_PHY
84137. DEST_PORT_PHY_LOOPBACK
84138. DEST_Q_SIZE
84139. DEST_REG_MASK
84140. DEST_REG_SHIFT
84141. DEST_RM
84142. DEST_SAS_ADDR
84143. DEST_SHIFT
84144. DEST_SPEC_PARAMS_ID_INDEX
84145. DEST_SPEC_PARAMS_PROTOCOL_INDEX
84146. DEST_X
84147. DEST_Y
84148. DEST_ZERO
84149. DES_BLOCK_MASK
84150. DES_BLOCK_SIZE
84151. DES_BLOCK_WORDS
84152. DES_EXPKEY_WORDS
84153. DES_IIP
84154. DES_IP
84155. DES_KEXPAND
84156. DES_KEY_SIZE
84157. DES_PC2
84158. DES_REG_CTRL
84159. DES_REG_CTRL_CBC
84160. DES_REG_CTRL_DIRECTION
84161. DES_REG_CTRL_INPUT_READY
84162. DES_REG_CTRL_OUTPUT_READY
84163. DES_REG_CTRL_TDES
84164. DES_REG_DATA_N
84165. DES_REG_IRQ_DATA_IN
84166. DES_REG_IRQ_DATA_OUT
84167. DES_REG_IRQ_ENABLE
84168. DES_REG_IRQ_STATUS
84169. DES_REG_IV
84170. DES_REG_KEY
84171. DES_REG_LENGTH_N
84172. DES_REG_MASK
84173. DES_REG_REV
84174. DES_ROUND
84175. DES_SEL_SHIFT
84176. DES_and_HASH
84177. DES_to_HASH
84178. DES_to_HASH_and_DOUT
84179. DETACHED
84180. DETACH_ALL_REQ
84181. DETACH_GROUP
84182. DETACH_MCAST
84183. DETAILED_TIMING_DESCRIPTIONS_START
84184. DETAILED_TIMING_DESCRIPTION_1
84185. DETAILED_TIMING_DESCRIPTION_2
84186. DETAILED_TIMING_DESCRIPTION_3
84187. DETAILED_TIMING_DESCRIPTION_4
84188. DETAILED_TIMING_DESCRIPTION_SIZE
84189. DETECT
84190. DETECTED_AUI
84191. DETECTED_BNC
84192. DETECTED_NONE
84193. DETECTED_RJ45F
84194. DETECTED_RJ45H
84195. DETECTION_COMPLETE_EVENT
84196. DETECTION_COMPLETE_INT_DISABLE
84197. DETECTION_METHOD
84198. DETECT_4_WIRE_MODE
84199. DETECT_5V_A
84200. DETECT_5V_B
84201. DETECT_5V_SEL
84202. DETECT_FALL
84203. DETECT_HPD
84204. DETECT_MODE
84205. DETECT_RAM
84206. DETECT_REASON_BOOT
84207. DETECT_REASON_HPD
84208. DETECT_REASON_HPDRX
84209. DETECT_RISE
84210. DETECT_SIGNAL
84211. DETECT_STATUS
84212. DETECT_UTIL
84213. DETECT_VGA_CLASS_ONLY
84214. DETH_PRN
84215. DETH_SQP_MASK
84216. DETILE_ARIDR_MODE_MASK
84217. DETILE_ARID_ALL
84218. DETILE_ARID_BYP_BUT_ARIDR
84219. DETILE_ARID_IN_ARIDR
84220. DETILE_ARID_IN_ARIDR2
84221. DETILE_BUFFER_PACKER_ENABLE
84222. DETILE_BUFFER_PACKER_IS_DISABLE
84223. DETILE_BUFFER_PACKER_IS_ENABLE
84224. DET_CTRL
84225. DET_MEM_POWER_LIGHT_SLEEP_MODE_1
84226. DET_MEM_POWER_LIGHT_SLEEP_MODE_2
84227. DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF
84228. DET_MEM_PWR_LIGHT_SLEEP_MODE
84229. DET_STA
84230. DET_STATUS
84231. DET_STAT_CDP
84232. DET_STAT_DCP
84233. DET_STAT_MASK
84234. DET_STAT_SDP
84235. DET_STAT_SHIFT
84236. DEUC
84237. DEUIS
84238. DEV
84239. DEV0BASE
84240. DEV0C
84241. DEV0MASK
84242. DEV0T
84243. DEV0_CFG1_ECC_DISABLE
84244. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84245. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84246. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84247. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84248. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84249. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84250. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84251. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84252. DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84253. DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84254. DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84255. DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84256. DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84257. DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84258. DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84259. DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84260. DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84261. DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84262. DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84263. DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84264. DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84265. DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84266. DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84267. DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84268. DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84269. DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84270. DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84271. DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK
84272. DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK
84273. DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT
84274. DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK
84275. DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK
84276. DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84277. DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84278. DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84279. DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84280. DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84281. DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84282. DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84283. DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK
84284. DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK
84285. DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84286. DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84287. DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84288. DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84289. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK
84290. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK
84291. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT
84292. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK
84293. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK
84294. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT
84295. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK
84296. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK
84297. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT
84298. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK
84299. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT
84300. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK
84301. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK
84302. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT
84303. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK
84304. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK
84305. DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT
84306. DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK
84307. DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK
84308. DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT
84309. DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK
84310. DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK
84311. DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT
84312. DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK
84313. DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK
84314. DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT
84315. DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK
84316. DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK
84317. DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT
84318. DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK
84319. DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK
84320. DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT
84321. DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK
84322. DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK
84323. DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT
84324. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84325. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84326. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84327. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84328. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84329. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84330. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84331. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84332. DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84333. DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84334. DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84335. DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84336. DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84337. DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84338. DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84339. DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84340. DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84341. DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84342. DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84343. DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84344. DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84345. DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84346. DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84347. DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84348. DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84349. DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84350. DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84351. DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK
84352. DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK
84353. DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84354. DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84355. DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84356. DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84357. DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84358. DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84359. DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84360. DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK
84361. DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK
84362. DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84363. DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84364. DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84365. DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84366. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84367. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84368. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84369. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84370. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84371. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84372. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84373. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84374. DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84375. DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84376. DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84377. DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84378. DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84379. DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84380. DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84381. DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84382. DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84383. DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84384. DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84385. DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84386. DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84387. DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84388. DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84389. DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84390. DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84391. DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84392. DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84393. DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK
84394. DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK
84395. DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84396. DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84397. DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84398. DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84399. DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84400. DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84401. DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84402. DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK
84403. DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK
84404. DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84405. DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84406. DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84407. DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84408. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84409. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84410. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84411. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84412. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84413. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84414. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84415. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84416. DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84417. DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84418. DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84419. DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84420. DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84421. DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84422. DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84423. DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84424. DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84425. DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84426. DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84427. DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84428. DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84429. DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84430. DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84431. DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84432. DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84433. DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84434. DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84435. DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK
84436. DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK
84437. DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84438. DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84439. DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84440. DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84441. DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84442. DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84443. DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84444. DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK
84445. DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK
84446. DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84447. DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84448. DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84449. DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84450. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84451. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84452. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84453. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84454. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84455. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84456. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84457. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84458. DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84459. DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84460. DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84461. DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84462. DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84463. DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84464. DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84465. DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84466. DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84467. DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84468. DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84469. DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84470. DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84471. DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84472. DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84473. DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84474. DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84475. DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84476. DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84477. DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK
84478. DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK
84479. DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84480. DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84481. DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84482. DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84483. DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84484. DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84485. DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84486. DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK
84487. DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK
84488. DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84489. DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84490. DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84491. DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84492. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84493. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84494. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84495. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84496. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84497. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84498. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84499. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84500. DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84501. DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84502. DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84503. DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84504. DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84505. DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84506. DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84507. DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84508. DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84509. DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84510. DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84511. DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84512. DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84513. DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84514. DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84515. DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84516. DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84517. DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84518. DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84519. DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK
84520. DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK
84521. DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84522. DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84523. DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84524. DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84525. DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84526. DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84527. DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84528. DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK
84529. DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK
84530. DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84531. DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84532. DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84533. DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84534. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84535. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84536. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84537. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84538. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84539. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84540. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84541. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84542. DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84543. DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84544. DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84545. DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84546. DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84547. DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84548. DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84549. DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84550. DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84551. DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84552. DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84553. DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84554. DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84555. DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84556. DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84557. DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84558. DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84559. DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84560. DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84561. DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK
84562. DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK
84563. DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84564. DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84565. DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84566. DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84567. DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84568. DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84569. DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84570. DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK
84571. DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK
84572. DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84573. DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84574. DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84575. DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84576. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84577. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK
84578. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84579. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84580. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84581. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84582. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84583. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK
84584. DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84585. DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84586. DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK
84587. DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84588. DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84589. DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK
84590. DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84591. DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84592. DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK
84593. DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84594. DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84595. DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK
84596. DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84597. DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84598. DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK
84599. DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84600. DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84601. DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK
84602. DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84603. DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK
84604. DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK
84605. DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84606. DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84607. DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK
84608. DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84609. DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84610. DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK
84611. DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84612. DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK
84613. DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK
84614. DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84615. DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84616. DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK
84617. DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84618. DEV1BASE
84619. DEV1C
84620. DEV1MASK
84621. DEV1TC
84622. DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84623. DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84624. DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84625. DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84626. DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84627. DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84628. DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84629. DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84630. DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84631. DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84632. DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84633. DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84634. DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84635. DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84636. DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84637. DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84638. DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84639. DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84640. DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK
84641. DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84642. DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84643. DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84644. DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84645. DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84646. DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK
84647. DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84648. DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84649. DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84650. DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84651. DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84652. DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84653. DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84654. DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84655. DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84656. DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84657. DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84658. DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84659. DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84660. DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84661. DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84662. DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84663. DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84664. DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84665. DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84666. DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84667. DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84668. DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK
84669. DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84670. DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84671. DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84672. DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84673. DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84674. DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK
84675. DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84676. DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84677. DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84678. DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84679. DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84680. DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84681. DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84682. DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84683. DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84684. DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84685. DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84686. DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84687. DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84688. DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84689. DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84690. DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84691. DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84692. DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84693. DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84694. DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84695. DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84696. DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK
84697. DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84698. DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84699. DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84700. DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84701. DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84702. DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK
84703. DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84704. DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84705. DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84706. DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84707. DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84708. DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84709. DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84710. DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84711. DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84712. DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84713. DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84714. DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84715. DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84716. DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84717. DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84718. DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84719. DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84720. DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84721. DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84722. DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84723. DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84724. DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK
84725. DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84726. DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84727. DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84728. DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84729. DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84730. DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK
84731. DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84732. DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84733. DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84734. DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84735. DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84736. DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84737. DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84738. DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84739. DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84740. DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84741. DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84742. DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84743. DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84744. DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84745. DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84746. DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84747. DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84748. DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84749. DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84750. DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84751. DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84752. DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK
84753. DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84754. DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84755. DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84756. DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84757. DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84758. DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK
84759. DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84760. DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84761. DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84762. DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84763. DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84764. DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84765. DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84766. DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84767. DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84768. DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84769. DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84770. DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84771. DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84772. DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84773. DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84774. DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84775. DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84776. DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84777. DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84778. DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84779. DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84780. DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK
84781. DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84782. DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84783. DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84784. DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84785. DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84786. DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK
84787. DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84788. DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84789. DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84790. DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84791. DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84792. DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84793. DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84794. DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84795. DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84796. DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84797. DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84798. DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84799. DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84800. DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84801. DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84802. DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84803. DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84804. DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84805. DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84806. DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84807. DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84808. DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK
84809. DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84810. DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84811. DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84812. DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84813. DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84814. DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK
84815. DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84816. DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84817. DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84818. DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK
84819. DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT
84820. DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84821. DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84822. DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK
84823. DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84824. DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK
84825. DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT
84826. DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK
84827. DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84828. DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK
84829. DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT
84830. DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK
84831. DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT
84832. DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK
84833. DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT
84834. DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK
84835. DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT
84836. DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK
84837. DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT
84838. DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK
84839. DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT
84840. DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK
84841. DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT
84842. DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK
84843. DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT
84844. DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK
84845. DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT
84846. DEV2BASE
84847. DEV2C
84848. DEV2MASK
84849. DEV2TC
84850. DEV3BASE
84851. DEV3C
84852. DEV3MASK
84853. DEV3TC
84854. DEVADD0
84855. DEVADD1
84856. DEVADD2
84857. DEVADD3
84858. DEVADD4
84859. DEVADD5
84860. DEVADD6
84861. DEVADD7
84862. DEVADD8
84863. DEVADD9
84864. DEVADDA
84865. DEVCD_TIMEOUT
84866. DEVCG_ACC_MASK
84867. DEVCG_ACC_MKNOD
84868. DEVCG_ACC_READ
84869. DEVCG_ACC_WRITE
84870. DEVCG_ALLOW
84871. DEVCG_DEFAULT_ALLOW
84872. DEVCG_DEFAULT_DENY
84873. DEVCG_DEFAULT_NONE
84874. DEVCG_DENY
84875. DEVCG_DEV_ALL
84876. DEVCG_DEV_BLOCK
84877. DEVCG_DEV_CHAR
84878. DEVCG_LIST
84879. DEVCLOCK
84880. DEVCMD2_DESC_SIZE
84881. DEVCMD2_FNORESULT
84882. DEVCMD2_RESULTS_SIZE_MAX
84883. DEVCMD2_RING_SIZE
84884. DEVCMD_TIMEOUT
84885. DEVCNT
84886. DEVCON0_AHLD
84887. DEVCON0_AKL
84888. DEVCON0_CMP
84889. DEVCON0_DDMA
84890. DEVCON0_EXW
84891. DEVCON0_MTM
84892. DEVCON0_ROT
84893. DEVCON0_RQL
84894. DEVCON1_BHLD
84895. DEVCON1_WEV
84896. DEVCONFIG
84897. DEVCONFIG1
84898. DEVCONF_ACCEPT_DAD
84899. DEVCONF_ACCEPT_RA
84900. DEVCONF_ACCEPT_RA_DEFRTR
84901. DEVCONF_ACCEPT_RA_FROM_LOCAL
84902. DEVCONF_ACCEPT_RA_MIN_HOP_LIMIT
84903. DEVCONF_ACCEPT_RA_MTU
84904. DEVCONF_ACCEPT_RA_PINFO
84905. DEVCONF_ACCEPT_RA_RTR_PREF
84906. DEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN
84907. DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN
84908. DEVCONF_ACCEPT_REDIRECTS
84909. DEVCONF_ACCEPT_SOURCE_ROUTE
84910. DEVCONF_ADDR_GEN_MODE
84911. DEVCONF_AUTOCONF
84912. DEVCONF_DAD_TRANSMITS
84913. DEVCONF_DISABLE_IPV6
84914. DEVCONF_DISABLE_POLICY
84915. DEVCONF_DROP_UNICAST_IN_L2_MULTICAST
84916. DEVCONF_DROP_UNSOLICITED_NA
84917. DEVCONF_ENHANCED_DAD
84918. DEVCONF_FORCE_MLD_VERSION
84919. DEVCONF_FORCE_TLLAO
84920. DEVCONF_FORWARDING
84921. DEVCONF_HOPLIMIT
84922. DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN
84923. DEVCONF_KEEP_ADDR_ON_DOWN
84924. DEVCONF_MAX
84925. DEVCONF_MAX_ADDRESSES
84926. DEVCONF_MAX_DESYNC_FACTOR
84927. DEVCONF_MC_FORWARDING
84928. DEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL
84929. DEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL
84930. DEVCONF_MTU6
84931. DEVCONF_NDISC_NOTIFY
84932. DEVCONF_NDISC_TCLASS
84933. DEVCONF_OPTIMISTIC_DAD
84934. DEVCONF_PROXY_NDP
84935. DEVCONF_REGEN_MAX_RETRY
84936. DEVCONF_RTR_PROBE_INTERVAL
84937. DEVCONF_RTR_SOLICITS
84938. DEVCONF_RTR_SOLICIT_DELAY
84939. DEVCONF_RTR_SOLICIT_INTERVAL
84940. DEVCONF_RTR_SOLICIT_MAX_INTERVAL
84941. DEVCONF_SEG6_ENABLED
84942. DEVCONF_SEG6_REQUIRE_HMAC
84943. DEVCONF_STABLE_SECRET
84944. DEVCONF_SUPPRESS_FRAG_NDISC
84945. DEVCONF_TEMP_PREFERED_LFT
84946. DEVCONF_TEMP_VALID_LFT
84947. DEVCONF_USE_OIF_ADDRS_ONLY
84948. DEVCONF_USE_OPTIMISTIC
84949. DEVCONF_USE_TEMPADDR
84950. DEVCOUNT
84951. DEVCPU_GCB_CHIP_REGS_CHIP_ID
84952. DEVCTRL2_IT_POL_MASK
84953. DEVCTRL2_IT_POL_SHIFT
84954. DEVCTRL2_PWON_LP_OFF_MASK
84955. DEVCTRL2_PWON_LP_OFF_SHIFT
84956. DEVCTRL2_PWON_LP_RST_MASK
84957. DEVCTRL2_PWON_LP_RST_SHIFT
84958. DEVCTRL2_SLEEPSIG_POL_MASK
84959. DEVCTRL2_SLEEPSIG_POL_SHIFT
84960. DEVCTRL2_TSLOT_LENGTH_MASK
84961. DEVCTRL2_TSLOT_LENGTH_SHIFT
84962. DEVCTRL_CK32K_CTRL_MASK
84963. DEVCTRL_CK32K_CTRL_SHIFT
84964. DEVCTRL_DEV_OFF_MASK
84965. DEVCTRL_DEV_OFF_RST_MASK
84966. DEVCTRL_DEV_OFF_RST_SHIFT
84967. DEVCTRL_DEV_OFF_SHIFT
84968. DEVCTRL_DEV_ON_MASK
84969. DEVCTRL_DEV_ON_SHIFT
84970. DEVCTRL_DEV_SLP_MASK
84971. DEVCTRL_DEV_SLP_SHIFT
84972. DEVCTRL_EPR
84973. DEVCTRL_IPP
84974. DEVCTRL_MPM
84975. DEVCTRL_PADDR
84976. DEVCTRL_PADDR_SHIFT
84977. DEVCTRL_PFE
84978. DEVCTRL_PMCE
84979. DEVCTRL_PME
84980. DEVCTRL_PWR_OFF_MASK
84981. DEVCTRL_PWR_OFF_SHIFT
84982. DEVCTRL_RTC_PWDN_MASK
84983. DEVCTRL_RTC_PWDN_SHIFT
84984. DEVCTRL_SR_CTL_I2C_SEL_MASK
84985. DEVCTRL_SR_CTL_I2C_SEL_SHIFT
84986. DEVCTXBASE
84987. DEVCTXDOMAIN0
84988. DEVCTXDOMAIN1
84989. DEVEN
84990. DEVEN_MCHBAR_EN
84991. DEVEXCEPT_MASK
84992. DEVFL_EXT
84993. DEVFL_FREED
84994. DEVFL_FREEING
84995. DEVFL_GDALLOC
84996. DEVFL_GD_NOW
84997. DEVFL_KICKME
84998. DEVFL_NEWSIZE
84999. DEVFL_TKILL
85000. DEVFL_UP
85001. DEVFN_PCIX_BRIDGE_NORTH_A
85002. DEVFN_PCIX_BRIDGE_NORTH_B
85003. DEVFN_PCIX_BRIDGE_SOUTH_A
85004. DEVFN_PCIX_BRIDGE_SOUTH_B
85005. DEVFREQ_FLAG_LEAST_UPPER_BOUND
85006. DEVFREQ_GOV_INTERVAL
85007. DEVFREQ_GOV_PASSIVE
85008. DEVFREQ_GOV_PERFORMANCE
85009. DEVFREQ_GOV_POWERSAVE
85010. DEVFREQ_GOV_RESUME
85011. DEVFREQ_GOV_SIMPLE_ONDEMAND
85012. DEVFREQ_GOV_START
85013. DEVFREQ_GOV_STOP
85014. DEVFREQ_GOV_SUSPEND
85015. DEVFREQ_GOV_USERSPACE
85016. DEVFREQ_MAX_FREQ
85017. DEVFREQ_MIN_FREQ
85018. DEVFREQ_NAME_LEN
85019. DEVFREQ_POSTCHANGE
85020. DEVFREQ_PRECHANGE
85021. DEVFREQ_TRANSITION_NOTIFIER
85022. DEVF_ANY_VXRES
85023. DEVF_CROSS4MB
85024. DEVF_CRTC2
85025. DEVF_DUALHEAD
85026. DEVF_G100
85027. DEVF_G200
85028. DEVF_G2CORE
85029. DEVF_G400
85030. DEVF_G450
85031. DEVF_G450DAC
85032. DEVF_G550
85033. DEVF_GCORE
85034. DEVF_MAVEN_CAPABLE
85035. DEVF_PANELLINK_CAPABLE
85036. DEVF_SRCORG
85037. DEVF_SUPPORT32MB
85038. DEVF_SWAPS
85039. DEVF_TEXT16B
85040. DEVF_TEXT4B
85041. DEVF_VIDEO64BIT
85042. DEVHASH
85043. DEVICE
85044. DEVICEADDR_USBADR
85045. DEVICEADDR_USBADRA
85046. DEVICEENABLE
85047. DEVICEID
85048. DEVICEIDREG
85049. DEVICEID_MFGID
85050. DEVICEID_PN
85051. DEVICEID_RSA
85052. DEVICES_CONNECTED
85053. DEVICES_CONNECTED__VALUE
85054. DEVICE_5702_3_4_FAMILY
85055. DEVICE_5705_FAMILY
85056. DEVICE_5706_FAMILY
85057. DEVICE_5714_FAMILY
85058. DEVICE_ACCESS
85059. DEVICE_ADDED_WO_CNT
85060. DEVICE_ADDED_W_CNT
85061. DEVICE_ADDR
85062. DEVICE_ADDR_TABLE_ADDR
85063. DEVICE_ADDR_TABLE_DEPTH
85064. DEVICE_ADDR_TABLE_POINTER
85065. DEVICE_ALI
85066. DEVICE_ALS300
85067. DEVICE_ALS300_PLUS
85068. DEVICE_ANALOG
85069. DEVICE_ASPEN_FAMILY
85070. DEVICE_ASPEN_PLUS_FAMILY
85071. DEVICE_ATTR
85072. DEVICE_ATTR_IGNORE_LOCKDEP
85073. DEVICE_ATTR_LEGACY
85074. DEVICE_ATTR_PREALLOC
85075. DEVICE_ATTR_RO
85076. DEVICE_ATTR_RW
85077. DEVICE_ATTR_SYS_INFO_STR
85078. DEVICE_ATTR_WO
85079. DEVICE_BASE
85080. DEVICE_BOOL_ATTR
85081. DEVICE_BTNIMG_ATTR
85082. DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
85083. DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK
85084. DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
85085. DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
85086. DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK
85087. DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
85088. DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
85089. DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK
85090. DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
85091. DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
85092. DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK
85093. DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
85094. DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
85095. DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK
85096. DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
85097. DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
85098. DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK
85099. DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
85100. DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
85101. DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK
85102. DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
85103. DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
85104. DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK
85105. DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
85106. DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
85107. DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK
85108. DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
85109. DEVICE_CAP2__LTR_SUPPORTED_MASK
85110. DEVICE_CAP2__LTR_SUPPORTED__MASK
85111. DEVICE_CAP2__LTR_SUPPORTED__SHIFT
85112. DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
85113. DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK
85114. DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
85115. DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
85116. DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK
85117. DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
85118. DEVICE_CAP2__OBFF_SUPPORTED_MASK
85119. DEVICE_CAP2__OBFF_SUPPORTED__MASK
85120. DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
85121. DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
85122. DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK
85123. DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
85124. DEVICE_CAP_MAX_PAYLOAD_MASK
85125. DEVICE_CAP_MAX_PAYLOAD_SHIFT
85126. DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
85127. DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK
85128. DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
85129. DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
85130. DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK
85131. DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
85132. DEVICE_CAP__EXTENDED_TAG_MASK
85133. DEVICE_CAP__EXTENDED_TAG__MASK
85134. DEVICE_CAP__EXTENDED_TAG__SHIFT
85135. DEVICE_CAP__FLR_CAPABLE_MASK
85136. DEVICE_CAP__FLR_CAPABLE__MASK
85137. DEVICE_CAP__FLR_CAPABLE__SHIFT
85138. DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
85139. DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK
85140. DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
85141. DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
85142. DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK
85143. DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
85144. DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
85145. DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK
85146. DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
85147. DEVICE_CAP__PHANTOM_FUNC_MASK
85148. DEVICE_CAP__PHANTOM_FUNC__MASK
85149. DEVICE_CAP__PHANTOM_FUNC__SHIFT
85150. DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
85151. DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK
85152. DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
85153. DEVICE_CFG1
85154. DEVICE_CFG2
85155. DEVICE_CFG_12BIT_DVOB
85156. DEVICE_CFG_12BIT_DVOC
85157. DEVICE_CFG_24BIT_DVOBC
85158. DEVICE_CFG_24BIT_DVOCB
85159. DEVICE_CFG_DUAL_DVOB
85160. DEVICE_CFG_DUAL_DVOBC
85161. DEVICE_CFG_DUAL_DVOC
85162. DEVICE_CFG_DUAL_LINK_DVOBC
85163. DEVICE_CFG_DUAL_LINK_DVOCB
85164. DEVICE_CFG_NONE
85165. DEVICE_CHANGED
85166. DEVICE_CHANNEL
85167. DEVICE_CILAI_FAMILY
85168. DEVICE_CLASS
85169. DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
85170. DEVICE_CNTL2__ARI_FORWARDING_EN__MASK
85171. DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
85172. DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
85173. DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK
85174. DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
85175. DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
85176. DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK
85177. DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
85178. DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
85179. DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK
85180. DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
85181. DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
85182. DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK
85183. DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
85184. DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
85185. DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK
85186. DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
85187. DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
85188. DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK
85189. DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
85190. DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
85191. DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK
85192. DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
85193. DEVICE_CNTL2__LTR_EN_MASK
85194. DEVICE_CNTL2__LTR_EN__MASK
85195. DEVICE_CNTL2__LTR_EN__SHIFT
85196. DEVICE_CNTL2__OBFF_EN_MASK
85197. DEVICE_CNTL2__OBFF_EN__MASK
85198. DEVICE_CNTL2__OBFF_EN__SHIFT
85199. DEVICE_CNTL__AUX_POWER_PM_EN_MASK
85200. DEVICE_CNTL__AUX_POWER_PM_EN__MASK
85201. DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
85202. DEVICE_CNTL__CORR_ERR_EN_MASK
85203. DEVICE_CNTL__CORR_ERR_EN__MASK
85204. DEVICE_CNTL__CORR_ERR_EN__SHIFT
85205. DEVICE_CNTL__EXTENDED_TAG_EN_MASK
85206. DEVICE_CNTL__EXTENDED_TAG_EN__MASK
85207. DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
85208. DEVICE_CNTL__FATAL_ERR_EN_MASK
85209. DEVICE_CNTL__FATAL_ERR_EN__MASK
85210. DEVICE_CNTL__FATAL_ERR_EN__SHIFT
85211. DEVICE_CNTL__INITIATE_FLR_MASK
85212. DEVICE_CNTL__INITIATE_FLR__MASK
85213. DEVICE_CNTL__INITIATE_FLR__SHIFT
85214. DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
85215. DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK
85216. DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
85217. DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
85218. DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK
85219. DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
85220. DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
85221. DEVICE_CNTL__NON_FATAL_ERR_EN__MASK
85222. DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
85223. DEVICE_CNTL__NO_SNOOP_EN_MASK
85224. DEVICE_CNTL__NO_SNOOP_EN__MASK
85225. DEVICE_CNTL__NO_SNOOP_EN__SHIFT
85226. DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
85227. DEVICE_CNTL__PHANTOM_FUNC_EN__MASK
85228. DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
85229. DEVICE_CNTL__RELAXED_ORD_EN_MASK
85230. DEVICE_CNTL__RELAXED_ORD_EN__MASK
85231. DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
85232. DEVICE_CNTL__USR_REPORT_EN_MASK
85233. DEVICE_CNTL__USR_REPORT_EN__MASK
85234. DEVICE_CNTL__USR_REPORT_EN__SHIFT
85235. DEVICE_CONFIG
85236. DEVICE_CONFIG_CONTAINER
85237. DEVICE_CONFIG_PARTITION
85238. DEVICE_COTOPAXI_FAMILY
85239. DEVICE_COUNT_COMPATIBLE
85240. DEVICE_COUNT_RESOURCE
85241. DEVICE_CRT
85242. DEVICE_CTRL
85243. DEVICE_CTRL_EXTENDED
85244. DEVICE_CTRL_MAXRRS_MIN
85245. DEVICE_CTRL_MAX_PAYLOAD_MASK
85246. DEVICE_CTRL_MAX_PAYLOAD_SHIFT
85247. DEVICE_CTRL_MAX_RREQ_SZ_MASK
85248. DEVICE_CTRL_MAX_RREQ_SZ_SHIFT
85249. DEVICE_CUMULUS_FAMILY
85250. DEVICE_D1_ENTRY
85251. DEVICE_D2_ENTRY
85252. DEVICE_D3_ENTRY
85253. DEVICE_DEF
85254. DEVICE_DESC_PARAM_ACTVE_ICC_LVL
85255. DEVICE_DESC_PARAM_BKOP_TERM_LT
85256. DEVICE_DESC_PARAM_BOOT_ENBL
85257. DEVICE_DESC_PARAM_DESC_ACCSS_ENBL
85258. DEVICE_DESC_PARAM_DEVICE_CLASS
85259. DEVICE_DESC_PARAM_DEVICE_SUB_CLASS
85260. DEVICE_DESC_PARAM_DEVICE_TYPE
85261. DEVICE_DESC_PARAM_DEV_VER
85262. DEVICE_DESC_PARAM_FFU_TMT
85263. DEVICE_DESC_PARAM_FRQ_RTC
85264. DEVICE_DESC_PARAM_HIGH_PR_LUN
85265. DEVICE_DESC_PARAM_INIT_PWR_MODE
85266. DEVICE_DESC_PARAM_LEN
85267. DEVICE_DESC_PARAM_MANF_DATE
85268. DEVICE_DESC_PARAM_MANF_ID
85269. DEVICE_DESC_PARAM_MANF_NAME
85270. DEVICE_DESC_PARAM_NUM_LU
85271. DEVICE_DESC_PARAM_NUM_SEC_WPA
85272. DEVICE_DESC_PARAM_NUM_WLU
85273. DEVICE_DESC_PARAM_OEM_ID
85274. DEVICE_DESC_PARAM_PRDCT_NAME
85275. DEVICE_DESC_PARAM_PRDCT_REV
85276. DEVICE_DESC_PARAM_PRTCL
85277. DEVICE_DESC_PARAM_PSA_MAX_DATA
85278. DEVICE_DESC_PARAM_PSA_TMT
85279. DEVICE_DESC_PARAM_Q_DPTH
85280. DEVICE_DESC_PARAM_RTT_CAP
85281. DEVICE_DESC_PARAM_SEC_LU
85282. DEVICE_DESC_PARAM_SEC_RMV_TYPE
85283. DEVICE_DESC_PARAM_SN
85284. DEVICE_DESC_PARAM_SPEC_VER
85285. DEVICE_DESC_PARAM_TYPE
85286. DEVICE_DESC_PARAM_UD_LEN
85287. DEVICE_DESC_PARAM_UD_OFFSET
85288. DEVICE_DESC_PARAM_UFS_FEAT
85289. DEVICE_DIGITAL
85290. DEVICE_DISABLE
85291. DEVICE_DVI
85292. DEVICE_EISA
85293. DEVICE_EKR_ATTR_GROUP
85294. DEVICE_EMACSL_RESET_POLL_COUNT
85295. DEVICE_ENABLE
85296. DEVICE_ERROR
85297. DEVICE_ERROR_INDICATOR
85298. DEVICE_ETHTOOL_IOCTL_SUPPORT
85299. DEVICE_FATAL_ERROR
85300. DEVICE_FLAGS_DISCONNECTED
85301. DEVICE_FLAGS_UNPLUG
85302. DEVICE_FORMAT_ID
85303. DEVICE_FULL_DRV_NAM
85304. DEVICE_G1K
85305. DEVICE_HP
85306. DEVICE_HWI
85307. DEVICE_ID
85308. DEVICE_ID_56301
85309. DEVICE_ID_56361
85310. DEVICE_ID_ALI5451
85311. DEVICE_ID_ANY
85312. DEVICE_ID_CZ_9870
85313. DEVICE_ID_CZ_9874
85314. DEVICE_ID_CZ_9875
85315. DEVICE_ID_CZ_9876
85316. DEVICE_ID_CZ_9877
85317. DEVICE_ID_DEVICE_ID_MASK
85318. DEVICE_ID_FROM_USB_PRODUCT_ID
85319. DEVICE_ID_KALINDI_9834
85320. DEVICE_ID_MASK
85321. DEVICE_ID_OFFSET
85322. DEVICE_ID_PANEL_BACK
85323. DEVICE_ID_REG
85324. DEVICE_ID_RENOIR_1636
85325. DEVICE_ID_REVISION_ID_MASK
85326. DEVICE_ID_SHIFT
85327. DEVICE_ID_SKYLAKE_OR_LATER
85328. DEVICE_ID_TEMASH_9839
85329. DEVICE_ID_TEMASH_983D
85330. DEVICE_ID_VI_ICELAND_M_6900
85331. DEVICE_ID_VI_ICELAND_M_6901
85332. DEVICE_ID_VI_ICELAND_M_6902
85333. DEVICE_ID_VI_ICELAND_M_6903
85334. DEVICE_ID_WM0010
85335. DEVICE_ID__DEVICE_ID_MASK
85336. DEVICE_ID__DEVICE_ID__MASK
85337. DEVICE_ID__DEVICE_ID__SHIFT
85338. DEVICE_ID__VALUE
85339. DEVICE_INIT
85340. DEVICE_INIT_COLD
85341. DEVICE_INIT_DXPL
85342. DEVICE_INIT_RESET
85343. DEVICE_INSTALLER
85344. DEVICE_INTEL
85345. DEVICE_INTEL_ICH4
85346. DEVICE_INT_ATTR
85347. DEVICE_IS_FLEXONENAND
85348. DEVICE_IS_TPM2
85349. DEVICE_LABEL_DSM
85350. DEVICE_LCD
85351. DEVICE_LED_SELECT_ATTR
85352. DEVICE_LO
85353. DEVICE_LOCK_ADDR
85354. DEVICE_LOGAN_5725
85355. DEVICE_LOGAN_5762
85356. DEVICE_LOGAN_57767
85357. DEVICE_LOGAN_57787
85358. DEVICE_LOGAN_FAMILY
85359. DEVICE_LUMINANCE_ATTR
85360. DEVICE_MAIN_AREA_SIZE
85361. DEVICE_MAIN_AREA_SIZE__VALUE
85362. DEVICE_MASK
85363. DEVICE_MIC1
85364. DEVICE_MIC2
85365. DEVICE_MODE_ATSC
85366. DEVICE_MODE_CMMB
85367. DEVICE_MODE_DAB_TDMB
85368. DEVICE_MODE_DAB_TDMB_DABIP
85369. DEVICE_MODE_DVBH
85370. DEVICE_MODE_DVBT
85371. DEVICE_MODE_DVBT_BDA
85372. DEVICE_MODE_FM_RADIO
85373. DEVICE_MODE_FM_RADIO_BDA
85374. DEVICE_MODE_ISDBT
85375. DEVICE_MODE_ISDBT_BDA
85376. DEVICE_MODE_MAX
85377. DEVICE_MODE_NONE
85378. DEVICE_MODE_RAW_TUNER
85379. DEVICE_MSG_WORK_MODE
85380. DEVICE_N
85381. DEVICE_NAME
85382. DEVICE_NAME_PEGA
85383. DEVICE_NAME_USER
85384. DEVICE_NFORCE
85385. DEVICE_NOT_FOUND
85386. DEVICE_NUM
85387. DEVICE_N_ADDRESS
85388. DEVICE_N_ENDPOINT_N_CTL_REG
85389. DEVICE_N_ENDPOINT_N_STAT_REG
85390. DEVICE_N_IRQ_EN_REG
85391. DEVICE_N_PORT_SEL
85392. DEVICE_OFF
85393. DEVICE_OFFLINE
85394. DEVICE_ON
85395. DEVICE_ONLINE
85396. DEVICE_PAIRED_PARAM_EQUAD_ID_LSB
85397. DEVICE_PAIRED_PARAM_EQUAD_ID_MSB
85398. DEVICE_PAIRED_PARAM_SPFUNCTION
85399. DEVICE_PAIRED_RF_REPORT_TYPE
85400. DEVICE_PARAM
85401. DEVICE_PARAM_0
85402. DEVICE_PARAM_0__VALUE
85403. DEVICE_PARAM_1
85404. DEVICE_PARAM_1__VALUE
85405. DEVICE_PARAM_2
85406. DEVICE_PARAM_2__VALUE
85407. DEVICE_PCI
85408. DEVICE_POLLER_JIFFIES
85409. DEVICE_PORT_DVOA
85410. DEVICE_PORT_DVOB
85411. DEVICE_PORT_DVOC
85412. DEVICE_POWER_FLAGS_32K_CLK_VALID_MSK
85413. DEVICE_POWER_FLAGS_ALLOW_MEM_RETENTION_MSK
85414. DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK
85415. DEVICE_PREFIX_ATTR
85416. DEVICE_PRESENT
85417. DEVICE_PRESENT_EN
85418. DEVICE_PRINT
85419. DEVICE_PROTOCOL
85420. DEVICE_RCV
85421. DEVICE_READ
85422. DEVICE_READY
85423. DEVICE_READY_REG
85424. DEVICE_REGISTER
85425. DEVICE_REGISTERED
85426. DEVICE_REMOTE_WAKEUP_ENABLE
85427. DEVICE_REMOVABLE
85428. DEVICE_REMOVED
85429. DEVICE_RESET
85430. DEVICE_RESET_REG
85431. DEVICE_RESET_TIMER_MASK
85432. DEVICE_RESET__BANK
85433. DEVICE_RETRY
85434. DEVICE_REV
85435. DEVICE_REV_ID
85436. DEVICE_REV_ID_DEV_ID_MASK
85437. DEVICE_REV_ID_DEV_ID_X16
85438. DEVICE_REV_ID_DEV_ID_X4
85439. DEVICE_REV_ID_DEV_ID_X8
85440. DEVICE_REV_MASK
85441. DEVICE_RTL8187
85442. DEVICE_RTL8187B
85443. DEVICE_SAME
85444. DEVICE_SAWTOOTH_FAMILY
85445. DEVICE_SCOPE
85446. DEVICE_SD
85447. DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP
85448. DEVICE_SET_NMI_REG
85449. DEVICE_SET_NMI_VAL_DRV
85450. DEVICE_SHASTA_FAMILY
85451. DEVICE_SIS
85452. DEVICE_SIZE
85453. DEVICE_SNAGGLETOOTH_FAMILY
85454. DEVICE_SOLEDAD_FAMILY
85455. DEVICE_SPARE_AREA_SIZE
85456. DEVICE_SPARE_AREA_SIZE__VALUE
85457. DEVICE_SPECIFIC
85458. DEVICE_SPEED_MASK
85459. DEVICE_STANFORD_FAMILY
85460. DEVICE_STANFORD_ME_FAMILY
85461. DEVICE_STATE_BOOT
85462. DEVICE_STATE_ENABLED_RADIO
85463. DEVICE_STATE_FLUSHING
85464. DEVICE_STATE_INIT
85465. DEVICE_STATE_INITIALIZED
85466. DEVICE_STATE_OFF
85467. DEVICE_STATE_PREBOOT
85468. DEVICE_STATE_PREINIT
85469. DEVICE_STATE_PRESENT
85470. DEVICE_STATE_READY
85471. DEVICE_STATE_REGISTERED_HW
85472. DEVICE_STATE_RESET
85473. DEVICE_STATE_SCANNING
85474. DEVICE_STATE_SLEEP
85475. DEVICE_STATE_STARTED
85476. DEVICE_STATUS2__RESERVED_MASK
85477. DEVICE_STATUS2__RESERVED__MASK
85478. DEVICE_STATUS2__RESERVED__SHIFT
85479. DEVICE_STATUS_REG
85480. DEVICE_STATUS__AUX_PWR_MASK
85481. DEVICE_STATUS__AUX_PWR__MASK
85482. DEVICE_STATUS__AUX_PWR__SHIFT
85483. DEVICE_STATUS__CORR_ERR_MASK
85484. DEVICE_STATUS__CORR_ERR__MASK
85485. DEVICE_STATUS__CORR_ERR__SHIFT
85486. DEVICE_STATUS__FATAL_ERR_MASK
85487. DEVICE_STATUS__FATAL_ERR__MASK
85488. DEVICE_STATUS__FATAL_ERR__SHIFT
85489. DEVICE_STATUS__NON_FATAL_ERR_MASK
85490. DEVICE_STATUS__NON_FATAL_ERR__MASK
85491. DEVICE_STATUS__NON_FATAL_ERR__SHIFT
85492. DEVICE_STATUS__TRANSACTIONS_PEND_MASK
85493. DEVICE_STATUS__TRANSACTIONS_PEND__MASK
85494. DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
85495. DEVICE_STATUS__USR_DETECTED_MASK
85496. DEVICE_STATUS__USR_DETECTED__MASK
85497. DEVICE_STATUS__USR_DETECTED__SHIFT
85498. DEVICE_STOCK_COUNT
85499. DEVICE_STRUCT
85500. DEVICE_STV_672
85501. DEVICE_STV_676
85502. DEVICE_SUB_CLASS
85503. DEVICE_SUSPENDED
85504. DEVICE_SWI
85505. DEVICE_SYSTEM_TIME_REG
85506. DEVICE_TO_HOST
85507. DEVICE_TREE_GUID
85508. DEVICE_TYPE_ANALOG_OUTPUT
85509. DEVICE_TYPE_CF
85510. DEVICE_TYPE_CLASS_EXTENSION
85511. DEVICE_TYPE_COMPOSITE_OUTPUT
85512. DEVICE_TYPE_CRT
85513. DEVICE_TYPE_CRT_DPMS
85514. DEVICE_TYPE_CRT_DPMS_HOTPLUG
85515. DEVICE_TYPE_CV
85516. DEVICE_TYPE_DFP
85517. DEVICE_TYPE_DIGITAL_OUTPUT
85518. DEVICE_TYPE_DISPLAYPORT_OUTPUT
85519. DEVICE_TYPE_DP
85520. DEVICE_TYPE_DP_DUAL_MODE
85521. DEVICE_TYPE_DP_DUAL_MODE_BITS
85522. DEVICE_TYPE_DUAL_CHANNEL
85523. DEVICE_TYPE_EFP
85524. DEVICE_TYPE_EFP1
85525. DEVICE_TYPE_EFP2
85526. DEVICE_TYPE_EFP3
85527. DEVICE_TYPE_EFP4
85528. DEVICE_TYPE_EFP_DVI_D_DUAL
85529. DEVICE_TYPE_EFP_DVI_D_HDCP
85530. DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR
85531. DEVICE_TYPE_EFP_DVI_I
85532. DEVICE_TYPE_EFP_HOTPLUG_PWR
85533. DEVICE_TYPE_EP
85534. DEVICE_TYPE_HDMI
85535. DEVICE_TYPE_HIGH_SPEED_LINK
85536. DEVICE_TYPE_HOTPLUG_SIGNALING
85537. DEVICE_TYPE_INTERNAL_CONNECTOR
85538. DEVICE_TYPE_INT_LFP
85539. DEVICE_TYPE_INT_TV
85540. DEVICE_TYPE_LCD
85541. DEVICE_TYPE_LEG_EP
85542. DEVICE_TYPE_LFP
85543. DEVICE_TYPE_LFP_CMOS_PWR
85544. DEVICE_TYPE_LFP_LVDS_DUAL
85545. DEVICE_TYPE_LFP_LVDS_DUAL_HDCP
85546. DEVICE_TYPE_LFP_LVDS_PWR
85547. DEVICE_TYPE_LFP_PANELLINK
85548. DEVICE_TYPE_LVDS_SIGNALING
85549. DEVICE_TYPE_MIPI_OUTPUT
85550. DEVICE_TYPE_NONE
85551. DEVICE_TYPE_NOT_HDMI_OUTPUT
85552. DEVICE_TYPE_NOT_SUPPORTED
85553. DEVICE_TYPE_OPENLDI_DUALPIX
85554. DEVICE_TYPE_OPENLDI_HOTPLUG_PWR
85555. DEVICE_TYPE_POWER_MANAGEMENT
85556. DEVICE_TYPE_RC
85557. DEVICE_TYPE_TMDS_DVI_SIGNALING
85558. DEVICE_TYPE_TV
85559. DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR
85560. DEVICE_TYPE_TV_COMPOSITE
85561. DEVICE_TYPE_TV_MACROVISION
85562. DEVICE_TYPE_TV_RF_COMPOSITE
85563. DEVICE_TYPE_TV_SCART
85564. DEVICE_TYPE_TV_SVIDEO_COMPOSITE
85565. DEVICE_TYPE_UNKNOWN
85566. DEVICE_TYPE_VIDEO_SIGNALING
85567. DEVICE_TYPE_WIRELESS
85568. DEVICE_TYPE_eDP
85569. DEVICE_TYPE_eDP_BITS
85570. DEVICE_T_BD_MASK
85571. DEVICE_T_ERROR
85572. DEVICE_ULONG_ATTR
85573. DEVICE_UPDATED
85574. DEVICE_USE_CODEC1
85575. DEVICE_USE_CODEC2
85576. DEVICE_USE_CODEC23
85577. DEVICE_USE_CODEC3
85578. DEVICE_VALUE
85579. DEVICE_VENDOR_MASK
85580. DEVICE_VERSION
85581. DEVICE_VMK8055
85582. DEVICE_VMK8061
85583. DEVICE_WAIT_MAX
85584. DEVICE_WIDTH
85585. DEVICE_WIDTH__VALUE
85586. DEVICE_WIRE_DVOB
85587. DEVICE_WIRE_DVOBB
85588. DEVICE_WIRE_DVOBC
85589. DEVICE_WIRE_DVOB_MASTER
85590. DEVICE_WIRE_DVOC
85591. DEVICE_WIRE_DVOCC
85592. DEVICE_WIRE_DVOC_MASTER
85593. DEVICE_WIRE_NONE
85594. DEVICE_WORK_PENDING
85595. DEVICE_WRITE
85596. DEVICE_ZD1211
85597. DEVICE_ZD1211B
85598. DEVID
85599. DEVID_9005_CLASS
85600. DEVID_9005_CLASS_SPI
85601. DEVID_9005_HOSTRAID
85602. DEVID_9005_MAXRATE
85603. DEVID_9005_MAXRATE_FAST
85604. DEVID_9005_MAXRATE_U160
85605. DEVID_9005_MAXRATE_ULTRA
85606. DEVID_9005_MAXRATE_ULTRA2
85607. DEVID_9005_MFUNC
85608. DEVID_9005_PACKETIZED
85609. DEVID_9005_TYPE
85610. DEVID_9005_TYPE_AAA
85611. DEVID_9005_TYPE_HBA
85612. DEVID_9005_TYPE_HBA_2EXT
85613. DEVID_9005_TYPE_IROC
85614. DEVID_9005_TYPE_MB
85615. DEVID_9005_TYPE_SISL
85616. DEVID_COUNT
85617. DEVID_DEVICEID_MASK
85618. DEVID_DEVICEID_SHIFT
85619. DEVID_FIELD
85620. DEVID_HASH_BITS
85621. DEVID_HASH_MASK
85622. DEVID_HASH_SIZE
85623. DEVID_MASK
85624. DEVID_SHIFT
85625. DEVID_VENDORID_MASK
85626. DEVID_VENDORID_SHIFT
85627. DEVINDEX_HASHBITS
85628. DEVINDEX_HASHSIZE
85629. DEVINET_SYSCTL_COMPLEX_ENTRY
85630. DEVINET_SYSCTL_ENTRY
85631. DEVINET_SYSCTL_FLUSHING_ENTRY
85632. DEVINET_SYSCTL_RO_ENTRY
85633. DEVINET_SYSCTL_RW_ENTRY
85634. DEVINFO_TO_MAX_PORTS
85635. DEVINFO_TO_ROOT_HUB_PORT
85636. DEVINT
85637. DEVKMSG_LOG_MASK_DEFAULT
85638. DEVKMSG_LOG_MASK_LOCK
85639. DEVKMSG_LOG_MASK_OFF
85640. DEVKMSG_LOG_MASK_ON
85641. DEVKMSG_STR_MAX_SIZE
85642. DEVLC_PFSC
85643. DEVLC_PSPD
85644. DEVLC_PSPD_HS
85645. DEVLC_PTS
85646. DEVLC_PTW
85647. DEVLC_STS
85648. DEVLINK_ATTR_BUS_NAME
85649. DEVLINK_ATTR_DEV_NAME
85650. DEVLINK_ATTR_DPIPE_ACTION
85651. DEVLINK_ATTR_DPIPE_ACTION_TYPE
85652. DEVLINK_ATTR_DPIPE_ACTION_VALUE
85653. DEVLINK_ATTR_DPIPE_ENTRIES
85654. DEVLINK_ATTR_DPIPE_ENTRY
85655. DEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES
85656. DEVLINK_ATTR_DPIPE_ENTRY_COUNTER
85657. DEVLINK_ATTR_DPIPE_ENTRY_INDEX
85658. DEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES
85659. DEVLINK_ATTR_DPIPE_FIELD
85660. DEVLINK_ATTR_DPIPE_FIELD_BITWIDTH
85661. DEVLINK_ATTR_DPIPE_FIELD_ID
85662. DEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE
85663. DEVLINK_ATTR_DPIPE_FIELD_NAME
85664. DEVLINK_ATTR_DPIPE_HEADER
85665. DEVLINK_ATTR_DPIPE_HEADERS
85666. DEVLINK_ATTR_DPIPE_HEADER_FIELDS
85667. DEVLINK_ATTR_DPIPE_HEADER_GLOBAL
85668. DEVLINK_ATTR_DPIPE_HEADER_ID
85669. DEVLINK_ATTR_DPIPE_HEADER_INDEX
85670. DEVLINK_ATTR_DPIPE_HEADER_NAME
85671. DEVLINK_ATTR_DPIPE_MATCH
85672. DEVLINK_ATTR_DPIPE_MATCH_TYPE
85673. DEVLINK_ATTR_DPIPE_MATCH_VALUE
85674. DEVLINK_ATTR_DPIPE_TABLE
85675. DEVLINK_ATTR_DPIPE_TABLES
85676. DEVLINK_ATTR_DPIPE_TABLE_ACTIONS
85677. DEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED
85678. DEVLINK_ATTR_DPIPE_TABLE_MATCHES
85679. DEVLINK_ATTR_DPIPE_TABLE_NAME
85680. DEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID
85681. DEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS
85682. DEVLINK_ATTR_DPIPE_TABLE_SIZE
85683. DEVLINK_ATTR_DPIPE_VALUE
85684. DEVLINK_ATTR_DPIPE_VALUE_MAPPING
85685. DEVLINK_ATTR_DPIPE_VALUE_MASK
85686. DEVLINK_ATTR_ESWITCH_ENCAP_MODE
85687. DEVLINK_ATTR_ESWITCH_INLINE_MODE
85688. DEVLINK_ATTR_ESWITCH_MODE
85689. DEVLINK_ATTR_FLASH_UPDATE_COMPONENT
85690. DEVLINK_ATTR_FLASH_UPDATE_FILE_NAME
85691. DEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE
85692. DEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG
85693. DEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL
85694. DEVLINK_ATTR_FMSG
85695. DEVLINK_ATTR_FMSG_ARR_NEST_START
85696. DEVLINK_ATTR_FMSG_NEST_END
85697. DEVLINK_ATTR_FMSG_OBJ_NAME
85698. DEVLINK_ATTR_FMSG_OBJ_NEST_START
85699. DEVLINK_ATTR_FMSG_OBJ_VALUE_DATA
85700. DEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE
85701. DEVLINK_ATTR_FMSG_PAIR_NEST_START
85702. DEVLINK_ATTR_HEALTH_REPORTER
85703. DEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER
85704. DEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS
85705. DEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS
85706. DEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT
85707. DEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD
85708. DEVLINK_ATTR_HEALTH_REPORTER_NAME
85709. DEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT
85710. DEVLINK_ATTR_HEALTH_REPORTER_STATE
85711. DEVLINK_ATTR_INFO_DRIVER_NAME
85712. DEVLINK_ATTR_INFO_SERIAL_NUMBER
85713. DEVLINK_ATTR_INFO_VERSION_FIXED
85714. DEVLINK_ATTR_INFO_VERSION_NAME
85715. DEVLINK_ATTR_INFO_VERSION_RUNNING
85716. DEVLINK_ATTR_INFO_VERSION_STORED
85717. DEVLINK_ATTR_INFO_VERSION_VALUE
85718. DEVLINK_ATTR_MAX
85719. DEVLINK_ATTR_PAD
85720. DEVLINK_ATTR_PARAM
85721. DEVLINK_ATTR_PARAM_GENERIC
85722. DEVLINK_ATTR_PARAM_NAME
85723. DEVLINK_ATTR_PARAM_TYPE
85724. DEVLINK_ATTR_PARAM_VALUE
85725. DEVLINK_ATTR_PARAM_VALUES_LIST
85726. DEVLINK_ATTR_PARAM_VALUE_CMODE
85727. DEVLINK_ATTR_PARAM_VALUE_DATA
85728. DEVLINK_ATTR_PORT_DESIRED_TYPE
85729. DEVLINK_ATTR_PORT_FLAVOUR
85730. DEVLINK_ATTR_PORT_IBDEV_NAME
85731. DEVLINK_ATTR_PORT_INDEX
85732. DEVLINK_ATTR_PORT_NETDEV_IFINDEX
85733. DEVLINK_ATTR_PORT_NETDEV_NAME
85734. DEVLINK_ATTR_PORT_NUMBER
85735. DEVLINK_ATTR_PORT_PCI_PF_NUMBER
85736. DEVLINK_ATTR_PORT_PCI_VF_NUMBER
85737. DEVLINK_ATTR_PORT_SPLIT_COUNT
85738. DEVLINK_ATTR_PORT_SPLIT_GROUP
85739. DEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER
85740. DEVLINK_ATTR_PORT_TYPE
85741. DEVLINK_ATTR_REGION_CHUNK
85742. DEVLINK_ATTR_REGION_CHUNKS
85743. DEVLINK_ATTR_REGION_CHUNK_ADDR
85744. DEVLINK_ATTR_REGION_CHUNK_DATA
85745. DEVLINK_ATTR_REGION_CHUNK_LEN
85746. DEVLINK_ATTR_REGION_NAME
85747. DEVLINK_ATTR_REGION_SIZE
85748. DEVLINK_ATTR_REGION_SNAPSHOT
85749. DEVLINK_ATTR_REGION_SNAPSHOTS
85750. DEVLINK_ATTR_REGION_SNAPSHOT_ID
85751. DEVLINK_ATTR_RELOAD_FAILED
85752. DEVLINK_ATTR_RESOURCE
85753. DEVLINK_ATTR_RESOURCE_ID
85754. DEVLINK_ATTR_RESOURCE_LIST
85755. DEVLINK_ATTR_RESOURCE_NAME
85756. DEVLINK_ATTR_RESOURCE_OCC
85757. DEVLINK_ATTR_RESOURCE_SIZE
85758. DEVLINK_ATTR_RESOURCE_SIZE_GRAN
85759. DEVLINK_ATTR_RESOURCE_SIZE_MAX
85760. DEVLINK_ATTR_RESOURCE_SIZE_MIN
85761. DEVLINK_ATTR_RESOURCE_SIZE_NEW
85762. DEVLINK_ATTR_RESOURCE_SIZE_VALID
85763. DEVLINK_ATTR_RESOURCE_UNIT
85764. DEVLINK_ATTR_SB_EGRESS_POOL_COUNT
85765. DEVLINK_ATTR_SB_EGRESS_TC_COUNT
85766. DEVLINK_ATTR_SB_INDEX
85767. DEVLINK_ATTR_SB_INGRESS_POOL_COUNT
85768. DEVLINK_ATTR_SB_INGRESS_TC_COUNT
85769. DEVLINK_ATTR_SB_OCC_CUR
85770. DEVLINK_ATTR_SB_OCC_MAX
85771. DEVLINK_ATTR_SB_POOL_CELL_SIZE
85772. DEVLINK_ATTR_SB_POOL_INDEX
85773. DEVLINK_ATTR_SB_POOL_SIZE
85774. DEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE
85775. DEVLINK_ATTR_SB_POOL_TYPE
85776. DEVLINK_ATTR_SB_SIZE
85777. DEVLINK_ATTR_SB_TC_INDEX
85778. DEVLINK_ATTR_SB_THRESHOLD
85779. DEVLINK_ATTR_STATS
85780. DEVLINK_ATTR_STATS_MAX
85781. DEVLINK_ATTR_STATS_RX_BYTES
85782. DEVLINK_ATTR_STATS_RX_PACKETS
85783. DEVLINK_ATTR_TRAP_ACTION
85784. DEVLINK_ATTR_TRAP_GENERIC
85785. DEVLINK_ATTR_TRAP_GROUP_NAME
85786. DEVLINK_ATTR_TRAP_METADATA
85787. DEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT
85788. DEVLINK_ATTR_TRAP_NAME
85789. DEVLINK_ATTR_TRAP_TYPE
85790. DEVLINK_ATTR_UNSPEC
85791. DEVLINK_CMD_DEL
85792. DEVLINK_CMD_DPIPE_ENTRIES_GET
85793. DEVLINK_CMD_DPIPE_HEADERS_GET
85794. DEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET
85795. DEVLINK_CMD_DPIPE_TABLE_GET
85796. DEVLINK_CMD_ESWITCH_GET
85797. DEVLINK_CMD_ESWITCH_MODE_GET
85798. DEVLINK_CMD_ESWITCH_MODE_SET
85799. DEVLINK_CMD_ESWITCH_SET
85800. DEVLINK_CMD_FLASH_UPDATE
85801. DEVLINK_CMD_FLASH_UPDATE_END
85802. DEVLINK_CMD_FLASH_UPDATE_STATUS
85803. DEVLINK_CMD_GET
85804. DEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE
85805. DEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR
85806. DEVLINK_CMD_HEALTH_REPORTER_DUMP_GET
85807. DEVLINK_CMD_HEALTH_REPORTER_GET
85808. DEVLINK_CMD_HEALTH_REPORTER_RECOVER
85809. DEVLINK_CMD_HEALTH_REPORTER_SET
85810. DEVLINK_CMD_INFO_GET
85811. DEVLINK_CMD_MAX
85812. DEVLINK_CMD_NEW
85813. DEVLINK_CMD_PARAM_DEL
85814. DEVLINK_CMD_PARAM_GET
85815. DEVLINK_CMD_PARAM_NEW
85816. DEVLINK_CMD_PARAM_SET
85817. DEVLINK_CMD_PORT_DEL
85818. DEVLINK_CMD_PORT_GET
85819. DEVLINK_CMD_PORT_NEW
85820. DEVLINK_CMD_PORT_PARAM_DEL
85821. DEVLINK_CMD_PORT_PARAM_GET
85822. DEVLINK_CMD_PORT_PARAM_NEW
85823. DEVLINK_CMD_PORT_PARAM_SET
85824. DEVLINK_CMD_PORT_SET
85825. DEVLINK_CMD_PORT_SPLIT
85826. DEVLINK_CMD_PORT_UNSPLIT
85827. DEVLINK_CMD_REGION_DEL
85828. DEVLINK_CMD_REGION_GET
85829. DEVLINK_CMD_REGION_NEW
85830. DEVLINK_CMD_REGION_READ
85831. DEVLINK_CMD_REGION_SET
85832. DEVLINK_CMD_RELOAD
85833. DEVLINK_CMD_RESOURCE_DUMP
85834. DEVLINK_CMD_RESOURCE_SET
85835. DEVLINK_CMD_SB_DEL
85836. DEVLINK_CMD_SB_GET
85837. DEVLINK_CMD_SB_NEW
85838. DEVLINK_CMD_SB_OCC_MAX_CLEAR
85839. DEVLINK_CMD_SB_OCC_SNAPSHOT
85840. DEVLINK_CMD_SB_POOL_DEL
85841. DEVLINK_CMD_SB_POOL_GET
85842. DEVLINK_CMD_SB_POOL_NEW
85843. DEVLINK_CMD_SB_POOL_SET
85844. DEVLINK_CMD_SB_PORT_POOL_DEL
85845. DEVLINK_CMD_SB_PORT_POOL_GET
85846. DEVLINK_CMD_SB_PORT_POOL_NEW
85847. DEVLINK_CMD_SB_PORT_POOL_SET
85848. DEVLINK_CMD_SB_SET
85849. DEVLINK_CMD_SB_TC_POOL_BIND_DEL
85850. DEVLINK_CMD_SB_TC_POOL_BIND_GET
85851. DEVLINK_CMD_SB_TC_POOL_BIND_NEW
85852. DEVLINK_CMD_SB_TC_POOL_BIND_SET
85853. DEVLINK_CMD_SET
85854. DEVLINK_CMD_TRAP_DEL
85855. DEVLINK_CMD_TRAP_GET
85856. DEVLINK_CMD_TRAP_GROUP_DEL
85857. DEVLINK_CMD_TRAP_GROUP_GET
85858. DEVLINK_CMD_TRAP_GROUP_NEW
85859. DEVLINK_CMD_TRAP_GROUP_SET
85860. DEVLINK_CMD_TRAP_NEW
85861. DEVLINK_CMD_TRAP_SET
85862. DEVLINK_CMD_UNSPEC
85863. DEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY
85864. DEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC
85865. DEVLINK_DPIPE_FIELD_IPV4_DST_IP
85866. DEVLINK_DPIPE_FIELD_IPV6_DST_IP
85867. DEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX
85868. DEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE
85869. DEVLINK_DPIPE_HEADER_ETHERNET
85870. DEVLINK_DPIPE_HEADER_IPV4
85871. DEVLINK_DPIPE_HEADER_IPV6
85872. DEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT
85873. DEVLINK_ESWITCH_ENCAP_MODE_BASIC
85874. DEVLINK_ESWITCH_ENCAP_MODE_NONE
85875. DEVLINK_ESWITCH_INLINE_MODE_LINK
85876. DEVLINK_ESWITCH_INLINE_MODE_NETWORK
85877. DEVLINK_ESWITCH_INLINE_MODE_NONE
85878. DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT
85879. DEVLINK_ESWITCH_MODE_LEGACY
85880. DEVLINK_ESWITCH_MODE_SWITCHDEV
85881. DEVLINK_FMSG_MAX_SIZE
85882. DEVLINK_FW_STRING_LEN
85883. DEVLINK_GENL_MCGRP_CONFIG_NAME
85884. DEVLINK_GENL_NAME
85885. DEVLINK_GENL_VERSION
85886. DEVLINK_HEALTH_REPORTER_STATE_ERROR
85887. DEVLINK_HEALTH_REPORTER_STATE_HEALTHY
85888. DEVLINK_INFO_VERSION_GENERIC_ASIC_ID
85889. DEVLINK_INFO_VERSION_GENERIC_ASIC_REV
85890. DEVLINK_INFO_VERSION_GENERIC_BOARD_ID
85891. DEVLINK_INFO_VERSION_GENERIC_BOARD_MANUFACTURE
85892. DEVLINK_INFO_VERSION_GENERIC_BOARD_REV
85893. DEVLINK_INFO_VERSION_GENERIC_FW
85894. DEVLINK_INFO_VERSION_GENERIC_FW_APP
85895. DEVLINK_INFO_VERSION_GENERIC_FW_MGMT
85896. DEVLINK_INFO_VERSION_GENERIC_FW_NCSI
85897. DEVLINK_INFO_VERSION_GENERIC_FW_UNDI
85898. DEVLINK_MCGRP_CONFIG
85899. DEVLINK_NL_FLAG_NEED_DEVLINK
85900. DEVLINK_NL_FLAG_NEED_PORT
85901. DEVLINK_NL_FLAG_NEED_SB
85902. DEVLINK_NL_FLAG_NO_LOCK
85903. DEVLINK_PARAM_CMODE_DRIVERINIT
85904. DEVLINK_PARAM_CMODE_MAX
85905. DEVLINK_PARAM_CMODE_PERMANENT
85906. DEVLINK_PARAM_CMODE_RUNTIME
85907. DEVLINK_PARAM_DRIVER
85908. DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DISK
85909. DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER
85910. DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH
85911. DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_UNKNOWN
85912. DEVLINK_PARAM_GENERIC
85913. DEVLINK_PARAM_GENERIC_ENABLE_SRIOV_NAME
85914. DEVLINK_PARAM_GENERIC_ENABLE_SRIOV_TYPE
85915. DEVLINK_PARAM_GENERIC_FW_LOAD_POLICY_NAME
85916. DEVLINK_PARAM_GENERIC_FW_LOAD_POLICY_TYPE
85917. DEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV
85918. DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY
85919. DEVLINK_PARAM_GENERIC_ID_IGNORE_ARI
85920. DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET
85921. DEVLINK_PARAM_GENERIC_ID_MAX
85922. DEVLINK_PARAM_GENERIC_ID_MAX_MACS
85923. DEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX
85924. DEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN
85925. DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT
85926. DEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE
85927. DEVLINK_PARAM_GENERIC_IGNORE_ARI_NAME
85928. DEVLINK_PARAM_GENERIC_IGNORE_ARI_TYPE
85929. DEVLINK_PARAM_GENERIC_INT_ERR_RESET_NAME
85930. DEVLINK_PARAM_GENERIC_INT_ERR_RESET_TYPE
85931. DEVLINK_PARAM_GENERIC_MAX_MACS_NAME
85932. DEVLINK_PARAM_GENERIC_MAX_MACS_TYPE
85933. DEVLINK_PARAM_GENERIC_MSIX_VEC_PER_PF_MAX_NAME
85934. DEVLINK_PARAM_GENERIC_MSIX_VEC_PER_PF_MAX_TYPE
85935. DEVLINK_PARAM_GENERIC_MSIX_VEC_PER_PF_MIN_NAME
85936. DEVLINK_PARAM_GENERIC_MSIX_VEC_PER_PF_MIN_TYPE
85937. DEVLINK_PARAM_GENERIC_REGION_SNAPSHOT_NAME
85938. DEVLINK_PARAM_GENERIC_REGION_SNAPSHOT_TYPE
85939. DEVLINK_PARAM_GENERIC_RESET_DEV_ON_DRV_PROBE_NAME
85940. DEVLINK_PARAM_GENERIC_RESET_DEV_ON_DRV_PROBE_TYPE
85941. DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_ALWAYS
85942. DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_DISK
85943. DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_NEVER
85944. DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_UNKNOWN
85945. DEVLINK_PARAM_TYPE_BOOL
85946. DEVLINK_PARAM_TYPE_STRING
85947. DEVLINK_PARAM_TYPE_U16
85948. DEVLINK_PARAM_TYPE_U32
85949. DEVLINK_PARAM_TYPE_U8
85950. DEVLINK_PORT_FLAVOUR_CPU
85951. DEVLINK_PORT_FLAVOUR_DSA
85952. DEVLINK_PORT_FLAVOUR_PCI_PF
85953. DEVLINK_PORT_FLAVOUR_PCI_VF
85954. DEVLINK_PORT_FLAVOUR_PHYSICAL
85955. DEVLINK_PORT_TYPE_AUTO
85956. DEVLINK_PORT_TYPE_ETH
85957. DEVLINK_PORT_TYPE_IB
85958. DEVLINK_PORT_TYPE_NOTSET
85959. DEVLINK_PORT_TYPE_WARN_TIMEOUT
85960. DEVLINK_REGION_READ_CHUNK_SIZE
85961. DEVLINK_RESOURCE_ID_PARENT_TOP
85962. DEVLINK_RESOURCE_UNIT_ENTRY
85963. DEVLINK_SB_POOL_TYPE_EGRESS
85964. DEVLINK_SB_POOL_TYPE_INGRESS
85965. DEVLINK_SB_THRESHOLD_TO_ALPHA_MAX
85966. DEVLINK_SB_THRESHOLD_TYPE_DYNAMIC
85967. DEVLINK_SB_THRESHOLD_TYPE_STATIC
85968. DEVLINK_TRAP
85969. DEVLINK_TRAP_ACTION_DROP
85970. DEVLINK_TRAP_ACTION_TRAP
85971. DEVLINK_TRAP_DRIVER
85972. DEVLINK_TRAP_GENERIC
85973. DEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE
85974. DEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST
85975. DEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER
85976. DEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER
85977. DEVLINK_TRAP_GENERIC_ID_MAX
85978. DEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER
85979. DEVLINK_TRAP_GENERIC_ID_SMAC_MC
85980. DEVLINK_TRAP_GENERIC_ID_TAIL_DROP
85981. DEVLINK_TRAP_GENERIC_ID_TTL_ERROR
85982. DEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH
85983. DEVLINK_TRAP_GENERIC_NAME_BLACKHOLE_ROUTE
85984. DEVLINK_TRAP_GENERIC_NAME_EMPTY_TX_LIST
85985. DEVLINK_TRAP_GENERIC_NAME_INGRESS_STP_FILTER
85986. DEVLINK_TRAP_GENERIC_NAME_INGRESS_VLAN_FILTER
85987. DEVLINK_TRAP_GENERIC_NAME_PORT_LOOPBACK_FILTER
85988. DEVLINK_TRAP_GENERIC_NAME_SMAC_MC
85989. DEVLINK_TRAP_GENERIC_NAME_TAIL_DROP
85990. DEVLINK_TRAP_GENERIC_NAME_TTL_ERROR
85991. DEVLINK_TRAP_GENERIC_NAME_VLAN_TAG_MISMATCH
85992. DEVLINK_TRAP_GROUP
85993. DEVLINK_TRAP_GROUP_GENERIC
85994. DEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS
85995. DEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS
85996. DEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS
85997. DEVLINK_TRAP_GROUP_GENERIC_ID_MAX
85998. DEVLINK_TRAP_GROUP_GENERIC_NAME_BUFFER_DROPS
85999. DEVLINK_TRAP_GROUP_GENERIC_NAME_L2_DROPS
86000. DEVLINK_TRAP_GROUP_GENERIC_NAME_L3_DROPS
86001. DEVLINK_TRAP_METADATA_TYPE_F_IN_PORT
86002. DEVLINK_TRAP_TYPE_DROP
86003. DEVLINK_TRAP_TYPE_EXCEPTION
86004. DEVM_ARAUX_COH
86005. DEVM_AWAUX_COH
86006. DEVM_IOREMAP
86007. DEVM_IOREMAP_NC
86008. DEVM_IOREMAP_UC
86009. DEVM_IOREMAP_WC
86010. DEVNAME
86011. DEVOLO_EAGLE_II_A_PID_PREFIRM
86012. DEVOLO_EAGLE_II_A_PID_PSTFIRM
86013. DEVOLO_EAGLE_II_B_PID_PREFIRM
86014. DEVOLO_EAGLE_II_B_PID_PSTFIRM
86015. DEVOLO_EAGLE_I_A_PID_PREFIRM
86016. DEVOLO_EAGLE_I_A_PID_PSTFIRM
86017. DEVOLO_EAGLE_I_B_PID_PREFIRM
86018. DEVOLO_EAGLE_I_B_PID_PSTFIRM
86019. DEVOLO_VID
86020. DEVPORT_MINOR
86021. DEVPTS_DEFAULT_MODE
86022. DEVPTS_DEFAULT_PTMX_MODE
86023. DEVPTS_SB
86024. DEVPTS_SUPER_MAGIC
86025. DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED
86026. DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID
86027. DEVREG_FAILURE_INVALID_PHY_ID
86028. DEVREG_FAILURE_OUT_OF_RESOURCE
86029. DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED
86030. DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE
86031. DEVREG_FAILURE_PORT_NOT_VALID_STATE
86032. DEVREG_SUCCESS
86033. DEVREV
86034. DEVRST
86035. DEVSEED
86036. DEVSEL
86037. DEVSEL_DCLKOUT_MARK
86038. DEVSEL_MASK
86039. DEVSTAT
86040. DEVSTATUS_CLEAR
86041. DEVS_CTRL
86042. DEVS_CTRL_DEVS_ACTIVE_MASK
86043. DEVS_CTRL_DEV_ACTIVE
86044. DEVS_CTRL_DEV_CLR
86045. DEVS_CTRL_DEV_CLR_ALL
86046. DEVS_CTRL_DEV_CLR_SHIFT
86047. DEVS_GRP_AND_MIPHY_DBG_REG3_MASK
86048. DEVS_GRP_AND_MIPHY_DBG_REG4_MASK
86049. DEVTIMER1
86050. DEVTIMER2
86051. DEVTREE_CHUNK_SIZE
86052. DEVTYPE_3M
86053. DEVTYPE_DMC_TSC10
86054. DEVTYPE_E2I
86055. DEVTYPE_EGALAX
86056. DEVTYPE_ELO
86057. DEVTYPE_ETOUCH
86058. DEVTYPE_ETURBO
86059. DEVTYPE_GENERAL_TOUCH
86060. DEVTYPE_GOTOP
86061. DEVTYPE_GUNZE
86062. DEVTYPE_IDEALTEK
86063. DEVTYPE_IGNORE
86064. DEVTYPE_IRTOUCH
86065. DEVTYPE_IRTOUCH_HIRES
86066. DEVTYPE_ITM
86067. DEVTYPE_JASTEC
86068. DEVTYPE_NEXIO
86069. DEVTYPE_PANJIT
86070. DEVTYPE_TC45USB
86071. DEVTYPE_ZYTRONIC
86072. DEVX_OBJ_FLAGS_CQ
86073. DEVX_OBJ_FLAGS_DCT
86074. DEVX_OBJ_FLAGS_INDIRECT_MKEY
86075. DEV_ADDR
86076. DEV_ADDR_DYNAMIC
86077. DEV_ADDR_DYNAMIC_ADDR_VALID
86078. DEV_ADDR_MASK
86079. DEV_ADDR_MSK
86080. DEV_ADDR_TABLE_DYNAMIC_ADDR
86081. DEV_ADDR_TABLE_LEGACY_I2C_DEV
86082. DEV_ADDR_TABLE_LOC
86083. DEV_ADDR_TABLE_STATIC_ADDR
86084. DEV_ALL
86085. DEV_ASPM_BACKDOOR
86086. DEV_ASPM_DISABLE
86087. DEV_ASPM_DYNAMIC
86088. DEV_ASPM_STATIC
86089. DEV_ASSIGN
86090. DEV_ATTR
86091. DEV_ATTR_RO
86092. DEV_ATTR_RO_PERM
86093. DEV_ATTR_RO_STR
86094. DEV_ATTR_RW_PERM
86095. DEV_ATTR_WO_PERM
86096. DEV_AUDIO_1
86097. DEV_AUDIO_2
86098. DEV_AV
86099. DEV_BANK_0_PARAM
86100. DEV_BANK_1_PARAM
86101. DEV_BANK_2_PARAM
86102. DEV_BANK_BOOT_PARAM
86103. DEV_BUS_CTRL
86104. DEV_BUS_INT_CAUSE
86105. DEV_BUS_INT_MASK
86106. DEV_BUS_PHYS_BASE
86107. DEV_BUS_TYPE
86108. DEV_BUS_VIRT_BASE
86109. DEV_C3XXX
86110. DEV_C3XXXVF
86111. DEV_C62X
86112. DEV_C62XVF
86113. DEV_CAP_EXT_2_FLAG_80_VFS
86114. DEV_CAP_EXT_2_FLAG_FSM
86115. DEV_CAP_EXT_2_FLAG_PFC_COUNTERS
86116. DEV_CAP_EXT_2_FLAG_VLAN_CONTROL
86117. DEV_CAR_KIT
86118. DEV_CDROM
86119. DEV_CDROM_AUTOCLOSE
86120. DEV_CDROM_AUTOEJECT
86121. DEV_CDROM_CHECK_MEDIA
86122. DEV_CDROM_DEBUG
86123. DEV_CDROM_INFO
86124. DEV_CDROM_LOCK
86125. DEV_CGROUP_PROG
86126. DEV_CHAR_TABLE_POINTER
86127. DEV_CH_ID_CTRL
86128. DEV_CK804
86129. DEV_CLASS_ECKD
86130. DEV_CLASS_FBA
86131. DEV_CLASS_UR_I
86132. DEV_CLASS_UR_O
86133. DEV_CLIENT_MASK
86134. DEV_CLIENT_STRING
86135. DEV_CLOCK_CFG
86136. DEV_CLOCK_CFG_LINK_SPEED
86137. DEV_CLOCK_CFG_LINK_SPEED_M
86138. DEV_CLOCK_CFG_MAC_RX_RST
86139. DEV_CLOCK_CFG_MAC_TX_RST
86140. DEV_CLOCK_CFG_PCS_RX_RST
86141. DEV_CLOCK_CFG_PCS_TX_RST
86142. DEV_CLOCK_CFG_PHY_RST
86143. DEV_CLOCK_CFG_PORT_RST
86144. DEV_CMD_PENDING
86145. DEV_CMD_TYPE_NOP
86146. DEV_CMD_TYPE_QUERY
86147. DEV_CNTRL2
86148. DEV_CNTR_LAST
86149. DEV_COMM
86150. DEV_COMMAND_REG
86151. DEV_CON
86152. DEV_CONNECT_DVI
86153. DEV_CONNECT_HDMI
86154. DEV_CONTROL_REG
86155. DEV_CON_CH
86156. DEV_CREATE_FLAG_MASK
86157. DEV_CTRL_ENABLE
86158. DEV_CTRL_HOT_JOIN_NACK
86159. DEV_CTRL_I2C_SLAVE_PRESENT
86160. DEV_CTRL_RESUME
86161. DEV_DASD
86162. DEV_DAX_BUS
86163. DEV_DAX_CLASS
86164. DEV_DBG
86165. DEV_DBG_NAME
86166. DEV_DB_NON_PERSISTENT
86167. DEV_DB_PERSISTENT
86168. DEV_DEBUG
86169. DEV_DEDICATED_CHG
86170. DEV_DESC_OFFSET_PID
86171. DEV_DESC_OFFSET_VID
86172. DEV_DH895XCC
86173. DEV_DH895XCCVF
86174. DEV_DISCONNECTED
86175. DEV_DISK_CAPABLE_NOT_PRESENT
86176. DEV_DMA_BUFF_STS_DMABUSY
86177. DEV_DMA_BUFF_STS_DMADONE
86178. DEV_DMA_BUFF_STS_HBUSY
86179. DEV_DMA_BUFF_STS_HREADY
86180. DEV_DMA_BUFF_STS_MASK
86181. DEV_DMA_BUFF_STS_SHIFT
86182. DEV_DMA_COHERENT
86183. DEV_DMA_IOC
86184. DEV_DMA_ISOC_FRNUM_MASK
86185. DEV_DMA_ISOC_FRNUM_SHIFT
86186. DEV_DMA_ISOC_NBYTES_SHIFT
86187. DEV_DMA_ISOC_PID_DATA0
86188. DEV_DMA_ISOC_PID_DATA1
86189. DEV_DMA_ISOC_PID_DATA2
86190. DEV_DMA_ISOC_PID_MASK
86191. DEV_DMA_ISOC_PID_MDATA
86192. DEV_DMA_ISOC_PID_SHIFT
86193. DEV_DMA_ISOC_RX_NBYTES_LIMIT
86194. DEV_DMA_ISOC_RX_NBYTES_MASK
86195. DEV_DMA_ISOC_TX_NBYTES_LIMIT
86196. DEV_DMA_ISOC_TX_NBYTES_MASK
86197. DEV_DMA_L
86198. DEV_DMA_MTRF
86199. DEV_DMA_NBYTES_LIMIT
86200. DEV_DMA_NBYTES_MASK
86201. DEV_DMA_NBYTES_SHIFT
86202. DEV_DMA_NON_COHERENT
86203. DEV_DMA_NOT_SUPPORTED
86204. DEV_DMA_SHORT
86205. DEV_DMA_SR
86206. DEV_DMA_STS_BUFF_ERR
86207. DEV_DMA_STS_BUFF_FLUSH
86208. DEV_DMA_STS_MASK
86209. DEV_DMA_STS_SHIFT
86210. DEV_DMA_STS_SUCC
86211. DEV_DMA_TYPE_AHB
86212. DEV_DMA_TYPE_AXI
86213. DEV_DMA_TYPE_OCP
86214. DEV_DMA_TYPE_PLB
86215. DEV_DMA_WIDTH_32
86216. DEV_DMA_WIDTH_64
86217. DEV_DOMID_MASK
86218. DEV_DOWN
86219. DEV_DUALPOINT
86220. DEV_EEE_CFG
86221. DEV_EEE_CFG_EEE_ENA
86222. DEV_EEE_CFG_EEE_TIMER_AGE
86223. DEV_EEE_CFG_EEE_TIMER_AGE_M
86224. DEV_EEE_CFG_EEE_TIMER_AGE_X
86225. DEV_EEE_CFG_EEE_TIMER_HOLDOFF
86226. DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M
86227. DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X
86228. DEV_EEE_CFG_EEE_TIMER_WAKEUP
86229. DEV_EEE_CFG_EEE_TIMER_WAKEUP_M
86230. DEV_EEE_CFG_EEE_TIMER_WAKEUP_X
86231. DEV_EEE_CFG_PORT_LPI
86232. DEV_EN
86233. DEV_ENTRY
86234. DEV_ENTRY_EINT_PASS
86235. DEV_ENTRY_EX
86236. DEV_ENTRY_INIT_PASS
86237. DEV_ENTRY_IR
86238. DEV_ENTRY_IRQ_TBL_EN
86239. DEV_ENTRY_IW
86240. DEV_ENTRY_LINT0_PASS
86241. DEV_ENTRY_LINT1_PASS
86242. DEV_ENTRY_MODE_MASK
86243. DEV_ENTRY_MODE_SHIFT
86244. DEV_ENTRY_NMI_PASS
86245. DEV_ENTRY_NO_PAGE_FAULT
86246. DEV_ENTRY_PPR
86247. DEV_ENTRY_SYSMGT1
86248. DEV_ENTRY_SYSMGT2
86249. DEV_ENTRY_TRANSLATION
86250. DEV_ENTRY_VALID
86251. DEV_ERR
86252. DEV_EVENTS
86253. DEV_EVENT_CONDOWN
86254. DEV_EVENT_CONUP
86255. DEV_EVENT_INTERRUPT
86256. DEV_EVENT_NOTOPER
86257. DEV_EVENT_RESTART
86258. DEV_EVENT_RXDOWN
86259. DEV_EVENT_RXUP
86260. DEV_EVENT_START
86261. DEV_EVENT_STOP
86262. DEV_EVENT_TIMEOUT
86263. DEV_EVENT_TXDOWN
86264. DEV_EVENT_TXUP
86265. DEV_EVENT_VERIFY
86266. DEV_FEATURE_CHANGED
86267. DEV_FLAGS_ANYUSE
86268. DEV_FLAGS_BURSTABLE
86269. DEV_FLAGS_IN
86270. DEV_FLAGS_INUSE
86271. DEV_FLAGS_OUT
86272. DEV_FLAGS_SYNC
86273. DEV_FLAG_UNKNOWN
86274. DEV_FLAG_X1
86275. DEV_FLAG_X16
86276. DEV_FLAG_X2
86277. DEV_FLAG_X32
86278. DEV_FLAG_X4
86279. DEV_FLAG_X64
86280. DEV_FLAG_X8
86281. DEV_FULLSPEED
86282. DEV_FUNC
86283. DEV_GET_MAGIC
86284. DEV_GET_MAX_DOWNSIZE
86285. DEV_GET_MAX_UPSIZE
86286. DEV_GRP_MASK
86287. DEV_GRP_NULL
86288. DEV_GRP_OFFSET
86289. DEV_GRP_P1
86290. DEV_GRP_P2
86291. DEV_GRP_P3
86292. DEV_GRP_SHIFT
86293. DEV_HAS_CHECKSUM
86294. DEV_HAS_COLLISION_FIX
86295. DEV_HAS_CORRECT_MACADDR
86296. DEV_HAS_GEAR_MODE
86297. DEV_HAS_HIGH_DMA
86298. DEV_HAS_LARGEDESC
86299. DEV_HAS_MGMT_UNIT
86300. DEV_HAS_MSI
86301. DEV_HAS_MSI_X
86302. DEV_HAS_PAUSEFRAME_TX_V1
86303. DEV_HAS_PAUSEFRAME_TX_V2
86304. DEV_HAS_PAUSEFRAME_TX_V3
86305. DEV_HAS_POWER_CNTRL
86306. DEV_HAS_STATISTICS_V1
86307. DEV_HAS_STATISTICS_V12
86308. DEV_HAS_STATISTICS_V123
86309. DEV_HAS_STATISTICS_V2
86310. DEV_HAS_STATISTICS_V3
86311. DEV_HAS_TEST_EXTENDED
86312. DEV_HAS_VLAN
86313. DEV_HIGHSPEED
86314. DEV_HISUPPORT
86315. DEV_HUB
86316. DEV_HWMON
86317. DEV_ID
86318. DEV_IDLE_EN
86319. DEV_ID_FAMILY
86320. DEV_ID_I3C_MASTER
86321. DEV_ID_MAX1668
86322. DEV_ID_MAX1805
86323. DEV_ID_MAX1989
86324. DEV_ID_NUM_BMSK
86325. DEV_ID_NUM_SHFT
86326. DEV_ID_PCI_DIS
86327. DEV_ID_PCI_HOST
86328. DEV_ID_REG
86329. DEV_ID_RR0
86330. DEV_ID_RR0_DEV_ADDR_MASK
86331. DEV_ID_RR0_GET_DEV_ADDR
86332. DEV_ID_RR0_HDR_CAP
86333. DEV_ID_RR0_IS_I3C
86334. DEV_ID_RR0_LVR_EXT_ADDR
86335. DEV_ID_RR0_SET_DEV_ADDR
86336. DEV_ID_RR1
86337. DEV_ID_RR1_PID_MSB
86338. DEV_ID_RR2
86339. DEV_ID_RR2_BCR
86340. DEV_ID_RR2_DCR
86341. DEV_ID_RR2_LVR
86342. DEV_ID_RR2_PID_LSB
86343. DEV_ID_SHIFT
86344. DEV_ID_SINGLE_PC
86345. DEV_INFO
86346. DEV_INFO_ACTIVE
86347. DEV_INFO_DISPLAY_FOR_EACH_FLAG
86348. DEV_INFO_FOR_EACH_FLAG
86349. DEV_INFO_MAX_NUM
86350. DEV_INITIALIZED
86351. DEV_INIT_TEST_WITH_RETURN
86352. DEV_INREQUEST
86353. DEV_INT
86354. DEV_IPMI
86355. DEV_IPMI_POWEROFF_POWERCYCLE
86356. DEV_IRQ
86357. DEV_IS_GONE
86358. DEV_JIG_UART_OFF
86359. DEV_JIG_UART_ON
86360. DEV_JIG_USB_OFF
86361. DEV_JIG_USB_ON
86362. DEV_JUKEBOX
86363. DEV_L0_STATE
86364. DEV_L1_STATE
86365. DEV_L2_STATE
86366. DEV_L3_STATE
86367. DEV_LABEL
86368. DEV_LIM_FLAG_ATOMIC
86369. DEV_LIM_FLAG_AUTO_PATH_MIG
86370. DEV_LIM_FLAG_BAD_PKEY_CNTR
86371. DEV_LIM_FLAG_BAD_QKEY_CNTR
86372. DEV_LIM_FLAG_IPOIB_CSUM
86373. DEV_LIM_FLAG_MW
86374. DEV_LIM_FLAG_RAW_ETHER
86375. DEV_LIM_FLAG_RAW_IPV6
86376. DEV_LIM_FLAG_RAW_MULTI
86377. DEV_LIM_FLAG_RC
86378. DEV_LIM_FLAG_RD
86379. DEV_LIM_FLAG_SRQ
86380. DEV_LIM_FLAG_UC
86381. DEV_LIM_FLAG_UD
86382. DEV_LIM_FLAG_UD_AV_PORT_ENFORCE
86383. DEV_LIM_FLAG_UD_MULTI
86384. DEV_LOWSPEED
86385. DEV_LST_COMP_MODE
86386. DEV_LST_DISABLED
86387. DEV_LST_HOT_RESET
86388. DEV_LST_INACTIVE
86389. DEV_LST_LB_STATE
86390. DEV_LST_POLLING
86391. DEV_LST_RECOVERY
86392. DEV_LST_RXDETECT
86393. DEV_LST_U0
86394. DEV_LST_U1
86395. DEV_LST_U2
86396. DEV_LST_U3
86397. DEV_MAC_ADV_CHK_CFG
86398. DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA
86399. DEV_MAC_DBG_CFG
86400. DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA
86401. DEV_MAC_DBG_CFG_TBI_MODE
86402. DEV_MAC_ENA_CFG
86403. DEV_MAC_ENA_CFG_RX_ENA
86404. DEV_MAC_ENA_CFG_TX_ENA
86405. DEV_MAC_FC_MAC_HIGH_CFG
86406. DEV_MAC_FC_MAC_LOW_CFG
86407. DEV_MAC_HDX_CFG
86408. DEV_MAC_HDX_CFG_BYPASS_COL_SYNC
86409. DEV_MAC_HDX_CFG_LATE_COL_POS
86410. DEV_MAC_HDX_CFG_LATE_COL_POS_M
86411. DEV_MAC_HDX_CFG_OB_ENA
86412. DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA
86413. DEV_MAC_HDX_CFG_SEED
86414. DEV_MAC_HDX_CFG_SEED_LOAD
86415. DEV_MAC_HDX_CFG_SEED_M
86416. DEV_MAC_HDX_CFG_SEED_X
86417. DEV_MAC_HDX_CFG_WEXC_DIS
86418. DEV_MAC_HID
86419. DEV_MAC_HID_ADB_MOUSE_SENDS_KEYCODES
86420. DEV_MAC_HID_KEYBOARD_LOCK_KEYCODES
86421. DEV_MAC_HID_KEYBOARD_SENDS_LINUX_KEYCODES
86422. DEV_MAC_HID_MOUSE_BUTTON2_KEYCODE
86423. DEV_MAC_HID_MOUSE_BUTTON3_KEYCODE
86424. DEV_MAC_HID_MOUSE_BUTTON_EMULATION
86425. DEV_MAC_IFG_CFG
86426. DEV_MAC_IFG_CFG_REDUCED_TX_IFG
86427. DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK
86428. DEV_MAC_IFG_CFG_RX_IFG1
86429. DEV_MAC_IFG_CFG_RX_IFG1_M
86430. DEV_MAC_IFG_CFG_RX_IFG2
86431. DEV_MAC_IFG_CFG_RX_IFG2_M
86432. DEV_MAC_IFG_CFG_RX_IFG2_X
86433. DEV_MAC_IFG_CFG_TX_IFG
86434. DEV_MAC_IFG_CFG_TX_IFG_M
86435. DEV_MAC_IFG_CFG_TX_IFG_X
86436. DEV_MAC_MAXLEN_CFG
86437. DEV_MAC_MODE_CFG
86438. DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA
86439. DEV_MAC_MODE_CFG_FDX_ENA
86440. DEV_MAC_MODE_CFG_GIGA_MODE_ENA
86441. DEV_MAC_STICKY
86442. DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY
86443. DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY
86444. DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY
86445. DEV_MAC_STICKY_RX_JUNK_STICKY
86446. DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY
86447. DEV_MAC_STICKY_TX_ABORT_STICKY
86448. DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY
86449. DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY
86450. DEV_MAC_STICKY_TX_JAM_STICKY
86451. DEV_MAC_STICKY_TX_RETRANSMIT_STICKY
86452. DEV_MAC_TAGS_CFG
86453. DEV_MAC_TAGS_CFG_PB_ENA
86454. DEV_MAC_TAGS_CFG_TAG_ID
86455. DEV_MAC_TAGS_CFG_TAG_ID_M
86456. DEV_MAC_TAGS_CFG_TAG_ID_X
86457. DEV_MAC_TAGS_CFG_VLAN_AWR_ENA
86458. DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA
86459. DEV_MAP
86460. DEV_MAP_BULK_SIZE
86461. DEV_MAX_NR
86462. DEV_MCP55
86463. DEV_MEM
86464. DEV_MESSAGE
86465. DEV_MESSAGE_LOG
86466. DEV_MISCONFIGURED
86467. DEV_MTT
86468. DEV_NAME
86469. DEV_NAME_LEN
86470. DEV_NEED_LINKTIMER
86471. DEV_NEED_LOW_POWER_FIX
86472. DEV_NEED_MSI_FIX
86473. DEV_NEED_PHY_INIT_FIX
86474. DEV_NEED_TIMERIRQ
86475. DEV_NEED_TX_LIMIT
86476. DEV_NEED_TX_LIMIT2
86477. DEV_NOTE_FWAKE
86478. DEV_NOTE_MASK
86479. DEV_NOTF_TYPE
86480. DEV_NOT_CAPABLE
86481. DEV_OFF
86482. DEV_OFF_RST
86483. DEV_OPMODE_AP_BT
86484. DEV_OPMODE_AP_BT_DUAL
86485. DEV_OPMODE_BT_ALONE
86486. DEV_OPMODE_BT_DUAL
86487. DEV_OPMODE_BT_LE_ALONE
86488. DEV_OPMODE_STA_BT
86489. DEV_OPMODE_STA_BT_DUAL
86490. DEV_OPMODE_STA_BT_LE
86491. DEV_OPMODE_WIFI_ALONE
86492. DEV_OPTICAL
86493. DEV_OTHER
86494. DEV_PARPORT
86495. DEV_PARPORT_AUTOPROBE
86496. DEV_PARPORT_BASE_ADDR
86497. DEV_PARPORT_DEFAULT
86498. DEV_PARPORT_DEFAULT_SPINTIME
86499. DEV_PARPORT_DEFAULT_TIMESLICE
86500. DEV_PARPORT_DEVICES
86501. DEV_PARPORT_DEVICES_ACTIVE
86502. DEV_PARPORT_DEVICE_TIMESLICE
86503. DEV_PARPORT_DMA
86504. DEV_PARPORT_IRQ
86505. DEV_PARPORT_MODES
86506. DEV_PARPORT_SPINTIME
86507. DEV_PCS_FX100_CFG
86508. DEV_PCS_FX100_CFG_FEFCHK_ENA
86509. DEV_PCS_FX100_CFG_FEFGEN_ENA
86510. DEV_PCS_FX100_CFG_LINKHYSTTIMER
86511. DEV_PCS_FX100_CFG_LINKHYSTTIMER_M
86512. DEV_PCS_FX100_CFG_LINKHYSTTIMER_X
86513. DEV_PCS_FX100_CFG_LINKHYST_TM_ENA
86514. DEV_PCS_FX100_CFG_LOOPBACK_ENA
86515. DEV_PCS_FX100_CFG_PCS_ENA
86516. DEV_PCS_FX100_CFG_RXBITSEL
86517. DEV_PCS_FX100_CFG_RXBITSEL_M
86518. DEV_PCS_FX100_CFG_RXBITSEL_X
86519. DEV_PCS_FX100_CFG_SD_ENA
86520. DEV_PCS_FX100_CFG_SD_POL
86521. DEV_PCS_FX100_CFG_SD_SEL
86522. DEV_PCS_FX100_CFG_SIGDET_CFG
86523. DEV_PCS_FX100_CFG_SIGDET_CFG_M
86524. DEV_PCS_FX100_CFG_SIGDET_CFG_X
86525. DEV_PCS_FX100_CFG_SWAP_MII_ENA
86526. DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA
86527. DEV_PCS_FX100_STATUS
86528. DEV_PCS_FX100_STATUS_EDGE_POS_PTP
86529. DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M
86530. DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X
86531. DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY
86532. DEV_PCS_FX100_STATUS_FEF_STATUS
86533. DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY
86534. DEV_PCS_FX100_STATUS_SIGNAL_DETECT
86535. DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY
86536. DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY
86537. DEV_PCS_FX100_STATUS_SYNC_STATUS
86538. DEV_PER_PCI
86539. DEV_PM_OPS
86540. DEV_PM_QOS_FLAGS
86541. DEV_PM_QOS_LATENCY_TOLERANCE
86542. DEV_PM_QOS_RESUME_LATENCY
86543. DEV_PORT_MISC
86544. DEV_PORT_MISC_DEV_LOOP_ENA
86545. DEV_PORT_MISC_FWD_CTRL_ENA
86546. DEV_PORT_MISC_FWD_ERROR_ENA
86547. DEV_PORT_MISC_FWD_PAUSE_ENA
86548. DEV_PORT_MISC_HDX_FAST_DIS
86549. DEV_PORT_SPEED
86550. DEV_PPD
86551. DEV_PRES_TIMER_OVERRIDE_ENABLE
86552. DEV_PRINTER
86553. DEV_PROC
86554. DEV_PROP_MAX
86555. DEV_PROP_STRING
86556. DEV_PROP_U16
86557. DEV_PROP_U32
86558. DEV_PROP_U64
86559. DEV_PROP_U8
86560. DEV_PR_ARG
86561. DEV_PR_FMT
86562. DEV_PTP_PREDICT_CFG
86563. DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG
86564. DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M
86565. DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG
86566. DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M
86567. DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X
86568. DEV_QUERY_REG0
86569. DEV_QUERY_REG1
86570. DEV_QUERY_REG2
86571. DEV_QUERY_REG3
86572. DEV_QUERY_REG4
86573. DEV_QUERY_REG5
86574. DEV_QUERY_REG6
86575. DEV_QUERY_REG7
86576. DEV_QUERY_REG8
86577. DEV_RAID
86578. DEV_RAID_SPEED_LIMIT_MAX
86579. DEV_RAID_SPEED_LIMIT_MIN
86580. DEV_RATE_CCK
86581. DEV_RATE_OFDM
86582. DEV_RATE_SHORT_PREAMBLE
86583. DEV_REG_IDX
86584. DEV_REMOUNT_ALL
86585. DEV_REMOVED
86586. DEV_REQUEST
86587. DEV_REV_NUM_BMSK
86588. DEV_REV_NUM_SHFT
86589. DEV_ROLE_MASTER
86590. DEV_ROLE_SLAVE
86591. DEV_RST
86592. DEV_RX_PATH_DELAY
86593. DEV_SCANNER
86594. DEV_SCSI
86595. DEV_SCSI_LOGGING_LEVEL
86596. DEV_SFR_TYPE_AHB
86597. DEV_SFR_TYPE_AXI
86598. DEV_SFR_TYPE_OCP
86599. DEV_SFR_TYPE_PLB
86600. DEV_SFR_WIDTH_16
86601. DEV_SFR_WIDTH_32
86602. DEV_SFR_WIDTH_64
86603. DEV_SFR_WIDTH_8
86604. DEV_SINGLEPOINT
86605. DEV_SKU_1
86606. DEV_SKU_2
86607. DEV_SKU_3
86608. DEV_SKU_4
86609. DEV_SKU_UNKNOWN
86610. DEV_SKU_VF
86611. DEV_SPEED
86612. DEV_SPEED_MASK
86613. DEV_STAT
86614. DEV_STATE_BOXED
86615. DEV_STATE_CMFCHANGE
86616. DEV_STATE_CMFUPDATE
86617. DEV_STATE_DISBAND_PGID
86618. DEV_STATE_DISCONNECTED
86619. DEV_STATE_DISCONNECTED_SENSE_ID
86620. DEV_STATE_DOWN
86621. DEV_STATE_ERR
86622. DEV_STATE_INIT
86623. DEV_STATE_NOT_OPER
86624. DEV_STATE_OFFLINE
86625. DEV_STATE_ONLINE
86626. DEV_STATE_QUIESCE
86627. DEV_STATE_RECOVER
86628. DEV_STATE_RUNNING
86629. DEV_STATE_SENSE_ID
86630. DEV_STATE_STARTWAIT
86631. DEV_STATE_STARTWAIT_RX
86632. DEV_STATE_STARTWAIT_RXTX
86633. DEV_STATE_STARTWAIT_TX
86634. DEV_STATE_STEAL_LOCK
86635. DEV_STATE_STOPPED
86636. DEV_STATE_STOPWAIT
86637. DEV_STATE_STOPWAIT_RX
86638. DEV_STATE_STOPWAIT_RXTX
86639. DEV_STATE_STOPWAIT_TX
86640. DEV_STATE_TIMEOUT_KILL
86641. DEV_STATE_UNINIT
86642. DEV_STATE_UP
86643. DEV_STATE_VERIFY
86644. DEV_STATE_W4SENSE
86645. DEV_STATUS_IN_USE
86646. DEV_STAT_ATTENTION
86647. DEV_STAT_BUSY
86648. DEV_STAT_CHN_END
86649. DEV_STAT_CU_END
86650. DEV_STAT_DEV_END
86651. DEV_STAT_INT
86652. DEV_STAT_STAT_MOD
86653. DEV_STAT_UNIT_CHECK
86654. DEV_STAT_UNIT_EXCEP
86655. DEV_SUPERSPEED
86656. DEV_SUPERSPEEDPLUS
86657. DEV_SUPERSPEED_ANY
86658. DEV_SUS
86659. DEV_SUS_CH
86660. DEV_T1_CHARGER_MASK
86661. DEV_T1_UART_MASK
86662. DEV_T1_USB_MASK
86663. DEV_T2_JIG_MASK
86664. DEV_T2_UART_MASK
86665. DEV_T2_USB_MASK
86666. DEV_TABLE_ENTRY_SIZE
86667. DEV_TAPE
86668. DEV_TTY
86669. DEV_TX_PATH_DELAY
86670. DEV_U2PHY_ULPI
86671. DEV_U2PHY_WIDTH_16
86672. DEV_U2_INACT_TIMEOUT_MSK
86673. DEV_U2_INACT_TIMEOUT_VALUE
86674. DEV_U3PHY_PIPE
86675. DEV_U3PHY_RMMI
86676. DEV_U3PHY_WIDTH_16
86677. DEV_U3PHY_WIDTH_32
86678. DEV_U3PHY_WIDTH_64
86679. DEV_U3PHY_WIDTH_8
86680. DEV_UART
86681. DEV_UNDEFSPEED
86682. DEV_UNKNOWN
86683. DEV_UP
86684. DEV_UPSTREAM
86685. DEV_USB
86686. DEV_USB_CHG
86687. DEV_USB_OTG
86688. DEV_VEND_ID_OFFSET
86689. DEV_VER
86690. DEV_VER_NXP_V1
86691. DEV_VER_TI_V1
86692. DEV_VER_V2
86693. DEV_VER_V3
86694. DEV_WARN
86695. DEV_WORM
86696. DEV_X1
86697. DEV_X16
86698. DEV_X2
86699. DEV_X32
86700. DEV_X4
86701. DEV_X64
86702. DEV_X8
86703. DEW
86704. DEWR
86705. DE_ALPHA
86706. DE_ALPHA_VALUE_MASK
86707. DE_AUI_BNC
86708. DE_AUX_CHANNEL_A
86709. DE_AUX_CHANNEL_A_IVB
86710. DE_BACKGROUND
86711. DE_BACKGROUND_COLOR_MASK
86712. DE_BASE_ADDR_TYPE1
86713. DE_BASE_ADDR_TYPE2
86714. DE_BASE_ADDR_TYPE3
86715. DE_CLIP_BR
86716. DE_CLIP_BR_BOTTOM_MASK
86717. DE_CLIP_BR_RIGHT_MASK
86718. DE_CLIP_TL
86719. DE_CLIP_TL_INHIBIT
86720. DE_CLIP_TL_LEFT_MASK
86721. DE_CLIP_TL_STATUS
86722. DE_CLIP_TL_TOP_MASK
86723. DE_COEFTAB_DATA
86724. DE_COLOR_COMPARE
86725. DE_COLOR_COMPARE_COLOR_MASK
86726. DE_COLOR_COMPARE_MASK
86727. DE_COLOR_COMPARE_MASK_MASK
86728. DE_CONTROL
86729. DE_CONTROL_ACTIVE_BLANK
86730. DE_CONTROL_COMMAND_ALPHA_BLEND
86731. DE_CONTROL_COMMAND_BITBLT
86732. DE_CONTROL_COMMAND_DE_TILE
86733. DE_CONTROL_COMMAND_FONT
86734. DE_CONTROL_COMMAND_HOST_READ
86735. DE_CONTROL_COMMAND_HOST_WRITE
86736. DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP
86737. DE_CONTROL_COMMAND_LINE_DRAW
86738. DE_CONTROL_COMMAND_MASK
86739. DE_CONTROL_COMMAND_RECTANGLE_FILL
86740. DE_CONTROL_COMMAND_RLE_STRIP
86741. DE_CONTROL_COMMAND_ROTATE
86742. DE_CONTROL_COMMAND_SHIFT
86743. DE_CONTROL_COMMAND_SHORT_STROKE
86744. DE_CONTROL_COMMAND_TEXTURE_LOAD
86745. DE_CONTROL_COMMAND_TRAPEZOID_FILL
86746. DE_CONTROL_DIRECTION
86747. DE_CONTROL_EARLY
86748. DE_CONTROL_EARLY_EXT
86749. DE_CONTROL_HOST
86750. DE_CONTROL_LAST_PIXEL
86751. DE_CONTROL_MAJOR
86752. DE_CONTROL_MONO_DATA_16_PACKED
86753. DE_CONTROL_MONO_DATA_32_PACKED
86754. DE_CONTROL_MONO_DATA_8_PACKED
86755. DE_CONTROL_MONO_DATA_MASK
86756. DE_CONTROL_MONO_DATA_NOT_PACKED
86757. DE_CONTROL_MONO_DATA_SHIFT
86758. DE_CONTROL_NORMAL
86759. DE_CONTROL_ONECLK
86760. DE_CONTROL_PATTERN
86761. DE_CONTROL_QUICK_START
86762. DE_CONTROL_REPEAT_ROTATE
86763. DE_CONTROL_ROP2_SOURCE
86764. DE_CONTROL_ROP_MASK
86765. DE_CONTROL_ROP_SELECT
86766. DE_CONTROL_ROTATION_0
86767. DE_CONTROL_ROTATION_180
86768. DE_CONTROL_ROTATION_270
86769. DE_CONTROL_ROTATION_90
86770. DE_CONTROL_ROTATION_MASK
86771. DE_CONTROL_SHORT_STROKE_DIR_0
86772. DE_CONTROL_SHORT_STROKE_DIR_135
86773. DE_CONTROL_SHORT_STROKE_DIR_180
86774. DE_CONTROL_SHORT_STROKE_DIR_225
86775. DE_CONTROL_SHORT_STROKE_DIR_270
86776. DE_CONTROL_SHORT_STROKE_DIR_315
86777. DE_CONTROL_SHORT_STROKE_DIR_45
86778. DE_CONTROL_SHORT_STROKE_DIR_90
86779. DE_CONTROL_SHORT_STROKE_DIR_MASK
86780. DE_CONTROL_STATUS
86781. DE_CONTROL_STEP_X
86782. DE_CONTROL_STEP_Y
86783. DE_CONTROL_STRETCH
86784. DE_CONTROL_TRANSPARENCY
86785. DE_CONTROL_TRANSPARENCY_MATCH
86786. DE_CONTROL_TRANSPARENCY_SELECT
86787. DE_CONTROL_UPDATE_DESTINATION_X
86788. DE_DATA_PORT
86789. DE_DEF_MSG_ENABLE
86790. DE_DELSEL
86791. DE_DESTINATION
86792. DE_DESTINATION_WRAP
86793. DE_DESTINATION_X_MASK
86794. DE_DESTINATION_X_SHIFT
86795. DE_DESTINATION_Y_MASK
86796. DE_DIMENSION
86797. DE_DIMENSION_X_MASK
86798. DE_DIMENSION_X_SHIFT
86799. DE_DIMENSION_Y_ET_MASK
86800. DE_DP_A_HOTPLUG
86801. DE_DP_A_HOTPLUG_IVB
86802. DE_DUMMY_SKB
86803. DE_EDP_PSR_INT_HSW
86804. DE_EEPROM_SIZE
86805. DE_EEPROM_WORDS
86806. DE_EMPHASIS
86807. DE_ERR_INT_IVB
86808. DE_FOREGROUND
86809. DE_FOREGROUND_COLOR_MASK
86810. DE_FREF_DELAY_MASK
86811. DE_FREF_DELAY_SHIFT
86812. DE_FREF_DE_PXQ_SHIFT
86813. DE_FREF_INV_SHIFT
86814. DE_FREF_SEL_DE_VHREF
86815. DE_FREF_SEL_FREF_HDMI
86816. DE_FREF_SEL_FREF_VHREF
86817. DE_FREF_SEL_MASK
86818. DE_FREF_SEL_NONE
86819. DE_FREF_SEL_SHIFT
86820. DE_GLITCH_2
86821. DE_GRAPHICS1
86822. DE_GRAPHICS2
86823. DE_GSE
86824. DE_GSE_IVB
86825. DE_GTT_FAULT
86826. DE_GUCRMR
86827. DE_HAVE_BARRIER_NUMBER
86828. DE_HE_ADDR
86829. DE_HS_ADDR
86830. DE_INVERT
86831. DE_IO
86832. DE_MASK
86833. DE_MASKS
86834. DE_MASKS_BIT_MASK
86835. DE_MASKS_BYTE_MASK
86836. DE_MASTER_IRQ_CONTROL
86837. DE_MAX_MEDIA
86838. DE_MEDIA_AUI
86839. DE_MEDIA_BNC
86840. DE_MEDIA_FIRST
86841. DE_MEDIA_INVALID
86842. DE_MEDIA_LAST
86843. DE_MEDIA_TP
86844. DE_MEDIA_TP_AUTO
86845. DE_MEDIA_TP_FD
86846. DE_MONO_PATTERN_HIGH
86847. DE_MONO_PATTERN_HIGH_PATTERN_MASK
86848. DE_MONO_PATTERN_LOW
86849. DE_MONO_PATTERN_LOW_PATTERN_MASK
86850. DE_NUM_REGS
86851. DE_PCH_EVENT
86852. DE_PCH_EVENT_IVB
86853. DE_PCU_EVENT
86854. DE_PERFORM_COUNTER
86855. DE_PIPEA_CRC_DONE
86856. DE_PIPEA_EVEN_FIELD
86857. DE_PIPEA_FIFO_UNDERRUN
86858. DE_PIPEA_LINE_COMPARE
86859. DE_PIPEA_ODD_FIELD
86860. DE_PIPEA_VBLANK
86861. DE_PIPEA_VBLANK_IVB
86862. DE_PIPEA_VSYNC
86863. DE_PIPEB_CRC_DONE
86864. DE_PIPEB_EVEN_FIELD
86865. DE_PIPEB_FIFO_UNDERRUN
86866. DE_PIPEB_LINE_COMPARE
86867. DE_PIPEB_ODD_FIELD
86868. DE_PIPEB_VBLANK
86869. DE_PIPEB_VBLANK_IVB
86870. DE_PIPEB_VSYNC
86871. DE_PIPEC_VBLANK_IVB
86872. DE_PIPE_CRC_DONE
86873. DE_PIPE_FIFO_UNDERRUN
86874. DE_PIPE_VBLANK
86875. DE_PIPE_VBLANK_IVB
86876. DE_PITCH
86877. DE_PITCH_DESTINATION_MASK
86878. DE_PITCH_DESTINATION_SHIFT
86879. DE_PITCH_SOURCE_MASK
86880. DE_PLANEA_FLIP_DONE
86881. DE_PLANEA_FLIP_DONE_IVB
86882. DE_PLANEB_FLIP_DONE
86883. DE_PLANEB_FLIP_DONE_IVB
86884. DE_PLANEC_FLIP_DONE_IVB
86885. DE_PLANE_FLIP_DONE
86886. DE_PLANE_FLIP_DONE_IVB
86887. DE_POISON
86888. DE_POL
86889. DE_POL_ACTIVE_HIGH
86890. DE_PORT_ADDR_TYPE1
86891. DE_PORT_ADDR_TYPE2
86892. DE_PORT_ADDR_TYPE3
86893. DE_REGS_SIZE
86894. DE_REGS_VER
86895. DE_RING_BYTES
86896. DE_RX_RING_SIZE
86897. DE_SELECT_ACTIVE
86898. DE_SELECT_ACTIVE_BLANK
86899. DE_SELECT_ACTIVE_IS
86900. DE_SETUP_FRAME_WORDS
86901. DE_SETUP_SKB
86902. DE_SMART
86903. DE_SOURCE
86904. DE_SOURCE_WRAP
86905. DE_SOURCE_X_K1_MASK
86906. DE_SOURCE_X_K1_MONO_MASK
86907. DE_SOURCE_X_K1_SHIFT
86908. DE_SOURCE_Y_K2_MASK
86909. DE_SPRITEA_FLIP_DONE
86910. DE_SPRITEA_FLIP_DONE_IVB
86911. DE_SPRITEB_FLIP_DONE
86912. DE_SPRITEB_FLIP_DONE_IVB
86913. DE_SPRITEC_FLIP_DONE_IVB
86914. DE_STATE1
86915. DE_STATE1_DE_ABORT
86916. DE_STATE2
86917. DE_STATE2_DE_FIFO_EMPTY
86918. DE_STATE2_DE_MEM_FIFO_EMPTY
86919. DE_STATE2_DE_STATUS_BUSY
86920. DE_STATUS
86921. DE_STATUS_2D
86922. DE_STATUS_CSC
86923. DE_STRETCH_FORMAT
86924. DE_STRETCH_FORMAT_ADDRESSING_LINEAR
86925. DE_STRETCH_FORMAT_ADDRESSING_MASK
86926. DE_STRETCH_FORMAT_ADDRESSING_SHIFT
86927. DE_STRETCH_FORMAT_ADDRESSING_XY
86928. DE_STRETCH_FORMAT_PATTERN_XY
86929. DE_STRETCH_FORMAT_PATTERN_X_MASK
86930. DE_STRETCH_FORMAT_PATTERN_X_SHIFT
86931. DE_STRETCH_FORMAT_PATTERN_Y_MASK
86932. DE_STRETCH_FORMAT_PATTERN_Y_SHIFT
86933. DE_STRETCH_FORMAT_PIXEL_FORMAT_16
86934. DE_STRETCH_FORMAT_PIXEL_FORMAT_24
86935. DE_STRETCH_FORMAT_PIXEL_FORMAT_32
86936. DE_STRETCH_FORMAT_PIXEL_FORMAT_8
86937. DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK
86938. DE_STRETCH_FORMAT_PIXEL_FORMAT_SHIFT
86939. DE_STRETCH_FORMAT_SOURCE_HEIGHT_MASK
86940. DE_TIMER_LINK
86941. DE_TIMER_NO_LINK
86942. DE_TX_RING_SIZE
86943. DE_VECTOR
86944. DE_VE_ADDR
86945. DE_VID
86946. DE_VIDEO1
86947. DE_VIDEO2
86948. DE_VS_ADDR
86949. DE_WIDTH_H_HI
86950. DE_WIDTH_H_LO
86951. DE_WIDTH_V_HI
86952. DE_WIDTH_V_LO
86953. DE_WINDOW_DESTINATION_BASE
86954. DE_WINDOW_DESTINATION_BASE_ADDRESS_MASK
86955. DE_WINDOW_DESTINATION_BASE_CS
86956. DE_WINDOW_DESTINATION_BASE_EXT
86957. DE_WINDOW_SOURCE_BASE
86958. DE_WINDOW_SOURCE_BASE_ADDRESS_MASK
86959. DE_WINDOW_SOURCE_BASE_CS
86960. DE_WINDOW_SOURCE_BASE_EXT
86961. DE_WINDOW_WIDTH
86962. DE_WINDOW_WIDTH_DST_MASK
86963. DE_WINDOW_WIDTH_DST_SHIFT
86964. DE_WINDOW_WIDTH_SRC_MASK
86965. DE_WRAP
86966. DE_WRAP_X_MASK
86967. DE_WRAP_Y_MASK
86968. DE_eckd_data
86969. DE_fba_data
86970. DF
86971. DFAB_A2_H_CLK
86972. DFAB_A2_RESET
86973. DFAB_ARB0_H_CLK
86974. DFAB_ARB0_RESET
86975. DFAB_ARB1_H_CLK
86976. DFAB_ARB1_RESET
86977. DFAB_CLK
86978. DFAB_CLK_SRC
86979. DFAB_CORE_CLK
86980. DFAB_CORE_RESET
86981. DFAB_SFAB_M_A_CLK
86982. DFAB_SFAB_M_RESET
86983. DFAB_SWAY0_H_CLK
86984. DFAB_SWAY0_RESET
86985. DFAB_SWAY1_H_CLK
86986. DFAB_SWAY1_RESET
86987. DFAR
86988. DFA_FB_A
86989. DFA_FB_B
86990. DFA_FB_BASE_MASK
86991. DFA_FB_C
86992. DFA_FB_D
86993. DFA_FB_ENABLE
86994. DFA_FB_STRIDE_1k
86995. DFA_FB_STRIDE_2k
86996. DFA_FB_STRIDE_4k
86997. DFA_FLAG_VERIFY_STATES
86998. DFA_NOMATCH
86999. DFA_PIX_16BIT_1555
87000. DFA_PIX_16BIT_565
87001. DFA_PIX_24BIT
87002. DFA_PIX_32BIT
87003. DFA_PIX_8BIT
87004. DFA_START
87005. DFB
87006. DFC
87007. DFCCTL
87008. DFCLSRESDB00
87009. DFCLSRESDBPTR0
87010. DFCMEM0
87011. DFCMEM1
87012. DFCMEM2
87013. DFCMEM3
87014. DFCMEM4
87015. DFCMEMCTL
87016. DFCVSAT
87017. DFC_HW_CGC_EN
87018. DFC_WRITE_WAIT_COUNT
87019. DFE
87020. DFE_CFG
87021. DFE_CTRL1
87022. DFE_CTRL2
87023. DFE_CTRL3
87024. DFE_PRIO_0
87025. DFE_PRIO_1
87026. DFE_PRIO_2
87027. DFE_PRIO_3
87028. DFE_RING_REGION_HI
87029. DFE_RING_REGION_LO
87030. DFE_THR_CTRL
87031. DFE_THR_DESC_ACDPTR_HI
87032. DFE_THR_DESC_ACDPTR_LO
87033. DFE_THR_DESC_CTRL
87034. DFE_THR_DESC_DPTR_HI
87035. DFE_THR_DESC_DPTR_LO
87036. DFE_THR_STAT
87037. DFH
87038. DFH_EOL
87039. DFH_ID
87040. DFH_ID_FIU_FME
87041. DFH_ID_FIU_PORT
87042. DFH_NEXT_HDR_OFST
87043. DFH_REVISION
87044. DFH_SIZE
87045. DFH_TYPE
87046. DFH_TYPE_AFU
87047. DFH_TYPE_FIU
87048. DFH_TYPE_PRIVATE
87049. DFIFBLKRST
87050. DFIFOEMP
87051. DFIFOFULL
87052. DFIFO_REG
87053. DFL
87054. DFLAGS
87055. DFLEXDPMLE1_DPMLETC_MASK
87056. DFLEXDPMLE1_DPMLETC_ML0
87057. DFLEXDPMLE1_DPMLETC_ML1_0
87058. DFLEXDPMLE1_DPMLETC_ML3
87059. DFLEXDPMLE1_DPMLETC_ML3_0
87060. DFLEXDPMLE1_DPMLETC_ML3_2
87061. DFLL_CLOSED_LOOP
87062. DFLL_CONFIG
87063. DFLL_CONFIG_DIV_MASK
87064. DFLL_CONFIG_DIV_PRESCALE
87065. DFLL_CTRL
87066. DFLL_CTRL_MODE_MASK
87067. DFLL_DISABLED
87068. DFLL_DROOP_CTRL
87069. DFLL_FREQ_REG_MULT_MASK
87070. DFLL_FREQ_REQ
87071. DFLL_FREQ_REQ_FORCE_ENABLE
87072. DFLL_FREQ_REQ_FORCE_MASK
87073. DFLL_FREQ_REQ_FORCE_SHIFT
87074. DFLL_FREQ_REQ_FREQ_VALID
87075. DFLL_FREQ_REQ_MULT_SHIFT
87076. DFLL_FREQ_REQ_SCALE_MASK
87077. DFLL_FREQ_REQ_SCALE_MAX
87078. DFLL_FREQ_REQ_SCALE_SHIFT
87079. DFLL_I2C_CFG
87080. DFLL_I2C_CFG_ARB_ENABLE
87081. DFLL_I2C_CFG_HS_CODE_MASK
87082. DFLL_I2C_CFG_HS_CODE_SHIFT
87083. DFLL_I2C_CFG_PACKET_ENABLE
87084. DFLL_I2C_CFG_SIZE_MASK
87085. DFLL_I2C_CFG_SIZE_SHIFT
87086. DFLL_I2C_CFG_SLAVE_ADDR_10
87087. DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT
87088. DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT
87089. DFLL_I2C_CLK_DIVISOR
87090. DFLL_I2C_CLK_DIVISOR_FS_SHIFT
87091. DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV
87092. DFLL_I2C_CLK_DIVISOR_HS_SHIFT
87093. DFLL_I2C_CLK_DIVISOR_MASK
87094. DFLL_I2C_CLK_DIVISOR_PREDIV
87095. DFLL_I2C_STS
87096. DFLL_I2C_STS_I2C_LAST_SHIFT
87097. DFLL_I2C_STS_I2C_REQ_PENDING
87098. DFLL_I2C_VDD_REG_ADDR
87099. DFLL_INTR_EN
87100. DFLL_INTR_MAX_MASK
87101. DFLL_INTR_MIN_MASK
87102. DFLL_INTR_STS
87103. DFLL_MONITOR_CTRL
87104. DFLL_MONITOR_CTRL_FREQ
87105. DFLL_MONITOR_DATA
87106. DFLL_MONITOR_DATA_NEW_MASK
87107. DFLL_MONITOR_DATA_VAL_MASK
87108. DFLL_MONITOR_DATA_VAL_SHIFT
87109. DFLL_OPEN_LOOP
87110. DFLL_OUTPUT_CFG
87111. DFLL_OUTPUT_CFG_I2C_ENABLE
87112. DFLL_OUTPUT_CFG_MAX_MASK
87113. DFLL_OUTPUT_CFG_MAX_SHIFT
87114. DFLL_OUTPUT_CFG_MIN_MASK
87115. DFLL_OUTPUT_CFG_MIN_SHIFT
87116. DFLL_OUTPUT_CFG_PWM_DELTA
87117. DFLL_OUTPUT_CFG_PWM_DIV_MASK
87118. DFLL_OUTPUT_CFG_PWM_DIV_SHIFT
87119. DFLL_OUTPUT_CFG_PWM_ENABLE
87120. DFLL_OUTPUT_CFG_SAFE_MASK
87121. DFLL_OUTPUT_CFG_SAFE_SHIFT
87122. DFLL_OUTPUT_FORCE
87123. DFLL_OUTPUT_FORCE_ENABLE
87124. DFLL_OUTPUT_FORCE_VALUE_MASK
87125. DFLL_OUTPUT_FORCE_VALUE_SHIFT
87126. DFLL_PARAMS
87127. DFLL_PARAMS_CF_PARAM_MASK
87128. DFLL_PARAMS_CF_PARAM_SHIFT
87129. DFLL_PARAMS_CG_PARAM_MASK
87130. DFLL_PARAMS_CG_PARAM_SHIFT
87131. DFLL_PARAMS_CG_SCALE
87132. DFLL_PARAMS_CI_PARAM_MASK
87133. DFLL_PARAMS_CI_PARAM_SHIFT
87134. DFLL_PARAMS_FORCE_MODE_MASK
87135. DFLL_PARAMS_FORCE_MODE_SHIFT
87136. DFLL_TUNE0
87137. DFLL_TUNE1
87138. DFLL_TUNE_LOW
87139. DFLL_TUNE_UNINITIALIZED
87140. DFLL_UNINITIALIZED
87141. DFLSTR0
87142. DFLSTR1
87143. DFLT_AXI_DBG_NUM_OF_BEATS
87144. DFLT_COALESCE_WAIT
87145. DFLT_DMA_CAM_NUM_OF_ENTRIES
87146. DFLT_DMA_COMM_Q_HIGH
87147. DFLT_DMA_COMM_Q_LOW
87148. DFLT_DMA_READ_INT_BUF_HIGH
87149. DFLT_DMA_READ_INT_BUF_LOW
87150. DFLT_DMA_WRITE_INT_BUF_HIGH
87151. DFLT_DMA_WRITE_INT_BUF_LOW
87152. DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN
87153. DFLT_FQ_ID
87154. DFLT_HWRM_CMD_TIMEOUT
87155. DFLT_INTER_FRAME_WAIT
87156. DFLT_MSG
87157. DFLT_MSGMAX
87158. DFLT_MSGSIZE
87159. DFLT_MSGSIZEMAX
87160. DFLT_MSG_ENABLE
87161. DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN
87162. DFLT_PORT_CUT_BYTES_FROM_END
87163. DFLT_PORT_ERRORS_TO_DISCARD
87164. DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS
87165. DFLT_PORT_MAX_FRAME_LENGTH
87166. DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV
87167. DFLT_PORT_RX_FIFO_THRESHOLD
87168. DFLT_PS2_MODE
87169. DFLT_QUEUESMAX
87170. DFLT_RESP_BITS_VALID
87171. DFLT_RESP_BIT_MODE
87172. DFLT_RESP_BIT_REPORTING
87173. DFLT_RESP_BIT_SCALING
87174. DFLT_RESP_REMOTE_MODE
87175. DFLT_RESP_SMBUS_BIT
87176. DFLT_RESP_STREAM_MODE
87177. DFLT_RQ_IDX
87178. DFLT_SMBUS_MODE
87179. DFLT_TOTAL_NUM_OF_TASKS
87180. DFLT_VOLUME_LEVEL
87181. DFL_BLOCK_LOCKS
87182. DFL_DLM_RECOVERY
87183. DFL_FIRST_MOUNT
87184. DFL_FIRST_MOUNT_DONE
87185. DFL_FME_BASE
87186. DFL_FPGA_API_VERSION
87187. DFL_FPGA_BASE
87188. DFL_FPGA_CHECK_EXTENSION
87189. DFL_FPGA_DEVT_FME
87190. DFL_FPGA_DEVT_MAX
87191. DFL_FPGA_DEVT_PORT
87192. DFL_FPGA_FEATURE_DEV_FME
87193. DFL_FPGA_FEATURE_DEV_PORT
87194. DFL_FPGA_FME_BRIDGE
87195. DFL_FPGA_FME_MGR
87196. DFL_FPGA_FME_PORT_ASSIGN
87197. DFL_FPGA_FME_PORT_PR
87198. DFL_FPGA_FME_PORT_RELEASE
87199. DFL_FPGA_FME_REGION
87200. DFL_FPGA_GET_API_VERSION
87201. DFL_FPGA_MAGIC
87202. DFL_FPGA_PORT_DMA_MAP
87203. DFL_FPGA_PORT_DMA_UNMAP
87204. DFL_FPGA_PORT_GET_INFO
87205. DFL_FPGA_PORT_GET_REGION_INFO
87206. DFL_FPGA_PORT_RESET
87207. DFL_HD_BASELINE_LATENCY
87208. DFL_IDLE_THRESHOLD
87209. DFL_ID_MAX
87210. DFL_LATENCY_TARGET
87211. DFL_MOUNT_DONE
87212. DFL_NO_DLM_OPS
87213. DFL_PORT_BASE
87214. DFL_PORT_REGION_INDEX_AFU
87215. DFL_PORT_REGION_INDEX_STP
87216. DFL_PORT_REGION_MMAP
87217. DFL_PORT_REGION_READ
87218. DFL_PORT_REGION_WRITE
87219. DFL_RX_BUFFERS
87220. DFL_RX_BUF_SZ
87221. DFL_THROTL_SLICE_HD
87222. DFL_THROTL_SLICE_SSD
87223. DFL_TX_BUFFERS
87224. DFL_TX_BUF_SZ
87225. DFL_UNMOUNT
87226. DFORM
87227. DFP
87228. DFP1IOutputControl
87229. DFP1I_OUTPUT_CONTROL_PARAMETERS
87230. DFP1I_OUTPUT_CONTROL_PS_ALLOCATION
87231. DFP1OutputControl
87232. DFP1XOutputControl
87233. DFP1X_OUTPUT_CONTROL_PARAMETERS
87234. DFP1X_OUTPUT_CONTROL_PS_ALLOCATION
87235. DFP1_OUTPUT_CONTROL_PARAMETERS
87236. DFP1_OUTPUT_CONTROL_PS_ALLOCATION
87237. DFP2IOutputControl
87238. DFP2I_OUTPUT_CONTROL_PARAMETERS
87239. DFP2I_OUTPUT_CONTROL_PS_ALLOCATION
87240. DFP2OutputControl
87241. DFP2_OUTPUT_CONTROL_PARAMETERS
87242. DFP2_OUTPUT_CONTROL_PS_ALLOCATION
87243. DFP_DPMS_STATUS_CHANGE_PARAMETERS
87244. DFP_ENCODER_TYPE_OFFSET
87245. DFP_RDESC_ORIG_SIZE
87246. DFQ_MIN_FREE_ENTRIES
87247. DFQ_MIN_FREE_ENTRIES_0
87248. DFQ_MIN_FREE_ENTRIES_1
87249. DFQ_MIN_FREE_ENTRIES_2
87250. DFQ_MIN_FREE_ENTRIES_3
87251. DFQ_MIN_FREE_ENTRIES_4
87252. DFQ_MIN_FREE_ENTRIES_5
87253. DFQ_MIN_FREE_ENTRIES_6
87254. DFQ_MIN_FREE_ENTRIES_7
87255. DFQ_NUM_ENTRIES
87256. DFQ_NUM_ENTRIES_0
87257. DFQ_NUM_ENTRIES_1
87258. DFQ_NUM_ENTRIES_2
87259. DFQ_NUM_ENTRIES_3
87260. DFQ_NUM_ENTRIES_4
87261. DFQ_NUM_ENTRIES_5
87262. DFQ_NUM_ENTRIES_6
87263. DFQ_NUM_ENTRIES_7
87264. DFQ_NUM_ENTRIES_8
87265. DFQ_SIZE
87266. DFQ_SIZE_0
87267. DFQ_SIZE_1
87268. DFQ_SIZE_2
87269. DFQ_SIZE_3
87270. DFQ_SIZE_4
87271. DFQ_SIZE_5
87272. DFQ_SIZE_6
87273. DFQ_SIZE_7
87274. DFR
87275. DFR_CHANGE_ROW
87276. DFR_DISABLE
87277. DFR_HASH
87278. DFR_HASHSIZE
87279. DFR_INT_INJ
87280. DFR_MAX
87281. DFR_SHOW_QUICKVIEW_ROW
87282. DFS
87283. DFSDM
87284. DFSDM1_CK
87285. DFSDM_AUDIO
87286. DFSDM_AWCFR
87287. DFSDM_AWCFR_AWHTF
87288. DFSDM_AWCFR_AWHTF_MASK
87289. DFSDM_AWCFR_AWLTF
87290. DFSDM_AWCFR_AWLTF_MASK
87291. DFSDM_AWHTR
87292. DFSDM_AWHTR_AWHT
87293. DFSDM_AWHTR_AWHT_MASK
87294. DFSDM_AWHTR_BKAWH
87295. DFSDM_AWHTR_BKAWH_MASK
87296. DFSDM_AWLTR
87297. DFSDM_AWLTR_AWLT
87298. DFSDM_AWLTR_AWLT_MASK
87299. DFSDM_AWLTR_BKAWL
87300. DFSDM_AWLTR_BKAWL_MASK
87301. DFSDM_AWSCDR
87302. DFSDM_AWSCDR_AWFORD
87303. DFSDM_AWSCDR_AWFORD_MASK
87304. DFSDM_AWSCDR_AWFOSR
87305. DFSDM_AWSCDR_AWFOSR_MASK
87306. DFSDM_AWSCDR_BKSCD
87307. DFSDM_AWSCDR_BKSCD_MASK
87308. DFSDM_AWSCDR_SCDT
87309. DFSDM_AWSCDR_SCDT_MASK
87310. DFSDM_AWSR
87311. DFSDM_AWSR_AWHTF
87312. DFSDM_AWSR_AWHTF_MASK
87313. DFSDM_AWSR_AWLTF
87314. DFSDM_AWSR_AWLTF_MASK
87315. DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL
87316. DFSDM_CHANNEL_SPI_CLOCK_INTERNAL
87317. DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING
87318. DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
87319. DFSDM_CHCFGR1
87320. DFSDM_CHCFGR1_CHEN
87321. DFSDM_CHCFGR1_CHEN_MASK
87322. DFSDM_CHCFGR1_CHINSEL
87323. DFSDM_CHCFGR1_CHINSEL_MASK
87324. DFSDM_CHCFGR1_CKABEN
87325. DFSDM_CHCFGR1_CKABEN_MASK
87326. DFSDM_CHCFGR1_CKOUTDIV
87327. DFSDM_CHCFGR1_CKOUTDIV_MASK
87328. DFSDM_CHCFGR1_CKOUTSRC
87329. DFSDM_CHCFGR1_CKOUTSRC_MASK
87330. DFSDM_CHCFGR1_DATMPX
87331. DFSDM_CHCFGR1_DATMPX_MASK
87332. DFSDM_CHCFGR1_DATPACK
87333. DFSDM_CHCFGR1_DATPACK_MASK
87334. DFSDM_CHCFGR1_DFSDMEN
87335. DFSDM_CHCFGR1_DFSDMEN_MASK
87336. DFSDM_CHCFGR1_SCDEN
87337. DFSDM_CHCFGR1_SCDEN_MASK
87338. DFSDM_CHCFGR1_SITP
87339. DFSDM_CHCFGR1_SITP_MASK
87340. DFSDM_CHCFGR1_SPICKSEL
87341. DFSDM_CHCFGR1_SPICKSEL_MASK
87342. DFSDM_CHCFGR2
87343. DFSDM_CHCFGR2_DTRBS
87344. DFSDM_CHCFGR2_DTRBS_MASK
87345. DFSDM_CHCFGR2_OFFSET
87346. DFSDM_CHCFGR2_OFFSET_MASK
87347. DFSDM_CHDATINR
87348. DFSDM_CHWDATR
87349. DFSDM_CNVTIMR
87350. DFSDM_CR1
87351. DFSDM_CR1_AWFSEL
87352. DFSDM_CR1_AWFSEL_MASK
87353. DFSDM_CR1_CFG_MASK
87354. DFSDM_CR1_DFEN
87355. DFSDM_CR1_DFEN_MASK
87356. DFSDM_CR1_FAST
87357. DFSDM_CR1_FAST_MASK
87358. DFSDM_CR1_JDMAEN
87359. DFSDM_CR1_JDMAEN_MASK
87360. DFSDM_CR1_JEXTEN
87361. DFSDM_CR1_JEXTEN_MASK
87362. DFSDM_CR1_JEXTSEL
87363. DFSDM_CR1_JEXTSEL_MASK
87364. DFSDM_CR1_JSCAN
87365. DFSDM_CR1_JSCAN_MASK
87366. DFSDM_CR1_JSWSTART
87367. DFSDM_CR1_JSWSTART_MASK
87368. DFSDM_CR1_JSYNC
87369. DFSDM_CR1_JSYNC_MASK
87370. DFSDM_CR1_RCH
87371. DFSDM_CR1_RCH_MASK
87372. DFSDM_CR1_RCONT
87373. DFSDM_CR1_RCONT_MASK
87374. DFSDM_CR1_RDMAEN
87375. DFSDM_CR1_RDMAEN_MASK
87376. DFSDM_CR1_RSWSTART
87377. DFSDM_CR1_RSWSTART_MASK
87378. DFSDM_CR1_RSYNC
87379. DFSDM_CR1_RSYNC_MASK
87380. DFSDM_CR2
87381. DFSDM_CR2_AWDCH
87382. DFSDM_CR2_AWDCH_MASK
87383. DFSDM_CR2_AWDIE
87384. DFSDM_CR2_AWDIE_MASK
87385. DFSDM_CR2_CKABIE
87386. DFSDM_CR2_CKABIE_MASK
87387. DFSDM_CR2_EXCH
87388. DFSDM_CR2_EXCH_MASK
87389. DFSDM_CR2_IE
87390. DFSDM_CR2_IE_MASK
87391. DFSDM_CR2_JEOCIE
87392. DFSDM_CR2_JEOCIE_MASK
87393. DFSDM_CR2_JOVRIE
87394. DFSDM_CR2_JOVRIE_MASK
87395. DFSDM_CR2_REOCIE
87396. DFSDM_CR2_REOCIE_MASK
87397. DFSDM_CR2_ROVRIE
87398. DFSDM_CR2_ROVRIE_MASK
87399. DFSDM_CR2_SCDIE
87400. DFSDM_CR2_SCDIE_MASK
87401. DFSDM_DATAR_CH_MASK
87402. DFSDM_DATAR_DATA_MASK
87403. DFSDM_DATAR_DATA_OFFSET
87404. DFSDM_DATA_MAX
87405. DFSDM_DATA_RES
87406. DFSDM_DEFAULT_OVERSAMPLING
87407. DFSDM_DMA_BUFFER_SIZE
87408. DFSDM_EXMAX
87409. DFSDM_EXMIN
87410. DFSDM_FASTSINC_ORDER
87411. DFSDM_FCR
87412. DFSDM_FCR_FORD
87413. DFSDM_FCR_FORD_MASK
87414. DFSDM_FCR_FOSR
87415. DFSDM_FCR_FOSR_MASK
87416. DFSDM_FCR_IOSR
87417. DFSDM_FCR_IOSR_MASK
87418. DFSDM_FILTER_BASE_ADR
87419. DFSDM_FILTER_REG_MASK
87420. DFSDM_FILTER_X_BASE_ADR
87421. DFSDM_ICR
87422. DFSDM_ICR_CLRCKABF
87423. DFSDM_ICR_CLRCKABF_CH
87424. DFSDM_ICR_CLRCKABF_CH_MASK
87425. DFSDM_ICR_CLRCKABF_MASK
87426. DFSDM_ICR_CLRJOVRF
87427. DFSDM_ICR_CLRJOVRF_MASK
87428. DFSDM_ICR_CLRROVRF
87429. DFSDM_ICR_CLRROVRF_MASK
87430. DFSDM_ICR_CLRSCDF
87431. DFSDM_ICR_CLRSCDF_CH
87432. DFSDM_ICR_CLRSCDF_CH_MASK
87433. DFSDM_ICR_CLRSCDF_MASK
87434. DFSDM_IIO
87435. DFSDM_ISR
87436. DFSDM_ISR_AWDF
87437. DFSDM_ISR_AWDF_MASK
87438. DFSDM_ISR_CKABF
87439. DFSDM_ISR_CKABF_MASK
87440. DFSDM_ISR_JCIP
87441. DFSDM_ISR_JCIP_MASK
87442. DFSDM_ISR_JEOCF
87443. DFSDM_ISR_JEOCF_MASK
87444. DFSDM_ISR_JOVRF
87445. DFSDM_ISR_JOVRF_MASK
87446. DFSDM_ISR_RCIP
87447. DFSDM_ISR_RCIP_MASK
87448. DFSDM_ISR_REOCF
87449. DFSDM_ISR_REOCF_MASK
87450. DFSDM_ISR_ROVRF
87451. DFSDM_ISR_ROVRF_MASK
87452. DFSDM_ISR_SCDF
87453. DFSDM_ISR_SCDF_MASK
87454. DFSDM_JCHGR
87455. DFSDM_JDATAR
87456. DFSDM_K
87457. DFSDM_MAX_FL_OVERSAMPLING
87458. DFSDM_MAX_INT_OVERSAMPLING
87459. DFSDM_MAX_PERIODS
87460. DFSDM_MAX_PERIOD_SIZE
87461. DFSDM_NB_SINC_ORDER
87462. DFSDM_R
87463. DFSDM_RDATAR
87464. DFSDM_SINC1_ORDER
87465. DFSDM_SINC2_ORDER
87466. DFSDM_SINC3_ORDER
87467. DFSDM_SINC4_ORDER
87468. DFSDM_SINC5_ORDER
87469. DFSDM_TIMEOUT
87470. DFSDM_TIMEOUT_US
87471. DFSMFlushEvents
87472. DFSO_DOWNDIFFERENCTIAL
87473. DFSO_UPTHRESHOLD
87474. DFSR
87475. DFSREF_REFERRAL_SERVER
87476. DFSREF_STORAGE_SERVER
87477. DFSREF_TARGET_FAILBACK
87478. DFSR_FSC_EXTABT_LPAE
87479. DFSR_FSC_EXTABT_nLPAE
87480. DFSR_LPAE
87481. DFS_BYPASS_ENABLE
87482. DFS_CACHE_HTABLE_SIZE
87483. DFS_CACHE_MAX_ENTRIES
87484. DFS_CHANNELS_CONFIG_COMPLETE_EVENT
87485. DFS_CHAN_MOVE_TIME
87486. DFS_DET_RANGE
87487. DFS_DOUBLE_SPEED
87488. DFS_MASK
87489. DFS_NAME_LIST_REF
87490. DFS_NORMAL_SPEED
87491. DFS_PATTERN_DETECTOR_H
87492. DFS_PEAK_MAG_THOLD_POSSIBLY_FALSE
87493. DFS_POOL_STAT_DEC
87494. DFS_POOL_STAT_INC
87495. DFS_PRI_DETECTOR_H
87496. DFS_QUAD_SPEED
87497. DFS_RSSI_POSSIBLY_FALSE
87498. DFS_STATS_RESET_MAGIC
87499. DFS_STAT_INC
87500. DFS_TARGET_SET_BOUNDARY
87501. DFS_TYPE_LINK
87502. DFS_TYPE_ROOT
87503. DFS_VERSION
87504. DFT1_CTL1
87505. DFT1_CTL2
87506. DFT1_STATUS
87507. DFT2_CTL1
87508. DFT2_CTL2
87509. DFT2_STATUS
87510. DFT3_CTL1
87511. DFT3_CTL2
87512. DFT3_STATUS
87513. DFT4_CTL1
87514. DFT4_CTL2
87515. DFT4_STATUS
87516. DFTMODE_CNTRL
87517. DFT_CFG_HEIGHT
87518. DFT_CFG_WIDTH
87519. DFT_OUT__dft_data_MASK
87520. DFT_OUT__dft_data__SHIFT
87521. DFT_PINSTRAPS__DFT_PINSTRAPS_MASK
87522. DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT
87523. DFT_THRESHOLD
87524. DFU_ABORT
87525. DFU_CLRSTATUS
87526. DFU_DETACH
87527. DFU_DNLOAD
87528. DFU_GETSTATE
87529. DFU_GETSTATUS
87530. DFU_UPLOAD
87531. DFW_CMD_CODE_DATA
87532. DFW_CMD_CODE_HDR
87533. DFW_CMD_FUSE
87534. DFW_CMD_INFO
87535. DFW_CMD_PLL
87536. DFX
87537. DFX_BASE__INST0_SEG0
87538. DFX_BASE__INST0_SEG1
87539. DFX_BASE__INST0_SEG2
87540. DFX_BASE__INST0_SEG3
87541. DFX_BASE__INST0_SEG4
87542. DFX_BASE__INST1_SEG0
87543. DFX_BASE__INST1_SEG1
87544. DFX_BASE__INST1_SEG2
87545. DFX_BASE__INST1_SEG3
87546. DFX_BASE__INST1_SEG4
87547. DFX_BASE__INST2_SEG0
87548. DFX_BASE__INST2_SEG1
87549. DFX_BASE__INST2_SEG2
87550. DFX_BASE__INST2_SEG3
87551. DFX_BASE__INST2_SEG4
87552. DFX_BASE__INST3_SEG0
87553. DFX_BASE__INST3_SEG1
87554. DFX_BASE__INST3_SEG2
87555. DFX_BASE__INST3_SEG3
87556. DFX_BASE__INST3_SEG4
87557. DFX_BASE__INST4_SEG0
87558. DFX_BASE__INST4_SEG1
87559. DFX_BASE__INST4_SEG2
87560. DFX_BASE__INST4_SEG3
87561. DFX_BASE__INST4_SEG4
87562. DFX_BUS_EISA
87563. DFX_BUS_TC
87564. DFX_DAP_BASE__INST0_SEG0
87565. DFX_DAP_BASE__INST0_SEG1
87566. DFX_DAP_BASE__INST0_SEG2
87567. DFX_DAP_BASE__INST0_SEG3
87568. DFX_DAP_BASE__INST0_SEG4
87569. DFX_DAP_BASE__INST1_SEG0
87570. DFX_DAP_BASE__INST1_SEG1
87571. DFX_DAP_BASE__INST1_SEG2
87572. DFX_DAP_BASE__INST1_SEG3
87573. DFX_DAP_BASE__INST1_SEG4
87574. DFX_DAP_BASE__INST2_SEG0
87575. DFX_DAP_BASE__INST2_SEG1
87576. DFX_DAP_BASE__INST2_SEG2
87577. DFX_DAP_BASE__INST2_SEG3
87578. DFX_DAP_BASE__INST2_SEG4
87579. DFX_DAP_BASE__INST3_SEG0
87580. DFX_DAP_BASE__INST3_SEG1
87581. DFX_DAP_BASE__INST3_SEG2
87582. DFX_DAP_BASE__INST3_SEG3
87583. DFX_DAP_BASE__INST3_SEG4
87584. DFX_DAP_BASE__INST4_SEG0
87585. DFX_DAP_BASE__INST4_SEG1
87586. DFX_DAP_BASE__INST4_SEG2
87587. DFX_DAP_BASE__INST4_SEG3
87588. DFX_DAP_BASE__INST4_SEG4
87589. DFX_DAP_HWID
87590. DFX_FC_PRH2_PRH1_PRH0
87591. DFX_HWID
87592. DFX_K_FAILURE
87593. DFX_K_HW_TIMEOUT
87594. DFX_K_OUTSTATE
87595. DFX_K_SUCCESS
87596. DFX_MASK_INTERRUPTS
87597. DFX_MMIO
87598. DFX_PRH0_BYTE
87599. DFX_PRH1_BYTE
87600. DFX_PRH2_BYTE
87601. DFX_UNMASK_INTERRUPTS
87602. DFX_board_t
87603. DFX_board_tag
87604. DF_ADDR0_GPIO_53
87605. DF_ADDR0_MMC1_CLK
87606. DF_ADDR1_CLK26MOUTDMD
87607. DF_ADDR1_GPIO_54
87608. DF_ADDR1_MMC1_CMD
87609. DF_ADDR2_CLK13MOUTDMD
87610. DF_ADDR2_GPIO_55
87611. DF_ADDR2_MMC1_DAT0
87612. DF_ADDR3_CLK26MOUTDMD
87613. DF_ADDR3_GPIO_56
87614. DF_ADDR3_MMC1_DAT1
87615. DF_ALE_SM_WEn_ND_ALE
87616. DF_ATA_DEVICE
87617. DF_BASE__INST0_SEG0
87618. DF_BASE__INST0_SEG1
87619. DF_BASE__INST0_SEG2
87620. DF_BASE__INST0_SEG3
87621. DF_BASE__INST0_SEG4
87622. DF_BASE__INST0_SEG5
87623. DF_BASE__INST1_SEG0
87624. DF_BASE__INST1_SEG1
87625. DF_BASE__INST1_SEG2
87626. DF_BASE__INST1_SEG3
87627. DF_BASE__INST1_SEG4
87628. DF_BASE__INST1_SEG5
87629. DF_BASE__INST2_SEG0
87630. DF_BASE__INST2_SEG1
87631. DF_BASE__INST2_SEG2
87632. DF_BASE__INST2_SEG3
87633. DF_BASE__INST2_SEG4
87634. DF_BASE__INST2_SEG5
87635. DF_BASE__INST3_SEG0
87636. DF_BASE__INST3_SEG1
87637. DF_BASE__INST3_SEG2
87638. DF_BASE__INST3_SEG3
87639. DF_BASE__INST3_SEG4
87640. DF_BASE__INST3_SEG5
87641. DF_BASE__INST4_SEG0
87642. DF_BASE__INST4_SEG1
87643. DF_BASE__INST4_SEG2
87644. DF_BASE__INST4_SEG3
87645. DF_BASE__INST4_SEG4
87646. DF_BASE__INST4_SEG5
87647. DF_BASE__INST5_SEG0
87648. DF_BASE__INST5_SEG1
87649. DF_BASE__INST5_SEG2
87650. DF_BASE__INST5_SEG3
87651. DF_BASE__INST5_SEG4
87652. DF_BASE__INST5_SEG5
87653. DF_BASE__INST6_SEG0
87654. DF_BASE__INST6_SEG1
87655. DF_BASE__INST6_SEG2
87656. DF_BASE__INST6_SEG3
87657. DF_BASE__INST6_SEG4
87658. DF_BASE__INST6_SEG5
87659. DF_BASE__INST7_SEG0
87660. DF_BASE__INST7_SEG1
87661. DF_BASE__INST7_SEG2
87662. DF_BASE__INST7_SEG3
87663. DF_BASE__INST7_SEG4
87664. DF_BASE__INST7_SEG5
87665. DF_BOOT_TGT
87666. DF_CLE_SM_OEn_ND_CLE
87667. DF_CLE_nOE_GPIO_48
87668. DF_CLE_nOE_ND_CLE
87669. DF_CONFIGURED
87670. DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK
87671. DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT
87672. DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK
87673. DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT
87674. DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK
87675. DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT
87676. DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK
87677. DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT
87678. DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK
87679. DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT
87680. DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK
87681. DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT
87682. DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK
87683. DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT
87684. DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK
87685. DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT
87686. DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK
87687. DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT
87688. DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK
87689. DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT
87690. DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK
87691. DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT
87692. DF_DHAR
87693. DF_DISABLE_RELOGIN
87694. DF_EMULATED_VPD_UNIT_SERIAL
87695. DF_ENCRYPTION_DISABLE
87696. DF_FIRMWARE_VPD_UNIT_SERIAL
87697. DF_FO_MASKED
87698. DF_HWID
87699. DF_HWIP
87700. DF_INT_RnB_GPIO_51
87701. DF_INT_RnB_ND_INT_RnB
87702. DF_IO0_DF_IO0
87703. DF_IO0_GPIO_43
87704. DF_IO0_ND_IO0
87705. DF_IO10_DF_IO10
87706. DF_IO10_GPIO_33
87707. DF_IO10_MMC2_DAT3
87708. DF_IO10_ND_IO10
87709. DF_IO11_DF_IO11
87710. DF_IO11_GPIO_32
87711. DF_IO11_MMC2_DAT2
87712. DF_IO11_ND_IO11
87713. DF_IO12_DF_IO12
87714. DF_IO12_GPIO_31
87715. DF_IO12_MMC2_DAT1
87716. DF_IO12_ND_IO12
87717. DF_IO13_DF_IO13
87718. DF_IO13_GPIO_30
87719. DF_IO13_MMC2_DAT0
87720. DF_IO13_ND_IO13
87721. DF_IO14_DF_IO14
87722. DF_IO14_GPIO_29
87723. DF_IO14_MMC2_CLK
87724. DF_IO14_ND_IO14
87725. DF_IO15_DF_IO15
87726. DF_IO15_GPIO_28
87727. DF_IO15_MMC2_CMD
87728. DF_IO15_ND_IO15
87729. DF_IO1_DF_IO1
87730. DF_IO1_GPIO_42
87731. DF_IO1_ND_IO1
87732. DF_IO2_DF_IO2
87733. DF_IO2_GPIO_41
87734. DF_IO2_ND_IO2
87735. DF_IO3_DF_IO3
87736. DF_IO3_GPIO_40
87737. DF_IO3_ND_IO3
87738. DF_IO4_DF_IO4
87739. DF_IO4_GPIO_39
87740. DF_IO4_ND_IO4
87741. DF_IO5_DF_IO5
87742. DF_IO5_GPIO_38
87743. DF_IO5_ND_IO5
87744. DF_IO6_DF_IO6
87745. DF_IO6_GPIO_37
87746. DF_IO6_ND_IO6
87747. DF_IO7_DF_IO7
87748. DF_IO7_GPIO_36
87749. DF_IO7_ND_IO7
87750. DF_IO8_DF_IO8
87751. DF_IO8_GPIO_35
87752. DF_IO8_ND_IO8
87753. DF_IO9_DF_IO9
87754. DF_IO9_GPIO_34
87755. DF_IO9_ND_IO9
87756. DF_IO9_USB_P2_7
87757. DF_IO_BIT
87758. DF_ISNS_DISCOVERED
87759. DF_MEDIA_STATUS_ENABLED
87760. DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK
87761. DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT
87762. DF_RDESC_ORIG_SIZE
87763. DF_RDY0_DF_RDY0
87764. DF_READ_ONLY
87765. DF_RELOGIN
87766. DF_REMOVABLE_MEDIA
87767. DF_REn_DF_REn
87768. DF_RX_BIT
87769. DF_S
87770. DF_SCLK_E_GPIO_52
87771. DF_SNIFF_MODE_ENABLE
87772. DF_SWAP32
87773. DF_SWITCH_TYPE_COUNT
87774. DF_SWITCH_TYPE_FAST
87775. DF_SWITCH_TYPE_SLOW
87776. DF_SWITCH_TYPE_e
87777. DF_TX_BIT
87778. DF_USING_ALIAS
87779. DF_USING_UDEV_PATH
87780. DF_V1_7_MGCG
87781. DF_V1_7_MGCG_DISABLE
87782. DF_V1_7_MGCG_ENABLE_00_CYCLE_DELAY
87783. DF_V1_7_MGCG_ENABLE_01_CYCLE_DELAY
87784. DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY
87785. DF_V1_7_MGCG_ENABLE_31_CYCLE_DELAY
87786. DF_V1_7_MGCG_ENABLE_63_CYCLE_DELAY
87787. DF_V3_6_GET_EVENT
87788. DF_V3_6_GET_INSTANCE
87789. DF_V3_6_GET_UNITMASK
87790. DF_V3_6_MAX_COUNTERS
87791. DF_V3_6_MGCG
87792. DF_V3_6_MGCG_DISABLE
87793. DF_V3_6_MGCG_ENABLE_00_CYCLE_DELAY
87794. DF_V3_6_MGCG_ENABLE_01_CYCLE_DELAY
87795. DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY
87796. DF_V3_6_MGCG_ENABLE_31_CYCLE_DELAY
87797. DF_V3_6_MGCG_ENABLE_63_CYCLE_DELAY
87798. DF_V3_6_PERFMON_OVERFLOW
87799. DF_VAL
87800. DF_VECTOR
87801. DF_WEn_DF_WEn
87802. DF_nADV1_ALE_DF_nADV1
87803. DF_nADV1_ALE_GPIO_49
87804. DF_nADV1_ALE_ND_ALE
87805. DF_nADV2_ALE_DF_nADV2
87806. DF_nADV2_ALE_GPIO_50
87807. DF_nADV2_ALE_ND_ALE
87808. DF_nADV2_ALE_nCS3
87809. DF_nCS0_DF_nCS0
87810. DF_nCS0_GPIO_44
87811. DF_nCS0_ND_nCS0
87812. DF_nCS0_SM_nCS2_nCS0
87813. DF_nCS0_nCS2
87814. DF_nCS1_DF_nCS1
87815. DF_nCS1_GPIO_45
87816. DF_nCS1_ND_nCS1
87817. DF_nCS1_nCS3
87818. DF_nRE_nOE_DF_nOE
87819. DF_nRE_nOE_GPIO_47
87820. DF_nRE_nOE_ND_nRE
87821. DF_nWE_DF_nWE
87822. DF_nWE_GPIO_46
87823. DF_nWE_ND_nWE
87824. DG00X_ADDR_BASE
87825. DG00X_OFFSET_CLOCK_SOURCE
87826. DG00X_OFFSET_DETECT_EXTERNAL
87827. DG00X_OFFSET_EXTERNAL_RATE
87828. DG00X_OFFSET_ISOC_CHANNELS
87829. DG00X_OFFSET_LOCAL_RATE
87830. DG00X_OFFSET_MESSAGE_ADDR
87831. DG00X_OFFSET_MMC
87832. DG00X_OFFSET_OPT_IFACE_MODE
87833. DG00X_OFFSET_STREAMING_SET
87834. DG00X_OFFSET_STREAMING_STATE
87835. DG0_MARK
87836. DG1_MARK
87837. DG2_MARK
87838. DG3_MARK
87839. DG4_MARK
87840. DG5_MARK
87841. DGCS
87842. DGM
87843. DGM_CMD_BIT
87844. DGM_FLOW_OFF
87845. DGM_FLOW_ON
87846. DGM_MTU
87847. DGPR
87848. DGPU_VI_PP_SMC_H
87849. DGT_CLK_CTL
87850. DGT_CLK_CTL_DIV_4
87851. DHAR
87852. DHAT_CMD
87853. DHBA_CMD
87854. DHBA_REQ_SIZE
87855. DHBA_RSP_SIZE
87856. DHCPACK
87857. DHCPDECLINE
87858. DHCPDISCOVER
87859. DHCPINFORM
87860. DHCPNAK
87861. DHCPOFFER
87862. DHCPRELEASE
87863. DHCPREQUEST
87864. DHCPV6_RAS_PORT
87865. DHCP_CLIENT_PORT
87866. DHCP_SERVER_PORT
87867. DHDET
87868. DHDET_HDEF
87869. DHDET_HDES
87870. DHP
87871. DHT
87872. DHT01
87873. DHT01_HBPS
87874. DHT01_HT
87875. DHT02
87876. DHT02_HAS
87877. DHT02_HLBS
87878. DHT03
87879. DHT03_HFPS
87880. DHT03_HRBS
87881. DHT11_AMBIG_HIGH
87882. DHT11_AMBIG_LOW
87883. DHT11_BITS_PER_READ
87884. DHT11_DATA_VALID_TIME
87885. DHT11_EDGES_PER_READ
87886. DHT11_EDGES_PREAMBLE
87887. DHT11_MIN_TIMERES
87888. DHT11_START_TRANSMISSION_MAX
87889. DHT11_START_TRANSMISSION_MIN
87890. DHT11_THRESHOLD
87891. DH_KPP_SECRET_MIN_SIZE
87892. DH_TEST__DH_TEST_MASK
87893. DH_TEST__DH_TEST__SHIFT
87894. DI
87895. DIAG204_CPU_CAPPED
87896. DIAG204_CPU_NAME_LEN
87897. DIAG204_CPU_ONLINE
87898. DIAG204_INFO_EXT
87899. DIAG204_INFO_SIMPLE
87900. DIAG204_LPAR_NAME_LEN
87901. DIAG204_LPAR_PHYS_FLG
87902. DIAG204_SUBC_RSI
87903. DIAG204_SUBC_STIB4
87904. DIAG204_SUBC_STIB6
87905. DIAG204_SUBC_STIB7
87906. DIAG26C_GET_MAC
87907. DIAG26C_MAC_SERVICES
87908. DIAG26C_PORT_VNIC
87909. DIAG26C_VERSION2
87910. DIAG26C_VERSION6_VM65918
87911. DIAG26C_VNIC_INFO
87912. DIAG304_CMD_MAX
87913. DIAG304_QUERY_PRP
87914. DIAG304_SET_CAPPING
87915. DIAG304_SET_WEIGHTS
87916. DIAG308_LOAD_CLEAR
87917. DIAG308_LOAD_NORMAL_DUMP
87918. DIAG308_RC_NOCONFIG
87919. DIAG308_RC_OK
87920. DIAG308_REL_HSA
87921. DIAG308_SCPDATA_OFFSET
87922. DIAG308_SCPDATA_SIZE
87923. DIAG308_SET
87924. DIAG308_STORE
87925. DIAG308_VMPARM_SIZE
87926. DIAGF
87927. DIAG_ACCESS_CE_TIMEOUT_US
87928. DIAG_ACCESS_CE_WAIT_US
87929. DIAG_BASE
87930. DIAG_BUFFER_START
87931. DIAG_CODE
87932. DIAG_CONFIG
87933. DIAG_COUNTER
87934. DIAG_DATA_UPLOAD_HEADER
87935. DIAG_DEV_ROWS
87936. DIAG_DL
87937. DIAG_DL1
87938. DIAG_DL2
87939. DIAG_FTP_RET_EBUSY
87940. DIAG_FTP_RET_EIO
87941. DIAG_FTP_RET_EPERM
87942. DIAG_FTP_RET_OK
87943. DIAG_FTP_STAT_EBASE
87944. DIAG_FTP_STAT_LDFAIL
87945. DIAG_FTP_STAT_LDNPERM
87946. DIAG_FTP_STAT_LDNRUNS
87947. DIAG_FTP_STAT_LDRUNS
87948. DIAG_FTP_STAT_OK
87949. DIAG_FTP_STAT_PGCC
87950. DIAG_FTP_STAT_PGIOE
87951. DIAG_FTP_STAT_TIMEOUT
87952. DIAG_HDR_LEN
87953. DIAG_MASK
87954. DIAG_MAX_BLOCKS
87955. DIAG_MAX_RETRIES
87956. DIAG_MODE_SET
87957. DIAG_NORMAL
87958. DIAG_OPEN
87959. DIAG_OVERLOAD
87960. DIAG_RESET_ADAPTER
87961. DIAG_SHORTGND
87962. DIAG_SIZE
87963. DIAG_STAT_X008
87964. DIAG_STAT_X00C
87965. DIAG_STAT_X010
87966. DIAG_STAT_X014
87967. DIAG_STAT_X044
87968. DIAG_STAT_X064
87969. DIAG_STAT_X09C
87970. DIAG_STAT_X0DC
87971. DIAG_STAT_X204
87972. DIAG_STAT_X210
87973. DIAG_STAT_X224
87974. DIAG_STAT_X250
87975. DIAG_STAT_X258
87976. DIAG_STAT_X26C
87977. DIAG_STAT_X288
87978. DIAG_STAT_X2C4
87979. DIAG_STAT_X2FC
87980. DIAG_STAT_X304
87981. DIAG_STAT_X308
87982. DIAG_STAT_X318
87983. DIAG_STAT_X500
87984. DIAG_SUB_HDR_LEN
87985. DIAG_TIMEOUT
87986. DIAG_TRANSFER_LIMIT
87987. DIAG_UL
87988. DIAG_WDOG_BUSY
87989. DIAG_WRITE_ENABLE
87990. DIAG_X
87991. DIAG_Y
87992. DIALOG_BOX
87993. DIALOG_MENU_BACK
87994. DIALOG_MENU_FORE
87995. DIALOG_PLUS
87996. DIALOG_TEXT
87997. DIB0070S_P1A
87998. DIB0070_H
87999. DIB0070_P1D
88000. DIB0070_P1F
88001. DIB0070_P1G
88002. DIB0090_H
88003. DIB0700_DEFAULT_DEVICE_PROPERTIES
88004. DIB0700_DEFAULT_STREAMING_CONFIG
88005. DIB0700_NUM_FRONTENDS
88006. DIB3000MB_BERLEN_DEFAULT
88007. DIB3000MB_BERLEN_LONG
88008. DIB3000MB_BERLEN_MEDIUM
88009. DIB3000MB_BERLEN_SHORT
88010. DIB3000MB_CLOCK_DEFAULT
88011. DIB3000MB_CLOCK_DIVERSITY
88012. DIB3000MB_DATA_DIVERSITY_IN_OFF
88013. DIB3000MB_DATA_DIVERSITY_IN_ON
88014. DIB3000MB_DDS_FREQ_LSB
88015. DIB3000MB_DDS_FREQ_MSB
88016. DIB3000MB_DEVICE_ID
88017. DIB3000MB_ELECT_OUT_MODE_OFF
88018. DIB3000MB_ELECT_OUT_MODE_ON
88019. DIB3000MB_FIFO_142
88020. DIB3000MB_FIFO_146
88021. DIB3000MB_FIFO_147
88022. DIB3000MB_FIFO_ACTIVATE
88023. DIB3000MB_FIFO_INHIBIT
88024. DIB3000MB_IMPNOISE_DEFAULT
88025. DIB3000MB_IMPNOISE_FIXED
88026. DIB3000MB_IMPNOISE_MOBILE
88027. DIB3000MB_IMPNOISE_OFF
88028. DIB3000MB_IRQ_EVENT_MASK
88029. DIB3000MB_ISI_ACTIVATE
88030. DIB3000MB_ISI_INHIBIT
88031. DIB3000MB_LOCK0_DEFAULT
88032. DIB3000MB_LOCK1_DEFAULT
88033. DIB3000MB_LOCK1_SEARCH_2048
88034. DIB3000MB_LOCK1_SEARCH_4
88035. DIB3000MB_LOCK2_DEFAULT
88036. DIB3000MB_MOBILE_ALGO_OFF
88037. DIB3000MB_MOBILE_ALGO_ON
88038. DIB3000MB_MOBILE_MODE_OFF
88039. DIB3000MB_MOBILE_MODE_ON
88040. DIB3000MB_MOBILE_MODE_QAM_64
88041. DIB3000MB_MOBILE_MODE_QAM_OFF
88042. DIB3000MB_MOBILE_MODE_QAM_QPSK_16
88043. DIB3000MB_MPEG2_OUT_MODE_188
88044. DIB3000MB_MPEG2_OUT_MODE_204
88045. DIB3000MB_MULTI_DEMOD_LSB
88046. DIB3000MB_MULTI_DEMOD_MSB
88047. DIB3000MB_NUM_PIDS
88048. DIB3000MB_OUTPUT_MODE_CONT_CLK
88049. DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
88050. DIB3000MB_OUTPUT_MODE_GATED_CLK
88051. DIB3000MB_OUTPUT_MODE_SERIAL
88052. DIB3000MB_OUTPUT_MODE_SLAVE
88053. DIB3000MB_PHASE_NOISE_DEFAULT
88054. DIB3000MB_PID_PARSE_ACTIVATE
88055. DIB3000MB_PID_PARSE_INHIBIT
88056. DIB3000MB_POWER_DOWN
88057. DIB3000MB_POWER_UP
88058. DIB3000MB_REG_AGC1_VALUE
88059. DIB3000MB_REG_AGC2_VALUE
88060. DIB3000MB_REG_AGC_LOCK
88061. DIB3000MB_REG_AGC_POWER
88062. DIB3000MB_REG_AS_IRQ_PENDING
88063. DIB3000MB_REG_BERLEN
88064. DIB3000MB_REG_BER_LSB
88065. DIB3000MB_REG_BER_MSB
88066. DIB3000MB_REG_CARRIER_LOCK
88067. DIB3000MB_REG_CLOCK
88068. DIB3000MB_REG_DATA_IN_DIVERSITY
88069. DIB3000MB_REG_DDS_FREQ_LSB
88070. DIB3000MB_REG_DDS_FREQ_MSB
88071. DIB3000MB_REG_DDS_INV
88072. DIB3000MB_REG_DDS_VALUE_LSB
88073. DIB3000MB_REG_DDS_VALUE_MSB
88074. DIB3000MB_REG_ELECT_OUT_MODE
88075. DIB3000MB_REG_FFT
88076. DIB3000MB_REG_FFT_WINDOW_POS
88077. DIB3000MB_REG_FIFO
88078. DIB3000MB_REG_FIFO_142
88079. DIB3000MB_REG_FIFO_146
88080. DIB3000MB_REG_FIFO_147
88081. DIB3000MB_REG_FIRST_PID
88082. DIB3000MB_REG_GUARD_TIME
88083. DIB3000MB_REG_IRQ_EVENT_MASK
88084. DIB3000MB_REG_ISI
88085. DIB3000MB_REG_LOCK0_MASK
88086. DIB3000MB_REG_LOCK0_VALUE
88087. DIB3000MB_REG_LOCK1_MASK
88088. DIB3000MB_REG_LOCK1_VALUE
88089. DIB3000MB_REG_LOCK2_MASK
88090. DIB3000MB_REG_LOCK2_VALUE
88091. DIB3000MB_REG_MER_LSB
88092. DIB3000MB_REG_MER_MSB
88093. DIB3000MB_REG_MOBILE_ALGO
88094. DIB3000MB_REG_MOBILE_MODE
88095. DIB3000MB_REG_MOBILE_MODE_QAM
88096. DIB3000MB_REG_MOBILE_NOISE_LSB
88097. DIB3000MB_REG_MOBILE_NOISE_MSB
88098. DIB3000MB_REG_MPEG2_OUT_MODE
88099. DIB3000MB_REG_MULTI_DEMOD_LSB
88100. DIB3000MB_REG_MULTI_DEMOD_MSB
88101. DIB3000MB_REG_NOISE_POWER_LSB
88102. DIB3000MB_REG_NOISE_POWER_MSB
88103. DIB3000MB_REG_OUTPUT_MODE
88104. DIB3000MB_REG_PACKET_ERROR_RATE
88105. DIB3000MB_REG_PHASE_NOISE
88106. DIB3000MB_REG_PID_PARSE
88107. DIB3000MB_REG_POWER_CONTROL
88108. DIB3000MB_REG_QAM
88109. DIB3000MB_REG_RESET_DEVICE
88110. DIB3000MB_REG_RESTART
88111. DIB3000MB_REG_RF_POWER
88112. DIB3000MB_REG_SEQ
88113. DIB3000MB_REG_SIGNAL_POWER
88114. DIB3000MB_REG_SYNC_IMPROVEMENT
88115. DIB3000MB_REG_TIMING_OFFSET_LSB
88116. DIB3000MB_REG_TIMING_OFFSET_MSB
88117. DIB3000MB_REG_TPS_1
88118. DIB3000MB_REG_TPS_2
88119. DIB3000MB_REG_TPS_3
88120. DIB3000MB_REG_TPS_4
88121. DIB3000MB_REG_TPS_5
88122. DIB3000MB_REG_TPS_CELL_ID
88123. DIB3000MB_REG_TPS_CODE_RATE_HP
88124. DIB3000MB_REG_TPS_CODE_RATE_LP
88125. DIB3000MB_REG_TPS_FFT
88126. DIB3000MB_REG_TPS_GUARD_TIME
88127. DIB3000MB_REG_TPS_HRCH
88128. DIB3000MB_REG_TPS_LOCK
88129. DIB3000MB_REG_TPS_QAM
88130. DIB3000MB_REG_TPS_VIT_ALPHA
88131. DIB3000MB_REG_TS_RS_LOCK
88132. DIB3000MB_REG_TS_SYNC_LOCK
88133. DIB3000MB_REG_TUNER
88134. DIB3000MB_REG_UNC
88135. DIB3000MB_REG_UNK_106
88136. DIB3000MB_REG_UNK_107
88137. DIB3000MB_REG_UNK_108
88138. DIB3000MB_REG_UNK_121
88139. DIB3000MB_REG_UNK_122
88140. DIB3000MB_REG_UNK_68
88141. DIB3000MB_REG_UNK_69
88142. DIB3000MB_REG_UNK_71
88143. DIB3000MB_REG_UNK_77
88144. DIB3000MB_REG_UNK_78
88145. DIB3000MB_REG_UNK_92
88146. DIB3000MB_REG_UNK_96
88147. DIB3000MB_REG_UNK_97
88148. DIB3000MB_REG_VIT_ALPHA
88149. DIB3000MB_REG_VIT_CODE_RATE
88150. DIB3000MB_REG_VIT_HP
88151. DIB3000MB_REG_VIT_HRCH
88152. DIB3000MB_REG_VIT_INDICATOR
88153. DIB3000MB_REG_VIT_LCK
88154. DIB3000MB_RESET_DEVICE
88155. DIB3000MB_RESET_DEVICE_RST
88156. DIB3000MB_RESTART_AGC
88157. DIB3000MB_RESTART_AUTO_SEARCH
88158. DIB3000MB_RESTART_CTRL
88159. DIB3000MB_RESTART_OFF
88160. DIB3000MB_SYNC_IMPROVE_2K_1_8
88161. DIB3000MB_SYNC_IMPROVE_DEFAULT
88162. DIB3000MB_UNK_106
88163. DIB3000MB_UNK_107
88164. DIB3000MB_UNK_108
88165. DIB3000MB_UNK_121_2K
88166. DIB3000MB_UNK_121_DEFAULT
88167. DIB3000MB_UNK_122
88168. DIB3000MB_UNK_68
88169. DIB3000MB_UNK_69
88170. DIB3000MB_UNK_71
88171. DIB3000MB_UNK_77
88172. DIB3000MB_UNK_78
88173. DIB3000MB_UNK_92
88174. DIB3000MB_UNK_96
88175. DIB3000MB_UNK_97
88176. DIB3000MC
88177. DIB3000MC_DEVICE_ID
88178. DIB3000MC_H
88179. DIB3000P_DEVICE_ID
88180. DIB3000_ACTIVATE_PID_FILTERING
88181. DIB3000_ALPHA_0
88182. DIB3000_ALPHA_1
88183. DIB3000_ALPHA_2
88184. DIB3000_ALPHA_4
88185. DIB3000_CONSTELLATION_16QAM
88186. DIB3000_CONSTELLATION_64QAM
88187. DIB3000_CONSTELLATION_QPSK
88188. DIB3000_DDS_INVERSION_OFF
88189. DIB3000_DDS_INVERSION_ON
88190. DIB3000_FEC_1_2
88191. DIB3000_FEC_2_3
88192. DIB3000_FEC_3_4
88193. DIB3000_FEC_5_6
88194. DIB3000_FEC_7_8
88195. DIB3000_GUARD_TIME_1_16
88196. DIB3000_GUARD_TIME_1_32
88197. DIB3000_GUARD_TIME_1_4
88198. DIB3000_GUARD_TIME_1_8
88199. DIB3000_H
88200. DIB3000_HRCH_OFF
88201. DIB3000_HRCH_ON
88202. DIB3000_I2C_ID_DIBCOM
88203. DIB3000_REG_DEVICE_ID
88204. DIB3000_REG_MANUFACTOR_ID
88205. DIB3000_SELECT_HP
88206. DIB3000_SELECT_LP
88207. DIB3000_TRANSMISSION_MODE_2K
88208. DIB3000_TRANSMISSION_MODE_8K
88209. DIB3000_TUNER_WRITE_DISABLE
88210. DIB3000_TUNER_WRITE_ENABLE
88211. DIB7000
88212. DIB7000MC
88213. DIB7000M_GPIO_DEFAULT_DIRECTIONS
88214. DIB7000M_GPIO_DEFAULT_PWM_POS
88215. DIB7000M_GPIO_DEFAULT_VALUES
88216. DIB7000M_GPIO_PWM_POS0
88217. DIB7000M_GPIO_PWM_POS1
88218. DIB7000M_GPIO_PWM_POS2
88219. DIB7000M_GPIO_PWM_POS3
88220. DIB7000M_H
88221. DIB7000M_POWER_ALL
88222. DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD
88223. DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD
88224. DIB7000M_POWER_INTERFACE_ONLY
88225. DIB7000M_POWER_INTERF_ANALOG_AGC
88226. DIB7000M_POWER_NO
88227. DIB7000P
88228. DIB7000P_GPIO_DEFAULT_DIRECTIONS
88229. DIB7000P_GPIO_DEFAULT_PWM_POS
88230. DIB7000P_GPIO_DEFAULT_VALUES
88231. DIB7000P_GPIO_PWM_POS0
88232. DIB7000P_GPIO_PWM_POS1
88233. DIB7000P_GPIO_PWM_POS2
88234. DIB7000P_GPIO_PWM_POS3
88235. DIB7000P_H
88236. DIB7000P_POWER_ALL
88237. DIB7000P_POWER_ANALOG_ADC
88238. DIB7000P_POWER_INTERFACE_ONLY
88239. DIB8000
88240. DIB8000_GPIO_DEFAULT_DIRECTIONS
88241. DIB8000_GPIO_DEFAULT_PWM_POS
88242. DIB8000_GPIO_DEFAULT_VALUES
88243. DIB8000_GPIO_PWM_POS0
88244. DIB8000_GPIO_PWM_POS1
88245. DIB8000_GPIO_PWM_POS2
88246. DIB8000_GPIO_PWM_POS3
88247. DIB8000_H
88248. DIB8000_POWER_ALL
88249. DIB8000_POWER_INTERFACE_ONLY
88250. DIB9000_GPIO_DEFAULT_DIRECTIONS
88251. DIB9000_GPIO_DEFAULT_PWM_POS
88252. DIB9000_GPIO_DEFAULT_VALUES
88253. DIB9000_H
88254. DIB9000_MSG_CACHE_SIZE
88255. DIB9000_PID_FILTER
88256. DIB9000_PID_FILTER_CTRL
88257. DIB9000_POWER_ALL
88258. DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD
88259. DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD
88260. DIB9000_POWER_INTERFACE_ONLY
88261. DIB9000_POWER_INTERF_ANALOG_AGC
88262. DIB9000_POWER_NO
88263. DIBCOM52
88264. DIBTX_ON_HOSTBUS
88265. DIBUSB_IOCTL_CMD_DISABLE_STREAM
88266. DIBUSB_IOCTL_CMD_ENABLE_STREAM
88267. DIBUSB_IOCTL_CMD_POWER_MODE
88268. DIBUSB_IOCTL_POWER_SLEEP
88269. DIBUSB_IOCTL_POWER_WAKEUP
88270. DIBUSB_RC_HAUPPAUGE_KEY_EMPTY
88271. DIBUSB_RC_HAUPPAUGE_KEY_PRESSED
88272. DIBUSB_REQ_I2C_READ
88273. DIBUSB_REQ_I2C_WRITE
88274. DIBUSB_REQ_INTR_READ
88275. DIBUSB_REQ_POLL_REMOTE
88276. DIBUSB_REQ_SET_IOCTL
88277. DIBUSB_REQ_SET_STREAMING_MODE
88278. DIBUSB_REQ_START_DEMOD
88279. DIBUSB_REQ_START_READ
88280. DIBX000_ADC_OFF
88281. DIBX000_ADC_ON
88282. DIBX000_COMMON_H
88283. DIBX000_I2C_INTERFACE_GPIO_1_2
88284. DIBX000_I2C_INTERFACE_GPIO_3_4
88285. DIBX000_I2C_INTERFACE_GPIO_6_7
88286. DIBX000_I2C_INTERFACE_TUNER
88287. DIBX000_SLOW_ADC_OFF
88288. DIBX000_SLOW_ADC_ON
88289. DIBX000_VBG_DISABLE
88290. DIBX000_VBG_ENABLE
88291. DIC
88292. DICE_CATEGORY_ID
88293. DICE_EXT_APP_APPLICATION_OFFSET
88294. DICE_EXT_APP_APPLICATION_SIZE
88295. DICE_EXT_APP_CAPS_OFFSET
88296. DICE_EXT_APP_CAPS_SIZE
88297. DICE_EXT_APP_CMD_OFFSET
88298. DICE_EXT_APP_CMD_SIZE
88299. DICE_EXT_APP_CURRENT_OFFSET
88300. DICE_EXT_APP_CURRENT_SIZE
88301. DICE_EXT_APP_MIXER_OFFSET
88302. DICE_EXT_APP_MIXER_SIZE
88303. DICE_EXT_APP_PEAK_OFFSET
88304. DICE_EXT_APP_PEAK_SIZE
88305. DICE_EXT_APP_ROUTER_OFFSET
88306. DICE_EXT_APP_ROUTER_SIZE
88307. DICE_EXT_APP_SPACE
88308. DICE_EXT_APP_STANDALONE_OFFSET
88309. DICE_EXT_APP_STANDALONE_SIZE
88310. DICE_EXT_APP_STREAM_OFFSET
88311. DICE_EXT_APP_STREAM_SIZE
88312. DICE_EXT_SYNC_OFFSET
88313. DICE_EXT_SYNC_SIZE
88314. DICE_GLOBAL_OFFSET
88315. DICE_GLOBAL_SIZE
88316. DICE_INTERFACE
88317. DICE_PRIVATE_SPACE
88318. DICE_RX_OFFSET
88319. DICE_RX_SIZE
88320. DICE_TX_OFFSET
88321. DICE_TX_SIZE
88322. DICE_UNUSED2_OFFSET
88323. DICE_UNUSED2_SIZE
88324. DICR
88325. DICR_MASTER
88326. DICR_RECEIVE
88327. DICR_TRANSMIT
88328. DICT
88329. DICTID
88330. DICT_MAX
88331. DIC_BIT
88332. DIC_DPE1
88333. DIC_DPE10
88334. DIC_DPE11
88335. DIC_DPE12
88336. DIC_DPE13
88337. DIC_DPE14
88338. DIC_DPE15
88339. DIC_DPE2
88340. DIC_DPE3
88341. DIC_DPE4
88342. DIC_DPE5
88343. DIC_DPE6
88344. DIC_DPE7
88345. DIC_DPE8
88346. DIC_DPE9
88347. DID
88348. DIDMIB_CAT_DOT11PHY
88349. DIDMIB_CAT_DOT11SMT
88350. DIDMIB_CAT_LNX
88351. DIDMIB_CAT_P2
88352. DIDMIB_DOT11MAC_OPERATIONTABLE
88353. DIDMIB_DOT11MAC_OPERATIONTABLE_FRAGMENTATIONTHRESHOLD
88354. DIDMIB_DOT11MAC_OPERATIONTABLE_LONGRETRYLIMIT
88355. DIDMIB_DOT11MAC_OPERATIONTABLE_MACADDRESS
88356. DIDMIB_DOT11MAC_OPERATIONTABLE_MAXTRANSMITMSDULIFETIME
88357. DIDMIB_DOT11MAC_OPERATIONTABLE_RTSTHRESHOLD
88358. DIDMIB_DOT11MAC_OPERATIONTABLE_SHORTRETRYLIMIT
88359. DIDMIB_DOT11PHY_DSSSTABLE
88360. DIDMIB_DOT11PHY_DSSSTABLE_CURRENTCHANNEL
88361. DIDMIB_DOT11PHY_OPERATIONTABLE
88362. DIDMIB_DOT11PHY_TXPOWERTABLE_CURRENTTXPOWERLEVEL
88363. DIDMIB_DOT11SMT_PRIVACYTABLE
88364. DIDMIB_DOT11SMT_PRIVACYTABLE_EXCLUDEUNENCRYPTED
88365. DIDMIB_DOT11SMT_PRIVACYTABLE_PRIVACYINVOKED
88366. DIDMIB_DOT11SMT_PRIVACYTABLE_WEPDEFAULTKEYID
88367. DIDMIB_DOT11SMT_WEPDEFAULTKEYSTABLE
88368. DIDMIB_LNX_CONFIGTABLE
88369. DIDMIB_LNX_CONFIGTABLE_RSNAIE
88370. DIDMIB_P2_MAC
88371. DIDMIB_P2_MAC_CURRENTTXRATE
88372. DIDMIB_P2_NIC_PRISUPRANGE
88373. DIDMIB_P2_STATIC
88374. DIDMIB_P2_STATIC_CNFPORTTYPE
88375. DIDMSG_DOT11IND_ASSOCIATE
88376. DIDMSG_DOT11IND_AUTHENTICATE
88377. DIDMSG_DOT11REQ_MIBGET
88378. DIDMSG_DOT11REQ_MIBGET_MIBATTRIBUTE
88379. DIDMSG_DOT11REQ_MIBGET_RESULTCODE
88380. DIDMSG_DOT11REQ_MIBSET
88381. DIDMSG_DOT11REQ_MIBSET_MIBATTRIBUTE
88382. DIDMSG_DOT11REQ_MIBSET_RESULTCODE
88383. DIDMSG_DOT11REQ_SCAN
88384. DIDMSG_DOT11REQ_SCAN_RESULTS
88385. DIDMSG_DOT11REQ_START
88386. DIDMSG_LNXREQ_AUTOJOIN
88387. DIDMSG_LNXREQ_COMMSQUALITY
88388. DIDMSG_LNXREQ_HOSTWEP
88389. DIDMSG_LNXREQ_IFSTATE
88390. DIDMSG_LNXREQ_WLANSNIFF
88391. DIDMSG_P2REQ_FLASHDL_STATE
88392. DIDMSG_P2REQ_FLASHDL_WRITE
88393. DIDMSG_P2REQ_RAMDL_STATE
88394. DIDMSG_P2REQ_RAMDL_STATE_ENABLE
88395. DIDMSG_P2REQ_RAMDL_STATE_EXEADDR
88396. DIDMSG_P2REQ_RAMDL_STATE_RESULTCODE
88397. DIDMSG_P2REQ_RAMDL_WRITE
88398. DIDMSG_P2REQ_RAMDL_WRITE_ADDR
88399. DIDMSG_P2REQ_RAMDL_WRITE_DATA
88400. DIDMSG_P2REQ_RAMDL_WRITE_LEN
88401. DIDMSG_P2REQ_RAMDL_WRITE_RESULTCODE
88402. DIDMSG_P2REQ_READPDA
88403. DIDMSG_P2REQ_READPDA_PDA
88404. DIDMSG_P2REQ_READPDA_RESULTCODE
88405. DIDSR
88406. DIDSR_CODE
88407. DIDSR_LCDS_DCLKIN
88408. DIDSR_LCDS_LVDS0
88409. DIDSR_LCDS_LVDS1
88410. DIDSR_LCDS_MASK
88411. DIDSR_PDCS_CLK
88412. DIDSR_PDCS_MASK
88413. DIDT_CTRL_EN
88414. DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK
88415. DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT
88416. DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK
88417. DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT
88418. DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK
88419. DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT
88420. DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK
88421. DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT
88422. DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK
88423. DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT
88424. DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK
88425. DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT
88426. DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK
88427. DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT
88428. DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK
88429. DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT
88430. DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK
88431. DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT
88432. DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK
88433. DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT
88434. DIDT_DBR_CTRL0__PHASE_OFFSET_MASK
88435. DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT
88436. DIDT_DBR_CTRL0__UNUSED_0_MASK
88437. DIDT_DBR_CTRL0__UNUSED_0__SHIFT
88438. DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK
88439. DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT
88440. DIDT_DBR_CTRL1__MAX_POWER_MASK
88441. DIDT_DBR_CTRL1__MAX_POWER__SHIFT
88442. DIDT_DBR_CTRL1__MIN_POWER_MASK
88443. DIDT_DBR_CTRL1__MIN_POWER__SHIFT
88444. DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK
88445. DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT
88446. DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK
88447. DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT
88448. DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK
88449. DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT
88450. DIDT_DBR_CTRL2__UNUSED_0_MASK
88451. DIDT_DBR_CTRL2__UNUSED_0__SHIFT
88452. DIDT_DBR_CTRL2__UNUSED_1_MASK
88453. DIDT_DBR_CTRL2__UNUSED_1__SHIFT
88454. DIDT_DBR_CTRL2__UNUSED_2_MASK
88455. DIDT_DBR_CTRL2__UNUSED_2__SHIFT
88456. DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK
88457. DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT
88458. DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK
88459. DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT
88460. DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK
88461. DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT
88462. DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK
88463. DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT
88464. DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK
88465. DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT
88466. DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK
88467. DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT
88468. DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK
88469. DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT
88470. DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK
88471. DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT
88472. DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK
88473. DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT
88474. DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK
88475. DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT
88476. DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK
88477. DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT
88478. DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK
88479. DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT
88480. DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK
88481. DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT
88482. DIDT_DBR_CTRL_OCP__UNUSED_0_MASK
88483. DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT
88484. DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK
88485. DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT
88486. DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK
88487. DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT
88488. DIDT_DBR_EDC_CTRL__EDC_EN_MASK
88489. DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT
88490. DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK
88491. DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT
88492. DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK
88493. DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT
88494. DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK
88495. DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT
88496. DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK
88497. DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT
88498. DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK
88499. DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT
88500. DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK
88501. DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT
88502. DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK
88503. DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT
88504. DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK
88505. DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT
88506. DIDT_DBR_EDC_CTRL__UNUSED_0_MASK
88507. DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT
88508. DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK
88509. DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT
88510. DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK
88511. DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT
88512. DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK
88513. DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT
88514. DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK
88515. DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT
88516. DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1_MASK
88517. DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1__SHIFT
88518. DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK
88519. DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT
88520. DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK
88521. DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT
88522. DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK
88523. DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT
88524. DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK
88525. DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT
88526. DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK
88527. DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT
88528. DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK
88529. DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT
88530. DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK
88531. DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT
88532. DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK
88533. DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT
88534. DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK
88535. DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT
88536. DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK
88537. DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT
88538. DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK
88539. DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT
88540. DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK
88541. DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT
88542. DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK
88543. DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT
88544. DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK
88545. DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT
88546. DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK
88547. DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT
88548. DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK
88549. DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT
88550. DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK
88551. DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT
88552. DIDT_DBR_EDC_STATUS__UNUSED_0_MASK
88553. DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT
88554. DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK
88555. DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT
88556. DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK
88557. DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT
88558. DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK
88559. DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
88560. DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK
88561. DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
88562. DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK
88563. DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT
88564. DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK
88565. DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT
88566. DIDT_DBR_STALL_CTRL__UNUSED_0_MASK
88567. DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT
88568. DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK
88569. DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT
88570. DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK
88571. DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT
88572. DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK
88573. DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT
88574. DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK
88575. DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT
88576. DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK
88577. DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT
88578. DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK
88579. DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT
88580. DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK
88581. DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT
88582. DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK
88583. DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT
88584. DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK
88585. DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT
88586. DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK
88587. DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT
88588. DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK
88589. DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT
88590. DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK
88591. DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT
88592. DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK
88593. DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT
88594. DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK
88595. DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT
88596. DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK
88597. DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT
88598. DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK
88599. DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT
88600. DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK
88601. DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT
88602. DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK
88603. DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT
88604. DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK
88605. DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT
88606. DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK
88607. DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT
88608. DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK
88609. DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT
88610. DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK
88611. DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT
88612. DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK
88613. DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT
88614. DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK
88615. DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT
88616. DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK
88617. DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT
88618. DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK
88619. DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT
88620. DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK
88621. DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT
88622. DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK
88623. DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT
88624. DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK
88625. DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT
88626. DIDT_DB_CTRL0
88627. DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK
88628. DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT
88629. DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK
88630. DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT
88631. DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK
88632. DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT
88633. DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK
88634. DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT
88635. DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK
88636. DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT
88637. DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK
88638. DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT
88639. DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK
88640. DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT
88641. DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK
88642. DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT
88643. DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK
88644. DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT
88645. DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK
88646. DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT
88647. DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK
88648. DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT
88649. DIDT_DB_CTRL0__DIDT_THROTTLE_MODE_MASK
88650. DIDT_DB_CTRL0__DIDT_THROTTLE_MODE__SHIFT
88651. DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK
88652. DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT
88653. DIDT_DB_CTRL0__PHASE_OFFSET_MASK
88654. DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT
88655. DIDT_DB_CTRL0__UNUSED_0_MASK
88656. DIDT_DB_CTRL0__UNUSED_0__SHIFT
88657. DIDT_DB_CTRL0__USE_REF_CLOCK_MASK
88658. DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT
88659. DIDT_DB_CTRL1__MAX_POWER_MASK
88660. DIDT_DB_CTRL1__MAX_POWER__SHIFT
88661. DIDT_DB_CTRL1__MIN_POWER_MASK
88662. DIDT_DB_CTRL1__MIN_POWER__SHIFT
88663. DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK
88664. DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT
88665. DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK
88666. DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT
88667. DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK
88668. DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT
88669. DIDT_DB_CTRL2__UNUSED_0_MASK
88670. DIDT_DB_CTRL2__UNUSED_0__SHIFT
88671. DIDT_DB_CTRL2__UNUSED_1_MASK
88672. DIDT_DB_CTRL2__UNUSED_1__SHIFT
88673. DIDT_DB_CTRL2__UNUSED_2_MASK
88674. DIDT_DB_CTRL2__UNUSED_2__SHIFT
88675. DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK
88676. DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT
88677. DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK
88678. DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT
88679. DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK
88680. DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT
88681. DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK
88682. DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT
88683. DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK
88684. DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT
88685. DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK
88686. DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT
88687. DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK
88688. DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT
88689. DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK
88690. DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT
88691. DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK
88692. DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT
88693. DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK
88694. DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT
88695. DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK
88696. DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT
88697. DIDT_DB_CTRL3__THROTTLE_POLICY_MASK
88698. DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT
88699. DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK
88700. DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT
88701. DIDT_DB_CTRL_OCP__UNUSED_0_MASK
88702. DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT
88703. DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK
88704. DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT
88705. DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK
88706. DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT
88707. DIDT_DB_EDC_CTRL__EDC_EN_MASK
88708. DIDT_DB_EDC_CTRL__EDC_EN__SHIFT
88709. DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK
88710. DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT
88711. DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK
88712. DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT
88713. DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK
88714. DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT
88715. DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK
88716. DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT
88717. DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK
88718. DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT
88719. DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK
88720. DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT
88721. DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK
88722. DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT
88723. DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK
88724. DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT
88725. DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK
88726. DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT
88727. DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK
88728. DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT
88729. DIDT_DB_EDC_CTRL__UNUSED_0_MASK
88730. DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT
88731. DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK
88732. DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT
88733. DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK
88734. DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT
88735. DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK
88736. DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT
88737. DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK
88738. DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT
88739. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK
88740. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT
88741. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK
88742. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT
88743. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK
88744. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT
88745. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK
88746. DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT
88747. DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK
88748. DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT
88749. DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK
88750. DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT
88751. DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK
88752. DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT
88753. DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK
88754. DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT
88755. DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK
88756. DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT
88757. DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK
88758. DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT
88759. DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK
88760. DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT
88761. DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK
88762. DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT
88763. DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK
88764. DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT
88765. DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK
88766. DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT
88767. DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK
88768. DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT
88769. DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK
88770. DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT
88771. DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK
88772. DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT
88773. DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK
88774. DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT
88775. DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK
88776. DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT
88777. DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK
88778. DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT
88779. DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK
88780. DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT
88781. DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK
88782. DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT
88783. DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK
88784. DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT
88785. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK
88786. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT
88787. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK
88788. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT
88789. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK
88790. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT
88791. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK
88792. DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT
88793. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK
88794. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT
88795. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK
88796. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT
88797. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK
88798. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT
88799. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK
88800. DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT
88801. DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK
88802. DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT
88803. DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK
88804. DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
88805. DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK
88806. DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
88807. DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK
88808. DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT
88809. DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK
88810. DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT
88811. DIDT_DB_STALL_CTRL__UNUSED_0_MASK
88812. DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT
88813. DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK
88814. DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT
88815. DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK
88816. DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT
88817. DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK
88818. DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT
88819. DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK
88820. DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT
88821. DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK
88822. DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT
88823. DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK
88824. DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT
88825. DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK
88826. DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT
88827. DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK
88828. DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT
88829. DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK
88830. DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT
88831. DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK
88832. DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT
88833. DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK
88834. DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT
88835. DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK
88836. DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT
88837. DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK
88838. DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT
88839. DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK
88840. DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT
88841. DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK
88842. DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT
88843. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
88844. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
88845. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
88846. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
88847. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
88848. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
88849. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK
88850. DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT
88851. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
88852. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
88853. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
88854. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
88855. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
88856. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
88857. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
88858. DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
88859. DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK
88860. DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT
88861. DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
88862. DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
88863. DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
88864. DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
88865. DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
88866. DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
88867. DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK
88868. DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT
88869. DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
88870. DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
88871. DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
88872. DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
88873. DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
88874. DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
88875. DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
88876. DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
88877. DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK
88878. DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT
88879. DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK
88880. DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT
88881. DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK
88882. DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT
88883. DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK
88884. DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT
88885. DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK
88886. DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT
88887. DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK
88888. DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT
88889. DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK
88890. DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT
88891. DIDT_DB_WEIGHT0_3__WEIGHT0_MASK
88892. DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT
88893. DIDT_DB_WEIGHT0_3__WEIGHT1_MASK
88894. DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT
88895. DIDT_DB_WEIGHT0_3__WEIGHT2_MASK
88896. DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT
88897. DIDT_DB_WEIGHT0_3__WEIGHT3_MASK
88898. DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT
88899. DIDT_DB_WEIGHT4_7__WEIGHT4_MASK
88900. DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT
88901. DIDT_DB_WEIGHT4_7__WEIGHT5_MASK
88902. DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT
88903. DIDT_DB_WEIGHT4_7__WEIGHT6_MASK
88904. DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT
88905. DIDT_DB_WEIGHT4_7__WEIGHT7_MASK
88906. DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT
88907. DIDT_DB_WEIGHT8_11__WEIGHT10_MASK
88908. DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT
88909. DIDT_DB_WEIGHT8_11__WEIGHT11_MASK
88910. DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT
88911. DIDT_DB_WEIGHT8_11__WEIGHT8_MASK
88912. DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT
88913. DIDT_DB_WEIGHT8_11__WEIGHT9_MASK
88914. DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT
88915. DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK
88916. DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT
88917. DIDT_IND_DATA__DIDT_IND_DATA_MASK
88918. DIDT_IND_DATA__DIDT_IND_DATA__SHIFT
88919. DIDT_IND_INDEX__DIDT_IND_INDEX_MASK
88920. DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT
88921. DIDT_SQ_CTRL0
88922. DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK
88923. DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT
88924. DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK
88925. DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT
88926. DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK
88927. DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT
88928. DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK
88929. DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT
88930. DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK
88931. DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT
88932. DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK
88933. DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
88934. DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK
88935. DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
88936. DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK
88937. DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT
88938. DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK
88939. DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT
88940. DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK
88941. DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT
88942. DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK
88943. DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT
88944. DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK
88945. DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT
88946. DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK
88947. DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT
88948. DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE_MASK
88949. DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE__SHIFT
88950. DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK
88951. DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT
88952. DIDT_SQ_CTRL0__PHASE_OFFSET_MASK
88953. DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT
88954. DIDT_SQ_CTRL0__UNUSED_0_MASK
88955. DIDT_SQ_CTRL0__UNUSED_0__SHIFT
88956. DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK
88957. DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT
88958. DIDT_SQ_CTRL1__MAX_POWER_MASK
88959. DIDT_SQ_CTRL1__MAX_POWER__SHIFT
88960. DIDT_SQ_CTRL1__MIN_POWER_MASK
88961. DIDT_SQ_CTRL1__MIN_POWER__SHIFT
88962. DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK
88963. DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT
88964. DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK
88965. DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT
88966. DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK
88967. DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT
88968. DIDT_SQ_CTRL2__UNUSED_0_MASK
88969. DIDT_SQ_CTRL2__UNUSED_0__SHIFT
88970. DIDT_SQ_CTRL2__UNUSED_1_MASK
88971. DIDT_SQ_CTRL2__UNUSED_1__SHIFT
88972. DIDT_SQ_CTRL2__UNUSED_2_MASK
88973. DIDT_SQ_CTRL2__UNUSED_2__SHIFT
88974. DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK
88975. DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT
88976. DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK
88977. DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT
88978. DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK
88979. DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT
88980. DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK
88981. DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT
88982. DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK
88983. DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT
88984. DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK
88985. DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT
88986. DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK
88987. DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT
88988. DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK
88989. DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT
88990. DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK
88991. DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT
88992. DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK
88993. DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT
88994. DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK
88995. DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT
88996. DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK
88997. DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT
88998. DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK
88999. DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT
89000. DIDT_SQ_CTRL_OCP__UNUSED_0_MASK
89001. DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT
89002. DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK
89003. DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT
89004. DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK
89005. DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT
89006. DIDT_SQ_EDC_CTRL__EDC_EN_MASK
89007. DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT
89008. DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK
89009. DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT
89010. DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK
89011. DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT
89012. DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK
89013. DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT
89014. DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK
89015. DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT
89016. DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK
89017. DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT
89018. DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK
89019. DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT
89020. DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK
89021. DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT
89022. DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK
89023. DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT
89024. DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK
89025. DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT
89026. DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK
89027. DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT
89028. DIDT_SQ_EDC_CTRL__UNUSED_0_MASK
89029. DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT
89030. DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK
89031. DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT
89032. DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK
89033. DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT
89034. DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK
89035. DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT
89036. DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK
89037. DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT
89038. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK
89039. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT
89040. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK
89041. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT
89042. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK
89043. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT
89044. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK
89045. DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT
89046. DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK
89047. DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT
89048. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK
89049. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT
89050. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK
89051. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT
89052. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK
89053. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT
89054. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK
89055. DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT
89056. DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK
89057. DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT
89058. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK
89059. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT
89060. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK
89061. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT
89062. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK
89063. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT
89064. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK
89065. DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT
89066. DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK
89067. DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT
89068. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK
89069. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT
89070. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK
89071. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT
89072. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK
89073. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT
89074. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK
89075. DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT
89076. DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK
89077. DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT
89078. DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK
89079. DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT
89080. DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK
89081. DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT
89082. DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK
89083. DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT
89084. DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK
89085. DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT
89086. DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK
89087. DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT
89088. DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK
89089. DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT
89090. DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK
89091. DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT
89092. DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK
89093. DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT
89094. DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK
89095. DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT
89096. DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK
89097. DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT
89098. DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK
89099. DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT
89100. DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK
89101. DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT
89102. DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK
89103. DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT
89104. DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK
89105. DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT
89106. DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK
89107. DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT
89108. DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK
89109. DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT
89110. DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK
89111. DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT
89112. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK
89113. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT
89114. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK
89115. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT
89116. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK
89117. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT
89118. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK
89119. DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT
89120. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK
89121. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT
89122. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK
89123. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT
89124. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK
89125. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT
89126. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK
89127. DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT
89128. DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK
89129. DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT
89130. DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK
89131. DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT
89132. DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK
89133. DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
89134. DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK
89135. DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
89136. DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK
89137. DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT
89138. DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK
89139. DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT
89140. DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK
89141. DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT
89142. DIDT_SQ_STALL_CTRL__UNUSED_0_MASK
89143. DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT
89144. DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK
89145. DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT
89146. DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK
89147. DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT
89148. DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK
89149. DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT
89150. DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK
89151. DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT
89152. DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK
89153. DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT
89154. DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK
89155. DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT
89156. DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK
89157. DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT
89158. DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK
89159. DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT
89160. DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK
89161. DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT
89162. DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK
89163. DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT
89164. DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK
89165. DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT
89166. DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK
89167. DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT
89168. DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK
89169. DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT
89170. DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK
89171. DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT
89172. DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK
89173. DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT
89174. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
89175. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
89176. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
89177. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
89178. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
89179. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
89180. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK
89181. DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT
89182. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
89183. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
89184. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
89185. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
89186. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
89187. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
89188. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
89189. DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
89190. DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK
89191. DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT
89192. DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
89193. DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
89194. DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
89195. DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
89196. DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
89197. DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
89198. DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK
89199. DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT
89200. DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
89201. DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
89202. DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
89203. DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
89204. DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
89205. DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
89206. DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
89207. DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
89208. DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK
89209. DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT
89210. DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK
89211. DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT
89212. DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK
89213. DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT
89214. DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK
89215. DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT
89216. DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK
89217. DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT
89218. DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK
89219. DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT
89220. DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK
89221. DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT
89222. DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK
89223. DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT
89224. DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK
89225. DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT
89226. DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK
89227. DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT
89228. DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK
89229. DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT
89230. DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK
89231. DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT
89232. DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK
89233. DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT
89234. DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK
89235. DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT
89236. DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK
89237. DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT
89238. DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK
89239. DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT
89240. DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK
89241. DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT
89242. DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK
89243. DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT
89244. DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK
89245. DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT
89246. DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK
89247. DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT
89248. DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK
89249. DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT
89250. DIDT_TCP_CTRL0
89251. DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK
89252. DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT
89253. DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK
89254. DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT
89255. DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK
89256. DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT
89257. DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK
89258. DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT
89259. DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK
89260. DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT
89261. DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK
89262. DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
89263. DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK
89264. DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
89265. DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK
89266. DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT
89267. DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK
89268. DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT
89269. DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK
89270. DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT
89271. DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK
89272. DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT
89273. DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK
89274. DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT
89275. DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK
89276. DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT
89277. DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE_MASK
89278. DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE__SHIFT
89279. DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK
89280. DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT
89281. DIDT_TCP_CTRL0__PHASE_OFFSET_MASK
89282. DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT
89283. DIDT_TCP_CTRL0__UNUSED_0_MASK
89284. DIDT_TCP_CTRL0__UNUSED_0__SHIFT
89285. DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK
89286. DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT
89287. DIDT_TCP_CTRL1__MAX_POWER_MASK
89288. DIDT_TCP_CTRL1__MAX_POWER__SHIFT
89289. DIDT_TCP_CTRL1__MIN_POWER_MASK
89290. DIDT_TCP_CTRL1__MIN_POWER__SHIFT
89291. DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK
89292. DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT
89293. DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK
89294. DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT
89295. DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK
89296. DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT
89297. DIDT_TCP_CTRL2__UNUSED_0_MASK
89298. DIDT_TCP_CTRL2__UNUSED_0__SHIFT
89299. DIDT_TCP_CTRL2__UNUSED_1_MASK
89300. DIDT_TCP_CTRL2__UNUSED_1__SHIFT
89301. DIDT_TCP_CTRL2__UNUSED_2_MASK
89302. DIDT_TCP_CTRL2__UNUSED_2__SHIFT
89303. DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK
89304. DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT
89305. DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK
89306. DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT
89307. DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK
89308. DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT
89309. DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK
89310. DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT
89311. DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK
89312. DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT
89313. DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK
89314. DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT
89315. DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK
89316. DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT
89317. DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK
89318. DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT
89319. DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK
89320. DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT
89321. DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK
89322. DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT
89323. DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK
89324. DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT
89325. DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK
89326. DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT
89327. DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK
89328. DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT
89329. DIDT_TCP_CTRL_OCP__UNUSED_0_MASK
89330. DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT
89331. DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK
89332. DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT
89333. DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK
89334. DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT
89335. DIDT_TCP_EDC_CTRL__EDC_EN_MASK
89336. DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT
89337. DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK
89338. DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT
89339. DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK
89340. DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT
89341. DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK
89342. DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT
89343. DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK
89344. DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT
89345. DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK
89346. DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT
89347. DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK
89348. DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT
89349. DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK
89350. DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT
89351. DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK
89352. DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT
89353. DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK
89354. DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT
89355. DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK
89356. DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT
89357. DIDT_TCP_EDC_CTRL__UNUSED_0_MASK
89358. DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT
89359. DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK
89360. DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT
89361. DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK
89362. DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT
89363. DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK
89364. DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT
89365. DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK
89366. DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT
89367. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK
89368. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT
89369. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK
89370. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT
89371. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK
89372. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT
89373. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK
89374. DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT
89375. DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK
89376. DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT
89377. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK
89378. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT
89379. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK
89380. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT
89381. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK
89382. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT
89383. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK
89384. DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT
89385. DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK
89386. DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT
89387. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK
89388. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT
89389. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK
89390. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT
89391. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK
89392. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT
89393. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK
89394. DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT
89395. DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK
89396. DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT
89397. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK
89398. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT
89399. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK
89400. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT
89401. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14_MASK
89402. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14__SHIFT
89403. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15_MASK
89404. DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15__SHIFT
89405. DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK
89406. DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT
89407. DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK
89408. DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT
89409. DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK
89410. DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT
89411. DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK
89412. DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT
89413. DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK
89414. DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT
89415. DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK
89416. DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT
89417. DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK
89418. DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT
89419. DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK
89420. DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT
89421. DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK
89422. DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT
89423. DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK
89424. DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT
89425. DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK
89426. DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT
89427. DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK
89428. DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT
89429. DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK
89430. DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT
89431. DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK
89432. DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT
89433. DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK
89434. DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT
89435. DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK
89436. DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT
89437. DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK
89438. DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT
89439. DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK
89440. DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT
89441. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK
89442. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT
89443. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK
89444. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT
89445. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK
89446. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT
89447. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK
89448. DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT
89449. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK
89450. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT
89451. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK
89452. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT
89453. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK
89454. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT
89455. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK
89456. DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT
89457. DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK
89458. DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT
89459. DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK
89460. DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT
89461. DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK
89462. DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
89463. DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK
89464. DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
89465. DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK
89466. DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT
89467. DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK
89468. DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT
89469. DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK
89470. DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT
89471. DIDT_TCP_STALL_CTRL__UNUSED_0_MASK
89472. DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT
89473. DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK
89474. DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT
89475. DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK
89476. DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT
89477. DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK
89478. DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT
89479. DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK
89480. DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT
89481. DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK
89482. DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT
89483. DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK
89484. DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT
89485. DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK
89486. DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT
89487. DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK
89488. DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT
89489. DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK
89490. DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT
89491. DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK
89492. DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT
89493. DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK
89494. DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT
89495. DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK
89496. DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT
89497. DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK
89498. DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT
89499. DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK
89500. DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT
89501. DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK
89502. DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT
89503. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
89504. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
89505. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
89506. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
89507. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
89508. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
89509. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK
89510. DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT
89511. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
89512. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
89513. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
89514. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
89515. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
89516. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
89517. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
89518. DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
89519. DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK
89520. DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT
89521. DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
89522. DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
89523. DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
89524. DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
89525. DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
89526. DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
89527. DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK
89528. DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT
89529. DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
89530. DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
89531. DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
89532. DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
89533. DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
89534. DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
89535. DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
89536. DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
89537. DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK
89538. DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT
89539. DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK
89540. DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT
89541. DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK
89542. DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT
89543. DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK
89544. DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT
89545. DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK
89546. DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT
89547. DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK
89548. DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT
89549. DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK
89550. DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT
89551. DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK
89552. DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT
89553. DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK
89554. DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT
89555. DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK
89556. DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT
89557. DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK
89558. DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT
89559. DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK
89560. DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT
89561. DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK
89562. DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT
89563. DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK
89564. DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT
89565. DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK
89566. DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT
89567. DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK
89568. DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT
89569. DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK
89570. DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT
89571. DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK
89572. DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT
89573. DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK
89574. DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT
89575. DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK
89576. DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT
89577. DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK
89578. DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT
89579. DIDT_TD_CTRL0
89580. DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK
89581. DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT
89582. DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK
89583. DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT
89584. DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK
89585. DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT
89586. DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK
89587. DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT
89588. DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK
89589. DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT
89590. DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK
89591. DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
89592. DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK
89593. DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
89594. DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK
89595. DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT
89596. DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK
89597. DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT
89598. DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK
89599. DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT
89600. DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK
89601. DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT
89602. DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK
89603. DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT
89604. DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK
89605. DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT
89606. DIDT_TD_CTRL0__DIDT_THROTTLE_MODE_MASK
89607. DIDT_TD_CTRL0__DIDT_THROTTLE_MODE__SHIFT
89608. DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK
89609. DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT
89610. DIDT_TD_CTRL0__PHASE_OFFSET_MASK
89611. DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT
89612. DIDT_TD_CTRL0__UNUSED_0_MASK
89613. DIDT_TD_CTRL0__UNUSED_0__SHIFT
89614. DIDT_TD_CTRL0__USE_REF_CLOCK_MASK
89615. DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT
89616. DIDT_TD_CTRL1__MAX_POWER_MASK
89617. DIDT_TD_CTRL1__MAX_POWER__SHIFT
89618. DIDT_TD_CTRL1__MIN_POWER_MASK
89619. DIDT_TD_CTRL1__MIN_POWER__SHIFT
89620. DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK
89621. DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT
89622. DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK
89623. DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT
89624. DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK
89625. DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT
89626. DIDT_TD_CTRL2__UNUSED_0_MASK
89627. DIDT_TD_CTRL2__UNUSED_0__SHIFT
89628. DIDT_TD_CTRL2__UNUSED_1_MASK
89629. DIDT_TD_CTRL2__UNUSED_1__SHIFT
89630. DIDT_TD_CTRL2__UNUSED_2_MASK
89631. DIDT_TD_CTRL2__UNUSED_2__SHIFT
89632. DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK
89633. DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT
89634. DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK
89635. DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT
89636. DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK
89637. DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT
89638. DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK
89639. DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT
89640. DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK
89641. DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT
89642. DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK
89643. DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT
89644. DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK
89645. DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT
89646. DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK
89647. DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT
89648. DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK
89649. DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT
89650. DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK
89651. DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT
89652. DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK
89653. DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT
89654. DIDT_TD_CTRL3__THROTTLE_POLICY_MASK
89655. DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT
89656. DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK
89657. DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT
89658. DIDT_TD_CTRL_OCP__UNUSED_0_MASK
89659. DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT
89660. DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK
89661. DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT
89662. DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK
89663. DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT
89664. DIDT_TD_EDC_CTRL__EDC_EN_MASK
89665. DIDT_TD_EDC_CTRL__EDC_EN__SHIFT
89666. DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK
89667. DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT
89668. DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK
89669. DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT
89670. DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK
89671. DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT
89672. DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK
89673. DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT
89674. DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK
89675. DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT
89676. DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK
89677. DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT
89678. DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK
89679. DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT
89680. DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK
89681. DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT
89682. DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK
89683. DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT
89684. DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK
89685. DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT
89686. DIDT_TD_EDC_CTRL__UNUSED_0_MASK
89687. DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT
89688. DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK
89689. DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT
89690. DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK
89691. DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT
89692. DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK
89693. DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT
89694. DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK
89695. DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT
89696. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK
89697. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT
89698. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK
89699. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT
89700. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK
89701. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT
89702. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK
89703. DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT
89704. DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK
89705. DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT
89706. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK
89707. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT
89708. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK
89709. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT
89710. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK
89711. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT
89712. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK
89713. DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT
89714. DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK
89715. DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT
89716. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK
89717. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT
89718. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK
89719. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT
89720. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK
89721. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT
89722. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK
89723. DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT
89724. DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK
89725. DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT
89726. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK
89727. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT
89728. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK
89729. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT
89730. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14_MASK
89731. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14__SHIFT
89732. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15_MASK
89733. DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15__SHIFT
89734. DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK
89735. DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT
89736. DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK
89737. DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT
89738. DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK
89739. DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT
89740. DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK
89741. DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT
89742. DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK
89743. DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT
89744. DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK
89745. DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT
89746. DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK
89747. DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT
89748. DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK
89749. DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT
89750. DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK
89751. DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT
89752. DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK
89753. DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT
89754. DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK
89755. DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT
89756. DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK
89757. DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT
89758. DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK
89759. DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT
89760. DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK
89761. DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT
89762. DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK
89763. DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT
89764. DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK
89765. DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT
89766. DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK
89767. DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT
89768. DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK
89769. DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT
89770. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK
89771. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT
89772. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK
89773. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT
89774. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK
89775. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT
89776. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK
89777. DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT
89778. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK
89779. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT
89780. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK
89781. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT
89782. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK
89783. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT
89784. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK
89785. DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT
89786. DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK
89787. DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT
89788. DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK
89789. DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT
89790. DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK
89791. DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT
89792. DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK
89793. DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT
89794. DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK
89795. DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT
89796. DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK
89797. DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT
89798. DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK
89799. DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT
89800. DIDT_TD_STALL_CTRL__UNUSED_0_MASK
89801. DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT
89802. DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK
89803. DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT
89804. DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK
89805. DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT
89806. DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK
89807. DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT
89808. DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK
89809. DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT
89810. DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK
89811. DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT
89812. DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK
89813. DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT
89814. DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK
89815. DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT
89816. DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK
89817. DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT
89818. DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK
89819. DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT
89820. DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK
89821. DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT
89822. DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK
89823. DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT
89824. DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK
89825. DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT
89826. DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK
89827. DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT
89828. DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK
89829. DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT
89830. DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK
89831. DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT
89832. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
89833. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
89834. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
89835. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
89836. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
89837. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
89838. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK
89839. DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT
89840. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
89841. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
89842. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
89843. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
89844. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
89845. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
89846. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
89847. DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
89848. DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK
89849. DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT
89850. DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK
89851. DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT
89852. DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK
89853. DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT
89854. DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK
89855. DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT
89856. DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK
89857. DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT
89858. DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK
89859. DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT
89860. DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK
89861. DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT
89862. DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK
89863. DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT
89864. DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK
89865. DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT
89866. DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK
89867. DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT
89868. DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK
89869. DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT
89870. DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK
89871. DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT
89872. DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK
89873. DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT
89874. DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK
89875. DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT
89876. DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK
89877. DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT
89878. DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK
89879. DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT
89880. DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK
89881. DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT
89882. DIDT_TD_TUNING_CTRL__UNUSED_0_MASK
89883. DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT
89884. DIDT_TD_WEIGHT0_3__WEIGHT0_MASK
89885. DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT
89886. DIDT_TD_WEIGHT0_3__WEIGHT1_MASK
89887. DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT
89888. DIDT_TD_WEIGHT0_3__WEIGHT2_MASK
89889. DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT
89890. DIDT_TD_WEIGHT0_3__WEIGHT3_MASK
89891. DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT
89892. DIDT_TD_WEIGHT4_7__WEIGHT4_MASK
89893. DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT
89894. DIDT_TD_WEIGHT4_7__WEIGHT5_MASK
89895. DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT
89896. DIDT_TD_WEIGHT4_7__WEIGHT6_MASK
89897. DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT
89898. DIDT_TD_WEIGHT4_7__WEIGHT7_MASK
89899. DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT
89900. DIDT_TD_WEIGHT8_11__WEIGHT10_MASK
89901. DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT
89902. DIDT_TD_WEIGHT8_11__WEIGHT11_MASK
89903. DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT
89904. DIDT_TD_WEIGHT8_11__WEIGHT8_MASK
89905. DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT
89906. DIDT_TD_WEIGHT8_11__WEIGHT9_MASK
89907. DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT
89908. DID_ABORT
89909. DID_ALLOC_FAILURE
89910. DID_BAD_INTR
89911. DID_BAD_TARGET
89912. DID_BUS_BUSY
89913. DID_ERROR
89914. DID_IMM_RETRY
89915. DID_MEDIUM_ERROR
89916. DID_NEXUS_FAILURE
89917. DID_NO_CONNECT
89918. DID_OK
89919. DID_PARITY
89920. DID_PASSTHROUGH
89921. DID_REG_CAN
89922. DID_REG_DIU
89923. DID_REG_FEC
89924. DID_REG_I2C
89925. DID_REG_NFC
89926. DID_REG_PATA
89927. DID_REG_PSC
89928. DID_REG_PSCFIFO
89929. DID_REG_USB
89930. DID_REG_VIU
89931. DID_REQUEUE
89932. DID_RESET
89933. DID_SDIO_LOCAL
89934. DID_SOFT_ERROR
89935. DID_TARGET_FAILURE
89936. DID_TIME_OUT
89937. DID_TRANSPORT_DISRUPTED
89938. DID_TRANSPORT_FAILFAST
89939. DID_UNDEFINE
89940. DID_UNDERFLOW
89941. DID_VPORT_ERROR
89942. DID_WLAN_FIFO
89943. DID_WLAN_IOREG
89944. DIE
89945. DIEBOLD_BCS_SE923_PID
89946. DIEN
89947. DIEN_REG
89948. DIEPCTL
89949. DIEPCTL0
89950. DIEPDMA
89951. DIEPEMPMSK
89952. DIEPINT
89953. DIEPMSK
89954. DIEPMSK_AHBERRMSK
89955. DIEPMSK_BNAININTRMSK
89956. DIEPMSK_EPDISBLDMSK
89957. DIEPMSK_INEPNAKEFFMSK
89958. DIEPMSK_INTKNEPMISMSK
89959. DIEPMSK_INTKNTXFEMPMSK
89960. DIEPMSK_NAKMSK
89961. DIEPMSK_TIMEOUTMSK
89962. DIEPMSK_TXFIFOEMPTY
89963. DIEPMSK_TXFIFOUNDRNMSK
89964. DIEPMSK_XFERCOMPLMSK
89965. DIEPTSIZ
89966. DIEPTSIZ0
89967. DIEPTSIZ0_PKTCNT
89968. DIEPTSIZ0_PKTCNT_LIMIT
89969. DIEPTSIZ0_PKTCNT_MASK
89970. DIEPTSIZ0_PKTCNT_SHIFT
89971. DIEPTSIZ0_XFERSIZE
89972. DIEPTSIZ0_XFERSIZE_LIMIT
89973. DIEPTSIZ0_XFERSIZE_MASK
89974. DIEPTSIZ0_XFERSIZE_SHIFT
89975. DIER
89976. DIER_ADCE
89977. DIER_CAIE
89978. DIER_FRE
89979. DIER_HBE
89980. DIER_RIE
89981. DIER_SVIE
89982. DIER_TVE
89983. DIER_VBE
89984. DIER_WCIE
89985. DIER_WEIE
89986. DIER_WNIE
89987. DIE_BPT
89988. DIE_BREAK
89989. DIE_BREAKPOINT
89990. DIE_CALL
89991. DIE_DABR_MATCH
89992. DIE_DEBUG
89993. DIE_DEBUG_2
89994. DIE_DIE
89995. DIE_DT
89996. DIE_FAULT
89997. DIE_FIND_CB_CHILD
89998. DIE_FIND_CB_CONTINUE
89999. DIE_FIND_CB_END
90000. DIE_FIND_CB_SIBLING
90001. DIE_FP
90002. DIE_GPF
90003. DIE_IABR_MATCH
90004. DIE_ID
90005. DIE_IERR
90006. DIE_INIT_ENTER
90007. DIE_INIT_MONARCH_ENTER
90008. DIE_INIT_MONARCH_LEAVE
90009. DIE_INIT_MONARCH_PROCESS
90010. DIE_INIT_SLAVE_ENTER
90011. DIE_INIT_SLAVE_LEAVE
90012. DIE_INIT_SLAVE_PROCESS
90013. DIE_INT3
90014. DIE_KDEBUG_ENTER
90015. DIE_KDEBUG_LEAVE
90016. DIE_KDUMP_ENTER
90017. DIE_KDUMP_LEAVE
90018. DIE_KERNELDEBUG
90019. DIE_MACHINE_HALT
90020. DIE_MACHINE_RESTART
90021. DIE_MASK
90022. DIE_MASK__VALUE
90023. DIE_MCA_MONARCH_ENTER
90024. DIE_MCA_MONARCH_LEAVE
90025. DIE_MCA_MONARCH_PROCESS
90026. DIE_MCA_NEW_TIMEOUT
90027. DIE_MCA_RENDZVOUS_ENTER
90028. DIE_MCA_RENDZVOUS_LEAVE
90029. DIE_MCA_RENDZVOUS_PROCESS
90030. DIE_MCA_SLAVE_ENTER
90031. DIE_MCA_SLAVE_LEAVE
90032. DIE_MCA_SLAVE_PROCESS
90033. DIE_MSAFP
90034. DIE_NMI
90035. DIE_NMIUNKNOWN
90036. DIE_NMIWATCHDOG
90037. DIE_NMI_IPI
90038. DIE_OOPS
90039. DIE_PAGE_FAULT
90040. DIE_PANIC
90041. DIE_REV
90042. DIE_RI
90043. DIE_SIB_FMT
90044. DIE_SSTEP
90045. DIE_SSTEPBP
90046. DIE_TEMP
90047. DIE_TRAP
90048. DIE_TRAP_TL1
90049. DIE_TYPE
90050. DIE_UNUSED
90051. DIE_UPROBE
90052. DIE_UPROBE_XOL
90053. DIF
90054. DIF0
90055. DIF1
90056. DIF2
90057. DIFACTNEGEN
90058. DIFF
90059. DIFFCHECK
90060. DIFFSERV_ENTRIES
90061. DIFFUSING_MATRIX_HEIGHT
90062. DIFFUSING_MATRIX_WIDTH
90063. DIFF_64
90064. DIFF_INVALID
90065. DIFF_MARGIN
90066. DIFF_MODE
90067. DIFF_SENSE
90068. DIFF_TARGET
90069. DIFROMREG
90070. DIFS
90071. DIF_0_N
90072. DIF_0_P
90073. DIF_1_N
90074. DIF_1_P
90075. DIF_2_N
90076. DIF_2_P
90077. DIF_3_N
90078. DIF_3_P
90079. DIF_4_N
90080. DIF_4_P
90081. DIF_AGC_CTRL_IF
90082. DIF_AGC_CTRL_INT
90083. DIF_AGC_CTRL_RF
90084. DIF_AGC_IF_INT_CURRENT
90085. DIF_AGC_IF_REF
90086. DIF_AGC_RF_CURRENT
90087. DIF_AV_SEP_CTRL
90088. DIF_BPF_COEFF01
90089. DIF_BPF_COEFF1011
90090. DIF_BPF_COEFF1213
90091. DIF_BPF_COEFF1415
90092. DIF_BPF_COEFF1617
90093. DIF_BPF_COEFF1819
90094. DIF_BPF_COEFF2021
90095. DIF_BPF_COEFF2223
90096. DIF_BPF_COEFF23
90097. DIF_BPF_COEFF2425
90098. DIF_BPF_COEFF2627
90099. DIF_BPF_COEFF2829
90100. DIF_BPF_COEFF3031
90101. DIF_BPF_COEFF3233
90102. DIF_BPF_COEFF3435
90103. DIF_BPF_COEFF36
90104. DIF_BPF_COEFF45
90105. DIF_BPF_COEFF67
90106. DIF_BPF_COEFF89
90107. DIF_BUNDLING_DMA_POOL_SIZE
90108. DIF_BUNDL_DMA_VALID
90109. DIF_COMP_FLT_CTRL
90110. DIF_ERR_APP
90111. DIF_ERR_GRD
90112. DIF_ERR_NONE
90113. DIF_ERR_REF
90114. DIF_I2S
90115. DIF_LEFT_JST
90116. DIF_MASK
90117. DIF_MISC_CTRL
90118. DIF_ON_IMMEDIATE_PARAMS_CRC_SEED_MASK
90119. DIF_ON_IMMEDIATE_PARAMS_CRC_SEED_SHIFT
90120. DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_MASK
90121. DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_SHIFT
90122. DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_WITH_MASK_MASK
90123. DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_WITH_MASK_SHIFT
90124. DIF_ON_IMMEDIATE_PARAMS_FORWARD_GUARD_MASK
90125. DIF_ON_IMMEDIATE_PARAMS_FORWARD_GUARD_SHIFT
90126. DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_MASK
90127. DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_SHIFT
90128. DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_WITH_MASK_MASK
90129. DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_WITH_MASK_SHIFT
90130. DIF_ON_IMMEDIATE_PARAMS_HOST_GUARD_TYPE_MASK
90131. DIF_ON_IMMEDIATE_PARAMS_HOST_GUARD_TYPE_SHIFT
90132. DIF_ON_IMMEDIATE_PARAMS_HOST_INTERFACE_MASK
90133. DIF_ON_IMMEDIATE_PARAMS_HOST_INTERFACE_SHIFT
90134. DIF_ON_IMMEDIATE_PARAMS_IGNORE_APP_TAG_MASK
90135. DIF_ON_IMMEDIATE_PARAMS_IGNORE_APP_TAG_SHIFT
90136. DIF_ON_IMMEDIATE_PARAMS_INITIAL_REF_TAG_IS_VALID_MASK
90137. DIF_ON_IMMEDIATE_PARAMS_INITIAL_REF_TAG_IS_VALID_SHIFT
90138. DIF_ON_IMMEDIATE_PARAMS_INTERVAL_SIZE_MASK
90139. DIF_ON_IMMEDIATE_PARAMS_INTERVAL_SIZE_SHIFT
90140. DIF_ON_IMMEDIATE_PARAMS_KEEP_REF_TAG_CONST_MASK
90141. DIF_ON_IMMEDIATE_PARAMS_KEEP_REF_TAG_CONST_SHIFT
90142. DIF_ON_IMMEDIATE_PARAMS_NETWORK_INTERFACE_MASK
90143. DIF_ON_IMMEDIATE_PARAMS_NETWORK_INTERFACE_SHIFT
90144. DIF_ON_IMMEDIATE_PARAMS_PROTECTION_TYPE_MASK
90145. DIF_ON_IMMEDIATE_PARAMS_PROTECTION_TYPE_SHIFT
90146. DIF_ON_IMMEDIATE_PARAMS_REF_TAG_MASK_MASK
90147. DIF_ON_IMMEDIATE_PARAMS_REF_TAG_MASK_SHIFT
90148. DIF_ON_IMMEDIATE_PARAMS_RESERVED_MASK
90149. DIF_ON_IMMEDIATE_PARAMS_RESERVED_SHIFT
90150. DIF_ON_IMMEDIATE_PARAMS_VALIDATE_APP_TAG_MASK
90151. DIF_ON_IMMEDIATE_PARAMS_VALIDATE_APP_TAG_SHIFT
90152. DIF_ON_IMMEDIATE_PARAMS_VALIDATE_GUARD_MASK
90153. DIF_ON_IMMEDIATE_PARAMS_VALIDATE_GUARD_SHIFT
90154. DIF_ON_IMMEDIATE_PARAMS_VALIDATE_REF_TAG_MASK
90155. DIF_ON_IMMEDIATE_PARAMS_VALIDATE_REF_TAG_SHIFT
90156. DIF_PLL_CTRL
90157. DIF_PLL_CTRL1
90158. DIF_PLL_CTRL2
90159. DIF_PLL_CTRL3
90160. DIF_PLL_FREQ_ERR
90161. DIF_PLL_FREQ_WORD
90162. DIF_RGHT_JST16
90163. DIF_RGHT_JST24
90164. DIF_RPT_VARIANCE
90165. DIF_SOFT_RST_CTRL_REVB
90166. DIF_SRC_GAIN_CONTROL
90167. DIF_SRC_PHASE_INC
90168. DIF_TDM0
90169. DIF_TDM1
90170. DIF_TDM2
90171. DIF_TDM3
90172. DIF_TUNER
90173. DIF_USE_BASEBAND
90174. DIF_VIDEO_AGC_CTRL
90175. DIF_VID_AUD_OVERRIDE
90176. DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK
90177. DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
90178. DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK
90179. DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
90180. DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
90181. DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
90182. DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
90183. DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
90184. DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
90185. DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
90186. DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK
90187. DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
90188. DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK
90189. DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
90190. DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
90191. DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
90192. DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
90193. DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
90194. DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
90195. DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
90196. DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
90197. DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
90198. DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
90199. DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
90200. DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
90201. DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
90202. DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK
90203. DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
90204. DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK
90205. DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
90206. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
90207. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
90208. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
90209. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
90210. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
90211. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
90212. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
90213. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
90214. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
90215. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
90216. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
90217. DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
90218. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
90219. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
90220. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
90221. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
90222. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
90223. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
90224. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
90225. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
90226. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
90227. DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
90228. DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
90229. DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
90230. DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
90231. DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
90232. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
90233. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
90234. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
90235. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
90236. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
90237. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
90238. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
90239. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
90240. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
90241. DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
90242. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
90243. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
90244. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
90245. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
90246. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
90247. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
90248. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
90249. DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
90250. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
90251. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
90252. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
90253. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
90254. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
90255. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
90256. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
90257. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
90258. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
90259. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
90260. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
90261. DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
90262. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
90263. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
90264. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
90265. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
90266. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
90267. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
90268. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
90269. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
90270. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
90271. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
90272. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
90273. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
90274. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
90275. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
90276. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
90277. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
90278. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
90279. DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
90280. DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
90281. DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
90282. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
90283. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
90284. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
90285. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
90286. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
90287. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
90288. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
90289. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
90290. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
90291. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
90292. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
90293. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
90294. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
90295. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
90296. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
90297. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
90298. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
90299. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
90300. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
90301. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
90302. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
90303. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
90304. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
90305. DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
90306. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
90307. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
90308. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
90309. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
90310. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
90311. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
90312. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
90313. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
90314. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
90315. DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
90316. DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
90317. DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
90318. DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
90319. DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
90320. DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
90321. DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
90322. DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
90323. DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
90324. DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
90325. DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
90326. DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
90327. DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
90328. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
90329. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
90330. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
90331. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
90332. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
90333. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
90334. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
90335. DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
90336. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
90337. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
90338. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
90339. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
90340. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
90341. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
90342. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
90343. DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
90344. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
90345. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
90346. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
90347. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
90348. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
90349. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
90350. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
90351. DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
90352. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
90353. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
90354. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
90355. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
90356. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
90357. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
90358. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
90359. DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
90360. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
90361. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
90362. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
90363. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
90364. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
90365. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
90366. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
90367. DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
90368. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
90369. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
90370. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
90371. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
90372. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
90373. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
90374. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
90375. DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
90376. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
90377. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
90378. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
90379. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
90380. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
90381. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
90382. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
90383. DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
90384. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
90385. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
90386. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
90387. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
90388. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
90389. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
90390. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
90391. DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
90392. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
90393. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
90394. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
90395. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
90396. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
90397. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
90398. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
90399. DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
90400. DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
90401. DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
90402. DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
90403. DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
90404. DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
90405. DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
90406. DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
90407. DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
90408. DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
90409. DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
90410. DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
90411. DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
90412. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
90413. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
90414. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
90415. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
90416. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
90417. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
90418. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
90419. DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
90420. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
90421. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
90422. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
90423. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
90424. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
90425. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
90426. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
90427. DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
90428. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
90429. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
90430. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
90431. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
90432. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
90433. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
90434. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
90435. DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
90436. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
90437. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
90438. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
90439. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
90440. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
90441. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
90442. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
90443. DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
90444. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
90445. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
90446. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
90447. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
90448. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
90449. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
90450. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
90451. DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
90452. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
90453. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
90454. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
90455. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
90456. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
90457. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
90458. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
90459. DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
90460. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
90461. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
90462. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
90463. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
90464. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
90465. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
90466. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
90467. DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
90468. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
90469. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
90470. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
90471. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
90472. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
90473. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
90474. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
90475. DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
90476. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
90477. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
90478. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
90479. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
90480. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
90481. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
90482. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
90483. DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
90484. DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
90485. DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
90486. DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
90487. DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
90488. DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
90489. DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
90490. DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
90491. DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
90492. DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
90493. DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
90494. DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
90495. DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
90496. DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
90497. DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
90498. DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
90499. DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
90500. DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
90501. DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
90502. DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
90503. DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
90504. DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
90505. DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
90506. DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
90507. DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
90508. DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
90509. DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
90510. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
90511. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
90512. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
90513. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
90514. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
90515. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
90516. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
90517. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
90518. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
90519. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
90520. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
90521. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
90522. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
90523. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
90524. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
90525. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
90526. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
90527. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
90528. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
90529. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
90530. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
90531. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
90532. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
90533. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
90534. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
90535. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
90536. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
90537. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
90538. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
90539. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
90540. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
90541. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
90542. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
90543. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
90544. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
90545. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
90546. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
90547. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
90548. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
90549. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
90550. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
90551. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
90552. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
90553. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
90554. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
90555. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
90556. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
90557. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
90558. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
90559. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
90560. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
90561. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
90562. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
90563. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
90564. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
90565. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
90566. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
90567. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
90568. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
90569. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
90570. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
90571. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
90572. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
90573. DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
90574. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
90575. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
90576. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
90577. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
90578. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
90579. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
90580. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
90581. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
90582. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
90583. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
90584. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
90585. DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
90586. DIG0_CNTL
90587. DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
90588. DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
90589. DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
90590. DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
90591. DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
90592. DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
90593. DIG0_DIG_BE_CNTL__DIG_MODE_MASK
90594. DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT
90595. DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
90596. DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
90597. DIG0_DIG_BE_CNTL__DIG_SWAP_MASK
90598. DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT
90599. DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
90600. DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
90601. DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
90602. DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
90603. DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
90604. DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
90605. DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
90606. DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
90607. DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK
90608. DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT
90609. DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
90610. DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
90611. DIG0_DIG_FE_CNTL__DIG_START_MASK
90612. DIG0_DIG_FE_CNTL__DIG_START__SHIFT
90613. DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
90614. DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
90615. DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
90616. DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
90617. DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
90618. DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
90619. DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK
90620. DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT
90621. DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK
90622. DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT
90623. DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
90624. DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
90625. DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
90626. DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
90627. DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
90628. DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
90629. DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
90630. DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
90631. DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
90632. DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
90633. DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
90634. DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
90635. DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
90636. DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
90637. DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
90638. DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
90639. DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
90640. DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
90641. DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
90642. DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
90643. DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
90644. DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
90645. DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
90646. DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
90647. DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
90648. DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
90649. DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
90650. DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
90651. DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
90652. DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
90653. DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
90654. DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
90655. DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
90656. DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
90657. DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
90658. DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
90659. DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
90660. DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
90661. DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
90662. DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
90663. DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
90664. DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
90665. DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
90666. DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
90667. DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
90668. DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
90669. DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
90670. DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
90671. DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
90672. DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
90673. DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
90674. DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
90675. DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
90676. DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
90677. DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
90678. DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
90679. DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
90680. DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
90681. DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
90682. DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
90683. DIG0_DIG_VERSION__DIG_TYPE_MASK
90684. DIG0_DIG_VERSION__DIG_TYPE__SHIFT
90685. DIG0_DME_CONTROL__METADATA_DB_DISABLE_MASK
90686. DIG0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT
90687. DIG0_DME_CONTROL__METADATA_DB_PENDING_MASK
90688. DIG0_DME_CONTROL__METADATA_DB_PENDING__SHIFT
90689. DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK
90690. DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT
90691. DIG0_DME_CONTROL__METADATA_DB_TAKEN_MASK
90692. DIG0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT
90693. DIG0_DME_CONTROL__METADATA_ENGINE_EN_MASK
90694. DIG0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT
90695. DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK
90696. DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT
90697. DIG0_DME_CONTROL__METADATA_STREAM_TYPE_MASK
90698. DIG0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT
90699. DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK
90700. DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT
90701. DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
90702. DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
90703. DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
90704. DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
90705. DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
90706. DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
90707. DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
90708. DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
90709. DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
90710. DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
90711. DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
90712. DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
90713. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
90714. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
90715. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
90716. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
90717. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
90718. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
90719. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
90720. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
90721. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
90722. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
90723. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
90724. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
90725. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
90726. DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
90727. DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
90728. DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
90729. DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
90730. DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
90731. DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
90732. DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
90733. DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
90734. DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
90735. DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
90736. DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
90737. DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
90738. DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
90739. DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
90740. DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
90741. DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
90742. DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
90743. DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
90744. DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
90745. DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
90746. DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
90747. DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
90748. DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
90749. DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
90750. DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
90751. DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
90752. DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
90753. DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
90754. DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
90755. DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK
90756. DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT
90757. DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
90758. DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
90759. DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
90760. DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
90761. DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
90762. DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
90763. DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
90764. DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
90765. DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
90766. DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
90767. DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK
90768. DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT
90769. DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK
90770. DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT
90771. DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK
90772. DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT
90773. DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
90774. DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
90775. DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
90776. DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
90777. DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK
90778. DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
90779. DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK
90780. DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
90781. DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
90782. DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
90783. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
90784. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
90785. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
90786. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK
90787. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT
90788. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
90789. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
90790. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
90791. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
90792. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
90793. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
90794. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK
90795. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT
90796. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
90797. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
90798. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
90799. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK
90800. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT
90801. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK
90802. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT
90803. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK
90804. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT
90805. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK
90806. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT
90807. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK
90808. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT
90809. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK
90810. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT
90811. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK
90812. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT
90813. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK
90814. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT
90815. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK
90816. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT
90817. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK
90818. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT
90819. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK
90820. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT
90821. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK
90822. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT
90823. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK
90824. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT
90825. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK
90826. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT
90827. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK
90828. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT
90829. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK
90830. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT
90831. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK
90832. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT
90833. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK
90834. DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT
90835. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK
90836. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT
90837. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK
90838. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT
90839. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
90840. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
90841. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
90842. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
90843. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
90844. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
90845. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
90846. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
90847. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
90848. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
90849. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
90850. DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
90851. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK
90852. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT
90853. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK
90854. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT
90855. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
90856. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
90857. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
90858. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
90859. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
90860. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
90861. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
90862. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
90863. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
90864. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
90865. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
90866. DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
90867. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK
90868. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT
90869. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK
90870. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT
90871. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
90872. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
90873. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
90874. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
90875. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
90876. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
90877. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
90878. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
90879. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
90880. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
90881. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
90882. DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
90883. DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK
90884. DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT
90885. DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK
90886. DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT
90887. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK
90888. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK
90889. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT
90890. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT
90891. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK
90892. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK
90893. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT
90894. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT
90895. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK
90896. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK
90897. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT
90898. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT
90899. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK
90900. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK
90901. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT
90902. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT
90903. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK
90904. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK
90905. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT
90906. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT
90907. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK
90908. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK
90909. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT
90910. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT
90911. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK
90912. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK
90913. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT
90914. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT
90915. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK
90916. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK
90917. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT
90918. DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT
90919. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
90920. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
90921. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
90922. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
90923. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
90924. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
90925. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
90926. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
90927. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
90928. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
90929. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
90930. DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
90931. DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
90932. DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
90933. DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
90934. DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
90935. DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
90936. DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
90937. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK
90938. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT
90939. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK
90940. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK
90941. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT
90942. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT
90943. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK
90944. DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT
90945. DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
90946. DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
90947. DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
90948. DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
90949. DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK
90950. DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
90951. DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
90952. DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
90953. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
90954. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
90955. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
90956. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
90957. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
90958. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
90959. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
90960. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
90961. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
90962. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
90963. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
90964. DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
90965. DIG0_REGISTER_OFFSET
90966. DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
90967. DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
90968. DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
90969. DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
90970. DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
90971. DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
90972. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
90973. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
90974. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
90975. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
90976. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
90977. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
90978. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
90979. DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
90980. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
90981. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
90982. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
90983. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
90984. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
90985. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
90986. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
90987. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
90988. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
90989. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
90990. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
90991. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
90992. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
90993. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
90994. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
90995. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
90996. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
90997. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
90998. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
90999. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
91000. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
91001. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
91002. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
91003. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
91004. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
91005. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
91006. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
91007. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
91008. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
91009. DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
91010. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
91011. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
91012. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
91013. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
91014. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
91015. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
91016. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
91017. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
91018. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
91019. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
91020. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
91021. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
91022. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
91023. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
91024. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
91025. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
91026. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
91027. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
91028. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
91029. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
91030. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
91031. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
91032. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
91033. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
91034. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
91035. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
91036. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
91037. DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
91038. DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK
91039. DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
91040. DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK
91041. DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
91042. DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK
91043. DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
91044. DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK
91045. DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
91046. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
91047. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
91048. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
91049. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
91050. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
91051. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
91052. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
91053. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
91054. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
91055. DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
91056. DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
91057. DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
91058. DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
91059. DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
91060. DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
91061. DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
91062. DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
91063. DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
91064. DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
91065. DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
91066. DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK
91067. DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT
91068. DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK
91069. DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT
91070. DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK
91071. DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
91072. DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK
91073. DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
91074. DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
91075. DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
91076. DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
91077. DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
91078. DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
91079. DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
91080. DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK
91081. DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
91082. DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK
91083. DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
91084. DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
91085. DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
91086. DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
91087. DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
91088. DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
91089. DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
91090. DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
91091. DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
91092. DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
91093. DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
91094. DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
91095. DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
91096. DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK
91097. DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
91098. DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK
91099. DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
91100. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
91101. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
91102. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
91103. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
91104. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
91105. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
91106. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
91107. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
91108. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
91109. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
91110. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
91111. DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
91112. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
91113. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
91114. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
91115. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
91116. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
91117. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
91118. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
91119. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
91120. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
91121. DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
91122. DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
91123. DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
91124. DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
91125. DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
91126. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
91127. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
91128. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
91129. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
91130. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
91131. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
91132. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
91133. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
91134. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
91135. DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
91136. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
91137. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
91138. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
91139. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
91140. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
91141. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
91142. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
91143. DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
91144. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
91145. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
91146. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
91147. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
91148. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
91149. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
91150. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
91151. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
91152. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
91153. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
91154. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
91155. DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
91156. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
91157. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
91158. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
91159. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
91160. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
91161. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
91162. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
91163. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
91164. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
91165. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
91166. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
91167. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
91168. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
91169. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
91170. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
91171. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
91172. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
91173. DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
91174. DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
91175. DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
91176. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
91177. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
91178. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
91179. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
91180. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
91181. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
91182. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
91183. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
91184. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
91185. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
91186. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
91187. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
91188. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
91189. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
91190. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
91191. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
91192. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
91193. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
91194. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
91195. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
91196. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
91197. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
91198. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
91199. DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
91200. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
91201. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
91202. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
91203. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
91204. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
91205. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
91206. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
91207. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
91208. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
91209. DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
91210. DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
91211. DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
91212. DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
91213. DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
91214. DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
91215. DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
91216. DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
91217. DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
91218. DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
91219. DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
91220. DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
91221. DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
91222. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
91223. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
91224. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
91225. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
91226. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
91227. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
91228. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
91229. DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
91230. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
91231. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
91232. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
91233. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
91234. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
91235. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
91236. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
91237. DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
91238. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
91239. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
91240. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
91241. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
91242. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
91243. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
91244. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
91245. DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
91246. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
91247. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
91248. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
91249. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
91250. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
91251. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
91252. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
91253. DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
91254. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
91255. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
91256. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
91257. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
91258. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
91259. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
91260. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
91261. DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
91262. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
91263. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
91264. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
91265. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
91266. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
91267. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
91268. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
91269. DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
91270. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
91271. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
91272. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
91273. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
91274. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
91275. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
91276. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
91277. DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
91278. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
91279. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
91280. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
91281. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
91282. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
91283. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
91284. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
91285. DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
91286. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
91287. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
91288. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
91289. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
91290. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
91291. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
91292. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
91293. DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
91294. DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
91295. DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
91296. DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
91297. DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
91298. DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
91299. DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
91300. DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
91301. DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
91302. DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
91303. DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
91304. DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
91305. DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
91306. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
91307. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
91308. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
91309. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
91310. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
91311. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
91312. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
91313. DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
91314. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
91315. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
91316. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
91317. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
91318. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
91319. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
91320. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
91321. DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
91322. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
91323. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
91324. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
91325. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
91326. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
91327. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
91328. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
91329. DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
91330. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
91331. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
91332. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
91333. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
91334. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
91335. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
91336. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
91337. DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
91338. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
91339. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
91340. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
91341. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
91342. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
91343. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
91344. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
91345. DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
91346. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
91347. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
91348. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
91349. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
91350. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
91351. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
91352. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
91353. DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
91354. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
91355. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
91356. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
91357. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
91358. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
91359. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
91360. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
91361. DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
91362. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
91363. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
91364. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
91365. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
91366. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
91367. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
91368. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
91369. DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
91370. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
91371. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
91372. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
91373. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
91374. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
91375. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
91376. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
91377. DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
91378. DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
91379. DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
91380. DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
91381. DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
91382. DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
91383. DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
91384. DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
91385. DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
91386. DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
91387. DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
91388. DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
91389. DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
91390. DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
91391. DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
91392. DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
91393. DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
91394. DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
91395. DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
91396. DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
91397. DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
91398. DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
91399. DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
91400. DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
91401. DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
91402. DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
91403. DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
91404. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
91405. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
91406. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
91407. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
91408. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
91409. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
91410. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
91411. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
91412. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
91413. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
91414. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
91415. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
91416. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
91417. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
91418. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
91419. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
91420. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
91421. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
91422. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
91423. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
91424. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
91425. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
91426. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
91427. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
91428. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
91429. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
91430. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
91431. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
91432. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
91433. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
91434. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
91435. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
91436. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
91437. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
91438. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
91439. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
91440. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
91441. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
91442. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
91443. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
91444. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
91445. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
91446. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
91447. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
91448. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
91449. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
91450. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
91451. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
91452. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
91453. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
91454. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
91455. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
91456. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
91457. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
91458. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
91459. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
91460. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
91461. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
91462. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
91463. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
91464. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
91465. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
91466. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
91467. DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
91468. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
91469. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
91470. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
91471. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
91472. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
91473. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
91474. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
91475. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
91476. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
91477. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
91478. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
91479. DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
91480. DIG1_CNTL
91481. DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
91482. DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
91483. DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
91484. DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
91485. DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
91486. DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
91487. DIG1_DIG_BE_CNTL__DIG_MODE_MASK
91488. DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT
91489. DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
91490. DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
91491. DIG1_DIG_BE_CNTL__DIG_SWAP_MASK
91492. DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT
91493. DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
91494. DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
91495. DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
91496. DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
91497. DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
91498. DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
91499. DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
91500. DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
91501. DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK
91502. DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT
91503. DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
91504. DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
91505. DIG1_DIG_FE_CNTL__DIG_START_MASK
91506. DIG1_DIG_FE_CNTL__DIG_START__SHIFT
91507. DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
91508. DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
91509. DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
91510. DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
91511. DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
91512. DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
91513. DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK
91514. DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT
91515. DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK
91516. DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT
91517. DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
91518. DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
91519. DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
91520. DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
91521. DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
91522. DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
91523. DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
91524. DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
91525. DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
91526. DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
91527. DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
91528. DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
91529. DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
91530. DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
91531. DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
91532. DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
91533. DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
91534. DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
91535. DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
91536. DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
91537. DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
91538. DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
91539. DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
91540. DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
91541. DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
91542. DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
91543. DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
91544. DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
91545. DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
91546. DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
91547. DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
91548. DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
91549. DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
91550. DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
91551. DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
91552. DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
91553. DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
91554. DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
91555. DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
91556. DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
91557. DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
91558. DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
91559. DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
91560. DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
91561. DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
91562. DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
91563. DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
91564. DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
91565. DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
91566. DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
91567. DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
91568. DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
91569. DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
91570. DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
91571. DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
91572. DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
91573. DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
91574. DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
91575. DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
91576. DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
91577. DIG1_DIG_VERSION__DIG_TYPE_MASK
91578. DIG1_DIG_VERSION__DIG_TYPE__SHIFT
91579. DIG1_DME_CONTROL__METADATA_DB_DISABLE_MASK
91580. DIG1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT
91581. DIG1_DME_CONTROL__METADATA_DB_PENDING_MASK
91582. DIG1_DME_CONTROL__METADATA_DB_PENDING__SHIFT
91583. DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK
91584. DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT
91585. DIG1_DME_CONTROL__METADATA_DB_TAKEN_MASK
91586. DIG1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT
91587. DIG1_DME_CONTROL__METADATA_ENGINE_EN_MASK
91588. DIG1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT
91589. DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK
91590. DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT
91591. DIG1_DME_CONTROL__METADATA_STREAM_TYPE_MASK
91592. DIG1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT
91593. DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK
91594. DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT
91595. DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
91596. DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
91597. DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
91598. DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
91599. DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
91600. DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
91601. DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
91602. DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
91603. DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
91604. DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
91605. DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
91606. DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
91607. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
91608. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
91609. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
91610. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
91611. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
91612. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
91613. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
91614. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
91615. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
91616. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
91617. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
91618. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
91619. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
91620. DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
91621. DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
91622. DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
91623. DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
91624. DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
91625. DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
91626. DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
91627. DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
91628. DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
91629. DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
91630. DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
91631. DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
91632. DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
91633. DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
91634. DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
91635. DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
91636. DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
91637. DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
91638. DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
91639. DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
91640. DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
91641. DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
91642. DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
91643. DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
91644. DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
91645. DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
91646. DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
91647. DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
91648. DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
91649. DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK
91650. DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT
91651. DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
91652. DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
91653. DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
91654. DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
91655. DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
91656. DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
91657. DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
91658. DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
91659. DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
91660. DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
91661. DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK
91662. DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT
91663. DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK
91664. DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT
91665. DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK
91666. DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT
91667. DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
91668. DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
91669. DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
91670. DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
91671. DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK
91672. DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
91673. DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK
91674. DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
91675. DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
91676. DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
91677. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
91678. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
91679. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
91680. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK
91681. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT
91682. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
91683. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
91684. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
91685. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
91686. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
91687. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
91688. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK
91689. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT
91690. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
91691. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
91692. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
91693. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK
91694. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT
91695. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK
91696. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT
91697. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK
91698. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT
91699. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK
91700. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT
91701. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK
91702. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT
91703. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK
91704. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT
91705. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK
91706. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT
91707. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK
91708. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT
91709. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK
91710. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT
91711. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK
91712. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT
91713. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK
91714. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT
91715. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK
91716. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT
91717. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK
91718. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT
91719. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK
91720. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT
91721. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK
91722. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT
91723. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK
91724. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT
91725. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK
91726. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT
91727. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK
91728. DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT
91729. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK
91730. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT
91731. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK
91732. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT
91733. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
91734. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
91735. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
91736. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
91737. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
91738. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
91739. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
91740. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
91741. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
91742. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
91743. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
91744. DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
91745. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK
91746. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT
91747. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK
91748. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT
91749. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
91750. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
91751. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
91752. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
91753. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
91754. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
91755. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
91756. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
91757. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
91758. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
91759. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
91760. DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
91761. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK
91762. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT
91763. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK
91764. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT
91765. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
91766. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
91767. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
91768. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
91769. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
91770. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
91771. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
91772. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
91773. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
91774. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
91775. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
91776. DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
91777. DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK
91778. DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT
91779. DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK
91780. DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT
91781. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK
91782. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK
91783. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT
91784. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT
91785. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK
91786. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK
91787. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT
91788. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT
91789. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK
91790. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK
91791. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT
91792. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT
91793. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK
91794. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK
91795. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT
91796. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT
91797. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK
91798. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK
91799. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT
91800. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT
91801. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK
91802. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK
91803. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT
91804. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT
91805. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK
91806. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK
91807. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT
91808. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT
91809. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK
91810. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK
91811. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT
91812. DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT
91813. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
91814. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
91815. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
91816. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
91817. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
91818. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
91819. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
91820. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
91821. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
91822. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
91823. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
91824. DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
91825. DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
91826. DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
91827. DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
91828. DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
91829. DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
91830. DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
91831. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK
91832. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT
91833. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK
91834. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK
91835. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT
91836. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT
91837. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK
91838. DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT
91839. DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
91840. DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
91841. DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
91842. DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
91843. DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK
91844. DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
91845. DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
91846. DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
91847. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
91848. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
91849. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
91850. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
91851. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
91852. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
91853. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
91854. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
91855. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
91856. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
91857. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
91858. DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
91859. DIG1_REGISTER_OFFSET
91860. DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
91861. DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
91862. DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
91863. DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
91864. DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
91865. DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
91866. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
91867. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
91868. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
91869. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
91870. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
91871. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
91872. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
91873. DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
91874. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
91875. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
91876. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
91877. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
91878. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
91879. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
91880. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
91881. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
91882. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
91883. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
91884. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
91885. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
91886. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
91887. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
91888. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
91889. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
91890. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
91891. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
91892. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
91893. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
91894. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
91895. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
91896. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
91897. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
91898. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
91899. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
91900. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
91901. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
91902. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
91903. DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
91904. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
91905. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
91906. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
91907. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
91908. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
91909. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
91910. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
91911. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
91912. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
91913. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
91914. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
91915. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
91916. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
91917. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
91918. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
91919. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
91920. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
91921. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
91922. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
91923. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
91924. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
91925. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
91926. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
91927. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
91928. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
91929. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
91930. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
91931. DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
91932. DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK
91933. DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
91934. DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK
91935. DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
91936. DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK
91937. DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
91938. DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK
91939. DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
91940. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
91941. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
91942. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
91943. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
91944. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
91945. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
91946. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
91947. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
91948. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
91949. DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
91950. DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
91951. DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
91952. DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
91953. DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
91954. DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
91955. DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
91956. DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
91957. DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
91958. DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
91959. DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
91960. DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK
91961. DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT
91962. DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK
91963. DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT
91964. DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK
91965. DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
91966. DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK
91967. DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
91968. DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
91969. DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
91970. DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
91971. DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
91972. DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
91973. DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
91974. DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK
91975. DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
91976. DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK
91977. DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
91978. DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
91979. DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
91980. DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
91981. DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
91982. DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
91983. DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
91984. DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
91985. DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
91986. DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
91987. DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
91988. DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
91989. DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
91990. DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK
91991. DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
91992. DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK
91993. DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
91994. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
91995. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
91996. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
91997. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
91998. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
91999. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
92000. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
92001. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
92002. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
92003. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
92004. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
92005. DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
92006. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
92007. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
92008. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
92009. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
92010. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
92011. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
92012. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
92013. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
92014. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
92015. DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
92016. DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
92017. DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
92018. DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
92019. DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
92020. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
92021. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
92022. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
92023. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
92024. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
92025. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
92026. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
92027. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
92028. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
92029. DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
92030. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
92031. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
92032. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
92033. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
92034. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
92035. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
92036. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
92037. DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
92038. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
92039. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
92040. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
92041. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
92042. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
92043. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
92044. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
92045. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
92046. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
92047. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
92048. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
92049. DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
92050. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
92051. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
92052. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
92053. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
92054. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
92055. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
92056. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
92057. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
92058. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
92059. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
92060. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
92061. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
92062. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
92063. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
92064. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
92065. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
92066. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
92067. DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
92068. DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
92069. DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
92070. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
92071. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
92072. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
92073. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
92074. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
92075. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
92076. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
92077. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
92078. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
92079. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
92080. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
92081. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
92082. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
92083. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
92084. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
92085. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
92086. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
92087. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
92088. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
92089. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
92090. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
92091. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
92092. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
92093. DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
92094. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
92095. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
92096. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
92097. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
92098. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
92099. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
92100. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
92101. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
92102. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
92103. DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
92104. DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
92105. DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
92106. DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
92107. DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
92108. DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
92109. DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
92110. DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
92111. DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
92112. DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
92113. DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
92114. DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
92115. DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
92116. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
92117. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
92118. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
92119. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
92120. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
92121. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
92122. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
92123. DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
92124. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
92125. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
92126. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
92127. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
92128. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
92129. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
92130. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
92131. DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
92132. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
92133. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
92134. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
92135. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
92136. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
92137. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
92138. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
92139. DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
92140. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
92141. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
92142. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
92143. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
92144. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
92145. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
92146. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
92147. DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
92148. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
92149. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
92150. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
92151. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
92152. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
92153. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
92154. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
92155. DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
92156. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
92157. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
92158. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
92159. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
92160. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
92161. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
92162. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
92163. DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
92164. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
92165. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
92166. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
92167. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
92168. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
92169. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
92170. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
92171. DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
92172. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
92173. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
92174. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
92175. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
92176. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
92177. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
92178. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
92179. DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
92180. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
92181. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
92182. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
92183. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
92184. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
92185. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
92186. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
92187. DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
92188. DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
92189. DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
92190. DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
92191. DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
92192. DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
92193. DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
92194. DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
92195. DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
92196. DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
92197. DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
92198. DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
92199. DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
92200. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
92201. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
92202. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
92203. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
92204. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
92205. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
92206. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
92207. DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
92208. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
92209. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
92210. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
92211. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
92212. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
92213. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
92214. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
92215. DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
92216. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
92217. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
92218. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
92219. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
92220. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
92221. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
92222. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
92223. DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
92224. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
92225. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
92226. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
92227. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
92228. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
92229. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
92230. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
92231. DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
92232. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
92233. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
92234. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
92235. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
92236. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
92237. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
92238. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
92239. DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
92240. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
92241. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
92242. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
92243. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
92244. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
92245. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
92246. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
92247. DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
92248. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
92249. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
92250. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
92251. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
92252. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
92253. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
92254. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
92255. DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
92256. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
92257. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
92258. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
92259. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
92260. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
92261. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
92262. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
92263. DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
92264. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
92265. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
92266. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
92267. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
92268. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
92269. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
92270. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
92271. DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
92272. DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
92273. DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
92274. DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
92275. DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
92276. DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
92277. DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
92278. DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
92279. DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
92280. DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
92281. DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
92282. DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
92283. DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
92284. DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
92285. DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
92286. DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
92287. DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
92288. DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
92289. DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
92290. DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
92291. DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
92292. DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
92293. DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
92294. DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
92295. DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
92296. DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
92297. DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
92298. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
92299. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
92300. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
92301. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
92302. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
92303. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
92304. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
92305. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
92306. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
92307. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
92308. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
92309. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
92310. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
92311. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
92312. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
92313. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
92314. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
92315. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
92316. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
92317. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
92318. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
92319. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
92320. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
92321. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
92322. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
92323. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
92324. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
92325. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
92326. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
92327. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
92328. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
92329. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
92330. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
92331. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
92332. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
92333. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
92334. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
92335. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
92336. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
92337. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
92338. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
92339. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
92340. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
92341. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
92342. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
92343. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
92344. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
92345. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
92346. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
92347. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
92348. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
92349. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
92350. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
92351. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
92352. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
92353. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
92354. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
92355. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
92356. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
92357. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
92358. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
92359. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
92360. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
92361. DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
92362. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
92363. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
92364. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
92365. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
92366. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
92367. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
92368. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
92369. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
92370. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
92371. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
92372. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
92373. DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
92374. DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
92375. DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
92376. DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
92377. DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
92378. DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
92379. DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
92380. DIG2_DIG_BE_CNTL__DIG_MODE_MASK
92381. DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT
92382. DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
92383. DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
92384. DIG2_DIG_BE_CNTL__DIG_SWAP_MASK
92385. DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT
92386. DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
92387. DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
92388. DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
92389. DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
92390. DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
92391. DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
92392. DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
92393. DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
92394. DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK
92395. DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT
92396. DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
92397. DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
92398. DIG2_DIG_FE_CNTL__DIG_START_MASK
92399. DIG2_DIG_FE_CNTL__DIG_START__SHIFT
92400. DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
92401. DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
92402. DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
92403. DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
92404. DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
92405. DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
92406. DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK
92407. DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT
92408. DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK
92409. DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT
92410. DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
92411. DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
92412. DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
92413. DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
92414. DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
92415. DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
92416. DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
92417. DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
92418. DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
92419. DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
92420. DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
92421. DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
92422. DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
92423. DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
92424. DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
92425. DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
92426. DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
92427. DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
92428. DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
92429. DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
92430. DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
92431. DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
92432. DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
92433. DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
92434. DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
92435. DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
92436. DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
92437. DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
92438. DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
92439. DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
92440. DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
92441. DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
92442. DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
92443. DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
92444. DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
92445. DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
92446. DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
92447. DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
92448. DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
92449. DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
92450. DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
92451. DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
92452. DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
92453. DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
92454. DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
92455. DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
92456. DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
92457. DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
92458. DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
92459. DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
92460. DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
92461. DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
92462. DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
92463. DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
92464. DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
92465. DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
92466. DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
92467. DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
92468. DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
92469. DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
92470. DIG2_DIG_VERSION__DIG_TYPE_MASK
92471. DIG2_DIG_VERSION__DIG_TYPE__SHIFT
92472. DIG2_DME_CONTROL__METADATA_DB_DISABLE_MASK
92473. DIG2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT
92474. DIG2_DME_CONTROL__METADATA_DB_PENDING_MASK
92475. DIG2_DME_CONTROL__METADATA_DB_PENDING__SHIFT
92476. DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK
92477. DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT
92478. DIG2_DME_CONTROL__METADATA_DB_TAKEN_MASK
92479. DIG2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT
92480. DIG2_DME_CONTROL__METADATA_ENGINE_EN_MASK
92481. DIG2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT
92482. DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK
92483. DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT
92484. DIG2_DME_CONTROL__METADATA_STREAM_TYPE_MASK
92485. DIG2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT
92486. DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK
92487. DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT
92488. DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
92489. DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
92490. DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
92491. DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
92492. DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
92493. DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
92494. DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
92495. DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
92496. DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
92497. DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
92498. DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
92499. DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
92500. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
92501. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
92502. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
92503. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
92504. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
92505. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
92506. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
92507. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
92508. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
92509. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
92510. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
92511. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
92512. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
92513. DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
92514. DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
92515. DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
92516. DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
92517. DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
92518. DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
92519. DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
92520. DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
92521. DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
92522. DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
92523. DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
92524. DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
92525. DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
92526. DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
92527. DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
92528. DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
92529. DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
92530. DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
92531. DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
92532. DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
92533. DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
92534. DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
92535. DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
92536. DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
92537. DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
92538. DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
92539. DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
92540. DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
92541. DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
92542. DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK
92543. DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT
92544. DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
92545. DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
92546. DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
92547. DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
92548. DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
92549. DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
92550. DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
92551. DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
92552. DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
92553. DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
92554. DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK
92555. DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT
92556. DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK
92557. DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT
92558. DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK
92559. DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT
92560. DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
92561. DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
92562. DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
92563. DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
92564. DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK
92565. DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
92566. DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK
92567. DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
92568. DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
92569. DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
92570. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
92571. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
92572. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
92573. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK
92574. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT
92575. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
92576. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
92577. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
92578. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
92579. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
92580. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
92581. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK
92582. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT
92583. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
92584. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
92585. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
92586. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK
92587. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT
92588. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK
92589. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT
92590. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK
92591. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT
92592. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK
92593. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT
92594. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK
92595. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT
92596. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK
92597. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT
92598. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK
92599. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT
92600. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK
92601. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT
92602. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK
92603. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT
92604. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK
92605. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT
92606. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK
92607. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT
92608. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK
92609. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT
92610. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK
92611. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT
92612. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK
92613. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT
92614. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK
92615. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT
92616. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK
92617. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT
92618. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK
92619. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT
92620. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK
92621. DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT
92622. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK
92623. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT
92624. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK
92625. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT
92626. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
92627. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
92628. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
92629. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
92630. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
92631. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
92632. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
92633. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
92634. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
92635. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
92636. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
92637. DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
92638. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK
92639. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT
92640. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK
92641. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT
92642. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
92643. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
92644. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
92645. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
92646. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
92647. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
92648. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
92649. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
92650. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
92651. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
92652. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
92653. DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
92654. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK
92655. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT
92656. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK
92657. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT
92658. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
92659. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
92660. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
92661. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
92662. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
92663. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
92664. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
92665. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
92666. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
92667. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
92668. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
92669. DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
92670. DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK
92671. DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT
92672. DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK
92673. DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT
92674. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK
92675. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK
92676. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT
92677. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT
92678. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK
92679. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK
92680. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT
92681. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT
92682. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK
92683. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK
92684. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT
92685. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT
92686. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK
92687. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK
92688. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT
92689. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT
92690. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK
92691. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK
92692. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT
92693. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT
92694. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK
92695. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK
92696. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT
92697. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT
92698. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK
92699. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK
92700. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT
92701. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT
92702. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK
92703. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK
92704. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT
92705. DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT
92706. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
92707. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
92708. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
92709. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
92710. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
92711. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
92712. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
92713. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
92714. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
92715. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
92716. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
92717. DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
92718. DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
92719. DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
92720. DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
92721. DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
92722. DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
92723. DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
92724. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK
92725. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT
92726. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK
92727. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK
92728. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT
92729. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT
92730. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK
92731. DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT
92732. DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
92733. DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
92734. DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
92735. DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
92736. DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK
92737. DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
92738. DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
92739. DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
92740. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
92741. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
92742. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
92743. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
92744. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
92745. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
92746. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
92747. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
92748. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
92749. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
92750. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
92751. DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
92752. DIG2_REGISTER_OFFSET
92753. DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
92754. DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
92755. DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
92756. DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
92757. DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
92758. DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
92759. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
92760. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
92761. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
92762. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
92763. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
92764. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
92765. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
92766. DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
92767. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
92768. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
92769. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
92770. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
92771. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
92772. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
92773. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
92774. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
92775. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
92776. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
92777. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
92778. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
92779. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
92780. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
92781. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
92782. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
92783. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
92784. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
92785. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
92786. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
92787. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
92788. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
92789. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
92790. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
92791. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
92792. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
92793. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
92794. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
92795. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
92796. DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
92797. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
92798. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
92799. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
92800. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
92801. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
92802. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
92803. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
92804. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
92805. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
92806. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
92807. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
92808. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
92809. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
92810. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
92811. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
92812. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
92813. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
92814. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
92815. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
92816. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
92817. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
92818. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
92819. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
92820. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
92821. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
92822. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
92823. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
92824. DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
92825. DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK
92826. DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
92827. DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK
92828. DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
92829. DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK
92830. DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
92831. DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK
92832. DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
92833. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
92834. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
92835. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
92836. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
92837. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
92838. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
92839. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
92840. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
92841. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
92842. DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
92843. DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
92844. DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
92845. DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
92846. DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
92847. DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
92848. DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
92849. DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
92850. DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
92851. DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
92852. DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
92853. DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK
92854. DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT
92855. DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK
92856. DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT
92857. DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK
92858. DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
92859. DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK
92860. DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
92861. DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
92862. DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
92863. DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
92864. DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
92865. DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
92866. DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
92867. DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK
92868. DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
92869. DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK
92870. DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
92871. DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
92872. DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
92873. DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
92874. DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
92875. DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
92876. DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
92877. DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
92878. DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
92879. DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
92880. DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
92881. DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
92882. DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
92883. DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK
92884. DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
92885. DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK
92886. DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
92887. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
92888. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
92889. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
92890. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
92891. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
92892. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
92893. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
92894. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
92895. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
92896. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
92897. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
92898. DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
92899. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
92900. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
92901. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
92902. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
92903. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
92904. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
92905. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
92906. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
92907. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
92908. DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
92909. DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
92910. DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
92911. DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
92912. DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
92913. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
92914. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
92915. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
92916. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
92917. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
92918. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
92919. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
92920. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
92921. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
92922. DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
92923. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
92924. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
92925. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
92926. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
92927. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
92928. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
92929. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
92930. DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
92931. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
92932. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
92933. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
92934. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
92935. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
92936. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
92937. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
92938. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
92939. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
92940. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
92941. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
92942. DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
92943. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
92944. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
92945. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
92946. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
92947. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
92948. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
92949. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
92950. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
92951. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
92952. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
92953. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
92954. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
92955. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
92956. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
92957. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
92958. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
92959. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
92960. DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
92961. DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
92962. DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
92963. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
92964. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
92965. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
92966. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
92967. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
92968. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
92969. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
92970. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
92971. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
92972. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
92973. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
92974. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
92975. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
92976. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
92977. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
92978. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
92979. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
92980. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
92981. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
92982. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
92983. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
92984. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
92985. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
92986. DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
92987. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
92988. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
92989. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
92990. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
92991. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
92992. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
92993. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
92994. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
92995. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
92996. DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
92997. DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
92998. DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
92999. DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
93000. DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
93001. DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
93002. DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
93003. DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
93004. DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
93005. DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
93006. DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
93007. DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
93008. DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
93009. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
93010. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
93011. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
93012. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
93013. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
93014. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
93015. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
93016. DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
93017. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
93018. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
93019. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
93020. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
93021. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
93022. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
93023. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
93024. DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
93025. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
93026. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
93027. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
93028. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
93029. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
93030. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
93031. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
93032. DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
93033. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
93034. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
93035. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
93036. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
93037. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
93038. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
93039. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
93040. DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
93041. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
93042. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
93043. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
93044. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
93045. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
93046. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
93047. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
93048. DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
93049. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
93050. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
93051. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
93052. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
93053. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
93054. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
93055. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
93056. DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
93057. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
93058. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
93059. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
93060. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
93061. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
93062. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
93063. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
93064. DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
93065. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
93066. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
93067. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
93068. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
93069. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
93070. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
93071. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
93072. DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
93073. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
93074. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
93075. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
93076. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
93077. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
93078. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
93079. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
93080. DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
93081. DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
93082. DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
93083. DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
93084. DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
93085. DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
93086. DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
93087. DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
93088. DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
93089. DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
93090. DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
93091. DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
93092. DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
93093. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
93094. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
93095. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
93096. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
93097. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
93098. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
93099. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
93100. DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
93101. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
93102. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
93103. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
93104. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
93105. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
93106. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
93107. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
93108. DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
93109. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
93110. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
93111. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
93112. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
93113. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
93114. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
93115. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
93116. DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
93117. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
93118. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
93119. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
93120. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
93121. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
93122. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
93123. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
93124. DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
93125. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
93126. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
93127. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
93128. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
93129. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
93130. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
93131. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
93132. DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
93133. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
93134. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
93135. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
93136. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
93137. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
93138. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
93139. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
93140. DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
93141. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
93142. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
93143. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
93144. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
93145. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
93146. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
93147. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
93148. DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
93149. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
93150. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
93151. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
93152. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
93153. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
93154. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
93155. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
93156. DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
93157. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
93158. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
93159. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
93160. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
93161. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
93162. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
93163. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
93164. DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
93165. DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
93166. DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
93167. DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
93168. DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
93169. DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
93170. DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
93171. DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
93172. DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
93173. DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
93174. DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
93175. DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
93176. DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
93177. DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
93178. DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
93179. DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
93180. DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
93181. DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
93182. DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
93183. DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
93184. DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
93185. DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
93186. DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
93187. DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
93188. DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
93189. DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
93190. DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
93191. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
93192. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
93193. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
93194. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
93195. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
93196. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
93197. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
93198. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
93199. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
93200. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
93201. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
93202. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
93203. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
93204. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
93205. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
93206. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
93207. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
93208. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
93209. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
93210. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
93211. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
93212. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
93213. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
93214. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
93215. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
93216. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
93217. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
93218. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
93219. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
93220. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
93221. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
93222. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
93223. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
93224. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
93225. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
93226. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
93227. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
93228. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
93229. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
93230. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
93231. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
93232. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
93233. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
93234. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
93235. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
93236. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
93237. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
93238. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
93239. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
93240. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
93241. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
93242. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
93243. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
93244. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
93245. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
93246. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
93247. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
93248. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
93249. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
93250. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
93251. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
93252. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
93253. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
93254. DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
93255. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
93256. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
93257. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
93258. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
93259. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
93260. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
93261. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
93262. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
93263. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
93264. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
93265. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
93266. DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
93267. DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
93268. DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
93269. DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
93270. DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
93271. DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
93272. DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
93273. DIG3_DIG_BE_CNTL__DIG_MODE_MASK
93274. DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT
93275. DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
93276. DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
93277. DIG3_DIG_BE_CNTL__DIG_SWAP_MASK
93278. DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT
93279. DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
93280. DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
93281. DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
93282. DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
93283. DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
93284. DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
93285. DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
93286. DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
93287. DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK
93288. DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT
93289. DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
93290. DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
93291. DIG3_DIG_FE_CNTL__DIG_START_MASK
93292. DIG3_DIG_FE_CNTL__DIG_START__SHIFT
93293. DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
93294. DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
93295. DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
93296. DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
93297. DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
93298. DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
93299. DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK
93300. DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT
93301. DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK
93302. DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT
93303. DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
93304. DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
93305. DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
93306. DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
93307. DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
93308. DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
93309. DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
93310. DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
93311. DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
93312. DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
93313. DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
93314. DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
93315. DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
93316. DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
93317. DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
93318. DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
93319. DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
93320. DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
93321. DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
93322. DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
93323. DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
93324. DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
93325. DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
93326. DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
93327. DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
93328. DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
93329. DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
93330. DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
93331. DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
93332. DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
93333. DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
93334. DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
93335. DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
93336. DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
93337. DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
93338. DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
93339. DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
93340. DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
93341. DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
93342. DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
93343. DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
93344. DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
93345. DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
93346. DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
93347. DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
93348. DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
93349. DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
93350. DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
93351. DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
93352. DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
93353. DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
93354. DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
93355. DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
93356. DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
93357. DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
93358. DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
93359. DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
93360. DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
93361. DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
93362. DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
93363. DIG3_DIG_VERSION__DIG_TYPE_MASK
93364. DIG3_DIG_VERSION__DIG_TYPE__SHIFT
93365. DIG3_DME_CONTROL__METADATA_DB_DISABLE_MASK
93366. DIG3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT
93367. DIG3_DME_CONTROL__METADATA_DB_PENDING_MASK
93368. DIG3_DME_CONTROL__METADATA_DB_PENDING__SHIFT
93369. DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK
93370. DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT
93371. DIG3_DME_CONTROL__METADATA_DB_TAKEN_MASK
93372. DIG3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT
93373. DIG3_DME_CONTROL__METADATA_ENGINE_EN_MASK
93374. DIG3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT
93375. DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK
93376. DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT
93377. DIG3_DME_CONTROL__METADATA_STREAM_TYPE_MASK
93378. DIG3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT
93379. DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK
93380. DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT
93381. DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
93382. DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
93383. DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
93384. DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
93385. DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
93386. DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
93387. DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
93388. DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
93389. DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
93390. DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
93391. DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
93392. DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
93393. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
93394. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
93395. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
93396. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
93397. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
93398. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
93399. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
93400. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
93401. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
93402. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
93403. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
93404. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
93405. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
93406. DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
93407. DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
93408. DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
93409. DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
93410. DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
93411. DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
93412. DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
93413. DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
93414. DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
93415. DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
93416. DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
93417. DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
93418. DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
93419. DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
93420. DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
93421. DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
93422. DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
93423. DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
93424. DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
93425. DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
93426. DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
93427. DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
93428. DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
93429. DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
93430. DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
93431. DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
93432. DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
93433. DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
93434. DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
93435. DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK
93436. DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT
93437. DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
93438. DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
93439. DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
93440. DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
93441. DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
93442. DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
93443. DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
93444. DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
93445. DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
93446. DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
93447. DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK
93448. DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT
93449. DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK
93450. DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT
93451. DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK
93452. DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT
93453. DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
93454. DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
93455. DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
93456. DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
93457. DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK
93458. DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
93459. DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK
93460. DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
93461. DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
93462. DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
93463. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
93464. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
93465. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
93466. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK
93467. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT
93468. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
93469. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
93470. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
93471. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
93472. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
93473. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
93474. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK
93475. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT
93476. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
93477. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
93478. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
93479. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK
93480. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT
93481. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK
93482. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT
93483. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK
93484. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT
93485. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK
93486. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT
93487. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK
93488. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT
93489. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK
93490. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT
93491. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK
93492. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT
93493. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK
93494. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT
93495. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK
93496. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT
93497. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK
93498. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT
93499. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK
93500. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT
93501. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK
93502. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT
93503. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK
93504. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT
93505. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK
93506. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT
93507. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK
93508. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT
93509. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK
93510. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT
93511. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK
93512. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT
93513. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK
93514. DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT
93515. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK
93516. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT
93517. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK
93518. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT
93519. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
93520. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
93521. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
93522. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
93523. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
93524. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
93525. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
93526. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
93527. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
93528. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
93529. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
93530. DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
93531. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK
93532. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT
93533. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK
93534. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT
93535. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
93536. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
93537. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
93538. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
93539. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
93540. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
93541. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
93542. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
93543. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
93544. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
93545. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
93546. DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
93547. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK
93548. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT
93549. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK
93550. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT
93551. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
93552. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
93553. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
93554. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
93555. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
93556. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
93557. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
93558. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
93559. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
93560. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
93561. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
93562. DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
93563. DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK
93564. DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT
93565. DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK
93566. DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT
93567. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK
93568. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK
93569. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT
93570. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT
93571. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK
93572. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK
93573. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT
93574. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT
93575. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK
93576. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK
93577. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT
93578. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT
93579. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK
93580. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK
93581. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT
93582. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT
93583. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK
93584. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK
93585. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT
93586. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT
93587. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK
93588. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK
93589. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT
93590. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT
93591. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK
93592. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK
93593. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT
93594. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT
93595. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK
93596. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK
93597. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT
93598. DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT
93599. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
93600. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
93601. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
93602. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
93603. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
93604. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
93605. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
93606. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
93607. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
93608. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
93609. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
93610. DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
93611. DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
93612. DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
93613. DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
93614. DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
93615. DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
93616. DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
93617. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK
93618. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT
93619. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK
93620. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK
93621. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT
93622. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT
93623. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK
93624. DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT
93625. DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
93626. DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
93627. DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
93628. DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
93629. DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK
93630. DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
93631. DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
93632. DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
93633. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
93634. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
93635. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
93636. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
93637. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
93638. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
93639. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
93640. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
93641. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
93642. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
93643. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
93644. DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
93645. DIG3_REGISTER_OFFSET
93646. DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
93647. DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
93648. DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
93649. DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
93650. DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
93651. DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
93652. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
93653. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
93654. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
93655. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
93656. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
93657. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
93658. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
93659. DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
93660. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
93661. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
93662. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
93663. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
93664. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
93665. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
93666. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
93667. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
93668. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
93669. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
93670. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
93671. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
93672. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
93673. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
93674. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
93675. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
93676. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
93677. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
93678. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
93679. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
93680. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
93681. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
93682. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
93683. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
93684. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
93685. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
93686. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
93687. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
93688. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
93689. DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
93690. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
93691. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
93692. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
93693. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
93694. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
93695. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
93696. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
93697. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
93698. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
93699. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
93700. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
93701. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
93702. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
93703. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
93704. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
93705. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
93706. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
93707. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
93708. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
93709. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
93710. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
93711. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
93712. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
93713. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
93714. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
93715. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
93716. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
93717. DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
93718. DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK
93719. DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
93720. DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK
93721. DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
93722. DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK
93723. DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
93724. DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK
93725. DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
93726. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
93727. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
93728. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
93729. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
93730. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
93731. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
93732. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
93733. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
93734. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
93735. DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
93736. DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
93737. DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
93738. DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
93739. DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
93740. DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
93741. DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
93742. DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
93743. DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
93744. DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
93745. DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
93746. DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK
93747. DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT
93748. DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK
93749. DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT
93750. DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK
93751. DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
93752. DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK
93753. DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
93754. DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
93755. DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
93756. DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
93757. DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
93758. DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
93759. DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
93760. DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK
93761. DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
93762. DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK
93763. DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
93764. DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
93765. DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
93766. DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
93767. DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
93768. DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
93769. DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
93770. DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
93771. DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
93772. DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
93773. DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
93774. DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
93775. DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
93776. DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK
93777. DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
93778. DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK
93779. DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
93780. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
93781. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
93782. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
93783. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
93784. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
93785. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
93786. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
93787. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
93788. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
93789. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
93790. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
93791. DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
93792. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
93793. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
93794. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
93795. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
93796. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
93797. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
93798. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
93799. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
93800. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
93801. DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
93802. DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
93803. DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
93804. DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
93805. DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
93806. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
93807. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
93808. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
93809. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
93810. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
93811. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
93812. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
93813. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
93814. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
93815. DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
93816. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
93817. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
93818. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
93819. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
93820. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
93821. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
93822. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
93823. DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
93824. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
93825. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
93826. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
93827. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
93828. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
93829. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
93830. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
93831. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
93832. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
93833. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
93834. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
93835. DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
93836. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
93837. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
93838. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
93839. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
93840. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
93841. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
93842. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
93843. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
93844. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
93845. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
93846. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
93847. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
93848. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
93849. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
93850. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
93851. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
93852. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
93853. DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
93854. DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
93855. DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
93856. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
93857. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
93858. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
93859. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
93860. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
93861. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
93862. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
93863. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
93864. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
93865. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
93866. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
93867. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
93868. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
93869. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
93870. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
93871. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
93872. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
93873. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
93874. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
93875. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
93876. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
93877. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
93878. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
93879. DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
93880. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
93881. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
93882. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
93883. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
93884. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
93885. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
93886. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
93887. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
93888. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
93889. DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
93890. DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
93891. DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
93892. DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
93893. DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
93894. DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
93895. DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
93896. DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
93897. DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
93898. DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
93899. DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
93900. DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
93901. DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
93902. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
93903. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
93904. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
93905. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
93906. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
93907. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
93908. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
93909. DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
93910. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
93911. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
93912. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
93913. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
93914. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
93915. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
93916. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
93917. DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
93918. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
93919. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
93920. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
93921. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
93922. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
93923. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
93924. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
93925. DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
93926. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
93927. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
93928. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
93929. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
93930. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
93931. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
93932. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
93933. DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
93934. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
93935. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
93936. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
93937. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
93938. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
93939. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
93940. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
93941. DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
93942. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
93943. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
93944. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
93945. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
93946. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
93947. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
93948. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
93949. DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
93950. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
93951. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
93952. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
93953. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
93954. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
93955. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
93956. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
93957. DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
93958. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
93959. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
93960. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
93961. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
93962. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
93963. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
93964. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
93965. DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
93966. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
93967. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
93968. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
93969. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
93970. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
93971. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
93972. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
93973. DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
93974. DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
93975. DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
93976. DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
93977. DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
93978. DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
93979. DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
93980. DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
93981. DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
93982. DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
93983. DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
93984. DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
93985. DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
93986. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
93987. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
93988. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
93989. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
93990. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
93991. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
93992. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
93993. DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
93994. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
93995. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
93996. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
93997. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
93998. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
93999. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
94000. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
94001. DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
94002. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
94003. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
94004. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
94005. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
94006. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
94007. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
94008. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
94009. DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
94010. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
94011. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
94012. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
94013. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
94014. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
94015. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
94016. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
94017. DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
94018. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
94019. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
94020. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
94021. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
94022. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
94023. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
94024. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
94025. DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
94026. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
94027. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
94028. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
94029. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
94030. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
94031. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
94032. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
94033. DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
94034. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
94035. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
94036. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
94037. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
94038. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
94039. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
94040. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
94041. DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
94042. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
94043. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
94044. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
94045. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
94046. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
94047. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
94048. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
94049. DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
94050. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
94051. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
94052. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
94053. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
94054. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
94055. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
94056. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
94057. DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
94058. DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
94059. DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
94060. DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
94061. DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
94062. DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
94063. DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
94064. DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
94065. DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
94066. DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
94067. DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
94068. DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
94069. DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
94070. DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
94071. DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
94072. DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
94073. DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
94074. DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
94075. DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
94076. DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
94077. DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
94078. DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
94079. DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
94080. DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
94081. DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
94082. DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
94083. DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
94084. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
94085. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
94086. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
94087. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
94088. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
94089. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
94090. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
94091. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
94092. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
94093. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
94094. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
94095. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
94096. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
94097. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
94098. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
94099. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
94100. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
94101. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
94102. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
94103. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
94104. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
94105. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
94106. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
94107. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
94108. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
94109. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
94110. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
94111. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
94112. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
94113. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
94114. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
94115. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
94116. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
94117. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
94118. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
94119. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
94120. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
94121. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
94122. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
94123. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
94124. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
94125. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
94126. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
94127. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
94128. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
94129. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
94130. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
94131. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
94132. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
94133. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
94134. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
94135. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
94136. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
94137. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
94138. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
94139. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
94140. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
94141. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
94142. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
94143. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
94144. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
94145. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
94146. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
94147. DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
94148. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
94149. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
94150. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
94151. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
94152. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
94153. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
94154. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
94155. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
94156. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
94157. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
94158. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
94159. DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
94160. DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
94161. DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
94162. DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
94163. DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
94164. DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
94165. DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
94166. DIG4_DIG_BE_CNTL__DIG_MODE_MASK
94167. DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT
94168. DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
94169. DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
94170. DIG4_DIG_BE_CNTL__DIG_SWAP_MASK
94171. DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT
94172. DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
94173. DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
94174. DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
94175. DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
94176. DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
94177. DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
94178. DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
94179. DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
94180. DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK
94181. DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT
94182. DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
94183. DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
94184. DIG4_DIG_FE_CNTL__DIG_START_MASK
94185. DIG4_DIG_FE_CNTL__DIG_START__SHIFT
94186. DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
94187. DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
94188. DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
94189. DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
94190. DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
94191. DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
94192. DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK
94193. DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT
94194. DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK
94195. DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT
94196. DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
94197. DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
94198. DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
94199. DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
94200. DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
94201. DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
94202. DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
94203. DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
94204. DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
94205. DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
94206. DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
94207. DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
94208. DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
94209. DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
94210. DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
94211. DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
94212. DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
94213. DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
94214. DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
94215. DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
94216. DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
94217. DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
94218. DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
94219. DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
94220. DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
94221. DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
94222. DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
94223. DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
94224. DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
94225. DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
94226. DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
94227. DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
94228. DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
94229. DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
94230. DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
94231. DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
94232. DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
94233. DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
94234. DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
94235. DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
94236. DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
94237. DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
94238. DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
94239. DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
94240. DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
94241. DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
94242. DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
94243. DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
94244. DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
94245. DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
94246. DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
94247. DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
94248. DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
94249. DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
94250. DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
94251. DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
94252. DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
94253. DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
94254. DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
94255. DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
94256. DIG4_DIG_VERSION__DIG_TYPE_MASK
94257. DIG4_DIG_VERSION__DIG_TYPE__SHIFT
94258. DIG4_DME_CONTROL__METADATA_DB_DISABLE_MASK
94259. DIG4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT
94260. DIG4_DME_CONTROL__METADATA_DB_PENDING_MASK
94261. DIG4_DME_CONTROL__METADATA_DB_PENDING__SHIFT
94262. DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK
94263. DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT
94264. DIG4_DME_CONTROL__METADATA_DB_TAKEN_MASK
94265. DIG4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT
94266. DIG4_DME_CONTROL__METADATA_ENGINE_EN_MASK
94267. DIG4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT
94268. DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK
94269. DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT
94270. DIG4_DME_CONTROL__METADATA_STREAM_TYPE_MASK
94271. DIG4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT
94272. DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK
94273. DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT
94274. DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
94275. DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
94276. DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
94277. DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
94278. DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
94279. DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
94280. DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
94281. DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
94282. DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
94283. DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
94284. DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
94285. DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
94286. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
94287. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
94288. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
94289. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
94290. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
94291. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
94292. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
94293. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
94294. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
94295. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
94296. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
94297. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
94298. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
94299. DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
94300. DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
94301. DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
94302. DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
94303. DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
94304. DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
94305. DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
94306. DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
94307. DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
94308. DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
94309. DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
94310. DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
94311. DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
94312. DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
94313. DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
94314. DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
94315. DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
94316. DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
94317. DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
94318. DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
94319. DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
94320. DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
94321. DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
94322. DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
94323. DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
94324. DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
94325. DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
94326. DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
94327. DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
94328. DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK
94329. DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT
94330. DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
94331. DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
94332. DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
94333. DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
94334. DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
94335. DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
94336. DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
94337. DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
94338. DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
94339. DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
94340. DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK
94341. DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT
94342. DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK
94343. DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT
94344. DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK
94345. DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT
94346. DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
94347. DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
94348. DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
94349. DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
94350. DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK
94351. DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
94352. DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK
94353. DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
94354. DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
94355. DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
94356. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
94357. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
94358. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
94359. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK
94360. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT
94361. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
94362. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
94363. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
94364. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
94365. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
94366. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
94367. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK
94368. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT
94369. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
94370. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
94371. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
94372. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK
94373. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT
94374. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK
94375. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT
94376. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK
94377. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT
94378. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK
94379. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT
94380. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK
94381. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT
94382. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK
94383. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT
94384. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK
94385. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT
94386. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK
94387. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT
94388. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK
94389. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT
94390. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK
94391. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT
94392. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK
94393. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT
94394. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK
94395. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT
94396. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK
94397. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT
94398. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK
94399. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT
94400. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK
94401. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT
94402. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK
94403. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT
94404. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK
94405. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT
94406. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK
94407. DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT
94408. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK
94409. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT
94410. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK
94411. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT
94412. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
94413. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
94414. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
94415. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
94416. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
94417. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
94418. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
94419. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
94420. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
94421. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
94422. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
94423. DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
94424. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK
94425. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT
94426. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK
94427. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT
94428. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
94429. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
94430. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
94431. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
94432. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
94433. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
94434. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
94435. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
94436. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
94437. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
94438. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
94439. DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
94440. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK
94441. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT
94442. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK
94443. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT
94444. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
94445. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
94446. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
94447. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
94448. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
94449. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
94450. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
94451. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
94452. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
94453. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
94454. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
94455. DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
94456. DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK
94457. DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT
94458. DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK
94459. DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT
94460. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK
94461. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK
94462. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT
94463. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT
94464. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK
94465. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK
94466. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT
94467. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT
94468. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK
94469. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK
94470. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT
94471. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT
94472. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK
94473. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK
94474. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT
94475. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT
94476. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK
94477. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK
94478. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT
94479. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT
94480. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK
94481. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK
94482. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT
94483. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT
94484. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK
94485. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK
94486. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT
94487. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT
94488. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK
94489. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK
94490. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT
94491. DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT
94492. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
94493. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
94494. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
94495. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
94496. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
94497. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
94498. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
94499. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
94500. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
94501. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
94502. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
94503. DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
94504. DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
94505. DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
94506. DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
94507. DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
94508. DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
94509. DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
94510. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK
94511. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT
94512. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK
94513. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK
94514. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT
94515. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT
94516. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK
94517. DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT
94518. DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
94519. DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
94520. DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
94521. DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
94522. DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK
94523. DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
94524. DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
94525. DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
94526. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
94527. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
94528. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
94529. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
94530. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
94531. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
94532. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
94533. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
94534. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
94535. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
94536. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
94537. DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
94538. DIG4_REGISTER_OFFSET
94539. DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
94540. DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
94541. DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
94542. DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
94543. DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
94544. DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
94545. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
94546. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
94547. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
94548. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
94549. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
94550. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
94551. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
94552. DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
94553. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
94554. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
94555. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
94556. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
94557. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
94558. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
94559. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
94560. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
94561. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
94562. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
94563. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
94564. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
94565. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
94566. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
94567. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
94568. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
94569. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
94570. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
94571. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
94572. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
94573. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
94574. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
94575. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
94576. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
94577. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
94578. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
94579. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
94580. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
94581. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
94582. DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
94583. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
94584. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
94585. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
94586. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
94587. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
94588. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
94589. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
94590. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
94591. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
94592. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
94593. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
94594. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
94595. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
94596. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
94597. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
94598. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
94599. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
94600. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
94601. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
94602. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
94603. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
94604. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
94605. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
94606. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
94607. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
94608. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
94609. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
94610. DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
94611. DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK
94612. DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
94613. DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK
94614. DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
94615. DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK
94616. DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
94617. DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK
94618. DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
94619. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
94620. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
94621. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
94622. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
94623. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
94624. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
94625. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
94626. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
94627. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
94628. DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
94629. DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
94630. DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
94631. DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
94632. DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
94633. DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
94634. DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
94635. DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
94636. DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
94637. DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
94638. DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
94639. DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK
94640. DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT
94641. DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK
94642. DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT
94643. DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK
94644. DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
94645. DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK
94646. DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
94647. DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
94648. DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
94649. DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
94650. DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
94651. DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
94652. DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
94653. DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK
94654. DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
94655. DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK
94656. DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
94657. DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
94658. DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
94659. DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
94660. DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
94661. DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
94662. DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
94663. DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
94664. DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
94665. DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
94666. DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
94667. DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
94668. DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
94669. DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK
94670. DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
94671. DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK
94672. DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
94673. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
94674. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
94675. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
94676. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
94677. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
94678. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
94679. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
94680. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
94681. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
94682. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
94683. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
94684. DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
94685. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
94686. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
94687. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
94688. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
94689. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
94690. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
94691. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
94692. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
94693. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
94694. DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
94695. DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
94696. DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
94697. DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
94698. DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
94699. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
94700. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
94701. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
94702. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
94703. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
94704. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
94705. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
94706. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
94707. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
94708. DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
94709. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
94710. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
94711. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
94712. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
94713. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
94714. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
94715. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
94716. DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
94717. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
94718. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
94719. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
94720. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
94721. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
94722. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
94723. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
94724. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
94725. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
94726. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
94727. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
94728. DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
94729. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
94730. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
94731. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
94732. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
94733. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
94734. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
94735. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
94736. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
94737. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
94738. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
94739. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
94740. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
94741. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
94742. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
94743. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
94744. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
94745. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
94746. DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
94747. DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
94748. DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
94749. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
94750. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
94751. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
94752. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
94753. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
94754. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
94755. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
94756. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
94757. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
94758. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
94759. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
94760. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
94761. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
94762. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
94763. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
94764. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
94765. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
94766. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
94767. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
94768. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
94769. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
94770. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
94771. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
94772. DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
94773. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
94774. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
94775. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
94776. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
94777. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
94778. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
94779. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
94780. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
94781. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
94782. DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
94783. DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
94784. DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
94785. DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
94786. DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
94787. DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
94788. DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
94789. DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
94790. DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
94791. DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
94792. DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
94793. DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
94794. DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
94795. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
94796. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
94797. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
94798. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
94799. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
94800. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
94801. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
94802. DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
94803. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
94804. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
94805. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
94806. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
94807. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
94808. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
94809. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
94810. DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
94811. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
94812. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
94813. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
94814. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
94815. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
94816. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
94817. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
94818. DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
94819. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
94820. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
94821. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
94822. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
94823. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
94824. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
94825. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
94826. DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
94827. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
94828. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
94829. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
94830. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
94831. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
94832. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
94833. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
94834. DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
94835. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
94836. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
94837. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
94838. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
94839. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
94840. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
94841. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
94842. DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
94843. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
94844. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
94845. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
94846. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
94847. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
94848. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
94849. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
94850. DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
94851. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
94852. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
94853. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
94854. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
94855. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
94856. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
94857. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
94858. DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
94859. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
94860. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
94861. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
94862. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
94863. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
94864. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
94865. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
94866. DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
94867. DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
94868. DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
94869. DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
94870. DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
94871. DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
94872. DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
94873. DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
94874. DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
94875. DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
94876. DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
94877. DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
94878. DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
94879. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
94880. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
94881. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
94882. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
94883. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
94884. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
94885. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
94886. DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
94887. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
94888. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
94889. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
94890. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
94891. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
94892. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
94893. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
94894. DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
94895. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
94896. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
94897. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
94898. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
94899. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
94900. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
94901. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
94902. DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
94903. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
94904. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
94905. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
94906. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
94907. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
94908. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
94909. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
94910. DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
94911. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
94912. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
94913. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
94914. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
94915. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
94916. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
94917. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
94918. DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
94919. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
94920. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
94921. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
94922. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
94923. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
94924. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
94925. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
94926. DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
94927. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
94928. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
94929. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
94930. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
94931. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
94932. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
94933. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
94934. DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
94935. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
94936. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
94937. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
94938. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
94939. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
94940. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
94941. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
94942. DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
94943. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
94944. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
94945. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
94946. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
94947. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
94948. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
94949. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
94950. DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
94951. DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
94952. DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
94953. DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
94954. DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
94955. DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
94956. DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
94957. DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
94958. DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
94959. DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
94960. DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
94961. DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
94962. DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
94963. DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
94964. DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
94965. DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
94966. DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
94967. DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
94968. DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
94969. DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
94970. DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
94971. DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
94972. DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
94973. DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
94974. DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
94975. DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
94976. DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
94977. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
94978. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
94979. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
94980. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
94981. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
94982. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
94983. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
94984. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
94985. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
94986. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
94987. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
94988. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
94989. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
94990. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
94991. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
94992. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
94993. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
94994. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
94995. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
94996. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
94997. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
94998. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
94999. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
95000. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
95001. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
95002. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
95003. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
95004. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
95005. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
95006. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
95007. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
95008. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
95009. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
95010. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
95011. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
95012. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
95013. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
95014. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
95015. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
95016. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
95017. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
95018. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
95019. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
95020. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
95021. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
95022. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
95023. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
95024. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
95025. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
95026. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
95027. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
95028. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
95029. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
95030. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
95031. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
95032. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
95033. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
95034. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
95035. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
95036. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
95037. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
95038. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
95039. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
95040. DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
95041. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
95042. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
95043. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
95044. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
95045. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
95046. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
95047. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
95048. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
95049. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
95050. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
95051. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
95052. DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
95053. DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
95054. DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
95055. DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
95056. DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
95057. DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
95058. DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
95059. DIG5_DIG_BE_CNTL__DIG_MODE_MASK
95060. DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT
95061. DIG5_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
95062. DIG5_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
95063. DIG5_DIG_BE_CNTL__DIG_SWAP_MASK
95064. DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT
95065. DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
95066. DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
95067. DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
95068. DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
95069. DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
95070. DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
95071. DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
95072. DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
95073. DIG5_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK
95074. DIG5_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT
95075. DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
95076. DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
95077. DIG5_DIG_FE_CNTL__DIG_START_MASK
95078. DIG5_DIG_FE_CNTL__DIG_START__SHIFT
95079. DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
95080. DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
95081. DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
95082. DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
95083. DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
95084. DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
95085. DIG5_DIG_FE_CNTL__DOLBY_VISION_EN_MASK
95086. DIG5_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT
95087. DIG5_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK
95088. DIG5_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT
95089. DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
95090. DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
95091. DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
95092. DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
95093. DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
95094. DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
95095. DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
95096. DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
95097. DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
95098. DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
95099. DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
95100. DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
95101. DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
95102. DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
95103. DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
95104. DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
95105. DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
95106. DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
95107. DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
95108. DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
95109. DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
95110. DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
95111. DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
95112. DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
95113. DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
95114. DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
95115. DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
95116. DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
95117. DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
95118. DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
95119. DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
95120. DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
95121. DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
95122. DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
95123. DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
95124. DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
95125. DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
95126. DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
95127. DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
95128. DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
95129. DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
95130. DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
95131. DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
95132. DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
95133. DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
95134. DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
95135. DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
95136. DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
95137. DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
95138. DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
95139. DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
95140. DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
95141. DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
95142. DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
95143. DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
95144. DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
95145. DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
95146. DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
95147. DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
95148. DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
95149. DIG5_DIG_VERSION__DIG_TYPE_MASK
95150. DIG5_DIG_VERSION__DIG_TYPE__SHIFT
95151. DIG5_DME_CONTROL__METADATA_DB_DISABLE_MASK
95152. DIG5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT
95153. DIG5_DME_CONTROL__METADATA_DB_PENDING_MASK
95154. DIG5_DME_CONTROL__METADATA_DB_PENDING__SHIFT
95155. DIG5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK
95156. DIG5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT
95157. DIG5_DME_CONTROL__METADATA_DB_TAKEN_MASK
95158. DIG5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT
95159. DIG5_DME_CONTROL__METADATA_ENGINE_EN_MASK
95160. DIG5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT
95161. DIG5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK
95162. DIG5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT
95163. DIG5_DME_CONTROL__METADATA_STREAM_TYPE_MASK
95164. DIG5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT
95165. DIG5_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK
95166. DIG5_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT
95167. DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
95168. DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
95169. DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
95170. DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
95171. DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
95172. DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
95173. DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
95174. DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
95175. DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
95176. DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
95177. DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
95178. DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
95179. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
95180. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
95181. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
95182. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
95183. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
95184. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
95185. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
95186. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
95187. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
95188. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
95189. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
95190. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
95191. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
95192. DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
95193. DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
95194. DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
95195. DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
95196. DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
95197. DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
95198. DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
95199. DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
95200. DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
95201. DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
95202. DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
95203. DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
95204. DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
95205. DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
95206. DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
95207. DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
95208. DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
95209. DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
95210. DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
95211. DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
95212. DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
95213. DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
95214. DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
95215. DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
95216. DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
95217. DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
95218. DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
95219. DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
95220. DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
95221. DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
95222. DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
95223. DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
95224. DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
95225. DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
95226. DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
95227. DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
95228. DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
95229. DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
95230. DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
95231. DIG5_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK
95232. DIG5_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT
95233. DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK
95234. DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT
95235. DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK
95236. DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT
95237. DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
95238. DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
95239. DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
95240. DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
95241. DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK
95242. DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
95243. DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK
95244. DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
95245. DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
95246. DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
95247. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
95248. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
95249. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
95250. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK
95251. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT
95252. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
95253. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
95254. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
95255. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
95256. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
95257. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
95258. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK
95259. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT
95260. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
95261. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
95262. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
95263. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK
95264. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT
95265. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK
95266. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT
95267. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK
95268. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT
95269. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK
95270. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT
95271. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK
95272. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT
95273. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK
95274. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT
95275. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK
95276. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT
95277. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK
95278. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT
95279. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK
95280. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT
95281. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK
95282. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT
95283. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK
95284. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT
95285. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK
95286. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT
95287. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK
95288. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT
95289. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK
95290. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT
95291. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK
95292. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT
95293. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK
95294. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT
95295. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK
95296. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT
95297. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK
95298. DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT
95299. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK
95300. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT
95301. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK
95302. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT
95303. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
95304. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
95305. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
95306. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
95307. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
95308. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
95309. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
95310. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
95311. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
95312. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
95313. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
95314. DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
95315. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK
95316. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT
95317. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK
95318. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT
95319. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
95320. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
95321. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
95322. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
95323. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
95324. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
95325. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
95326. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
95327. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
95328. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
95329. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
95330. DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
95331. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK
95332. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT
95333. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK
95334. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT
95335. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
95336. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
95337. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
95338. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
95339. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
95340. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
95341. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
95342. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
95343. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
95344. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
95345. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
95346. DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
95347. DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK
95348. DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT
95349. DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK
95350. DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT
95351. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK
95352. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK
95353. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT
95354. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT
95355. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK
95356. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK
95357. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT
95358. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT
95359. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK
95360. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK
95361. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT
95362. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT
95363. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK
95364. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK
95365. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT
95366. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT
95367. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK
95368. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK
95369. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT
95370. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT
95371. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK
95372. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK
95373. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT
95374. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT
95375. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK
95376. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK
95377. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT
95378. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT
95379. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK
95380. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK
95381. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT
95382. DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT
95383. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
95384. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
95385. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
95386. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
95387. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
95388. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
95389. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
95390. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
95391. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
95392. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
95393. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
95394. DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
95395. DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
95396. DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
95397. DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
95398. DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
95399. DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
95400. DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
95401. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK
95402. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT
95403. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK
95404. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK
95405. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT
95406. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT
95407. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK
95408. DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT
95409. DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
95410. DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
95411. DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
95412. DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
95413. DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK
95414. DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
95415. DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
95416. DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
95417. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
95418. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
95419. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
95420. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
95421. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
95422. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
95423. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
95424. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
95425. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
95426. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
95427. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
95428. DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
95429. DIG5_REGISTER_OFFSET
95430. DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
95431. DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
95432. DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
95433. DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
95434. DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
95435. DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
95436. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
95437. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
95438. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
95439. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
95440. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
95441. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
95442. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
95443. DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
95444. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
95445. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
95446. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
95447. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
95448. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
95449. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
95450. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
95451. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
95452. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
95453. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
95454. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
95455. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
95456. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
95457. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
95458. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
95459. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
95460. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
95461. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
95462. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
95463. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
95464. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
95465. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
95466. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
95467. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
95468. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
95469. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
95470. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
95471. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
95472. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
95473. DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
95474. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
95475. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
95476. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
95477. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
95478. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
95479. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
95480. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
95481. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
95482. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
95483. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
95484. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
95485. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
95486. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
95487. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
95488. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
95489. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
95490. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
95491. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
95492. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
95493. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
95494. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
95495. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
95496. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
95497. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
95498. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
95499. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
95500. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
95501. DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
95502. DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK
95503. DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
95504. DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK
95505. DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
95506. DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK
95507. DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
95508. DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK
95509. DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
95510. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
95511. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
95512. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
95513. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
95514. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
95515. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
95516. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
95517. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
95518. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
95519. DIG5_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
95520. DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
95521. DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
95522. DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
95523. DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
95524. DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
95525. DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
95526. DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
95527. DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
95528. DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
95529. DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
95530. DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK
95531. DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT
95532. DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK
95533. DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT
95534. DIG6_AFMT_60958_0__AFMT_60958_CS_A_MASK
95535. DIG6_AFMT_60958_0__AFMT_60958_CS_A__SHIFT
95536. DIG6_AFMT_60958_0__AFMT_60958_CS_B_MASK
95537. DIG6_AFMT_60958_0__AFMT_60958_CS_B__SHIFT
95538. DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
95539. DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
95540. DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
95541. DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
95542. DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
95543. DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
95544. DIG6_AFMT_60958_0__AFMT_60958_CS_C_MASK
95545. DIG6_AFMT_60958_0__AFMT_60958_CS_C__SHIFT
95546. DIG6_AFMT_60958_0__AFMT_60958_CS_D_MASK
95547. DIG6_AFMT_60958_0__AFMT_60958_CS_D__SHIFT
95548. DIG6_AFMT_60958_0__AFMT_60958_CS_MODE_MASK
95549. DIG6_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
95550. DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
95551. DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
95552. DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
95553. DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
95554. DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
95555. DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
95556. DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
95557. DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
95558. DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
95559. DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
95560. DIG6_AFMT_60958_1__AFMT_60958_VALID_L_MASK
95561. DIG6_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
95562. DIG6_AFMT_60958_1__AFMT_60958_VALID_R_MASK
95563. DIG6_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
95564. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
95565. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
95566. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
95567. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
95568. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
95569. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
95570. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
95571. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
95572. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
95573. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
95574. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
95575. DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
95576. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
95577. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
95578. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
95579. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
95580. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
95581. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
95582. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
95583. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
95584. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
95585. DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
95586. DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
95587. DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
95588. DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
95589. DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
95590. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
95591. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
95592. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
95593. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
95594. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
95595. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
95596. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
95597. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
95598. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
95599. DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
95600. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
95601. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
95602. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
95603. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
95604. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
95605. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
95606. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
95607. DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
95608. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
95609. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
95610. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
95611. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
95612. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
95613. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
95614. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
95615. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
95616. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
95617. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
95618. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
95619. DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
95620. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
95621. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
95622. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
95623. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
95624. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
95625. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
95626. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
95627. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
95628. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
95629. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
95630. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
95631. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
95632. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
95633. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
95634. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
95635. DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
95636. DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
95637. DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
95638. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
95639. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
95640. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
95641. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
95642. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
95643. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
95644. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
95645. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
95646. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
95647. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
95648. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
95649. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
95650. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
95651. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
95652. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
95653. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
95654. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
95655. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
95656. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
95657. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
95658. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
95659. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
95660. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
95661. DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
95662. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
95663. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
95664. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
95665. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
95666. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
95667. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
95668. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
95669. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
95670. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
95671. DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
95672. DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
95673. DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
95674. DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
95675. DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
95676. DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
95677. DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
95678. DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
95679. DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
95680. DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
95681. DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
95682. DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
95683. DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
95684. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
95685. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
95686. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
95687. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
95688. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
95689. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
95690. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
95691. DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
95692. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
95693. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
95694. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
95695. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
95696. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
95697. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
95698. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
95699. DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
95700. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
95701. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
95702. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
95703. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
95704. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
95705. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
95706. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
95707. DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
95708. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
95709. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
95710. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
95711. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
95712. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
95713. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
95714. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
95715. DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
95716. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
95717. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
95718. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
95719. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
95720. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
95721. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
95722. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
95723. DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
95724. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
95725. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
95726. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
95727. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
95728. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
95729. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
95730. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
95731. DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
95732. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
95733. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
95734. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
95735. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
95736. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
95737. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
95738. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
95739. DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
95740. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
95741. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
95742. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
95743. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
95744. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
95745. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
95746. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
95747. DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
95748. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
95749. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
95750. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
95751. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
95752. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
95753. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
95754. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
95755. DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
95756. DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
95757. DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
95758. DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
95759. DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
95760. DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
95761. DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
95762. DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
95763. DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
95764. DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
95765. DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
95766. DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
95767. DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
95768. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
95769. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
95770. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
95771. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
95772. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
95773. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
95774. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
95775. DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
95776. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
95777. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
95778. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
95779. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
95780. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
95781. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
95782. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
95783. DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
95784. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
95785. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
95786. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
95787. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
95788. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
95789. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
95790. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
95791. DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
95792. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
95793. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
95794. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
95795. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
95796. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
95797. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
95798. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
95799. DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
95800. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
95801. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
95802. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
95803. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
95804. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
95805. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
95806. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
95807. DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
95808. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
95809. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
95810. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
95811. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
95812. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
95813. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
95814. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
95815. DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
95816. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
95817. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
95818. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
95819. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
95820. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
95821. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
95822. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
95823. DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
95824. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
95825. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
95826. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
95827. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
95828. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
95829. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
95830. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
95831. DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
95832. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
95833. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
95834. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
95835. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
95836. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
95837. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
95838. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
95839. DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
95840. DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
95841. DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
95842. DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
95843. DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
95844. DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
95845. DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
95846. DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
95847. DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
95848. DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
95849. DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
95850. DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
95851. DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
95852. DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
95853. DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
95854. DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
95855. DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
95856. DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
95857. DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
95858. DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
95859. DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
95860. DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
95861. DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
95862. DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
95863. DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
95864. DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
95865. DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
95866. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK
95867. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK
95868. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT
95869. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT
95870. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK
95871. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK
95872. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT
95873. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT
95874. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK
95875. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK
95876. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT
95877. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT
95878. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK
95879. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK
95880. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT
95881. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT
95882. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK
95883. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK
95884. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT
95885. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT
95886. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK
95887. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK
95888. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT
95889. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT
95890. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK
95891. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK
95892. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT
95893. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT
95894. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK
95895. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK
95896. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT
95897. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT
95898. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK
95899. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK
95900. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT
95901. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT
95902. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK
95903. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK
95904. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT
95905. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT
95906. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK
95907. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK
95908. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT
95909. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT
95910. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK
95911. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK
95912. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT
95913. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT
95914. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK
95915. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK
95916. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT
95917. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT
95918. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK
95919. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK
95920. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT
95921. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT
95922. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK
95923. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK
95924. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT
95925. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT
95926. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK
95927. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK
95928. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT
95929. DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT
95930. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
95931. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
95932. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
95933. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
95934. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK
95935. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT
95936. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK
95937. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT
95938. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
95939. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
95940. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK
95941. DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT
95942. DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
95943. DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
95944. DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
95945. DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
95946. DIG6_DIG_BE_CNTL__DIG_HPD_SELECT_MASK
95947. DIG6_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
95948. DIG6_DIG_BE_CNTL__DIG_MODE_MASK
95949. DIG6_DIG_BE_CNTL__DIG_MODE__SHIFT
95950. DIG6_DIG_BE_CNTL__DIG_SWAP_MASK
95951. DIG6_DIG_BE_CNTL__DIG_SWAP__SHIFT
95952. DIG6_DIG_BE_EN_CNTL__DIG_ENABLE_MASK
95953. DIG6_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
95954. DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
95955. DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
95956. DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
95957. DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
95958. DIG6_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK
95959. DIG6_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT
95960. DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
95961. DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
95962. DIG6_DIG_FE_CNTL__DIG_START_MASK
95963. DIG6_DIG_FE_CNTL__DIG_START__SHIFT
95964. DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
95965. DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
95966. DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
95967. DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
95968. DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
95969. DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
95970. DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
95971. DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
95972. DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
95973. DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
95974. DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
95975. DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
95976. DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
95977. DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
95978. DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
95979. DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
95980. DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
95981. DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
95982. DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
95983. DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
95984. DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
95985. DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
95986. DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
95987. DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
95988. DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
95989. DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
95990. DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
95991. DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
95992. DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
95993. DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
95994. DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
95995. DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
95996. DIG6_DIG_LANE_ENABLE__DIG_CLK_EN_MASK
95997. DIG6_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
95998. DIG6_DIG_LANE_ENABLE__DIG_LANE0EN_MASK
95999. DIG6_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
96000. DIG6_DIG_LANE_ENABLE__DIG_LANE1EN_MASK
96001. DIG6_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
96002. DIG6_DIG_LANE_ENABLE__DIG_LANE2EN_MASK
96003. DIG6_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
96004. DIG6_DIG_LANE_ENABLE__DIG_LANE3EN_MASK
96005. DIG6_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
96006. DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
96007. DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
96008. DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
96009. DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
96010. DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
96011. DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
96012. DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
96013. DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
96014. DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
96015. DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
96016. DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
96017. DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
96018. DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
96019. DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
96020. DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
96021. DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
96022. DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
96023. DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
96024. DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
96025. DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
96026. DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
96027. DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
96028. DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
96029. DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
96030. DIG6_DIG_VERSION__DIG_TYPE_MASK
96031. DIG6_DIG_VERSION__DIG_TYPE__SHIFT
96032. DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
96033. DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
96034. DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
96035. DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
96036. DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
96037. DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
96038. DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
96039. DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
96040. DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
96041. DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
96042. DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
96043. DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
96044. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
96045. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
96046. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
96047. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
96048. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
96049. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
96050. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
96051. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
96052. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
96053. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
96054. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
96055. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
96056. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
96057. DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
96058. DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
96059. DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
96060. DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
96061. DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
96062. DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
96063. DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
96064. DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
96065. DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
96066. DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
96067. DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
96068. DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
96069. DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
96070. DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
96071. DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
96072. DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
96073. DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
96074. DIG6_HDMI_CONTROL__HDMI_ERROR_ACK_MASK
96075. DIG6_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
96076. DIG6_HDMI_CONTROL__HDMI_ERROR_MASK_MASK
96077. DIG6_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
96078. DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
96079. DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
96080. DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
96081. DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
96082. DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
96083. DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
96084. DIG6_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK
96085. DIG6_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT
96086. DIG6_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK
96087. DIG6_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT
96088. DIG6_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK
96089. DIG6_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT
96090. DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK
96091. DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT
96092. DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK
96093. DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT
96094. DIG6_HDMI_GC__HDMI_DEFAULT_PHASE_MASK
96095. DIG6_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
96096. DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
96097. DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
96098. DIG6_HDMI_GC__HDMI_GC_AVMUTE_MASK
96099. DIG6_HDMI_GC__HDMI_GC_AVMUTE__SHIFT
96100. DIG6_HDMI_GC__HDMI_PACKING_PHASE_MASK
96101. DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
96102. DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
96103. DIG6_HDMI_GC__HDMI_PACKING_PHASE__SHIFT
96104. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
96105. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
96106. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
96107. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
96108. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
96109. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
96110. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
96111. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
96112. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
96113. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
96114. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
96115. DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
96116. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
96117. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
96118. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
96119. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
96120. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
96121. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
96122. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
96123. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
96124. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
96125. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
96126. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
96127. DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
96128. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK
96129. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT
96130. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK
96131. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT
96132. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK
96133. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT
96134. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK
96135. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT
96136. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK
96137. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT
96138. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK
96139. DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT
96140. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK
96141. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT
96142. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK
96143. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT
96144. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK
96145. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT
96146. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK
96147. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT
96148. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK
96149. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT
96150. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK
96151. DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT
96152. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
96153. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
96154. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
96155. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
96156. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
96157. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
96158. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
96159. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
96160. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
96161. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
96162. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
96163. DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
96164. DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
96165. DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
96166. DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
96167. DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
96168. DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
96169. DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
96170. DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
96171. DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
96172. DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
96173. DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
96174. DIG6_HDMI_STATUS__HDMI_ERROR_INT_MASK
96175. DIG6_HDMI_STATUS__HDMI_ERROR_INT__SHIFT
96176. DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
96177. DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
96178. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
96179. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
96180. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
96181. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
96182. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
96183. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
96184. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
96185. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
96186. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
96187. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
96188. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
96189. DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
96190. DIG6_REGISTER_OFFSET
96191. DIG6_TMDS_CNTL__TMDS_SYNC_PHASE_MASK
96192. DIG6_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
96193. DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
96194. DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
96195. DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
96196. DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
96197. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
96198. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
96199. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
96200. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
96201. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
96202. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
96203. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
96204. DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
96205. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
96206. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
96207. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
96208. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
96209. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
96210. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
96211. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
96212. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
96213. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
96214. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
96215. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
96216. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
96217. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
96218. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
96219. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
96220. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
96221. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
96222. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
96223. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
96224. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
96225. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
96226. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
96227. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
96228. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
96229. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
96230. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
96231. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
96232. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
96233. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
96234. DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
96235. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
96236. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
96237. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
96238. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
96239. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
96240. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
96241. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
96242. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
96243. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
96244. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
96245. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
96246. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
96247. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
96248. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
96249. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
96250. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
96251. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
96252. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
96253. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
96254. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
96255. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
96256. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
96257. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
96258. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
96259. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
96260. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
96261. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
96262. DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
96263. DIG6_TMDS_CTL_BITS__TMDS_CTL0_MASK
96264. DIG6_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
96265. DIG6_TMDS_CTL_BITS__TMDS_CTL1_MASK
96266. DIG6_TMDS_CTL_BITS__TMDS_CTL1__SHIFT
96267. DIG6_TMDS_CTL_BITS__TMDS_CTL2_MASK
96268. DIG6_TMDS_CTL_BITS__TMDS_CTL2__SHIFT
96269. DIG6_TMDS_CTL_BITS__TMDS_CTL3_MASK
96270. DIG6_TMDS_CTL_BITS__TMDS_CTL3__SHIFT
96271. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
96272. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
96273. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
96274. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
96275. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
96276. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
96277. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
96278. DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
96279. DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
96280. DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
96281. DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
96282. DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
96283. DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
96284. DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
96285. DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
96286. DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
96287. DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
96288. DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
96289. DIG7_REGISTER_OFFSET
96290. DIG8_REGISTER_OFFSET
96291. DIGA_BE_SOFT_RESET
96292. DIGA_BE_SOFT_RESET_0
96293. DIGA_BE_SOFT_RESET_1
96294. DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT
96295. DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT
96296. DIGA_DP_VID_STREAM_DISABLE_INTERRUPT
96297. DIGA_FE_SOFT_RESET
96298. DIGA_FE_SOFT_RESET_0
96299. DIGA_FE_SOFT_RESET_1
96300. DIGBEEP_HZ_MAX
96301. DIGBEEP_HZ_MIN
96302. DIGBEEP_HZ_STEP
96303. DIGB_BE_SOFT_RESET
96304. DIGB_BE_SOFT_RESET_0
96305. DIGB_BE_SOFT_RESET_1
96306. DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT
96307. DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT
96308. DIGB_DP_VID_STREAM_DISABLE_INTERRUPT
96309. DIGB_FE_SOFT_RESET
96310. DIGB_FE_SOFT_RESET_0
96311. DIGB_FE_SOFT_RESET_1
96312. DIGCTRL
96313. DIGC_BE_SOFT_RESET
96314. DIGC_BE_SOFT_RESET_0
96315. DIGC_BE_SOFT_RESET_1
96316. DIGC_FE_SOFT_RESET
96317. DIGC_FE_SOFT_RESET_0
96318. DIGC_FE_SOFT_RESET_1
96319. DIGD_BE_SOFT_RESET
96320. DIGD_BE_SOFT_RESET_0
96321. DIGD_BE_SOFT_RESET_1
96322. DIGD_FE_SOFT_RESET
96323. DIGD_FE_SOFT_RESET_0
96324. DIGD_FE_SOFT_RESET_1
96325. DIGEST
96326. DIGEST_ALGO_MAX
96327. DIGEST_ALGO_SHA1
96328. DIGEST_ALGO_SHA256
96329. DIGEST_PTR
96330. DIGE_BE_SOFT_RESET
96331. DIGE_BE_SOFT_RESET_0
96332. DIGE_BE_SOFT_RESET_1
96333. DIGE_FE_SOFT_RESET
96334. DIGE_FE_SOFT_RESET_0
96335. DIGE_FE_SOFT_RESET_1
96336. DIGF_BE_SOFT_RESET
96337. DIGF_BE_SOFT_RESET_0
96338. DIGF_BE_SOFT_RESET_1
96339. DIGF_FE_SOFT_RESET
96340. DIGF_FE_SOFT_RESET_0
96341. DIGF_FE_SOFT_RESET_1
96342. DIGG_BE_SOFT_RESET
96343. DIGG_BE_SOFT_RESET_0
96344. DIGG_BE_SOFT_RESET_1
96345. DIGG_FE_SOFT_RESET
96346. DIGG_FE_SOFT_RESET_0
96347. DIGG_FE_SOFT_RESET_1
96348. DIGICOLOR_USART_NR
96349. DIGICU_MAJOR
96350. DIGIFACE_DS_CHANNELS
96351. DIGIFACE_SS_CHANNELS
96352. DIGITAL5_ACTUAL_SPEED_TX_MASK
96353. DIGITALNOW_BLUEBIRD_DUAL_1_COLD
96354. DIGITALNOW_BLUEBIRD_DUAL_1_WARM
96355. DIGITAL_ATR_REQ_MAX_SIZE
96356. DIGITAL_ATR_REQ_MIN_SIZE
96357. DIGITAL_ATR_RES_RWT
96358. DIGITAL_ATR_RES_TO_WT
96359. DIGITAL_ATS_FSCI
96360. DIGITAL_ATS_MAX_FSC
96361. DIGITAL_ATTRIB_P1_SUPRESS_EOS
96362. DIGITAL_ATTRIB_P1_SUPRESS_SOS
96363. DIGITAL_ATTRIB_P1_TR0_DEFAULT
96364. DIGITAL_ATTRIB_P1_TR1_DEFAULT
96365. DIGITAL_ATTRIB_P2_LISTEN_POLL_1
96366. DIGITAL_ATTRIB_P2_MAX_FRAME_256
96367. DIGITAL_ATTRIB_P2_POLL_LISTEN_1
96368. DIGITAL_ATTRIB_P4_DID
96369. DIGITAL_CMD_ALL_REQ
96370. DIGITAL_CMD_ATR_REQ
96371. DIGITAL_CMD_ATR_RES
96372. DIGITAL_CMD_ATTRIB_REQ
96373. DIGITAL_CMD_DEP_REQ
96374. DIGITAL_CMD_DEP_RES
96375. DIGITAL_CMD_IN_SEND
96376. DIGITAL_CMD_ISO15693_INVENTORY_REQ
96377. DIGITAL_CMD_PSL_REQ
96378. DIGITAL_CMD_PSL_RES
96379. DIGITAL_CMD_SEL_REQ_CL1
96380. DIGITAL_CMD_SEL_REQ_CL2
96381. DIGITAL_CMD_SEL_REQ_CL3
96382. DIGITAL_CMD_SENSB_REQ
96383. DIGITAL_CMD_SENSB_RES
96384. DIGITAL_CMD_SENSF_REQ
96385. DIGITAL_CMD_SENSF_RES
96386. DIGITAL_CMD_SENS_REQ
96387. DIGITAL_CMD_TG_LISTEN
96388. DIGITAL_CMD_TG_LISTEN_MD
96389. DIGITAL_CMD_TG_LISTEN_MDAA
96390. DIGITAL_CMD_TG_SEND
96391. DIGITAL_CRC_LEN
96392. DIGITAL_DID_MAX
96393. DIGITAL_DRV_CAPS_IN_CRC
96394. DIGITAL_DRV_CAPS_TG_CRC
96395. DIGITAL_EVERYWHERE_OUI
96396. DIGITAL_GB_BIT
96397. DIGITAL_ISO15693_REQ_FLAG_DATA_RATE
96398. DIGITAL_ISO15693_REQ_FLAG_INVENTORY
96399. DIGITAL_ISO15693_REQ_FLAG_NB_SLOTS
96400. DIGITAL_ISO15693_RES_FLAG_ERROR
96401. DIGITAL_ISO15693_RES_IS_VALID
96402. DIGITAL_ISO_DEP_BLOCK_HAS_DID
96403. DIGITAL_ISO_DEP_I_BLOCK
96404. DIGITAL_ISO_DEP_I_PCB
96405. DIGITAL_ISO_DEP_PCB_TYPE
96406. DIGITAL_ISO_DEP_PNI
96407. DIGITAL_MAX_HEADER_LEN
96408. DIGITAL_MDAA_NFCID1_SIZE
96409. DIGITAL_MIC
96410. DIGITAL_MIFARE_ACK_RES
96411. DIGITAL_MIFARE_READ_RES_LEN
96412. DIGITAL_MIXER_IN0
96413. DIGITAL_MIXER_IN1
96414. DIGITAL_MIXER_IN10
96415. DIGITAL_MIXER_IN11
96416. DIGITAL_MIXER_IN2
96417. DIGITAL_MIXER_IN3
96418. DIGITAL_MIXER_IN4
96419. DIGITAL_MIXER_IN5
96420. DIGITAL_MIXER_IN6
96421. DIGITAL_MIXER_IN7
96422. DIGITAL_MIXER_IN8
96423. DIGITAL_MIXER_IN9
96424. DIGITAL_MIXER_OUT0
96425. DIGITAL_MODES
96426. DIGITAL_MODE_ADAT
96427. DIGITAL_MODE_NONE
96428. DIGITAL_MODE_SPDIF_CDROM
96429. DIGITAL_MODE_SPDIF_OPTICAL
96430. DIGITAL_MODE_SPDIF_RCA
96431. DIGITAL_NFC_DEP_DID_BIT_SET
96432. DIGITAL_NFC_DEP_FRAME_DIR_IN
96433. DIGITAL_NFC_DEP_FRAME_DIR_OUT
96434. DIGITAL_NFC_DEP_IN_MAX_WT
96435. DIGITAL_NFC_DEP_MI_BIT_SET
96436. DIGITAL_NFC_DEP_NACK_BIT_SET
96437. DIGITAL_NFC_DEP_NAD_BIT_SET
96438. DIGITAL_NFC_DEP_NFCA_SOD_SB
96439. DIGITAL_NFC_DEP_N_RETRY_ATN
96440. DIGITAL_NFC_DEP_N_RETRY_NACK
96441. DIGITAL_NFC_DEP_PFB_ACK_NACK_PDU
96442. DIGITAL_NFC_DEP_PFB_DID_BIT
96443. DIGITAL_NFC_DEP_PFB_IS_TIMEOUT
96444. DIGITAL_NFC_DEP_PFB_I_PDU
96445. DIGITAL_NFC_DEP_PFB_MI_BIT
96446. DIGITAL_NFC_DEP_PFB_NACK_BIT
96447. DIGITAL_NFC_DEP_PFB_PNI
96448. DIGITAL_NFC_DEP_PFB_SUPERVISOR_PDU
96449. DIGITAL_NFC_DEP_PFB_TIMEOUT_BIT
96450. DIGITAL_NFC_DEP_PFB_TYPE
96451. DIGITAL_NFC_DEP_REQ_RES_HEADROOM
96452. DIGITAL_NFC_DEP_REQ_RES_TAILROOM
96453. DIGITAL_NFC_DEP_RTOX_MAX
96454. DIGITAL_NFC_DEP_RTOX_VALUE
96455. DIGITAL_NFC_DEP_TG_MAX_WT
96456. DIGITAL_PAYLOAD_BITS_TO_FSL
96457. DIGITAL_PAYLOAD_BITS_TO_PP
96458. DIGITAL_PAYLOAD_FSL_TO_BITS
96459. DIGITAL_PAYLOAD_PP_TO_BITS
96460. DIGITAL_PAYLOAD_SIZE_MAX
96461. DIGITAL_POLL_INTERVAL
96462. DIGITAL_PORTA_HOTPLUG_ENABLE
96463. DIGITAL_PORTA_HOTPLUG_LONG_DETECT
96464. DIGITAL_PORTA_HOTPLUG_NO_DETECT
96465. DIGITAL_PORTA_HOTPLUG_SHORT_DETECT
96466. DIGITAL_PORTA_HOTPLUG_STATUS_MASK
96467. DIGITAL_PORTA_PULSE_DURATION_100ms
96468. DIGITAL_PORTA_PULSE_DURATION_2ms
96469. DIGITAL_PORTA_PULSE_DURATION_4_5ms
96470. DIGITAL_PORTA_PULSE_DURATION_6ms
96471. DIGITAL_PORTA_PULSE_DURATION_MASK
96472. DIGITAL_PORT_HOTPLUG_CNTRL
96473. DIGITAL_PROTO_ISO15693_RF_TECH
96474. DIGITAL_PROTO_NFCA_RF_TECH
96475. DIGITAL_PROTO_NFCB_RF_TECH
96476. DIGITAL_PROTO_NFCF_RF_TECH
96477. DIGITAL_RATS_BYTE1
96478. DIGITAL_RATS_PARAM
96479. DIGITAL_SDD_REQ_SEL_PAR
96480. DIGITAL_SDD_RES_CT
96481. DIGITAL_SDD_RES_LEN
96482. DIGITAL_SEL_RES_IS_NFC_DEP
96483. DIGITAL_SEL_RES_IS_T2T
96484. DIGITAL_SEL_RES_IS_T4T
96485. DIGITAL_SEL_RES_LEN
96486. DIGITAL_SEL_RES_NFCID1_COMPLETE
96487. DIGITAL_SEL_RES_NFC_DEP
96488. DIGITAL_SENSB_ADVANCED
96489. DIGITAL_SENSB_ALLB_REQ
96490. DIGITAL_SENSB_EXTENDED
96491. DIGITAL_SENSB_FSCI
96492. DIGITAL_SENSB_N
96493. DIGITAL_SENSF_FELICA_SC
96494. DIGITAL_SENSF_NFCID2_NFC_DEP_B1
96495. DIGITAL_SENSF_NFCID2_NFC_DEP_B2
96496. DIGITAL_SENSF_REQ_RC_AP
96497. DIGITAL_SENSF_REQ_RC_NONE
96498. DIGITAL_SENSF_REQ_RC_SC
96499. DIGITAL_SENSF_RES_MIN_LENGTH
96500. DIGITAL_SENSF_RES_RD_AP_B1
96501. DIGITAL_SENSF_RES_RD_AP_B2
96502. DIGITAL_SENS_RES_IS_T1T
96503. DIGITAL_SENS_RES_IS_VALID
96504. DIGITAL_SENS_RES_NFC_DEP
96505. DIGITAL_THRU_ONLY_SAMPLERATE
96506. DIGITAL_VIDEO_CREATOR_I
96507. DIGITIZER_USAGE_TILT_X
96508. DIGITIZER_USAGE_TILT_Y
96509. DIGITIZER_USAGE_TIP_PRESSURE
96510. DIGITS
96511. DIGIT_EN_MASK
96512. DIGI_2_ID
96513. DIGI_4_ID
96514. DIGI_ASSERT
96515. DIGI_BAD_FIRST_PARAMETER
96516. DIGI_BAD_SECOND_PARAMETER
96517. DIGI_BAUD_110
96518. DIGI_BAUD_115200
96519. DIGI_BAUD_1200
96520. DIGI_BAUD_14400
96521. DIGI_BAUD_150
96522. DIGI_BAUD_153600
96523. DIGI_BAUD_1800
96524. DIGI_BAUD_19200
96525. DIGI_BAUD_200
96526. DIGI_BAUD_230400
96527. DIGI_BAUD_2400
96528. DIGI_BAUD_28800
96529. DIGI_BAUD_300
96530. DIGI_BAUD_38400
96531. DIGI_BAUD_460800
96532. DIGI_BAUD_4800
96533. DIGI_BAUD_50
96534. DIGI_BAUD_57600
96535. DIGI_BAUD_600
96536. DIGI_BAUD_7200
96537. DIGI_BAUD_75
96538. DIGI_BAUD_76800
96539. DIGI_BAUD_9600
96540. DIGI_BREAK_ERROR
96541. DIGI_CLOSE_TIMEOUT
96542. DIGI_CMD_AND_UART_REGISTER
96543. DIGI_CMD_BREAK_CONTROL
96544. DIGI_CMD_GET_PORT_TYPE
96545. DIGI_CMD_IFLUSH_FIFO
96546. DIGI_CMD_LOCAL_LOOPBACK
96547. DIGI_CMD_OR_UART_REGISTER
96548. DIGI_CMD_READ_INPUT_SIGNALS
96549. DIGI_CMD_READ_UART_REGISTER
96550. DIGI_CMD_RECEIVE_DATA
96551. DIGI_CMD_RECEIVE_DISABLE
96552. DIGI_CMD_RECEIVE_ENABLE
96553. DIGI_CMD_SEND_DATA
96554. DIGI_CMD_SET_BAUD_RATE
96555. DIGI_CMD_SET_DTR_SIGNAL
96556. DIGI_CMD_SET_INPUT_FLOW_CONTROL
96557. DIGI_CMD_SET_OUTPUT_FLOW_CONTROL
96558. DIGI_CMD_SET_PARITY
96559. DIGI_CMD_SET_RTS_SIGNAL
96560. DIGI_CMD_SET_STOP_BITS
96561. DIGI_CMD_SET_WORD_SIZE
96562. DIGI_CMD_TRANSMIT_IDLE
96563. DIGI_CMD_WRITE_UART_REGISTER
96564. DIGI_DEASSERT
96565. DIGI_DISABLE
96566. DIGI_DTR_ACTIVE
96567. DIGI_DTR_INACTIVE
96568. DIGI_DTR_INPUT_FLOW_CONTROL
96569. DIGI_ENABLE
96570. DIGI_FLUSH_RX
96571. DIGI_FLUSH_TX
96572. DIGI_FRAMING_ERROR
96573. DIGI_INPUT_FLOW_CONTROL_DTR
96574. DIGI_INPUT_FLOW_CONTROL_RTS
96575. DIGI_INPUT_FLOW_CONTROL_XON_XOFF
96576. DIGI_INVALID_LINE
96577. DIGI_INVALID_OPCODE
96578. DIGI_IN_BUF_SIZE
96579. DIGI_MAJOR
96580. DIGI_NO_ERROR
96581. DIGI_OUTPUT_FLOW_CONTROL_CTS
96582. DIGI_OUTPUT_FLOW_CONTROL_DSR
96583. DIGI_OUTPUT_FLOW_CONTROL_XON_XOFF
96584. DIGI_OUT_BUF_SIZE
96585. DIGI_OVERRUN_ERROR
96586. DIGI_PARITY_ERROR
96587. DIGI_PARITY_EVEN
96588. DIGI_PARITY_MARK
96589. DIGI_PARITY_NONE
96590. DIGI_PARITY_ODD
96591. DIGI_PARITY_SPACE
96592. DIGI_READ_INPUT_SIGNALS_BUSY
96593. DIGI_READ_INPUT_SIGNALS_CTS
96594. DIGI_READ_INPUT_SIGNALS_DCD
96595. DIGI_READ_INPUT_SIGNALS_DSR
96596. DIGI_READ_INPUT_SIGNALS_ERR
96597. DIGI_READ_INPUT_SIGNALS_PE
96598. DIGI_READ_INPUT_SIGNALS_RI
96599. DIGI_READ_INPUT_SIGNALS_SLOT
96600. DIGI_RESUME_TX
96601. DIGI_RETRY_TIMEOUT
96602. DIGI_RTS_ACTIVE
96603. DIGI_RTS_INACTIVE
96604. DIGI_RTS_INPUT_FLOW_CONTROL
96605. DIGI_RTS_TOGGLE
96606. DIGI_STOP_BITS_1
96607. DIGI_STOP_BITS_2
96608. DIGI_TRANSMIT_IDLE
96609. DIGI_TRANSMIT_NOT_IDLE
96610. DIGI_VENDOR_ID
96611. DIGI_WORD_SIZE_5
96612. DIGI_WORD_SIZE_6
96613. DIGI_WORD_SIZE_7
96614. DIGI_WORD_SIZE_8
96615. DIGLPA_BE_SOFT_RESET
96616. DIGLPA_BE_SOFT_RESET_0
96617. DIGLPA_BE_SOFT_RESET_1
96618. DIGLPA_FE_SOFT_RESET
96619. DIGLPA_FE_SOFT_RESET_0
96620. DIGLPA_FE_SOFT_RESET_1
96621. DIGLPB_BE_SOFT_RESET
96622. DIGLPB_BE_SOFT_RESET_0
96623. DIGLPB_BE_SOFT_RESET_1
96624. DIGLPB_FE_SOFT_RESET
96625. DIGLPB_FE_SOFT_RESET_0
96626. DIGLPB_FE_SOFT_RESET_1
96627. DIGMIC_3P25M_1P625M_SEL_CTL_MASK
96628. DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT
96629. DIGMIC_3P25M_1P625M_SEL_CTL_SFT
96630. DIGMIC_TESTCK_SEL_MASK
96631. DIGMIC_TESTCK_SEL_MASK_SFT
96632. DIGMIC_TESTCK_SEL_SFT
96633. DIGMIC_TESTCK_SRC_SEL_MASK
96634. DIGMIC_TESTCK_SRC_SEL_MASK_SFT
96635. DIGMIC_TESTCK_SRC_SEL_SFT
96636. DIGRFEN
96637. DIGR_INT_G0
96638. DIGR_INT_G1
96639. DIGR_INT_G2
96640. DIG_10BIT_TEST_PATTERN
96641. DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM
96642. DIG_ALGO_BY_FALSE_ALARM
96643. DIG_ALGO_BY_RSSI
96644. DIG_ALGO_BY_TOW_PORT
96645. DIG_ALGO_MAX
96646. DIG_ALL_PIXEL
96647. DIG_ALTERNATING_TEST_PATTERN
96648. DIG_AP_ADD_STATION
96649. DIG_AP_CONNECT
96650. DIG_AP_DISCONNECT
96651. DIG_BE_CNTL_HPD1
96652. DIG_BE_CNTL_HPD2
96653. DIG_BE_CNTL_HPD3
96654. DIG_BE_CNTL_HPD4
96655. DIG_BE_CNTL_HPD5
96656. DIG_BE_CNTL_HPD6
96657. DIG_BE_CNTL_HPD_SELECT
96658. DIG_BE_CNTL_MODE
96659. DIG_BE_CNTL_NO_HPD
96660. DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
96661. DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
96662. DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK
96663. DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT
96664. DIG_BE_CNTL__DIG_HPD_SELECT_MASK
96665. DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT
96666. DIG_BE_CNTL__DIG_MODE_MASK
96667. DIG_BE_CNTL__DIG_MODE__SHIFT
96668. DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK
96669. DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT
96670. DIG_BE_CNTL__DIG_SWAP_MASK
96671. DIG_BE_CNTL__DIG_SWAP__SHIFT
96672. DIG_BE_DP_MST_MODE
96673. DIG_BE_DP_SST_MODE
96674. DIG_BE_EN_CNTL__DIG_ENABLE_MASK
96675. DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT
96676. DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK
96677. DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT
96678. DIG_BE_RESERVED1
96679. DIG_BE_RESERVED2
96680. DIG_BE_RESERVED3
96681. DIG_BE_RESERVED4
96682. DIG_BE_SDVO_RESERVED
96683. DIG_BE_TMDS_DVI_MODE
96684. DIG_BE_TMDS_HDMI_MODE
96685. DIG_CLK_CTL_D_MBHC_CLK_EN
96686. DIG_CLK_CTL_D_MBHC_CLK_EN_MASK
96687. DIG_CLK_CTL_NCP_CLK_EN
96688. DIG_CLK_CTL_NCP_CLK_EN_MASK
96689. DIG_CLK_CTL_RXD1_CLK_EN
96690. DIG_CLK_CTL_RXD2_CLK_EN
96691. DIG_CLK_CTL_RXD3_CLK_EN
96692. DIG_CLK_CTL_RXD_PDM_CLK_EN
96693. DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK
96694. DIG_CLK_CTL_TXD_CLK_EN
96695. DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK
96696. DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT
96697. DIG_CONNECT
96698. DIG_CONNECT_MAX
96699. DIG_CORE_RST
96700. DIG_CORE_WORK
96701. DIG_CS_MAX
96702. DIG_CS_RATIO_HIGHER
96703. DIG_CS_RATIO_LOWER
96704. DIG_CTL1
96705. DIG_CTL2
96706. DIG_CVRG_FA_TH_EXTRA_HIGH
96707. DIG_CVRG_FA_TH_HIGH
96708. DIG_CVRG_FA_TH_LOW
96709. DIG_CVRG_MAX
96710. DIG_CVRG_MID
96711. DIG_CVRG_MIN
96712. DIG_DIGITAL_BYPASS_SEL
96713. DIG_DIGITAL_BYPASS_SEL_10BPP_LSB
96714. DIG_DIGITAL_BYPASS_SEL_12BPC_LSB
96715. DIG_DIGITAL_BYPASS_SEL_36BPP
96716. DIG_DIGITAL_BYPASS_SEL_48BPP_LSB
96717. DIG_DIGITAL_BYPASS_SEL_48BPP_MSB
96718. DIG_DIGITAL_BYPASS_SEL_ALPHA
96719. DIG_DIGITAL_BYPASS_SEL_BYPASS
96720. DIG_DISCONNECT
96721. DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT
96722. DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK
96723. DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK
96724. DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK
96725. DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK
96726. DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT
96727. DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK
96728. DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC
96729. DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT
96730. DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK
96731. DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT
96732. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK
96733. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT
96734. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK
96735. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK
96736. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT
96737. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT
96738. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK
96739. DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT
96740. DIG_ENCODER_CONTROL_PARAMETERS
96741. DIG_ENCODER_CONTROL_PARAMETERS_V2
96742. DIG_ENCODER_CONTROL_PARAMETERS_V3
96743. DIG_ENCODER_CONTROL_PARAMETERS_V4
96744. DIG_ENCODER_CONTROL_PARAMETERS_V5
96745. DIG_ENCODER_CONTROL_PS_ALLOCATION
96746. DIG_EVEN_PIXEL_ONLY
96747. DIG_EXT_PORT_STAGE_0
96748. DIG_EXT_PORT_STAGE_1
96749. DIG_EXT_PORT_STAGE_2
96750. DIG_EXT_PORT_STAGE_3
96751. DIG_EXT_PORT_STAGE_MAX
96752. DIG_FE_CNTL_SOURCE_SELECT
96753. DIG_FE_CNTL_STEREOSYNC_SELECT
96754. DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK
96755. DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT
96756. DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK
96757. DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT
96758. DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK
96759. DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT
96760. DIG_FE_CNTL__DIG_START_MASK
96761. DIG_FE_CNTL__DIG_START__SHIFT
96762. DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK
96763. DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT
96764. DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK
96765. DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT
96766. DIG_FE_CNTL__DIG_SWAP_MASK
96767. DIG_FE_CNTL__DIG_SWAP__SHIFT
96768. DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK
96769. DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT
96770. DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK
96771. DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT
96772. DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK
96773. DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT
96774. DIG_FE_SOURCE_FROM_FMT0
96775. DIG_FE_SOURCE_FROM_FMT1
96776. DIG_FE_SOURCE_FROM_FMT2
96777. DIG_FE_SOURCE_FROM_FMT3
96778. DIG_FE_SOURCE_FROM_FMT4
96779. DIG_FE_SOURCE_FROM_FMT5
96780. DIG_FE_SOURCE_FROM_OTG0
96781. DIG_FE_SOURCE_FROM_OTG1
96782. DIG_FE_SOURCE_FROM_OTG2
96783. DIG_FE_SOURCE_FROM_OTG3
96784. DIG_FE_SOURCE_FROM_OTG4
96785. DIG_FE_SOURCE_FROM_OTG5
96786. DIG_FE_SOURCE_RESERVED
96787. DIG_FE_STEREOSYNC_FROM_FMT0
96788. DIG_FE_STEREOSYNC_FROM_FMT1
96789. DIG_FE_STEREOSYNC_FROM_FMT2
96790. DIG_FE_STEREOSYNC_FROM_FMT3
96791. DIG_FE_STEREOSYNC_FROM_FMT4
96792. DIG_FE_STEREOSYNC_FROM_FMT5
96793. DIG_FE_STEREOSYNC_FROM_OTG0
96794. DIG_FE_STEREOSYNC_FROM_OTG1
96795. DIG_FE_STEREOSYNC_FROM_OTG2
96796. DIG_FE_STEREOSYNC_FROM_OTG3
96797. DIG_FE_STEREOSYNC_FROM_OTG4
96798. DIG_FE_STEREOSYNC_FROM_OTG5
96799. DIG_FE_STEREOSYNC_RESERVED
96800. DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK
96801. DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT
96802. DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK
96803. DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT
96804. DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK
96805. DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT
96806. DIG_FIFO_ERROR_ACK
96807. DIG_FIFO_ERROR_ACK_INT
96808. DIG_FIFO_ERROR_NOT_ACK
96809. DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL
96810. DIG_FIFO_FORCE_RECOMP_MINMAX
96811. DIG_FIFO_NOT_FORCE_RECAL_AVERAGE
96812. DIG_FIFO_NOT_FORCE_RECOMP_MINMAX
96813. DIG_FIFO_READ_CLOCK_SRC
96814. DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG
96815. DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE
96816. DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE
96817. DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX
96818. DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL
96819. DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK
96820. DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT
96821. DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK
96822. DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
96823. DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK
96824. DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT
96825. DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK
96826. DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
96827. DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK
96828. DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
96829. DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK
96830. DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT
96831. DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK
96832. DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT
96833. DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK
96834. DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT
96835. DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK
96836. DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT
96837. DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK
96838. DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT
96839. DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK
96840. DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
96841. DIG_FIFO_USE_CAL_AVERAGE_LEVEL
96842. DIG_FIFO_USE_OVERWRITE_LEVEL
96843. DIG_IN
96844. DIG_INPUT_PIXEL_SEL
96845. DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96846. DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96847. DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96848. DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96849. DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96850. DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96851. DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96852. DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96853. DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96854. DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96855. DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96856. DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96857. DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96858. DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96859. DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96860. DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96861. DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96862. DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96863. DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96864. DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96865. DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96866. DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96867. DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96868. DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96869. DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96870. DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96871. DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96872. DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96873. DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK
96874. DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT
96875. DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK
96876. DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT
96877. DIG_IN_DEBUG_MODE
96878. DIG_IN_NORMAL_OPERATION
96879. DIG_LANE_ENABLE__DIG_CLK_EN_MASK
96880. DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT
96881. DIG_LANE_ENABLE__DIG_LANE0EN_MASK
96882. DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT
96883. DIG_LANE_ENABLE__DIG_LANE1EN_MASK
96884. DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT
96885. DIG_LANE_ENABLE__DIG_LANE2EN_MASK
96886. DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT
96887. DIG_LANE_ENABLE__DIG_LANE3EN_MASK
96888. DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT
96889. DIG_MODE
96890. DIG_MODE_DP
96891. DIG_MODE_LVDS
96892. DIG_MODE_SDVO
96893. DIG_MODE_TMDS_DVI
96894. DIG_MODE_TMDS_HDMI
96895. DIG_MULTISTA_CONNECT
96896. DIG_MULTISTA_DISCONNECT
96897. DIG_ODD_PIXEL_ONLY
96898. DIG_OP_TYPE_MAX
96899. DIG_OUT
96900. DIG_OUTPUT_CRC_CNTL_LINK_SEL
96901. DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK
96902. DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT
96903. DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK
96904. DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT
96905. DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK
96906. DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT
96907. DIG_OUTPUT_CRC_DATA_SEL
96908. DIG_OUTPUT_CRC_FOR_ACTIVEONLY
96909. DIG_OUTPUT_CRC_FOR_AUDIO
96910. DIG_OUTPUT_CRC_FOR_FULLFRAME
96911. DIG_OUTPUT_CRC_FOR_VBI
96912. DIG_OUTPUT_CRC_ON_LINK0
96913. DIG_OUTPUT_CRC_ON_LINK1
96914. DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK
96915. DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT
96916. DIG_PD_AT_HIGH_POWER
96917. DIG_PD_AT_LOW_POWER
96918. DIG_PD_AT_NORMAL_POWER
96919. DIG_PD_MAX
96920. DIG_PERF_FA_TH_EXTRA_HIGH
96921. DIG_PERF_FA_TH_HIGH
96922. DIG_PERF_FA_TH_LOW
96923. DIG_PERF_MAX
96924. DIG_PERF_MID
96925. DIG_PLL_CTL1
96926. DIG_PLL_CTL2
96927. DIG_PLL_CTL3
96928. DIG_PLL_CTL4
96929. DIG_PLL_CTL5
96930. DIG_RANDOM_PATTERN_ENABLED
96931. DIG_RANDOM_PATTERN_RESETED
96932. DIG_RANDOM_PATTERN_SEED_RAN_PAT
96933. DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS
96934. DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH
96935. DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK
96936. DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT
96937. DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK
96938. DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT
96939. DIG_REG
96940. DIG_RSSI_GAIN_OFFSET
96941. DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK
96942. DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT
96943. DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK
96944. DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT
96945. DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK
96946. DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT
96947. DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK
96948. DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT
96949. DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK
96950. DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT
96951. DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK
96952. DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT
96953. DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK
96954. DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT
96955. DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK
96956. DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT
96957. DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK
96958. DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT
96959. DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK
96960. DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT
96961. DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK
96962. DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT
96963. DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK
96964. DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT
96965. DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK
96966. DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT
96967. DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK
96968. DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT
96969. DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK
96970. DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT
96971. DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK
96972. DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT
96973. DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK
96974. DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT
96975. DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK
96976. DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT
96977. DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK
96978. DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT
96979. DIG_STA_BEFORE_CONNECT
96980. DIG_STA_CONNECT
96981. DIG_STA_DISCONNECT
96982. DIG_SW_SEL
96983. DIG_T
96984. DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK
96985. DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT
96986. DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK
96987. DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT
96988. DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK
96989. DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT
96990. DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG
96991. DIG_TEST_PATTERN_EXTERNAL_RESET_EN
96992. DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE
96993. DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL
96994. DIG_TEST_PATTERN_NORMAL
96995. DIG_TEST_PATTERN_RANDOM
96996. DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN
96997. DIG_TEST_PATTERN_RANDOM_PATTERN_RESET
96998. DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN
96999. DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK
97000. DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT
97001. DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK
97002. DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT
97003. DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK
97004. DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT
97005. DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK
97006. DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT
97007. DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK
97008. DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT
97009. DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK
97010. DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT
97011. DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK
97012. DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT
97013. DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK
97014. DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT
97015. DIG_THERM_DPM
97016. DIG_THERM_DPM_MASK
97017. DIG_THERM_DPM_SHIFT
97018. DIG_THERM_INTH
97019. DIG_THERM_INTH_MASK
97020. DIG_THERM_INTH_SHIFT
97021. DIG_THERM_INTL
97022. DIG_THERM_INTL_MASK
97023. DIG_THERM_INTL_SHIFT
97024. DIG_TRANSMITTER_CONTROL_PARAMETERS
97025. DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
97026. DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6
97027. DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
97028. DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
97029. DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
97030. DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
97031. DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5
97032. DIG_TRANSMITTER_INFO_HEADER_V3_1
97033. DIG_TRANSMITTER_INFO_HEADER_V3_2
97034. DIG_TRANSMITTER_INFO_HEADER_V3_3
97035. DIG_TWO_PORT_ALGO_FALSE_ALARM
97036. DIG_TWO_PORT_ALGO_RSSI
97037. DIG_TYPE_BACKOFF
97038. DIG_TYPE_DISABLE
97039. DIG_TYPE_ENABLE
97040. DIG_TYPE_RX_GAIN_MAX
97041. DIG_TYPE_RX_GAIN_MIN
97042. DIG_TYPE_THRESH_HIGH
97043. DIG_TYPE_THRESH_LOW
97044. DIG_VERSION__DIG_TYPE_MASK
97045. DIG_VERSION__DIG_TYPE__SHIFT
97046. DIL
97047. DILB
97048. DILS
97049. DIM
97050. DIM2_MASK
97051. DIM2_OS62420_H
97052. DIM2_SYSFS_H
97053. DIMBR_mskDIMB
97054. DIMBR_offDIMB
97055. DIMD
97056. DIMM0_COR_ERR
97057. DIMM1_COR_ERR
97058. DIMM2_COR_ERR
97059. DIMMS_PER_CHANNEL
97060. DIMMS_PRESENT
97061. DIMM_BOT_COR_ERR
97062. DIMM_IOCTL
97063. DIMM_LABEL_SZ
97064. DIMM_MASK
97065. DIMM_PRESENT
97066. DIMM_PRESENT_MASK
97067. DIMM_SIZE
97068. DIMM_TOP_COR_ERR
97069. DIM_APPLY_NEW_PROFILE
97070. DIM_CQ_PERIOD_MODE_START_FROM_CQE
97071. DIM_CQ_PERIOD_MODE_START_FROM_EQE
97072. DIM_CQ_PERIOD_NUM_MODES
97073. DIM_EN
97074. DIM_ERR_BAD_BUFFER_SIZE
97075. DIM_ERR_BAD_CONFIG
97076. DIM_ERR_DRIVER_NOT_INITIALIZED
97077. DIM_ERR_OVERFLOW
97078. DIM_ERR_UNDERFLOW
97079. DIM_GOING_LEFT
97080. DIM_GOING_RIGHT
97081. DIM_H
97082. DIM_INIT_ERR_CHANNEL_ADDRESS
97083. DIM_INIT_ERR_DIM_ADDR
97084. DIM_INIT_ERR_MLB_CLOCK
97085. DIM_INIT_ERR_OUT_OF_MEMORY
97086. DIM_MEASURE_IN_PROGRESS
97087. DIM_NEVENTS
97088. DIM_NO_ERROR
97089. DIM_ON_EDGE
97090. DIM_PARKING_ON_TOP
97091. DIM_PARKING_TIRED
97092. DIM_START_MEASURE
97093. DIM_STATS_BETTER
97094. DIM_STATS_SAME
97095. DIM_STATS_WORSE
97096. DIM_STEPPED
97097. DIM_TOO_TIRED
97098. DIM_TYPE
97099. DIM_TYPE_1D
97100. DIM_TYPE_2D
97101. DIM_TYPE_3D
97102. DIM_TYPE_RESERVED
97103. DIN
97104. DINDEX
97105. DINDIR
97106. DINO_BRDG_FEAT
97107. DINO_BRIDGE_ALIGN
97108. DINO_CFG_TOK
97109. DINO_CMD_TX
97110. DINO_CMD_WEP_KEY
97111. DINO_CONFIG_DATA
97112. DINO_DAMODE
97113. DINO_DEBUG
97114. DINO_DEV
97115. DINO_ENABLE_CS
97116. DINO_ENABLE_SYSTEM
97117. DINO_FIX_UNASSIGNED_INTERRUPTS
97118. DINO_GMASK
97119. DINO_GSC2X_CONFIG
97120. DINO_IAR0
97121. DINO_IAR1
97122. DINO_ICR
97123. DINO_ILR
97124. DINO_IMR
97125. DINO_IODC_ADDR
97126. DINO_IODC_DATA_0
97127. DINO_IODC_DATA_1
97128. DINO_IO_ADDR_EN
97129. DINO_IO_COMMAND
97130. DINO_IO_CONTROL
97131. DINO_IO_DATA
97132. DINO_IO_ERR_INFO
97133. DINO_IO_FBB_EN
97134. DINO_IO_GSC_ERR_RESP
97135. DINO_IO_PCI_ERR_RESP
97136. DINO_IO_STATUS
97137. DINO_IPR
97138. DINO_IRQS
97139. DINO_IRR0
97140. DINO_IRR1
97141. DINO_IRR_MASK
97142. DINO_LOCAL_IRQS
97143. DINO_MASK_IRQ
97144. DINO_MAX_LMMIO_RESOURCES
97145. DINO_MEM_DATA
97146. DINO_MLTIM
97147. DINO_PAMR
97148. DINO_PAPR
97149. DINO_PCICMD
97150. DINO_PCIROR
97151. DINO_PCISTS
97152. DINO_PCIWOR
97153. DINO_PCI_ADDR
97154. DINO_PORT_IN
97155. DINO_PORT_OUT
97156. DINO_RXFIFO_DATA
97157. DINO_TLTIM
97158. DINO_TOC_ADDR
97159. DINT
97160. DINTCTRL
97161. DINTRCNT
97162. DINTRE
97163. DINTRE_CUR_OR_EN
97164. DINTRE_CUR_UR_EN
97165. DINTRE_HBLNK0_EN
97166. DINTRE_HBLNK1_EN
97167. DINTRE_STR1_OR_EN
97168. DINTRE_STR1_UR_EN
97169. DINTRE_STR2_OR_EN
97170. DINTRE_STR2_UR_EN
97171. DINTRE_VEVENT0_EN
97172. DINTRE_VEVENT1_EN
97173. DINTRS
97174. DINTRS_CUR_OR_S
97175. DINTRS_CUR_UR_S
97176. DINTRS_HBLNK0_S
97177. DINTRS_HBLNK1_S
97178. DINTRS_STR1_OR_S
97179. DINTRS_STR1_UR_S
97180. DINTRS_STR2_OR_S
97181. DINTRS_STR2_UR_S
97182. DINTRS_VEVENT0_S
97183. DINTRS_VEVENT1_S
97184. DINTSTS
97185. DINTSTSCLR
97186. DINT__MARK
97187. DIN_AES_AESMAC
97188. DIN_AES_DOUT
97189. DIN_DES_DOUT
97190. DIN_ERR_SHIFT
97191. DIN_HASH
97192. DIN_HASH_and_BYPASS
97193. DIN_INTR_SHIFT
97194. DIN_RC4_DOUT
97195. DIN_RDY_SHIFT
97196. DIN_SIZE_AVAIL_MASK
97197. DIN_SIZE_AVAIL_SHIFT
97198. DIN_SM4_DOUT
97199. DIO0
97200. DIO0_irq_handler
97201. DIO1
97202. DIO1_irq_handler
97203. DIO2
97204. DIO200_CLK_SCE
97205. DIO200_ENHANCE
97206. DIO200_GAT_SCE
97207. DIO200_INT_SCE
97208. DIO200_IO_SIZE
97209. DIO200_MAX_ISNS
97210. DIO200_MAX_SUBDEVS
97211. DIO200_PCIE_IO_SIZE
97212. DIO200_TS_CONFIG
97213. DIO200_TS_COUNT
97214. DIO200_VERSION
97215. DIO3
97216. DIO4
97217. DIO48E_EXTENT
97218. DIO48E_NGPIO
97219. DIO5
97220. DIOERR
97221. DIOFBNAME
97222. DIOII_BASE
97223. DIOII_DEVSIZE
97224. DIOII_END
97225. DIOII_SCBASE
97226. DIOII_SIZE
97227. DIOII_SIZEOFF
97228. DIOLAN_FLUSH_LEN
97229. DIOLAN_INBUF_LEN
97230. DIOLAN_OUTBUF_LEN
97231. DIOLAN_SYNC_TIMEOUT
97232. DIOLAN_USB_TIMEOUT
97233. DIOMAPPING2_CLK_OUT_DIV_16
97234. DIOMAPPING2_CLK_OUT_DIV_2
97235. DIOMAPPING2_CLK_OUT_DIV_32
97236. DIOMAPPING2_CLK_OUT_DIV_4
97237. DIOMAPPING2_CLK_OUT_DIV_8
97238. DIOMAPPING2_CLK_OUT_NO_DIV
97239. DIOMAPPING2_CLK_OUT_OFF
97240. DIOMAPPING2_CLK_OUT_RC
97241. DIOMEM_DISABLE_MEM_PWR_CTRL
97242. DIOMEM_DYNAMIC_DEEP_SLEEP_EN
97243. DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE
97244. DIOMEM_DYNAMIC_LIGHT_SLEEP_EN
97245. DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE
97246. DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE
97247. DIOMEM_ENABLE_MEM_PWR_CTRL
97248. DIOMEM_FORCE_DEEP_SLEEP_REQUEST
97249. DIOMEM_FORCE_LIGHT_SLEEP_REQ
97250. DIOMEM_FORCE_LIGHT_SLEEP_REQUEST
97251. DIOMEM_FORCE_SHUT_DOWN_REQUEST
97252. DIOMEM_NO_FORCE_REQ
97253. DIOMEM_NO_FORCE_REQUEST
97254. DIOMEM_PWR_DIS_CTRL
97255. DIOMEM_PWR_FORCE_CTRL
97256. DIOMEM_PWR_FORCE_CTRL2
97257. DIOMEM_PWR_SEL_CTRL
97258. DIOMEM_PWR_SEL_CTRL2
97259. DIONAME
97260. DIO_24_CNFG_REG
97261. DIO_24_PORTA_REG
97262. DIO_24_PORTB_REG
97263. DIO_24_PORTC_REG
97264. DIO_8255_OFFSET
97265. DIO_AUTOMODE
97266. DIO_BASE
97267. DIO_BASE_REG
97268. DIO_BASE__INST0_SEG0
97269. DIO_BASE__INST0_SEG1
97270. DIO_BASE__INST0_SEG2
97271. DIO_BASE__INST0_SEG3
97272. DIO_BASE__INST0_SEG4
97273. DIO_BASE__INST1_SEG0
97274. DIO_BASE__INST1_SEG1
97275. DIO_BASE__INST1_SEG2
97276. DIO_BASE__INST1_SEG3
97277. DIO_BASE__INST1_SEG4
97278. DIO_BASE__INST2_SEG0
97279. DIO_BASE__INST2_SEG1
97280. DIO_BASE__INST2_SEG2
97281. DIO_BASE__INST2_SEG3
97282. DIO_BASE__INST2_SEG4
97283. DIO_BASE__INST3_SEG0
97284. DIO_BASE__INST3_SEG1
97285. DIO_BASE__INST3_SEG2
97286. DIO_BASE__INST3_SEG3
97287. DIO_BASE__INST3_SEG4
97288. DIO_BASE__INST4_SEG0
97289. DIO_BASE__INST4_SEG1
97290. DIO_BASE__INST4_SEG2
97291. DIO_BASE__INST4_SEG3
97292. DIO_BASE__INST4_SEG4
97293. DIO_BASE__INST5_SEG0
97294. DIO_BASE__INST5_SEG1
97295. DIO_BASE__INST5_SEG2
97296. DIO_BASE__INST5_SEG3
97297. DIO_BASE__INST5_SEG4
97298. DIO_BASE__INST6_SEG0
97299. DIO_BASE__INST6_SEG1
97300. DIO_BASE__INST6_SEG2
97301. DIO_BASE__INST6_SEG3
97302. DIO_BASE__INST6_SEG4
97303. DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK
97304. DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT
97305. DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK
97306. DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT
97307. DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK
97308. DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT
97309. DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK
97310. DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT
97311. DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK
97312. DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT
97313. DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK
97314. DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT
97315. DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK
97316. DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT
97317. DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK
97318. DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT
97319. DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK
97320. DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT
97321. DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK
97322. DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT
97323. DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK
97324. DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT
97325. DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK
97326. DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT
97327. DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK
97328. DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT
97329. DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK
97330. DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT
97331. DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK
97332. DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT
97333. DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK
97334. DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT
97335. DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK
97336. DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT
97337. DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK
97338. DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT
97339. DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK
97340. DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT
97341. DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK
97342. DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT
97343. DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK
97344. DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT
97345. DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK
97346. DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT
97347. DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK
97348. DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT
97349. DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK
97350. DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT
97351. DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK
97352. DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT
97353. DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK
97354. DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT
97355. DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK
97356. DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT
97357. DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK
97358. DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT
97359. DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK
97360. DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT
97361. DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK
97362. DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT
97363. DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK
97364. DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT
97365. DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK
97366. DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT
97367. DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK
97368. DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT
97369. DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK
97370. DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT
97371. DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK
97372. DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT
97373. DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK
97374. DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT
97375. DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK
97376. DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT
97377. DIO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK
97378. DIO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT
97379. DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK
97380. DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT
97381. DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK
97382. DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT
97383. DIO_CLK_OUT
97384. DIO_COMPLETE_ASYNC
97385. DIO_COMPLETE_INVALIDATE
97386. DIO_CRC_OK
97387. DIO_DATA
97388. DIO_DATA_60XX_REG
97389. DIO_DCLK
97390. DIO_DESC2_DAVINCI
97391. DIO_DESC2_GATORBOX
97392. DIO_DESC2_HRCCATSEYE
97393. DIO_DESC2_HRMCATSEYE
97394. DIO_DESC2_HYPERION
97395. DIO_DESC2_LRCATSEYE
97396. DIO_DESC2_RENAISSANCE
97397. DIO_DESC2_TIGER
97398. DIO_DESC2_TOPCAT
97399. DIO_DESC2_XGENESIS
97400. DIO_DESC2_XXXCATSEYE
97401. DIO_DESC2_YGENESIS
97402. DIO_DESC_DCA0
97403. DIO_DESC_DCA0REM
97404. DIO_DESC_DCA1
97405. DIO_DESC_DCA1REM
97406. DIO_DESC_DCL
97407. DIO_DESC_DCLREM
97408. DIO_DESC_DCM
97409. DIO_DESC_DCMREM
97410. DIO_DESC_FBUFFER
97411. DIO_DESC_FHPIB
97412. DIO_DESC_LAN
97413. DIO_DESC_MISC0
97414. DIO_DESC_MISC1
97415. DIO_DESC_MISC10
97416. DIO_DESC_MISC11
97417. DIO_DESC_MISC12
97418. DIO_DESC_MISC13
97419. DIO_DESC_MISC2
97420. DIO_DESC_MISC3
97421. DIO_DESC_MISC4
97422. DIO_DESC_MISC5
97423. DIO_DESC_MISC6
97424. DIO_DESC_MISC7
97425. DIO_DESC_MISC8
97426. DIO_DESC_MISC9
97427. DIO_DESC_NHPIB
97428. DIO_DESC_PARALLEL
97429. DIO_DESC_SCSI0
97430. DIO_DESC_SCSI1
97431. DIO_DESC_SCSI2
97432. DIO_DESC_SCSI3
97433. DIO_DESC_VME
97434. DIO_DEVSIZE
97435. DIO_DIRECTION_60XX_REG
97436. DIO_ENCODE_ID
97437. DIO_END
97438. DIO_FIFO_ERROR
97439. DIO_FIFO_ERROR_00
97440. DIO_FIFO_ERROR_01
97441. DIO_FIFO_ERROR_10
97442. DIO_FIFO_ERROR_11
97443. DIO_FIFO_FULL_DIO1
97444. DIO_FIFO_FULL_DIO3
97445. DIO_FIFO_LEVEL
97446. DIO_FIFO_NOT_EMPTY_DIO1
97447. DIO_FIFO_NOT_EMPTY_FIO2
97448. DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK
97449. DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT
97450. DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK
97451. DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT
97452. DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK
97453. DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT
97454. DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE
97455. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK
97456. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT
97457. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK
97458. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT
97459. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK
97460. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT
97461. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK
97462. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT
97463. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK
97464. DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT
97465. DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL
97466. DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE
97467. DIO_HWID
97468. DIO_ID
97469. DIO_ID2_DAVINCI
97470. DIO_ID2_GATORBOX
97471. DIO_ID2_HRCCATSEYE
97472. DIO_ID2_HRMCATSEYE
97473. DIO_ID2_HYPERION
97474. DIO_ID2_LRCATSEYE
97475. DIO_ID2_RENAISSANCE
97476. DIO_ID2_TIGER
97477. DIO_ID2_TOPCAT
97478. DIO_ID2_XGENESIS
97479. DIO_ID2_XXXCATSEYE
97480. DIO_ID2_YGENESIS
97481. DIO_IDOFF
97482. DIO_ID_DCA0
97483. DIO_ID_DCA0REM
97484. DIO_ID_DCA1
97485. DIO_ID_DCA1REM
97486. DIO_ID_DCL
97487. DIO_ID_DCLREM
97488. DIO_ID_DCM
97489. DIO_ID_DCMREM
97490. DIO_ID_FBUFFER
97491. DIO_ID_FHPIB
97492. DIO_ID_LAN
97493. DIO_ID_MISC0
97494. DIO_ID_MISC1
97495. DIO_ID_MISC10
97496. DIO_ID_MISC11
97497. DIO_ID_MISC12
97498. DIO_ID_MISC13
97499. DIO_ID_MISC2
97500. DIO_ID_MISC3
97501. DIO_ID_MISC4
97502. DIO_ID_MISC5
97503. DIO_ID_MISC6
97504. DIO_ID_MISC7
97505. DIO_ID_MISC8
97506. DIO_ID_MISC9
97507. DIO_ID_NHPIB
97508. DIO_ID_PARALLEL
97509. DIO_ID_SCSI0
97510. DIO_ID_SCSI1
97511. DIO_ID_SCSI2
97512. DIO_ID_SCSI3
97513. DIO_ID_VME
97514. DIO_INLINE_BIO_VECS
97515. DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
97516. DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
97517. DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
97518. DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
97519. DIO_IPL
97520. DIO_IPLOFF
97521. DIO_ISDIOII
97522. DIO_LOCKING
97523. DIO_MAX_BLOCKS
97524. DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS_MASK
97525. DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS__SHIFT
97526. DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE_MASK
97527. DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE__SHIFT
97528. DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS_MASK
97529. DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS__SHIFT
97530. DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE_MASK
97531. DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE__SHIFT
97532. DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS_MASK
97533. DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS__SHIFT
97534. DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE_MASK
97535. DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE__SHIFT
97536. DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS_MASK
97537. DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS__SHIFT
97538. DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE_MASK
97539. DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE__SHIFT
97540. DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS_MASK
97541. DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS__SHIFT
97542. DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE_MASK
97543. DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE__SHIFT
97544. DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS_MASK
97545. DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS__SHIFT
97546. DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE_MASK
97547. DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE__SHIFT
97548. DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK
97549. DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT
97550. DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK
97551. DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT
97552. DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK
97553. DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT
97554. DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK
97555. DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT
97556. DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK
97557. DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT
97558. DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK
97559. DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT
97560. DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK
97561. DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT
97562. DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK
97563. DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT
97564. DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_DIS_MASK
97565. DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_DIS__SHIFT
97566. DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_FORCE_MASK
97567. DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_FORCE__SHIFT
97568. DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_DIS_MASK
97569. DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_DIS__SHIFT
97570. DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_FORCE_MASK
97571. DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_FORCE__SHIFT
97572. DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_DIS_MASK
97573. DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_DIS__SHIFT
97574. DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_FORCE_MASK
97575. DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_FORCE__SHIFT
97576. DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_DIS_MASK
97577. DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_DIS__SHIFT
97578. DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_FORCE_MASK
97579. DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_FORCE__SHIFT
97580. DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_DIS_MASK
97581. DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_DIS__SHIFT
97582. DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_FORCE_MASK
97583. DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_FORCE__SHIFT
97584. DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_DIS_MASK
97585. DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_DIS__SHIFT
97586. DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_FORCE_MASK
97587. DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_FORCE__SHIFT
97588. DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK
97589. DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT
97590. DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK
97591. DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT
97592. DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK
97593. DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT
97594. DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK
97595. DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT
97596. DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK
97597. DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT
97598. DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK
97599. DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT
97600. DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK
97601. DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT
97602. DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK
97603. DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT
97604. DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK
97605. DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT
97606. DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK
97607. DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT
97608. DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK
97609. DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT
97610. DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK
97611. DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT
97612. DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK
97613. DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT
97614. DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK
97615. DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT
97616. DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK
97617. DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT
97618. DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK
97619. DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT
97620. DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK
97621. DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT
97622. DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK
97623. DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT
97624. DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK
97625. DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT
97626. DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK
97627. DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT
97628. DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK
97629. DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT
97630. DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK
97631. DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT
97632. DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK
97633. DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT
97634. DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK
97635. DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT
97636. DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK
97637. DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT
97638. DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK
97639. DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT
97640. DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK
97641. DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT
97642. DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK
97643. DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT
97644. DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK
97645. DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT
97646. DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE_MASK
97647. DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE__SHIFT
97648. DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE_MASK
97649. DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE__SHIFT
97650. DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE_MASK
97651. DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE__SHIFT
97652. DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE_MASK
97653. DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE__SHIFT
97654. DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE_MASK
97655. DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE__SHIFT
97656. DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE_MASK
97657. DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE__SHIFT
97658. DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK
97659. DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT
97660. DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK
97661. DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT
97662. DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK
97663. DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT
97664. DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK
97665. DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT
97666. DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK
97667. DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT
97668. DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK
97669. DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT
97670. DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK
97671. DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT
97672. DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK
97673. DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT
97674. DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK
97675. DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT
97676. DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK
97677. DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT
97678. DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK
97679. DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT
97680. DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK
97681. DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT
97682. DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK
97683. DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT
97684. DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK
97685. DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT
97686. DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK
97687. DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT
97688. DIO_METADATA
97689. DIO_MODE_READY_DIO4
97690. DIO_MODE_READY_DIO5
97691. DIO_NEEDSSECID
97692. DIO_OTG_EXT_VSYNC_CNTL__DIO_GENERICB_EXT_VSYNC_MASK_MASK
97693. DIO_OTG_EXT_VSYNC_CNTL__DIO_GENERICB_EXT_VSYNC_MASK__SHIFT
97694. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG0_EXT_VSYNC_MUX_MASK
97695. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG0_EXT_VSYNC_MUX__SHIFT
97696. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG1_EXT_VSYNC_MUX_MASK
97697. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG1_EXT_VSYNC_MUX__SHIFT
97698. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG2_EXT_VSYNC_MUX_MASK
97699. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG2_EXT_VSYNC_MUX__SHIFT
97700. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG3_EXT_VSYNC_MUX_MASK
97701. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG3_EXT_VSYNC_MUX__SHIFT
97702. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG4_EXT_VSYNC_MUX_MASK
97703. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG4_EXT_VSYNC_MUX__SHIFT
97704. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG5_EXT_VSYNC_MUX_MASK
97705. DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG5_EXT_VSYNC_MUX__SHIFT
97706. DIO_OTG_EXT_VSYNC_CNTL__DIO_SWAPLOCKB_EXT_VSYNC_MASK_MASK
97707. DIO_OTG_EXT_VSYNC_CNTL__DIO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT
97708. DIO_PACKET_SENT
97709. DIO_PAGES
97710. DIO_PAYLOAD_READY
97711. DIO_PLL_LOCK
97712. DIO_PORT0_DATA_OFFSET
97713. DIO_PORT0_DIR_OFFSET
97714. DIO_PORT1_DATA_OFFSET
97715. DIO_PORT1_DIR_OFFSET
97716. DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK
97717. DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT
97718. DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK
97719. DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT
97720. DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK
97721. DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT
97722. DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK
97723. DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT
97724. DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK
97725. DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT
97726. DIO_R
97727. DIO_RSSI_DIO0
97728. DIO_RSSI_DIO3_4
97729. DIO_RX_READY
97730. DIO_SCINHOLE
97731. DIO_SCMAX
97732. DIO_SCRATCH0__DIO_SCRATCH0_MASK
97733. DIO_SCRATCH0__DIO_SCRATCH0__SHIFT
97734. DIO_SCRATCH1__DIO_SCRATCH1_MASK
97735. DIO_SCRATCH1__DIO_SCRATCH1__SHIFT
97736. DIO_SCRATCH2__DIO_SCRATCH2_MASK
97737. DIO_SCRATCH2__DIO_SCRATCH2__SHIFT
97738. DIO_SCRATCH3__DIO_SCRATCH3_MASK
97739. DIO_SCRATCH3__DIO_SCRATCH3__SHIFT
97740. DIO_SCRATCH4__DIO_SCRATCH4_MASK
97741. DIO_SCRATCH4__DIO_SCRATCH4__SHIFT
97742. DIO_SCRATCH5__DIO_SCRATCH5_MASK
97743. DIO_SCRATCH5__DIO_SCRATCH5__SHIFT
97744. DIO_SCRATCH6__DIO_SCRATCH6_MASK
97745. DIO_SCRATCH6__DIO_SCRATCH6__SHIFT
97746. DIO_SCRATCH7__DIO_SCRATCH7_MASK
97747. DIO_SCRATCH7__DIO_SCRATCH7__SHIFT
97748. DIO_SECID
97749. DIO_SECIDOFF
97750. DIO_SIZE
97751. DIO_SKIP_HOLES
97752. DIO_SOFT_RESET__DACA_SOFT_RESET_MASK
97753. DIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT
97754. DIO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK
97755. DIO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT
97756. DIO_SOFT_RESET__DVO_SOFT_RESET_MASK
97757. DIO_SOFT_RESET__DVO_SOFT_RESET__SHIFT
97758. DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK
97759. DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT
97760. DIO_SOFT_RESET__I2S1_SOFT_RESET_MASK
97761. DIO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT
97762. DIO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK
97763. DIO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT
97764. DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK
97765. DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT
97766. DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK
97767. DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT
97768. DIO_SYNC_ADDRESS
97769. DIO_TIMEOUT_DIO1
97770. DIO_TIMEOUT_DIO4
97771. DIO_TX_READY
97772. DIO_VIRADDRBASE
97773. DIO_W
97774. DIO_WAIT
97775. DIO_WILDCARD
97776. DIP
97777. DIPC
97778. DIPRINTK
97779. DIPSW
97780. DIPSWMR_OFS
97781. DIP_4S
97782. DIP_8S
97783. DIP_E1
97784. DIP_FLAGS_ACR
97785. DIP_FLAGS_GC
97786. DIP_FREQ
97787. DIP_IF_FLAGS_IF1
97788. DIP_IF_FLAGS_IF2
97789. DIP_IF_FLAGS_IF3
97790. DIP_IF_FLAGS_IF4
97791. DIP_IF_FLAGS_IF5
97792. DIP_PORT_SEL_MASK
97793. DIP_SWITCHES_VADDR
97794. DIR
97795. DIRA
97796. DIRB
97797. DIRCMD_FIFO_DEPTH
97798. DIRCNTL_MSC
97799. DIRCNTL_MSDA
97800. DIRCNTL_SCC
97801. DIRCNTL_SDAC
97802. DIRCOUNT
97803. DIRCTNL_FREE
97804. DIRECT
97805. DIRECT64_PROPNAME
97806. DIRECTCTRL10
97807. DIRECTCTRL19
97808. DIRECTED
97809. DIRECTION
97810. DIRECTIONAL_MSK
97811. DIRECTION_MARK
97812. DIRECTION_OF_TRANSFER
97813. DIRECTION_REG_OFFSET
97814. DIRECTIVE_ABSENT
97815. DIRECTIVE_ALL
97816. DIRECTIVE_ANY
97817. DIRECTIVE_APPLICATION
97818. DIRECTIVE_AUTOMATIC
97819. DIRECTIVE_BEGIN
97820. DIRECTIVE_BIT
97821. DIRECTIVE_BMPString
97822. DIRECTIVE_BOOLEAN
97823. DIRECTIVE_BY
97824. DIRECTIVE_CHARACTER
97825. DIRECTIVE_CHOICE
97826. DIRECTIVE_CLASS
97827. DIRECTIVE_COMPONENT
97828. DIRECTIVE_COMPONENTS
97829. DIRECTIVE_CONSTRAINED
97830. DIRECTIVE_CONTAINING
97831. DIRECTIVE_DEFAULT
97832. DIRECTIVE_DEFINED
97833. DIRECTIVE_DEFINITIONS
97834. DIRECTIVE_EMBEDDED
97835. DIRECTIVE_ENCODED
97836. DIRECTIVE_ENCODING_CONTROL
97837. DIRECTIVE_END
97838. DIRECTIVE_ENUMERATED
97839. DIRECTIVE_EXCEPT
97840. DIRECTIVE_EXPLICIT
97841. DIRECTIVE_EXPORTS
97842. DIRECTIVE_EXTENSIBILITY
97843. DIRECTIVE_EXTERNAL
97844. DIRECTIVE_FALSE
97845. DIRECTIVE_FROM
97846. DIRECTIVE_GeneralString
97847. DIRECTIVE_GeneralizedTime
97848. DIRECTIVE_GraphicString
97849. DIRECTIVE_IA5String
97850. DIRECTIVE_IDENTIFIER
97851. DIRECTIVE_IMPLICIT
97852. DIRECTIVE_IMPLIED
97853. DIRECTIVE_IMPORTS
97854. DIRECTIVE_INCLUDES
97855. DIRECTIVE_INSTANCE
97856. DIRECTIVE_INSTRUCTIONS
97857. DIRECTIVE_INTEGER
97858. DIRECTIVE_INTERSECTION
97859. DIRECTIVE_ISO646String
97860. DIRECTIVE_MAX
97861. DIRECTIVE_MIN
97862. DIRECTIVE_MINUS_INFINITY
97863. DIRECTIVE_NULL
97864. DIRECTIVE_NumericString
97865. DIRECTIVE_OBJECT
97866. DIRECTIVE_OCTET
97867. DIRECTIVE_OF
97868. DIRECTIVE_OPTIONAL
97869. DIRECTIVE_ObjectDescriptor
97870. DIRECTIVE_PATTERN
97871. DIRECTIVE_PDV
97872. DIRECTIVE_PLUS_INFINITY
97873. DIRECTIVE_PRESENT
97874. DIRECTIVE_PRIVATE
97875. DIRECTIVE_PrintableString
97876. DIRECTIVE_REAL
97877. DIRECTIVE_RELATIVE_OID
97878. DIRECTIVE_SEQUENCE
97879. DIRECTIVE_SET
97880. DIRECTIVE_SIZE
97881. DIRECTIVE_STRING
97882. DIRECTIVE_SYNTAX
97883. DIRECTIVE_T61String
97884. DIRECTIVE_TAGS
97885. DIRECTIVE_TRUE
97886. DIRECTIVE_TeletexString
97887. DIRECTIVE_UNION
97888. DIRECTIVE_UNIQUE
97889. DIRECTIVE_UNIVERSAL
97890. DIRECTIVE_UTCTime
97891. DIRECTIVE_UTF8String
97892. DIRECTIVE_UniversalString
97893. DIRECTIVE_VideotexString
97894. DIRECTIVE_VisibleString
97895. DIRECTIVE_WITH
97896. DIRECTORY_FOUND
97897. DIRECTORY_NOT_FOUND
97898. DIRECTORY_SIZE
97899. DIRECT_3DYCS_CONNECT_MASK
97900. DIRECT_ABORT
97901. DIRECT_ACCESS_DEVICE
97902. DIRECT_ARGUMENTS
97903. DIRECT_CMD_FIFO_RST
97904. DIRECT_CMD_MAIN_SETTINGS
97905. DIRECT_CMD_RDDATA
97906. DIRECT_CMD_RD_PROPS
97907. DIRECT_CMD_RD_STS
97908. DIRECT_CMD_RD_STS_CLR
97909. DIRECT_CMD_RD_STS_CTL
97910. DIRECT_CMD_RD_STS_FLAG
97911. DIRECT_CMD_SEND
97912. DIRECT_CMD_STOP_READ
97913. DIRECT_CMD_STS
97914. DIRECT_CMD_STS_CLR
97915. DIRECT_CMD_STS_CTL
97916. DIRECT_CMD_STS_FLAG
97917. DIRECT_CMD_WRDATA
97918. DIRECT_COMPANDING_MASK
97919. DIRECT_CONN
97920. DIRECT_FETCH_THRESHOLD
97921. DIRECT_FRAGMENT
97922. DIRECT_IF_44MHZ
97923. DIRECT_IF_57MHZ
97924. DIRECT_IF_REVB_BASE
97925. DIRECT_IO
97926. DIRECT_IP_DEVICE
97927. DIRECT_LOOKUP_MASK
97928. DIRECT_LOOKUP_SHIFT
97929. DIRECT_MODE
97930. DIRECT_REG_RD
97931. DIRECT_REG_WR
97932. DIRECT_REG_WR64
97933. DIRECT_ROUTING
97934. DIRECT_SPEED_CHANGE
97935. DIREND
97936. DIRENT
97937. DIRENTRY_UNIQUENESS
97938. DIRENTRY_VI_FIRST_DIRENTRY_ITEM
97939. DIRENT_HTREE
97940. DIRENT_SIZE
97941. DIRPD
97942. DIRQ
97943. DIRREAD
97944. DIRSIZ
97945. DIRTY
97946. DIRTYBIT
97947. DIRTYPE_PREMIUM
97948. DIRTYPE_STANDARD
97949. DIRTY_CMAP
97950. DIRTY_CNODE
97951. DIRTY_COLD_DATA
97952. DIRTY_COLD_NODE
97953. DIRTY_DENTS
97954. DIRTY_FULL_SCOPE
97955. DIRTY_HOT_DATA
97956. DIRTY_HOT_NODE
97957. DIRTY_I
97958. DIRTY_MEM_BITS
97959. DIRTY_META
97960. DIRTY_POLL_THRESH
97961. DIRTY_SCOPE
97962. DIRTY_TID_CTL
97963. DIRTY_TID_CTL_DTIDCLR
97964. DIRTY_TID_CTL_DTIDENAB
97965. DIRTY_TID_CTL_NPTHRED
97966. DIRTY_TID_CTL_RDTHRED
97967. DIRTY_TID_STAT
97968. DIRTY_TID_STAT_NPWSTAT
97969. DIRTY_TID_STAT_RDSTAT
97970. DIRTY_WARM_DATA
97971. DIRTY_WARM_NODE
97972. DIRTY_ZNODE
97973. DIRWRITE
97974. DIR_BIT
97975. DIR_BI_DIR
97976. DIR_BOF
97977. DIR_BOFE
97978. DIR_COA
97979. DIR_COAE
97980. DIR_COF
97981. DIR_COFE
97982. DIR_CORR
97983. DIR_DIRECT
97984. DIR_DOWN
97985. DIR_EOM
97986. DIR_EOME
97987. DIR_EOT
97988. DIR_EOTE
97989. DIR_ERROR_VALID_AE
97990. DIR_ERROR_VALID_CE
97991. DIR_ERROR_VALID_MASK
97992. DIR_ERROR_VALID_SHFT
97993. DIR_ERROR_VALID_UCE
97994. DIR_ERR_HSPEC_MASK
97995. DIR_ID_1
97996. DIR_IN
97997. DIR_INBOUND
97998. DIR_INDEX_FREE
97999. DIR_INDEX_VALID
98000. DIR_INODE
98001. DIR_MASK
98002. DIR_MODE
98003. DIR_NO_DATA
98004. DIR_OFFSET
98005. DIR_OP
98006. DIR_OUT
98007. DIR_OUTBOUND
98008. DIR_OUTPUT
98009. DIR_PORT
98010. DIR_RD
98011. DIR_READ
98012. DIR_REF
98013. DIR_REFE
98014. DIR_RESERVED
98015. DIR_RX
98016. DIR_SHIFT
98017. DIR_STRING
98018. DIR_TO_DEVICE
98019. DIR_TO_INI
98020. DIR_TX
98021. DIR_UDRF
98022. DIR_UDRFE
98023. DIR_UP
98024. DIR_WRITE
98025. DIS
98026. DISA
98027. DISABLE
98028. DISABLED
98029. DISABLED_BLOCK0
98030. DISABLED_BLOCK1
98031. DISABLED_BLOCK2
98032. DISABLED_BLOCK3
98033. DISABLED_MASK0
98034. DISABLED_MASK1
98035. DISABLED_MASK10
98036. DISABLED_MASK11
98037. DISABLED_MASK12
98038. DISABLED_MASK13
98039. DISABLED_MASK14
98040. DISABLED_MASK15
98041. DISABLED_MASK16
98042. DISABLED_MASK17
98043. DISABLED_MASK18
98044. DISABLED_MASK2
98045. DISABLED_MASK3
98046. DISABLED_MASK4
98047. DISABLED_MASK5
98048. DISABLED_MASK6
98049. DISABLED_MASK7
98050. DISABLED_MASK8
98051. DISABLED_MASK9
98052. DISABLED_MASK_BIT_SET
98053. DISABLED_MASK_CHECK
98054. DISABLED_PERIOD
98055. DISABLEIRQS
98056. DISABLERX
98057. DISABLES_SDMA
98058. DISABLEVLAN_F
98059. DISABLEVLAN_S
98060. DISABLEVLAN_V
98061. DISABLE_11D
98062. DISABLE_ACB_TOV
98063. DISABLE_ALL_INTERRUPTS
98064. DISABLE_ALL_INTRS
98065. DISABLE_ASL_3G
98066. DISABLE_ASL_BLUETOOTH
98067. DISABLE_ASL_CAMERA
98068. DISABLE_ASL_CARDREADER
98069. DISABLE_ASL_DISPLAYSWITCH
98070. DISABLE_ASL_GPS
98071. DISABLE_ASL_HWCF
98072. DISABLE_ASL_IRDA
98073. DISABLE_ASL_MODEM
98074. DISABLE_ASL_TV
98075. DISABLE_ASL_WIMAX
98076. DISABLE_ASL_WLAN
98077. DISABLE_AUTO
98078. DISABLE_AUTO_INFO_FIFO
98079. DISABLE_AUTO_NEG_FOR_DUPLEX
98080. DISABLE_AUTO_NEG_FOR_FLOW_CTRL
98081. DISABLE_AUTO_NEG_SPEED_GMII
98082. DISABLE_BB_RF
98083. DISABLE_BINNING_USE_LEGACY_SC
98084. DISABLE_BINNING_USE_NEW_SC
98085. DISABLE_BITSTUFF_AND_NRZI_ENCODE
98086. DISABLE_BL
98087. DISABLE_BRANCH_PROFILING
98088. DISABLE_CE
98089. DISABLE_CENTAUR_MCR
98090. DISABLE_CLOCK_GATING
98091. DISABLE_CLOCK_GATING_IN_DCO
98092. DISABLE_COAL
98093. DISABLE_CONVERSION_INT
98094. DISABLE_CP_PG
98095. DISABLE_CUBE_ANISO
98096. DISABLE_CUBE_WRAP
98097. DISABLE_CYRIX_ARR
98098. DISABLE_DDR_CONFSPACE
98099. DISABLE_DLL_PWRDOWN
98100. DISABLE_EARLY_EOT
98101. DISABLE_ECC_ON_ME_PIPE
98102. DISABLE_ECHO
98103. DISABLE_END_OF_FRAME
98104. DISABLE_EVENT_STR
98105. DISABLE_F
98106. DISABLE_FCP_RING_INT
98107. DISABLE_FIFO
98108. DISABLE_FOR_THIS_AC
98109. DISABLE_GDS_PG
98110. DISABLE_HIST_STR
98111. DISABLE_HP_AUTO_MDIX_MASK
98112. DISABLE_INT
98113. DISABLE_INTERP_1
98114. DISABLE_INTERRUPT
98115. DISABLE_INTERRUPTS
98116. DISABLE_INTERRUPT_MASK
98117. DISABLE_INTRS
98118. DISABLE_INTR_BYTE
98119. DISABLE_IN_SUSPEND
98120. DISABLE_IRQs
98121. DISABLE_JITTER_REMOVAL
98122. DISABLE_K6_MTRR
98123. DISABLE_KBD
98124. DISABLE_KEY
98125. DISABLE_LA57
98126. DISABLE_LAN_EN
98127. DISABLE_LEGACY
98128. DISABLE_LOOP_BACK
98129. DISABLE_MAC_SPOOFCHK
98130. DISABLE_MC_CFGPROGRAMMING
98131. DISABLE_MC_LOADMICROCODE
98132. DISABLE_MEM_PWR_CTRL
98133. DISABLE_MOUSE
98134. DISABLE_MPX
98135. DISABLE_MSI_FLAG
98136. DISABLE_MS_CD
98137. DISABLE_NEC
98138. DISABLE_NUMA_STAT
98139. DISABLE_OSPKE
98140. DISABLE_PAIR_SWAP_CORR_MASK
98141. DISABLE_PA_SC_GUIDANCE
98142. DISABLE_PCID
98143. DISABLE_PCLK_RESET
98144. DISABLE_PHY
98145. DISABLE_PHY_IF_OOB_FAILS
98146. DISABLE_PI
98147. DISABLE_PIXEL_MASK_CAMMING
98148. DISABLE_PKU
98149. DISABLE_POLARITY_CORR_MASK
98150. DISABLE_PROCESS_QUEUES
98151. DISABLE_PTI
98152. DISABLE_REFRESH
98153. DISABLE_REGISTER_PAIR
98154. DISABLE_S
98155. DISABLE_SDIO_FUNC
98156. DISABLE_SD_CD
98157. DISABLE_SEAGATE
98158. DISABLE_SEL
98159. DISABLE_SELF_GUID_CHECK
98160. DISABLE_SIGNAL_DETECT_FLT
98161. DISABLE_SLOT
98162. DISABLE_SMAP
98163. DISABLE_SSID_FLAG
98164. DISABLE_STATISTIC_COUNTER_ID_VALUE
98165. DISABLE_STATUS_AFTER_WRITE
98166. DISABLE_TEXTURE
98167. DISABLE_TF0
98168. DISABLE_TF1
98169. DISABLE_THE_CLOCK
98170. DISABLE_THE_FEATURE
98171. DISABLE_THE_INTERRUPT
98172. DISABLE_TILE_COVERED_FOR_PS_ITER
98173. DISABLE_TIME
98174. DISABLE_TRXPKT_BUF_ACCESS
98175. DISABLE_TX
98176. DISABLE_TX_CRS
98177. DISABLE_UDF_IEX_TRAP
98178. DISABLE_UMIP
98179. DISABLE_UNCONDITIONAL
98180. DISABLE_V
98181. DISABLE_VAL
98182. DISABLE_VCS
98183. DISABLE_VHT_MCS_SET
98184. DISABLE_VIDEO_BTA
98185. DISABLE_VIDEO_RESYNC
98186. DISABLE_VME
98187. DISABLE_VPP
98188. DISABLE_W83877F
98189. DISABLE_XD_CD
98190. DISAIP
98191. DISALLOW_BEACONS
98192. DISALLOW_BROADCAST_DATA
98193. DISASSOCIATION_BSSID
98194. DISASSOC_TYPE
98195. DISC
98196. DISCARD
98197. DISCARDS
98198. DISCARD_CHAR
98199. DISCARD_COMPLETED_NOTSUPP
98200. DISCARD_COMPLETED_WITH_ERROR
98201. DISCARD_DONE
98202. DISCARD_IN_FLIGHT
98203. DISCARD_MY_DATA
98204. DISCARD_PACKET
98205. DISCARD_READY
98206. DISCARD_TIME
98207. DISCARD_UNUSED_VPI_VCI_BITS_SET
98208. DISCE_DISCOVER_DOMAIN
98209. DISCE_RESUME
98210. DISCE_REVALIDATE_DOMAIN
98211. DISCE_SUSPEND
98212. DISCHARGE_THRESHOLD
98213. DISCONN
98214. DISCONNECT
98215. DISCONNECTED
98216. DISCONNECTED_SC
98217. DISCONNECTING
98218. DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS
98219. DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD
98220. DISCONNECT_CMD
98221. DISCONNECT_DEAUTH
98222. DISCONNECT_DISASSOC
98223. DISCONNECT_EVENT_COMPLETE_ID
98224. DISCONNECT_IMMEDIATE
98225. DISCONNECT_SCHEDULED
98226. DISCONNECT_SENT
98227. DISCONNECT_ST
98228. DISCONNECT_START
98229. DISCONNECT_STATUS
98230. DISCONNECT_TID
98231. DISCONN_EVT_IN_RECONN
98232. DISCONN_INTR
98233. DISCONN_SEQ
98234. DISCONN_UPCALL
98235. DISCON_IND
98236. DISCON_THRESHOLD_260
98237. DISCON_THRESHOLD_270
98238. DISCON_THRESHOLD_280
98239. DISCON_THRESHOLD_290
98240. DISCON_TIMER_INTVAL
98241. DISCOVERED
98242. DISCOVERY
98243. DISCOVERY_FINDING
98244. DISCOVERY_MAX_FAIL
98245. DISCOVERY_RESOLVING
98246. DISCOVERY_STARTING
98247. DISCOVERY_STOPPED
98248. DISCOVERY_STOPPING
98249. DISCOVERY_TABLE_SIGNATURE
98250. DISCOVERY_TMR_SIZE
98251. DISCOVER_REQ_SIZE
98252. DISCOVER_RESP_SIZE
98253. DISCOV_BREDR_INQUIRY_LEN
98254. DISCOV_INTERLEAVED_INQUIRY_LEN
98255. DISCOV_INTERLEAVED_TIMEOUT
98256. DISCOV_LE_FAST_ADV_INT_MAX
98257. DISCOV_LE_FAST_ADV_INT_MIN
98258. DISCOV_LE_RESTART_DELAY
98259. DISCOV_LE_SCAN_INT
98260. DISCOV_LE_SCAN_WIN
98261. DISCOV_LE_TIMEOUT
98262. DISCOV_TYPE_BREDR
98263. DISCOV_TYPE_INTERLEAVED
98264. DISCOV_TYPE_LE
98265. DISCPRIV_OK
98266. DISCW
98267. DISC_ALLOW
98268. DISC_ENABLE_BIT
98269. DISC_EV_FAILED
98270. DISC_EV_NONE
98271. DISC_EV_SUCCESS
98272. DISC_NOT_ALLOW
98273. DISC_NUM_EVENTS
98274. DISC_PRIV
98275. DISDATAFB
98276. DISDPLL
98277. DISEQC2_CTRL1
98278. DISEQC2_CTRL2
98279. DISEQC2_FIFO
98280. DISEQC2_STAT
98281. DISEQC_INSTR
98282. DISEQC_MODE
98283. DISEQC_RATIO
98284. DISEQC_RESET
98285. DISFB
98286. DISFC
98287. DISGARTCPU
98288. DISGARTIO
98289. DISGR0_CX_COMABT_INT
98290. DISGR0_CX_COMEND_INT
98291. DISGR0_CX_COMFAIL_INT
98292. DISGR0_CX_IN_INT
98293. DISGR0_CX_OUT_INT
98294. DISGR0_CX_SETUP_INT
98295. DISGR1_IN_INT
98296. DISGR1_OUT_INT
98297. DISGR1_SPK_INT
98298. DISGR2_DMA_CMPLT
98299. DISGR2_DMA_ERROR
98300. DISGR2_ISO_SEQ_ABORT_INT
98301. DISGR2_ISO_SEQ_ERR_INT
98302. DISGR2_RESM_INT
98303. DISGR2_RX0BYTE_INT
98304. DISGR2_SUSP_INT
98305. DISGR2_TX0BYTE_INT
98306. DISGR2_USBRST_INT
98307. DISIZE
98308. DISKLABELMAGIC
98309. DISKS_ARRAY_ELEMS
98310. DISKWRITE
98311. DISK_ACTIVITY_LIGHT
98312. DISK_EVENT_EJECT_REQUEST
98313. DISK_EVENT_FLAG_POLL
98314. DISK_EVENT_FLAG_UEVENT
98315. DISK_EVENT_MEDIA_CHANGE
98316. DISK_IN
98317. DISK_LEAF_NODE_LEVEL
98318. DISK_MAX_PARTS
98319. DISK_NAME_LEN
98320. DISK_PITER_INCL_EMPTY
98321. DISK_PITER_INCL_EMPTY_PART0
98322. DISK_PITER_INCL_PART0
98323. DISK_PITER_REVERSE
98324. DISK_TYPE
98325. DISMOD_3STATE
98326. DISMOD_HIGH
98327. DISMOD_LOW
98328. DISMOD_MASK
98329. DISMOD_VAL
98330. DISP
98331. DISP0
98332. DISP1
98333. DISP1_GAP
98334. DISP1_GAP_MASK
98335. DISP1_GAP_MCHG
98336. DISP1_GAP_MCHG_MASK
98337. DISP2
98338. DISP2_GAP
98339. DISP2_GAP_MASK
98340. DISP2_GAP_MCHG
98341. DISP2_GAP_MCHG_MASK
98342. DISP3
98343. DISPARB
98344. DISPARB_AEND_MASK
98345. DISPARB_AEND_SHIFT
98346. DISPARB_BEND_MASK
98347. DISPARB_BEND_SHIFT
98348. DISPATCH0_FP_USE
98349. DISPATCH0_IC_MISPRED
98350. DISPATCH0_IC_MISS
98351. DISPATCH0_STOREBUF
98352. DISPATCH_LIST_SIZE
98353. DISPATCH_LOG_BYTES
98354. DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
98355. DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK
98356. DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT
98357. DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK
98358. DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT
98359. DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK
98360. DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT
98361. DISPCLK_CHG_FWD_CORR_DISABLE
98362. DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING
98363. DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING
98364. DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK
98365. DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT
98366. DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK
98367. DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT
98368. DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK
98369. DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT
98370. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK
98371. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT
98372. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK
98373. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT
98374. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK
98375. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT
98376. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK
98377. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT
98378. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK
98379. DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT
98380. DISPCLK_FREQ_RAMP_COMPLETED
98381. DISPCLK_FREQ_RAMP_DONE
98382. DISPCLK_FREQ_RAMP_IN_PROGRESS
98383. DISPC_ACCU0_OFFSET
98384. DISPC_ACCU1_OFFSET
98385. DISPC_ACCU2_0_OFFSET
98386. DISPC_ACCU2_1_OFFSET
98387. DISPC_ATTR2_OFFSET
98388. DISPC_ATTR_OFFSET
98389. DISPC_BA0_OFFSET
98390. DISPC_BA0_UV_OFFSET
98391. DISPC_BA1_OFFSET
98392. DISPC_BA1_UV_OFFSET
98393. DISPC_CAPABLE
98394. DISPC_COLOR_COMPONENT_RGB_Y
98395. DISPC_COLOR_COMPONENT_UV
98396. DISPC_CONFIG
98397. DISPC_CONFIG2
98398. DISPC_CONFIG3
98399. DISPC_CONTROL
98400. DISPC_CONTROL2
98401. DISPC_CONTROL3
98402. DISPC_CONV_COEF_OFFSET
98403. DISPC_CPR_COEF_B
98404. DISPC_CPR_COEF_G
98405. DISPC_CPR_COEF_R
98406. DISPC_DATA_CYCLE1
98407. DISPC_DATA_CYCLE2
98408. DISPC_DATA_CYCLE3
98409. DISPC_DEFAULT_COLOR
98410. DISPC_DIVISOR
98411. DISPC_DIVISORo
98412. DISPC_FIFO_SIZE_STATUS_OFFSET
98413. DISPC_FIFO_THRESH_OFFSET
98414. DISPC_FIR2_OFFSET
98415. DISPC_FIR_COEF_H2_OFFSET
98416. DISPC_FIR_COEF_HV2_OFFSET
98417. DISPC_FIR_COEF_HV_OFFSET
98418. DISPC_FIR_COEF_H_OFFSET
98419. DISPC_FIR_COEF_V2_OFFSET
98420. DISPC_FIR_COEF_V_OFFSET
98421. DISPC_FIR_OFFSET
98422. DISPC_GAMMA_TABLE0
98423. DISPC_GAMMA_TABLE1
98424. DISPC_GAMMA_TABLE2
98425. DISPC_GAMMA_TABLE3
98426. DISPC_GLOBAL_ALPHA
98427. DISPC_GLOBAL_BUFFER
98428. DISPC_GLOBAL_MFLAG_ATTRIBUTE
98429. DISPC_IRQENABLE
98430. DISPC_IRQSTATUS
98431. DISPC_IRQ_ACBIAS_COUNT_STAT
98432. DISPC_IRQ_ACBIAS_COUNT_STAT2
98433. DISPC_IRQ_ACBIAS_COUNT_STAT3
98434. DISPC_IRQ_EVSYNC_EVEN
98435. DISPC_IRQ_EVSYNC_ODD
98436. DISPC_IRQ_FRAMEDONE
98437. DISPC_IRQ_FRAMEDONE2
98438. DISPC_IRQ_FRAMEDONE3
98439. DISPC_IRQ_FRAMEDONETV
98440. DISPC_IRQ_FRAMEDONEWB
98441. DISPC_IRQ_GFX_END_WIN
98442. DISPC_IRQ_GFX_FIFO_UNDERFLOW
98443. DISPC_IRQ_MASK_ERROR
98444. DISPC_IRQ_OCP_ERR
98445. DISPC_IRQ_PAL_GAMMA_MASK
98446. DISPC_IRQ_PROG_LINE_NUM
98447. DISPC_IRQ_SYNC_LOST
98448. DISPC_IRQ_SYNC_LOST2
98449. DISPC_IRQ_SYNC_LOST3
98450. DISPC_IRQ_SYNC_LOST_DIGIT
98451. DISPC_IRQ_VID1_END_WIN
98452. DISPC_IRQ_VID1_FIFO_UNDERFLOW
98453. DISPC_IRQ_VID2_END_WIN
98454. DISPC_IRQ_VID2_FIFO_UNDERFLOW
98455. DISPC_IRQ_VID3_END_WIN
98456. DISPC_IRQ_VID3_FIFO_UNDERFLOW
98457. DISPC_IRQ_VSYNC
98458. DISPC_IRQ_VSYNC2
98459. DISPC_IRQ_VSYNC3
98460. DISPC_IRQ_WAKEUP
98461. DISPC_IRQ_WBBUFFEROVERFLOW
98462. DISPC_IRQ_WBUNCOMPLETEERROR
98463. DISPC_LINE_NUMBER
98464. DISPC_LINE_STATUS
98465. DISPC_MAX_CHANNEL_GAMMA
98466. DISPC_MAX_NR_FIFOS
98467. DISPC_MAX_NR_ISRS
98468. DISPC_MFLAG_THRESHOLD_OFFSET
98469. DISPC_MGR_FLD_CPR
98470. DISPC_MGR_FLD_ENABLE
98471. DISPC_MGR_FLD_FIFOHANDCHECK
98472. DISPC_MGR_FLD_GO
98473. DISPC_MGR_FLD_NUM
98474. DISPC_MGR_FLD_STALLMODE
98475. DISPC_MGR_FLD_STNTFT
98476. DISPC_MGR_FLD_TCKENABLE
98477. DISPC_MGR_FLD_TCKSELECTION
98478. DISPC_MGR_FLD_TFTDATALINES
98479. DISPC_MSTANDBY_CTRL
98480. DISPC_OVL_ACCU0
98481. DISPC_OVL_ACCU1
98482. DISPC_OVL_ACCU2_0
98483. DISPC_OVL_ACCU2_1
98484. DISPC_OVL_ATTRIBUTES
98485. DISPC_OVL_ATTRIBUTES2
98486. DISPC_OVL_BA0
98487. DISPC_OVL_BA0_UV
98488. DISPC_OVL_BA1
98489. DISPC_OVL_BA1_UV
98490. DISPC_OVL_BASE
98491. DISPC_OVL_CONV_COEF
98492. DISPC_OVL_FIFO_SIZE_STATUS
98493. DISPC_OVL_FIFO_THRESHOLD
98494. DISPC_OVL_FIR
98495. DISPC_OVL_FIR2
98496. DISPC_OVL_FIR_COEF_H
98497. DISPC_OVL_FIR_COEF_H2
98498. DISPC_OVL_FIR_COEF_HV
98499. DISPC_OVL_FIR_COEF_HV2
98500. DISPC_OVL_FIR_COEF_V
98501. DISPC_OVL_FIR_COEF_V2
98502. DISPC_OVL_MFLAG_THRESHOLD
98503. DISPC_OVL_PICTURE_SIZE
98504. DISPC_OVL_PIXEL_INC
98505. DISPC_OVL_POSITION
98506. DISPC_OVL_PRELOAD
98507. DISPC_OVL_ROW_INC
98508. DISPC_OVL_SIZE
98509. DISPC_OVL_TABLE_BA
98510. DISPC_OVL_WINDOW_SKIP
98511. DISPC_PIC_SIZE_OFFSET
98512. DISPC_PIX_INC_OFFSET
98513. DISPC_POL_FREQ
98514. DISPC_POS_OFFSET
98515. DISPC_PRELOAD_OFFSET
98516. DISPC_REG
98517. DISPC_REVISION
98518. DISPC_ROW_INC_OFFSET
98519. DISPC_SIZE_MGR
98520. DISPC_SIZE_OFFSET
98521. DISPC_SYSCONFIG
98522. DISPC_SYSSTATUS
98523. DISPC_SZ_REGS
98524. DISPC_TABLE_BA_OFFSET
98525. DISPC_TIMING_H
98526. DISPC_TIMING_V
98527. DISPC_TRANS_COLOR
98528. DISPC_WINDOW_SKIP_OFFSET
98529. DISPIO_CR_TX_BMU_CR0
98530. DISPLACE_NEW_PACKING_LOCALITIES
98531. DISPLAY
98532. DISPLAY0_ID
98533. DISPLAY0_TYPE
98534. DISPLAY1_ID
98535. DISPLAY1_TYPE
98536. DISPLAY2_ID
98537. DISPLAY2_TYPE
98538. DISPLAY3_ID
98539. DISPLAY3_TYPE
98540. DISPLAY4_ID
98541. DISPLAY4_TYPE
98542. DISPLAY5_ID
98543. DISPLAY5_TYPE
98544. DISPLAYID_EXT
98545. DISPLAYPHY_CORE_SELECT
98546. DISPLAYPHY_LANEMASK
98547. DISPLAYPHY_LANESELECT_SHIFT
98548. DISPLAYPHY_PHYID_SHIFT
98549. DISPLAYPHY_RX_SELECT
98550. DISPLAYPHY_TX_SELECT
98551. DISPLAY_15BPP_MODE
98552. DISPLAY_16BPP_MODE
98553. DISPLAY_24BPP_MODE
98554. DISPLAY_32BPP_MODE
98555. DISPLAY_8BPP_MODE
98556. DISPLAY_ATTR
98557. DISPLAY_BASE_ADDR
98558. DISPLAY_BRIGHTNESS_AUTO
98559. DISPLAY_CAPS__DP_PCLK_FROM_PPLL
98560. DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED
98561. DISPLAY_CNTL
98562. DISPLAY_COLOR_MODE
98563. DISPLAY_CONFIG_CONTAINER
98564. DISPLAY_CONFIG_PARTITION
98565. DISPLAY_CONTENT_TYPE_CINEMA
98566. DISPLAY_CONTENT_TYPE_GAME
98567. DISPLAY_CONTENT_TYPE_GRAPHICS
98568. DISPLAY_CONTENT_TYPE_NO_DATA
98569. DISPLAY_CONTENT_TYPE_PHOTO
98570. DISPLAY_CONTROL_750LE
98571. DISPLAY_CONTROL_REG
98572. DISPLAY_CTRL_1
98573. DISPLAY_CTRL_2
98574. DISPLAY_CTRL_3
98575. DISPLAY_CTRL_CLOCK_PHASE
98576. DISPLAY_CTRL_GAMMA
98577. DISPLAY_CTRL_HSYNC_PHASE
98578. DISPLAY_CTRL_PLANE
98579. DISPLAY_CTRL_TIMING
98580. DISPLAY_CTRL_VSYNC_PHASE
98581. DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
98582. DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
98583. DISPLAY_DIMMING_ON
98584. DISPLAY_DIR_NAME
98585. DISPLAY_DONGLE_DP_DVI_CONVERTER
98586. DISPLAY_DONGLE_DP_DVI_DONGLE
98587. DISPLAY_DONGLE_DP_HDMI_CONVERTER
98588. DISPLAY_DONGLE_DP_HDMI_DONGLE
98589. DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE
98590. DISPLAY_DONGLE_DP_VGA_CONVERTER
98591. DISPLAY_DONGLE_NONE
98592. DISPLAY_FLAGS_DE_HIGH
98593. DISPLAY_FLAGS_DE_LOW
98594. DISPLAY_FLAGS_DOUBLECLK
98595. DISPLAY_FLAGS_DOUBLESCAN
98596. DISPLAY_FLAGS_HSYNC_HIGH
98597. DISPLAY_FLAGS_HSYNC_LOW
98598. DISPLAY_FLAGS_INTERLACED
98599. DISPLAY_FLAGS_PIXDATA_NEGEDGE
98600. DISPLAY_FLAGS_PIXDATA_POSEDGE
98601. DISPLAY_FLAGS_SYNC_NEGEDGE
98602. DISPLAY_FLAGS_SYNC_POSEDGE
98603. DISPLAY_FLAGS_VSYNC_HIGH
98604. DISPLAY_FLAGS_VSYNC_LOW
98605. DISPLAY_GAMMA_DISABLE
98606. DISPLAY_GAMMA_ENABLE
98607. DISPLAY_GAP
98608. DISPLAY_GAP_IGNORE
98609. DISPLAY_GAP_VBLANK
98610. DISPLAY_GAP_VBLANK_OR_WM
98611. DISPLAY_GAP_WATERMARK
98612. DISPLAY_HITM
98613. DISPLAY_IPS_CONTROL
98614. DISPLAY_LCL
98615. DISPLAY_LINE_LIMIT
98616. DISPLAY_MAX
98617. DISPLAY_MICRO_TILING
98618. DISPLAY_MINOR_BASE
98619. DISPLAY_MMIO_BASE
98620. DISPLAY_MODE
98621. DISPLAY_MODEL_LASI
98622. DISPLAY_MODEL_LCD
98623. DISPLAY_MODEL_NONE
98624. DISPLAY_MODEL_OLD_ASP
98625. DISPLAY_OBJECT_TYPE_CONNECTOR
98626. DISPLAY_OBJECT_TYPE_ENCODER
98627. DISPLAY_OBJECT_TYPE_GPU
98628. DISPLAY_OBJECT_TYPE_NONE
98629. DISPLAY_ON
98630. DISPLAY_OUTPUT_DUAL_LVDS
98631. DISPLAY_OUTPUT_LVDS
98632. DISPLAY_OUTPUT_RGB
98633. DISPLAY_PHY_CONTROL
98634. DISPLAY_PHY_STATUS
98635. DISPLAY_PLANE_A
98636. DISPLAY_PLANE_B
98637. DISPLAY_PLANE_DISABLE
98638. DISPLAY_PLANE_ENABLE
98639. DISPLAY_PLANE_FLIP_PENDING
98640. DISPLAY_PORT_PLL_BIOS_0
98641. DISPLAY_PORT_PLL_BIOS_1
98642. DISPLAY_PORT_PLL_BIOS_2
98643. DISPLAY_PORT_RX
98644. DISPLAY_RATE_SELECT_FPA1
98645. DISPLAY_REG
98646. DISPLAY_RMT
98647. DISPLAY_STATS
98648. DISPLAY_STATS_BEGIN
98649. DISPLAY_STATS_END
98650. DISPLAY_STATUS
98651. DISPLAY_TOT
98652. DISPLAY_TYPE_CRT
98653. DISPLAY_TYPE_DP
98654. DISPLAY_TYPE_EXTERNAL_FLAT_PANEL
98655. DISPLAY_TYPE_HDMI
98656. DISPLAY_TYPE_INTERNAL_FLAT_PANEL
98657. DISPLAY_TYPE_NONE
98658. DISPLAY_TYPE_TV
98659. DISPLAY_VGA_MODE
98660. DISPLAY_WM
98661. DISPLAY_WM_MASK
98662. DISPLAY_WM_SHIFT
98663. DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK
98664. DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT
98665. DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK
98666. DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT
98667. DISPPLANE_15_16BPP
98668. DISPPLANE_16BPP
98669. DISPPLANE_32BPP
98670. DISPPLANE_32BPP_NO_ALPHA
98671. DISPPLANE_8BPP
98672. DISPPLANE_ALPHA_PREMULTIPLY
98673. DISPPLANE_ALPHA_TRANS_DISABLE
98674. DISPPLANE_ALPHA_TRANS_ENABLE
98675. DISPPLANE_BGRA555
98676. DISPPLANE_BGRA888
98677. DISPPLANE_BGRX101010
98678. DISPPLANE_BGRX555
98679. DISPPLANE_BGRX565
98680. DISPPLANE_BGRX888
98681. DISPPLANE_BOTTOM
98682. DISPPLANE_GAMMA_DISABLE
98683. DISPPLANE_GAMMA_ENABLE
98684. DISPPLANE_LINE_DOUBLE
98685. DISPPLANE_MIRROR
98686. DISPPLANE_NO_LINE_DOUBLE
98687. DISPPLANE_PIPE_CSC_ENABLE
98688. DISPPLANE_PIXFORMAT_MASK
98689. DISPPLANE_PLANE_DISABLE
98690. DISPPLANE_PLANE_ENABLE
98691. DISPPLANE_RGBA101010
98692. DISPPLANE_RGBA888
98693. DISPPLANE_RGBX101010
98694. DISPPLANE_RGBX161616
98695. DISPPLANE_RGBX888
98696. DISPPLANE_ROTATE_180
98697. DISPPLANE_SEL_PIPE
98698. DISPPLANE_SEL_PIPE_A
98699. DISPPLANE_SEL_PIPE_B
98700. DISPPLANE_SEL_PIPE_MASK
98701. DISPPLANE_SEL_PIPE_POS
98702. DISPPLANE_SEL_PIPE_SHIFT
98703. DISPPLANE_SPRITE_ABOVE_DISPLAY
98704. DISPPLANE_SPRITE_ABOVE_DISPLAYA
98705. DISPPLANE_SPRITE_ABOVE_OVERLAY
98706. DISPPLANE_SRC_KEY_DISABLE
98707. DISPPLANE_SRC_KEY_ENABLE
98708. DISPPLANE_STEREO_DISABLE
98709. DISPPLANE_STEREO_ENABLE
98710. DISPPLANE_STEREO_POLARITY_FIRST
98711. DISPPLANE_STEREO_POLARITY_SECOND
98712. DISPPLANE_TILED
98713. DISPPLANE_TRICKLE_FEED_DISABLE
98714. DISPPLANE_YUV422
98715. DISPPLL
98716. DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK
98717. DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT
98718. DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK
98719. DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT
98720. DISPPLL_CONFIG_COHERENT_MODE
98721. DISPPLL_CONFIG_DUAL_LINK
98722. DISPPLL_CONFIG_DVO_24BIT
98723. DISPPLL_CONFIG_DVO_DDR_SPEED
98724. DISPPLL_CONFIG_DVO_LOW12BIT
98725. DISPPLL_CONFIG_DVO_OUTPUT_SEL
98726. DISPPLL_CONFIG_DVO_RATE_SEL
98727. DISPPLL_CONFIG_DVO_SDR_SPEED
98728. DISPPLL_CONFIG_DVO_UPPER12BIT
98729. DISPPLL_CONFIG_SS_ENABLE
98730. DISP_4
98731. DISP_8
98732. DISP_AAL_EN
98733. DISP_AAL_SIZE
98734. DISP_AB_CNT
98735. DISP_ALIGNMENT_LSB
98736. DISP_ALIGNMENT_MSB
98737. DISP_ARB_CTL
98738. DISP_ARB_CTL2
98739. DISP_BASE
98740. DISP_BASEADDR_MASK
98741. DISP_BRDRCOLR
98742. DISP_BRDRHORZ
98743. DISP_BRDRVERT
98744. DISP_BRIDGE_PU_PD_CTRL_REG
98745. DISP_CC_MDSS_AHB_CLK
98746. DISP_CC_MDSS_AXI_CLK
98747. DISP_CC_MDSS_BYTE0_CLK
98748. DISP_CC_MDSS_BYTE0_CLK_SRC
98749. DISP_CC_MDSS_BYTE0_DIV_CLK_SRC
98750. DISP_CC_MDSS_BYTE0_INTF_CLK
98751. DISP_CC_MDSS_BYTE1_CLK
98752. DISP_CC_MDSS_BYTE1_CLK_SRC
98753. DISP_CC_MDSS_BYTE1_DIV_CLK_SRC
98754. DISP_CC_MDSS_BYTE1_INTF_CLK
98755. DISP_CC_MDSS_ESC0_CLK
98756. DISP_CC_MDSS_ESC0_CLK_SRC
98757. DISP_CC_MDSS_ESC1_CLK
98758. DISP_CC_MDSS_ESC1_CLK_SRC
98759. DISP_CC_MDSS_MDP_CLK
98760. DISP_CC_MDSS_MDP_CLK_SRC
98761. DISP_CC_MDSS_MDP_LUT_CLK
98762. DISP_CC_MDSS_PCLK0_CLK
98763. DISP_CC_MDSS_PCLK0_CLK_SRC
98764. DISP_CC_MDSS_PCLK1_CLK
98765. DISP_CC_MDSS_PCLK1_CLK_SRC
98766. DISP_CC_MDSS_ROT_CLK
98767. DISP_CC_MDSS_ROT_CLK_SRC
98768. DISP_CC_MDSS_RSCC_AHB_CLK
98769. DISP_CC_MDSS_RSCC_BCR
98770. DISP_CC_MDSS_RSCC_VSYNC_CLK
98771. DISP_CC_MDSS_VSYNC_CLK
98772. DISP_CC_MDSS_VSYNC_CLK_SRC
98773. DISP_CC_PLL0
98774. DISP_CD_CNT
98775. DISP_CHAR_RAM
98776. DISP_CLK_DP
98777. DISP_CLK_DPPHY
98778. DISP_CLK_DSIM1
98779. DISP_CLK_FIMD1
98780. DISP_CLK_HDMI
98781. DISP_CLK_HDMIPHY
98782. DISP_CLK_MIPIPHY
98783. DISP_CLK_MIXER
98784. DISP_CLK_PIXEL_DISP
98785. DISP_CLK_PIXEL_MIXER
98786. DISP_CLK_SMMU_FIMD1M0
98787. DISP_CLK_SMMU_FIMD1M1
98788. DISP_CLK_SMMU_TV
98789. DISP_CNT_CMD
98790. DISP_COLOR_CFG_MAIN
98791. DISP_COLOR_HEIGHT
98792. DISP_COLOR_START
98793. DISP_COLOR_START_MT2701
98794. DISP_COLOR_START_MT8173
98795. DISP_COLOR_WIDTH
98796. DISP_CRT
98797. DISP_CTL
98798. DISP_CTL_OFF
98799. DISP_CTRL
98800. DISP_CTRL_MODE_C_DISPLAY
98801. DISP_CTRL_MODE_MASK
98802. DISP_CTRL_MODE_NC_DISPLAY
98803. DISP_CTRL_MODE_STOP
98804. DISP_D1D2_GRPH_RST
98805. DISP_D1D2_OV0_RST
98806. DISP_D1D2_SUBPIC_RST
98807. DISP_D3_GRPH_RST
98808. DISP_D3_OV0_RST
98809. DISP_D3_SUBPIC_RST
98810. DISP_DATA_FORMAT_DF1P1C
98811. DISP_DATA_FORMAT_DF1P2C16B
98812. DISP_DATA_FORMAT_DF1P2C18B
98813. DISP_DATA_FORMAT_DF1P2C24B
98814. DISP_DATA_FORMAT_DF1P3C18B
98815. DISP_DATA_FORMAT_DF1P3C24B
98816. DISP_DATA_FORMAT_DF2S
98817. DISP_DATA_FORMAT_DF3S
98818. DISP_DATA_FORMAT_DFSPI
98819. DISP_DATA_PARTITION_5_6
98820. DISP_DFP
98821. DISP_DITHERING
98822. DISP_DITHER_15
98823. DISP_DITHER_16
98824. DISP_DITHER_5
98825. DISP_DITHER_7
98826. DISP_DIWADDRL
98827. DISP_DIWADDRS
98828. DISP_DIWCONF
98829. DISP_DIWHSTRT
98830. DISP_DIWMODE
98831. DISP_DIWSIZE
98832. DISP_DIWVSTRT
98833. DISP_DOUT_PCLK_DISP_111
98834. DISP_DOUT_SCLK_FIMD1_EXTCLKPLL
98835. DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI
98836. DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE_MASK
98837. DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE__SHIFT
98838. DISP_DVO_ENABLE_RST
98839. DISP_EF_CNT
98840. DISP_EOT_GEN
98841. DISP_FBC_MEMORY_WAKE
98842. DISP_FBC_WM_DIS
98843. DISP_FLIP_EVENT
98844. DISP_FREQ_MULTIPLIER
98845. DISP_GAMMA_CFG
98846. DISP_GAMMA_EN
98847. DISP_GAMMA_LUT
98848. DISP_GAMMA_SIZE
98849. DISP_GAP
98850. DISP_GAP_MASK
98851. DISP_GAP_MCHG
98852. DISP_GAP_MCHG_MASK
98853. DISP_GEN_CHECKSUM
98854. DISP_GEN_ECC
98855. DISP_GH_CNT
98856. DISP_HORIZ_COUNT
98857. DISP_HW_DEBUG
98858. DISP_IJ_CNT
98859. DISP_INTERRUPT_STATUS
98860. DISP_INTERRUPT_STATUS_CONTINUE
98861. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE_MASK
98862. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE__SHIFT
98863. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE_MASK
98864. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE__SHIFT
98865. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE_MASK
98866. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE__SHIFT
98867. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE_MASK
98868. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE__SHIFT
98869. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE_MASK
98870. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE__SHIFT
98871. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE_MASK
98872. DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE__SHIFT
98873. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK
98874. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT
98875. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK
98876. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT
98877. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK
98878. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT
98879. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK
98880. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT
98881. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK
98882. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT
98883. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK
98884. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT
98885. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK
98886. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT
98887. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK
98888. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT
98889. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT_MASK
98890. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT__SHIFT
98891. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT_MASK
98892. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT__SHIFT
98893. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT_MASK
98894. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT__SHIFT
98895. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT_MASK
98896. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT__SHIFT
98897. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT_MASK
98898. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT__SHIFT
98899. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT_MASK
98900. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT__SHIFT
98901. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT_MASK
98902. DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT__SHIFT
98903. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
98904. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
98905. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
98906. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
98907. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
98908. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
98909. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
98910. DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
98911. DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK
98912. DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT
98913. DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK
98914. DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT
98915. DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK
98916. DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT
98917. DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK
98918. DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT
98919. DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK
98920. DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT
98921. DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK
98922. DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT
98923. DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK
98924. DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT
98925. DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt_MASK
98926. DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt__SHIFT
98927. DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt_MASK
98928. DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt__SHIFT
98929. DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt_MASK
98930. DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt__SHIFT
98931. DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt_MASK
98932. DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt__SHIFT
98933. DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt_MASK
98934. DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt__SHIFT
98935. DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt_MASK
98936. DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt__SHIFT
98937. DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK
98938. DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT
98939. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK
98940. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT
98941. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK
98942. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT
98943. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK
98944. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT
98945. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK
98946. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT
98947. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK
98948. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT
98949. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK
98950. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT
98951. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK
98952. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT
98953. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK
98954. DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT
98955. DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK
98956. DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT
98957. DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK
98958. DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT
98959. DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK
98960. DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT
98961. DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK
98962. DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT
98963. DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK
98964. DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT
98965. DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK
98966. DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT
98967. DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK
98968. DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT
98969. DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK
98970. DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT
98971. DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK
98972. DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT
98973. DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK
98974. DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT
98975. DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK
98976. DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT
98977. DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK
98978. DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT
98979. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK
98980. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT
98981. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK
98982. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT
98983. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK
98984. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT
98985. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK
98986. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT
98987. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK
98988. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT
98989. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK
98990. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT
98991. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK
98992. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT
98993. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK
98994. DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT
98995. DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK
98996. DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT
98997. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK
98998. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT
98999. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK
99000. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT
99001. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK
99002. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT
99003. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK
99004. DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT
99005. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK
99006. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT
99007. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK
99008. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT
99009. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK
99010. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT
99011. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK
99012. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT
99013. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99014. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99015. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK
99016. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT
99017. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK
99018. DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT
99019. DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK
99020. DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT
99021. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK
99022. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT
99023. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK
99024. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT
99025. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK
99026. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT
99027. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK
99028. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT
99029. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99030. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99031. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK
99032. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT
99033. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK
99034. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT
99035. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK
99036. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT
99037. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK
99038. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT
99039. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK
99040. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT
99041. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK
99042. DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT
99043. DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK
99044. DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT
99045. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK
99046. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT
99047. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK
99048. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT
99049. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK
99050. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT
99051. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK
99052. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT
99053. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99054. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99055. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK
99056. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT
99057. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK
99058. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT
99059. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK
99060. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT
99061. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK
99062. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT
99063. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK
99064. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT
99065. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK
99066. DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT
99067. DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK
99068. DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT
99069. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK
99070. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT
99071. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK
99072. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT
99073. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK
99074. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT
99075. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK
99076. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT
99077. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99078. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99079. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK
99080. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT
99081. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK
99082. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT
99083. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK
99084. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT
99085. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK
99086. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT
99087. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99088. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99089. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK
99090. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT
99091. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK
99092. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT
99093. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK
99094. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT
99095. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK
99096. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT
99097. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99098. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99099. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK
99100. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT
99101. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK
99102. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT
99103. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK
99104. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT
99105. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK
99106. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT
99107. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99108. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99109. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK
99110. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT
99111. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK
99112. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT
99113. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK
99114. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT
99115. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK
99116. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT
99117. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK
99118. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT
99119. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK
99120. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT
99121. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK
99122. DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT
99123. DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK
99124. DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT
99125. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK
99126. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99127. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK
99128. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT
99129. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK
99130. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99131. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK
99132. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT
99133. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK
99134. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99135. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK
99136. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT
99137. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK
99138. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99139. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK
99140. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT
99141. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK
99142. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99143. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK
99144. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT
99145. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK
99146. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99147. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK
99148. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT
99149. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK
99150. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99151. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK
99152. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT
99153. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK
99154. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT
99155. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK
99156. DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT
99157. DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK
99158. DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT
99159. DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK
99160. DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT
99161. DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK
99162. DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT
99163. DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK
99164. DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT
99165. DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK
99166. DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT
99167. DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK
99168. DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT
99169. DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK
99170. DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT
99171. DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK
99172. DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT
99173. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK
99174. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT
99175. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK
99176. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT
99177. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK
99178. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT
99179. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK
99180. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT
99181. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK
99182. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT
99183. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK
99184. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT
99185. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK
99186. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT
99187. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK
99188. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT
99189. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT_MASK
99190. DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT__SHIFT
99191. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK
99192. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT
99193. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK
99194. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT
99195. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK
99196. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT
99197. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK
99198. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT
99199. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK
99200. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT
99201. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK
99202. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT
99203. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK
99204. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT
99205. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK
99206. DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT
99207. DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK
99208. DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT
99209. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK
99210. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT
99211. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK
99212. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT
99213. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK
99214. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT
99215. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK
99216. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT
99217. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK
99218. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT
99219. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK
99220. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT
99221. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK
99222. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT
99223. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK
99224. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT
99225. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK
99226. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT
99227. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK
99228. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT
99229. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK
99230. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT
99231. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK
99232. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT
99233. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK
99234. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT
99235. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK
99236. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT
99237. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK
99238. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT
99239. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK
99240. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT
99241. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK
99242. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT
99243. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK
99244. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT
99245. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK
99246. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT
99247. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK
99248. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT
99249. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK
99250. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT
99251. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK
99252. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT
99253. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK
99254. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT
99255. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK
99256. DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT
99257. DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99258. DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99259. DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99260. DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99261. DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK
99262. DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT
99263. DISP_INTERRUPT_STATUS_CONTINUE2
99264. DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK
99265. DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT
99266. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK
99267. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT
99268. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK
99269. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT
99270. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK
99271. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT
99272. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK
99273. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT
99274. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK
99275. DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT
99276. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK
99277. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT
99278. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK
99279. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT
99280. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK
99281. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT
99282. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK
99283. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT
99284. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK
99285. DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT
99286. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK
99287. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT
99288. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK
99289. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT
99290. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK
99291. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT
99292. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK
99293. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT
99294. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK
99295. DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT
99296. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK
99297. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT
99298. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK
99299. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT
99300. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK
99301. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT
99302. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK
99303. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT
99304. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK
99305. DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT
99306. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK
99307. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT
99308. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK
99309. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT
99310. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK
99311. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT
99312. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK
99313. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT
99314. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK
99315. DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT
99316. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK
99317. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT
99318. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK
99319. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT
99320. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK
99321. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT
99322. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK
99323. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT
99324. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK
99325. DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT
99326. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK
99327. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT
99328. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK
99329. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT
99330. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK
99331. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT
99332. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK
99333. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT
99334. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK
99335. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT
99336. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK
99337. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT
99338. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK
99339. DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT
99340. DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99341. DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99342. DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99343. DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99344. DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK
99345. DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT
99346. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK
99347. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT
99348. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK
99349. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT
99350. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK
99351. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT
99352. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK
99353. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT
99354. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK
99355. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT
99356. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK
99357. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT
99358. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK
99359. DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT
99360. DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK
99361. DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT
99362. DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK
99363. DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT
99364. DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK
99365. DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT
99366. DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK
99367. DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT
99368. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK
99369. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT
99370. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK
99371. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT
99372. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK
99373. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT
99374. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK
99375. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT
99376. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK
99377. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT
99378. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK
99379. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT
99380. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK
99381. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT
99382. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK
99383. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT
99384. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK
99385. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT
99386. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK
99387. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT
99388. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK
99389. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT
99390. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK
99391. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT
99392. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK
99393. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT
99394. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK
99395. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT
99396. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK
99397. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT
99398. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK
99399. DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT
99400. DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK
99401. DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT
99402. DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK
99403. DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT
99404. DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK
99405. DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT
99406. DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK
99407. DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT
99408. DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK
99409. DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT
99410. DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK
99411. DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT
99412. DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK
99413. DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT
99414. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK
99415. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT
99416. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK
99417. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT
99418. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK
99419. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT
99420. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK
99421. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT
99422. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK
99423. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT
99424. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK
99425. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT
99426. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK
99427. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT
99428. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK
99429. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT
99430. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK
99431. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT
99432. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK
99433. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT
99434. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK
99435. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT
99436. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK
99437. DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT
99438. DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK
99439. DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT
99440. DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK
99441. DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT
99442. DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK
99443. DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT
99444. DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK
99445. DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT
99446. DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK
99447. DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT
99448. DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK
99449. DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT
99450. DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK
99451. DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT
99452. DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK
99453. DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT
99454. DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK
99455. DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT
99456. DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK
99457. DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT
99458. DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK
99459. DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT
99460. DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK
99461. DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT
99462. DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK
99463. DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT
99464. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK
99465. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT
99466. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK
99467. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT
99468. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK
99469. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT
99470. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK
99471. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT
99472. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK
99473. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT
99474. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK
99475. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT
99476. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK
99477. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT
99478. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK
99479. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT
99480. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK
99481. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT
99482. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK
99483. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT
99484. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK
99485. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT
99486. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK
99487. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT
99488. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK
99489. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT
99490. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK
99491. DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT
99492. DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK
99493. DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT
99494. DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK
99495. DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT
99496. DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK
99497. DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT
99498. DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK
99499. DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT
99500. DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK
99501. DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT
99502. DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK
99503. DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT
99504. DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK
99505. DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT
99506. DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK
99507. DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT
99508. DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK
99509. DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT
99510. DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK
99511. DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT
99512. DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK
99513. DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT
99514. DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK
99515. DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT
99516. DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK
99517. DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT
99518. DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK
99519. DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT
99520. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK
99521. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99522. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99523. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99524. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99525. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99526. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK
99527. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT
99528. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK
99529. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT
99530. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK
99531. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT
99532. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK
99533. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99534. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99535. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99536. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99537. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99538. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK
99539. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT
99540. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK
99541. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT
99542. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK
99543. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT
99544. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK
99545. DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT
99546. DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK
99547. DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT
99548. DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99549. DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT
99550. DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK
99551. DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT
99552. DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99553. DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99554. DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99555. DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99556. DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK
99557. DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT
99558. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
99559. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT
99560. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
99561. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT
99562. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK
99563. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT
99564. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK
99565. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT
99566. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK
99567. DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT
99568. DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK
99569. DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT
99570. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK
99571. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99572. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99573. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99574. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99575. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99576. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK
99577. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT
99578. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK
99579. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT
99580. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK
99581. DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT
99582. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK
99583. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99584. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99585. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99586. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99587. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99588. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK
99589. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT
99590. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK
99591. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT
99592. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK
99593. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT
99594. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK
99595. DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT
99596. DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK
99597. DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT
99598. DISP_INTERRUPT_STATUS_CONTINUE3
99599. DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK
99600. DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT
99601. DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK
99602. DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT
99603. DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK
99604. DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT
99605. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK
99606. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99607. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99608. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99609. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99610. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99611. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK
99612. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT
99613. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK
99614. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT
99615. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK
99616. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT
99617. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK
99618. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99619. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99620. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99621. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99622. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99623. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK
99624. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT
99625. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK
99626. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT
99627. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK
99628. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT
99629. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK
99630. DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT
99631. DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK
99632. DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT
99633. DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
99634. DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT
99635. DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK
99636. DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT
99637. DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99638. DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99639. DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99640. DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99641. DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK
99642. DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT
99643. DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
99644. DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT
99645. DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
99646. DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT
99647. DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK
99648. DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT
99649. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK
99650. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99651. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99652. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99653. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99654. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99655. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK
99656. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT
99657. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK
99658. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT
99659. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK
99660. DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT
99661. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK
99662. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99663. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99664. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99665. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99666. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99667. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK
99668. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT
99669. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK
99670. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT
99671. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK
99672. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT
99673. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK
99674. DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT
99675. DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK
99676. DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT
99677. DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT_MASK
99678. DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT__SHIFT
99679. DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT_MASK
99680. DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT__SHIFT
99681. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK
99682. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT
99683. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK
99684. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT
99685. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK
99686. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT
99687. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK
99688. DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT
99689. DISP_INTERRUPT_STATUS_CONTINUE4
99690. DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK
99691. DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT
99692. DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK
99693. DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT
99694. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK
99695. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99696. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99697. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99698. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99699. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99700. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK
99701. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT
99702. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK
99703. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT
99704. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK
99705. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT
99706. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK
99707. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99708. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99709. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99710. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99711. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99712. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK
99713. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99714. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99715. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99716. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99717. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99718. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK
99719. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT
99720. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK
99721. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT
99722. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK
99723. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT
99724. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK
99725. DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT
99726. DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK
99727. DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT
99728. DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
99729. DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT
99730. DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK
99731. DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT
99732. DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99733. DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99734. DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99735. DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99736. DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK
99737. DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT
99738. DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
99739. DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT
99740. DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
99741. DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT
99742. DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK
99743. DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT
99744. DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK
99745. DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT
99746. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK
99747. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99748. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99749. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99750. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99751. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99752. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK
99753. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT
99754. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK
99755. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT
99756. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK
99757. DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT
99758. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK
99759. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99760. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99761. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99762. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99763. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99764. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK
99765. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99766. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99767. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99768. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99769. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99770. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK
99771. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT
99772. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK
99773. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT
99774. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK
99775. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT
99776. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK
99777. DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT
99778. DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK
99779. DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT
99780. DISP_INTERRUPT_STATUS_CONTINUE5
99781. DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK
99782. DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT
99783. DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK
99784. DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT
99785. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK
99786. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT
99787. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK
99788. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT
99789. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK
99790. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT
99791. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK
99792. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99793. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99794. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99795. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99796. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99797. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK
99798. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99799. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99800. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99801. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99802. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99803. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK
99804. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT
99805. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK
99806. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT
99807. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK
99808. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT
99809. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK
99810. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT
99811. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK
99812. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT
99813. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK
99814. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT
99815. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK
99816. DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT
99817. DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK
99818. DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT
99819. DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
99820. DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT
99821. DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK
99822. DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT
99823. DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99824. DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99825. DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99826. DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99827. DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK
99828. DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT
99829. DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
99830. DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT
99831. DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
99832. DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT
99833. DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK
99834. DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT
99835. DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK
99836. DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT
99837. DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK
99838. DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT
99839. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK
99840. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT
99841. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
99842. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
99843. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
99844. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
99845. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK
99846. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT
99847. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
99848. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
99849. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
99850. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
99851. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK
99852. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT
99853. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK
99854. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT
99855. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK
99856. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT
99857. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK
99858. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT
99859. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK
99860. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT
99861. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK
99862. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT
99863. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK
99864. DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT
99865. DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK
99866. DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT
99867. DISP_INTERRUPT_STATUS_CONTINUE6
99868. DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK
99869. DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT
99870. DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK
99871. DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT
99872. DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK
99873. DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT
99874. DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK
99875. DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT
99876. DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK
99877. DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT
99878. DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK
99879. DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT
99880. DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK
99881. DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT
99882. DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK
99883. DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT
99884. DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK
99885. DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT
99886. DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK
99887. DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT
99888. DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK
99889. DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT
99890. DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK
99891. DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT
99892. DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK
99893. DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT
99894. DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK
99895. DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT
99896. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK
99897. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT
99898. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK
99899. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT
99900. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK
99901. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT
99902. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK
99903. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT
99904. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK
99905. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT
99906. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK
99907. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT
99908. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK
99909. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT
99910. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK
99911. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT
99912. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK
99913. DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
99914. DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
99915. DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
99916. DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
99917. DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
99918. DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK
99919. DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT
99920. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK
99921. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT
99922. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK
99923. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT
99924. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK
99925. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT
99926. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK
99927. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT
99928. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK
99929. DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT
99930. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK
99931. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT
99932. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK
99933. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT
99934. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK
99935. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT
99936. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK
99937. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT
99938. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK
99939. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT
99940. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK
99941. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT
99942. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK
99943. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT
99944. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK
99945. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT
99946. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK
99947. DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
99948. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK
99949. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT
99950. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK
99951. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT
99952. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK
99953. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT
99954. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK
99955. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT
99956. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK
99957. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT
99958. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK
99959. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT
99960. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK
99961. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT
99962. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK
99963. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT
99964. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK
99965. DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
99966. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK
99967. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT
99968. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK
99969. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT
99970. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK
99971. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT
99972. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK
99973. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT
99974. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK
99975. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT
99976. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK
99977. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT
99978. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK
99979. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT
99980. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK
99981. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT
99982. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK
99983. DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
99984. DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK
99985. DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT
99986. DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK
99987. DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT
99988. DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK
99989. DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT
99990. DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK
99991. DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT
99992. DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK
99993. DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT
99994. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT_MASK
99995. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT__SHIFT
99996. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT_MASK
99997. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT__SHIFT
99998. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT_MASK
99999. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT__SHIFT
100000. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT_MASK
100001. DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT__SHIFT
100002. DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK
100003. DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT
100004. DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK
100005. DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT
100006. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK
100007. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT
100008. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK
100009. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT
100010. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK
100011. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT
100012. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK
100013. DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT
100014. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK
100015. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT
100016. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK
100017. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT
100018. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK
100019. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT
100020. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK
100021. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT
100022. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK
100023. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT
100024. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK
100025. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT
100026. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK
100027. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT
100028. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK
100029. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT
100030. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100031. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100032. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK
100033. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT
100034. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK
100035. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT
100036. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK
100037. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT
100038. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK
100039. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT
100040. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK
100041. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT
100042. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK
100043. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT
100044. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK
100045. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT
100046. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK
100047. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT
100048. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100049. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100050. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK
100051. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT
100052. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK
100053. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT
100054. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK
100055. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT
100056. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK
100057. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT
100058. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK
100059. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT
100060. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK
100061. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT
100062. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK
100063. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT
100064. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK
100065. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT
100066. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100067. DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100068. DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK
100069. DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT
100070. DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK
100071. DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT
100072. DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK
100073. DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT
100074. DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK
100075. DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT
100076. DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK
100077. DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT
100078. DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK
100079. DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT
100080. DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK
100081. DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT
100082. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT_MASK
100083. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT__SHIFT
100084. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT_MASK
100085. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT__SHIFT
100086. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT_MASK
100087. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT__SHIFT
100088. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT_MASK
100089. DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT__SHIFT
100090. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK
100091. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT
100092. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK
100093. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT
100094. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK
100095. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT
100096. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK
100097. DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT
100098. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK
100099. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT
100100. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK
100101. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT
100102. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK
100103. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT
100104. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK
100105. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT
100106. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK
100107. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT
100108. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK
100109. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT
100110. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK
100111. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT
100112. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK
100113. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT
100114. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100115. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100116. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK
100117. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT
100118. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK
100119. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT
100120. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK
100121. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT
100122. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK
100123. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT
100124. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK
100125. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT
100126. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK
100127. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT
100128. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK
100129. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT
100130. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK
100131. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT
100132. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100133. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100134. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK
100135. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT
100136. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK
100137. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT
100138. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK
100139. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT
100140. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK
100141. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT
100142. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK
100143. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT
100144. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK
100145. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT
100146. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK
100147. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT
100148. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK
100149. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT
100150. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100151. DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100152. DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK
100153. DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT
100154. DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK
100155. DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT
100156. DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK
100157. DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT
100158. DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK
100159. DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT
100160. DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK
100161. DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT
100162. DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK
100163. DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT
100164. DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK
100165. DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT
100166. DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100167. DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100168. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK
100169. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT
100170. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK
100171. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT
100172. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK
100173. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT
100174. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT_MASK
100175. DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT__SHIFT
100176. DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK
100177. DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT
100178. DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK
100179. DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT
100180. DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK
100181. DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT
100182. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK
100183. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT
100184. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
100185. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
100186. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
100187. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
100188. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK
100189. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT
100190. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK
100191. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT
100192. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK
100193. DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT
100194. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK
100195. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT
100196. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
100197. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
100198. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
100199. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
100200. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK
100201. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT
100202. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK
100203. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT
100204. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK
100205. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT
100206. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK
100207. DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT
100208. DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK
100209. DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT
100210. DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100211. DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT
100212. DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK
100213. DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT
100214. DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
100215. DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
100216. DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
100217. DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
100218. DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK
100219. DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT
100220. DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK
100221. DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT
100222. DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK
100223. DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT
100224. DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
100225. DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT
100226. DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK
100227. DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT
100228. DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
100229. DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT
100230. DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK
100231. DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT
100232. DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK
100233. DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT
100234. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK
100235. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT
100236. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK
100237. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT
100238. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK
100239. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT
100240. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK
100241. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT
100242. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK
100243. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT
100244. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK
100245. DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT
100246. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK
100247. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT
100248. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
100249. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
100250. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
100251. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
100252. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK
100253. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT
100254. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK
100255. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT
100256. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK
100257. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT
100258. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK
100259. DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT
100260. DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK
100261. DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT
100262. DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK
100263. DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT
100264. DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK
100265. DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT
100266. DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK
100267. DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT
100268. DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK
100269. DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT
100270. DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK
100271. DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT
100272. DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK
100273. DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT
100274. DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
100275. DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
100276. DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
100277. DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
100278. DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK
100279. DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT
100280. DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK
100281. DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT
100282. DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK
100283. DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT
100284. DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK
100285. DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT
100286. DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK
100287. DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT
100288. DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK
100289. DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT
100290. DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK
100291. DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT
100292. DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK
100293. DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT
100294. DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100295. DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT
100296. DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK
100297. DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT
100298. DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK
100299. DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT
100300. DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK
100301. DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT
100302. DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK
100303. DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT
100304. DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK
100305. DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT
100306. DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK
100307. DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT
100308. DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK
100309. DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT
100310. DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK
100311. DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT
100312. DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK
100313. DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT
100314. DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
100315. DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT
100316. DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
100317. DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT
100318. DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK
100319. DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT
100320. DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK
100321. DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT
100322. DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK
100323. DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT
100324. DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
100325. DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
100326. DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK
100327. DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT
100328. DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK
100329. DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT
100330. DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK
100331. DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT
100332. DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK
100333. DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT
100334. DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK
100335. DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT
100336. DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK
100337. DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT
100338. DISP_INTF_SEL
100339. DISP_IPC_ENABLE
100340. DISP_LCD
100341. DISP_LIN_TRANS_GRPH_A
100342. DISP_LIN_TRANS_GRPH_B
100343. DISP_LIN_TRANS_GRPH_C
100344. DISP_LIN_TRANS_GRPH_D
100345. DISP_LIN_TRANS_GRPH_E
100346. DISP_LIN_TRANS_GRPH_F
100347. DISP_LIN_TRANS_VID_A
100348. DISP_LIN_TRANS_VID_B
100349. DISP_LIN_TRANS_VID_C
100350. DISP_LIN_TRANS_VID_D
100351. DISP_LIN_TRANS_VID_E
100352. DISP_LIN_TRANS_VID_F
100353. DISP_MARK
100354. DISP_MERGE_CNTL
100355. DISP_MISC_CNTL
100356. DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS
100357. DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP
100358. DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK
100359. DISP_MISC_CNTL_SOFT_RESET_GRPH_PP
100360. DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK
100361. DISP_MISC_CNTL_SOFT_RESET_LVDS
100362. DISP_MISC_CNTL_SOFT_RESET_OV0_PP
100363. DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK
100364. DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP
100365. DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK
100366. DISP_MISC_CNTL_SOFT_RESET_TMDS
100367. DISP_MISC_CNTL_SOFT_RESET_TV
100368. DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK
100369. DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK
100370. DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK
100371. DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS
100372. DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK
100373. DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP
100374. DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK
100375. DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK
100376. DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK
100377. DISP_MISC_CNTL__SOFT_RESET_GRPH_PP
100378. DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK
100379. DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK
100380. DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK
100381. DISP_MISC_CNTL__SOFT_RESET_LVDS
100382. DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK
100383. DISP_MISC_CNTL__SOFT_RESET_OV0_PP
100384. DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK
100385. DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK
100386. DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK
100387. DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP
100388. DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK
100389. DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK
100390. DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK
100391. DISP_MISC_CNTL__SOFT_RESET_TMDS
100392. DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK
100393. DISP_MISC_CNTL__SOFT_RESET_TV
100394. DISP_MISC_CNTL__SOFT_RESET_TV_MASK
100395. DISP_MISC_CNTL__SYNC_PAD_FLOP_EN
100396. DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK
100397. DISP_MISC_CNTL__SYNC_STRENGTH_MASK
100398. DISP_MOUT_ACLK_DISP_222_USER
100399. DISP_MOUT_ACLK_DISP_333_USER
100400. DISP_MOUT_HDMI_PHY_PIXEL
100401. DISP_MOUT_HDMI_PHY_PIXEL_USER
100402. DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER
100403. DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER
100404. DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER
100405. DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER
100406. DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER
100407. DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER
100408. DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER
100409. DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER
100410. DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER
100411. DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER
100412. DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS
100413. DISP_MOUT_SCLK_DISP_PIXEL_USER
100414. DISP_MOUT_SCLK_HDMI_PIXEL
100415. DISP_MOUT_SCLK_HDMI_SPDIF
100416. DISP_NR_CLK
100417. DISP_OD_CFG
100418. DISP_OD_EN
100419. DISP_OD_INTEN
100420. DISP_OD_INTSTA
100421. DISP_OD_SIZE
100422. DISP_OFF
100423. DISP_ON
100424. DISP_ORDER_BLUE_RED
100425. DISP_ORDER_RED_BLUE
100426. DISP_OUTPUT_CNTL
100427. DISP_PAGE
100428. DISP_PASS
100429. DISP_PHY_CONFIG__Corner_MASK
100430. DISP_PHY_CONFIG__Corner__SHIFT
100431. DISP_PHY_CONFIG__DispPHYConfig_MASK
100432. DISP_PHY_CONFIG__DispPHYConfig__SHIFT
100433. DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit_MASK
100434. DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit__SHIFT
100435. DISP_PIC_FRAME_TYPE
100436. DISP_PIC_PROFILE
100437. DISP_PIXDEPTH
100438. DISP_PLL_CON0
100439. DISP_PLL_CON1
100440. DISP_PLL_EN
100441. DISP_PLL_FDET
100442. DISP_PLL_FREQ_DET
100443. DISP_PLL_LOCK
100444. DISP_PLL_M
100445. DISP_PLL_N
100446. DISP_PLL_P
100447. DISP_PM
100448. DISP_PWM_EN
100449. DISP_PWR_MAN
100450. DISP_PWR_MAN_AUTO_PWRUP_EN
100451. DISP_PWR_MAN_DIG_TMDS_ENABLE_RST
100452. DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN
100453. DISP_PWR_MAN_DISP_D1D2_GRPH_RST
100454. DISP_PWR_MAN_DISP_D1D2_OV0_RST
100455. DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST
100456. DISP_PWR_MAN_DISP_D3_GRPH_RST
100457. DISP_PWR_MAN_DISP_D3_OV0_RST
100458. DISP_PWR_MAN_DISP_D3_REG_RST
100459. DISP_PWR_MAN_DISP_D3_RST
100460. DISP_PWR_MAN_DISP_D3_SUBPIC_RST
100461. DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN
100462. DISP_PWR_MAN_TV_ENABLE_RST
100463. DISP_PWR_MAN__AUTO_PWRUP_EN
100464. DISP_PWR_MAN__AUTO_PWRUP_EN_MASK
100465. DISP_PWR_MAN__DIG_TMDS_ENABLE_RST
100466. DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK
100467. DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN
100468. DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK
100469. DISP_PWR_MAN__DISP_D1D2_GRPH_RST
100470. DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK
100471. DISP_PWR_MAN__DISP_D1D2_OV0_RST
100472. DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK
100473. DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST
100474. DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK
100475. DISP_PWR_MAN__DISP_D3_GRPH_RST
100476. DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK
100477. DISP_PWR_MAN__DISP_D3_OV0_RST
100478. DISP_PWR_MAN__DISP_D3_OV0_RST_MASK
100479. DISP_PWR_MAN__DISP_D3_REG_RST
100480. DISP_PWR_MAN__DISP_D3_REG_RST_MASK
100481. DISP_PWR_MAN__DISP_D3_RST
100482. DISP_PWR_MAN__DISP_D3_RST_MASK
100483. DISP_PWR_MAN__DISP_D3_SUBPIC_RST
100484. DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK
100485. DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN
100486. DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
100487. DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK
100488. DISP_PWR_MAN__TV_ENABLE_RST
100489. DISP_PWR_MAN__TV_ENABLE_RST_MASK
100490. DISP_PW_ID_NONE
100491. DISP_RDMA_MEM_CON
100492. DISP_RDMA_MEM_GMC_SETTING_0
100493. DISP_RDMA_MEM_SRC_PITCH
100494. DISP_RDMA_MEM_START_ADDR
100495. DISP_REG_CONFIG_DISP_COLOR0_SEL_IN
100496. DISP_REG_CONFIG_DISP_COLOR1_SEL_IN
100497. DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN
100498. DISP_REG_CONFIG_DISP_OD_MOUT_EN
100499. DISP_REG_CONFIG_DISP_OVL0_MOUT_EN
100500. DISP_REG_CONFIG_DISP_OVL1_MOUT_EN
100501. DISP_REG_CONFIG_DISP_OVL_MOUT_EN
100502. DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN
100503. DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN
100504. DISP_REG_CONFIG_DISP_RDMA2_SOUT
100505. DISP_REG_CONFIG_DISP_UFOE_MOUT_EN
100506. DISP_REG_CONFIG_DPI_SEL
100507. DISP_REG_CONFIG_DPI_SEL_IN
100508. DISP_REG_CONFIG_DSIE_SEL_IN
100509. DISP_REG_CONFIG_DSIO_SEL_IN
100510. DISP_REG_CONFIG_DSI_SEL
100511. DISP_REG_CONFIG_MMSYS_CG_CON0
100512. DISP_REG_CONFIG_OUT_SEL
100513. DISP_REG_MUTEX
100514. DISP_REG_MUTEX_EN
100515. DISP_REG_MUTEX_MOD
100516. DISP_REG_MUTEX_MOD2
100517. DISP_REG_MUTEX_RST
100518. DISP_REG_MUTEX_SOF
100519. DISP_REG_OVL_ADDR
100520. DISP_REG_OVL_ADDR_MT2701
100521. DISP_REG_OVL_ADDR_MT8173
100522. DISP_REG_OVL_CON
100523. DISP_REG_OVL_EN
100524. DISP_REG_OVL_INTEN
100525. DISP_REG_OVL_INTSTA
100526. DISP_REG_OVL_OFFSET
100527. DISP_REG_OVL_PITCH
100528. DISP_REG_OVL_RDMA_CTRL
100529. DISP_REG_OVL_RDMA_GMC
100530. DISP_REG_OVL_ROI_BGCLR
100531. DISP_REG_OVL_ROI_SIZE
100532. DISP_REG_OVL_RST
100533. DISP_REG_OVL_SRC_CON
100534. DISP_REG_OVL_SRC_SIZE
100535. DISP_REG_RDMA_FIFO_CON
100536. DISP_REG_RDMA_GLOBAL_CON
100537. DISP_REG_RDMA_INT_ENABLE
100538. DISP_REG_RDMA_INT_STATUS
100539. DISP_REG_RDMA_SIZE_CON_0
100540. DISP_REG_RDMA_SIZE_CON_1
100541. DISP_REG_RDMA_TARGET_LINE
100542. DISP_REG_UFO_START
100543. DISP_SCLK_PIXEL
100544. DISP_SEL0_ADDR
100545. DISP_SEL1_ADDR
100546. DISP_SEL2_ADDR
100547. DISP_SEL3_ADDR
100548. DISP_SEL4_ADDR
100549. DISP_SEL5_ADDR
100550. DISP_SEL6_ADDR
100551. DISP_SEL7_ADDR
100552. DISP_SEQ_A
100553. DISP_SEQ_B
100554. DISP_SL
100555. DISP_SLC
100556. DISP_SRC_DISP
100557. DISP_SRC_NONE
100558. DISP_SRC_OVLY2
100559. DISP_SRC_ROT
100560. DISP_SRC_SCL2
100561. DISP_SYNCCONF
100562. DISP_SYNCSIZE
100563. DISP_TEST_DEBUG_CNTL
100564. DISP_TILE_SURFACE_SWIZZLING
100565. DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK
100566. DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
100567. DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK
100568. DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
100569. DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK
100570. DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK
100571. DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT
100572. DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK
100573. DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
100574. DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
100575. DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
100576. DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK
100577. DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT
100578. DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT
100579. DISP_TIMER_ID__DISP_T0_INT_ID_MASK
100580. DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT
100581. DISP_TIMER_ID__DISP_T1_INT_ID_MASK
100582. DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT
100583. DISP_TIMER_INTERRUPT
100584. DISP_UDC_RAM
100585. DISP_VBLANK
100586. DISP_VSYNC
100587. DISRDMST
100588. DISRXCTL
100589. DISRXDATA
100590. DISRX_ST0
100591. DISRX_ST1
100592. DISR_EL1
100593. DISR_EL1_ESR_MASK
100594. DISR_EL1_IDS
100595. DIST
100596. DISTEXT
100597. DISTLBWALKPRB
100598. DISTRIBUTION_MAX_INDEX
100599. DISTRIBUTION_MAX_SIZE
100600. DISTS
100601. DISTXCTL
100602. DISTXDATA
100603. DISTX_MODE
100604. DIST_BOOK
100605. DIST_CORE
100606. DIST_DRAWER
100607. DIST_EMPTY
100608. DIST_MAX
100609. DIST_MC
100610. DIST_MODEL_END
100611. DIST_MODEL_START
100612. DIST_SLOTS
100613. DIST_SLOT_BITS
100614. DIST_STATES
100615. DISWRMST8
100616. DISWRMST9
100617. DIS_1588_CLKS
100618. DIS_ADAPTIVE
100619. DIS_ALWAYS
100620. DIS_ATIM
100621. DIS_AUTO_DS
100622. DIS_AUTO_PS
100623. DIS_BCNQ_SUB
100624. DIS_BIT
100625. DIS_CARRIER_EXTEND
100626. DIS_DPD_MASK
100627. DIS_DPD_RATE6M
100628. DIS_DPD_RATE9M
100629. DIS_DPD_RATEALL
100630. DIS_DPD_RATEMCS0
100631. DIS_DPD_RATEMCS1
100632. DIS_DPD_RATEMCS8
100633. DIS_DPD_RATEMCS9
100634. DIS_DPD_RATEVHT1SS_MCS0
100635. DIS_DPD_RATEVHT1SS_MCS1
100636. DIS_DPD_RATEVHT2SS_MCS0
100637. DIS_DPD_RATEVHT2SS_MCS1
100638. DIS_DPF1
100639. DIS_DPF10
100640. DIS_DPF11
100641. DIS_DPF12
100642. DIS_DPF13
100643. DIS_DPF14
100644. DIS_DPF15
100645. DIS_DPF2
100646. DIS_DPF3
100647. DIS_DPF4
100648. DIS_DPF5
100649. DIS_DPF6
100650. DIS_DPF7
100651. DIS_DPF8
100652. DIS_DPF9
100653. DIS_EDCA_CNT_DWN
100654. DIS_EEE_10M
100655. DIS_EOT
100656. DIS_FALSE_LINK
100657. DIS_GCLK
100658. DIS_GPADC
100659. DIS_HOR_CRT_DIVBY2
100660. DIS_INT
100661. DIS_LINK_RST
100662. DIS_MCU_CLROOB
100663. DIS_MMC1_DPLL_REQ
100664. DIS_MMC2_DPLL_REQ
100665. DIS_NEVER
100666. DIS_PAD_SD_CLK_GATE
100667. DIS_PRECHARGE
100668. DIS_PS
100669. DIS_REMOTE_FAULT_SENSING
100670. DIS_RX_BSSID_FIT
100671. DIS_SAMPLE_RATE_148_5
100672. DIS_SAMPLE_RATE_25_2
100673. DIS_SAMPLE_RATE_27
100674. DIS_SAMPLE_RATE_54
100675. DIS_SAMPLE_RATE_74_25
100676. DIS_SCHMIT
100677. DIS_SDSAVE
100678. DIS_TERM
100679. DIS_TERM_DRV
100680. DIS_TRRR_GENERATION
100681. DIS_TSF_UDT
100682. DIS_TSF_UDT0_NORMAL_CHIP
100683. DIS_TSF_UDT0_TEST_CHIP
100684. DIS_TSF_UPDATE
100685. DIS_UART1_DPLL_REQ
100686. DIS_UART2_DPLL_REQ
100687. DIS_UART3_DPLL_REQ
100688. DIS_USB_HOST_DPLL_REQ
100689. DIS_USB_PVCI_CLK
100690. DIS_VGA_PASSTHROUGH
100691. DIS_ZERO
100692. DITEN
100693. DITHERCTRL2
100694. DITHERING_DEPTH_6BPC
100695. DITHERING_DEPTH_8BPC
100696. DITHERING_DEPTH_AUTO
100697. DITHERING_ENABLE
100698. DITHERING_MODE_AUTO
100699. DITHERING_MODE_DYNAMIC2X2
100700. DITHERING_MODE_OFF
100701. DITHERING_MODE_ON
100702. DITHERING_MODE_STATIC2X2
100703. DITHERING_MODE_TEMPORAL
100704. DITHER_4X8_EN1
100705. DITHER_4X8_EN1_SHIFT
100706. DITHER_4X8_EN2
100707. DITHER_4X8_EN2_SHIFT
100708. DITHER_ADD_LSHIFT_B
100709. DITHER_ADD_LSHIFT_G
100710. DITHER_ADD_LSHIFT_R
100711. DITHER_ADD_RSHIFT_B
100712. DITHER_ADD_RSHIFT_G
100713. DITHER_ADD_RSHIFT_R
100714. DITHER_ALWAYS
100715. DITHER_BYSPASS
100716. DITHER_CONTROL_DISABLE
100717. DITHER_CONTROL_ERRDIFF
100718. DITHER_CONTROL_MASK
100719. DITHER_CONTROL_ORDERED
100720. DITHER_DIS
100721. DITHER_DISABLE
100722. DITHER_DOWN_ALLEGRO
100723. DITHER_DOWN_FRC
100724. DITHER_EN
100725. DITHER_EN1
100726. DITHER_EN2
100727. DITHER_IF_ALPHA_OFF
100728. DITHER_LSB_ERR_SHIFT_B
100729. DITHER_LSB_ERR_SHIFT_G
100730. DITHER_LSB_ERR_SHIFT_R
100731. DITHER_MODE1
100732. DITHER_MODE1_SHIFT
100733. DITHER_MODE2
100734. DITHER_MODE2_SHIFT
100735. DITHER_NEW_BIT_MODE
100736. DITHER_ON
100737. DITHER_OPTION_DEFAULT
100738. DITHER_OPTION_DISABLE
100739. DITHER_OPTION_FM10
100740. DITHER_OPTION_FM6
100741. DITHER_OPTION_FM8
100742. DITHER_OPTION_INVALID
100743. DITHER_OPTION_MAX
100744. DITHER_OPTION_SPATIAL10
100745. DITHER_OPTION_SPATIAL10_FM6
100746. DITHER_OPTION_SPATIAL10_FM8
100747. DITHER_OPTION_SPATIAL10_FRAME_RANDOM
100748. DITHER_OPTION_SPATIAL6
100749. DITHER_OPTION_SPATIAL6_FRAME_RANDOM
100750. DITHER_OPTION_SPATIAL8
100751. DITHER_OPTION_SPATIAL8_FM6
100752. DITHER_OPTION_SPATIAL8_FRAME_RANDOM
100753. DITHER_OPTION_TRUN10
100754. DITHER_OPTION_TRUN10_FM6
100755. DITHER_OPTION_TRUN10_FM8
100756. DITHER_OPTION_TRUN10_SPATIAL6
100757. DITHER_OPTION_TRUN10_SPATIAL8
100758. DITHER_OPTION_TRUN10_SPATIAL8_FM6
100759. DITHER_OPTION_TRUN6
100760. DITHER_OPTION_TRUN8
100761. DITHER_OPTION_TRUN8_FM6
100762. DITHER_OPTION_TRUN8_SPATIAL6
100763. DITHER_OVFLW_BIT_B
100764. DITHER_OVFLW_BIT_G
100765. DITHER_OVFLW_BIT_R
100766. DITHER_PIXEL
100767. DITHER_SUBPIXEL
100768. DITHER_TBL_INDEX_SEL
100769. DITHER_TB_4X4_INDEX0
100770. DITHER_TB_4X4_INDEX1
100771. DITHER_TB_4X8_INDEX0
100772. DITHER_TB_4X8_INDEX1
100773. DITHER_TB_4X8_INDEX2
100774. DITHER_TB_4X8_INDEX3
100775. DITHMODE
100776. DITHMODE_B_POS_5BIT
100777. DITHMODE_B_POS_6BIT
100778. DITHMODE_B_POS_8BIT
100779. DITHMODE_B_POS_MASK
100780. DITHMODE_B_POS_SHIFT
100781. DITHMODE_DITH_EN
100782. DITHMODE_G_POS_5BIT
100783. DITHMODE_G_POS_6BIT
100784. DITHMODE_G_POS_8BIT
100785. DITHMODE_G_POS_MASK
100786. DITHMODE_G_POS_SHIFT
100787. DITHMODE_R_POS_5BIT
100788. DITHMODE_R_POS_6BIT
100789. DITHMODE_R_POS_8BIT
100790. DITHMODE_R_POS_MASK
100791. DITHMODE_R_POS_SHIFT
100792. DITH_CNTL_ADDR
100793. DITOREG
100794. DIV
100795. DIV16
100796. DIV2
100797. DIV2B
100798. DIV2_RATIO0
100799. DIV3B
100800. DIV4
100801. DIV4B
100802. DIV4_B
100803. DIV4_B3
100804. DIV4_DDR
100805. DIV4_DU
100806. DIV4_ENABLE_NR
100807. DIV4_GA
100808. DIV4_I
100809. DIV4_IRDA
100810. DIV4_M
100811. DIV4_M1
100812. DIV4_NR
100813. DIV4_P
100814. DIV4_RATIO
100815. DIV4_REPARENT_NR
100816. DIV4_S
100817. DIV4_S1
100818. DIV4_SH
100819. DIV4_SHA
100820. DIV4_SIUA
100821. DIV4_SIUB
100822. DIV4_U
100823. DIV64_U64_ROUND_CLOSEST
100824. DIV64_U64_ROUND_UP
100825. DIV6_FA
100826. DIV6_FB
100827. DIV6_I
100828. DIV6_NR
100829. DIV6_S
100830. DIV6_V
100831. DIV8
100832. DIVAGCCK
100833. DIVA_EEPROM_CLK
100834. DIVA_HSCX_ALE
100835. DIVA_HSCX_PORT
100836. DIVA_IRQ_BIT
100837. DIVA_IRQ_CLR
100838. DIVA_ISAC_ALE
100839. DIVA_ISAC_PORT
100840. DIVA_LED_A
100841. DIVA_LED_B
100842. DIVA_PCI_CTRL
100843. DIVA_RESET_BIT
100844. DIVERSITY_ANTENNA_A
100845. DIVERSITY_ANTENNA_B
100846. DIVERSITY_EITHER
100847. DIVERSITY_STATS_NUM_OF_ANT
100848. DIVIDER
100849. DIVIDER_3BIT
100850. DIVIDER_4BIT
100851. DIVIDE_BY_10
100852. DIVIDE_BY_2
100853. DIVIDE_BY_3
100854. DIVIDE_BY_4
100855. DIVIDE_BY_5
100856. DIVIDE_BY_6
100857. DIVIDE_BY_7
100858. DIVIDE_BY_8
100859. DIVIDE_BY_9
100860. DIVIL_BALL_OPTS
100861. DIVIL_CAP
100862. DIVIL_CONFIG
100863. DIVIL_DIAG
100864. DIVIL_ERROR
100865. DIVIL_LBAR_ACPI
100866. DIVIL_LBAR_GPIO
100867. DIVIL_LBAR_IRQ
100868. DIVIL_LBAR_KEL
100869. DIVIL_LBAR_MFGPT
100870. DIVIL_LBAR_PMS
100871. DIVIL_LBAR_SMB
100872. DIVIL_LEG_IO
100873. DIVIL_MSR_REG
100874. DIVIL_PM
100875. DIVIL_SMI
100876. DIVIL_SOFT_IRQ
100877. DIVIL_SOFT_RESET
100878. DIVISIONBYZEROEXCEPTION
100879. DIVISOR_CLK
100880. DIVISOR_ENABLE_MASK
100881. DIVISOR_IR_B_126
100882. DIVISOR_LATCH_LSB
100883. DIVISOR_LATCH_MSB
100884. DIVISOR_MAX
100885. DIVISOR_MIN
100886. DIVM_MASK
100887. DIVM_SHIFT
100888. DIVN_MASK
100889. DIVN_SHIFT
100890. DIVQ_VALUES
100891. DIVR
100892. DIVSEL_MASK
100893. DIVT
100894. DIVTBL
100895. DIVUL
100896. DIVVT
100897. DIV_18KHZ
100898. DIV_2
100899. DIV_4
100900. DIV_8
100901. DIV_ADJ
100902. DIV_APB
100903. DIV_APOLLO0
100904. DIV_APOLLO1
100905. DIV_APOLLO_PLL_FREQ_DET
100906. DIV_ATLAS0
100907. DIV_ATLAS1
100908. DIV_ATLAS_PLL_FREQ_DET
100909. DIV_AUD0
100910. DIV_AUD1
100911. DIV_BUS
100912. DIV_BYPASS
100913. DIV_BY_CLKS_PER_SEC
100914. DIV_CAM
100915. DIV_CAM00
100916. DIV_CAM01
100917. DIV_CAM02
100918. DIV_CAM03
100919. DIV_CAM1
100920. DIV_CAM10
100921. DIV_CAM11
100922. DIV_CAM_EN
100923. DIV_CAM_SEL
100924. DIV_CAM_SEL_EN
100925. DIV_CAM_SHIFT
100926. DIV_CAM_WIDTH
100927. DIV_CCORE
100928. DIV_CDREX0
100929. DIV_CDREX1
100930. DIV_CLOCKS
100931. DIV_CPIF
100932. DIV_CPU
100933. DIV_CPU0
100934. DIV_CPU1
100935. DIV_CPU_EN
100936. DIV_CPU_RST
100937. DIV_CPU_SEL
100938. DIV_CPU_SEL_EN
100939. DIV_CPU_SHIFT
100940. DIV_CPU_WIDTH
100941. DIV_CTL
100942. DIV_CTL1_DIV_FACTOR_MASK
100943. DIV_CTRL0
100944. DIV_CTRL1
100945. DIV_CTRL1_N_RESET_MASK
100946. DIV_DC
100947. DIV_DCLK0
100948. DIV_DCLK1
100949. DIV_DC_EN
100950. DIV_DC_RST
100951. DIV_DC_SEL
100952. DIV_DC_SEL_EN
100953. DIV_DC_SHIFT
100954. DIV_DC_WIDTH
100955. DIV_DDR_EN
100956. DIV_DDR_RST
100957. DIV_DDR_SHIFT
100958. DIV_DDR_WIDTH
100959. DIV_DISABLE
100960. DIV_DISP
100961. DIV_DISP10
100962. DIV_DISP1_0
100963. DIV_DISP_PLL_FREQ_DET
100964. DIV_DMC0
100965. DIV_DMC1
100966. DIV_EGL
100967. DIV_EGL_PLL_FDET
100968. DIV_EN
100969. DIV_ENABLE
100970. DIV_ENABLE_ACLK_G2D
100971. DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D
100972. DIV_ENABLE_IP_G2D0
100973. DIV_ENABLE_IP_G2D1
100974. DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D
100975. DIV_ENABLE_PCLK_G2D
100976. DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D
100977. DIV_ENABLE_SHIFT
100978. DIV_F
100979. DIV_FACTOR_MASK
100980. DIV_FRAC
100981. DIV_FRAC_START
100982. DIV_FRAC_START3
100983. DIV_FRAC_START3_MUX
100984. DIV_FRAC_START_MUX
100985. DIV_FROM_REG
100986. DIV_FSYS0
100987. DIV_FSYS1
100988. DIV_FSYS2
100989. DIV_FSYS3
100990. DIV_G2D
100991. DIV_G3D
100992. DIV_G3D_PLL_FDET
100993. DIV_G3D_PLL_FREQ_DET
100994. DIV_GATE
100995. DIV_GEN
100996. DIV_GSCL
100997. DIV_HALF
100998. DIV_HEVC
100999. DIV_ID
101000. DIV_ID_MASK
101001. DIV_ID_SHIFT
101002. DIV_IMAGE
101003. DIV_ISP
101004. DIV_ISP0
101005. DIV_ISP1
101006. DIV_KFC
101007. DIV_KFC0
101008. DIV_KFC_PLL_FDET
101009. DIV_LCD
101010. DIV_LCD0
101011. DIV_LEFTBUS
101012. DIV_LO_OUT
101013. DIV_MASK
101014. DIV_MASK_ALL
101015. DIV_MAU
101016. DIV_MAUDIO
101017. DIV_MAX
101018. DIV_MFC
101019. DIV_MIF
101020. DIV_MIF1
101021. DIV_MIF2
101022. DIV_MIF3
101023. DIV_MIF4
101024. DIV_MIF5
101025. DIV_MIF_PLL_FDET
101026. DIV_MIF_PLL_FREQ_DET
101027. DIV_MIN
101028. DIV_MODE
101029. DIV_MSCL
101030. DIV_N_MIN
101031. DIV_N_TO_CLK
101032. DIV_ONLY
101033. DIV_ON_DIBTX
101034. DIV_PARA_UPDATE
101035. DIV_PERI
101036. DIV_PERIC
101037. DIV_PERIC0
101038. DIV_PERIC1
101039. DIV_PERIC2
101040. DIV_PERIC3
101041. DIV_PERIC4
101042. DIV_PERIC5
101043. DIV_PERIL0
101044. DIV_PERIL1
101045. DIV_PERIL2
101046. DIV_PERIL3
101047. DIV_PERIL4
101048. DIV_PERIL5
101049. DIV_PRE_N
101050. DIV_RATIO_SHIFT
101051. DIV_RATIO_WIDTH
101052. DIV_REG_100_MHZ
101053. DIV_REG_200_MHZ
101054. DIV_RIGHTBUS
101055. DIV_ROUND
101056. DIV_ROUNDUP
101057. DIV_ROUND_CLOSEST
101058. DIV_ROUND_CLOSEST_DOWN
101059. DIV_ROUND_CLOSEST_ULL
101060. DIV_ROUND_DOWN_ULL
101061. DIV_ROUND_UP
101062. DIV_ROUND_UP_SECTOR_T
101063. DIV_ROUND_UP_ULL
101064. DIV_SAFE
101065. DIV_SEL0
101066. DIV_SEL1
101067. DIV_SEL2
101068. DIV_SELECT_MASK
101069. DIV_STAT_APOLLO0
101070. DIV_STAT_APOLLO1
101071. DIV_STAT_APOLLO_PLL_FREQ_DET
101072. DIV_STAT_ATLAS0
101073. DIV_STAT_ATLAS1
101074. DIV_STAT_ATLAS_PLL_FREQ_DET
101075. DIV_STAT_AUD0
101076. DIV_STAT_AUD1
101077. DIV_STAT_BUS
101078. DIV_STAT_CAM00
101079. DIV_STAT_CAM01
101080. DIV_STAT_CAM02
101081. DIV_STAT_CAM03
101082. DIV_STAT_CAM10
101083. DIV_STAT_CAM11
101084. DIV_STAT_DISP
101085. DIV_STAT_DISP_PLL_FREQ_DET
101086. DIV_STAT_EGL
101087. DIV_STAT_EGL_PLL_FDET
101088. DIV_STAT_G2D
101089. DIV_STAT_G3D
101090. DIV_STAT_G3D_PLL_FDET
101091. DIV_STAT_G3D_PLL_FREQ_DET
101092. DIV_STAT_GSCL
101093. DIV_STAT_HEVC
101094. DIV_STAT_ISP
101095. DIV_STAT_KFC
101096. DIV_STAT_KFC_PLL_FDET
101097. DIV_STAT_MFC
101098. DIV_STAT_MIF
101099. DIV_STAT_MIF1
101100. DIV_STAT_MIF2
101101. DIV_STAT_MIF3
101102. DIV_STAT_MIF4
101103. DIV_STAT_MIF5
101104. DIV_STAT_MIF_PLL_FDET
101105. DIV_STAT_MIF_PLL_FREQ_DET
101106. DIV_STAT_MSCL
101107. DIV_STAT_PERI
101108. DIV_STAT_PERIC
101109. DIV_STAT_TOP0
101110. DIV_STAT_TOP1
101111. DIV_STAT_TOP2
101112. DIV_STAT_TOP3
101113. DIV_STAT_TOP4
101114. DIV_STAT_TOP_BUS
101115. DIV_STAT_TOP_CAM10
101116. DIV_STAT_TOP_CAM11
101117. DIV_STAT_TOP_DISP
101118. DIV_STAT_TOP_FSYS0
101119. DIV_STAT_TOP_FSYS1
101120. DIV_STAT_TOP_FSYS2
101121. DIV_STAT_TOP_G2D_MFC
101122. DIV_STAT_TOP_GSCL_ISP0
101123. DIV_STAT_TOP_HPM
101124. DIV_STAT_TOP_ISP10
101125. DIV_STAT_TOP_ISP11
101126. DIV_STAT_TOP_MSCL
101127. DIV_STAT_TOP_PERI0
101128. DIV_STAT_TOP_PERI1
101129. DIV_STAT_TOP_PERI2
101130. DIV_STAT_TOP_PERIC0
101131. DIV_STAT_TOP_PERIC1
101132. DIV_STAT_TOP_PERIC2
101133. DIV_STAT_TOP_PERIC3
101134. DIV_STAT_TOP_PLL_FDET
101135. DIV_STAT_TOP_PLL_FREQ_DET
101136. DIV_STEP
101137. DIV_T
101138. DIV_TABLE
101139. DIV_TOP
101140. DIV_TOP0
101141. DIV_TOP03
101142. DIV_TOP0_PERIC0
101143. DIV_TOP0_PERIC1
101144. DIV_TOP0_PERIC2
101145. DIV_TOP0_PERIC3
101146. DIV_TOP1
101147. DIV_TOP13
101148. DIV_TOP1_FSYS0
101149. DIV_TOP1_FSYS1
101150. DIV_TOP1_FSYS11
101151. DIV_TOP2
101152. DIV_TOP3
101153. DIV_TOP4
101154. DIV_TOP8
101155. DIV_TOP9
101156. DIV_TOPC0
101157. DIV_TOPC1
101158. DIV_TOPC3
101159. DIV_TOP_BUS
101160. DIV_TOP_CAM10
101161. DIV_TOP_CAM11
101162. DIV_TOP_DISP
101163. DIV_TOP_FSYS0
101164. DIV_TOP_FSYS1
101165. DIV_TOP_FSYS2
101166. DIV_TOP_G2D_MFC
101167. DIV_TOP_GSCL_ISP0
101168. DIV_TOP_HPM
101169. DIV_TOP_ISP10
101170. DIV_TOP_ISP11
101171. DIV_TOP_MSCL
101172. DIV_TOP_PERI0
101173. DIV_TOP_PERI1
101174. DIV_TOP_PERI2
101175. DIV_TOP_PERIC0
101176. DIV_TOP_PERIC1
101177. DIV_TOP_PERIC2
101178. DIV_TOP_PERIC3
101179. DIV_TOP_PERIC4
101180. DIV_TOP_PLL_FDET
101181. DIV_TOP_PLL_FREQ_DET
101182. DIV_TO_REG
101183. DIV_TV
101184. DI_AW0
101185. DI_AW1
101186. DI_BS_CLKGEN0
101187. DI_BS_CLKGEN1
101188. DI_D3_CLK_IDLE_SHIFT
101189. DI_D3_CLK_POL_SHIFT
101190. DI_D3_CLK_SEL_SHIFT
101191. DI_D3_DATAMSK_SHIFT
101192. DI_D3_DATA_POL_SHIFT
101193. DI_D3_DRDY_SHARP_POL_SHIFT
101194. DI_D3_HSYNC_POL_SHIFT
101195. DI_D3_VSYNC_POL_SHIFT
101196. DI_DISABLE
101197. DI_DISP0_CB0_MAP
101198. DI_DISP0_CB1_MAP
101199. DI_DISP0_CB2_MAP
101200. DI_DISP0_DB0_MAP
101201. DI_DISP0_DB1_MAP
101202. DI_DISP0_DB2_MAP
101203. DI_DISP0_TIME_CONF_1
101204. DI_DISP0_TIME_CONF_2
101205. DI_DISP0_TIME_CONF_3
101206. DI_DISP1_CB0_MAP
101207. DI_DISP1_CB1_MAP
101208. DI_DISP1_CB2_MAP
101209. DI_DISP1_DB0_MAP
101210. DI_DISP1_DB1_MAP
101211. DI_DISP1_DB2_MAP
101212. DI_DISP1_TIME_CONF_1
101213. DI_DISP1_TIME_CONF_2
101214. DI_DISP1_TIME_CONF_3
101215. DI_DISP2_CB0_MAP
101216. DI_DISP2_CB1_MAP
101217. DI_DISP2_CB2_MAP
101218. DI_DISP2_DB0_MAP
101219. DI_DISP2_DB1_MAP
101220. DI_DISP2_DB2_MAP
101221. DI_DISP2_TIME_CONF_1
101222. DI_DISP2_TIME_CONF_2
101223. DI_DISP2_TIME_CONF_3
101224. DI_DISP3_B0_MAP
101225. DI_DISP3_B1_MAP
101226. DI_DISP3_B2_MAP
101227. DI_DISP3_TIME_CONF
101228. DI_DISP_ACC_CC
101229. DI_DISP_IF_CONF
101230. DI_DISP_LLA_CONF
101231. DI_DISP_LLA_DATA
101232. DI_DISP_SIG_POL
101233. DI_DOS_HIGH
101234. DI_DPMI_VALID
101235. DI_DW_GEN
101236. DI_DW_GEN_ACCESS_SIZE_OFFSET
101237. DI_DW_GEN_COMPONENT_SIZE_OFFSET
101238. DI_DW_SET
101239. DI_ENABLE
101240. DI_EXT
101241. DI_FACE_BACKFACE_CULL
101242. DI_FACE_CULL_FETCH
101243. DI_FACE_CULL_NONE
101244. DI_FACE_FRONTFACE_CULL
101245. DI_GENERAL
101246. DI_GEN_DI_CLK_EXT
101247. DI_GEN_DI_VSYNC_EXT
101248. DI_GEN_POLARITY_1
101249. DI_GEN_POLARITY_2
101250. DI_GEN_POLARITY_3
101251. DI_GEN_POLARITY_4
101252. DI_GEN_POLARITY_5
101253. DI_GEN_POLARITY_6
101254. DI_GEN_POLARITY_7
101255. DI_GEN_POLARITY_8
101256. DI_GEN_POLARITY_DISP_CLK
101257. DI_HSP_CLK_PER
101258. DI_INDEX_SIZE_16_BIT
101259. DI_INDEX_SIZE_32_BIT
101260. DI_INDEX_SIZE_8_BIT
101261. DI_MAJOR_MODE_0
101262. DI_MAJOR_MODE_1
101263. DI_MASK
101264. DI_MAX_FLUSH
101265. DI_PIN11
101266. DI_PIN12
101267. DI_PIN13
101268. DI_PIN14
101269. DI_PIN15
101270. DI_PIN16
101271. DI_PIN17
101272. DI_PIN_CS
101273. DI_PIN_SER_CLK
101274. DI_PIN_SER_RS
101275. DI_POL
101276. DI_POL_DRDY_DATA_POLARITY
101277. DI_POL_DRDY_POLARITY_15
101278. DI_PT_2D_COPY_RECT_LIST_V0
101279. DI_PT_2D_COPY_RECT_LIST_V1
101280. DI_PT_2D_COPY_RECT_LIST_V2
101281. DI_PT_2D_COPY_RECT_LIST_V3
101282. DI_PT_2D_FILL_RECT_LIST
101283. DI_PT_2D_LINE_STRIP
101284. DI_PT_2D_RECTANGLE
101285. DI_PT_2D_TRI_STRIP
101286. DI_PT_LINELIST
101287. DI_PT_LINELIST_ADJ
101288. DI_PT_LINELOOP
101289. DI_PT_LINESTRIP
101290. DI_PT_LINESTRIP_ADJ
101291. DI_PT_LINE_ADJ
101292. DI_PT_NONE
101293. DI_PT_PATCH
101294. DI_PT_POINTLIST
101295. DI_PT_POINTLIST_PSIZE
101296. DI_PT_POLYGON
101297. DI_PT_QUADLIST
101298. DI_PT_QUADSTRIP
101299. DI_PT_RECTLIST
101300. DI_PT_TRIFAN
101301. DI_PT_TRILIST
101302. DI_PT_TRILIST_ADJ
101303. DI_PT_TRISTRIP
101304. DI_PT_TRISTRIP_ADJ
101305. DI_PT_TRI_ADJ
101306. DI_PT_TRI_WITH_WFLAGS
101307. DI_PT_UNUSED_0
101308. DI_PT_UNUSED_1
101309. DI_PT_UNUSED_3
101310. DI_PT_UNUSED_4
101311. DI_REG
101312. DI_SCR_CONF
101313. DI_SER_CONF
101314. DI_SER_DISP1_CONF
101315. DI_SER_DISP2_CONF
101316. DI_SET
101317. DI_SRC_SEL_AUTO_INDEX
101318. DI_SRC_SEL_DMA
101319. DI_SRC_SEL_IMMEDIATE
101320. DI_SRC_SEL_RESERVED
101321. DI_SSC
101322. DI_STAT
101323. DI_STP_REP
101324. DI_SW_GEN0
101325. DI_SW_GEN0_OFFSET_COUNT
101326. DI_SW_GEN0_OFFSET_SRC
101327. DI_SW_GEN0_RUN_COUNT
101328. DI_SW_GEN0_RUN_SRC
101329. DI_SW_GEN1
101330. DI_SW_GEN1_AUTO_RELOAD
101331. DI_SW_GEN1_CNT_CLR_SRC
101332. DI_SW_GEN1_CNT_DOWN
101333. DI_SW_GEN1_CNT_POL_CLR_SRC
101334. DI_SW_GEN1_CNT_POL_GEN_EN
101335. DI_SW_GEN1_CNT_POL_TRIGGER_SRC
101336. DI_SW_GEN1_CNT_UP
101337. DI_SYNC_AS_GEN
101338. DI_SYNC_CLK
101339. DI_SYNC_CNT1
101340. DI_SYNC_CNT4
101341. DI_SYNC_CNT5
101342. DI_SYNC_DE
101343. DI_SYNC_HSYNC
101344. DI_SYNC_INT_HSYNC
101345. DI_SYNC_NONE
101346. DI_SYNC_VSYNC
101347. DI_VSYNC_SEL_OFFSET
101348. DInfo
101349. DIstruct
101350. DItype
101351. DIunion
101352. DJF
101353. DJP
101354. DJREPORT_LONG_LENGTH
101355. DJREPORT_SHORT_LENGTH
101356. DJV
101357. DJ_DEVICE_INDEX_MAX
101358. DJ_DEVICE_INDEX_MIN
101359. DJ_MAX_NUMBER_NOTIFS
101360. DJ_MAX_PAIRED_DEVICES
101361. DJ_RECEIVER_INDEX
101362. DK_CXLFLASH_ALL_PORTS_ACTIVE
101363. DK_CXLFLASH_APP_CLOSE_ADAP_FD
101364. DK_CXLFLASH_ATTACH
101365. DK_CXLFLASH_ATTACH_REUSE_CONTEXT
101366. DK_CXLFLASH_CONTEXT_SQ_CMD_MODE
101367. DK_CXLFLASH_DETACH
101368. DK_CXLFLASH_MANAGE_LUN
101369. DK_CXLFLASH_MANAGE_LUN_ALL_PORTS_ACCESSIBLE
101370. DK_CXLFLASH_MANAGE_LUN_DISABLE_SUPERPIPE
101371. DK_CXLFLASH_MANAGE_LUN_ENABLE_SUPERPIPE
101372. DK_CXLFLASH_MANAGE_LUN_WWID_LEN
101373. DK_CXLFLASH_RECOVER_AFU
101374. DK_CXLFLASH_RECOVER_AFU_CONTEXT_RESET
101375. DK_CXLFLASH_RELEASE
101376. DK_CXLFLASH_USER_DIRECT
101377. DK_CXLFLASH_USER_VIRTUAL
101378. DK_CXLFLASH_UVIRTUAL_NEED_WRITE_SAME
101379. DK_CXLFLASH_VERIFY
101380. DK_CXLFLASH_VERIFY_HINT_SENSE
101381. DK_CXLFLASH_VERIFY_SENSE_LEN
101382. DK_CXLFLASH_VERSION_0
101383. DK_CXLFLASH_VLUN_CLONE
101384. DK_CXLFLASH_VLUN_RESIZE
101385. DK_PAL_A2
101386. DK_PAL_MONO
101387. DK_PAL_NICAM
101388. DK_SECAM_A2DK1
101389. DK_SECAM_A2LDK3
101390. DK_SECAM_A2MONO
101391. DL19FDUPLX
101392. DL1_DATA2_DATA_MASK
101393. DL1_DATA2_DATA_MASK_SFT
101394. DL1_DATA2_DATA_SFT
101395. DL1_DATA2_HD_ALIGN_MASK
101396. DL1_DATA2_HD_ALIGN_MASK_SFT
101397. DL1_DATA2_HD_ALIGN_SFT
101398. DL1_DATA2_HD_MASK
101399. DL1_DATA2_HD_MASK_SFT
101400. DL1_DATA2_HD_SFT
101401. DL1_DATA2_MINLEN_MASK
101402. DL1_DATA2_MINLEN_MASK_SFT
101403. DL1_DATA2_MINLEN_SFT
101404. DL1_DATA2_MODE_MASK
101405. DL1_DATA2_MODE_MASK_SFT
101406. DL1_DATA2_MODE_SFT
101407. DL1_DATA2_NORMAL_MODE_MASK
101408. DL1_DATA2_NORMAL_MODE_MASK_SFT
101409. DL1_DATA2_NORMAL_MODE_SFT
101410. DL1_DATA2_ON_MASK
101411. DL1_DATA2_ON_MASK_SFT
101412. DL1_DATA2_ON_SFT
101413. DL1_DATA_MASK
101414. DL1_DATA_MASK_SFT
101415. DL1_DATA_SFT
101416. DL1_HD_ALIGN_MASK
101417. DL1_HD_ALIGN_MASK_SFT
101418. DL1_HD_ALIGN_SFT
101419. DL1_HD_MASK
101420. DL1_HD_MASK_SFT
101421. DL1_HD_SFT
101422. DL1_MAXLEN_MASK
101423. DL1_MAXLEN_MASK_SFT
101424. DL1_MAXLEN_SFT
101425. DL1_MINLEN_MASK
101426. DL1_MINLEN_MASK_SFT
101427. DL1_MINLEN_SFT
101428. DL1_MODE_MASK
101429. DL1_MODE_MASK_SFT
101430. DL1_MODE_SFT
101431. DL1_NORMAL_MODE_MASK
101432. DL1_NORMAL_MODE_MASK_SFT
101433. DL1_NORMAL_MODE_SFT
101434. DL1_ON_MASK
101435. DL1_ON_MASK_SFT
101436. DL1_ON_SFT
101437. DL1_PBUF_SIZE_MASK
101438. DL1_PBUF_SIZE_MASK_SFT
101439. DL1_PBUF_SIZE_SFT
101440. DL2_ARAMPSP_CTL_PRE_MASK
101441. DL2_ARAMPSP_CTL_PRE_MASK_SFT
101442. DL2_ARAMPSP_CTL_PRE_SFT
101443. DL2_DATA_MASK
101444. DL2_DATA_MASK_SFT
101445. DL2_DATA_SFT
101446. DL2_HD_ALIGN_MASK
101447. DL2_HD_ALIGN_MASK_SFT
101448. DL2_HD_ALIGN_SFT
101449. DL2_HD_MASK
101450. DL2_HD_MASK_SFT
101451. DL2_HD_SFT
101452. DL2_MAXLEN_MASK
101453. DL2_MAXLEN_MASK_SFT
101454. DL2_MAXLEN_SFT
101455. DL2_MINLEN_MASK
101456. DL2_MINLEN_MASK_SFT
101457. DL2_MINLEN_SFT
101458. DL2_MODE_MASK
101459. DL2_MODE_MASK_SFT
101460. DL2_MODE_SFT
101461. DL2_NORMAL_MODE_MASK
101462. DL2_NORMAL_MODE_MASK_SFT
101463. DL2_NORMAL_MODE_SFT
101464. DL2_ON_MASK
101465. DL2_ON_MASK_SFT
101466. DL2_ON_SFT
101467. DL2_PBUF_SIZE_MASK
101468. DL2_PBUF_SIZE_MASK_SFT
101469. DL2_PBUF_SIZE_SFT
101470. DL3_DATA_MASK
101471. DL3_DATA_MASK_SFT
101472. DL3_DATA_SFT
101473. DL3_HD_ALIGN_MASK
101474. DL3_HD_ALIGN_MASK_SFT
101475. DL3_HD_ALIGN_SFT
101476. DL3_HD_MASK
101477. DL3_HD_MASK_SFT
101478. DL3_HD_SFT
101479. DL3_MAXLEN_MASK
101480. DL3_MAXLEN_MASK_SFT
101481. DL3_MAXLEN_SFT
101482. DL3_MINLEN_MASK
101483. DL3_MINLEN_MASK_SFT
101484. DL3_MINLEN_SFT
101485. DL3_MODE_MASK
101486. DL3_MODE_MASK_SFT
101487. DL3_MODE_SFT
101488. DL3_NORMAL_MODE_MASK
101489. DL3_NORMAL_MODE_MASK_SFT
101490. DL3_NORMAL_MODE_SFT
101491. DL3_ON_MASK
101492. DL3_ON_MASK_SFT
101493. DL3_ON_SFT
101494. DL3_PBUF_SIZE_MASK
101495. DL3_PBUF_SIZE_MASK_SFT
101496. DL3_PBUF_SIZE_SFT
101497. DLA
101498. DLAB
101499. DLAVAIL
101500. DLAVAILQ
101501. DLB
101502. DLC
101503. DLCI_ACCOUNT_CIR_IN
101504. DLCI_BUFFER_IF
101505. DLCI_CLOSED
101506. DLCI_CLOSING
101507. DLCI_GET_CONF
101508. DLCI_GET_SLAVE
101509. DLCI_IGNORE_CIR_OUT
101510. DLCI_MODE_ABM
101511. DLCI_MODE_ADM
101512. DLCI_OPEN
101513. DLCI_OPENING
101514. DLCI_SET_CONF
101515. DLCI_VALID_FLAGS
101516. DLCRKM
101517. DLC_RTR_SHIFT
101518. DLDO1
101519. DLDO10
101520. DLDO11
101521. DLDO12
101522. DLDO2
101523. DLDO3
101524. DLDO4
101525. DLDO5
101526. DLDO6
101527. DLDO7
101528. DLDO8
101529. DLDO9
101530. DLE
101531. DLEVEL_PINS_BITS
101532. DLEVEL_PINS_MASK
101533. DLEVEL_PINS_PER_REG
101534. DLEVEL_REGS_OFFSET
101535. DLEV_DAT
101536. DLE_ENTRIES
101537. DLE_FLAG
101538. DLE_TOTAL_SIZE
101539. DLFB_IOCTL_REPORT_DAMAGE
101540. DLFB_IOCTL_RETURN_EDID
101541. DLFW_RESTORE_REG_NUM
101542. DLG_COLOR
101543. DLH
101544. DLINE_SZ
101545. DLINFO_ITEMS
101546. DLINK_DIAG
101547. DLINK_EEPROM
101548. DLINK_GPIO
101549. DLINK_PRODUCT_DWM_652
101550. DLINK_PRODUCT_DWM_652_U5
101551. DLINK_PRODUCT_DWM_652_U5A
101552. DLINK_VENDOR_ID
101553. DLL
101554. DLL1_CNTL
101555. DLL1_DIAG_CTRL
101556. DLL2_CNTL
101557. DLLCTRL
101558. DLLCTRL_RLD_ADRLN
101559. DLLFRQ
101560. DLLI_SIZE_BIT_SIZE
101561. DLLPR
101562. DLLRDY_MASK
101563. DLLRDY_SHIFT
101564. DLLTRM_ICP
101565. DLL_CALIB
101566. DLL_CALIB_ACK_WAIT_VAL
101567. DLL_CALIB_INTERVAL_DVFS
101568. DLL_CALIB_INTERVAL_MASK
101569. DLL_CALIB_INTERVAL_SHIFT
101570. DLL_CHANGE_NONE
101571. DLL_CHANGE_OFF
101572. DLL_CHANGE_ON
101573. DLL_CNTL
101574. DLL_CNTL__DLL_LOCK_TIME_MASK
101575. DLL_CNTL__DLL_LOCK_TIME__SHIFT
101576. DLL_CNTL__DLL_RESET_TIME_MASK
101577. DLL_CNTL__DLL_RESET_TIME__SHIFT
101578. DLL_CNTL__MRDCK0_BYPASS_MASK
101579. DLL_CNTL__MRDCK0_BYPASS__SHIFT
101580. DLL_CNTL__MRDCK1_BYPASS_MASK
101581. DLL_CNTL__MRDCK1_BYPASS__SHIFT
101582. DLL_CNTL__PWR2_MODE_MASK
101583. DLL_CNTL__PWR2_MODE__SHIFT
101584. DLL_DIAG_CTRL
101585. DLL_ENBL
101586. DLL_FORCE_SR_C_MASK
101587. DLL_FORCE_SR_C_SHIFT
101588. DLL_FORCE_VALUE
101589. DLL_HALF_DELAY_MASK_4D5
101590. DLL_HALF_DELAY_SHIFT_4D5
101591. DLL_HANDLE_T
101592. DLL_PRESENT
101593. DLL_PWDN
101594. DLL_RDY_MASK
101595. DLL_READY
101596. DLL_READY_READ
101597. DLL_REF
101598. DLL_REG_SET
101599. DLL_RESET
101600. DLL_RESET_DELAY
101601. DLL_SLAVE_DLY_CTRL_MASK_4D
101602. DLL_SLAVE_DLY_CTRL_SHIFT_4D
101603. DLL_SLEEP_DELAY
101604. DLL_SPEED
101605. DLL_SPEED_MASK
101606. DLL_STATUS
101607. DLL_SWT
101608. DLL_TRIM
101609. DLL_TRIM_ICP_MASK
101610. DLL_TRIM_ICP_SHIFT
101611. DLM
101612. DLMAPI_H
101613. DLMB_mskDBB
101614. DLMB_mskDBM
101615. DLMB_mskDBPA
101616. DLMB_mskDEN
101617. DLMB_mskDLMSZ
101618. DLMB_offDBB
101619. DLMB_offDBM
101620. DLMB_offDBPA
101621. DLMB_offDEN
101622. DLMB_offDLMSZ
101623. DLMCH_BIT_WIDTH_MASK
101624. DLMCOMMON_H
101625. DLMCONVERT_H
101626. DLMDEBUG_H
101627. DLMDOMAIN_H
101628. DLMFS_CAPABILITIES
101629. DLMFS_I
101630. DLMFS_MAGIC
101631. DLMGLUE_H
101632. DLM_ABORT
101633. DLM_ASSERT
101634. DLM_ASSERT_JOINED_MSG
101635. DLM_ASSERT_MASTER_FINISH_MIGRATION
101636. DLM_ASSERT_MASTER_MLE_CLEANUP
101637. DLM_ASSERT_MASTER_MSG
101638. DLM_ASSERT_MASTER_REQUERY
101639. DLM_ASSERT_RESPONSE_MASTERY_REF
101640. DLM_ASSERT_RESPONSE_REASSERT
101641. DLM_AST
101642. DLM_ASTUNLOCK
101643. DLM_BADARGS
101644. DLM_BADPARAM
101645. DLM_BADRESOURCE
101646. DLM_BADTYPE
101647. DLM_BAD_DEVICE_PATH
101648. DLM_BAST
101649. DLM_BEGIN_EXIT_DOMAIN_MSG
101650. DLM_BEGIN_RECO_MSG
101651. DLM_BLOCKED
101652. DLM_BLOCKED_LIST
101653. DLM_BLOCKED_ORPHAN
101654. DLM_BUCKETS_PER_PAGE
101655. DLM_CALLBACKS_SIZE
101656. DLM_CANCEL
101657. DLM_CANCELGRANT
101658. DLM_CANCEL_JOIN_MSG
101659. DLM_CB_BAST
101660. DLM_CB_CAST
101661. DLM_CB_SKIP
101662. DLM_CMD_HELLO
101663. DLM_CMD_MAX
101664. DLM_CMD_TIMEOUT
101665. DLM_CMD_UNSPEC
101666. DLM_CONVERTING_LIST
101667. DLM_CONVERT_LOCK_MAX_LEN
101668. DLM_CONVERT_LOCK_MSG
101669. DLM_CREATE_LOCK_MSG
101670. DLM_CTXT_IN_SHUTDOWN
101671. DLM_CTXT_JOINED
101672. DLM_CTXT_LEAVING
101673. DLM_CTXT_NEW
101674. DLM_CVTUNGRANT
101675. DLM_DEADLOCK
101676. DLM_DEBUGFS_DIR
101677. DLM_DEBUGFS_DLM_STATE
101678. DLM_DEBUGFS_LOCKING_STATE
101679. DLM_DEBUGFS_MLE_STATE
101680. DLM_DEBUGFS_PURGE_LIST
101681. DLM_DEBUG_BUF_LEN
101682. DLM_DENIED
101683. DLM_DENIED_GRACE_PERIOD
101684. DLM_DENIED_NOASTS
101685. DLM_DENIED_NOLOCKS
101686. DLM_DEREF_LOCKRES_DONE
101687. DLM_DEREF_LOCKRES_MSG
101688. DLM_DEREF_RESPONSE_DONE
101689. DLM_DEREF_RESPONSE_INPROG
101690. DLM_DEVICE_VERSION_MAJOR
101691. DLM_DEVICE_VERSION_MINOR
101692. DLM_DEVICE_VERSION_PATCH
101693. DLM_DOMAIN_BACKOFF_MS
101694. DLM_DOMAIN_NAME_MAX_LEN
101695. DLM_ECANCEL
101696. DLM_ERRNO_EBADR
101697. DLM_ERRNO_EBADSLT
101698. DLM_ERRNO_EDEADLK
101699. DLM_ERRNO_EINPROGRESS
101700. DLM_ERRNO_EOPNOTSUPP
101701. DLM_ERRNO_EPROTO
101702. DLM_ERRNO_ETIMEDOUT
101703. DLM_EUNLOCK
101704. DLM_EXIT_DOMAIN_MSG
101705. DLM_FINALIZE_RECO_MSG
101706. DLM_FINALIZE_STAGE2
101707. DLM_FORWARD
101708. DLM_GENL_NAME
101709. DLM_GENL_VERSION
101710. DLM_GRANTED
101711. DLM_GRANTED_LIST
101712. DLM_HASH_BUCKETS
101713. DLM_HASH_PAGES
101714. DLM_HASH_SIZE_DEFAULT
101715. DLM_HB_NODE_DOWN_PRI
101716. DLM_HB_NODE_UP_PRI
101717. DLM_HEADER_MAJOR
101718. DLM_HEADER_MINOR
101719. DLM_HEADER_SLOTS
101720. DLM_IFL_DEAD
101721. DLM_IFL_DEADLOCK_CANCEL
101722. DLM_IFL_ENDOFLIFE
101723. DLM_IFL_MSTCPY
101724. DLM_IFL_ORPHAN
101725. DLM_IFL_OVERLAP_CANCEL
101726. DLM_IFL_OVERLAP_UNLOCK
101727. DLM_IFL_RESEND
101728. DLM_IFL_STUB_MS
101729. DLM_IFL_TIMEOUT_CANCEL
101730. DLM_IFL_USER
101731. DLM_IFL_WATCH_TIMEWARN
101732. DLM_INBUF_LEN
101733. DLM_IVBUFLEN
101734. DLM_IVGROUPID
101735. DLM_IVLOCKID
101736. DLM_IVRESHANDLE
101737. DLM_JOIN_TIMEOUT_MSECS
101738. DLM_LKF_ALTCW
101739. DLM_LKF_ALTPR
101740. DLM_LKF_CANCEL
101741. DLM_LKF_CONVDEADLK
101742. DLM_LKF_CONVERT
101743. DLM_LKF_EXPEDITE
101744. DLM_LKF_FORCEUNLOCK
101745. DLM_LKF_HEADQUE
101746. DLM_LKF_IVVALBLK
101747. DLM_LKF_LOCAL
101748. DLM_LKF_NODLCKBLK
101749. DLM_LKF_NODLCKWT
101750. DLM_LKF_NOORDER
101751. DLM_LKF_NOQUEUE
101752. DLM_LKF_NOQUEUEBAST
101753. DLM_LKF_ORPHAN
101754. DLM_LKF_PERSISTENT
101755. DLM_LKF_QUECVT
101756. DLM_LKF_TIMEOUT
101757. DLM_LKF_VALBLK
101758. DLM_LKSB_GET_LVB
101759. DLM_LKSB_PUT_LVB
101760. DLM_LKSB_UNUSED1
101761. DLM_LKSB_UNUSED2
101762. DLM_LKSB_UNUSED3
101763. DLM_LKSB_UNUSED4
101764. DLM_LKSB_UNUSED5
101765. DLM_LKSB_UNUSED6
101766. DLM_LKSTS_CONVERT
101767. DLM_LKSTS_GRANTED
101768. DLM_LKSTS_WAITING
101769. DLM_LOCKID_NAME_MAX
101770. DLM_LOCKSPACE_LEN
101771. DLM_LOCK_CR
101772. DLM_LOCK_CW
101773. DLM_LOCK_DATA_VERSION
101774. DLM_LOCK_EX
101775. DLM_LOCK_IV
101776. DLM_LOCK_NL
101777. DLM_LOCK_PR
101778. DLM_LOCK_PW
101779. DLM_LOCK_REQUEST_MSG
101780. DLM_LOCK_RES_BLOCK_DIRTY
101781. DLM_LOCK_RES_DIRTY
101782. DLM_LOCK_RES_DROPPING_REF
101783. DLM_LOCK_RES_IN_PROGRESS
101784. DLM_LOCK_RES_MIGRATING
101785. DLM_LOCK_RES_OWNER_UNKNOWN
101786. DLM_LOCK_RES_READY
101787. DLM_LOCK_RES_RECOVERING
101788. DLM_LOCK_RES_RECOVERY_WAITING
101789. DLM_LOCK_RES_SETREF_INPROG
101790. DLM_LOCK_RES_UNINITED
101791. DLM_LSFL_FS
101792. DLM_LSFL_NEWEXCL
101793. DLM_LSFL_TIMEWARN
101794. DLM_LU_ADD
101795. DLM_LU_MATCH
101796. DLM_LU_RECOVER_DIR
101797. DLM_LU_RECOVER_MASTER
101798. DLM_LVB_LEN
101799. DLM_MASTERY_TIMEOUT_MS
101800. DLM_MASTER_REQUERY_MSG
101801. DLM_MASTER_REQUEST_MSG
101802. DLM_MASTER_RESP_ERROR
101803. DLM_MASTER_RESP_MAYBE
101804. DLM_MASTER_RESP_NO
101805. DLM_MASTER_RESP_YES
101806. DLM_MAXHANDLES
101807. DLM_MAXSTATS
101808. DLM_MAX_ADDR_COUNT
101809. DLM_MAX_MIGRATABLE_LOCKS
101810. DLM_MIGRATE_REQUEST_MSG
101811. DLM_MIGRATE_RESPONSE_MASTERY_REF
101812. DLM_MIGRATING
101813. DLM_MIGRATION_RETRY_MS
101814. DLM_MIG_LOCKRES_MAX_LEN
101815. DLM_MIG_LOCKRES_MSG
101816. DLM_MIG_LOCKRES_RESERVED
101817. DLM_MLE_BLOCK
101818. DLM_MLE_MASTER
101819. DLM_MLE_MIGRATION
101820. DLM_MLE_NUM_TYPES
101821. DLM_MOD_KEY
101822. DLM_MRES_ALL_DONE
101823. DLM_MRES_MIGRATION
101824. DLM_MRES_RECOVERY
101825. DLM_MSG
101826. DLM_MSG_BAST
101827. DLM_MSG_CANCEL
101828. DLM_MSG_CANCEL_REPLY
101829. DLM_MSG_CONVERT
101830. DLM_MSG_CONVERT_REPLY
101831. DLM_MSG_GRANT
101832. DLM_MSG_LOOKUP
101833. DLM_MSG_LOOKUP_REPLY
101834. DLM_MSG_PURGE
101835. DLM_MSG_REMOVE
101836. DLM_MSG_REQUEST
101837. DLM_MSG_REQUEST_REPLY
101838. DLM_MSG_UNLOCK
101839. DLM_MSG_UNLOCK_REPLY
101840. DLM_NOCLINFO
101841. DLM_NODE_DEATH_WAIT_MAX
101842. DLM_NOLOCKMGR
101843. DLM_NOPURGED
101844. DLM_NORMAL
101845. DLM_NOSUPPORT
101846. DLM_NOTQUEUED
101847. DLM_NO_CONTROL_DEVICE
101848. DLM_NO_DEVICE_PERMISSION
101849. DLM_PLOCK_FL_CLOSE
101850. DLM_PLOCK_MISC_NAME
101851. DLM_PLOCK_OP_GET
101852. DLM_PLOCK_OP_LOCK
101853. DLM_PLOCK_OP_UNLOCK
101854. DLM_PLOCK_VERSION_MAJOR
101855. DLM_PLOCK_VERSION_MINOR
101856. DLM_PLOCK_VERSION_PATCH
101857. DLM_PROC_FLAGS_CLOSING
101858. DLM_PROC_FLAGS_COMPAT
101859. DLM_PROXY_AST_MAX_LEN
101860. DLM_PROXY_AST_MSG
101861. DLM_PURGE_INTERVAL_MS
101862. DLM_QUERY_JOIN_MSG
101863. DLM_QUERY_NODEINFO
101864. DLM_QUERY_REGION
101865. DLM_RCOM
101866. DLM_RCOM_LOCK
101867. DLM_RCOM_LOCK_REPLY
101868. DLM_RCOM_LOOKUP
101869. DLM_RCOM_LOOKUP_REPLY
101870. DLM_RCOM_NAMES
101871. DLM_RCOM_NAMES_REPLY
101872. DLM_RCOM_STATUS
101873. DLM_RCOM_STATUS_REPLY
101874. DLM_RECOVERING
101875. DLM_RECOVERY_LOCK_NAME
101876. DLM_RECOVERY_LOCK_NAME_LEN
101877. DLM_RECO_DATA_DONE_MSG
101878. DLM_RECO_NODE_DATA_DEAD
101879. DLM_RECO_NODE_DATA_DONE
101880. DLM_RECO_NODE_DATA_FINALIZE_SENT
101881. DLM_RECO_NODE_DATA_INIT
101882. DLM_RECO_NODE_DATA_RECEIVING
101883. DLM_RECO_NODE_DATA_REQUESTED
101884. DLM_RECO_NODE_DATA_REQUESTING
101885. DLM_RECO_STATE_ACTIVE
101886. DLM_RECO_STATE_FINALIZE
101887. DLM_RECO_THREAD_TIMEOUT_MS
101888. DLM_REJECTED
101889. DLM_REMOVE_NAMES_MAX
101890. DLM_RESNAME_MAXLEN
101891. DLM_RSF_NEED_SLOTS
101892. DLM_RS_DIR
101893. DLM_RS_DIR_ALL
101894. DLM_RS_DONE
101895. DLM_RS_DONE_ALL
101896. DLM_RS_LOCKS
101897. DLM_RS_LOCKS_ALL
101898. DLM_RS_NODES
101899. DLM_RS_NODES_ALL
101900. DLM_RTF_SHRINK
101901. DLM_SBF_ALTMODE
101902. DLM_SBF_DEMOTED
101903. DLM_SBF_VALNOTVALID
101904. DLM_STATUS_CONVERT
101905. DLM_STATUS_GRANTED
101906. DLM_STATUS_WAITING
101907. DLM_SYNC
101908. DLM_SYSERR
101909. DLM_THREAD_MAX_ASTS
101910. DLM_THREAD_MAX_DIRTY
101911. DLM_THREAD_MS
101912. DLM_THREAD_SHUFFLE_INTERVAL
101913. DLM_THREAD_TIMEOUT_MS
101914. DLM_TIMEOUT
101915. DLM_TYPE_LOCK
101916. DLM_TYPE_MAX
101917. DLM_TYPE_UNSPEC
101918. DLM_UNLOCK_CALL_AST
101919. DLM_UNLOCK_CLEAR_CONVERT_TYPE
101920. DLM_UNLOCK_FREE_LOCK
101921. DLM_UNLOCK_LOCK_MAX_LEN
101922. DLM_UNLOCK_LOCK_MSG
101923. DLM_UNLOCK_REGRANT_LOCK
101924. DLM_UNLOCK_REMOVE_LOCK
101925. DLM_UNUSED_MSG1
101926. DLM_USER_CREATE_LOCKSPACE
101927. DLM_USER_DEADLOCK
101928. DLM_USER_LOCK
101929. DLM_USER_LSFLG_AUTOFREE
101930. DLM_USER_LSFLG_FORCEFREE
101931. DLM_USER_LVB_LEN
101932. DLM_USER_PURGE
101933. DLM_USER_QUERY
101934. DLM_USER_REMOVE_LOCKSPACE
101935. DLM_USER_UNLOCK
101936. DLM_VALNOTVALID
101937. DLM_VERS_CONFLICT
101938. DLM_VOID
101939. DLM_WORKING
101940. DLN2_ADC_CHAN
101941. DLN2_ADC_CHANNEL_DISABLE
101942. DLN2_ADC_CHANNEL_ENABLE
101943. DLN2_ADC_CHANNEL_GET_ALL_VAL
101944. DLN2_ADC_CHANNEL_GET_CFG
101945. DLN2_ADC_CHANNEL_GET_VAL
101946. DLN2_ADC_CHANNEL_SET_CFG
101947. DLN2_ADC_CONDITION_MET_EV
101948. DLN2_ADC_DATA_BITS
101949. DLN2_ADC_DISABLE
101950. DLN2_ADC_ENABLE
101951. DLN2_ADC_EVENT_ALWAYS
101952. DLN2_ADC_EVENT_BELOW
101953. DLN2_ADC_EVENT_INSIDE
101954. DLN2_ADC_EVENT_LEVEL_ABOVE
101955. DLN2_ADC_EVENT_NONE
101956. DLN2_ADC_EVENT_OUTSIDE
101957. DLN2_ADC_GET_CHANNEL_COUNT
101958. DLN2_ADC_ID
101959. DLN2_ADC_MAX_CHANNELS
101960. DLN2_ADC_MOD_NAME
101961. DLN2_ADC_SET_RESOLUTION
101962. DLN2_CMD
101963. DLN2_EP_IN
101964. DLN2_EP_OUT
101965. DLN2_GENERIC_CMD
101966. DLN2_GENERIC_MODULE_ID
101967. DLN2_GPIO_CONDITION_MET_EV
101968. DLN2_GPIO_DIRECTION_IN
101969. DLN2_GPIO_DIRECTION_OUT
101970. DLN2_GPIO_EVENT_CHANGE
101971. DLN2_GPIO_EVENT_CHANGE_FALLING
101972. DLN2_GPIO_EVENT_CHANGE_RISING
101973. DLN2_GPIO_EVENT_LVL_HIGH
101974. DLN2_GPIO_EVENT_LVL_LOW
101975. DLN2_GPIO_EVENT_MASK
101976. DLN2_GPIO_EVENT_NONE
101977. DLN2_GPIO_GET_DEBOUNCE
101978. DLN2_GPIO_GET_PIN_COUNT
101979. DLN2_GPIO_ID
101980. DLN2_GPIO_MAX_PINS
101981. DLN2_GPIO_PIN_DISABLE
101982. DLN2_GPIO_PIN_ENABLE
101983. DLN2_GPIO_PIN_GET_DIRECTION
101984. DLN2_GPIO_PIN_GET_EVENT_CFG
101985. DLN2_GPIO_PIN_GET_OUT_VAL
101986. DLN2_GPIO_PIN_GET_VAL
101987. DLN2_GPIO_PIN_SET_DIRECTION
101988. DLN2_GPIO_PIN_SET_EVENT_CFG
101989. DLN2_GPIO_PIN_SET_OUT_VAL
101990. DLN2_GPIO_PORT_GET_VAL
101991. DLN2_GPIO_SET_DEBOUNCE
101992. DLN2_HANDLES
101993. DLN2_HANDLE_CTRL
101994. DLN2_HANDLE_EVENT
101995. DLN2_HANDLE_GPIO
101996. DLN2_HANDLE_I2C
101997. DLN2_HANDLE_SPI
101998. DLN2_HW_ID
101999. DLN2_I2C_BUF_SIZE
102000. DLN2_I2C_CMD
102001. DLN2_I2C_DISABLE
102002. DLN2_I2C_ENABLE
102003. DLN2_I2C_GET_MAX_REPLY_COUNT
102004. DLN2_I2C_GET_PORT_COUNT
102005. DLN2_I2C_IS_ENABLED
102006. DLN2_I2C_MAX_XFER_SIZE
102007. DLN2_I2C_MODULE_ID
102008. DLN2_I2C_PULLUP_DISABLE
102009. DLN2_I2C_PULLUP_ENABLE
102010. DLN2_I2C_PULLUP_IS_ENABLED
102011. DLN2_I2C_READ
102012. DLN2_I2C_SCAN_DEVICES
102013. DLN2_I2C_SET_MAX_REPLY_COUNT
102014. DLN2_I2C_TRANSFER
102015. DLN2_I2C_WRITE
102016. DLN2_MAX_RX_SLOTS
102017. DLN2_MAX_URBS
102018. DLN2_RPM_AUTOSUSPEND_TIMEOUT
102019. DLN2_RX_BUF_SIZE
102020. DLN2_SPI_ATTR_LEAVE_SS_LOW
102021. DLN2_SPI_BUF_SIZE
102022. DLN2_SPI_CMD
102023. DLN2_SPI_DISABLE
102024. DLN2_SPI_ENABLE
102025. DLN2_SPI_GET_CPHA
102026. DLN2_SPI_GET_CPOL
102027. DLN2_SPI_GET_DELAY_AFTER_SS
102028. DLN2_SPI_GET_DELAY_BETWEEN_FRAMES
102029. DLN2_SPI_GET_DELAY_BETWEEN_SS
102030. DLN2_SPI_GET_FRAME_SIZE
102031. DLN2_SPI_GET_FREQUENCY
102032. DLN2_SPI_GET_MAX_DELAY_AFTER_SS
102033. DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES
102034. DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS
102035. DLN2_SPI_GET_MAX_FREQUENCY
102036. DLN2_SPI_GET_MIN_DELAY_AFTER_SS
102037. DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES
102038. DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS
102039. DLN2_SPI_GET_MIN_FREQUENCY
102040. DLN2_SPI_GET_MODE
102041. DLN2_SPI_GET_PORT_COUNT
102042. DLN2_SPI_GET_SS
102043. DLN2_SPI_GET_SS_COUNT
102044. DLN2_SPI_GET_SUPPORTED_CPHA_VALUES
102045. DLN2_SPI_GET_SUPPORTED_CPOL_VALUES
102046. DLN2_SPI_GET_SUPPORTED_FRAME_SIZES
102047. DLN2_SPI_GET_SUPPORTED_MODES
102048. DLN2_SPI_IS_ENABLED
102049. DLN2_SPI_MAX_XFER_SIZE
102050. DLN2_SPI_MODULE_ID
102051. DLN2_SPI_READ
102052. DLN2_SPI_READ_WRITE
102053. DLN2_SPI_RELEASE_SS
102054. DLN2_SPI_SET_CPHA
102055. DLN2_SPI_SET_CPOL
102056. DLN2_SPI_SET_DELAY_AFTER_SS
102057. DLN2_SPI_SET_DELAY_BETWEEN_FRAMES
102058. DLN2_SPI_SET_DELAY_BETWEEN_SS
102059. DLN2_SPI_SET_FRAME_SIZE
102060. DLN2_SPI_SET_FREQUENCY
102061. DLN2_SPI_SET_MODE
102062. DLN2_SPI_SET_SS
102063. DLN2_SPI_SS_AAT_DISABLE
102064. DLN2_SPI_SS_AAT_ENABLE
102065. DLN2_SPI_SS_AAT_IS_ENABLED
102066. DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE
102067. DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE
102068. DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED
102069. DLN2_SPI_SS_MULTI_DISABLE
102070. DLN2_SPI_SS_MULTI_ENABLE
102071. DLN2_SPI_SS_MULTI_IS_ENABLED
102072. DLN2_SPI_SS_VARIABLE_DISABLE
102073. DLN2_SPI_SS_VARIABLE_ENABLE
102074. DLN2_SPI_SS_VARIABLE_IS_ENABLED
102075. DLN2_SPI_WRITE
102076. DLN2_TRANSFERS_CANCEL
102077. DLN2_TRANSFERS_WAIT_COMPLETE
102078. DLN2_USB_TIMEOUT
102079. DLNKTST
102080. DLOAD_FLAG_VER_MASK
102081. DLOAD_FLAG_VER_SHIFT
102082. DLOAD_HANDLER_VER
102083. DLOCK
102084. DLO_GB16
102085. DLO_RG16
102086. DLO_RGB8
102087. DLO_RGB_GETBLU
102088. DLO_RGB_GETGRN
102089. DLO_RGB_GETRED
102090. DLPAR_KOBJ_NAME
102091. DLPAR_MEM_ADD
102092. DLPAR_MEM_REM
102093. DLPAR_MODULE_NAME
102094. DLPAR_PORT_ADD_REM
102095. DLR
102096. DLR_ASSIST_ENABLE
102097. DLR_BACKUP_AUTO_ON
102098. DLR_BEACON_TX_ENABLE
102099. DLR_FRAME_QID_M
102100. DLR_NODE_STATE_FAULT
102101. DLR_NODE_STATE_IDLE
102102. DLR_NODE_STATE_M
102103. DLR_NODE_STATE_NORMAL
102104. DLR_NODE_STATE_S
102105. DLR_RESET_SEQ_ID
102106. DLR_RING_STATE_FAULT
102107. DLR_RING_STATE_NORMAL
102108. DLR_SRC_PORT_BOTH
102109. DLR_SRC_PORT_EACH
102110. DLR_SRC_PORT_M
102111. DLR_SRC_PORT_UNICAST
102112. DLR_TIMEOUT_WINDOW_M
102113. DLR_VLAN_ID_M
102114. DLST
102115. DLSTATUS_PHYLINKUP
102116. DLSTS
102117. DLSTS_RLD_ADONE
102118. DLVRY_QUEUE_ENABLE
102119. DLVRY_Q_0_BASE_ADDR_HI
102120. DLVRY_Q_0_BASE_ADDR_LO
102121. DLVRY_Q_0_DEPTH
102122. DLVRY_Q_0_RD_PTR
102123. DLVRY_Q_0_WR_PTR
102124. DLYCTR
102125. DLY_INT_A
102126. DLY_INT_A_BITS
102127. DLY_INT_A_R0
102128. DLY_INT_A_R1
102129. DLY_INT_A_R2
102130. DLY_INT_A_R3
102131. DLY_INT_A_T0
102132. DLY_INT_A_T1
102133. DLY_INT_A_T2
102134. DLY_INT_A_T3
102135. DLY_INT_B
102136. DLY_INT_B_BITS
102137. DLY_INT_B_R0
102138. DLY_INT_B_R1
102139. DLY_INT_B_R2
102140. DLY_INT_B_R3
102141. DLY_INT_B_T0
102142. DLY_INT_B_T1
102143. DLY_INT_B_T2
102144. DLY_INT_B_T3
102145. DL_2_CH1_SATURATION_EN_CTL_MASK
102146. DL_2_CH1_SATURATION_EN_CTL_MASK_SFT
102147. DL_2_CH1_SATURATION_EN_CTL_SFT
102148. DL_2_CH2_SATURATION_EN_CTL_MASK
102149. DL_2_CH2_SATURATION_EN_CTL_MASK_SFT
102150. DL_2_CH2_SATURATION_EN_CTL_SFT
102151. DL_2_FADEIN_0START_EN_MASK
102152. DL_2_FADEIN_0START_EN_MASK_SFT
102153. DL_2_FADEIN_0START_EN_SFT
102154. DL_2_GAIN_CTL_PRE_MASK
102155. DL_2_GAIN_CTL_PRE_MASK_SFT
102156. DL_2_GAIN_CTL_PRE_SFT
102157. DL_2_GAIN_MODE_CTL_MASK
102158. DL_2_GAIN_MODE_CTL_MASK_SFT
102159. DL_2_GAIN_MODE_CTL_SFT
102160. DL_2_GAIN_ON_CTL_PRE_MASK
102161. DL_2_GAIN_ON_CTL_PRE_MASK_SFT
102162. DL_2_GAIN_ON_CTL_PRE_SFT
102163. DL_2_IIRMODE_CTL_PRE_MASK
102164. DL_2_IIRMODE_CTL_PRE_MASK_SFT
102165. DL_2_IIRMODE_CTL_PRE_SFT
102166. DL_2_IIR_ON_CTL_PRE_MASK
102167. DL_2_IIR_ON_CTL_PRE_MASK_SFT
102168. DL_2_IIR_ON_CTL_PRE_SFT
102169. DL_2_INPUT_MODE_CTL_MASK
102170. DL_2_INPUT_MODE_CTL_MASK_SFT
102171. DL_2_INPUT_MODE_CTL_SFT
102172. DL_2_MUTE_CH1_OFF_CTL_PRE_MASK
102173. DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT
102174. DL_2_MUTE_CH1_OFF_CTL_PRE_SFT
102175. DL_2_MUTE_CH2_OFF_CTL_PRE_MASK
102176. DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT
102177. DL_2_MUTE_CH2_OFF_CTL_PRE_SFT
102178. DL_2_OUTPUT_SEL_CTL_MASK
102179. DL_2_OUTPUT_SEL_CTL_MASK_SFT
102180. DL_2_OUTPUT_SEL_CTL_SFT
102181. DL_2_SIDE_TONE_ON_CTL_PRE_MASK
102182. DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT
102183. DL_2_SIDE_TONE_ON_CTL_PRE_SFT
102184. DL_2_SRC_ON_TMP_CTL_PRE_MASK
102185. DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT
102186. DL_2_SRC_ON_TMP_CTL_PRE_SFT
102187. DL_2_VOICE_MODE_CTL_PRE_MASK
102188. DL_2_VOICE_MODE_CTL_PRE_MASK_SFT
102189. DL_2_VOICE_MODE_CTL_PRE_SFT
102190. DL_ADD_VALID_FLAGS
102191. DL_AFC0CREDITTHRESHOLD
102192. DL_AFC0REQTIMEOUTVAL
102193. DL_AFC1CREDITTHRESHOLD
102194. DL_AFC1REQTIMEOUTVAL
102195. DL_ALIGN_DOWN
102196. DL_ALIGN_UP
102197. DL_BAD_CRC
102198. DL_BAD_HDR
102199. DL_BEGIN
102200. DL_BIT_VALUE_FMW
102201. DL_CHECK_CRC
102202. DL_CTL
102203. DL_CTL_ADDRESS_HIGH
102204. DL_CTL_ADDRESS_LOW
102205. DL_CTL_CONTROL
102206. DL_CTL_DATA
102207. DL_DATA_IND
102208. DL_DATA_REQ
102209. DL_DCS_PORT_A
102210. DL_DCS_PORT_A_AND_C
102211. DL_DCS_PORT_C
102212. DL_DEFER_RESP_OK
102213. DL_DEFIO_WRITE_DELAY
102214. DL_DEFIO_WRITE_DISABLE
102215. DL_DEV_DRIVER_BOUND
102216. DL_DEV_NO_DRIVER
102217. DL_DEV_PROBING
102218. DL_DEV_UNBINDING
102219. DL_DISABLE_HW_CG_CTL_MASK
102220. DL_DISABLE_HW_CG_CTL_MASK_SFT
102221. DL_DISABLE_HW_CG_CTL_SFT
102222. DL_DOWN
102223. DL_END
102224. DL_ERR_DISABLED
102225. DL_ERR_NONE
102226. DL_ERR_SBUS
102227. DL_ERR_SECURITY
102228. DL_ERR_SWAP_PARITY
102229. DL_ERR_XFR_PARITY
102230. DL_ESTABLISH_CNF
102231. DL_ESTABLISH_IND
102232. DL_ESTABLISH_REQ
102233. DL_EXEC
102234. DL_FC0PROTTIMEOUTVAL
102235. DL_FC1PROTTIMEOUTVAL
102236. DL_FLAG_AUTOPROBE_CONSUMER
102237. DL_FLAG_AUTOREMOVE_CONSUMER
102238. DL_FLAG_AUTOREMOVE_SUPPLIER
102239. DL_FLAG_MANAGED
102240. DL_FLAG_PM_RUNTIME
102241. DL_FLAG_RPM_ACTIVE
102242. DL_FLAG_STATELESS
102243. DL_GAIN_0DB
102244. DL_GAIN_8DB
102245. DL_GAIN_N_10DB
102246. DL_GAIN_N_10DB_REG
102247. DL_GAIN_N_1DB
102248. DL_GAIN_N_40DB
102249. DL_GAIN_N_40DB_REG
102250. DL_GAIN_REG_MASK
102251. DL_GETSTATE
102252. DL_GETVER
102253. DL_GO
102254. DL_GO_PROTECTED
102255. DL_IMAGE_TOOBIG
102256. DL_INFORMATION_IND
102257. DL_INFORMATION_REQ
102258. DL_INFO_L2_CONNECT
102259. DL_INFO_L2_REMOVED
102260. DL_INTERN_MSG
102261. DL_MANAGED_LINK_FLAGS
102262. DL_MASK
102263. DL_MAX_TRIES
102264. DL_MODE_ENCRYPT
102265. DL_MODE_KEY_IDX
102266. DL_MODE_NEED_RSP
102267. DL_MODE_RESET_SEC_IV
102268. DL_MODE_WORKING_PDA_CR4
102269. DL_NVRAM_TOOBIG
102270. DL_PEERTC0PRESENT
102271. DL_PEERTC0RXINITCREVAL
102272. DL_PEERTC1PRESENT
102273. DL_PEERTC1RXINITCREVAL
102274. DL_PHY_MASK
102275. DL_READY
102276. DL_REBOOT
102277. DL_RELEASE_CNF
102278. DL_RELEASE_IND
102279. DL_RELEASE_REQ
102280. DL_RESETCFG
102281. DL_RUNNABLE
102282. DL_SCALE
102283. DL_SHIFT
102284. DL_SINE_ON_MASK
102285. DL_SINE_ON_MASK_SFT
102286. DL_SINE_ON_SFT
102287. DL_START
102288. DL_START_FAIL
102289. DL_STATE_ACTIVE
102290. DL_STATE_AVAILABLE
102291. DL_STATE_CONSUMER_PROBE
102292. DL_STATE_DORMANT
102293. DL_STATE_NONE
102294. DL_STATE_SUPPLIER_UNBIND
102295. DL_STATUS_BOTH
102296. DL_STATUS_HFI0
102297. DL_STATUS_HFI1
102298. DL_TC0OUTACKTHRESHOLD
102299. DL_TC0REPLAYTIMEOUTVAL
102300. DL_TC0RXINITCREDITVAL
102301. DL_TC0TXBUFFERSIZE
102302. DL_TC0TXFCTHRESHOLD
102303. DL_TC0TXMAXSDUSIZE
102304. DL_TC1OUTACKTHRESHOLD
102305. DL_TC1REPLAYTIMEOUTVAL
102306. DL_TC1RXINITCREDITVAL
102307. DL_TC1TXBUFFERSIZE
102308. DL_TC1TXFCTHRESHOLD
102309. DL_TC1TXMAXSDUSIZE
102310. DL_TIMER200_IND
102311. DL_TIMER203_IND
102312. DL_TOGGLE_MASK
102313. DL_TXPREEMPTIONCAP
102314. DL_TYPE_CLM
102315. DL_UNITDATA_IND
102316. DL_UNITDATA_REQ
102317. DL_WAITING
102318. DLine
102319. DLinkDSC350
102320. DM
102321. DM0
102322. DM05_LNB_13V
102323. DM05_LNB_18V
102324. DM05_LNB_MASK
102325. DM05_LNB_OFF
102326. DM1
102327. DM1105_BOARD_AXESS_DM05
102328. DM1105_BOARD_DVBWORLD_2002
102329. DM1105_BOARD_DVBWORLD_2004
102330. DM1105_BOARD_NOAUTO
102331. DM1105_BOARD_UNBRANDED_I2C_ON_GPIO
102332. DM1105_BOARD_UNKNOWN
102333. DM1105_CR
102334. DM1105_CWSEL
102335. DM1105_DMA_BYTES
102336. DM1105_DMA_PACKETS
102337. DM1105_DMA_PACKET_LENGTH
102338. DM1105_DTALENTH
102339. DM1105_ENCRYPT
102340. DM1105_EVEN
102341. DM1105_GPIOCTR
102342. DM1105_GPIOVAL
102343. DM1105_HOST_AD
102344. DM1105_HOST_CTR
102345. DM1105_I2CCTR
102346. DM1105_I2CDAT
102347. DM1105_I2CSTS
102348. DM1105_I2C_GPIO_NAME
102349. DM1105_I2C_RA
102350. DM1105_INTCNT
102351. DM1105_INTMAK
102352. DM1105_INTSTS
102353. DM1105_IRCODE
102354. DM1105_IRCTR
102355. DM1105_IRMODE
102356. DM1105_IR_EN
102357. DM1105_LNB_13V
102358. DM1105_LNB_18V
102359. DM1105_LNB_MASK
102360. DM1105_LNB_OFF
102361. DM1105_MAX
102362. DM1105_ODD
102363. DM1105_PID
102364. DM1105_PIDN
102365. DM1105_REP_FLG
102366. DM1105_RLEN
102367. DM1105_RST
102368. DM1105_STADR
102369. DM1105_SYSTEMCODE
102370. DM1105_SYS_CHK
102371. DM1105_TSCTR
102372. DM1105_VER
102373. DM1105_WRP
102374. DM1_CIDPLANES
102375. DM1_NOPLANES
102376. DM1_OLAYPLANES
102377. DM1_PLANES
102378. DM1_PUPPLANES
102379. DM1_RGBAPLANES
102380. DM1_RGBPLANES
102381. DM2
102382. DM3
102383. DM355
102384. DM355EVM_MSP_COMMAND
102385. DM355EVM_MSP_FIRMREV
102386. DM355EVM_MSP_INPUT_COUNT
102387. DM355EVM_MSP_INPUT_HIGH
102388. DM355EVM_MSP_INPUT_LOW
102389. DM355EVM_MSP_LED
102390. DM355EVM_MSP_RESET
102391. DM355EVM_MSP_RTC_0
102392. DM355EVM_MSP_RTC_1
102393. DM355EVM_MSP_RTC_2
102394. DM355EVM_MSP_RTC_3
102395. DM355EVM_MSP_SDMMC
102396. DM355EVM_MSP_STATUS
102397. DM355EVM_MSP_SWITCH1
102398. DM355EVM_MSP_SWITCH2
102399. DM355EVM_MSP_VIDEO_IN
102400. DM355_ASYNC_EMIF_CONTROL_BASE
102401. DM355_ASYNC_EMIF_DATA_CE0_BASE
102402. DM355_DEEPSLEEP
102403. DM355_DEEPSLEEP_PADDR
102404. DM355_EVT26_MMC0_RX
102405. DM355_EVT8_ASP1_TX
102406. DM355_EVT9_ASP1_RX
102407. DM355_I2C_SCL
102408. DM355_I2C_SCL_PIN
102409. DM355_I2C_SDA
102410. DM355_I2C_SDA_PIN
102411. DM355_INT_EDMA_CC
102412. DM355_INT_EDMA_TC0_ERR
102413. DM355_INT_EDMA_TC1_ERR
102414. DM355_LPSC_MMC_SD1
102415. DM355_LPSC_McBSP1
102416. DM355_LPSC_PWM3
102417. DM355_LPSC_RTO
102418. DM355_LPSC_SPI1
102419. DM355_LPSC_SPI2
102420. DM355_LPSC_TIMER3
102421. DM355_LPSC_VPSS_DAC
102422. DM355_MCBSP0_BDR
102423. DM355_MCBSP0_BDX
102424. DM355_MCBSP0_BFSR
102425. DM355_MCBSP0_BFSX
102426. DM355_MCBSP0_R
102427. DM355_MCBSP0_X
102428. DM355_MMCSD0
102429. DM355_MMCSD0_BASE
102430. DM355_MMCSD1_BASE
102431. DM355_OSD_BASE
102432. DM355_REF_FREQ
102433. DM355_SD1_CLK
102434. DM355_SD1_CMD
102435. DM355_SD1_DATA0
102436. DM355_SD1_DATA1
102437. DM355_SD1_DATA2
102438. DM355_SD1_DATA3
102439. DM355_SPI0_SDENA0
102440. DM355_SPI0_SDENA1
102441. DM355_SPI0_SDI
102442. DM355_UART2_BASE
102443. DM355_VENC_BASE
102444. DM355_VIN_CAM_HD
102445. DM355_VIN_CAM_VD
102446. DM355_VIN_CAM_WEN
102447. DM355_VIN_CINH_EN
102448. DM355_VIN_CINL_EN
102449. DM355_VIN_PCLK
102450. DM355_VIN_YIN_EN
102451. DM355_VOUT_COUTH_EN
102452. DM355_VOUT_COUTL_EN
102453. DM355_VOUT_FIELD
102454. DM355_VOUT_FIELD_G70
102455. DM355_VOUT_HVSYNC
102456. DM355_VPBE_OSD_SUBDEV_NAME
102457. DM355_VPBE_VENC_SUBDEV_NAME
102458. DM355_VPSSBL_CCDCMUX
102459. DM355_VPSSBL_EVTSEL
102460. DM355_VPSSBL_EVTSEL_DEFAULT
102461. DM355_VPSSBL_INTSEL
102462. DM355_VPSSBL_INTSEL_DEFAULT
102463. DM355_VPSSCLK_CLKCTRL
102464. DM365
102465. DM365_AEMIF_A3
102466. DM365_AEMIF_A7
102467. DM365_AEMIF_AR_A14
102468. DM365_AEMIF_AR_BA0
102469. DM365_AEMIF_CE0
102470. DM365_AEMIF_CE1
102471. DM365_AEMIF_D15_8
102472. DM365_AEMIF_WE_OE
102473. DM365_ASYNC_EMIF_CONTROL_BASE
102474. DM365_ASYNC_EMIF_DATA_CE0_BASE
102475. DM365_ASYNC_EMIF_DATA_CE1_BASE
102476. DM365_CCDC_PG_HD_POL_SHIFT
102477. DM365_CCDC_PG_VD_POL_SHIFT
102478. DM365_CLKOUT0
102479. DM365_CLKOUT1
102480. DM365_CLKOUT2
102481. DM365_EMAC_BASE
102482. DM365_EMAC_CNTRL_MOD_OFFSET
102483. DM365_EMAC_CNTRL_OFFSET
102484. DM365_EMAC_CNTRL_RAM_OFFSET
102485. DM365_EMAC_CNTRL_RAM_SIZE
102486. DM365_EMAC_COL
102487. DM365_EMAC_CRS
102488. DM365_EMAC_MDCLK
102489. DM365_EMAC_MDIO
102490. DM365_EMAC_MDIO_BASE
102491. DM365_EMAC_RXD0
102492. DM365_EMAC_RXD1
102493. DM365_EMAC_RXD2
102494. DM365_EMAC_RXD3
102495. DM365_EMAC_RX_CLK
102496. DM365_EMAC_RX_DV
102497. DM365_EMAC_RX_ER
102498. DM365_EMAC_TXD0
102499. DM365_EMAC_TXD1
102500. DM365_EMAC_TXD2
102501. DM365_EMAC_TXD3
102502. DM365_EMAC_TX_CLK
102503. DM365_EMAC_TX_EN
102504. DM365_EVM_PHY_ID
102505. DM365_EVT26_MMC0_RX
102506. DM365_EVT2_ASP_TX
102507. DM365_EVT2_VC_TX
102508. DM365_EVT3_ASP_RX
102509. DM365_EVT3_VC_RX
102510. DM365_GPIO20
102511. DM365_GPIO30
102512. DM365_GPIO31
102513. DM365_GPIO32
102514. DM365_GPIO33
102515. DM365_GPIO40
102516. DM365_GPIO64_57
102517. DM365_I2C_SCL
102518. DM365_I2C_SDA
102519. DM365_INT_EDMA_CC
102520. DM365_INT_EDMA_TC0_ERR
102521. DM365_INT_EDMA_TC1_ERR
102522. DM365_INT_EDMA_TC2_ERR
102523. DM365_INT_EDMA_TC3_ERR
102524. DM365_INT_EMAC_MISCPULSE
102525. DM365_INT_EMAC_RXPULSE
102526. DM365_INT_EMAC_RXTHRESH
102527. DM365_INT_EMAC_TXPULSE
102528. DM365_INT_HDVICP_DISABLE
102529. DM365_INT_HDVICP_ENABLE
102530. DM365_INT_IMX0_DISABLE
102531. DM365_INT_IMX0_ENABLE
102532. DM365_INT_IMX1_DISABLE
102533. DM365_INT_IMX1_ENABLE
102534. DM365_INT_NSF_DISABLE
102535. DM365_INT_NSF_ENABLE
102536. DM365_INT_PRTCSS
102537. DM365_ISP5_BCR
102538. DM365_ISP5_BCR_ISIF_OUT_ENABLE
102539. DM365_ISP5_CCDCMUX
102540. DM365_ISP5_INTSEL1
102541. DM365_ISP5_INTSEL1_DEFAULT
102542. DM365_ISP5_INTSEL2
102543. DM365_ISP5_INTSEL2_DEFAULT
102544. DM365_ISP5_INTSEL3
102545. DM365_ISP5_INTSEL3_DEFAULT
102546. DM365_ISP5_PCCR
102547. DM365_ISP5_PCCR_BL_CLK_ENABLE
102548. DM365_ISP5_PCCR_H3A_CLK_ENABLE
102549. DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE
102550. DM365_ISP5_PCCR_IPIPE_CLK_ENABLE
102551. DM365_ISP5_PCCR_ISIF_CLK_ENABLE
102552. DM365_ISP5_PCCR_RSV
102553. DM365_ISP5_PCCR_RSZ_CLK_ENABLE
102554. DM365_ISP5_PG_FRAME_SIZE
102555. DM365_KEYSCAN
102556. DM365_KEYSCAN_BASE
102557. DM365_LPSC_DAC_CLK
102558. DM365_LPSC_EMAC
102559. DM365_LPSC_MJCP
102560. DM365_LPSC_MMC_SD1
102561. DM365_LPSC_McBSP1
102562. DM365_LPSC_PWM3
102563. DM365_LPSC_RTO
102564. DM365_LPSC_SPI0
102565. DM365_LPSC_SPI1
102566. DM365_LPSC_SPI2
102567. DM365_LPSC_SPI3
102568. DM365_LPSC_SPI4
102569. DM365_LPSC_TIMER3
102570. DM365_LPSC_TIMER4
102571. DM365_LPSC_VOICE_CODEC
102572. DM365_LPSC_VPSSMSTR
102573. DM365_MCBSP0_BDR
102574. DM365_MCBSP0_BDX
102575. DM365_MCBSP0_BFSR
102576. DM365_MCBSP0_BFSX
102577. DM365_MCBSP0_R
102578. DM365_MCBSP0_X
102579. DM365_MMCSD0
102580. DM365_MMCSD0_BASE
102581. DM365_MMCSD1_BASE
102582. DM365_OSD_BASE
102583. DM365_PWM0
102584. DM365_PWM0_G23
102585. DM365_PWM1
102586. DM365_PWM1_G25
102587. DM365_PWM2_G87
102588. DM365_PWM2_G88
102589. DM365_PWM2_G89
102590. DM365_PWM2_G90
102591. DM365_PWM3_G80
102592. DM365_PWM3_G81
102593. DM365_PWM3_G85
102594. DM365_PWM3_G86
102595. DM365_REF_FREQ
102596. DM365_RTC_BASE
102597. DM365_SD1_CLK
102598. DM365_SD1_CMD
102599. DM365_SD1_DATA0
102600. DM365_SD1_DATA1
102601. DM365_SD1_DATA2
102602. DM365_SD1_DATA3
102603. DM365_SPI0_SCLK
102604. DM365_SPI0_SDENA0
102605. DM365_SPI0_SDENA1
102606. DM365_SPI0_SDI
102607. DM365_SPI0_SDO
102608. DM365_SPI1_SCLK
102609. DM365_SPI1_SDENA0
102610. DM365_SPI1_SDENA1
102611. DM365_SPI1_SDI
102612. DM365_SPI1_SDO
102613. DM365_SPI2_SCLK
102614. DM365_SPI2_SDENA0
102615. DM365_SPI2_SDENA1
102616. DM365_SPI2_SDI
102617. DM365_SPI2_SDO
102618. DM365_SPI3_SCLK
102619. DM365_SPI3_SDENA0
102620. DM365_SPI3_SDENA1
102621. DM365_SPI3_SDI
102622. DM365_SPI3_SDO
102623. DM365_SPI4_SCLK
102624. DM365_SPI4_SDENA0
102625. DM365_SPI4_SDENA1
102626. DM365_SPI4_SDI
102627. DM365_SPI4_SDO
102628. DM365_UART0_RXD
102629. DM365_UART0_TXD
102630. DM365_UART1_BASE
102631. DM365_UART1_CTS
102632. DM365_UART1_RTS
102633. DM365_UART1_RXD
102634. DM365_UART1_TXD
102635. DM365_VENC_BASE
102636. DM365_VIN_CAM_HD
102637. DM365_VIN_CAM_VD
102638. DM365_VIN_CAM_WEN
102639. DM365_VIN_YIN0_3_EN
102640. DM365_VIN_YIN4_7_EN
102641. DM365_VOUT_COUTH_EN
102642. DM365_VOUT_COUTL_EN
102643. DM365_VOUT_FIELD
102644. DM365_VOUT_FIELD_G81
102645. DM365_VOUT_HVSYNC
102646. DM365_VPBE_CLK_CTRL
102647. DM365_VPBE_OSD_SUBDEV_NAME
102648. DM365_VPBE_VENC_SUBDEV_NAME
102649. DM644X
102650. DM644X_AEAW
102651. DM644X_AEAW0
102652. DM644X_AEAW1
102653. DM644X_AEAW2
102654. DM644X_AEAW3
102655. DM644X_AEAW4
102656. DM644X_ASYNC_EMIF_CONTROL_BASE
102657. DM644X_ASYNC_EMIF_DATA_CE0_BASE
102658. DM644X_ASYNC_EMIF_DATA_CE1_BASE
102659. DM644X_ASYNC_EMIF_DATA_CE2_BASE
102660. DM644X_ASYNC_EMIF_DATA_CE3_BASE
102661. DM644X_ATAEN
102662. DM644X_ATAEN_DISABLE
102663. DM644X_EMACEN
102664. DM644X_EMAC_BASE
102665. DM644X_EMAC_CNTRL_MOD_OFFSET
102666. DM644X_EMAC_CNTRL_OFFSET
102667. DM644X_EMAC_CNTRL_RAM_OFFSET
102668. DM644X_EMAC_CNTRL_RAM_SIZE
102669. DM644X_EMAC_MDIO_BASE
102670. DM644X_EVM_PHY_ID
102671. DM644X_GPIO0
102672. DM644X_GPIO3
102673. DM644X_GPIO3V
102674. DM644X_GPIO43_44
102675. DM644X_GPIO46_47
102676. DM644X_HDIREN
102677. DM644X_HPIEN_DISABLE
102678. DM644X_I2C
102679. DM644X_I2C_SCL_PIN
102680. DM644X_I2C_SDA_PIN
102681. DM644X_LFLDEN
102682. DM644X_LOEEN
102683. DM644X_MCBSP
102684. DM644X_MSTK
102685. DM644X_OSD_BASE
102686. DM644X_PWM0
102687. DM644X_PWM1
102688. DM644X_PWM2
102689. DM644X_REF_FREQ
102690. DM644X_RGB666
102691. DM644X_SBL_PCR_VPSS
102692. DM644X_UART1
102693. DM644X_UART2
102694. DM644X_VENC_BASE
102695. DM644X_VLSCREN
102696. DM644X_VLYNQEN
102697. DM644X_VLYNQWD
102698. DM644X_VPBE_OSD_SUBDEV_NAME
102699. DM644X_VPBE_VENC_SUBDEV_NAME
102700. DM644X_VPSS_BASE
102701. DM644X_VPSS_DACCLKEN
102702. DM644X_VPSS_MUXSEL_PLL2_MODE
102703. DM644X_VPSS_MUXSEL_VPBECLK_MODE
102704. DM644X_VPSS_VENCLKEN
102705. DM6467T_EVM_REF_FREQ
102706. DM646X_ASYNC_EMIF_CONTROL_BASE
102707. DM646X_ASYNC_EMIF_CS2_SPACE_BASE
102708. DM646X_ATAEN
102709. DM646X_AUDCK0
102710. DM646X_AUDCK1
102711. DM646X_AUX_FREQ
102712. DM646X_CRGMUX
102713. DM646X_EMAC_BASE
102714. DM646X_EMAC_CNTRL_MOD_OFFSET
102715. DM646X_EMAC_CNTRL_OFFSET
102716. DM646X_EMAC_CNTRL_RAM_OFFSET
102717. DM646X_EMAC_CNTRL_RAM_SIZE
102718. DM646X_EMAC_MDIO_BASE
102719. DM646X_EVM_ATA_PWD
102720. DM646X_EVM_ATA_RST
102721. DM646X_EVM_PHY_ID
102722. DM646X_LPSC_AEMIF
102723. DM646X_LPSC_ARM
102724. DM646X_LPSC_ARM_INTC
102725. DM646X_LPSC_C64X_CPU
102726. DM646X_LPSC_CRGEN0
102727. DM646X_LPSC_CRGEN1
102728. DM646X_LPSC_DDR_EMIF
102729. DM646X_LPSC_EMAC
102730. DM646X_LPSC_GPIO
102731. DM646X_LPSC_HDVICP0
102732. DM646X_LPSC_HDVICP1
102733. DM646X_LPSC_I2C
102734. DM646X_LPSC_McASP0
102735. DM646X_LPSC_McASP1
102736. DM646X_LPSC_PCI
102737. DM646X_LPSC_PWM0
102738. DM646X_LPSC_PWM1
102739. DM646X_LPSC_SPI
102740. DM646X_LPSC_TIMER0
102741. DM646X_LPSC_TIMER1
102742. DM646X_LPSC_TPCC
102743. DM646X_LPSC_TPTC0
102744. DM646X_LPSC_TPTC1
102745. DM646X_LPSC_TPTC2
102746. DM646X_LPSC_TPTC3
102747. DM646X_LPSC_TSIF0
102748. DM646X_LPSC_TSIF1
102749. DM646X_LPSC_UART0
102750. DM646X_LPSC_UART1
102751. DM646X_LPSC_UART2
102752. DM646X_LPSC_VDCE
102753. DM646X_LPSC_VPSSMSTR
102754. DM646X_LPSC_VPSSSLV
102755. DM646X_PTSIMUX_DISABLE
102756. DM646X_PTSIMUX_PARALLEL
102757. DM646X_PTSIMUX_SERIAL
102758. DM646X_PTSOMUX_DISABLE
102759. DM646X_PTSOMUX_PARALLEL
102760. DM646X_PTSOMUX_SERIAL
102761. DM646X_REF_FREQ
102762. DM646X_STSIMUX
102763. DM646X_STSIMUX_DISABLE
102764. DM646X_STSOMUX
102765. DM646X_STSOMUX_DISABLE
102766. DM6_AUX1PARTITION
102767. DM6_AUX3PARTITION
102768. DM6_PARTITION
102769. DM814X_CM_ALWON_ATL_CLKCTRL
102770. DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL
102771. DM814X_CM_ALWON_DCAN_0_1_CLKCTRL
102772. DM814X_CM_ALWON_DEBUGSS_CLKCTRL
102773. DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL
102774. DM814X_CM_ALWON_MLB_CLKCTRL
102775. DM814X_CM_ALWON_MMCHS_0_CLKCTRL
102776. DM814X_CM_ALWON_MMCHS_1_CLKCTRL
102777. DM814X_CM_ALWON_MMCHS_2_CLKCTRL
102778. DM814X_CM_ALWON_MPU_CLKCTRL
102779. DM814X_CM_ALWON_OCM_0_CLKCTRL
102780. DM814X_CM_ALWON_PATA_CLKCTRL
102781. DM814X_CM_ALWON_UART_3_CLKCTRL
102782. DM814X_CM_ALWON_UART_4_CLKCTRL
102783. DM814X_CM_ALWON_UART_5_CLKCTRL
102784. DM814X_CM_ALWON_VCP_CLKCTRL
102785. DM814X_IOPAD
102786. DM814_CLKCTRL_INDEX
102787. DM814_CLKCTRL_OFFSET
102788. DM814_CPGMAC0_CLKCTRL
102789. DM814_GPIO1_CLKCTRL
102790. DM814_GPIO2_CLKCTRL
102791. DM814_GPMC_CLKCTRL
102792. DM814_I2C1_CLKCTRL
102793. DM814_I2C2_CLKCTRL
102794. DM814_MCSPI1_CLKCTRL
102795. DM814_MMC1_CLKCTRL
102796. DM814_MMC2_CLKCTRL
102797. DM814_MMC3_CLKCTRL
102798. DM814_MPU_CLKCTRL
102799. DM814_RTC_CLKCTRL
102800. DM814_TPCC_CLKCTRL
102801. DM814_TPTC0_CLKCTRL
102802. DM814_TPTC1_CLKCTRL
102803. DM814_TPTC2_CLKCTRL
102804. DM814_TPTC3_CLKCTRL
102805. DM814_UART1_CLKCTRL
102806. DM814_UART2_CLKCTRL
102807. DM814_UART3_CLKCTRL
102808. DM814_USB_OTG_HS_CLKCTRL
102809. DM814_WD_TIMER_CLKCTRL
102810. DM816X_CM_ALWON_ETHERNET_1_CLKCTRL
102811. DM816X_CM_ALWON_MPU_CLKCTRL
102812. DM816X_CM_ALWON_OCMC_0_CLKCTRL
102813. DM816X_CM_ALWON_OCMC_1_CLKCTRL
102814. DM816X_CM_ALWON_SDIO_CLKCTRL
102815. DM816X_CM_ALWON_SR_0_CLKCTRL
102816. DM816X_CM_ALWON_SR_1_CLKCTRL
102817. DM816X_CM_ALWON_TIMER_1_CLKCTRL
102818. DM816X_CM_ALWON_TIMER_2_CLKCTRL
102819. DM816X_CM_ALWON_TIMER_3_CLKCTRL
102820. DM816X_CM_ALWON_TIMER_4_CLKCTRL
102821. DM816X_CM_ALWON_TIMER_5_CLKCTRL
102822. DM816X_CM_ALWON_TIMER_6_CLKCTRL
102823. DM816X_CM_ALWON_TIMER_7_CLKCTRL
102824. DM816X_DM_ALWON_BASE
102825. DM816X_IOPAD
102826. DM816X_USBPHY_CTRL_TXPREEMTUNE
102827. DM816X_USBPHY_CTRL_TXRISETUNE
102828. DM816X_USBPHY_CTRL_TXVREFTUNE
102829. DM816X_USB_CTRL_PHYCLKSRC
102830. DM816X_USB_CTRL_PHYSLEEP0
102831. DM816X_USB_CTRL_PHYSLEEP1
102832. DM816_CLKCTRL_INDEX
102833. DM816_CLKCTRL_OFFSET
102834. DM816_DAVINCI_MDIO_CLKCTRL
102835. DM816_EMAC1_CLKCTRL
102836. DM816_GPIO1_CLKCTRL
102837. DM816_GPIO2_CLKCTRL
102838. DM816_GPMC_CLKCTRL
102839. DM816_I2C1_CLKCTRL
102840. DM816_I2C2_CLKCTRL
102841. DM816_MAILBOX_CLKCTRL
102842. DM816_MCSPI1_CLKCTRL
102843. DM816_MMC1_CLKCTRL
102844. DM816_MPU_CLKCTRL
102845. DM816_RTC_CLKCTRL
102846. DM816_SPINBOX_CLKCTRL
102847. DM816_TIMER1_CLKCTRL
102848. DM816_TIMER2_CLKCTRL
102849. DM816_TIMER3_CLKCTRL
102850. DM816_TIMER4_CLKCTRL
102851. DM816_TIMER5_CLKCTRL
102852. DM816_TIMER6_CLKCTRL
102853. DM816_TIMER7_CLKCTRL
102854. DM816_TPCC_CLKCTRL
102855. DM816_TPTC0_CLKCTRL
102856. DM816_TPTC1_CLKCTRL
102857. DM816_TPTC2_CLKCTRL
102858. DM816_TPTC3_CLKCTRL
102859. DM816_UART1_CLKCTRL
102860. DM816_UART2_CLKCTRL
102861. DM816_UART3_CLKCTRL
102862. DM816_USB_OTG_HS_CLKCTRL
102863. DM816_WD_TIMER_CLKCTRL
102864. DM81XX_CM_ALWON_CONTROL_CLKCTRL
102865. DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL
102866. DM81XX_CM_ALWON_GPIO_0_CLKCTRL
102867. DM81XX_CM_ALWON_GPIO_1_CLKCTRL
102868. DM81XX_CM_ALWON_GPMC_CLKCTRL
102869. DM81XX_CM_ALWON_I2C_0_CLKCTRL
102870. DM81XX_CM_ALWON_I2C_1_CLKCTRL
102871. DM81XX_CM_ALWON_L3_CLKCTRL
102872. DM81XX_CM_ALWON_L4HS_CLKCTRL
102873. DM81XX_CM_ALWON_L4LS_CLKCTRL
102874. DM81XX_CM_ALWON_MAILBOX_CLKCTRL
102875. DM81XX_CM_ALWON_MCASP0_CLKCTRL
102876. DM81XX_CM_ALWON_MCASP1_CLKCTRL
102877. DM81XX_CM_ALWON_MCASP2_CLKCTRL
102878. DM81XX_CM_ALWON_MCBSP_CLKCTRL
102879. DM81XX_CM_ALWON_MMUCFG_CLKCTRL
102880. DM81XX_CM_ALWON_MMUDATA_CLKCTRL
102881. DM81XX_CM_ALWON_RTC_CLKCTRL
102882. DM81XX_CM_ALWON_SPINBOX_CLKCTRL
102883. DM81XX_CM_ALWON_SPI_CLKCTRL
102884. DM81XX_CM_ALWON_TPCC_CLKCTRL
102885. DM81XX_CM_ALWON_TPTC0_CLKCTRL
102886. DM81XX_CM_ALWON_TPTC1_CLKCTRL
102887. DM81XX_CM_ALWON_TPTC2_CLKCTRL
102888. DM81XX_CM_ALWON_TPTC3_CLKCTRL
102889. DM81XX_CM_ALWON_UART_0_CLKCTRL
102890. DM81XX_CM_ALWON_UART_1_CLKCTRL
102891. DM81XX_CM_ALWON_UART_2_CLKCTRL
102892. DM81XX_CM_ALWON_WDTIMER_CLKCTRL
102893. DM81XX_CM_DEFAULT_OFFSET
102894. DM81XX_CM_DEFAULT_SATA_CLKCTRL
102895. DM81XX_CM_DEFAULT_USB_CLKCTRL
102896. DM9000_ADDR
102897. DM9000_BPTR
102898. DM9000_CHIPR
102899. DM9000_EPAR
102900. DM9000_EPCR
102901. DM9000_EPDRH
102902. DM9000_EPDRL
102903. DM9000_ETXCSR
102904. DM9000_FCR
102905. DM9000_FCTR
102906. DM9000_GPCR
102907. DM9000_GPR
102908. DM9000_ID
102909. DM9000_IMR
102910. DM9000_IRQ
102911. DM9000_ISR
102912. DM9000_MAR
102913. DM9000_MRCMD
102914. DM9000_MRCMDX
102915. DM9000_MRRH
102916. DM9000_MRRL
102917. DM9000_MWCMD
102918. DM9000_MWCMDX
102919. DM9000_MWRH
102920. DM9000_MWRL
102921. DM9000_NCR
102922. DM9000_NSR
102923. DM9000_PAR
102924. DM9000_PHY
102925. DM9000_PIDH
102926. DM9000_PIDL
102927. DM9000_PKT_ERR
102928. DM9000_PKT_MAX
102929. DM9000_PKT_RDY
102930. DM9000_PLATF_16BITONLY
102931. DM9000_PLATF_32BITONLY
102932. DM9000_PLATF_8BITONLY
102933. DM9000_PLATF_EXT_PHY
102934. DM9000_PLATF_NO_EEPROM
102935. DM9000_PLATF_SIMPLE_PHY
102936. DM9000_RCR
102937. DM9000_RCSR
102938. DM9000_ROCR
102939. DM9000_RSR
102940. DM9000_RWPAH
102941. DM9000_RWPAL
102942. DM9000_SMCR
102943. DM9000_TCCR
102944. DM9000_TCR
102945. DM9000_TRPAH
102946. DM9000_TRPAL
102947. DM9000_TSR1
102948. DM9000_TSR2
102949. DM9000_TXPLH
102950. DM9000_TXPLL
102951. DM9000_VIDH
102952. DM9000_VIDL
102953. DM9000_WCR
102954. DM9102A_IO_SIZE
102955. DM9102_IO_SIZE
102956. DM910X
102957. DM910X_RESET
102958. DM9161_DELAY
102959. DM9801_NOISE_FLOOR
102960. DM9802_NOISE_FLOOR
102961. DM9K_MSC_VALUE
102962. DMA
102963. DMA0CFG
102964. DMA0_ACTIVE
102965. DMA0_BASE_ADDR
102966. DMA0_CHAN_CTRL
102967. DMA0_CHAN_STAT
102968. DMA0_CURRENT_PCL
102969. DMA0_FIFO_SIZE
102970. DMA0_ID
102971. DMA0_PREV_PCL
102972. DMA0_READY
102973. DMA0_REGISTER_OFFSET
102974. DMA0_SHUT
102975. DMA0_WORD0_CMP_ENABLE
102976. DMA0_WORD0_CMP_VALUE
102977. DMA0_WORD1_CMP_ENABLE
102978. DMA0_WORD1_CMP_VALUE
102979. DMA1
102980. DMA10_B_ADDR
102981. DMA10_CNT1
102982. DMA10_CNT2
102983. DMA10_PTR1
102984. DMA10_PTR2
102985. DMA10_P_ADDR
102986. DMA11_CNT1
102987. DMA11_CNT2
102988. DMA11_PTR1
102989. DMA11_PTR2
102990. DMA12_CNT1
102991. DMA12_CNT2
102992. DMA12_PTR1
102993. DMA12_PTR2
102994. DMA13_CNT1
102995. DMA13_CNT2
102996. DMA13_PTR1
102997. DMA13_PTR2
102998. DMA14_CNT1
102999. DMA14_CNT2
103000. DMA14_PTR1
103001. DMA14_PTR2
103002. DMA15_CNT1
103003. DMA15_CNT2
103004. DMA15_PTR1
103005. DMA15_PTR2
103006. DMA16_CNT1
103007. DMA16_CNT2
103008. DMA16_PTR1
103009. DMA16_PTR2
103010. DMA17_CNT1
103011. DMA17_CNT2
103012. DMA17_PTR1
103013. DMA17_PTR2
103014. DMA18_CNT1
103015. DMA18_CNT2
103016. DMA18_PTR1
103017. DMA18_PTR2
103018. DMA19_CNT1
103019. DMA19_CNT2
103020. DMA19_PTR1
103021. DMA19_PTR2
103022. DMA1CFG
103023. DMA1_ACTIVE
103024. DMA1_ALPHA
103025. DMA1_ALPHA_MODE
103026. DMA1_BUSY
103027. DMA1_BUSY_MASK
103028. DMA1_CARRY
103029. DMA1_CHAN_CTRL
103030. DMA1_CHAN_STAT
103031. DMA1_CK
103032. DMA1_CKEY
103033. DMA1_CLEAR_FF_REG
103034. DMA1_CLR_MASK_REG
103035. DMA1_CMD_REG
103036. DMA1_CNT1
103037. DMA1_CNT2
103038. DMA1_CURRENT_PCL
103039. DMA1_DSCALE
103040. DMA1_EXT_MODE_REG
103041. DMA1_EXT_REG
103042. DMA1_FIFO_SIZE
103043. DMA1_FRAME_TRIG
103044. DMA1_GATED_ENA
103045. DMA1_ID
103046. DMA1_LNBUF_ENA
103047. DMA1_MASK_ALL_REG
103048. DMA1_MASK_REG
103049. DMA1_MODE_REG
103050. DMA1_PREV_PCL
103051. DMA1_PTR1
103052. DMA1_PTR2
103053. DMA1_PWRDN_ENA
103054. DMA1_PXLCMD
103055. DMA1_R
103056. DMA1_READY
103057. DMA1_REGISTER_OFFSET
103058. DMA1_REQ_REG
103059. DMA1_RESET_REG
103060. DMA1_SHUT
103061. DMA1_STAT_REG
103062. DMA1_TEMP_REG
103063. DMA1_VSYNC_INV
103064. DMA1_VSYNC_MODE
103065. DMA1_WORD0_CMP_ENABLE
103066. DMA1_WORD0_CMP_VALUE
103067. DMA1_WORD1_CMP_ENABLE
103068. DMA1_WORD1_CMP_VALUE
103069. DMA2
103070. DMA20_CNT1
103071. DMA20_CNT2
103072. DMA20_PTR1
103073. DMA20_PTR2
103074. DMA21_CNT1
103075. DMA21_CNT2
103076. DMA21_PTR1
103077. DMA21_PTR2
103078. DMA22_CNT1
103079. DMA22_CNT2
103080. DMA22_PTR1
103081. DMA22_PTR2
103082. DMA23_CNT1
103083. DMA23_CNT2
103084. DMA23_PTR1
103085. DMA23_PTR2
103086. DMA24_CNT1
103087. DMA24_CNT2
103088. DMA24_PTR1
103089. DMA24_PTR2
103090. DMA25_CNT1
103091. DMA25_CNT2
103092. DMA25_PTR1
103093. DMA25_PTR2
103094. DMA26_CNT1
103095. DMA26_CNT2
103096. DMA26_PTR1
103097. DMA26_PTR2
103098. DMA2D_CK
103099. DMA2_CHAN_CTRL
103100. DMA2_CHAN_STAT
103101. DMA2_CK
103102. DMA2_CLEAR_FF_REG
103103. DMA2_CLR_MASK_REG
103104. DMA2_CMD_REG
103105. DMA2_CNT1
103106. DMA2_CNT2
103107. DMA2_CURRENT_PCL
103108. DMA2_EXT_MODE_REG
103109. DMA2_EXT_REG
103110. DMA2_MASK_ALL_REG
103111. DMA2_MASK_REG
103112. DMA2_MODE_REG
103113. DMA2_OUTPUT_ADDR_ARRAY_OFFS
103114. DMA2_PREV_PCL
103115. DMA2_PTR1
103116. DMA2_PTR2
103117. DMA2_R
103118. DMA2_READY
103119. DMA2_REQ_REG
103120. DMA2_RESET_REG
103121. DMA2_SHUT
103122. DMA2_STAT_REG
103123. DMA2_TEMP_REG
103124. DMA2_WORD0_CMP_ENABLE
103125. DMA2_WORD0_CMP_VALUE
103126. DMA2_WORD1_CMP_ENABLE
103127. DMA2_WORD1_CMP_VALUE
103128. DMA32_ZONE
103129. DMA3_CHAN_CTRL
103130. DMA3_CHAN_STAT
103131. DMA3_CNT1
103132. DMA3_CNT2
103133. DMA3_CURRENT_PCL
103134. DMA3_PREV_PCL
103135. DMA3_PTR1
103136. DMA3_PTR2
103137. DMA3_READY
103138. DMA3_WORD0_CMP_ENABLE
103139. DMA3_WORD0_CMP_VALUE
103140. DMA3_WORD1_CMP_ENABLE
103141. DMA3_WORD1_CMP_VALUE
103142. DMA40_AUTOSUSPEND_DELAY
103143. DMA4_CHAN_CTRL
103144. DMA4_CHAN_STAT
103145. DMA4_CNT1
103146. DMA4_CNT2
103147. DMA4_CURRENT_PCL
103148. DMA4_PREV_PCL
103149. DMA4_PTR1
103150. DMA4_PTR2
103151. DMA4_READY
103152. DMA4_WORD0_CMP_ENABLE
103153. DMA4_WORD0_CMP_VALUE
103154. DMA4_WORD1_CMP_ENABLE
103155. DMA4_WORD1_CMP_VALUE
103156. DMA5_CNT1
103157. DMA5_CNT2
103158. DMA5_PTR1
103159. DMA5_PTR2
103160. DMA64REGOFFS
103161. DMA64RXREGOFFS
103162. DMA64TXREGOFFS
103163. DMA6_CNT1
103164. DMA6_CNT2
103165. DMA6_PTR1
103166. DMA6_PTR2
103167. DMA7_CNT1
103168. DMA7_CNT2
103169. DMA7_PTR1
103170. DMA7_PTR2
103171. DMA8_CNT1
103172. DMA8_CNT2
103173. DMA8_PTR1
103174. DMA8_PTR2
103175. DMA9_CNT1
103176. DMA9_CNT2
103177. DMA9_PTR1
103178. DMA9_PTR2
103179. DMAARB
103180. DMABLK
103181. DMABRG
103182. DMABRG0
103183. DMABRG1
103184. DMABRG2
103185. DMABRGCR
103186. DMABRGI0
103187. DMABRGI1
103188. DMABRGI2
103189. DMABRGIRQ_A0RXF
103190. DMABRGIRQ_A0RXH
103191. DMABRGIRQ_A0TXF
103192. DMABRGIRQ_A0TXH
103193. DMABRGIRQ_A1RXF
103194. DMABRGIRQ_A1RXH
103195. DMABRGIRQ_A1TXF
103196. DMABRGIRQ_A1TXH
103197. DMABRGIRQ_USBDMA
103198. DMABRGIRQ_USBDMAERR
103199. DMABRG_PERIOD_MAX
103200. DMABRG_PERIOD_MIN
103201. DMABRG_PREALLOC_BUFFER
103202. DMABRG_PREALLOC_BUFFER_MAX
103203. DMABUFFERENTRY
103204. DMABUFFERSIZE
103205. DMABUFSIZE
103206. DMAC
103207. DMAC0
103208. DMAC0123
103209. DMAC0A
103210. DMAC0A_DEI0
103211. DMAC0A_DEI1
103212. DMAC0A_DEI2
103213. DMAC0A_DEI3
103214. DMAC0B
103215. DMAC0B_DADERR
103216. DMAC0B_DEI4
103217. DMAC0B_DEI5
103218. DMAC0RX_OFFSET
103219. DMAC0TX_OFFSET
103220. DMAC0_0
103221. DMAC0_1
103222. DMAC0_2
103223. DMAC0_3
103224. DMAC0_4
103225. DMAC0_5
103226. DMAC0_6
103227. DMAC0_DMAE
103228. DMAC0_DMINT0
103229. DMAC0_DMINT1
103230. DMAC0_DMINT2
103231. DMAC0_DMINT3
103232. DMAC0_DMINT4
103233. DMAC0_DMINT5
103234. DMAC0_DMINTA
103235. DMAC0_OFFSET
103236. DMAC1
103237. DMAC10
103238. DMAC11
103239. DMAC12
103240. DMAC13
103241. DMAC14
103242. DMAC15
103243. DMAC1A
103244. DMAC1A_DEI0
103245. DMAC1A_DEI1
103246. DMAC1A_DEI2
103247. DMAC1A_DEI3
103248. DMAC1B
103249. DMAC1B_DADERR
103250. DMAC1B_DEI4
103251. DMAC1B_DEI5
103252. DMAC1RX_OFFSET
103253. DMAC1TX_OFFSET
103254. DMAC1_0
103255. DMAC1_1
103256. DMAC1_2
103257. DMAC1_3
103258. DMAC1_DMAE
103259. DMAC1_DMINT1
103260. DMAC1_DMINT10
103261. DMAC1_DMINT11
103262. DMAC1_DMINT6
103263. DMAC1_DMINT7
103264. DMAC1_DMINT8
103265. DMAC1_DMINT9
103266. DMAC1_OFFSET
103267. DMAC2
103268. DMAC2_DMINT2
103269. DMAC2_OFFSET
103270. DMAC3
103271. DMAC3_DMINT3
103272. DMAC4
103273. DMAC45
103274. DMAC4_DMINT4
103275. DMAC5
103276. DMAC5_DMINT5
103277. DMAC6
103278. DMAC6_7
103279. DMAC6_DMINT6
103280. DMAC7
103281. DMAC7_DMINT7
103282. DMAC8
103283. DMAC8_11
103284. DMAC9
103285. DMACHCR0
103286. DMACH_AC97_MICIN
103287. DMACH_AC97_PCMIN
103288. DMACH_AC97_PCMOUT
103289. DMACH_EXTERNAL
103290. DMACH_G
103291. DMACH_HSI_I2SV40_RX
103292. DMACH_HSI_I2SV40_TX
103293. DMACH_I2S0_IN
103294. DMACH_I2S0_OUT
103295. DMACH_I2S1_IN
103296. DMACH_I2S1_OUT
103297. DMACH_I2S_IN
103298. DMACH_I2S_OUT
103299. DMACH_IRDA
103300. DMACH_M
103301. DMACH_MAX
103302. DMACH_MIC_IN
103303. DMACH_PCM0_RX
103304. DMACH_PCM0_TX
103305. DMACH_PCM1_RX
103306. DMACH_PCM1_TX
103307. DMACH_PCM_IN
103308. DMACH_PCM_OUT
103309. DMACH_PWM
103310. DMACH_S
103311. DMACH_SDI
103312. DMACH_SECURITY_RX
103313. DMACH_SECURITY_TX
103314. DMACH_SPI0
103315. DMACH_SPI0_RX
103316. DMACH_SPI0_TX
103317. DMACH_SPI1
103318. DMACH_SPI1_RX
103319. DMACH_SPI1_TX
103320. DMACH_TIMER
103321. DMACH_UART0
103322. DMACH_UART0_SRC2
103323. DMACH_UART1
103324. DMACH_UART1_SRC2
103325. DMACH_UART2
103326. DMACH_UART2_SRC2
103327. DMACH_UART3
103328. DMACH_UART3_SRC2
103329. DMACH_USB_EP1
103330. DMACH_USB_EP2
103331. DMACH_USB_EP3
103332. DMACH_USB_EP4
103333. DMACH_XD0
103334. DMACH_XD1
103335. DMACKSUM
103336. DMACKSUMS
103337. DMACK_REQ
103338. DMACMD_DIR
103339. DMACMD_SG
103340. DMACNTLMODFREG_ENDDSP0
103341. DMACNTLMODFREG_ENDDSP1
103342. DMACNTLMODFREG_ENDDSP2
103343. DMACNTLMODFREG_ENDDSP3
103344. DMACNTLMODFREG_STARTDSP0
103345. DMACNTLMODFREG_STARTDSP1
103346. DMACNTLMODFREG_STARTDSP2
103347. DMACNTLMODFREG_STARTDSP3
103348. DMACNTRL0
103349. DMACNTRL1
103350. DMACONTROL_AUTOREPEAT
103351. DMACONTROL_BLOCK_MASK
103352. DMACONTROL_DIRECTION
103353. DMACONTROL_PAGE_MASK
103354. DMACONTROL_STOPPED
103355. DMACOPY
103356. DMACOPYS
103357. DMACPSR1_DMA_ABORT
103358. DMACPSR1_DMA_LEN
103359. DMACPSR1_DMA_START
103360. DMACPSR1_DMA_TYPE
103361. DMACPY
103362. DMACSR0
103363. DMACSR1
103364. DMACSSD
103365. DMACTL
103366. DMACTL_ACTIVE
103367. DMACTL_CLRRUN
103368. DMACTL_DEAD
103369. DMACTL_RUN
103370. DMACTL_WAKE
103371. DMACTRL_GRS
103372. DMACTRL_GTS
103373. DMACTRL_INIT_SETTINGS
103374. DMAC_BLOCK0_SELECTOR
103375. DMAC_BLOCK1_SELECTOR
103376. DMAC_BLOCK2_SELECTOR
103377. DMAC_BLOCK3_SELECTOR
103378. DMAC_BLOCK4_SELECTOR
103379. DMAC_BLOCK5_SELECTOR
103380. DMAC_BLOCK6_SELECTOR
103381. DMAC_BLOCK7_SELECTOR
103382. DMAC_BLOCK8_SELECTOR
103383. DMAC_BLOCK9_SELECTOR
103384. DMAC_BLOCKA_SELECTOR
103385. DMAC_BLOCKB_SELECTOR
103386. DMAC_BLOCKC_SELECTOR
103387. DMAC_BLOCKD_SELECTOR
103388. DMAC_BLOCKE_SELECTOR
103389. DMAC_BLOCKF_SELECTOR
103390. DMAC_BUFFER_SIZE
103391. DMAC_CFG
103392. DMAC_CFG_ALLFLUSH_EN
103393. DMAC_CFG_BURST_LEN
103394. DMAC_CFG_BURST_SZ
103395. DMAC_CFG_CH_ARB_SEL_RX_HIGH_
103396. DMAC_CFG_COAL_EN_
103397. DMAC_CFG_DIR_READ
103398. DMAC_CFG_LASTFLUSH_EN
103399. DMAC_CFG_MAX_DSPACE_128_
103400. DMAC_CFG_MAX_DSPACE_16_
103401. DMAC_CFG_MAX_DSPACE_32_
103402. DMAC_CFG_MAX_DSPACE_64_
103403. DMAC_CFG_MAX_READ_REQ_MASK_
103404. DMAC_CFG_MAX_READ_REQ_SET_
103405. DMAC_CFG_PERIPH_EN
103406. DMAC_CFG_QE
103407. DMAC_CFG_START
103408. DMAC_CHANNEL
103409. DMAC_CHANNELS_CONFIGURED
103410. DMAC_CHANNELS_TEI_CAPABLE
103411. DMAC_CHANNEL_STATE_INITIAL
103412. DMAC_CHANNEL_STATE_SET
103413. DMAC_CHANNEL_STATE_STARTED
103414. DMAC_CHANNEL_STATE_STOPPED
103415. DMAC_CHANNEL_STATE_STOP_PENDING
103416. DMAC_CHAN_EN_SHIFT
103417. DMAC_CHAN_EN_WE_SHIFT
103418. DMAC_CHAN_SUSP_SHIFT
103419. DMAC_CHAN_SUSP_WE_SHIFT
103420. DMAC_CHEN
103421. DMAC_CHEN_H
103422. DMAC_CHEN_L
103423. DMAC_CMD
103424. DMAC_CMD_RX_SWR_
103425. DMAC_CMD_START_R_
103426. DMAC_CMD_START_T_
103427. DMAC_CMD_STOP_R_
103428. DMAC_CMD_STOP_T_
103429. DMAC_CMD_SWR_
103430. DMAC_CMD_TX_SWR_
103431. DMAC_COAL_CFG
103432. DMAC_COAL_CFG_CSR_EXIT_COAL_
103433. DMAC_COAL_CFG_FLUSH_INTS_
103434. DMAC_COAL_CFG_INT_EXIT_COAL_
103435. DMAC_COAL_CFG_RX_THRES_MASK_
103436. DMAC_COAL_CFG_RX_THRES_SET_
103437. DMAC_COAL_CFG_TIMER_LIMIT_MASK_
103438. DMAC_COAL_CFG_TIMER_LIMIT_SET_
103439. DMAC_COAL_CFG_TIMER_TX_START_
103440. DMAC_COAL_CFG_TX_THRES_MASK_
103441. DMAC_COAL_CFG_TX_THRES_SET_
103442. DMAC_COMMON_INTCLEAR
103443. DMAC_COMMON_INTSIGNAL_ENA
103444. DMAC_COMMON_INTSTATUS
103445. DMAC_COMMON_INTSTATUS_ENA
103446. DMAC_COMPVER
103447. DMAC_CONFIG
103448. DMAC_CONFIG_AC97RD
103449. DMAC_CONFIG_AC97WR
103450. DMAC_CONFIG_EN
103451. DMAC_CONFIG_MASKIE
103452. DMAC_CONFIG_MASKITC
103453. DMAC_CONFIG_MMCRD
103454. DMAC_CONFIG_MMCWR
103455. DMAC_CONFIG_UART0_RD
103456. DMAC_CONFIG_UART0_WR
103457. DMAC_CONFIG_UART1RD
103458. DMAC_CONFIG_UART1_WR
103459. DMAC_CONTROL
103460. DMAC_CONTROL_BURST_16BYTE
103461. DMAC_CONTROL_BURST_1BYTE
103462. DMAC_CONTROL_BURST_4BYTE
103463. DMAC_CONTROL_BURST_8BYTE
103464. DMAC_CONTROL_DI
103465. DMAC_CONTROL_OSF_
103466. DMAC_CONTROL_SF_
103467. DMAC_CONTROL_SI
103468. DMAC_CONTROL_SIZE_BYTE
103469. DMAC_CONTROL_SIZE_HWORD
103470. DMAC_CONTROL_SIZE_WORD
103471. DMAC_CONTROL_SR_
103472. DMAC_CONTROL_ST_
103473. DMAC_CONTROL_TTM_
103474. DMAC_DACK0_MARK
103475. DMAC_DACK1_MARK
103476. DMAC_DADERR
103477. DMAC_DESTADDR
103478. DMAC_DEVCON0
103479. DMAC_DEVCON1
103480. DMAC_DREQ0_MARK
103481. DMAC_DREQ1_MARK
103482. DMAC_ENCH
103483. DMAC_EN_MASK
103484. DMAC_EN_POS
103485. DMAC_ID
103486. DMAC_IECR
103487. DMAC_IESR
103488. DMAC_INIT
103489. DMAC_INTR_ENA
103490. DMAC_INTR_ENA_AIS_
103491. DMAC_INTR_ENA_NIS_
103492. DMAC_INTR_ENA_RWT_
103493. DMAC_INTR_ENA_RXBU_
103494. DMAC_INTR_ENA_RXPS_
103495. DMAC_INTR_ENA_RX_
103496. DMAC_INTR_ENA_TXBU_
103497. DMAC_INTR_ENA_TXPS_
103498. DMAC_INTR_ENA_TX_
103499. DMAC_INTSTATUS
103500. DMAC_INT_BIT_RXFRM_
103501. DMAC_INT_BIT_TX_IOC_
103502. DMAC_INT_EN_CLR
103503. DMAC_INT_EN_SET
103504. DMAC_INT_STS
103505. DMAC_IR_MASK
103506. DMAC_ISR
103507. DMAC_ITCCR
103508. DMAC_ITCSR
103509. DMAC_MASKREG
103510. DMAC_MAX_BLK_SIZE
103511. DMAC_MAX_CHANNELS
103512. DMAC_MAX_MASTERS
103513. DMAC_MODE
103514. DMAC_MODECON
103515. DMAC_MODE_ENABLE
103516. DMAC_MODE_NS
103517. DMAC_MODE_RESET
103518. DMAC_M_BIT
103519. DMAC_OBFF_CFG
103520. DMAC_OBFF_RX_THRES_MASK_
103521. DMAC_OBFF_RX_THRES_SET_
103522. DMAC_OBFF_TX_THRES_MASK_
103523. DMAC_OBFF_TX_THRES_SET_
103524. DMAC_OFFSET
103525. DMAC_PAGE0_SELECTOR
103526. DMAC_PAGE1_SELECTOR
103527. DMAC_PAGE2_SELECTOR
103528. DMAC_PAGE3_SELECTOR
103529. DMAC_RD_CFG
103530. DMAC_RD_CNT
103531. DMAC_READ
103532. DMAC_REGS_VIRT
103533. DMAC_REQREG
103534. DMAC_RESET
103535. DMAC_SIZE
103536. DMAC_SRCADDR
103537. DMAC_STATUS
103538. DMAC_STS_AIS_
103539. DMAC_STS_NIS_
103540. DMAC_STS_RS_
103541. DMAC_STS_RWT_
103542. DMAC_STS_RXBU_
103543. DMAC_STS_RXPS_
103544. DMAC_STS_RX_
103545. DMAC_STS_TS_
103546. DMAC_STS_TXBU_
103547. DMAC_STS_TXPS_
103548. DMAC_STS_TXUNF_
103549. DMAC_STS_TX_
103550. DMAC_TEMPHI
103551. DMAC_TEMPLO
103552. DMAC_TXADRHI
103553. DMAC_TXADRLO
103554. DMAC_TXADRMD
103555. DMAC_TXCNTHI
103556. DMAC_TXCNTLO
103557. DMAC_T_BIT
103558. DMAC_WRITE
103559. DMAC_WR_CFG
103560. DMAC_WR_CNT
103561. DMACtrl
103562. DMADAC0
103563. DMADAC1
103564. DMADATA_ENDIAN_SHIFT
103565. DMADATA_OFFSET
103566. DMADESC_APPEND_CRC
103567. DMADESC_CRC_MASK
103568. DMADESC_ENDIAN_SHIFT
103569. DMADESC_EOP_MASK
103570. DMADESC_ERR_MASK
103571. DMADESC_ESOP_MASK
103572. DMADESC_LENGTH_MASK
103573. DMADESC_LENGTH_SHIFT
103574. DMADESC_OVSIZE_MASK
103575. DMADESC_OV_MASK
103576. DMADESC_OWNER_MASK
103577. DMADESC_RXER_MASK
103578. DMADESC_SOP_MASK
103579. DMADESC_UNDER_MASK
103580. DMADESC_USB_NOZERO_MASK
103581. DMADESC_USB_ZERO_MASK
103582. DMADESC_WRAP_MASK
103583. DMADONE
103584. DMADPR0
103585. DMADPR1
103586. DMADSPBASEADDRREG_ENDDSP0
103587. DMADSPBASEADDRREG_ENDDSP1
103588. DMADSPBASEADDRREG_ENDDSP2
103589. DMADSPBASEADDRREG_ENDDSP3
103590. DMADSPBASEADDRREG_STARTDSP0
103591. DMADSPBASEADDRREG_STARTDSP1
103592. DMADSPBASEADDRREG_STARTDSP2
103593. DMADSPBASEADDRREG_STARTDSP3
103594. DMADSPCURADDRREG_ENDDSP0
103595. DMADSPCURADDRREG_ENDDSP1
103596. DMADSPCURADDRREG_ENDDSP2
103597. DMADSPCURADDRREG_ENDDSP3
103598. DMADSPCURADDRREG_STARTDSP0
103599. DMADSPCURADDRREG_STARTDSP1
103600. DMADSPCURADDRREG_STARTDSP2
103601. DMADSPCURADDRREG_STARTDSP3
103602. DMADone
103603. DMAE
103604. DMAE0_IRQ
103605. DMAE1_IRQ
103606. DMAE2
103607. DMAE3
103608. DMAEN
103609. DMAEND
103610. DMAENGINE_ALIGN_16_BYTES
103611. DMAENGINE_ALIGN_1_BYTE
103612. DMAENGINE_ALIGN_2_BYTES
103613. DMAENGINE_ALIGN_32_BYTES
103614. DMAENGINE_ALIGN_4_BYTES
103615. DMAENGINE_ALIGN_64_BYTES
103616. DMAENGINE_ALIGN_8_BYTES
103617. DMAENGINE_H
103618. DMAERR
103619. DMAE_CMD_COMP_CRC_EN_MASK
103620. DMAE_CMD_COMP_CRC_EN_MASK_NONE
103621. DMAE_CMD_COMP_CRC_EN_MASK_SET
103622. DMAE_CMD_COMP_CRC_EN_SHIFT
103623. DMAE_CMD_COMP_CRC_OFFSET_MASK
103624. DMAE_CMD_COMP_CRC_OFFSET_SHIFT
103625. DMAE_CMD_COMP_FUNC_MASK
103626. DMAE_CMD_COMP_FUNC_SHIFT
103627. DMAE_CMD_COMP_WORD_EN_MASK
103628. DMAE_CMD_COMP_WORD_EN_SHIFT
103629. DMAE_CMD_CRC_RESET_MASK
103630. DMAE_CMD_CRC_RESET_SHIFT
103631. DMAE_CMD_C_DST_GRC
103632. DMAE_CMD_C_DST_MASK
103633. DMAE_CMD_C_DST_PCI
103634. DMAE_CMD_C_DST_SHIFT
103635. DMAE_CMD_C_ENABLE
103636. DMAE_CMD_DST_ADDR_RESET_MASK
103637. DMAE_CMD_DST_ADDR_RESET_SHIFT
103638. DMAE_CMD_DST_GRC
103639. DMAE_CMD_DST_MASK
103640. DMAE_CMD_DST_MASK_GRC
103641. DMAE_CMD_DST_MASK_NONE
103642. DMAE_CMD_DST_MASK_PCIE
103643. DMAE_CMD_DST_PCI
103644. DMAE_CMD_DST_PF_ID_MASK
103645. DMAE_CMD_DST_PF_ID_SHIFT
103646. DMAE_CMD_DST_RESET
103647. DMAE_CMD_DST_SHIFT
103648. DMAE_CMD_DST_VF_ID_MASK
103649. DMAE_CMD_DST_VF_ID_SHIFT
103650. DMAE_CMD_DST_VF_ID_VALID_MASK
103651. DMAE_CMD_DST_VF_ID_VALID_SHIFT
103652. DMAE_CMD_E1HVN_SHIFT
103653. DMAE_CMD_ENDIANITY
103654. DMAE_CMD_ENDIANITY_B_DW_SWAP
103655. DMAE_CMD_ENDIANITY_B_SWAP
103656. DMAE_CMD_ENDIANITY_DW_SWAP
103657. DMAE_CMD_ENDIANITY_MODE_MASK
103658. DMAE_CMD_ENDIANITY_MODE_SHIFT
103659. DMAE_CMD_ENDIANITY_NO_SWAP
103660. DMAE_CMD_ERR_HANDLING_MASK
103661. DMAE_CMD_ERR_HANDLING_SHIFT
103662. DMAE_CMD_PORT_0
103663. DMAE_CMD_PORT_1
103664. DMAE_CMD_PORT_ID_MASK
103665. DMAE_CMD_PORT_ID_SHIFT
103666. DMAE_CMD_RESERVED1_MASK
103667. DMAE_CMD_RESERVED1_SHIFT
103668. DMAE_CMD_RESERVED2_MASK
103669. DMAE_CMD_RESERVED2_SHIFT
103670. DMAE_CMD_SIZE
103671. DMAE_CMD_SIZE_TO_FILL
103672. DMAE_CMD_SRC_ADDR_RESET_MASK
103673. DMAE_CMD_SRC_ADDR_RESET_SHIFT
103674. DMAE_CMD_SRC_GRC
103675. DMAE_CMD_SRC_MASK
103676. DMAE_CMD_SRC_MASK_GRC
103677. DMAE_CMD_SRC_MASK_PCIE
103678. DMAE_CMD_SRC_PCI
103679. DMAE_CMD_SRC_PF_ID_MASK
103680. DMAE_CMD_SRC_PF_ID_SHIFT
103681. DMAE_CMD_SRC_RESET
103682. DMAE_CMD_SRC_SHIFT
103683. DMAE_CMD_SRC_VF_ID_MASK
103684. DMAE_CMD_SRC_VF_ID_SHIFT
103685. DMAE_CMD_SRC_VF_ID_VALID_MASK
103686. DMAE_CMD_SRC_VF_ID_VALID_SHIFT
103687. DMAE_COMMAND_CRC_RESET
103688. DMAE_COMMAND_CRC_RESET_SHIFT
103689. DMAE_COMMAND_C_DST
103690. DMAE_COMMAND_C_DST_SHIFT
103691. DMAE_COMMAND_C_FUNC
103692. DMAE_COMMAND_C_FUNC_SHIFT
103693. DMAE_COMMAND_C_TYPE_CRC_ENABLE
103694. DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT
103695. DMAE_COMMAND_C_TYPE_CRC_OFFSET
103696. DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT
103697. DMAE_COMMAND_C_TYPE_ENABLE
103698. DMAE_COMMAND_C_TYPE_ENABLE_SHIFT
103699. DMAE_COMMAND_DST
103700. DMAE_COMMAND_DST_RESET
103701. DMAE_COMMAND_DST_RESET_SHIFT
103702. DMAE_COMMAND_DST_SHIFT
103703. DMAE_COMMAND_DST_VFID
103704. DMAE_COMMAND_DST_VFID_SHIFT
103705. DMAE_COMMAND_DST_VFPF
103706. DMAE_COMMAND_DST_VFPF_SHIFT
103707. DMAE_COMMAND_DST_VN
103708. DMAE_COMMAND_DST_VN_SHIFT
103709. DMAE_COMMAND_E1HVN
103710. DMAE_COMMAND_E1HVN_SHIFT
103711. DMAE_COMMAND_ENDIANITY
103712. DMAE_COMMAND_ENDIANITY_SHIFT
103713. DMAE_COMMAND_ERR_POLICY
103714. DMAE_COMMAND_ERR_POLICY_SHIFT
103715. DMAE_COMMAND_PORT
103716. DMAE_COMMAND_PORT_SHIFT
103717. DMAE_COMMAND_RESERVED0
103718. DMAE_COMMAND_RESERVED0_SHIFT
103719. DMAE_COMMAND_RESERVED1
103720. DMAE_COMMAND_RESERVED1_SHIFT
103721. DMAE_COMMAND_RESERVED2
103722. DMAE_COMMAND_RESERVED2_SHIFT
103723. DMAE_COMMAND_SRC
103724. DMAE_COMMAND_SRC_RESET
103725. DMAE_COMMAND_SRC_RESET_SHIFT
103726. DMAE_COMMAND_SRC_SHIFT
103727. DMAE_COMMAND_SRC_VFID
103728. DMAE_COMMAND_SRC_VFID_SHIFT
103729. DMAE_COMMAND_SRC_VFPF
103730. DMAE_COMMAND_SRC_VFPF_SHIFT
103731. DMAE_COMPLETION_VAL
103732. DMAE_COMP_GRC
103733. DMAE_COMP_PCI
103734. DMAE_COMP_REGULAR
103735. DMAE_COMP_VAL
103736. DMAE_COM_SET_ERR
103737. DMAE_C_DST
103738. DMAE_C_SRC
103739. DMAE_DP_DST_GRC
103740. DMAE_DP_DST_NONE
103741. DMAE_DP_DST_PCI
103742. DMAE_DP_SRC_GRC
103743. DMAE_DP_SRC_PCI
103744. DMAE_DST_GRC
103745. DMAE_DST_NONE
103746. DMAE_DST_PCI
103747. DMAE_DST_PF
103748. DMAE_DST_VF
103749. DMAE_GO_VALUE
103750. DMAE_INT
103751. DMAE_LEN32_RD_MAX
103752. DMAE_LEN32_WR_MAX
103753. DMAE_MAX_CLIENTS
103754. DMAE_MAX_RW_SIZE
103755. DMAE_MIN_WAIT_TIME
103756. DMAE_NOT_RDY
103757. DMAE_PCI_ERROR
103758. DMAE_PCI_ERR_FLAG
103759. DMAE_READY_CB
103760. DMAE_REG_BACKWARD_COMP_EN
103761. DMAE_REG_CMD_MEM
103762. DMAE_REG_CMD_MEM_SIZE
103763. DMAE_REG_CRC16C_INIT
103764. DMAE_REG_CRC16T10_INIT
103765. DMAE_REG_DBG_DWORD_ENABLE
103766. DMAE_REG_DBG_FORCE_FRAME
103767. DMAE_REG_DBG_FORCE_VALID
103768. DMAE_REG_DBG_SELECT
103769. DMAE_REG_DBG_SHIFT
103770. DMAE_REG_DMAE_INT_MASK
103771. DMAE_REG_DMAE_PRTY_MASK
103772. DMAE_REG_DMAE_PRTY_STS
103773. DMAE_REG_DMAE_PRTY_STS_CLR
103774. DMAE_REG_GO_C0
103775. DMAE_REG_GO_C1
103776. DMAE_REG_GO_C10
103777. DMAE_REG_GO_C11
103778. DMAE_REG_GO_C12
103779. DMAE_REG_GO_C13
103780. DMAE_REG_GO_C14
103781. DMAE_REG_GO_C15
103782. DMAE_REG_GO_C16
103783. DMAE_REG_GO_C17
103784. DMAE_REG_GO_C18
103785. DMAE_REG_GO_C19
103786. DMAE_REG_GO_C2
103787. DMAE_REG_GO_C20
103788. DMAE_REG_GO_C21
103789. DMAE_REG_GO_C22
103790. DMAE_REG_GO_C23
103791. DMAE_REG_GO_C24
103792. DMAE_REG_GO_C25
103793. DMAE_REG_GO_C26
103794. DMAE_REG_GO_C27
103795. DMAE_REG_GO_C28
103796. DMAE_REG_GO_C29
103797. DMAE_REG_GO_C3
103798. DMAE_REG_GO_C30
103799. DMAE_REG_GO_C31
103800. DMAE_REG_GO_C4
103801. DMAE_REG_GO_C5
103802. DMAE_REG_GO_C6
103803. DMAE_REG_GO_C7
103804. DMAE_REG_GO_C8
103805. DMAE_REG_GO_C9
103806. DMAE_REG_GRC_IFEN
103807. DMAE_REG_INIT
103808. DMAE_REG_PCI_IFEN
103809. DMAE_REG_PXP_REQ_INIT_CRD
103810. DMAE_SRC_GRC
103811. DMAE_SRC_PCI
103812. DMAE_SRC_PF
103813. DMAE_SRC_VF
103814. DMAE_TIMEOUT
103815. DMAFIFO_AD_OMASK
103816. DMAFIFO_AD_SMASK
103817. DMAFIFO_AD_SRDD
103818. DMAFIFO_AD_SRDP
103819. DMAFIFO_AD_SRFD
103820. DMAFIFO_AD_SRFP
103821. DMAFIFO_AD_SXDD
103822. DMAFIFO_AD_SXDP
103823. DMAFIFO_AD_SXFD
103824. DMAFIFO_AD_SXFP
103825. DMAF_ALL
103826. DMAF_AUD0
103827. DMAF_AUD1
103828. DMAF_AUD2
103829. DMAF_AUD3
103830. DMAF_BLITHOG
103831. DMAF_BLITTER
103832. DMAF_BLTDONE
103833. DMAF_BLTNZERO
103834. DMAF_COPPER
103835. DMAF_DISK
103836. DMAF_MASTER
103837. DMAF_RASTER
103838. DMAF_SETCLR
103839. DMAF_SPRITE
103840. DMAGLOBSTATSREGDSP0
103841. DMAGLOBSTATSREGDSP1
103842. DMAGLOBSTATSREGDSP2
103843. DMAGLOBSTATSREGDSP3
103844. DMAHOSTBASEADDRREG_ENDDSP0
103845. DMAHOSTBASEADDRREG_ENDDSP1
103846. DMAHOSTBASEADDRREG_ENDDSP2
103847. DMAHOSTBASEADDRREG_ENDDSP3
103848. DMAHOSTBASEADDRREG_STARTDSP0
103849. DMAHOSTBASEADDRREG_STARTDSP1
103850. DMAHOSTBASEADDRREG_STARTDSP2
103851. DMAHOSTBASEADDRREG_STARTDSP3
103852. DMAHOSTCURADDRREG_ENDDSP0
103853. DMAHOSTCURADDRREG_ENDDSP1
103854. DMAHOSTCURADDRREG_ENDDSP2
103855. DMAHOSTCURADDRREG_ENDDSP3
103856. DMAHOSTCURADDRREG_STARTDSP0
103857. DMAHOSTCURADDRREG_STARTDSP1
103858. DMAHOSTCURADDRREG_STARTDSP2
103859. DMAHOSTCURADDRREG_STARTDSP3
103860. DMAIE
103861. DMAIF
103862. DMAIF0_RESET
103863. DMAIF1_RESET
103864. DMAIF2_RESET
103865. DMAIF3_RESET
103866. DMAIF4_RESET
103867. DMAIF5_RESET
103868. DMAIF6_RESET
103869. DMAIF7_RESET
103870. DMAINTERRUPT
103871. DMAINTRMASK
103872. DMAInProgress
103873. DMALADR0
103874. DMALADR1
103875. DMAMARBR
103876. DMAMODE0
103877. DMAMODE1
103878. DMAMR
103879. DMAMR_TX_MODE_FULL
103880. DMAMR_TX_MODE_NONE
103881. DMAMR_TX_MODE_PART
103882. DMAMUX
103883. DMAMUX_NR
103884. DMAMUX_R
103885. DMAM_CFG
103886. DMAM_CFG_CONT
103887. DMAM_CFG_DIR_READ
103888. DMAM_CFG_EN
103889. DMAM_CFG_SDMA_GAP
103890. DMAM_CFG_START
103891. DMAM_CNT
103892. DMANOCS
103893. DMAOFFSET
103894. DMAON
103895. DMAOR
103896. DMAOR_AE
103897. DMAOR_BRG
103898. DMAOR_DME
103899. DMAOR_DMEN
103900. DMAOR_INIT
103901. DMAOR_NMIF
103902. DMAPADR0
103903. DMAPADR1
103904. DMAPBUFFERENTRY
103905. DMAPI_MINOR
103906. DMAPLUS
103907. DMAPOOL_DEBUG
103908. DMARD05_AXIS_SCALE_VAL
103909. DMARD05_CHIP_ID
103910. DMARD06_ACCEL_CHANNEL
103911. DMARD06_AXIS_SCALE_VAL
103912. DMARD06_CHIP_ID
103913. DMARD06_CHIP_ID_REG
103914. DMARD06_CTRL1_REG
103915. DMARD06_DRV_NAME
103916. DMARD06_MODE_NORMAL
103917. DMARD06_MODE_POWERDOWN
103918. DMARD06_PM_OPS
103919. DMARD06_SIGN_BIT
103920. DMARD06_TEMP_CENTER_VAL
103921. DMARD06_TEMP_CHANNEL
103922. DMARD06_TOUT_REG
103923. DMARD06_XOUT_REG
103924. DMARD06_YOUT_REG
103925. DMARD06_ZOUT_REG
103926. DMARD07_CHIP_ID
103927. DMARD09_AXIS_X
103928. DMARD09_AXIS_X_OFFSET
103929. DMARD09_AXIS_Y
103930. DMARD09_AXIS_Y_OFFSET
103931. DMARD09_AXIS_Z
103932. DMARD09_AXIS_Z_OFFSET
103933. DMARD09_BUF_LEN
103934. DMARD09_CHANNEL
103935. DMARD09_CHIPID
103936. DMARD09_DRV_NAME
103937. DMARD09_REG_CHIPID
103938. DMARD09_REG_STAT
103939. DMARD09_REG_X
103940. DMARD09_REG_Y
103941. DMARD09_REG_Z
103942. DMARD10_CHANNEL
103943. DMARD10_MODE_ACTIVE
103944. DMARD10_MODE_OFF
103945. DMARD10_MODE_READ_OTP
103946. DMARD10_MODE_RESET_DATA_PATH
103947. DMARD10_MODE_STANDBY
103948. DMARD10_REG_ACTR
103949. DMARD10_REG_AFEM
103950. DMARD10_REG_MISC2
103951. DMARD10_REG_PD
103952. DMARD10_REG_STADR
103953. DMARD10_REG_STAINT
103954. DMARD10_VALUE_AFEM_AFEN_NORMAL
103955. DMARD10_VALUE_CKSEL_ODR_100_204
103956. DMARD10_VALUE_INTC
103957. DMARD10_VALUE_MISC2_OSCA_EN
103958. DMARD10_VALUE_PD_RST
103959. DMARD10_VALUE_STADR
103960. DMARD10_VALUE_STAINT
103961. DMARD10_VALUE_TAPNS_AVE_2
103962. DMARD10_X_OFFSET
103963. DMARD10_Y_OFFSET
103964. DMARD10_Z_OFFSET
103965. DMAREG
103966. DMAREG0
103967. DMAREG1
103968. DMAREQ
103969. DMARES
103970. DMARESETMODULE
103971. DMARSRA
103972. DMARXCTRL
103973. DMARXDESCH
103974. DMARXDESCL
103975. DMARXSTATUS
103976. DMARX_CTRL_ENABLE
103977. DMARX_CTRL_ROMASK
103978. DMARX_CTRL_ROSHIFT
103979. DMARX_STAT_CDMASK
103980. DMARX_STAT_EBEBW
103981. DMARX_STAT_EBEDA
103982. DMARX_STAT_EDFO
103983. DMARX_STAT_EDPE
103984. DMARX_STAT_EMASK
103985. DMARX_STAT_ENONE
103986. DMARX_STAT_SACTIVE
103987. DMARX_STAT_SDISABLED
103988. DMARX_STAT_SIDLE
103989. DMARX_STAT_SMASK
103990. DMARX_STAT_SSTOPPED
103991. DMAR_AFLOG_REG
103992. DMAR_CAP_REG
103993. DMAR_CCMD_REG
103994. DMAR_DLY_CNT_BMSK
103995. DMAR_DLY_CNT_DEF
103996. DMAR_DLY_CNT_SHFT
103997. DMAR_DSM_FUNC_ATSR
103998. DMAR_DSM_FUNC_DRHD
103999. DMAR_DSM_FUNC_RHSA
104000. DMAR_DSM_REV_ID
104001. DMAR_ECAP_REG
104002. DMAR_EN
104003. DMAR_FEADDR_REG
104004. DMAR_FECTL_REG
104005. DMAR_FEDATA_REG
104006. DMAR_FEUADDR_REG
104007. DMAR_FSTS_REG
104008. DMAR_GCMD_REG
104009. DMAR_GSTS_REG
104010. DMAR_ICS_REG
104011. DMAR_INTR_REMAP
104012. DMAR_IQA_REG
104013. DMAR_IQH_REG
104014. DMAR_IQT_REG
104015. DMAR_IQ_SHIFT
104016. DMAR_IRTA_REG
104017. DMAR_MTRRCAP_REG
104018. DMAR_MTRRDEF_REG
104019. DMAR_MTRR_FIX16K_80000_REG
104020. DMAR_MTRR_FIX16K_A0000_REG
104021. DMAR_MTRR_FIX4K_C0000_REG
104022. DMAR_MTRR_FIX4K_C8000_REG
104023. DMAR_MTRR_FIX4K_D0000_REG
104024. DMAR_MTRR_FIX4K_D8000_REG
104025. DMAR_MTRR_FIX4K_E0000_REG
104026. DMAR_MTRR_FIX4K_E8000_REG
104027. DMAR_MTRR_FIX4K_F0000_REG
104028. DMAR_MTRR_FIX4K_F8000_REG
104029. DMAR_MTRR_FIX64K_00000_REG
104030. DMAR_MTRR_PHYSBASE0_REG
104031. DMAR_MTRR_PHYSBASE1_REG
104032. DMAR_MTRR_PHYSBASE2_REG
104033. DMAR_MTRR_PHYSBASE3_REG
104034. DMAR_MTRR_PHYSBASE4_REG
104035. DMAR_MTRR_PHYSBASE5_REG
104036. DMAR_MTRR_PHYSBASE6_REG
104037. DMAR_MTRR_PHYSBASE7_REG
104038. DMAR_MTRR_PHYSBASE8_REG
104039. DMAR_MTRR_PHYSBASE9_REG
104040. DMAR_MTRR_PHYSMASK0_REG
104041. DMAR_MTRR_PHYSMASK1_REG
104042. DMAR_MTRR_PHYSMASK2_REG
104043. DMAR_MTRR_PHYSMASK3_REG
104044. DMAR_MTRR_PHYSMASK4_REG
104045. DMAR_MTRR_PHYSMASK5_REG
104046. DMAR_MTRR_PHYSMASK6_REG
104047. DMAR_MTRR_PHYSMASK7_REG
104048. DMAR_MTRR_PHYSMASK8_REG
104049. DMAR_MTRR_PHYSMASK9_REG
104050. DMAR_OPERATION_TIMEOUT
104051. DMAR_PEADDR_REG
104052. DMAR_PECTL_REG
104053. DMAR_PEDATA_REG
104054. DMAR_PEUADDR_REG
104055. DMAR_PHMBASE_REG
104056. DMAR_PHMLIMIT_REG
104057. DMAR_PLATFORM_OPT_IN
104058. DMAR_PLMBASE_REG
104059. DMAR_PLMLIMIT_REG
104060. DMAR_PMEN_REG
104061. DMAR_PQA_REG
104062. DMAR_PQH_REG
104063. DMAR_PQT_REG
104064. DMAR_PRS_REG
104065. DMAR_REQ_PRI
104066. DMAR_RTADDR_REG
104067. DMAR_TO_INT
104068. DMAR_UNITS_SUPPORTED
104069. DMAR_VCCAP_REG
104070. DMAR_VCMD_REG
104071. DMAR_VCRSP_REG
104072. DMAR_VER_MAJOR
104073. DMAR_VER_MINOR
104074. DMAR_VER_REG
104075. DMAR_X2APIC_OPT_OUT
104076. DMAReset
104077. DMASCR_ANY_ERR
104078. DMASCR_CHAIN_COMPLETE
104079. DMASCR_CHAIN_COMP_EN
104080. DMASCR_CHAIN_EN
104081. DMASCR_DMA_COMPLETE
104082. DMASCR_DMA_COMP_EN
104083. DMASCR_ERROR_MASK
104084. DMASCR_ERR_INT_EN
104085. DMASCR_GO
104086. DMASCR_HARD_ERROR
104087. DMASCR_MASTER_ABT
104088. DMASCR_MBE_ERR
104089. DMASCR_PARITY_ERR_DET
104090. DMASCR_PARITY_ERR_REP
104091. DMASCR_PARITY_INT_EN
104092. DMASCR_READ
104093. DMASCR_READLINE
104094. DMASCR_READMULTI
104095. DMASCR_SEM_EN
104096. DMASCR_SYSTEM_ERR_SIG
104097. DMASCR_TARGET_ABT
104098. DMASCR_TRANSFER_READ
104099. DMASIZ0
104100. DMASIZ1
104101. DMASNDGetAdr
104102. DMASNDSetBase
104103. DMASNDSetEnd
104104. DMASND_CTRL_OFF
104105. DMASND_CTRL_ON
104106. DMASND_CTRL_RECORD_OFF
104107. DMASND_CTRL_RECORD_ON
104108. DMASND_CTRL_RECORD_REPEAT
104109. DMASND_CTRL_REPEAT
104110. DMASND_CTRL_SELECT_RECORD
104111. DMASND_CTRL_SELECT_REPLAY
104112. DMASND_MFP_INT_RECORD
104113. DMASND_MFP_INT_REPLAY
104114. DMASND_MODE_12KHZ
104115. DMASND_MODE_16BIT
104116. DMASND_MODE_25KHZ
104117. DMASND_MODE_50KHZ
104118. DMASND_MODE_6KHZ
104119. DMASND_MODE_8BIT
104120. DMASND_MODE_MONO
104121. DMASND_MODE_STEREO
104122. DMASND_TIMERA_INT_RECORD
104123. DMASND_TIMERA_INT_REPLAY
104124. DMASOUND_ATARI_EDITION
104125. DMASOUND_ATARI_REVISION
104126. DMASOUND_CORE_EDITION
104127. DMASOUND_CORE_REVISION
104128. DMASOUND_PAULA_EDITION
104129. DMASOUND_PAULA_REVISION
104130. DMASOUND_Q40_EDITION
104131. DMASOUND_Q40_REVISION
104132. DMAST
104133. DMASTAT
104134. DMASTAT_DRQ
104135. DMASTAT_OFFSET
104136. DMASTOP
104137. DMAS_CTRL
104138. DMAS_CTRL_DIR_READ
104139. DMAS_CTRL_EN
104140. DMASp
104141. DMATANXCOUNTREG_ENDDSP0
104142. DMATANXCOUNTREG_ENDDSP1
104143. DMATANXCOUNTREG_ENDDSP2
104144. DMATANXCOUNTREG_ENDDSP3
104145. DMATANXCOUNTREG_STARTDSP0
104146. DMATANXCOUNTREG_STARTDSP1
104147. DMATANXCOUNTREG_STARTDSP2
104148. DMATANXCOUNTREG_STARTDSP3
104149. DMATC
104150. DMATC0
104151. DMATC1
104152. DMATC2
104153. DMATC3
104154. DMATC_CLEAR_REG
104155. DMATFNR_ACC_CXF
104156. DMATFNR_ACC_F0
104157. DMATFNR_ACC_F1
104158. DMATFNR_ACC_F2
104159. DMATFNR_ACC_F3
104160. DMATFNR_ACC_FN
104161. DMATFNR_DISDMA
104162. DMATHR
104163. DMATIMEBUGREG_ENDDSP0
104164. DMATIMEBUGREG_ENDDSP1
104165. DMATIMEBUGREG_ENDDSP2
104166. DMATIMEBUGREG_ENDDSP3
104167. DMATIMEBUGREG_STARTDSP0
104168. DMATIMEBUGREG_STARTDSP1
104169. DMATIMEBUGREG_STARTDSP2
104170. DMATIMEBUGREG_STARTDSP3
104171. DMATXCTRL
104172. DMATXDESCH
104173. DMATXDESCL
104174. DMATXSTATUS
104175. DMATX_CTRL_ENABLE
104176. DMATX_CTRL_FAIRPRIOR
104177. DMATX_CTRL_FLUSH
104178. DMATX_CTRL_LPBACK
104179. DMATX_CTRL_SUSPEND
104180. DMATX_STAT_CDMASK
104181. DMATX_STAT_EBEBR
104182. DMATX_STAT_EBEDA
104183. DMATX_STAT_EDFU
104184. DMATX_STAT_EDPE
104185. DMATX_STAT_EMASK
104186. DMATX_STAT_ENONE
104187. DMATX_STAT_FLUSHED
104188. DMATX_STAT_SACTIVE
104189. DMATX_STAT_SDISABLED
104190. DMATX_STAT_SIDLE
104191. DMATX_STAT_SMASK
104192. DMATX_STAT_SSTOPPED
104193. DMATX_STAT_SSUSP
104194. DMAW_DLY_CNT_BMSK
104195. DMAW_DLY_CNT_DEF
104196. DMAW_DLY_CNT_SHFT
104197. DMAW_EN
104198. DMAW_TO_INT
104199. DMAX
104200. DMAXFERABORT
104201. DMAXFERCOMP
104202. DMAXFERERROR
104203. DMA_0
104204. DMA_1
104205. DMA_1024
104206. DMA_128
104207. DMA_1_DESTINATION
104208. DMA_1_DESTINATION_ADDRESS_CS
104209. DMA_1_DESTINATION_ADDRESS_EXT
104210. DMA_1_DESTINATION_ADDRESS_MASK
104211. DMA_1_SIZE_CONTROL
104212. DMA_1_SIZE_CONTROL_SIZE_MASK
104213. DMA_1_SIZE_CONTROL_STATUS
104214. DMA_1_SOURCE
104215. DMA_1_SOURCE_ADDRESS_CS
104216. DMA_1_SOURCE_ADDRESS_EXT
104217. DMA_1_SOURCE_ADDRESS_MASK
104218. DMA_2
104219. DMA_256
104220. DMA_2CLKS
104221. DMA_2DSCTL_mskSTWECNT
104222. DMA_2DSCTL_offSTWECNT
104223. DMA_2DSET_mskHTSTR
104224. DMA_2DSET_mskWECNT
104225. DMA_2DSET_offHTSTR
104226. DMA_2DSET_offWECNT
104227. DMA_2W_BURST
104228. DMA_3
104229. DMA_3CLKS
104230. DMA_512
104231. DMA_8BIT
104232. DMA_AB
104233. DMA_ABORT
104234. DMA_ABORT_DONE
104235. DMA_ABORT_DONE_INTERRUPT
104236. DMA_ABORT_INTERRUPT
104237. DMA_ABORT_INTERRUPT_ABORT_0
104238. DMA_ABORT_INTERRUPT_ABORT_1
104239. DMA_ABORT_INTERRUPT_INT_0
104240. DMA_ABORT_INTERRUPT_INT_1
104241. DMA_ACC_SZ_ERR
104242. DMA_ACT
104243. DMA_ACTION
104244. DMA_ACTIVE
104245. DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT_MASK
104246. DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT__SHIFT
104247. DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN_MASK
104248. DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN__SHIFT
104249. DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD_MASK
104250. DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD__SHIFT
104251. DMA_ACTIVITY_TIMEOUT
104252. DMA_ACTIVITY_VECTOR_MASK
104253. DMA_ACT_mskACMD
104254. DMA_ACT_offACMD
104255. DMA_ADDR
104256. DMA_ADDRESS
104257. DMA_ADDRESS_128_BITS_ALIGNMENT
104258. DMA_ADDRESS_HOLD
104259. DMA_ADDRESS_SPACE_GTT
104260. DMA_ADDRESS_SPACE_WOPCM
104261. DMA_ADDR_0
104262. DMA_ADDR_0_HIGH
104263. DMA_ADDR_0_LOW
104264. DMA_ADDR_1
104265. DMA_ADDR_1_HIGH
104266. DMA_ADDR_1_LOW
104267. DMA_ADDR_2
104268. DMA_ADDR_3
104269. DMA_ADDR_36BIT
104270. DMA_ADDR_4
104271. DMA_ADDR_5
104272. DMA_ADDR_6
104273. DMA_ADDR_7
104274. DMA_ADDR_DEF_BITS
104275. DMA_ADDR_DISAB
104276. DMA_ADDR_EXT_BITS
104277. DMA_ADDR_HIGH32
104278. DMA_ADDR_HIGH_4BIT
104279. DMA_ADDR_INVALID
104280. DMA_ADDR_LIST_MASK
104281. DMA_ADDR_LIST_SHIFT
104282. DMA_ADDR_LOW32
104283. DMA_ADDR_T_SHIFT
104284. DMA_ADDR_T_WIDTH
104285. DMA_ADD_ENABLE
104286. DMA_AHB_SLV_CFG_ON
104287. DMA_ALIGN
104288. DMA_ALIGNMENT
104289. DMA_ALIGN_MASK
104290. DMA_ARBITER_MODE_MASK
104291. DMA_ARBITER_RR
104292. DMA_ARBITER_SP
104293. DMA_ARBITER_WRR
104294. DMA_ARB_CTRL
104295. DMA_ASYNC_TX
104296. DMA_ATTR_AEQ_DEFAULT
104297. DMA_ATTR_ALLOC_SINGLE_PAGES
104298. DMA_ATTR_CEQ_DEFAULT
104299. DMA_ATTR_FORCE_CONTIGUOUS
104300. DMA_ATTR_NON_CONSISTENT
104301. DMA_ATTR_NO_KERNEL_MAPPING
104302. DMA_ATTR_NO_WARN
104303. DMA_ATTR_PRIVILEGED
104304. DMA_ATTR_SKIP_CPU_SYNC
104305. DMA_ATTR_WEAK_ORDERING
104306. DMA_ATTR_WRITE_BARRIER
104307. DMA_ATTR_WRITE_COMBINE
104308. DMA_AUTOINIT
104309. DMA_AUTO_CLR_FIFO
104310. DMA_AUTO_NADDR
104311. DMA_AVAILABLE
104312. DMA_AXIARCR
104313. DMA_AXIAWARCR
104314. DMA_AXIAWCR
104315. DMA_AXI_1KBBE
104316. DMA_AXI_AAL
104317. DMA_AXI_BLEN128
104318. DMA_AXI_BLEN16
104319. DMA_AXI_BLEN256
104320. DMA_AXI_BLEN32
104321. DMA_AXI_BLEN4
104322. DMA_AXI_BLEN64
104323. DMA_AXI_BLEN8
104324. DMA_AXI_BLEN_128
104325. DMA_AXI_BLEN_16
104326. DMA_AXI_BLEN_256
104327. DMA_AXI_BLEN_32
104328. DMA_AXI_BLEN_4
104329. DMA_AXI_BLEN_64
104330. DMA_AXI_BLEN_8
104331. DMA_AXI_BLEN_ALL
104332. DMA_AXI_BURST_LEN_MASK
104333. DMA_AXI_BUS_MODE
104334. DMA_AXI_CTRL_MARPROT
104335. DMA_AXI_CTRL_MAWPROT
104336. DMA_AXI_CTRL_NON_SECURE
104337. DMA_AXI_EN_LPI
104338. DMA_AXI_LPI_XIT_FRM
104339. DMA_AXI_MAX_OSR_LIMIT
104340. DMA_AXI_OSR_MAX
104341. DMA_AXI_RD_OSR_LMT
104342. DMA_AXI_RD_OSR_LMT_MASK
104343. DMA_AXI_RD_OSR_LMT_SHIFT
104344. DMA_AXI_UNDEF
104345. DMA_AXI_WR_OSR_LMT
104346. DMA_AXI_WR_OSR_LMT_MASK
104347. DMA_AXI_WR_OSR_LMT_SHIFT
104348. DMA_A_CHAN0_DONE_INT
104349. DMA_A_CHAN1_DONE_INT
104350. DMA_A_INTERRUPT
104351. DMA_A_INTERRUPT_ENABLE
104352. DMA_Addr_Reg
104353. DMA_BACKPRESSURE_MASK
104354. DMA_BACKPRESSURE_STATUS_MASK
104355. DMA_BAH_BIT
104356. DMA_BAH_MASK
104357. DMA_BAM_H_CLK
104358. DMA_BAM_RESET
104359. DMA_BAR
104360. DMA_BASE
104361. DMA_BASE_2
104362. DMA_BASE_READ
104363. DMA_BASE_WRITE
104364. DMA_BCNT_ENAB
104365. DMA_BCR
104366. DMA_BE
104367. DMA_BE0
104368. DMA_BE1
104369. DMA_BEGINDMA_R
104370. DMA_BEGINDMA_W
104371. DMA_BIDIRECTIONAL
104372. DMA_BIT_MASK
104373. DMA_BIT_MASK_LEN
104374. DMA_BLOCK
104375. DMA_BLOCK_SIZE
104376. DMA_BLR
104377. DMA_BOUNDARY
104378. DMA_BREG
104379. DMA_BRST0
104380. DMA_BRST16
104381. DMA_BRST32
104382. DMA_BRST64
104383. DMA_BRST_SZ
104384. DMA_BUCR
104385. DMA_BUFFER
104386. DMA_BUFFER0_COUNT
104387. DMA_BUFFER0_START
104388. DMA_BUFFER1_COUNT
104389. DMA_BUFFER1_START
104390. DMA_BUFFER_ACK
104391. DMA_BUFFER_ALLOC_NOTIFY
104392. DMA_BUFFER_ALLOC_RESPONSE
104393. DMA_BUFFER_CONTROL
104394. DMA_BUFFER_CURRENT
104395. DMA_BUFFER_DONE_CNT_MASK
104396. DMA_BUFFER_DONE_CNT_SHIFT
104397. DMA_BUFFER_LEN
104398. DMA_BUFFER_SIZE
104399. DMA_BUFFER_VALID
104400. DMA_BUFF_TYPE
104401. DMA_BUFLENGTH_MASK
104402. DMA_BUFLENGTH_SHIFT
104403. DMA_BUF_BASE
104404. DMA_BUF_IOCTL_SYNC
104405. DMA_BUF_LEN
104406. DMA_BUF_MAGIC
104407. DMA_BUF_NAME_LEN
104408. DMA_BUF_SET_NAME
104409. DMA_BUF_SET_NAME_A
104410. DMA_BUF_SET_NAME_B
104411. DMA_BUF_SIZE
104412. DMA_BUF_SIZE_FOR_TRACE
104413. DMA_BUF_SYNC_END
104414. DMA_BUF_SYNC_READ
104415. DMA_BUF_SYNC_RW
104416. DMA_BUF_SYNC_START
104417. DMA_BUF_SYNC_VALID_FLAGS_MASK
104418. DMA_BUF_SYNC_WRITE
104419. DMA_BURST
104420. DMA_BURST1
104421. DMA_BURST16
104422. DMA_BURST2
104423. DMA_BURST32
104424. DMA_BURST4
104425. DMA_BURST64
104426. DMA_BURST8
104427. DMA_BURSTBITS
104428. DMA_BURST_512
104429. DMA_BURST_64
104430. DMA_BURST_DEFAULT
104431. DMA_BURST_LEN_DEFAULT
104432. DMA_BURST_MODE
104433. DMA_BURST_SHIFT
104434. DMA_BURST_SIZE
104435. DMA_BUSY
104436. DMA_BUSY_MASK
104437. DMA_BUSY_TIMEOUT
104438. DMA_BUS_FB
104439. DMA_BUS_MODE
104440. DMA_BUS_MODE_8PBL
104441. DMA_BUS_MODE_AAL
104442. DMA_BUS_MODE_ATDS
104443. DMA_BUS_MODE_BAR_BUS
104444. DMA_BUS_MODE_BLE
104445. DMA_BUS_MODE_DA
104446. DMA_BUS_MODE_DBO
104447. DMA_BUS_MODE_DEFAULT
104448. DMA_BUS_MODE_DSL_MASK
104449. DMA_BUS_MODE_DSL_SHIFT
104450. DMA_BUS_MODE_FB
104451. DMA_BUS_MODE_MAXPBL
104452. DMA_BUS_MODE_MB
104453. DMA_BUS_MODE_PBL
104454. DMA_BUS_MODE_PBL_MASK
104455. DMA_BUS_MODE_PBL_SHIFT
104456. DMA_BUS_MODE_RPBL_MASK
104457. DMA_BUS_MODE_RPBL_SHIFT
104458. DMA_BUS_MODE_SFT_RESET
104459. DMA_BUS_MODE_SPH
104460. DMA_BUS_MODE_USP
104461. DMA_BUS_PR_RATIO_MASK
104462. DMA_BUS_PR_RATIO_SHIFT
104463. DMA_BYTE_COUNT
104464. DMA_BYTE_COUNT_MASK
104465. DMA_B_CHAN0_DONE_INT
104466. DMA_B_CHAN1_DONE_INT
104467. DMA_B_INTERRUPT
104468. DMA_B_INTERRUPT_ENABLE
104469. DMA_CAM_NUM_OF_ENTRIES_FMAN_V2
104470. DMA_CAM_NUM_OF_ENTRIES_FMAN_V3
104471. DMA_CAM_SIZEOF_ENTRY
104472. DMA_CAM_UNITS
104473. DMA_CANCELLED
104474. DMA_CB_START
104475. DMA_CB_STOP_AND_ABORT
104476. DMA_CCMD_DEVICE_INVL
104477. DMA_CCMD_DID
104478. DMA_CCMD_DOMAIN_INVL
104479. DMA_CCMD_FM
104480. DMA_CCMD_GLOBAL_INVL
104481. DMA_CCMD_ICC
104482. DMA_CCMD_INVL_GRANU_OFFSET
104483. DMA_CCMD_MASK_1BIT
104484. DMA_CCMD_MASK_2BIT
104485. DMA_CCMD_MASK_3BIT
104486. DMA_CCMD_MASK_NOBIT
104487. DMA_CCMD_SID
104488. DMA_CCNR
104489. DMA_CCR
104490. DMA_CCR_EVT_DATA_RW
104491. DMA_CCR_EVT_DESP_READ
104492. DMA_CCR_EVT_EARLY_END
104493. DMA_CCR_EVT_NO_STATUS
104494. DMA_CCR_EVT_OVERRUN
104495. DMA_CCR_EVT_SUCCESS
104496. DMA_CCR_EVT_UNDERRUN
104497. DMA_CCR_IF_TO_PERIPHERAL
104498. DMA_CCR_PERIPHERAL_TO_IF
104499. DMA_CCR_RUN
104500. DMA_CDB_64B_ADDR
104501. DMA_CDB_ADDR_MSK
104502. DMA_CDB_MSK
104503. DMA_CDB_NO_INT
104504. DMA_CDB_OPC_DCHECK128
104505. DMA_CDB_OPC_DFILL128
104506. DMA_CDB_OPC_MULTICAST
104507. DMA_CDB_OPC_MV_SG1_SG2
104508. DMA_CDB_OPC_NO_OP
104509. DMA_CDB_SG_DST1
104510. DMA_CDB_SG_DST2
104511. DMA_CDB_SG_SRC
104512. DMA_CDB_STATUS_MSK
104513. DMA_CFG
104514. DMA_CFG_A
104515. DMA_CFG_B
104516. DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN
104517. DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK
104518. DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS
104519. DMA_CFG_DESC_TX_0_CMD_EOP_LEN
104520. DMA_CFG_DESC_TX_0_CMD_EOP_MSK
104521. DMA_CFG_DESC_TX_0_CMD_EOP_POS
104522. DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN
104523. DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK
104524. DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS
104525. DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN
104526. DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK
104527. DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS
104528. DMA_CFG_DESC_TX_0_L4_LENGTH_LEN
104529. DMA_CFG_DESC_TX_0_L4_LENGTH_MSK
104530. DMA_CFG_DESC_TX_0_L4_LENGTH_POS
104531. DMA_CFG_DESC_TX_0_L4_TYPE_LEN
104532. DMA_CFG_DESC_TX_0_L4_TYPE_MSK
104533. DMA_CFG_DESC_TX_0_L4_TYPE_POS
104534. DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN
104535. DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK
104536. DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS
104537. DMA_CFG_DESC_TX_0_QID_LEN
104538. DMA_CFG_DESC_TX_0_QID_MSK
104539. DMA_CFG_DESC_TX_0_QID_POS
104540. DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN
104541. DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK
104542. DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS
104543. DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN
104544. DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK
104545. DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS
104546. DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN
104547. DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK
104548. DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS
104549. DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN
104550. DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK
104551. DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS
104552. DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN
104553. DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK
104554. DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS
104555. DMA_CFG_DFMPP_HHHP
104556. DMA_CFG_DFMPP_HHP
104557. DMA_CFG_DFMPP_HP
104558. DMA_CFG_DFMPP_LP
104559. DMA_CFG_DXEPR_HHHP
104560. DMA_CFG_DXEPR_HHP
104561. DMA_CFG_DXEPR_HP
104562. DMA_CFG_DXEPR_LP
104563. DMA_CFG_FALGN
104564. DMA_CFG_RES
104565. DMA_CFG_msk2DET
104566. DMA_CFG_mskNCHN
104567. DMA_CFG_mskUNEA
104568. DMA_CFG_mskVER
104569. DMA_CFG_off2DET
104570. DMA_CFG_offNCHN
104571. DMA_CFG_offUNEA
104572. DMA_CFG_offVER
104573. DMA_CH5
104574. DMA_CH5_CH6
104575. DMA_CH6
104576. DMA_CH6_CH7
104577. DMA_CH7
104578. DMA_CH7_CH5
104579. DMA_CHAIN_COUNT
104580. DMA_CHAIN_NOTSTARTED
104581. DMA_CHAIN_STARTED
104582. DMA_CHAN0_DBG_STAT_RPS
104583. DMA_CHAN0_DBG_STAT_RPS_SHIFT
104584. DMA_CHAN0_DBG_STAT_TPS
104585. DMA_CHAN0_DBG_STAT_TPS_SHIFT
104586. DMA_CHANNEL
104587. DMA_CHANNELS
104588. DMA_CHANNELS_MAX
104589. DMA_CHANNEL_0_INTERRUPT_ACTIVE
104590. DMA_CHANNEL_0_TEST
104591. DMA_CHANNEL_1_INTERRUPT_ACTIVE
104592. DMA_CHANNEL_1_TEST
104593. DMA_CHANNEL_ENABLE
104594. DMA_CHANNEL_INTERRUPT_SELECT
104595. DMA_CHANNEL_LEN
104596. DMA_CHANNEL_NB_MAX
104597. DMA_CHANNEL_SEL
104598. DMA_CHANNEL_TIMEOUT
104599. DMA_CHANS
104600. DMA_CHANX_BASE_ADDR
104601. DMA_CHAN_ACT_BIT
104602. DMA_CHAN_ALLOTED
104603. DMA_CHAN_BASE_ADDR
104604. DMA_CHAN_BASE_OFFSET
104605. DMA_CHAN_BITS
104606. DMA_CHAN_CFG_DST_BURST_A31
104607. DMA_CHAN_CFG_DST_BURST_H3
104608. DMA_CHAN_CFG_DST_DRQ_A31
104609. DMA_CHAN_CFG_DST_DRQ_H6
104610. DMA_CHAN_CFG_DST_MODE_A31
104611. DMA_CHAN_CFG_DST_MODE_H6
104612. DMA_CHAN_CFG_DST_WIDTH
104613. DMA_CHAN_CFG_SRC_BURST_A31
104614. DMA_CHAN_CFG_SRC_BURST_H3
104615. DMA_CHAN_CFG_SRC_DRQ_A31
104616. DMA_CHAN_CFG_SRC_DRQ_H6
104617. DMA_CHAN_CFG_SRC_MODE_A31
104618. DMA_CHAN_CFG_SRC_MODE_H6
104619. DMA_CHAN_CFG_SRC_WIDTH
104620. DMA_CHAN_CONTROL
104621. DMA_CHAN_COUNT
104622. DMA_CHAN_CTRL
104623. DMA_CHAN_CTRL_BUSY
104624. DMA_CHAN_CTRL_ENABLE
104625. DMA_CHAN_CTRL_LINK
104626. DMA_CHAN_CUR_CFG
104627. DMA_CHAN_CUR_CNT
104628. DMA_CHAN_CUR_DST
104629. DMA_CHAN_CUR_PARA
104630. DMA_CHAN_CUR_RX_BUF_ADDR
104631. DMA_CHAN_CUR_RX_DESC
104632. DMA_CHAN_CUR_SRC
104633. DMA_CHAN_CUR_TX_BUF_ADDR
104634. DMA_CHAN_CUR_TX_DESC
104635. DMA_CHAN_DONE_BIT
104636. DMA_CHAN_ENABLE
104637. DMA_CHAN_ENABLE_START
104638. DMA_CHAN_ENABLE_STOP
104639. DMA_CHAN_ETH_RCV
104640. DMA_CHAN_ETH_XMT
104641. DMA_CHAN_FIFO_TO_MEM
104642. DMA_CHAN_INTR_ABNORMAL
104643. DMA_CHAN_INTR_ABNORMAL_4_10
104644. DMA_CHAN_INTR_DEFAULT_MASK
104645. DMA_CHAN_INTR_DEFAULT_MASK_4_10
104646. DMA_CHAN_INTR_ENA
104647. DMA_CHAN_INTR_ENA_AIE
104648. DMA_CHAN_INTR_ENA_AIE_4_10
104649. DMA_CHAN_INTR_ENA_CDE
104650. DMA_CHAN_INTR_ENA_ERE
104651. DMA_CHAN_INTR_ENA_ETE
104652. DMA_CHAN_INTR_ENA_FBE
104653. DMA_CHAN_INTR_ENA_NIE
104654. DMA_CHAN_INTR_ENA_NIE_4_10
104655. DMA_CHAN_INTR_ENA_RBUE
104656. DMA_CHAN_INTR_ENA_RIE
104657. DMA_CHAN_INTR_ENA_RSE
104658. DMA_CHAN_INTR_ENA_RWE
104659. DMA_CHAN_INTR_ENA_TBUE
104660. DMA_CHAN_INTR_ENA_TIE
104661. DMA_CHAN_INTR_ENA_TSE
104662. DMA_CHAN_INTR_NORMAL
104663. DMA_CHAN_INTR_NORMAL_4_10
104664. DMA_CHAN_INVALID
104665. DMA_CHAN_LLI_ADDR
104666. DMA_CHAN_MAX_DRQ_A31
104667. DMA_CHAN_MAX_DRQ_H6
104668. DMA_CHAN_MEM_TO_FIFO
104669. DMA_CHAN_MEM_TO_PCI
104670. DMA_CHAN_MODE_AUTO
104671. DMA_CHAN_MODE_BIT
104672. DMA_CHAN_MODE_BURST
104673. DMA_CHAN_MODE_MSK
104674. DMA_CHAN_MODE_RSVD
104675. DMA_CHAN_MODE_XFRT
104676. DMA_CHAN_NOT_ALLOTED
104677. DMA_CHAN_OFFSET
104678. DMA_CHAN_ON
104679. DMA_CHAN_PAUSE
104680. DMA_CHAN_PAUSE_PAUSE
104681. DMA_CHAN_PAUSE_RESUME
104682. DMA_CHAN_PCI_TO_MEM
104683. DMA_CHAN_REG_NUMBER
104684. DMA_CHAN_RST
104685. DMA_CHAN_RUN_BIT
104686. DMA_CHAN_RX_BASE_ADDR
104687. DMA_CHAN_RX_CONTROL
104688. DMA_CHAN_RX_END_ADDR
104689. DMA_CHAN_RX_RING_LEN
104690. DMA_CHAN_RX_WATCHDOG
104691. DMA_CHAN_SIZE
104692. DMA_CHAN_SLOT_CTRL_STATUS
104693. DMA_CHAN_STAT
104694. DMA_CHAN_STATUS
104695. DMA_CHAN_STATUS_AIS
104696. DMA_CHAN_STATUS_CDE
104697. DMA_CHAN_STATUS_ERI
104698. DMA_CHAN_STATUS_ETI
104699. DMA_CHAN_STATUS_FBE
104700. DMA_CHAN_STATUS_NIS
104701. DMA_CHAN_STATUS_RBU
104702. DMA_CHAN_STATUS_REB
104703. DMA_CHAN_STATUS_REB_SHIFT
104704. DMA_CHAN_STATUS_RI
104705. DMA_CHAN_STATUS_RPS
104706. DMA_CHAN_STATUS_RWT
104707. DMA_CHAN_STATUS_TBU
104708. DMA_CHAN_STATUS_TEB
104709. DMA_CHAN_STATUS_TEB_SHIFT
104710. DMA_CHAN_STATUS_TI
104711. DMA_CHAN_STATUS_TPS
104712. DMA_CHAN_STAT_ISOPKT
104713. DMA_CHAN_STAT_PCIERR
104714. DMA_CHAN_STAT_PKTCMPL
104715. DMA_CHAN_STAT_PKTERR
104716. DMA_CHAN_STAT_SELFID
104717. DMA_CHAN_STAT_SPECIALACK
104718. DMA_CHAN_TX_BASE_ADDR
104719. DMA_CHAN_TX_CONTROL
104720. DMA_CHAN_TX_END_ADDR
104721. DMA_CHAN_TX_RING_LEN
104722. DMA_CHNSEL_mskCHAN
104723. DMA_CHNSEL_offCHAN
104724. DMA_CHN_CFG
104725. DMA_CHUNKSIZE
104726. DMA_CHUNK_SIZE
104727. DMA_CH_0_BMON_0_MAX_OFFSET
104728. DMA_CH_0_BMON_0_SECTION
104729. DMA_CH_0_BMON_1_MAX_OFFSET
104730. DMA_CH_0_BMON_1_SECTION
104731. DMA_CH_0_BMON_CTI_MAX_OFFSET
104732. DMA_CH_0_BMON_CTI_SECTION
104733. DMA_CH_0_CFG0_RD_MAX_OUTSTAND_MASK
104734. DMA_CH_0_CFG0_RD_MAX_OUTSTAND_SHIFT
104735. DMA_CH_0_CFG0_WR_MAX_OUTSTAND_MASK
104736. DMA_CH_0_CFG0_WR_MAX_OUTSTAND_SHIFT
104737. DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_MASK
104738. DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_SHIFT
104739. DMA_CH_0_CFG2_FORCE_WORD_MASK
104740. DMA_CH_0_CFG2_FORCE_WORD_SHIFT
104741. DMA_CH_0_COMIT_TRANSFER_CTL_MASK
104742. DMA_CH_0_COMIT_TRANSFER_CTL_SHIFT
104743. DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_MASK
104744. DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_SHIFT
104745. DMA_CH_0_COMIT_TRANSFER_MEM_SET_MASK
104746. DMA_CH_0_COMIT_TRANSFER_MEM_SET_SHIFT
104747. DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_MASK
104748. DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_SHIFT
104749. DMA_CH_0_COMIT_TRANSFER_NOSNOOP_MASK
104750. DMA_CH_0_COMIT_TRANSFER_NOSNOOP_SHIFT
104751. DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_MASK
104752. DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_SHIFT
104753. DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_MASK
104754. DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_SHIFT
104755. DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_MASK
104756. DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_SHIFT
104757. DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_MASK
104758. DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_SHIFT
104759. DMA_CH_0_CS_CTI_MAX_OFFSET
104760. DMA_CH_0_CS_CTI_SECTION
104761. DMA_CH_0_CS_ETF_MAX_OFFSET
104762. DMA_CH_0_CS_ETF_SECTION
104763. DMA_CH_0_CS_SPMU_MAX_OFFSET
104764. DMA_CH_0_CS_SPMU_SECTION
104765. DMA_CH_0_CS_STM_MAX_OFFSET
104766. DMA_CH_0_CS_STM_SECTION
104767. DMA_CH_0_DST_ADDR_HI_STS_VAL_MASK
104768. DMA_CH_0_DST_ADDR_HI_STS_VAL_SHIFT
104769. DMA_CH_0_DST_ADDR_LO_STS_VAL_MASK
104770. DMA_CH_0_DST_ADDR_LO_STS_VAL_SHIFT
104771. DMA_CH_0_DST_TSIZE_STS_VAL_MASK
104772. DMA_CH_0_DST_TSIZE_STS_VAL_SHIFT
104773. DMA_CH_0_ERRMSG_ADDR_HI_VAL_MASK
104774. DMA_CH_0_ERRMSG_ADDR_HI_VAL_SHIFT
104775. DMA_CH_0_ERRMSG_ADDR_LO_VAL_MASK
104776. DMA_CH_0_ERRMSG_ADDR_LO_VAL_SHIFT
104777. DMA_CH_0_ERRMSG_WDATA_VAL_MASK
104778. DMA_CH_0_ERRMSG_WDATA_VAL_SHIFT
104779. DMA_CH_0_LDMA_DST_ADDR_HI_VAL_MASK
104780. DMA_CH_0_LDMA_DST_ADDR_HI_VAL_SHIFT
104781. DMA_CH_0_LDMA_DST_ADDR_LO_VAL_MASK
104782. DMA_CH_0_LDMA_DST_ADDR_LO_VAL_SHIFT
104783. DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_MASK
104784. DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_SHIFT
104785. DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_MASK
104786. DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_SHIFT
104787. DMA_CH_0_LDMA_TSIZE_VAL_MASK
104788. DMA_CH_0_LDMA_TSIZE_VAL_SHIFT
104789. DMA_CH_0_MAX_OFFSET
104790. DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_MASK
104791. DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_SHIFT
104792. DMA_CH_0_MEM_INIT_BUSY_SBC_MD_MASK
104793. DMA_CH_0_MEM_INIT_BUSY_SBC_MD_SHIFT
104794. DMA_CH_0_RD_COMP_ADDR_HI_VAL_MASK
104795. DMA_CH_0_RD_COMP_ADDR_HI_VAL_SHIFT
104796. DMA_CH_0_RD_COMP_ADDR_LO_VAL_MASK
104797. DMA_CH_0_RD_COMP_ADDR_LO_VAL_SHIFT
104798. DMA_CH_0_RD_COMP_WDATA_VAL_MASK
104799. DMA_CH_0_RD_COMP_WDATA_VAL_SHIFT
104800. DMA_CH_0_RD_RATE_LIM_EN_VAL_MASK
104801. DMA_CH_0_RD_RATE_LIM_EN_VAL_SHIFT
104802. DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_MASK
104803. DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT
104804. DMA_CH_0_RD_RATE_LIM_SAT_VAL_MASK
104805. DMA_CH_0_RD_RATE_LIM_SAT_VAL_SHIFT
104806. DMA_CH_0_RD_RATE_LIM_TOUT_VAL_MASK
104807. DMA_CH_0_RD_RATE_LIM_TOUT_VAL_SHIFT
104808. DMA_CH_0_SECTION
104809. DMA_CH_0_SRC_ADDR_HI_STS_VAL_MASK
104810. DMA_CH_0_SRC_ADDR_HI_STS_VAL_SHIFT
104811. DMA_CH_0_SRC_ADDR_LO_STS_VAL_MASK
104812. DMA_CH_0_SRC_ADDR_LO_STS_VAL_SHIFT
104813. DMA_CH_0_SRC_TSIZE_STS_VAL_MASK
104814. DMA_CH_0_SRC_TSIZE_STS_VAL_SHIFT
104815. DMA_CH_0_STS0_DMA_BUSY_MASK
104816. DMA_CH_0_STS0_DMA_BUSY_SHIFT
104817. DMA_CH_0_STS0_RD_STS_CTX_FULL_MASK
104818. DMA_CH_0_STS0_RD_STS_CTX_FULL_SHIFT
104819. DMA_CH_0_STS0_WR_STS_CTX_FULL_MASK
104820. DMA_CH_0_STS0_WR_STS_CTX_FULL_SHIFT
104821. DMA_CH_0_STS1_RD_STS_CTX_CNT_MASK
104822. DMA_CH_0_STS1_RD_STS_CTX_CNT_SHIFT
104823. DMA_CH_0_STS2_WR_STS_CTX_CNT_MASK
104824. DMA_CH_0_STS2_WR_STS_CTX_CNT_SHIFT
104825. DMA_CH_0_STS3_RD_STS_TRN_CNT_MASK
104826. DMA_CH_0_STS3_RD_STS_TRN_CNT_SHIFT
104827. DMA_CH_0_STS4_WR_STS_TRN_CNT_MASK
104828. DMA_CH_0_STS4_WR_STS_TRN_CNT_SHIFT
104829. DMA_CH_0_TDMA_CTL_DTYPE_MASK
104830. DMA_CH_0_TDMA_CTL_DTYPE_SHIFT
104831. DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_MASK
104832. DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_SHIFT
104833. DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_MASK
104834. DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_SHIFT
104835. DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_MASK
104836. DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_SHIFT
104837. DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_MASK
104838. DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_SHIFT
104839. DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_MASK
104840. DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_SHIFT
104841. DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_MASK
104842. DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_SHIFT
104843. DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_MASK
104844. DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_SHIFT
104845. DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_MASK
104846. DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_SHIFT
104847. DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_MASK
104848. DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_SHIFT
104849. DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_MASK
104850. DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_SHIFT
104851. DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_MASK
104852. DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_SHIFT
104853. DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_MASK
104854. DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_SHIFT
104855. DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_MASK
104856. DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_SHIFT
104857. DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_MASK
104858. DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_SHIFT
104859. DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_MASK
104860. DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_SHIFT
104861. DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_MASK
104862. DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_SHIFT
104863. DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_MASK
104864. DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_SHIFT
104865. DMA_CH_0_TDMA_DST_STRIDE_0_VAL_MASK
104866. DMA_CH_0_TDMA_DST_STRIDE_0_VAL_SHIFT
104867. DMA_CH_0_TDMA_DST_STRIDE_1_VAL_MASK
104868. DMA_CH_0_TDMA_DST_STRIDE_1_VAL_SHIFT
104869. DMA_CH_0_TDMA_DST_STRIDE_2_VAL_MASK
104870. DMA_CH_0_TDMA_DST_STRIDE_2_VAL_SHIFT
104871. DMA_CH_0_TDMA_DST_STRIDE_3_VAL_MASK
104872. DMA_CH_0_TDMA_DST_STRIDE_3_VAL_SHIFT
104873. DMA_CH_0_TDMA_DST_STRIDE_4_VAL_MASK
104874. DMA_CH_0_TDMA_DST_STRIDE_4_VAL_SHIFT
104875. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_MASK
104876. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_SHIFT
104877. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_MASK
104878. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_SHIFT
104879. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_MASK
104880. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_SHIFT
104881. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_MASK
104882. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_SHIFT
104883. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_MASK
104884. DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_SHIFT
104885. DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_MASK
104886. DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_SHIFT
104887. DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_MASK
104888. DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_SHIFT
104889. DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_MASK
104890. DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_SHIFT
104891. DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_MASK
104892. DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_SHIFT
104893. DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_MASK
104894. DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_SHIFT
104895. DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_MASK
104896. DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_SHIFT
104897. DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_MASK
104898. DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_SHIFT
104899. DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_MASK
104900. DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_SHIFT
104901. DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_MASK
104902. DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_SHIFT
104903. DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_MASK
104904. DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_SHIFT
104905. DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_MASK
104906. DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_SHIFT
104907. DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_MASK
104908. DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_SHIFT
104909. DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_MASK
104910. DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_SHIFT
104911. DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_MASK
104912. DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_SHIFT
104913. DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_MASK
104914. DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_SHIFT
104915. DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_MASK
104916. DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_SHIFT
104917. DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_MASK
104918. DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_SHIFT
104919. DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_MASK
104920. DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_SHIFT
104921. DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_MASK
104922. DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_SHIFT
104923. DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_MASK
104924. DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_SHIFT
104925. DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_MASK
104926. DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_SHIFT
104927. DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_MASK
104928. DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_SHIFT
104929. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_MASK
104930. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_SHIFT
104931. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_MASK
104932. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_SHIFT
104933. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_MASK
104934. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_SHIFT
104935. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_MASK
104936. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_SHIFT
104937. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_MASK
104938. DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_SHIFT
104939. DMA_CH_0_USER_CTI_MAX_OFFSET
104940. DMA_CH_0_USER_CTI_SECTION
104941. DMA_CH_0_WR_COMP_ADDR_HI_VAL_MASK
104942. DMA_CH_0_WR_COMP_ADDR_HI_VAL_SHIFT
104943. DMA_CH_0_WR_COMP_ADDR_LO_VAL_MASK
104944. DMA_CH_0_WR_COMP_ADDR_LO_VAL_SHIFT
104945. DMA_CH_0_WR_COMP_WDATA_VAL_MASK
104946. DMA_CH_0_WR_COMP_WDATA_VAL_SHIFT
104947. DMA_CH_0_WR_RATE_LIM_EN_VAL_MASK
104948. DMA_CH_0_WR_RATE_LIM_EN_VAL_SHIFT
104949. DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_MASK
104950. DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_SHIFT
104951. DMA_CH_0_WR_RATE_LIM_SAT_VAL_MASK
104952. DMA_CH_0_WR_RATE_LIM_SAT_VAL_SHIFT
104953. DMA_CH_0_WR_RATE_LIM_TOUT_VAL_MASK
104954. DMA_CH_0_WR_RATE_LIM_TOUT_VAL_SHIFT
104955. DMA_CH_1_BMON_0_MAX_OFFSET
104956. DMA_CH_1_BMON_0_SECTION
104957. DMA_CH_1_BMON_1_MAX_OFFSET
104958. DMA_CH_1_BMON_1_SECTION
104959. DMA_CH_1_BMON_CTI_MAX_OFFSET
104960. DMA_CH_1_BMON_CTI_SECTION
104961. DMA_CH_1_CS_CTI_MAX_OFFSET
104962. DMA_CH_1_CS_CTI_SECTION
104963. DMA_CH_1_CS_ETF_MAX_OFFSET
104964. DMA_CH_1_CS_ETF_SECTION
104965. DMA_CH_1_CS_SPMU_MAX_OFFSET
104966. DMA_CH_1_CS_SPMU_SECTION
104967. DMA_CH_1_CS_STM_MAX_OFFSET
104968. DMA_CH_1_CS_STM_SECTION
104969. DMA_CH_1_MAX_OFFSET
104970. DMA_CH_1_SECTION
104971. DMA_CH_1_USER_CTI_MAX_OFFSET
104972. DMA_CH_1_USER_CTI_SECTION
104973. DMA_CH_2_BMON_0_MAX_OFFSET
104974. DMA_CH_2_BMON_0_SECTION
104975. DMA_CH_2_BMON_1_MAX_OFFSET
104976. DMA_CH_2_BMON_1_SECTION
104977. DMA_CH_2_BMON_CTI_MAX_OFFSET
104978. DMA_CH_2_BMON_CTI_SECTION
104979. DMA_CH_2_CS_CTI_MAX_OFFSET
104980. DMA_CH_2_CS_CTI_SECTION
104981. DMA_CH_2_CS_ETF_MAX_OFFSET
104982. DMA_CH_2_CS_ETF_SECTION
104983. DMA_CH_2_CS_SPMU_MAX_OFFSET
104984. DMA_CH_2_CS_SPMU_SECTION
104985. DMA_CH_2_CS_STM_MAX_OFFSET
104986. DMA_CH_2_CS_STM_SECTION
104987. DMA_CH_2_MAX_OFFSET
104988. DMA_CH_2_SECTION
104989. DMA_CH_2_USER_CTI_MAX_OFFSET
104990. DMA_CH_2_USER_CTI_SECTION
104991. DMA_CH_3_BMON_0_MAX_OFFSET
104992. DMA_CH_3_BMON_0_SECTION
104993. DMA_CH_3_BMON_1_MAX_OFFSET
104994. DMA_CH_3_BMON_1_SECTION
104995. DMA_CH_3_BMON_CTI_MAX_OFFSET
104996. DMA_CH_3_BMON_CTI_SECTION
104997. DMA_CH_3_CS_CTI_MAX_OFFSET
104998. DMA_CH_3_CS_CTI_SECTION
104999. DMA_CH_3_CS_ETF_MAX_OFFSET
105000. DMA_CH_3_CS_ETF_SECTION
105001. DMA_CH_3_CS_SPMU_MAX_OFFSET
105002. DMA_CH_3_CS_SPMU_SECTION
105003. DMA_CH_3_CS_STM_MAX_OFFSET
105004. DMA_CH_3_CS_STM_SECTION
105005. DMA_CH_3_MAX_OFFSET
105006. DMA_CH_3_SECTION
105007. DMA_CH_3_USER_CTI_MAX_OFFSET
105008. DMA_CH_3_USER_CTI_SECTION
105009. DMA_CH_4_BMON_0_MAX_OFFSET
105010. DMA_CH_4_BMON_0_SECTION
105011. DMA_CH_4_BMON_1_MAX_OFFSET
105012. DMA_CH_4_BMON_1_SECTION
105013. DMA_CH_4_BMON_CTI_MAX_OFFSET
105014. DMA_CH_4_BMON_CTI_SECTION
105015. DMA_CH_4_CS_CTI_MAX_OFFSET
105016. DMA_CH_4_CS_CTI_SECTION
105017. DMA_CH_4_CS_ETF_MAX_OFFSET
105018. DMA_CH_4_CS_ETF_SECTION
105019. DMA_CH_4_CS_SPMU_MAX_OFFSET
105020. DMA_CH_4_CS_SPMU_SECTION
105021. DMA_CH_4_CS_STM_MAX_OFFSET
105022. DMA_CH_4_CS_STM_SECTION
105023. DMA_CH_4_MAX_OFFSET
105024. DMA_CH_4_SECTION
105025. DMA_CH_4_USER_CTI_MAX_OFFSET
105026. DMA_CH_4_USER_CTI_SECTION
105027. DMA_CH_ALLOC_DONE
105028. DMA_CH_BASE
105029. DMA_CH_CARBR_HI
105030. DMA_CH_CARBR_LO
105031. DMA_CH_CARDR_LO
105032. DMA_CH_CATBR_HI
105033. DMA_CH_CATBR_LO
105034. DMA_CH_CATDR_LO
105035. DMA_CH_CR
105036. DMA_CH_CR_PBLX8_INDEX
105037. DMA_CH_CR_PBLX8_LEN
105038. DMA_CH_CR_PBLX8_POS
105039. DMA_CH_CR_PBLX8_WIDTH
105040. DMA_CH_CR_SPH_INDEX
105041. DMA_CH_CR_SPH_LEN
105042. DMA_CH_CR_SPH_POS
105043. DMA_CH_CR_SPH_WIDTH
105044. DMA_CH_FUNNEL_6_1_MAX_OFFSET
105045. DMA_CH_FUNNEL_6_1_SECTION
105046. DMA_CH_IER
105047. DMA_CH_IER_AIE20_INDEX
105048. DMA_CH_IER_AIE20_WIDTH
105049. DMA_CH_IER_AIE_INDEX
105050. DMA_CH_IER_AIE_LEN
105051. DMA_CH_IER_AIE_POS
105052. DMA_CH_IER_AIE_WIDTH
105053. DMA_CH_IER_FBEE_INDEX
105054. DMA_CH_IER_FBEE_LEN
105055. DMA_CH_IER_FBEE_POS
105056. DMA_CH_IER_FBEE_WIDTH
105057. DMA_CH_IER_NIE20_INDEX
105058. DMA_CH_IER_NIE20_WIDTH
105059. DMA_CH_IER_NIE_INDEX
105060. DMA_CH_IER_NIE_LEN
105061. DMA_CH_IER_NIE_POS
105062. DMA_CH_IER_NIE_WIDTH
105063. DMA_CH_IER_RBUE_INDEX
105064. DMA_CH_IER_RBUE_LEN
105065. DMA_CH_IER_RBUE_POS
105066. DMA_CH_IER_RBUE_WIDTH
105067. DMA_CH_IER_RIE_INDEX
105068. DMA_CH_IER_RIE_LEN
105069. DMA_CH_IER_RIE_POS
105070. DMA_CH_IER_RIE_WIDTH
105071. DMA_CH_IER_RSE_INDEX
105072. DMA_CH_IER_RSE_LEN
105073. DMA_CH_IER_RSE_POS
105074. DMA_CH_IER_RSE_WIDTH
105075. DMA_CH_IER_TBUE_INDEX
105076. DMA_CH_IER_TBUE_LEN
105077. DMA_CH_IER_TBUE_POS
105078. DMA_CH_IER_TBUE_WIDTH
105079. DMA_CH_IER_TIE_INDEX
105080. DMA_CH_IER_TIE_LEN
105081. DMA_CH_IER_TIE_POS
105082. DMA_CH_IER_TIE_WIDTH
105083. DMA_CH_IER_TXSE_INDEX
105084. DMA_CH_IER_TXSE_LEN
105085. DMA_CH_IER_TXSE_POS
105086. DMA_CH_IER_TXSE_WIDTH
105087. DMA_CH_INC
105088. DMA_CH_LINK_ENABLED
105089. DMA_CH_NOTSTARTED
105090. DMA_CH_PARAMS_SET_DONE
105091. DMA_CH_PAUSED
105092. DMA_CH_PRIO_HIGH
105093. DMA_CH_PRIO_LOW
105094. DMA_CH_QUEUED
105095. DMA_CH_RCR
105096. DMA_CH_RCR_PBL_INDEX
105097. DMA_CH_RCR_PBL_LEN
105098. DMA_CH_RCR_PBL_POS
105099. DMA_CH_RCR_PBL_WIDTH
105100. DMA_CH_RCR_RBSZ_INDEX
105101. DMA_CH_RCR_RBSZ_LEN
105102. DMA_CH_RCR_RBSZ_POS
105103. DMA_CH_RCR_RBSZ_WIDTH
105104. DMA_CH_RCR_SR_INDEX
105105. DMA_CH_RCR_SR_LEN
105106. DMA_CH_RCR_SR_POS
105107. DMA_CH_RCR_SR_WIDTH
105108. DMA_CH_RDLR_HI
105109. DMA_CH_RDLR_LO
105110. DMA_CH_RDRLR
105111. DMA_CH_RDTR_LO
105112. DMA_CH_RIWT
105113. DMA_CH_RIWT_RWT_INDEX
105114. DMA_CH_RIWT_RWT_LEN
105115. DMA_CH_RIWT_RWT_POS
105116. DMA_CH_RIWT_RWT_WIDTH
105117. DMA_CH_SELECT_BIT
105118. DMA_CH_SR
105119. DMA_CH_SR_FBE_INDEX
105120. DMA_CH_SR_FBE_LEN
105121. DMA_CH_SR_FBE_POS
105122. DMA_CH_SR_FBE_WIDTH
105123. DMA_CH_SR_RBU_INDEX
105124. DMA_CH_SR_RBU_LEN
105125. DMA_CH_SR_RBU_POS
105126. DMA_CH_SR_RBU_WIDTH
105127. DMA_CH_SR_RI_INDEX
105128. DMA_CH_SR_RI_LEN
105129. DMA_CH_SR_RI_POS
105130. DMA_CH_SR_RI_WIDTH
105131. DMA_CH_SR_RPS_INDEX
105132. DMA_CH_SR_RPS_LEN
105133. DMA_CH_SR_RPS_POS
105134. DMA_CH_SR_RPS_WIDTH
105135. DMA_CH_SR_TBU_INDEX
105136. DMA_CH_SR_TBU_LEN
105137. DMA_CH_SR_TBU_POS
105138. DMA_CH_SR_TBU_WIDTH
105139. DMA_CH_SR_TI_INDEX
105140. DMA_CH_SR_TI_LEN
105141. DMA_CH_SR_TI_POS
105142. DMA_CH_SR_TI_WIDTH
105143. DMA_CH_SR_TPS_INDEX
105144. DMA_CH_SR_TPS_LEN
105145. DMA_CH_SR_TPS_POS
105146. DMA_CH_SR_TPS_WIDTH
105147. DMA_CH_STARTED
105148. DMA_CH_TCR
105149. DMA_CH_TCR_OSP_INDEX
105150. DMA_CH_TCR_OSP_LEN
105151. DMA_CH_TCR_OSP_POS
105152. DMA_CH_TCR_OSP_WIDTH
105153. DMA_CH_TCR_PBL_INDEX
105154. DMA_CH_TCR_PBL_LEN
105155. DMA_CH_TCR_PBL_POS
105156. DMA_CH_TCR_PBL_WIDTH
105157. DMA_CH_TCR_ST_INDEX
105158. DMA_CH_TCR_ST_LEN
105159. DMA_CH_TCR_ST_POS
105160. DMA_CH_TCR_ST_WIDTH
105161. DMA_CH_TCR_TSE_INDEX
105162. DMA_CH_TCR_TSE_LEN
105163. DMA_CH_TCR_TSE_POS
105164. DMA_CH_TCR_TSE_WIDTH
105165. DMA_CH_TDLR_HI
105166. DMA_CH_TDLR_LO
105167. DMA_CH_TDRLR
105168. DMA_CH_TDTR_LO
105169. DMA_CLASS_EN
105170. DMA_CLEAR
105171. DMA_CLEAR_COUNT_ENABLE
105172. DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK
105173. DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK
105174. DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105175. DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK
105176. DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK
105177. DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105178. DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK
105179. DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105180. DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105181. DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK
105182. DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105183. DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105184. DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK
105185. DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK
105186. DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT
105187. DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK
105188. DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK
105189. DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT
105190. DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK
105191. DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK
105192. DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105193. DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK
105194. DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK
105195. DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105196. DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK
105197. DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105198. DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105199. DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK
105200. DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105201. DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105202. DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK
105203. DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK
105204. DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT
105205. DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK
105206. DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK
105207. DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT
105208. DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK
105209. DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105210. DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK
105211. DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105212. DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105213. DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105214. DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105215. DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105216. DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK
105217. DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT
105218. DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK
105219. DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT
105220. DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK
105221. DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105222. DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK
105223. DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105224. DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105225. DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105226. DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105227. DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105228. DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK
105229. DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT
105230. DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK
105231. DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT
105232. DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK
105233. DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105234. DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK
105235. DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105236. DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105237. DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105238. DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105239. DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105240. DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK
105241. DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT
105242. DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK
105243. DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT
105244. DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK
105245. DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105246. DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK
105247. DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105248. DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105249. DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105250. DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105251. DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105252. DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK
105253. DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT
105254. DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK
105255. DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT
105256. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK
105257. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK
105258. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT
105259. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK
105260. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK
105261. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT
105262. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK
105263. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK
105264. DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT
105265. DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK
105266. DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105267. DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK
105268. DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105269. DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105270. DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105271. DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105272. DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105273. DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK
105274. DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT
105275. DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK
105276. DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT
105277. DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK
105278. DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT
105279. DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK
105280. DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT
105281. DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK
105282. DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT
105283. DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK
105284. DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105285. DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK
105286. DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105287. DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105288. DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105289. DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105290. DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105291. DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK
105292. DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT
105293. DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK
105294. DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT
105295. DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK
105296. DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105297. DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK
105298. DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105299. DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105300. DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105301. DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105302. DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105303. DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK
105304. DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT
105305. DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK
105306. DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT
105307. DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK
105308. DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105309. DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK
105310. DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105311. DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105312. DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105313. DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105314. DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105315. DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK
105316. DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT
105317. DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK
105318. DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT
105319. DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK
105320. DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105321. DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK
105322. DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105323. DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105324. DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105325. DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105326. DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105327. DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK
105328. DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT
105329. DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK
105330. DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT
105331. DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK
105332. DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105333. DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK
105334. DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105335. DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105336. DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105337. DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105338. DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105339. DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK
105340. DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT
105341. DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK
105342. DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT
105343. DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK
105344. DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105345. DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK
105346. DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105347. DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105348. DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105349. DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105350. DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105351. DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK
105352. DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT
105353. DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK
105354. DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT
105355. DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK
105356. DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT
105357. DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK
105358. DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT
105359. DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK
105360. DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT
105361. DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK
105362. DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105363. DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK
105364. DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105365. DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105366. DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105367. DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105368. DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105369. DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK
105370. DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT
105371. DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK
105372. DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT
105373. DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK
105374. DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105375. DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK
105376. DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105377. DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105378. DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105379. DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105380. DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105381. DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK
105382. DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT
105383. DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK
105384. DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT
105385. DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK
105386. DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105387. DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK
105388. DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105389. DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105390. DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105391. DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105392. DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105393. DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK
105394. DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT
105395. DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK
105396. DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT
105397. DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK
105398. DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105399. DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK
105400. DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105401. DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105402. DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105403. DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105404. DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105405. DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK
105406. DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT
105407. DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK
105408. DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT
105409. DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK
105410. DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT
105411. DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK
105412. DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
105413. DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK
105414. DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT
105415. DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK
105416. DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT
105417. DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK
105418. DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT
105419. DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK
105420. DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT
105421. DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK
105422. DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT
105423. DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK
105424. DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT
105425. DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK
105426. DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT
105427. DMA_CLK_CONTROLS
105428. DMA_CLK_CTRL
105429. DMA_CLK_DIV4
105430. DMA_CLK_ENB
105431. DMA_CMD
105432. DMA_CMD_ENABLE
105433. DMA_CNTL
105434. DMA_CNTR
105435. DMA_CNTR_DISAB
105436. DMA_CNT_0
105437. DMA_CNT_1
105438. DMA_CNT_2
105439. DMA_CNT_3
105440. DMA_CNT_4
105441. DMA_CNT_5
105442. DMA_CNT_6
105443. DMA_CNT_7
105444. DMA_COMMAND
105445. DMA_COMMIT
105446. DMA_COMM_Q_HIGH_FMAN_V2
105447. DMA_COMM_Q_HIGH_FMAN_V3
105448. DMA_COMM_Q_LOW_FMAN_V2
105449. DMA_COMM_Q_LOW_FMAN_V3
105450. DMA_COMPLETE
105451. DMA_COMPLETION_TIMEOUT
105452. DMA_COM_PIPE_NO
105453. DMA_CONFIG
105454. DMA_CONFIGURED
105455. DMA_CONTIG
105456. DMA_CONTROL
105457. DMA_CONTROL_DACK
105458. DMA_CONTROL_DFF
105459. DMA_CONTROL_DT
105460. DMA_CONTROL_EFC
105461. DMA_CONTROL_ENABLE
105462. DMA_CONTROL_FEF
105463. DMA_CONTROL_FTF
105464. DMA_CONTROL_FUF
105465. DMA_CONTROL_ID
105466. DMA_CONTROL_MSS_MASK
105467. DMA_CONTROL_OSF
105468. DMA_CONTROL_OSP
105469. DMA_CONTROL_REG
105470. DMA_CONTROL_RFA_MASK
105471. DMA_CONTROL_RFD_MASK
105472. DMA_CONTROL_RSF
105473. DMA_CONTROL_RST
105474. DMA_CONTROL_RTC_128
105475. DMA_CONTROL_RTC_32
105476. DMA_CONTROL_RTC_64
105477. DMA_CONTROL_RTC_96
105478. DMA_CONTROL_SE
105479. DMA_CONTROL_SF
105480. DMA_CONTROL_SMALL_CB_CONST_VALUE
105481. DMA_CONTROL_SR
105482. DMA_CONTROL_ST
105483. DMA_CONTROL_TC_RX_MASK
105484. DMA_CONTROL_TC_TX_MASK
105485. DMA_CONTROL_TSE
105486. DMA_CONTROL_TSF
105487. DMA_CONTROL_TTC_128
105488. DMA_CONTROL_TTC_16
105489. DMA_CONTROL_TTC_18
105490. DMA_CONTROL_TTC_192
105491. DMA_CONTROL_TTC_24
105492. DMA_CONTROL_TTC_256
105493. DMA_CONTROL_TTC_32
105494. DMA_CONTROL_TTC_40
105495. DMA_CONTROL_TTC_64
105496. DMA_CONTROL_TTC_DEFAULT
105497. DMA_CON_PIPE_DIR
105498. DMA_CON_PIPE_NO_MASK
105499. DMA_CON_PIPE_NO_SHIFT
105500. DMA_CON_PRD_EN
105501. DMA_COPY
105502. DMA_COPY_SIZE
105503. DMA_COUNT
105504. DMA_COUNT_BIT
105505. DMA_COUNT_MASK
105506. DMA_CPU
105507. DMA_CPU_CLOCKGATE
105508. DMA_CPU_ID
105509. DMA_CPU_PC
105510. DMA_CPU_RUN
105511. DMA_CPU_VCR
105512. DMA_CR_C
105513. DMA_CR_D
105514. DMA_CR_E
105515. DMA_CSR
105516. DMA_CSR_DISAB
105517. DMA_CTL0_BITS_PER_CH
105518. DMA_CTL0_DIR_SHIFT_BITS
105519. DMA_CTL0_DISABLE
105520. DMA_CTL0_MODE_MASK_BITS
105521. DMA_CTL0_ONESHOT
105522. DMA_CTL0_SG
105523. DMA_CTL2_IRQ_ENABLE_MASK
105524. DMA_CTL2_START_SHIFT_BITS
105525. DMA_CTL_CMD
105526. DMA_CTL_DACK
105527. DMA_CTRL
105528. DMA_CTRL_ACK
105529. DMA_CTRL_CCLEAR
105530. DMA_CTRL_CIRQ
105531. DMA_CTRL_CSUSPEND
105532. DMA_CTRL_DMAR_BURST_LEN_MASK
105533. DMA_CTRL_DMAR_BURST_LEN_SHIFT
105534. DMA_CTRL_DMAR_DLY_CNT_MASK
105535. DMA_CTRL_DMAR_DLY_CNT_SHIFT
105536. DMA_CTRL_DMAR_EN
105537. DMA_CTRL_DMAR_ENH_ORDER
105538. DMA_CTRL_DMAR_IN_ORDER
105539. DMA_CTRL_DMAR_OUT_ORDER
105540. DMA_CTRL_DMAR_REQ_PRI
105541. DMA_CTRL_DMASTART
105542. DMA_CTRL_DMAW_BURST_LEN_MASK
105543. DMA_CTRL_DMAW_BURST_LEN_SHIFT
105544. DMA_CTRL_DMAW_DLY_CNT_MASK
105545. DMA_CTRL_DMAW_DLY_CNT_SHIFT
105546. DMA_CTRL_DMAW_EN
105547. DMA_CTRL_FCLEAR
105548. DMA_CTRL_FLAGS_LAST
105549. DMA_CTRL_PEN
105550. DMA_CTRL_RCB_VALUE
105551. DMA_CTRL_RDLY_CNT_DEF
105552. DMA_CTRL_RDLY_CNT_MASK
105553. DMA_CTRL_RDLY_CNT_SHIFT
105554. DMA_CTRL_REUSE
105555. DMA_CTRL_ROC
105556. DMA_CTRL_RORDER_MODE_ENHANCE
105557. DMA_CTRL_RORDER_MODE_IN
105558. DMA_CTRL_RORDER_MODE_MASK
105559. DMA_CTRL_RORDER_MODE_OUT
105560. DMA_CTRL_RORDER_MODE_SHIFT
105561. DMA_CTRL_RPEND_CLR
105562. DMA_CTRL_RREQ_BLEN_MASK
105563. DMA_CTRL_RREQ_BLEN_SHIFT
105564. DMA_CTRL_RREQ_PRI_DATA
105565. DMA_CTRL_RXCMB_EN
105566. DMA_CTRL_RXMULTI
105567. DMA_CTRL_SMB_NOW
105568. DMA_CTRL_TXCMB_EN
105569. DMA_CTRL_UNFRAMED
105570. DMA_CTRL_WDLY_CNT_DEF
105571. DMA_CTRL_WDLY_CNT_MASK
105572. DMA_CTRL_WDLY_CNT_SHIFT
105573. DMA_CTRL_WPEND_CLR
105574. DMA_CTRL_WREQ_BLEN_MASK
105575. DMA_CTRL_WREQ_BLEN_SHIFT
105576. DMA_CUED_MULT1_OFF
105577. DMA_CUED_MULT2_OFF
105578. DMA_CUED_MULT3_OFF
105579. DMA_CUED_REGION_MSK
105580. DMA_CUED_REGION_OFF
105581. DMA_CUED_XOR_BASE
105582. DMA_CUED_XOR_HB
105583. DMA_CUED_XOR_WIN_MSK
105584. DMA_CURRENT_PCL
105585. DMA_CURSOR
105586. DMA_CURSOR_SDM845_MASK
105587. DMA_CUR_RX_BUF_ADDR
105588. DMA_CUR_TX_BUF_ADDR
105589. DMA_CYCLIC
105590. DMA_CYCLIC_MAX_PERIOD
105591. DMA_C_CHAN0_DONE_INT
105592. DMA_C_CHAN1_DONE_INT
105593. DMA_C_INDEX_MASK
105594. DMA_C_INTERRUPT
105595. DMA_C_INTERRUPT_ENABLE
105596. DMA_D0
105597. DMA_D1
105598. DMA_DACK_ENABLE
105599. DMA_DAC_MASK
105600. DMA_DAH_MASK
105601. DMA_DAR
105602. DMA_DATA
105603. DMA_DBG_VENDOR_MSG
105604. DMA_DBOSR
105605. DMA_DBSA
105606. DMA_DBSB
105607. DMA_DBTA
105608. DMA_DBTB
105609. DMA_DBTOCR
105610. DMA_DBTOSR
105611. DMA_DCR
105612. DMA_DCSR_C
105613. DMA_DCSR_R
105614. DMA_DCSR_S
105615. DMA_DDAR
105616. DMA_DDMA
105617. DMA_DEBUG_DYNAMIC_ENTRIES
105618. DMA_DEBUG_STACKTRACE_ENTRIES
105619. DMA_DEBUG_STATUS_0
105620. DMA_DEBUG_STATUS_1
105621. DMA_DEBUG_STATUS_2
105622. DMA_DEBUG_STATUS_RS_MASK
105623. DMA_DEBUG_STATUS_TS_MASK
105624. DMA_DEFAULT_ARB_RATE
105625. DMA_DEFAULT_FIFO_DEPTH
105626. DMA_DEM_EN_BIT
105627. DMA_DESCPT
105628. DMA_DESCRIPTOR_ADDR
105629. DMA_DESCRIPTOR_SPACING_128
105630. DMA_DESCRIPTOR_SPACING_16
105631. DMA_DESCRIPTOR_SPACING_32
105632. DMA_DESCRIPTOR_SPACING_64
105633. DMA_DESC_ADDRESS_HI
105634. DMA_DESC_ADDRESS_LO
105635. DMA_DESC_ALIGNMENT
105636. DMA_DESC_ALLOC_MASK
105637. DMA_DESC_COD
105638. DMA_DESC_COF
105639. DMA_DESC_COUNT_BIT
105640. DMA_DESC_COUNT_MSK
105641. DMA_DESC_CTL_AFIFO
105642. DMA_DESC_CTL_EOP
105643. DMA_DESC_CTL_IRQONDONE
105644. DMA_DESC_CTL_IRQONERR
105645. DMA_DESC_CTL_SOP
105646. DMA_DESC_DEV_CMD_16WORDS
105647. DMA_DESC_DEV_CMD_2WORDS
105648. DMA_DESC_DEV_CMD_4WORDS
105649. DMA_DESC_DEV_CMD_6WORDS
105650. DMA_DESC_DEV_CMD_8WORDS
105651. DMA_DESC_DEV_CMD_BIT
105652. DMA_DESC_DEV_CMD_BYTE
105653. DMA_DESC_DEV_CMD_HLF_WD
105654. DMA_DESC_DEV_CMD_MSK
105655. DMA_DESC_DEV_CMD_WORD
105656. DMA_DESC_DONE
105657. DMA_DESC_DS_BIT
105658. DMA_DESC_DS_MSK
105659. DMA_DESC_DUAL_SPI
105660. DMA_DESC_END_WITHOUT_IRQ
105661. DMA_DESC_END_WITH_IRQ
105662. DMA_DESC_ESTS_ECRC
105663. DMA_DESC_ESTS_POISON
105664. DMA_DESC_ESTS_UNSUCCESSFUL
105665. DMA_DESC_FINI
105666. DMA_DESC_FOLLOW_WITHOUT_IRQ
105667. DMA_DESC_FOLLOW_WITH_IRQ
105668. DMA_DESC_HOST
105669. DMA_DESC_IOD
105670. DMA_DESC_IOF
105671. DMA_DESC_LENGTH_STATUS
105672. DMA_DESC_MAX_COUNT_1_BYTE
105673. DMA_DESC_MAX_COUNT_2_BYTES
105674. DMA_DESC_MAX_COUNT_4_BYTES
105675. DMA_DESC_MONOLITHIC
105676. DMA_DESC_QUAD_SPI
105677. DMA_DESC_RAM_INIT_BUSY
105678. DMA_DESC_SINGLE_SPI
105679. DMA_DESC_SIZ
105680. DMA_DESC_SIZE
105681. DMA_DESC_STS_COMPLETE
105682. DMA_DESC_STS_EOP
105683. DMA_DESC_STS_ERROR
105684. DMA_DESC_STS_SHORT
105685. DMA_DESC_STS_SOP
105686. DMA_DESC_STS_USLSZ
105687. DMA_DESC_STS_USMSZ
105688. DMA_DESC_TERM
105689. DMA_DESC_WIDTH_1_BYTE
105690. DMA_DESC_WIDTH_2_BYTES
105691. DMA_DESC_WIDTH_4_BYTES
105692. DMA_DESC_WIDTH_SHIFT_BITS
105693. DMA_DEST_LEN_OFFSET
105694. DMA_DEST_MAX_NUM
105695. DMA_DEVICE_ID
105696. DMA_DEV_TO_DEV
105697. DMA_DEV_TO_MEM
105698. DMA_DID_BIT
105699. DMA_DID_MASK
105700. DMA_DIMR
105701. DMA_DIR
105702. DMA_DIRECTION
105703. DMA_DIRECT_DIRECT
105704. DMA_DIR_FROM_CARD
105705. DMA_DIR_RX
105706. DMA_DIR_TO_CARD
105707. DMA_DIR_TX
105708. DMA_DISABLE
105709. DMA_DISABLED
105710. DMA_DISABLE_TIME
105711. DMA_DISR
105712. DMA_DLLI
105713. DMA_DMEM_OFFSET
105714. DMA_DONE_EN
105715. DMA_DONE_INT
105716. DMA_DONE_INTERRUPT
105717. DMA_DONE_INTERRUPT_ENABLE
105718. DMA_DONE_INT_EN
105719. DMA_DONE_MASK
105720. DMA_DONE_ST
105721. DMA_DONT_USE
105722. DMA_DR
105723. DMA_DRAM_TO_DRAM
105724. DMA_DRAM_TO_HOST
105725. DMA_DRAM_TO_SRAM
105726. DMA_DRAW_PRIMITIVE
105727. DMA_DROP
105728. DMA_DRTOSR
105729. DMA_DS
105730. DMA_DSBL_RD_DRN
105731. DMA_DSBL_WR_INV
105732. DMA_DSCR_CTRL
105733. DMA_DSCR_DEVICE
105734. DMA_DSCR_HOST
105735. DMA_DSCR_NUM
105736. DMA_DSESR
105737. DMA_DSR0
105738. DMA_DSR0_RPS_START
105739. DMA_DSR0_TPS_START
105740. DMA_DSR1
105741. DMA_DSRX_FIRST_QUEUE
105742. DMA_DSRX_INC
105743. DMA_DSRX_QPR
105744. DMA_DSRX_RPS_START
105745. DMA_DSRX_TPS_START
105746. DMA_DSR_Q_LEN
105747. DMA_DSR_Q_WIDTH
105748. DMA_DSR_RPS_LEN
105749. DMA_DSR_RPS_WIDTH
105750. DMA_DSR_TPS_LEN
105751. DMA_DSR_TPS_WIDTH
105752. DMA_DST_ADDR_OFFSET
105753. DMA_DTMR_CLK_DIV_1
105754. DMA_DTMR_CLK_DIV_16
105755. DMA_DTMR_ENABLE
105756. DMA_DTMR_RESTART
105757. DMA_DUAL
105758. DMA_DUMMY_DATA
105759. DMA_DW16
105760. DMA_DW32
105761. DMA_DW8
105762. DMA_DW_BIT
105763. DMA_DW_MASK
105764. DMA_D_CHAN0_DONE_INT
105765. DMA_D_CHAN1_DONE_INT
105766. DMA_D_INTERRUPT
105767. DMA_D_INTERRUPT_ENABLE
105768. DMA_DmBurst_Mask
105769. DMA_E
105770. DMA_ECC_INT_ENABLE
105771. DMA_ECC_INT_STATUS
105772. DMA_EN
105773. DMA_ENABLE
105774. DMA_ENABLED
105775. DMA_ENABLE_DMASDRW
105776. DMA_ENABLE__FLAG
105777. DMA_ENDINT
105778. DMA_ENDINTEN
105779. DMA_ENDPOINT_SELECT
105780. DMA_END_ADDR
105781. DMA_END_ADDR_HI
105782. DMA_END_L
105783. DMA_END_S
105784. DMA_ENGINES_NUM
105785. DMA_ENGINE_HANDLE_IRQ
105786. DMA_ENHANCE
105787. DMA_ENUM_MAX
105788. DMA_EN_BIT
105789. DMA_EN_ENETAUI
105790. DMA_EOP
105791. DMA_EOT_ENABLE
105792. DMA_EPILOGUE_SOMETHING
105793. DMA_ERRATA_3_3
105794. DMA_ERRATA_IFRAME_BUFFERING
105795. DMA_ERRATA_PARALLEL_CHANNELS
105796. DMA_ERRATA_i378
105797. DMA_ERRATA_i541
105798. DMA_ERRATA_i88
105799. DMA_ERROR
105800. DMA_ERROR_MASK
105801. DMA_ERROR_P
105802. DMA_ERROR_RECORD
105803. DMA_ERRREC_BASE
105804. DMA_ESCV1
105805. DMA_ESC_BURST
105806. DMA_ETH_RX
105807. DMA_ETH_TX
105808. DMA_ETOP_ENDIANNESS
105809. DMA_EXT_IO0
105810. DMA_EXT_IO1
105811. DMA_EXT_IO2
105812. DMA_EXT_IO3
105813. DMA_E_BURST16
105814. DMA_E_BURST32
105815. DMA_E_BURST8
105816. DMA_E_BURSTS
105817. DMA_FADD
105818. DMA_FADD_I8XX
105819. DMA_FC_THRESH_HI
105820. DMA_FC_THRESH_LO
105821. DMA_FECTL_IM
105822. DMA_FENCE_ERR
105823. DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
105824. DMA_FENCE_FLAG_SIGNALED_BIT
105825. DMA_FENCE_FLAG_TIMESTAMP_BIT
105826. DMA_FENCE_FLAG_USER_BITS
105827. DMA_FENCE_TRACE
105828. DMA_FENCE_WARN
105829. DMA_FF_ALLEMPTY
105830. DMA_FF_ALLEMPTY_MASK
105831. DMA_FF_UNDERFLOW
105832. DMA_FF_UNDERFLOW_ENA
105833. DMA_FF_UNDERFLOW_ENA_MASK
105834. DMA_FF_UNDERFLOW_MASK
105835. DMA_FIFO0
105836. DMA_FIFO1
105837. DMA_FIFO_CTRL
105838. DMA_FIFO_ENABLE
105839. DMA_FIFO_GUARD
105840. DMA_FIFO_HALF_HALF
105841. DMA_FIFO_INV
105842. DMA_FIFO_ISDRAIN
105843. DMA_FIFO_STDRAIN
105844. DMA_FIFO_THRESHOLD
105845. DMA_FIFO_VALIDATE
105846. DMA_FIRMWARE_CONFIG
105847. DMA_FIRMWARE_VERSION
105848. DMA_FLOPPY
105849. DMA_FLOPPYDISK
105850. DMA_FLOW_PERIOD_MASK
105851. DMA_FLUSH
105852. DMA_FRAME_CNT_ISR
105853. DMA_FRAME_CNT_ISR_MASK
105854. DMA_FRAME_CNT_MASK
105855. DMA_FRAME_IRQ
105856. DMA_FRAME_IRQ0
105857. DMA_FRAME_IRQ0_ENA
105858. DMA_FRAME_IRQ0_ENA_MASK
105859. DMA_FRAME_IRQ0_LEVEL
105860. DMA_FRAME_IRQ0_LEVEL_MASK
105861. DMA_FRAME_IRQ0_MASK
105862. DMA_FRAME_IRQ1
105863. DMA_FRAME_IRQ1_ENA
105864. DMA_FRAME_IRQ1_ENA_MASK
105865. DMA_FRAME_IRQ1_LEVEL
105866. DMA_FRAME_IRQ1_LEVEL_MASK
105867. DMA_FRAME_IRQ1_MASK
105868. DMA_FRAME_IRQ_ENA
105869. DMA_FRCD_F
105870. DMA_FREQ
105871. DMA_FROM_DEVICE
105872. DMA_FSTS_ICE
105873. DMA_FSTS_IQE
105874. DMA_FSTS_ITE
105875. DMA_FSTS_PFO
105876. DMA_FSTS_PPF
105877. DMA_FSTS_PRO
105878. DMA_GATHER_SCATTER
105879. DMA_GCMD_CFI
105880. DMA_GCMD_EAFL
105881. DMA_GCMD_IRE
105882. DMA_GCMD_QIE
105883. DMA_GCMD_SFL
105884. DMA_GCMD_SIRTP
105885. DMA_GCMD_SRTP
105886. DMA_GCMD_TE
105887. DMA_GCMD_WBF
105888. DMA_GCR_DMA_EN
105889. DMA_GCR_SOFT_RESET
105890. DMA_GCSW_mskC0INT
105891. DMA_GCSW_mskC0STAT
105892. DMA_GCSW_mskC1INT
105893. DMA_GCSW_mskC1STAT
105894. DMA_GCSW_mskEN
105895. DMA_GCSW_offC0INT
105896. DMA_GCSW_offC0STAT
105897. DMA_GCSW_offC1INT
105898. DMA_GCSW_offC1STAT
105899. DMA_GCSW_offEN
105900. DMA_GLOBAL_REGISTER
105901. DMA_GO
105902. DMA_GSCR
105903. DMA_GSTS_AFLS
105904. DMA_GSTS_CFIS
105905. DMA_GSTS_FLS
105906. DMA_GSTS_IRES
105907. DMA_GSTS_IRTPS
105908. DMA_GSTS_QIES
105909. DMA_GSTS_RTPS
105910. DMA_GSTS_TES
105911. DMA_GSTS_WBFS
105912. DMA_GUC_WOPCM_OFFSET
105913. DMA_H
105914. DMA_HALT
105915. DMA_HALT_POLL
105916. DMA_HALT_TIMEOUT
105917. DMA_HASCOUNT
105918. DMA_HAS_CONSTANT_FILL_CAPS
105919. DMA_HAS_DESCRIPTOR_CAPS
105920. DMA_HAS_PQ_CONTINUE
105921. DMA_HAS_TRANSPARENT_CAPS
105922. DMA_HIPAGE_0
105923. DMA_HIPAGE_1
105924. DMA_HIPAGE_2
105925. DMA_HIPAGE_3
105926. DMA_HIPAGE_4
105927. DMA_HIPAGE_5
105928. DMA_HIPAGE_6
105929. DMA_HIPAGE_7
105930. DMA_HI_LE
105931. DMA_HI_PAGE_0
105932. DMA_HI_PAGE_1
105933. DMA_HI_PAGE_2
105934. DMA_HI_PAGE_3
105935. DMA_HI_PAGE_5
105936. DMA_HI_PAGE_6
105937. DMA_HI_PAGE_7
105938. DMA_HNDL_ERROR
105939. DMA_HNDL_INTR
105940. DMA_HOST_RX_DESC
105941. DMA_HOST_TO_DRAM
105942. DMA_HOST_TO_SRAM
105943. DMA_HOST_TX_DESC
105944. DMA_HW_FAULT
105945. DMA_HW_FEATURE
105946. DMA_HW_FEAT_ACTPHYIF
105947. DMA_HW_FEAT_ADDMAC
105948. DMA_HW_FEAT_AVSEL
105949. DMA_HW_FEAT_EEESEL
105950. DMA_HW_FEAT_ENHDESSEL
105951. DMA_HW_FEAT_EXTHASHEN
105952. DMA_HW_FEAT_FLEXIPPSEN
105953. DMA_HW_FEAT_GMIISEL
105954. DMA_HW_FEAT_HASHSEL
105955. DMA_HW_FEAT_HDSEL
105956. DMA_HW_FEAT_INTTSEN
105957. DMA_HW_FEAT_L3L4FLTREN
105958. DMA_HW_FEAT_MGKSEL
105959. DMA_HW_FEAT_MIISEL
105960. DMA_HW_FEAT_MMCSEL
105961. DMA_HW_FEAT_PCSSEL
105962. DMA_HW_FEAT_RWKSEL
105963. DMA_HW_FEAT_RXCHCNT
105964. DMA_HW_FEAT_RXFIFOSIZE
105965. DMA_HW_FEAT_RXTYP1COE
105966. DMA_HW_FEAT_RXTYP2COE
105967. DMA_HW_FEAT_SAVLANINS
105968. DMA_HW_FEAT_SMASEL
105969. DMA_HW_FEAT_TSVER1SEL
105970. DMA_HW_FEAT_TSVER2SEL
105971. DMA_HW_FEAT_TXCHCNT
105972. DMA_HW_FEAT_TXCOESEL
105973. DMA_I2C_INTERRUPT_ADDR
105974. DMA_I2S_BLOB_SIZE
105975. DMA_IB_CNTL
105976. DMA_IB_ENABLE
105977. DMA_IB_PACKET
105978. DMA_IB_RPTR
105979. DMA_IB_SWAP_ENABLE
105980. DMA_IDLE
105981. DMA_IDLEMODE_FORCE_IDLE
105982. DMA_IDLEMODE_NO_IDLE
105983. DMA_IDLEMODE_SMARTIDLE
105984. DMA_IDLE_REQ
105985. DMA_ID_AC97C_RX
105986. DMA_ID_AC97C_TX
105987. DMA_ID_GP04
105988. DMA_ID_GP05
105989. DMA_ID_I2S_RX
105990. DMA_ID_I2S_TX
105991. DMA_ID_SD0_RX
105992. DMA_ID_SD0_TX
105993. DMA_ID_SD1_RX
105994. DMA_ID_SD1_TX
105995. DMA_ID_TLB_ADDR
105996. DMA_ID_TLB_ADDR_MASK
105997. DMA_ID_TLB_DID
105998. DMA_ID_TLB_DSI_FLUSH
105999. DMA_ID_TLB_GLOBAL_FLUSH
106000. DMA_ID_TLB_IH_NONLEAF
106001. DMA_ID_TLB_PSI_FLUSH
106002. DMA_ID_TLB_READ_DRAIN
106003. DMA_ID_TLB_WRITE_DRAIN
106004. DMA_ID_UART0_RX
106005. DMA_ID_UART0_TX
106006. DMA_ID_UART3_RX
106007. DMA_ID_UART3_TX
106008. DMA_ID_USBDEV_EP0_RX
106009. DMA_ID_USBDEV_EP0_TX
106010. DMA_ID_USBDEV_EP2_TX
106011. DMA_ID_USBDEV_EP3_TX
106012. DMA_ID_USBDEV_EP4_RX
106013. DMA_ID_USBDEV_EP5_RX
106014. DMA_IE
106015. DMA_IER_INT_EN
106016. DMA_IMEM_OFFSET
106017. DMA_IN
106018. DMA_INDEX2RING_0
106019. DMA_INDEX2RING_1
106020. DMA_INDEX2RING_2
106021. DMA_INDEX2RING_3
106022. DMA_INDEX2RING_4
106023. DMA_INDEX2RING_5
106024. DMA_INDEX2RING_6
106025. DMA_INDEX2RING_7
106026. DMA_INPUT_COMMAND_DISABLE
106027. DMA_INPUT_COMMAND_ENABLE
106028. DMA_INPUT_ERROR_NONE
106029. DMA_INPUT_FORMAT_BAYER
106030. DMA_INPUT_FORMAT_YUV420
106031. DMA_INPUT_FORMAT_YUV422
106032. DMA_INPUT_FORMAT_YUV444
106033. DMA_INPUT_ORDER_CBCR
106034. DMA_INPUT_ORDER_CBYCRY
106035. DMA_INPUT_ORDER_CRCB
106036. DMA_INPUT_ORDER_CRYCBY
106037. DMA_INPUT_ORDER_GR_BG
106038. DMA_INPUT_ORDER_NO
106039. DMA_INPUT_ORDER_YCBCR
106040. DMA_INPUT_ORDER_YCBYCR
106041. DMA_INPUT_ORDER_YCRYCB
106042. DMA_INPUT_ORDER_YYCBCR
106043. DMA_INT
106044. DMA_INTERFACE_DWDMA
106045. DMA_INTERFACE_GDMA
106046. DMA_INTERFACE_IDMA
106047. DMA_INTERFACE_NODMA
106048. DMA_INTERLEAVE
106049. DMA_INTERNAL
106050. DMA_INTERRUPT
106051. DMA_INTERRUPTS
106052. DMA_INTERRUPT_STATUS_REG
106053. DMA_INTR
106054. DMA_INTR_ABNORMAL
106055. DMA_INTR_DEFAULT_MASK
106056. DMA_INTR_EN
106057. DMA_INTR_ENA
106058. DMA_INTR_ENA_AIE
106059. DMA_INTR_ENA_ERE
106060. DMA_INTR_ENA_ETE
106061. DMA_INTR_ENA_FBE
106062. DMA_INTR_ENA_NIE
106063. DMA_INTR_ENA_OVE
106064. DMA_INTR_ENA_RIE
106065. DMA_INTR_ENA_RSE
106066. DMA_INTR_ENA_RUE
106067. DMA_INTR_ENA_RWE
106068. DMA_INTR_ENA_TIE
106069. DMA_INTR_ENA_TJE
106070. DMA_INTR_ENA_TSE
106071. DMA_INTR_ENA_TUE
106072. DMA_INTR_ENA_UNE
106073. DMA_INTR_EN_BIT
106074. DMA_INTR_NORMAL
106075. DMA_INTR_PROT_WR_CMP
106076. DMA_INTR_THRESHOLD_MASK
106077. DMA_INTR__DESC_COMP_CHANNEL0
106078. DMA_INTR__DESC_COMP_CHANNEL1
106079. DMA_INTR__DESC_COMP_CHANNEL2
106080. DMA_INTR__DESC_COMP_CHANNEL3
106081. DMA_INTR__MEMCOPY_DESC_COMP
106082. DMA_INTR__TARGET_ERROR
106083. DMA_INTSOFF
106084. DMA_INTSON
106085. DMA_INT_EN
106086. DMA_INT_ENAB
106087. DMA_INT_ENABLE
106088. DMA_INT_PENDING
106089. DMA_INV
106090. DMA_INVALID_ADDRESS
106091. DMA_INVALID_ID
106092. DMA_IN_PROGRESS
106093. DMA_IP_CTRL_REG
106094. DMA_IRQ
106095. DMA_IRQ_ACK
106096. DMA_IRQ_ACK_MASK
106097. DMA_IRQ_CHAN_NR
106098. DMA_IRQ_CHAN_WIDTH
106099. DMA_IRQ_EN
106100. DMA_IRQ_ENTRY
106101. DMA_IRQ_EN_MASK
106102. DMA_IRQ_EXIT
106103. DMA_IRQ_HALF
106104. DMA_IRQ_P
106105. DMA_IRQ_PKG
106106. DMA_IRQ_QUEUE
106107. DMA_IRQ_STAT
106108. DMA_ISADDR_mskISADDR
106109. DMA_ISADDR_offISADDR
106110. DMA_ISA_CASCADE
106111. DMA_ISBROKEN
106112. DMA_ISESC1
106113. DMA_ISR
106114. DMA_ISR_INT_STS
106115. DMA_ISR_MACIS_INDEX
106116. DMA_ISR_MACIS_LEN
106117. DMA_ISR_MACIS_POS
106118. DMA_ISR_MACIS_WIDTH
106119. DMA_ISR_MTLIS_INDEX
106120. DMA_ISR_MTLIS_LEN
106121. DMA_ISR_MTLIS_POS
106122. DMA_ISR_MTLIS_WIDTH
106123. DMA_IntMask
106124. DMA_LADR
106125. DMA_LCD_CCR
106126. DMA_LCD_CTRL
106127. DMA_LCD_LCH_CTRL
106128. DMA_LENGTH_DEF
106129. DMA_LENGTH_MAX
106130. DMA_LENGTH_MIN
106131. DMA_LINE_CONTROL_GROUP1
106132. DMA_LINE_CONTROL_GROUP2
106133. DMA_LINKED_LCH
106134. DMA_LIODN_BASE_MASK
106135. DMA_LIODN_SHIFT
106136. DMA_LITTLE_ENDIAN_MODE
106137. DMA_LOADED_ADDR
106138. DMA_LOADED_NADDR
106139. DMA_LOCALS
106140. DMA_LOCAL_ADDR
106141. DMA_LOCAL_DONE
106142. DMA_LOOPBACK
106143. DMA_LOWER
106144. DMA_LO_LE
106145. DMA_LO_PAGE_0
106146. DMA_LO_PAGE_1
106147. DMA_LO_PAGE_2
106148. DMA_LO_PAGE_3
106149. DMA_LO_PAGE_5
106150. DMA_LO_PAGE_6
106151. DMA_LO_PAGE_7
106152. DMA_M66EnStat
106153. DMA_MACRO_BMON_0_MAX_OFFSET
106154. DMA_MACRO_BMON_0_SECTION
106155. DMA_MACRO_BMON_1_MAX_OFFSET
106156. DMA_MACRO_BMON_1_SECTION
106157. DMA_MACRO_BMON_2_MAX_OFFSET
106158. DMA_MACRO_BMON_2_SECTION
106159. DMA_MACRO_BMON_3_MAX_OFFSET
106160. DMA_MACRO_BMON_3_SECTION
106161. DMA_MACRO_BMON_4_MAX_OFFSET
106162. DMA_MACRO_BMON_4_SECTION
106163. DMA_MACRO_BMON_5_MAX_OFFSET
106164. DMA_MACRO_BMON_5_SECTION
106165. DMA_MACRO_BMON_6_MAX_OFFSET
106166. DMA_MACRO_BMON_6_SECTION
106167. DMA_MACRO_BMON_7_MAX_OFFSET
106168. DMA_MACRO_BMON_7_SECTION
106169. DMA_MACRO_BMON_CTI_MAX_OFFSET
106170. DMA_MACRO_BMON_CTI_SECTION
106171. DMA_MACRO_CS_CTI_MAX_OFFSET
106172. DMA_MACRO_CS_CTI_SECTION
106173. DMA_MACRO_CS_ETF_MAX_OFFSET
106174. DMA_MACRO_CS_ETF_SECTION
106175. DMA_MACRO_CS_SPMU_MAX_OFFSET
106176. DMA_MACRO_CS_SPMU_SECTION
106177. DMA_MACRO_CS_STM_MAX_OFFSET
106178. DMA_MACRO_CS_STM_SECTION
106179. DMA_MACRO_FUNNEL_3_1_MAX_OFFSET
106180. DMA_MACRO_FUNNEL_3_1_SECTION
106181. DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK
106182. DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT
106183. DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK
106184. DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT
106185. DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK
106186. DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT
106187. DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK
106188. DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT
106189. DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK
106190. DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT
106191. DMA_MACRO_LBW_RANGE_BASE_R_MASK
106192. DMA_MACRO_LBW_RANGE_BASE_R_SHIFT
106193. DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK
106194. DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT
106195. DMA_MACRO_LBW_RANGE_MASK_R_MASK
106196. DMA_MACRO_LBW_RANGE_MASK_R_SHIFT
106197. DMA_MACRO_MAX_OFFSET
106198. DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK
106199. DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT
106200. DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK
106201. DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT
106202. DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK
106203. DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT
106204. DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK
106205. DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT
106206. DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK
106207. DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT
106208. DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK
106209. DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT
106210. DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK
106211. DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT
106212. DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK
106213. DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT
106214. DMA_MACRO_READ_CREDIT_R_MASK
106215. DMA_MACRO_READ_CREDIT_R_SHIFT
106216. DMA_MACRO_READ_EN_R_MASK
106217. DMA_MACRO_READ_EN_R_SHIFT
106218. DMA_MACRO_SECTION
106219. DMA_MACRO_USER_CTI_MAX_OFFSET
106220. DMA_MACRO_USER_CTI_SECTION
106221. DMA_MACRO_WRITE_CREDIT_R_MASK
106222. DMA_MACRO_WRITE_CREDIT_R_SHIFT
106223. DMA_MACRO_WRITE_EN_R_MASK
106224. DMA_MACRO_WRITE_EN_R_SHIFT
106225. DMA_MAC_RST_TO
106226. DMA_MAGIC_COOKIE
106227. DMA_MAPPING_ERROR
106228. DMA_MASK
106229. DMA_MASK_CTL0_MODE
106230. DMA_MASK_CTL2_MODE
106231. DMA_MASK_NONE
106232. DMA_MAX
106233. DMA_MAXEND
106234. DMA_MAX_BUFS
106235. DMA_MAX_BURST_LENGTH
106236. DMA_MAX_CHANNEL
106237. DMA_MAX_CHANNELS
106238. DMA_MAX_CHAN_BYTES
106239. DMA_MAX_CHAN_DESCRIPTORS
106240. DMA_MAX_COUNT
106241. DMA_MAX_NUM
106242. DMA_MAX_PKT_SIZE_MASK
106243. DMA_MAX_PKT_SIZE_SHIFT
106244. DMA_MAX_QMS
106245. DMA_MAX_SIZE
106246. DMA_MAX_TRANSFER_SIZE
106247. DMA_MBUF_DONE_THRESH
106248. DMA_MDELAY
106249. DMA_MEMCPY
106250. DMA_MEMDMA_DMEM
106251. DMA_MEMDMA_IMEM
106252. DMA_MEMDMA_OFFSET
106253. DMA_MEMORY
106254. DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE
106255. DMA_MEMSET
106256. DMA_MEMSET_SG
106257. DMA_MEM_MULTI_READ
106258. DMA_MEM_TO_DEV
106259. DMA_MEM_TO_MEM
106260. DMA_MEM_WRITE_INVAL
106261. DMA_MIN
106262. DMA_MIN_BYTES
106263. DMA_MIN_COOKIE
106264. DMA_MIN_SIZE
106265. DMA_MISSED_FRAME_CTR
106266. DMA_MISSED_FRAME_M_CNTR
106267. DMA_MISSED_FRAME_OVE
106268. DMA_MISSED_FRAME_OVE_CNTR
106269. DMA_MISSED_FRAME_OVE_M
106270. DMA_MLB_RX
106271. DMA_MLB_TX
106272. DMA_MLLI
106273. DMA_MME_TPC_RESET
106274. DMA_MODE
106275. DMA_MODE_AID_MODE_SHIFT
106276. DMA_MODE_AXI_DBG_MASK
106277. DMA_MODE_AXI_DBG_SHIFT
106278. DMA_MODE_BER
106279. DMA_MODE_BITS
106280. DMA_MODE_CACHE_OR_SHIFT
106281. DMA_MODE_CASCADE
106282. DMA_MODE_CEN_MASK
106283. DMA_MODE_CEN_SHIFT
106284. DMA_MODE_CLEAR
106285. DMA_MODE_DBG_SHIFT
106286. DMA_MODE_DES_SA_BIT
106287. DMA_MODE_DSIZE_MASK
106288. DMA_MODE_DSIZE_OFF
106289. DMA_MODE_ECC
106290. DMA_MODE_END
106291. DMA_MODE_FLAG
106292. DMA_MODE_LONG_BIT
106293. DMA_MODE_MASK
106294. DMA_MODE_NO_ENABLE
106295. DMA_MODE_NULL
106296. DMA_MODE_READ
106297. DMA_MODE_READ_LONG
106298. DMA_MODE_READ_LONG_SINGLE
106299. DMA_MODE_READ_SINGLE
106300. DMA_MODE_READ_WORD
106301. DMA_MODE_READ_WORD_SINGLE
106302. DMA_MODE_SECURE_PROT
106303. DMA_MODE_SET
106304. DMA_MODE_SINGLE_BIT
106305. DMA_MODE_SIZE_BYTE
106306. DMA_MODE_SIZE_LINE
106307. DMA_MODE_SIZE_LONG
106308. DMA_MODE_SIZE_WORD
106309. DMA_MODE_SRC_SA_BIT
106310. DMA_MODE_SSIZE_MASK
106311. DMA_MODE_SSIZE_OFF
106312. DMA_MODE_WORD_BIT
106313. DMA_MODE_WRITE
106314. DMA_MODE_WRITE_BIT
106315. DMA_MODE_WRITE_LONG
106316. DMA_MODE_WRITE_LONG_SINGLE
106317. DMA_MODE_WRITE_SINGLE
106318. DMA_MODE_WRITE_WORD
106319. DMA_MODE_WRITE_WORD_SINGLE
106320. DMA_MPU_MODE
106321. DMA_MPU_MODE_SHIFT
106322. DMA_MR
106323. DMA_MR_INTM_INDEX
106324. DMA_MR_INTM_WIDTH
106325. DMA_MR_SWR_INDEX
106326. DMA_MR_SWR_LEN
106327. DMA_MR_SWR_POS
106328. DMA_MR_SWR_WIDTH
106329. DMA_MST_CTRL
106330. DMA_MST_CTRL_BURST_1
106331. DMA_MST_CTRL_BURST_16
106332. DMA_MST_CTRL_BURST_4
106333. DMA_MST_CTRL_BURST_8
106334. DMA_MST_CTRL_EN_A
106335. DMA_MST_CTRL_EN_B
106336. DMA_MST_CTRL_GO
106337. DMA_MST_CTRL_IE_DONE
106338. DMA_MST_CTRL_IN
106339. DMA_MST_CTRL_IS_DONE
106340. DMA_MST_CTRL_OUT
106341. DMA_MST_CTRL_PERF_EN
106342. DMA_MST_CTRL_REUSE
106343. DMA_NC
106344. DMA_NDAR
106345. DMA_NONE
106346. DMA_NOTIFIER_HANDLE_BASE
106347. DMA_NOTIFIER_OFFSET_BASE
106348. DMA_NOTIFIER_SIZE
106349. DMA_NO_MASK
106350. DMA_NRTR_DBG_E_ARB_L_MASK
106351. DMA_NRTR_DBG_E_ARB_L_SHIFT
106352. DMA_NRTR_DBG_E_ARB_MAX_CREDIT_MASK
106353. DMA_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT
106354. DMA_NRTR_DBG_E_ARB_N_MASK
106355. DMA_NRTR_DBG_E_ARB_N_SHIFT
106356. DMA_NRTR_DBG_E_ARB_S_MASK
106357. DMA_NRTR_DBG_E_ARB_S_SHIFT
106358. DMA_NRTR_DBG_E_ARB_W_MASK
106359. DMA_NRTR_DBG_E_ARB_W_SHIFT
106360. DMA_NRTR_DBG_L_ARB_E_MASK
106361. DMA_NRTR_DBG_L_ARB_E_SHIFT
106362. DMA_NRTR_DBG_L_ARB_MAX_CREDIT_MASK
106363. DMA_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT
106364. DMA_NRTR_DBG_L_ARB_N_MASK
106365. DMA_NRTR_DBG_L_ARB_N_SHIFT
106366. DMA_NRTR_DBG_L_ARB_S_MASK
106367. DMA_NRTR_DBG_L_ARB_S_SHIFT
106368. DMA_NRTR_DBG_L_ARB_W_MASK
106369. DMA_NRTR_DBG_L_ARB_W_SHIFT
106370. DMA_NRTR_DBG_N_ARB_E_MASK
106371. DMA_NRTR_DBG_N_ARB_E_SHIFT
106372. DMA_NRTR_DBG_N_ARB_L_MASK
106373. DMA_NRTR_DBG_N_ARB_L_SHIFT
106374. DMA_NRTR_DBG_N_ARB_MAX_CREDIT_MASK
106375. DMA_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT
106376. DMA_NRTR_DBG_N_ARB_S_MASK
106377. DMA_NRTR_DBG_N_ARB_S_SHIFT
106378. DMA_NRTR_DBG_N_ARB_W_MASK
106379. DMA_NRTR_DBG_N_ARB_W_SHIFT
106380. DMA_NRTR_DBG_S_ARB_E_MASK
106381. DMA_NRTR_DBG_S_ARB_E_SHIFT
106382. DMA_NRTR_DBG_S_ARB_L_MASK
106383. DMA_NRTR_DBG_S_ARB_L_SHIFT
106384. DMA_NRTR_DBG_S_ARB_MAX_CREDIT_MASK
106385. DMA_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT
106386. DMA_NRTR_DBG_S_ARB_N_MASK
106387. DMA_NRTR_DBG_S_ARB_N_SHIFT
106388. DMA_NRTR_DBG_S_ARB_W_MASK
106389. DMA_NRTR_DBG_S_ARB_W_SHIFT
106390. DMA_NRTR_DBG_W_ARB_E_MASK
106391. DMA_NRTR_DBG_W_ARB_E_SHIFT
106392. DMA_NRTR_DBG_W_ARB_L_MASK
106393. DMA_NRTR_DBG_W_ARB_L_SHIFT
106394. DMA_NRTR_DBG_W_ARB_MAX_CREDIT_MASK
106395. DMA_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT
106396. DMA_NRTR_DBG_W_ARB_N_MASK
106397. DMA_NRTR_DBG_W_ARB_N_SHIFT
106398. DMA_NRTR_DBG_W_ARB_S_MASK
106399. DMA_NRTR_DBG_W_ARB_S_SHIFT
106400. DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK
106401. DMA_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT
106402. DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK
106403. DMA_NRTR_HBW_MAX_CRED_RD_RS_SHIFT
106404. DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK
106405. DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT
106406. DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK
106407. DMA_NRTR_HBW_MAX_CRED_WR_RS_SHIFT
106408. DMA_NRTR_HBW_RANGE_BASE_H_VAL_MASK
106409. DMA_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT
106410. DMA_NRTR_HBW_RANGE_BASE_L_VAL_MASK
106411. DMA_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT
106412. DMA_NRTR_HBW_RANGE_HIT_IND_MASK
106413. DMA_NRTR_HBW_RANGE_HIT_IND_SHIFT
106414. DMA_NRTR_HBW_RANGE_MASK_H_VAL_MASK
106415. DMA_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT
106416. DMA_NRTR_HBW_RANGE_MASK_L_VAL_MASK
106417. DMA_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT
106418. DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK
106419. DMA_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT
106420. DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK
106421. DMA_NRTR_LBW_MAX_CRED_RD_RS_SHIFT
106422. DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK
106423. DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT
106424. DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK
106425. DMA_NRTR_LBW_MAX_CRED_WR_RS_SHIFT
106426. DMA_NRTR_LBW_RANGE_BASE_VAL_MASK
106427. DMA_NRTR_LBW_RANGE_BASE_VAL_SHIFT
106428. DMA_NRTR_LBW_RANGE_HIT_IND_MASK
106429. DMA_NRTR_LBW_RANGE_HIT_IND_SHIFT
106430. DMA_NRTR_LBW_RANGE_MASK_VAL_MASK
106431. DMA_NRTR_LBW_RANGE_MASK_VAL_SHIFT
106432. DMA_NRTR_MAX_OFFSET
106433. DMA_NRTR_NON_LIN_SCRAMB_EN_MASK
106434. DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT
106435. DMA_NRTR_RGLTR_RD_EN_MASK
106436. DMA_NRTR_RGLTR_RD_EN_SHIFT
106437. DMA_NRTR_RGLTR_RD_RESULT_VAL_MASK
106438. DMA_NRTR_RGLTR_RD_RESULT_VAL_SHIFT
106439. DMA_NRTR_RGLTR_WR_EN_MASK
106440. DMA_NRTR_RGLTR_WR_EN_SHIFT
106441. DMA_NRTR_RGLTR_WR_RESULT_VAL_MASK
106442. DMA_NRTR_RGLTR_WR_RESULT_VAL_SHIFT
106443. DMA_NRTR_SCRAMB_EN_VAL_MASK
106444. DMA_NRTR_SCRAMB_EN_VAL_SHIFT
106445. DMA_NRTR_SECTION
106446. DMA_NRTR_SPLIT_CFG_B2B_OPT_MASK
106447. DMA_NRTR_SPLIT_CFG_B2B_OPT_SHIFT
106448. DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK
106449. DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT
106450. DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK
106451. DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT
106452. DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK
106453. DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT
106454. DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK
106455. DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT
106456. DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK
106457. DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT
106458. DMA_NRTR_SPLIT_COEF_VAL_MASK
106459. DMA_NRTR_SPLIT_COEF_VAL_SHIFT
106460. DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK
106461. DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT
106462. DMA_NRTR_SPLIT_RD_SAT_VAL_MASK
106463. DMA_NRTR_SPLIT_RD_SAT_VAL_SHIFT
106464. DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK
106465. DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT
106466. DMA_NRTR_SPLIT_WR_SAT_VAL_MASK
106467. DMA_NRTR_SPLIT_WR_SAT_VAL_SHIFT
106468. DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK
106469. DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT
106470. DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK
106471. DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT
106472. DMA_NULL_TYPE
106473. DMA_NUM_DEV
106474. DMA_NUM_DEV_BANK2
106475. DMA_OCP_RESET
106476. DMA_OFF
106477. DMA_OFFSET
106478. DMA_ON
106479. DMA_OP
106480. DMA_OSP_DISABLE
106481. DMA_OSP_ENABLE
106482. DMA_OUT
106483. DMA_OUTPUT_COMMAND_DISABLE
106484. DMA_OUTPUT_COMMAND_ENABLE
106485. DMA_OUTPUT_ERROR_NONE
106486. DMA_OUTPUT_FORMAT_BAYER
106487. DMA_OUTPUT_FORMAT_RGB
106488. DMA_OUTPUT_FORMAT_YUV420
106489. DMA_OUTPUT_FORMAT_YUV422
106490. DMA_OUTPUT_FORMAT_YUV444
106491. DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE
106492. DMA_OUTPUT_NOTIFY_DMA_DONE_ENABLE
106493. DMA_OUTPUT_ORDER_BGR
106494. DMA_OUTPUT_ORDER_CBCR
106495. DMA_OUTPUT_ORDER_CBCRY
106496. DMA_OUTPUT_ORDER_CBYCR
106497. DMA_OUTPUT_ORDER_CBYCRY
106498. DMA_OUTPUT_ORDER_CRCB
106499. DMA_OUTPUT_ORDER_CRCBY
106500. DMA_OUTPUT_ORDER_CRYCB
106501. DMA_OUTPUT_ORDER_CRYCBY
106502. DMA_OUTPUT_ORDER_GB_BG
106503. DMA_OUTPUT_ORDER_NO
106504. DMA_OUTPUT_ORDER_YCBCR
106505. DMA_OUTPUT_ORDER_YCBYCR
106506. DMA_OUTPUT_ORDER_YCRCB
106507. DMA_OUTPUT_ORDER_YCRYCB
106508. DMA_OUTPUT_ORDER_YYCBCR
106509. DMA_OUT_AUTO_START_ENABLE
106510. DMA_OUT_FIFO_TRANSFER_DONE
106511. DMA_OV1
106512. DMA_OV2_Cb
106513. DMA_OV2_Cr
106514. DMA_OV2_Y
106515. DMA_OVERLAY_FRAME_SIZE_NWORDS
106516. DMA_OWN
106517. DMA_P
106518. DMA_PACKET
106519. DMA_PACKET_CONSTANT_FILL
106520. DMA_PACKET_COPY
106521. DMA_PACKET_FENCE
106522. DMA_PACKET_INDIRECT_BUFFER
106523. DMA_PACKET_NOP
106524. DMA_PACKET_POLL_REG_MEM
106525. DMA_PACKET_SEMAPHORE
106526. DMA_PACKET_SRBM_WRITE
106527. DMA_PACKET_TRAP
106528. DMA_PACKET_WRITE
106529. DMA_PACK_SIZE_MASK
106530. DMA_PADR
106531. DMA_PAGE_0
106532. DMA_PAGE_1
106533. DMA_PAGE_2
106534. DMA_PAGE_3
106535. DMA_PAGE_5
106536. DMA_PAGE_6
106537. DMA_PAGE_7
106538. DMA_PAGE_INVALID
106539. DMA_PAGE_SIZE
106540. DMA_PAGE_TABLE0_ADDR
106541. DMA_PAGE_TABLE1_ADDR
106542. DMA_PARITY_OFF
106543. DMA_PAUSED
106544. DMA_PAUSES
106545. DMA_PAUSE_DONE
106546. DMA_PAUSE_DONE_INTERRUPT
106547. DMA_PBL_1
106548. DMA_PBL_128
106549. DMA_PBL_16
106550. DMA_PBL_2
106551. DMA_PBL_256
106552. DMA_PBL_32
106553. DMA_PBL_4
106554. DMA_PBL_64
106555. DMA_PBL_8
106556. DMA_PBL_X8_DISABLE
106557. DMA_PBL_X8_ENABLE
106558. DMA_PCI_ADDR
106559. DMA_PCI_BYTE_COUNT
106560. DMA_PCI_DONE
106561. DMA_PCI_DUAL_ADDR
106562. DMA_PCPCI
106563. DMA_PDEN
106564. DMA_PEND_READ
106565. DMA_PERIPHERAL_ADDR
106566. DMA_PER_DREQ_MODE
106567. DMA_PER_IDLE_INT
106568. DMA_PER_INJECT_PKT
106569. DMA_PER_INJECT_PKT_ADDR
106570. DMA_PER_INJECT_PKT_DEST
106571. DMA_PER_INJECT_PKT_SRC
106572. DMA_PER_MAX_CHUNK
106573. DMA_PER_MAX_OPCODE
106574. DMA_PER_MBOX_CLEAR
106575. DMA_PER_MBOX_MASK
106576. DMA_PER_MBOX_SET
106577. DMA_PER_MBOX_STATUS
106578. DMA_PER_OFFSET
106579. DMA_PER_PAGE_SIZE
106580. DMA_PER_PAT_PTR
106581. DMA_PER_PAT_PTR_INIT
106582. DMA_PER_PRIORITY
106583. DMA_PER_SLEEP_COUNTER
106584. DMA_PER_SLEEP_MASK
106585. DMA_PER_STBUS_ACCESS
106586. DMA_PER_STBUS_ADDRESS
106587. DMA_PER_STBUS_SYNC
106588. DMA_PER_TPn_DACK
106589. DMA_PER_TPn_DACK_SET
106590. DMA_PER_TPn_DREQ
106591. DMA_PER_TPn_DREQ_MASK
106592. DMA_PFC_ENABLE
106593. DMA_PG
106594. DMA_PGFSM_CONFIG
106595. DMA_PGFSM_WRITE
106596. DMA_PHYS
106597. DMA_PMEN_EPM
106598. DMA_PMEN_PRS
106599. DMA_POLICY_MASK
106600. DMA_POLL
106601. DMA_POOL_SIZE
106602. DMA_PORT
106603. DMA_PORTA_CHAN0_ADDR_HI
106604. DMA_PORTA_CHAN0_ADDR_LOW
106605. DMA_PORTA_CHAN0_CONTROL
106606. DMA_PORTA_CHAN0_TRANS_STATE
106607. DMA_PORTA_CHAN1_ADDR_HI
106608. DMA_PORTA_CHAN1_ADDR_LOW
106609. DMA_PORTA_CHAN1_CONTROL
106610. DMA_PORTA_CHAN1_TRANS_STATE
106611. DMA_PORTA_CONTROL_REG_BASE
106612. DMA_PORTA_MANAGEMENT
106613. DMA_PORTB_CHAN0_ADDR_HI
106614. DMA_PORTB_CHAN0_ADDR_LOW
106615. DMA_PORTB_CHAN0_CONTROL
106616. DMA_PORTB_CHAN0_TRANS_STATE
106617. DMA_PORTB_CHAN1_ADDR_HI
106618. DMA_PORTB_CHAN1_ADDR_LOW
106619. DMA_PORTB_CHAN1_CONTROL
106620. DMA_PORTB_CHAN1_TRANS_STATE
106621. DMA_PORTB_CONTROL_REG_BASE
106622. DMA_PORTB_MANAGEMENT
106623. DMA_PORTC_CONTROL_REG_BASE
106624. DMA_PORTD_CONTROL_REG_BASE
106625. DMA_PORT_CAP
106626. DMA_PORT_CSS_ADDRESS
106627. DMA_PORT_CSS_MAX_SIZE
106628. DMA_PORT_DEU
106629. DMA_PORT_ETOP
106630. DMA_PORT_H_
106631. DMA_PORT_RETRIES
106632. DMA_PORT_TIMEOUT
106633. DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE
106634. DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE
106635. DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE
106636. DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK
106637. DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT
106638. DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK
106639. DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT
106640. DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK
106641. DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT
106642. DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK
106643. DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT
106644. DMA_POWER_CNTL
106645. DMA_PQ
106646. DMA_PQ_VAL
106647. DMA_PRDS_BUSBASE_TP
106648. DMA_PRDS_BUSRP_TP
106649. DMA_PRDS_BUSTOP_TP
106650. DMA_PRDS_BUSWP_TP
106651. DMA_PRDS_MEMBASE
106652. DMA_PRDS_MEMTOP
106653. DMA_PRDS_PKTSIZE
106654. DMA_PRDS_SIZE
106655. DMA_PRDS_TPENABLE
106656. DMA_PREEMPT_ENABLE
106657. DMA_PREP_CMD
106658. DMA_PREP_CONTINUE
106659. DMA_PREP_FENCE
106660. DMA_PREP_INTERRUPT
106661. DMA_PREP_PQ_DISABLE_P
106662. DMA_PREP_PQ_DISABLE_Q
106663. DMA_PREP_ZERO_P
106664. DMA_PREP_ZERO_Q
106665. DMA_PREV_PCL
106666. DMA_PRIORITY_0
106667. DMA_PRIORITY_1
106668. DMA_PRIORITY_2
106669. DMA_PRIO_DEFAULT
106670. DMA_PRIO_HIGH
106671. DMA_PRIO_LOW
106672. DMA_PRIO_MASK
106673. DMA_PRIO_MEDIUM
106674. DMA_PRIO_MED_H
106675. DMA_PRIO_MED_L
106676. DMA_PRIO_REG_INDEX
106677. DMA_PRIO_REG_SHIFT
106678. DMA_PRIVATE
106679. DMA_PROCESS_MON_MAX_OFFSET
106680. DMA_PROCESS_MON_SECTION
106681. DMA_PROTO
106682. DMA_PRS_PPR
106683. DMA_PTE_LARGE_PAGE
106684. DMA_PTE_PDE_PACKET
106685. DMA_PTE_READ
106686. DMA_PTE_SNP
106687. DMA_PTE_WRITE
106688. DMA_PTRREC_BASE
106689. DMA_PTRREC_INPUT_OFFSET
106690. DMA_PUADR
106691. DMA_PUNTFIFO
106692. DMA_P_INDEX_DISCARD_CNT_MASK
106693. DMA_P_INDEX_DISCARD_CNT_SHIFT
106694. DMA_P_INDEX_MASK
106695. DMA_PowrMgmnt
106696. DMA_QM_0_CP_BARRIER_CFG_EBGUARD_MASK
106697. DMA_QM_0_CP_BARRIER_CFG_EBGUARD_SHIFT
106698. DMA_QM_0_CP_CURRENT_INST_HI_VAL_MASK
106699. DMA_QM_0_CP_CURRENT_INST_HI_VAL_SHIFT
106700. DMA_QM_0_CP_CURRENT_INST_LO_VAL_MASK
106701. DMA_QM_0_CP_CURRENT_INST_LO_VAL_SHIFT
106702. DMA_QM_0_CP_DBG_0_VAL_MASK
106703. DMA_QM_0_CP_DBG_0_VAL_SHIFT
106704. DMA_QM_0_CP_FENCE0_CNT_VAL_MASK
106705. DMA_QM_0_CP_FENCE0_CNT_VAL_SHIFT
106706. DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_MASK
106707. DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_SHIFT
106708. DMA_QM_0_CP_FENCE1_CNT_VAL_MASK
106709. DMA_QM_0_CP_FENCE1_CNT_VAL_SHIFT
106710. DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_MASK
106711. DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_SHIFT
106712. DMA_QM_0_CP_FENCE2_CNT_VAL_MASK
106713. DMA_QM_0_CP_FENCE2_CNT_VAL_SHIFT
106714. DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_MASK
106715. DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_SHIFT
106716. DMA_QM_0_CP_FENCE3_CNT_VAL_MASK
106717. DMA_QM_0_CP_FENCE3_CNT_VAL_SHIFT
106718. DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_MASK
106719. DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_SHIFT
106720. DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_MASK
106721. DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT
106722. DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK
106723. DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT
106724. DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK
106725. DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT
106726. DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK
106727. DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT
106728. DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK
106729. DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT
106730. DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_MASK
106731. DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT
106732. DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_MASK
106733. DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT
106734. DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_MASK
106735. DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT
106736. DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_MASK
106737. DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT
106738. DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_MASK
106739. DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT
106740. DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_MASK
106741. DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT
106742. DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_MASK
106743. DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT
106744. DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_MASK
106745. DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT
106746. DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_MASK
106747. DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT
106748. DMA_QM_0_CP_STS_ERDY_MASK
106749. DMA_QM_0_CP_STS_ERDY_SHIFT
106750. DMA_QM_0_CP_STS_FENCE_ID_MASK
106751. DMA_QM_0_CP_STS_FENCE_ID_SHIFT
106752. DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_MASK
106753. DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_SHIFT
106754. DMA_QM_0_CP_STS_MRDY_MASK
106755. DMA_QM_0_CP_STS_MRDY_SHIFT
106756. DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_MASK
106757. DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_SHIFT
106758. DMA_QM_0_CP_STS_RRDY_MASK
106759. DMA_QM_0_CP_STS_RRDY_SHIFT
106760. DMA_QM_0_CP_STS_SW_STOP_MASK
106761. DMA_QM_0_CP_STS_SW_STOP_SHIFT
106762. DMA_QM_0_CQ_ARUSER_NOSNOOP_MASK
106763. DMA_QM_0_CQ_ARUSER_NOSNOOP_SHIFT
106764. DMA_QM_0_CQ_ARUSER_WORD_MASK
106765. DMA_QM_0_CQ_ARUSER_WORD_SHIFT
106766. DMA_QM_0_CQ_BUF_ADDR_VAL_MASK
106767. DMA_QM_0_CQ_BUF_ADDR_VAL_SHIFT
106768. DMA_QM_0_CQ_BUF_RDATA_VAL_MASK
106769. DMA_QM_0_CQ_BUF_RDATA_VAL_SHIFT
106770. DMA_QM_0_CQ_CFG0_RESERVED_MASK
106771. DMA_QM_0_CQ_CFG0_RESERVED_SHIFT
106772. DMA_QM_0_CQ_CFG1_CREDIT_LIM_MASK
106773. DMA_QM_0_CQ_CFG1_CREDIT_LIM_SHIFT
106774. DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_MASK
106775. DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_SHIFT
106776. DMA_QM_0_CQ_CTL_CTL_MASK
106777. DMA_QM_0_CQ_CTL_CTL_SHIFT
106778. DMA_QM_0_CQ_CTL_RPT_MASK
106779. DMA_QM_0_CQ_CTL_RPT_SHIFT
106780. DMA_QM_0_CQ_CTL_STS_CTL_MASK
106781. DMA_QM_0_CQ_CTL_STS_CTL_SHIFT
106782. DMA_QM_0_CQ_CTL_STS_RPT_MASK
106783. DMA_QM_0_CQ_CTL_STS_RPT_SHIFT
106784. DMA_QM_0_CQ_IFIFO_CNT_VAL_MASK
106785. DMA_QM_0_CQ_IFIFO_CNT_VAL_SHIFT
106786. DMA_QM_0_CQ_PTR_HI_STS_VAL_MASK
106787. DMA_QM_0_CQ_PTR_HI_STS_VAL_SHIFT
106788. DMA_QM_0_CQ_PTR_HI_VAL_MASK
106789. DMA_QM_0_CQ_PTR_HI_VAL_SHIFT
106790. DMA_QM_0_CQ_PTR_LO_STS_VAL_MASK
106791. DMA_QM_0_CQ_PTR_LO_STS_VAL_SHIFT
106792. DMA_QM_0_CQ_PTR_LO_VAL_MASK
106793. DMA_QM_0_CQ_PTR_LO_VAL_SHIFT
106794. DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_MASK
106795. DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_SHIFT
106796. DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK
106797. DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT
106798. DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_MASK
106799. DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_SHIFT
106800. DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_MASK
106801. DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT
106802. DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_MASK
106803. DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_SHIFT
106804. DMA_QM_0_CQ_STS0_CQ_FREE_CNT_MASK
106805. DMA_QM_0_CQ_STS0_CQ_FREE_CNT_SHIFT
106806. DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_MASK
106807. DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_SHIFT
106808. DMA_QM_0_CQ_STS1_CQ_BUSY_MASK
106809. DMA_QM_0_CQ_STS1_CQ_BUSY_SHIFT
106810. DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_MASK
106811. DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT
106812. DMA_QM_0_CQ_TSIZE_STS_VAL_MASK
106813. DMA_QM_0_CQ_TSIZE_STS_VAL_SHIFT
106814. DMA_QM_0_CQ_TSIZE_VAL_MASK
106815. DMA_QM_0_CQ_TSIZE_VAL_SHIFT
106816. DMA_QM_0_GLBL_CFG0_CP_EN_MASK
106817. DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT
106818. DMA_QM_0_GLBL_CFG0_CQF_EN_MASK
106819. DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT
106820. DMA_QM_0_GLBL_CFG0_DMA_EN_MASK
106821. DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT
106822. DMA_QM_0_GLBL_CFG0_PQF_EN_MASK
106823. DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT
106824. DMA_QM_0_GLBL_CFG1_CP_FLUSH_MASK
106825. DMA_QM_0_GLBL_CFG1_CP_FLUSH_SHIFT
106826. DMA_QM_0_GLBL_CFG1_CP_STOP_MASK
106827. DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT
106828. DMA_QM_0_GLBL_CFG1_CQF_FLUSH_MASK
106829. DMA_QM_0_GLBL_CFG1_CQF_FLUSH_SHIFT
106830. DMA_QM_0_GLBL_CFG1_CQF_STOP_MASK
106831. DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT
106832. DMA_QM_0_GLBL_CFG1_DMA_FLUSH_MASK
106833. DMA_QM_0_GLBL_CFG1_DMA_FLUSH_SHIFT
106834. DMA_QM_0_GLBL_CFG1_DMA_STOP_MASK
106835. DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
106836. DMA_QM_0_GLBL_CFG1_PQF_FLUSH_MASK
106837. DMA_QM_0_GLBL_CFG1_PQF_FLUSH_SHIFT
106838. DMA_QM_0_GLBL_CFG1_PQF_STOP_MASK
106839. DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT
106840. DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_MASK
106841. DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_SHIFT
106842. DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_MASK
106843. DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_SHIFT
106844. DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK
106845. DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT
106846. DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK
106847. DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT
106848. DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK
106849. DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT
106850. DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK
106851. DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT
106852. DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK
106853. DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT
106854. DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK
106855. DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT
106856. DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK
106857. DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT
106858. DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK
106859. DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT
106860. DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK
106861. DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT
106862. DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK
106863. DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT
106864. DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK
106865. DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT
106866. DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK
106867. DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT
106868. DMA_QM_0_GLBL_ERR_WDATA_VAL_MASK
106869. DMA_QM_0_GLBL_ERR_WDATA_VAL_SHIFT
106870. DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_MASK
106871. DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_SHIFT
106872. DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_MASK
106873. DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_SHIFT
106874. DMA_QM_0_GLBL_PROT_CP_ERR_PROT_MASK
106875. DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT
106876. DMA_QM_0_GLBL_PROT_CP_PROT_MASK
106877. DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT
106878. DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_MASK
106879. DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT
106880. DMA_QM_0_GLBL_PROT_CQF_PROT_MASK
106881. DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT
106882. DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_MASK
106883. DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT
106884. DMA_QM_0_GLBL_PROT_DMA_PROT_MASK
106885. DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT
106886. DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_MASK
106887. DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT
106888. DMA_QM_0_GLBL_PROT_PQF_PROT_MASK
106889. DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT
106890. DMA_QM_0_GLBL_SECURE_PROPS_ASID_MASK
106891. DMA_QM_0_GLBL_SECURE_PROPS_ASID_SHIFT
106892. DMA_QM_0_GLBL_SECURE_PROPS_MMBP_MASK
106893. DMA_QM_0_GLBL_SECURE_PROPS_MMBP_SHIFT
106894. DMA_QM_0_GLBL_STS0_CP_IDLE_MASK
106895. DMA_QM_0_GLBL_STS0_CP_IDLE_SHIFT
106896. DMA_QM_0_GLBL_STS0_CP_IS_STOP_MASK
106897. DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT
106898. DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK
106899. DMA_QM_0_GLBL_STS0_CQF_IDLE_SHIFT
106900. DMA_QM_0_GLBL_STS0_CQF_IS_STOP_MASK
106901. DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT
106902. DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK
106903. DMA_QM_0_GLBL_STS0_DMA_IDLE_SHIFT
106904. DMA_QM_0_GLBL_STS0_DMA_IS_STOP_MASK
106905. DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT
106906. DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK
106907. DMA_QM_0_GLBL_STS0_PQF_IDLE_SHIFT
106908. DMA_QM_0_GLBL_STS0_PQF_IS_STOP_MASK
106909. DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT
106910. DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_MASK
106911. DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT
106912. DMA_QM_0_GLBL_STS1_CP_RD_ERR_MASK
106913. DMA_QM_0_GLBL_STS1_CP_RD_ERR_SHIFT
106914. DMA_QM_0_GLBL_STS1_CP_STOP_OP_MASK
106915. DMA_QM_0_GLBL_STS1_CP_STOP_OP_SHIFT
106916. DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK
106917. DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT
106918. DMA_QM_0_GLBL_STS1_CQF_RD_ERR_MASK
106919. DMA_QM_0_GLBL_STS1_CQF_RD_ERR_SHIFT
106920. DMA_QM_0_GLBL_STS1_DMA_RD_ERR_MASK
106921. DMA_QM_0_GLBL_STS1_DMA_RD_ERR_SHIFT
106922. DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_MASK
106923. DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT
106924. DMA_QM_0_GLBL_STS1_DMA_WR_ERR_MASK
106925. DMA_QM_0_GLBL_STS1_DMA_WR_ERR_SHIFT
106926. DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_MASK
106927. DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT
106928. DMA_QM_0_GLBL_STS1_PQF_RD_ERR_MASK
106929. DMA_QM_0_GLBL_STS1_PQF_RD_ERR_SHIFT
106930. DMA_QM_0_MAX_OFFSET
106931. DMA_QM_0_PQ_ARUSER_NOSNOOP_MASK
106932. DMA_QM_0_PQ_ARUSER_NOSNOOP_SHIFT
106933. DMA_QM_0_PQ_ARUSER_WORD_MASK
106934. DMA_QM_0_PQ_ARUSER_WORD_SHIFT
106935. DMA_QM_0_PQ_BASE_HI_VAL_MASK
106936. DMA_QM_0_PQ_BASE_HI_VAL_SHIFT
106937. DMA_QM_0_PQ_BASE_LO_VAL_MASK
106938. DMA_QM_0_PQ_BASE_LO_VAL_SHIFT
106939. DMA_QM_0_PQ_BUF_ADDR_VAL_MASK
106940. DMA_QM_0_PQ_BUF_ADDR_VAL_SHIFT
106941. DMA_QM_0_PQ_BUF_RDATA_VAL_MASK
106942. DMA_QM_0_PQ_BUF_RDATA_VAL_SHIFT
106943. DMA_QM_0_PQ_CFG0_RESERVED_MASK
106944. DMA_QM_0_PQ_CFG0_RESERVED_SHIFT
106945. DMA_QM_0_PQ_CFG1_CREDIT_LIM_MASK
106946. DMA_QM_0_PQ_CFG1_CREDIT_LIM_SHIFT
106947. DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_MASK
106948. DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_SHIFT
106949. DMA_QM_0_PQ_CI_VAL_MASK
106950. DMA_QM_0_PQ_CI_VAL_SHIFT
106951. DMA_QM_0_PQ_PI_VAL_MASK
106952. DMA_QM_0_PQ_PI_VAL_SHIFT
106953. DMA_QM_0_PQ_PUSH0_PTR_LO_MASK
106954. DMA_QM_0_PQ_PUSH0_PTR_LO_SHIFT
106955. DMA_QM_0_PQ_PUSH1_PTR_HI_MASK
106956. DMA_QM_0_PQ_PUSH1_PTR_HI_SHIFT
106957. DMA_QM_0_PQ_PUSH2_TSIZE_MASK
106958. DMA_QM_0_PQ_PUSH2_TSIZE_SHIFT
106959. DMA_QM_0_PQ_PUSH3_CTL_MASK
106960. DMA_QM_0_PQ_PUSH3_CTL_SHIFT
106961. DMA_QM_0_PQ_PUSH3_RPT_MASK
106962. DMA_QM_0_PQ_PUSH3_RPT_SHIFT
106963. DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_MASK
106964. DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_SHIFT
106965. DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK
106966. DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT
106967. DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_MASK
106968. DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_SHIFT
106969. DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_MASK
106970. DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT
106971. DMA_QM_0_PQ_SIZE_VAL_MASK
106972. DMA_QM_0_PQ_SIZE_VAL_SHIFT
106973. DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_MASK
106974. DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_SHIFT
106975. DMA_QM_0_PQ_STS0_PQ_FREE_CNT_MASK
106976. DMA_QM_0_PQ_STS0_PQ_FREE_CNT_SHIFT
106977. DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_MASK
106978. DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_SHIFT
106979. DMA_QM_0_PQ_STS1_PQ_BUSY_MASK
106980. DMA_QM_0_PQ_STS1_PQ_BUSY_SHIFT
106981. DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_MASK
106982. DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT
106983. DMA_QM_0_SECTION
106984. DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT
106985. DMA_QM_1_MAX_OFFSET
106986. DMA_QM_1_SECTION
106987. DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT
106988. DMA_QM_2_MAX_OFFSET
106989. DMA_QM_2_SECTION
106990. DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT
106991. DMA_QM_3_MAX_OFFSET
106992. DMA_QM_3_SECTION
106993. DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT
106994. DMA_QM_4_MAX_OFFSET
106995. DMA_QM_4_SECTION
106996. DMA_QM_IDLE_MASK
106997. DMA_QUEUE_RESET
106998. DMA_Q_BASE_MASK
106999. DMA_RAM_SIZE
107000. DMA_RANGE_ALL
107001. DMA_RANGE_TRANSFERED
107002. DMA_RANGE_TRANSMITTED
107003. DMA_RATE_ADJ_MASK
107004. DMA_RATE_LIMIT_EN_MASK
107005. DMA_RBR_END
107006. DMA_RBR_FORMAT
107007. DMA_RBSZ_MASK
107008. DMA_RBSZ_SHIFT
107009. DMA_RB_BASE
107010. DMA_RB_CNTL
107011. DMA_RB_ENABLE
107012. DMA_RB_RPTR
107013. DMA_RB_RPTR_ADDR_HI
107014. DMA_RB_RPTR_ADDR_LO
107015. DMA_RB_SIZE
107016. DMA_RB_SWAP_ENABLE
107017. DMA_RB_WPTR
107018. DMA_RCV_BASE_ADDR
107019. DMA_RCV_POLL_DEMAND
107020. DMA_RD
107021. DMA_RD_REGULATOR_MAX_OFFSET
107022. DMA_RD_REGULATOR_SECTION
107023. DMA_READ
107024. DMA_READY
107025. DMA_READ_AHEAD
107026. DMA_READ_ALIGN
107027. DMA_READ_CHANS
107028. DMA_READ_DONE
107029. DMA_READ_ERR
107030. DMA_READ_FROM_HOST
107031. DMA_READ_LINE_ENABLE
107032. DMA_READ_MAX_128
107033. DMA_READ_MAX_16
107034. DMA_READ_MAX_1K
107035. DMA_READ_MAX_256
107036. DMA_READ_MAX_32
107037. DMA_READ_MAX_4
107038. DMA_READ_MAX_64
107039. DMA_READ_MULTIPLE_ENABLE
107040. DMA_READ_WRITE_MASK
107041. DMA_REGISTER_H
107042. DMA_REGISTER_MODE
107043. DMA_REGPAIR_LE
107044. DMA_REGS_OFFSET
107045. DMA_REMAP
107046. DMA_REQUEST
107047. DMA_REQUEST_ENABLE
107048. DMA_REQUEST_OUTSTANDING
107049. DMA_RESERVE
107050. DMA_RESERVED_BYTES
107051. DMA_RESET
107052. DMA_RESETFF
107053. DMA_RESET_FAS366
107054. DMA_RESIDUE_GRANULARITY_BURST
107055. DMA_RESIDUE_GRANULARITY_DESCRIPTOR
107056. DMA_RESIDUE_GRANULARITY_SEGMENT
107057. DMA_RESUME
107058. DMA_RETRY
107059. DMA_RETRY_ABORT
107060. DMA_RING0_TIMEOUT
107061. DMA_RING10_TIMEOUT
107062. DMA_RING11_TIMEOUT
107063. DMA_RING12_TIMEOUT
107064. DMA_RING13_TIMEOUT
107065. DMA_RING14_TIMEOUT
107066. DMA_RING15_TIMEOUT
107067. DMA_RING16_TIMEOUT
107068. DMA_RING1_TIMEOUT
107069. DMA_RING2_TIMEOUT
107070. DMA_RING3_TIMEOUT
107071. DMA_RING4_TIMEOUT
107072. DMA_RING5_TIMEOUT
107073. DMA_RING6_TIMEOUT
107074. DMA_RING7_TIMEOUT
107075. DMA_RING8_TIMEOUT
107076. DMA_RING9_TIMEOUT
107077. DMA_RINGS_SIZE
107078. DMA_RING_BUFFER_SIZE_MASK
107079. DMA_RING_BUF_EN_MASK
107080. DMA_RING_BUF_EN_SHIFT
107081. DMA_RING_BUF_PRIORITY_MASK
107082. DMA_RING_BUF_PRIORITY_SHIFT
107083. DMA_RING_BUF_SIZE
107084. DMA_RING_CFG
107085. DMA_RING_SIZE
107086. DMA_RING_SIZE_MASK
107087. DMA_RING_SIZE_SHIFT
107088. DMA_ROMCODE_BUG
107089. DMA_ROM_TABLE_MAX_OFFSET
107090. DMA_ROM_TABLE_SECTION
107091. DMA_RPTR_WRITEBACK_ENABLE
107092. DMA_RPTR_WRITEBACK_SWAP_ENABLE
107093. DMA_RPTR_WRITEBACK_TIMER
107094. DMA_RQ_C1_2PAGE_LOOP_BEGIN
107095. DMA_RQ_C1_AT_SAMPLE_END
107096. DMA_RQ_C1_BEFORE_LOOP_END
107097. DMA_RQ_C1_BEFORE_SAMPLE_END
107098. DMA_RQ_C1_COUNT_MASK
107099. DMA_RQ_C1_COUNT_SHIFT
107100. DMA_RQ_C1_DESTINATION_SCATTER
107101. DMA_RQ_C1_DEST_LINEAR
107102. DMA_RQ_C1_DEST_MOD1024
107103. DMA_RQ_C1_DEST_MOD128
107104. DMA_RQ_C1_DEST_MOD16
107105. DMA_RQ_C1_DEST_MOD256
107106. DMA_RQ_C1_DEST_MOD32
107107. DMA_RQ_C1_DEST_MOD512
107108. DMA_RQ_C1_DEST_MOD64
107109. DMA_RQ_C1_DEST_ON_HOST
107110. DMA_RQ_C1_DEST_SIZE_MASK
107111. DMA_RQ_C1_DONE_FLAG
107112. DMA_RQ_C1_FULL_PAGE
107113. DMA_RQ_C1_LOOP_BEGIN
107114. DMA_RQ_C1_LOOP_END_STATE_MASK
107115. DMA_RQ_C1_NOT_LOOP_END
107116. DMA_RQ_C1_OPTIMIZE_STATE
107117. DMA_RQ_C1_PAGE_MAP_ERROR
107118. DMA_RQ_C1_PAGE_MAP_MASK
107119. DMA_RQ_C1_PM_LOOP_NEXT_PENDING
107120. DMA_RQ_C1_PM_NEXT_PENDING
107121. DMA_RQ_C1_PM_NONE_PENDING
107122. DMA_RQ_C1_PM_RESERVED
107123. DMA_RQ_C1_SAMPLE_END_STATE_MASK
107124. DMA_RQ_C1_SOURCE_GATHER
107125. DMA_RQ_C1_SOURCE_LINEAR
107126. DMA_RQ_C1_SOURCE_MOD1024
107127. DMA_RQ_C1_SOURCE_MOD128
107128. DMA_RQ_C1_SOURCE_MOD16
107129. DMA_RQ_C1_SOURCE_MOD256
107130. DMA_RQ_C1_SOURCE_MOD32
107131. DMA_RQ_C1_SOURCE_MOD512
107132. DMA_RQ_C1_SOURCE_MOD64
107133. DMA_RQ_C1_SOURCE_ON_HOST
107134. DMA_RQ_C1_SOURCE_SIZE_MASK
107135. DMA_RQ_C1_WRITEBACK_DEST_FLAG
107136. DMA_RQ_C1_WRITEBACK_SRC_FLAG
107137. DMA_RQ_C2_AC_8_TO_16_BIT
107138. DMA_RQ_C2_AC_ENDIAN_CONVERT
107139. DMA_RQ_C2_AC_MONO_TO_STEREO
107140. DMA_RQ_C2_AC_NONE
107141. DMA_RQ_C2_AC_SIGNED_CONVERT
107142. DMA_RQ_C2_AUDIO_CONVERT_MASK
107143. DMA_RQ_C2_LOOP_END_MASK
107144. DMA_RQ_C2_LOOP_END_SHIFT
107145. DMA_RQ_C2_LOOP_MASK
107146. DMA_RQ_C2_MULTI_PAGE_LOOP
107147. DMA_RQ_C2_NO_LOOP
107148. DMA_RQ_C2_NO_VIRTUAL_SIGNAL
107149. DMA_RQ_C2_ONE_PAGE_LOOP
107150. DMA_RQ_C2_SIGNAL_DEST_PINGPONG
107151. DMA_RQ_C2_SIGNAL_EVERY_DMA
107152. DMA_RQ_C2_SIGNAL_LOOP_BACK
107153. DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE
107154. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG
107155. DMA_RQ_C2_TWO_PAGE_LOOP
107156. DMA_RQ_C2_VIRTUAL_CHANNEL_MASK
107157. DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT
107158. DMA_RQ_C2_VIRTUAL_SIGNAL_MASK
107159. DMA_RQ_CONTROL1
107160. DMA_RQ_CONTROL2
107161. DMA_RQ_DESTINATION_ADDR
107162. DMA_RQ_LOOP_START_ADDR
107163. DMA_RQ_NEXT_PAGE_ADDR
107164. DMA_RQ_NEXT_PAGE_SGDESC
107165. DMA_RQ_PAGE_MAP_ADDR
107166. DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK
107167. DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT
107168. DMA_RQ_PMA_PAGE_TABLE_MASK
107169. DMA_RQ_PMA_PAGE_TABLE_SHIFT
107170. DMA_RQ_POST_LOOP_ADDR
107171. DMA_RQ_SD_ADDRESS_MASK
107172. DMA_RQ_SD_ADDRESS_SHIFT
107173. DMA_RQ_SD_END_FLAG
107174. DMA_RQ_SD_ERROR_FLAG
107175. DMA_RQ_SD_MEMORY_ID_MASK
107176. DMA_RQ_SD_OMNIMEM_ADDR
107177. DMA_RQ_SD_SP_DEBUG_ADDR
107178. DMA_RQ_SD_SP_PARAM_ADDR
107179. DMA_RQ_SD_SP_PROGRAM_ADDR
107180. DMA_RQ_SD_SP_SAMPLE_ADDR
107181. DMA_RQ_SOURCE_ADDR
107182. DMA_RSSR
107183. DMA_RST
107184. DMA_RST_ENET
107185. DMA_RST_SCSI
107186. DMA_RTADDR_RTT
107187. DMA_RTADDR_SMT
107188. DMA_RTOR
107189. DMA_RUN_SOMETHING1
107190. DMA_RUN_SOMETHING2
107191. DMA_RWCTRL_ASSERT_ALL_BE
107192. DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
107193. DMA_RWCTRL_DIS_CACHE_ALIGNMENT
107194. DMA_RWCTRL_ONE_DMA
107195. DMA_RWCTRL_PCI_READ_CMD
107196. DMA_RWCTRL_PCI_READ_CMD_SHIFT
107197. DMA_RWCTRL_PCI_WRITE_CMD
107198. DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
107199. DMA_RWCTRL_READ_BNDRY_1024
107200. DMA_RWCTRL_READ_BNDRY_128
107201. DMA_RWCTRL_READ_BNDRY_128_PCIX
107202. DMA_RWCTRL_READ_BNDRY_16
107203. DMA_RWCTRL_READ_BNDRY_256
107204. DMA_RWCTRL_READ_BNDRY_256_PCIX
107205. DMA_RWCTRL_READ_BNDRY_32
107206. DMA_RWCTRL_READ_BNDRY_384_PCIX
107207. DMA_RWCTRL_READ_BNDRY_512
107208. DMA_RWCTRL_READ_BNDRY_64
107209. DMA_RWCTRL_READ_BNDRY_DISAB
107210. DMA_RWCTRL_READ_BNDRY_MASK
107211. DMA_RWCTRL_READ_WATER
107212. DMA_RWCTRL_READ_WATER_SHIFT
107213. DMA_RWCTRL_TAGGED_STAT_WA
107214. DMA_RWCTRL_USE_MEM_READ_MULT
107215. DMA_RWCTRL_WRITE_BNDRY_1024
107216. DMA_RWCTRL_WRITE_BNDRY_128
107217. DMA_RWCTRL_WRITE_BNDRY_128_PCIE
107218. DMA_RWCTRL_WRITE_BNDRY_128_PCIX
107219. DMA_RWCTRL_WRITE_BNDRY_16
107220. DMA_RWCTRL_WRITE_BNDRY_256
107221. DMA_RWCTRL_WRITE_BNDRY_256_PCIX
107222. DMA_RWCTRL_WRITE_BNDRY_32
107223. DMA_RWCTRL_WRITE_BNDRY_384_PCIX
107224. DMA_RWCTRL_WRITE_BNDRY_512
107225. DMA_RWCTRL_WRITE_BNDRY_64
107226. DMA_RWCTRL_WRITE_BNDRY_64_PCIE
107227. DMA_RWCTRL_WRITE_BNDRY_DISAB
107228. DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
107229. DMA_RWCTRL_WRITE_BNDRY_MASK
107230. DMA_RWCTRL_WRITE_WATER
107231. DMA_RWCTRL_WRITE_WATER_SHIFT
107232. DMA_RW_POINTER_MASK
107233. DMA_RX
107234. DMA_RXEDMACR
107235. DMA_RXEDMACR_RDPS_INDEX
107236. DMA_RXEDMACR_RDPS_WIDTH
107237. DMA_RXGCR
107238. DMA_RXOR12
107239. DMA_RXOR123
107240. DMA_RXOR124
107241. DMA_RXOR125
107242. DMA_RX_ALL_MULTICAST
107243. DMA_RX_AXI_BUS_ERR
107244. DMA_RX_BRDCAST
107245. DMA_RX_BROADCAST
107246. DMA_RX_BUFFER_ECC_ERR
107247. DMA_RX_BURST_SIZE
107248. DMA_RX_CHK_V12
107249. DMA_RX_CHK_V3PLUS
107250. DMA_RX_CLK_CGC_ON
107251. DMA_RX_CRC_ERROR
107252. DMA_RX_CSUM_IP
107253. DMA_RX_CSUM_TCP
107254. DMA_RX_CSUM_UDP
107255. DMA_RX_DATA_LEN_OVERFLOW
107256. DMA_RX_DATA_LEN_UNDERFLOW
107257. DMA_RX_DATA_OFFSET_ERR
107258. DMA_RX_DATA_OVERFLOW_ERR
107259. DMA_RX_DATA_SGL_OVERFLOW
107260. DMA_RX_DATA_SGL_OVERFLOW_ERR
107261. DMA_RX_DATA_UNDERFLOW_ERR
107262. DMA_RX_DIF_APP_ERR
107263. DMA_RX_DIF_CRC_ERR
107264. DMA_RX_DIF_RPP_ERR
107265. DMA_RX_DIF_SGL_OVERFLOW
107266. DMA_RX_DIF_SGL_OVERFLOW_ERR
107267. DMA_RX_ENABLE
107268. DMA_RX_ERR
107269. DMA_RX_ERROR
107270. DMA_RX_ERR_BASE
107271. DMA_RX_EVENT_EN
107272. DMA_RX_FI_MASK
107273. DMA_RX_FI_SHIFT
107274. DMA_RX_FLOW_ENABLE
107275. DMA_RX_IRQ_EN
107276. DMA_RX_LG
107277. DMA_RX_MAX_ERR_CODE
107278. DMA_RX_MODE
107279. DMA_RX_MULT
107280. DMA_RX_NO
107281. DMA_RX_OV
107282. DMA_RX_PIO_DATA_LEN_ERR
107283. DMA_RX_PRIO_SHIFT
107284. DMA_RX_PROMISCUOUS
107285. DMA_RX_RAM_ECC_ERR
107286. DMA_RX_RDSETUP_ACTIVE_ERR
107287. DMA_RX_RDSETUP_ESTATUS_ERR
107288. DMA_RX_RDSETUP_LEN_ODD_ERR
107289. DMA_RX_RDSETUP_LEN_OVER_ERR
107290. DMA_RX_RDSETUP_LEN_ZERO_ERR
107291. DMA_RX_RDSETUP_OFFSET_ERR
107292. DMA_RX_RDSETUP_STATUS_BSY_ERR
107293. DMA_RX_RDSETUP_STATUS_DRQ_ERR
107294. DMA_RX_RDSETUP_STATUS_ERR
107295. DMA_RX_RESP_BUFFER_OVERFLOW_ERR
107296. DMA_RX_RESP_BUF_OVERFLOW
107297. DMA_RX_RING_SZ
107298. DMA_RX_RUNNING
107299. DMA_RX_RXER
107300. DMA_RX_SATA_FRAME_TYPE_ERR
107301. DMA_RX_SHUTDOWN
107302. DMA_RX_SIZE
107303. DMA_RX_START
107304. DMA_RX_STATUS
107305. DMA_RX_STATUS_BUSY_MSK
107306. DMA_RX_STATUS_BUSY_OFF
107307. DMA_RX_TIMEOUT
107308. DMA_RX_TIMEOUT_DEFAULT
107309. DMA_RX_TIMEOUT_MASK
107310. DMA_RX_TIMEOUT_SHIFT
107311. DMA_RX_UNEXP_NORM_RESP_ERR
107312. DMA_RX_UNEXP_RDFRAME_ERR
107313. DMA_RX_UNEXP_RETRANS_RESP_ERR
107314. DMA_RX_UNEXP_RX_DATA_ERR
107315. DMA_RX_UNICAST
107316. DMA_RX_UNKNOWN_FRM_ERR
107317. DMA_RX_WATCHDOG
107318. DMA_RxAlign
107319. DMA_RxAlign_1
107320. DMA_RxAlign_2
107321. DMA_RxAlign_3
107322. DMA_RxBigE
107323. DMA_S
107324. DMA_S0
107325. DMA_S1
107326. DMA_SAFETY_INT_STATUS
107327. DMA_SAFE_GUARD
107328. DMA_SAR
107329. DMA_SA_H4BIT
107330. DMA_SBMR
107331. DMA_SBMR_AAL_INDEX
107332. DMA_SBMR_AAL_WIDTH
107333. DMA_SBMR_BLEN_128
107334. DMA_SBMR_BLEN_128_LEN
107335. DMA_SBMR_BLEN_128_POS
107336. DMA_SBMR_BLEN_16
107337. DMA_SBMR_BLEN_256
107338. DMA_SBMR_BLEN_256_LEN
107339. DMA_SBMR_BLEN_256_POS
107340. DMA_SBMR_BLEN_32
107341. DMA_SBMR_BLEN_4
107342. DMA_SBMR_BLEN_64
107343. DMA_SBMR_BLEN_64_LEN
107344. DMA_SBMR_BLEN_64_POS
107345. DMA_SBMR_BLEN_8
107346. DMA_SBMR_BLEN_INDEX
107347. DMA_SBMR_BLEN_WIDTH
107348. DMA_SBMR_EAME_INDEX
107349. DMA_SBMR_EAME_LEN
107350. DMA_SBMR_EAME_POS
107351. DMA_SBMR_EAME_WIDTH
107352. DMA_SBMR_RD_OSR_LMT_INDEX
107353. DMA_SBMR_RD_OSR_LMT_WIDTH
107354. DMA_SBMR_UNDEF_INDEX
107355. DMA_SBMR_UNDEF_LEN
107356. DMA_SBMR_UNDEF_POS
107357. DMA_SBMR_UNDEF_WIDTH
107358. DMA_SBMR_WR_OSR_LMT_INDEX
107359. DMA_SBMR_WR_OSR_LMT_WIDTH
107360. DMA_SCATTER_GATHER_DONE_INTERRUPT
107361. DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE
107362. DMA_SCATTER_GATHER_ENABLE
107363. DMA_SCB_BURST_SIZE
107364. DMA_SCB_BURST_SIZE_MASK
107365. DMA_SCHED_CTRL
107366. DMA_SCHED_CTRL_EN
107367. DMA_SCHED_WORD
107368. DMA_SCRATCH_PAD
107369. DMA_SCSI_DISAB
107370. DMA_SCSI_ON
107371. DMA_SCSI_SBUS64
107372. DMA_SDHCI_RX
107373. DMA_SDHCI_TX
107374. DMA_SDM845_MASK
107375. DMA_SELECT_INDEX
107376. DMA_SEMAPHORE_ADDR
107377. DMA_SEM_INCOMPLETE_TIMER_CNTL
107378. DMA_SEM_WAIT_FAIL_TIMER_CNTL
107379. DMA_SETSTART
107380. DMA_SETUP_msk2DE
107381. DMA_SETUP_mskCIE
107382. DMA_SETUP_mskCOA
107383. DMA_SETUP_mskEIE
107384. DMA_SETUP_mskESTR
107385. DMA_SETUP_mskLM
107386. DMA_SETUP_mskSIE
107387. DMA_SETUP_mskTDIR
107388. DMA_SETUP_mskTES
107389. DMA_SETUP_mskUE
107390. DMA_SETUP_off2DE
107391. DMA_SETUP_offCIE
107392. DMA_SETUP_offCOA
107393. DMA_SETUP_offEIE
107394. DMA_SETUP_offESTR
107395. DMA_SETUP_offLM
107396. DMA_SETUP_offSIE
107397. DMA_SETUP_offTDIR
107398. DMA_SETUP_offTES
107399. DMA_SETUP_offUE
107400. DMA_SET_REGISTERS
107401. DMA_SGL_TYPE
107402. DMA_SG_LOOP_END_FLAG
107403. DMA_SG_NEXT_ENTRY_MASK
107404. DMA_SG_NEXT_ENTRY_SHIFT
107405. DMA_SG_SAMPLE_END_FLAG
107406. DMA_SG_SAMPLE_END_MASK
107407. DMA_SG_SAMPLE_END_SHIFT
107408. DMA_SG_SIGNAL_END_FLAG
107409. DMA_SG_SIGNAL_PAGE_FLAG
107410. DMA_SHUTDOWN_CMPL
107411. DMA_SIZE
107412. DMA_SLAVE
107413. DMA_SLAVE_BUSWIDTH_16_BYTES
107414. DMA_SLAVE_BUSWIDTH_1_BYTE
107415. DMA_SLAVE_BUSWIDTH_2_BYTES
107416. DMA_SLAVE_BUSWIDTH_32_BYTES
107417. DMA_SLAVE_BUSWIDTH_3_BYTES
107418. DMA_SLAVE_BUSWIDTH_4_BYTES
107419. DMA_SLAVE_BUSWIDTH_64_BYTES
107420. DMA_SLAVE_BUSWIDTH_8_BYTES
107421. DMA_SLAVE_BUSWIDTH_UNDEFINED
107422. DMA_SLOT_SIZE
107423. DMA_SOMETHING_ELSE
107424. DMA_SOP
107425. DMA_SPLIT_BUS_MODE
107426. DMA_SRAM
107427. DMA_SRAM_TO_DRAM
107428. DMA_SRAM_TO_HOST
107429. DMA_SRAM_TO_SRAM
107430. DMA_SRBM_POLL_PACKET
107431. DMA_SRBM_READ_PACKET
107432. DMA_SRC_ADDR_OFFSET
107433. DMA_SRC_LAST_TRANSFER
107434. DMA_SRC_LEN_OFFSET
107435. DMA_SREG
107436. DMA_START
107437. DMA_STARTS
107438. DMA_START_ADDR
107439. DMA_START_ADDR_HI
107440. DMA_STAT
107441. DMA_STATE_RUN
107442. DMA_STATE_STOP
107443. DMA_STATUS
107444. DMA_STATUS0_ERR
107445. DMA_STATUS2_ERR
107446. DMA_STATUS_ACCESS
107447. DMA_STATUS_AIS
107448. DMA_STATUS_BITS_PER_CH
107449. DMA_STATUS_BUS_ERR
107450. DMA_STATUS_CHAN0
107451. DMA_STATUS_CHAN1
107452. DMA_STATUS_CHAN2
107453. DMA_STATUS_CHAN3
107454. DMA_STATUS_CHAN4
107455. DMA_STATUS_CHAN5
107456. DMA_STATUS_CHAN6
107457. DMA_STATUS_CHAN7
107458. DMA_STATUS_CSR
107459. DMA_STATUS_CTRL
107460. DMA_STATUS_DESC_READ
107461. DMA_STATUS_EB_MASK
107462. DMA_STATUS_EB_RX_ABORT
107463. DMA_STATUS_EB_TX_ABORT
107464. DMA_STATUS_ERI
107465. DMA_STATUS_ETI
107466. DMA_STATUS_FBI
107467. DMA_STATUS_FM_SPDAT_ECC
107468. DMA_STATUS_FM_WRITE_ECC
107469. DMA_STATUS_GLI
107470. DMA_STATUS_GLPII
107471. DMA_STATUS_GMI
107472. DMA_STATUS_GPI
107473. DMA_STATUS_IDLE
107474. DMA_STATUS_IRQ
107475. DMA_STATUS_MAC
107476. DMA_STATUS_MASK_BITS
107477. DMA_STATUS_MTL
107478. DMA_STATUS_NIS
107479. DMA_STATUS_OVF
107480. DMA_STATUS_READ_ECC
107481. DMA_STATUS_REG
107482. DMA_STATUS_RI
107483. DMA_STATUS_RPS
107484. DMA_STATUS_RS_MASK
107485. DMA_STATUS_RS_SHIFT
107486. DMA_STATUS_RU
107487. DMA_STATUS_RWT
107488. DMA_STATUS_SHIFT_BITS
107489. DMA_STATUS_SYSTEM_WRITE_ECC
107490. DMA_STATUS_TI
107491. DMA_STATUS_TJT
107492. DMA_STATUS_TPS
107493. DMA_STATUS_TS_MASK
107494. DMA_STATUS_TS_SHIFT
107495. DMA_STATUS_TU
107496. DMA_STATUS_UNF
107497. DMA_STATUS_WAIT
107498. DMA_STATUS_mskDERR
107499. DMA_STATUS_mskEBUS
107500. DMA_STATUS_mskESUP
107501. DMA_STATUS_mskEUNA
107502. DMA_STATUS_mskIOOR
107503. DMA_STATUS_mskIUNA
107504. DMA_STATUS_mskSTAT
107505. DMA_STATUS_mskSTUNA
107506. DMA_STATUS_offDERR
107507. DMA_STATUS_offEBUS
107508. DMA_STATUS_offESUP
107509. DMA_STATUS_offEUNA
107510. DMA_STATUS_offIOOR
107511. DMA_STATUS_offIUNA
107512. DMA_STATUS_offSTAT
107513. DMA_STATUS_offSTUNA
107514. DMA_STAT_CHAIN
107515. DMA_STAT_DONE
107516. DMA_STAT_ERR
107517. DMA_STAT_FINI
107518. DMA_STAT_HALT
107519. DMA_ST_AB
107520. DMA_ST_INT
107521. DMA_ST_OFL
107522. DMA_ST_WRITE
107523. DMA_SUPPORTED
107524. DMA_SWIntReq
107525. DMA_SW_ERR
107526. DMA_SYSCONFIG_AUTOIDLE
107527. DMA_SYSCONFIG_CLOCKACTIVITY_MASK
107528. DMA_SYSCONFIG_EMUFREE
107529. DMA_SYSCONFIG_MIDLEMODE
107530. DMA_SYSCONFIG_MIDLEMODE_MASK
107531. DMA_SYSCONFIG_SIDLEMODE
107532. DMA_SYSCONFIG_SIDLEMODE_MASK
107533. DMA_SYSCONFIG_SOFTRESET
107534. DMA_SYS_BUS_AAL
107535. DMA_SYS_BUS_FB
107536. DMA_SYS_BUS_MB
107537. DMA_SYS_BUS_MODE
107538. DMA_TABLE_BYTES
107539. DMA_TAGSTATUS_INTR_ALL
107540. DMA_TAGSTATUS_INTR_ANY
107541. DMA_TAIL_ENABLE
107542. DMA_TCNT_mskTCNT
107543. DMA_TCNT_offTCNT
107544. DMA_TC_BIT
107545. DMA_TC_CLEAR_REG
107546. DMA_TC_EQ_0
107547. DMA_TC_INT_CLR_REG
107548. DMA_TDFDQ
107549. DMA_TDMA
107550. DMA_TEARDOWN
107551. DMA_TEI_CAPABLE
107552. DMA_TERM
107553. DMA_TERM_CNTR
107554. DMA_TEST
107555. DMA_THREAD_FIFO_25
107556. DMA_THREAD_FIFO_50
107557. DMA_THREAD_FIFO_75
107558. DMA_THREAD_FIFO_NONE
107559. DMA_THREAD_RESERVE_NORM
107560. DMA_THREAD_RESERVE_ONET
107561. DMA_THREAD_RESERVE_THREET
107562. DMA_THREAD_RESERVE_TWOT
107563. DMA_THRESHOLD
107564. DMA_THRESH_0
107565. DMA_THRESH_0_1
107566. DMA_THRESH_0_1_2
107567. DMA_THRESH_16W
107568. DMA_THRESH_1W
107569. DMA_THRESH_2W
107570. DMA_THRESH_32W
107571. DMA_THRESH_4W
107572. DMA_THRESH_8W
107573. DMA_THRESH_COMMQ_SHIFT
107574. DMA_THRESH_NONE
107575. DMA_THRESH_READ_INT_BUF_MASK
107576. DMA_THRESH_READ_INT_BUF_SHIFT
107577. DMA_THRESH_WRITE_INT_BUF_MASK
107578. DMA_TILING_CONFIG
107579. DMA_TILING_CONFIG2
107580. DMA_TIM
107581. DMA_TIMEOUT
107582. DMA_TIMEOUT_ENABLE
107583. DMA_TIMEOUT_MASK
107584. DMA_TIMEOUT_MS
107585. DMA_TIMEOUT_VAL
107586. DMA_TIMER_0
107587. DMA_TIMER_1
107588. DMA_TIMER_2
107589. DMA_TIMER_3
107590. DMA_TIMER_INTERVAL
107591. DMA_TLB_DID
107592. DMA_TLB_DSI_FLUSH
107593. DMA_TLB_FLUSH_GRANU_OFFSET
107594. DMA_TLB_GLOBAL_FLUSH
107595. DMA_TLB_IAIG
107596. DMA_TLB_IH_NONLEAF
107597. DMA_TLB_IIRG
107598. DMA_TLB_IVT
107599. DMA_TLB_MAX_SIZE
107600. DMA_TLB_PSI_FLUSH
107601. DMA_TLB_READ_DRAIN
107602. DMA_TLB_WRITE_DRAIN
107603. DMA_TO_CPU
107604. DMA_TO_DEVICE
107605. DMA_TPS_STOPPED
107606. DMA_TPS_SUSPENDED
107607. DMA_TRACKER_LIST_SIZE8
107608. DMA_TRANSACTION_DONE_INTERRUPT
107609. DMA_TRANSFER
107610. DMA_TRANSFER_BITS
107611. DMA_TRANSFER_FRAME_SIZE_NWORDS
107612. DMA_TRANSFER_LIODN_MASK
107613. DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS
107614. DMA_TRANSFER_PORTID_MASK
107615. DMA_TRANSFER_PORTID_SHIFT
107616. DMA_TRANSFER_SIZE
107617. DMA_TRANSFER_TNUM_MASK
107618. DMA_TRANSFER_TNUM_SHIFT
107619. DMA_TRANSMITION_START
107620. DMA_TRANSMITION_STOP
107621. DMA_TRANS_ABORTED
107622. DMA_TRANS_NOERROR
107623. DMA_TRANS_NONE
107624. DMA_TRANS_READ_FAILED
107625. DMA_TRANS_UNIT_188
107626. DMA_TRANS_WRITE_FAILED
107627. DMA_TRIES
107628. DMA_TS8
107629. DMA_TSB_SWAP_EN
107630. DMA_TX
107631. DMA_TXEDMACR
107632. DMA_TXEDMACR_TDPS_INDEX
107633. DMA_TXEDMACR_TDPS_WIDTH
107634. DMA_TXGCR
107635. DMA_TX_APPEND_CRC
107636. DMA_TX_AXI_BUS_ERR
107637. DMA_TX_BASE_ADDR
107638. DMA_TX_BURST_SIZE
107639. DMA_TX_CLK_CGC_ON
107640. DMA_TX_CRC_ENABLE
107641. DMA_TX_CSUM_IP
107642. DMA_TX_CSUM_TCP
107643. DMA_TX_CSUM_UDP
107644. DMA_TX_DATA_SGL_OVERFLOW
107645. DMA_TX_DATA_SGL_OVERFLOW_ERR
107646. DMA_TX_DATA_UNDERFLOW_ERR
107647. DMA_TX_DFX0
107648. DMA_TX_DFX1
107649. DMA_TX_DFX1_IPTT_MSK
107650. DMA_TX_DFX1_IPTT_OFF
107651. DMA_TX_DIF_APP_ERR
107652. DMA_TX_DIF_CRC_ERR
107653. DMA_TX_DIF_LEN_ALIGN_ERR
107654. DMA_TX_DIF_RPP_ERR
107655. DMA_TX_DIF_SGL_OVERFLOW
107656. DMA_TX_DIF_SGL_OVERFLOW_ERR
107657. DMA_TX_DO_CSUM
107658. DMA_TX_ENABLE
107659. DMA_TX_ERR
107660. DMA_TX_ERR_BASE
107661. DMA_TX_ERR_MSK
107662. DMA_TX_ERR_OFF
107663. DMA_TX_EVENT_EN
107664. DMA_TX_FIFO_DFX0
107665. DMA_TX_FILT_EINFO
107666. DMA_TX_FILT_PSWORDS
107667. DMA_TX_FLOW_ENABLE
107668. DMA_TX_IRQ_EN
107669. DMA_TX_LOOPBACK
107670. DMA_TX_MAX_ERR_CODE
107671. DMA_TX_MODE
107672. DMA_TX_OW_CRC
107673. DMA_TX_PAD_ENABLE
107674. DMA_TX_PRIO_SHIFT
107675. DMA_TX_QTAG_SHIFT
107676. DMA_TX_RAM_ECC_ERR
107677. DMA_TX_RING_SZ
107678. DMA_TX_SIZE
107679. DMA_TX_STATUS
107680. DMA_TX_STATUS_BUSY_MSK
107681. DMA_TX_STATUS_BUSY_OFF
107682. DMA_TX_TYPE_END
107683. DMA_TX_UNDERRUN
107684. DMA_TX_UNEXP_RETRANS_ERR
107685. DMA_TX_UNEXP_XFER_ERR
107686. DMA_TX_UNEXP_XFER_RDY_ERR
107687. DMA_TX_XFER_LEN_OVERFLOW
107688. DMA_TX_XFER_OFFSET_ERR
107689. DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR
107690. DMA_TX_XFER_RDY_OFFSET_ERR
107691. DMA_TYPE_FIFO
107692. DMA_TYPE_MEMORY
107693. DMA_TestMode
107694. DMA_TxBigE
107695. DMA_TxWakeUp
107696. DMA_U
107697. DMA_UART_RX
107698. DMA_UART_TX
107699. DMA_UPPER
107700. DMA_V
107701. DMA_VALID
107702. DMA_VALID_BIT_ENABLE
107703. DMA_VALID_BIT_POLLING_ENABLE
107704. DMA_VERHME
107705. DMA_VERS0
107706. DMA_VERS1
107707. DMA_VERS2
107708. DMA_VERSPLUS
107709. DMA_VIDEO_DROP
107710. DMA_VIDEO_RX
107711. DMA_VIRTUAL_FLOPPY
107712. DMA_VIRTUAL_SOUND
107713. DMA_WAIT_TIMEOUT
107714. DMA_WBACK
107715. DMA_WBACK_INV
107716. DMA_WBDMA1
107717. DMA_WBDMA16
107718. DMA_WBDMA2
107719. DMA_WBDMA4
107720. DMA_WD
107721. DMA_WEIGHT
107722. DMA_WINDOW_SIZE_MASK
107723. DMA_WORD0_CMP_ENABLE
107724. DMA_WORD0_CMP_VALUE
107725. DMA_WORD1_CMP_ENABLE
107726. DMA_WORD1_CMP_ENABLE_MASTER
107727. DMA_WORD1_CMP_ENABLE_SELF_ID
107728. DMA_WORD1_CMP_MATCH_BROADCAST
107729. DMA_WORD1_CMP_MATCH_BUS_BCAST
107730. DMA_WORD1_CMP_MATCH_EXACT
107731. DMA_WORD1_CMP_MATCH_LOCAL_NODE
107732. DMA_WORD1_CMP_MATCH_OTHERBUS
107733. DMA_WORD1_CMP_VALUE
107734. DMA_WORTH_THRESHOLD
107735. DMA_WR
107736. DMA_WRAP
107737. DMA_WRITE
107738. DMA_WRITE_ALL_ALIGN
107739. DMA_WRITE_CHANS
107740. DMA_WRITE_DONE
107741. DMA_WRITE_ERR
107742. DMA_WRITE_MAX_128
107743. DMA_WRITE_MAX_16
107744. DMA_WRITE_MAX_1K
107745. DMA_WRITE_MAX_256
107746. DMA_WRITE_MAX_32
107747. DMA_WRITE_MAX_4
107748. DMA_WRITE_MAX_64
107749. DMA_WRITE_P
107750. DMA_WRITE_TO_HOST
107751. DMA_WR_REGULATOR_MAX_OFFSET
107752. DMA_WR_REGULATOR_SECTION
107753. DMA_WSRA
107754. DMA_WSRB
107755. DMA_XFER
107756. DMA_XFER_ACK
107757. DMA_XFER_MODE
107758. DMA_XMT_POLL_DEMAND
107759. DMA_XOFF_THRESHOLD_MASK
107760. DMA_XOFF_THRESHOLD_SHIFT
107761. DMA_XON_THREHOLD_MASK
107762. DMA_XOR
107763. DMA_XOR_VAL
107764. DMA_XSRA
107765. DMA_XSRB
107766. DMA_Y
107767. DMA_YSRA
107768. DMA_YSRB
107769. DMA_ZONE
107770. DMA_buff_in
107771. DMA_buff_out
107772. DMA_control
107773. DMA_single_in
107774. DMA_single_out
107775. DMA_sync
107776. DMA_sync_char
107777. DMC
107778. DMC0
107779. DMC1
107780. DMCE
107781. DMCFS_260M
107782. DMCFS_26M
107783. DMCR
107784. DMCRIT
107785. DMCR_CAP_RMWAKUP
107786. DMCR_CHIP_EN
107787. DMCR_GLINT_EN
107788. DMCR_GOSUSP
107789. DMCR_HALF_SPEED
107790. DMCR_HS_EN
107791. DMCR_SFRST
107792. DMCTRL
107793. DMCTRL_BURSTLEN
107794. DMCTRL_D_THRHLD
107795. DMCTRL_MEM_REF
107796. DMCTRL_MEM_REF_ACT
107797. DMCTRL_MEM_REF_BOTH
107798. DMCTRL_MEM_REF_HB
107799. DMCTRL_MEM_REF_VB
107800. DMCTRL_UV_THRHLD
107801. DMCTRL_V_THRHLD
107802. DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK
107803. DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT
107804. DMCUB_CNTL__DMCUB_ENABLE_MASK
107805. DMCUB_CNTL__DMCUB_ENABLE__SHIFT
107806. DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK
107807. DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT
107808. DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK
107809. DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT
107810. DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK
107811. DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT
107812. DMCUB_CNTL__DMCUB_SOFT_RESET_MASK
107813. DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT
107814. DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK
107815. DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT
107816. DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK
107817. DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT
107818. DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK
107819. DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT
107820. DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK
107821. DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT
107822. DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK
107823. DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT
107824. DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK
107825. DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT
107826. DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK
107827. DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT
107828. DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK
107829. DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT
107830. DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK
107831. DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT
107832. DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK
107833. DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT
107834. DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK
107835. DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT
107836. DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK
107837. DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT
107838. DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK
107839. DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT
107840. DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK
107841. DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT
107842. DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK
107843. DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT
107844. DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK
107845. DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT
107846. DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK
107847. DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT
107848. DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK
107849. DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT
107850. DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK
107851. DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT
107852. DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK
107853. DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT
107854. DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK
107855. DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT
107856. DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK
107857. DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT
107858. DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK
107859. DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT
107860. DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK
107861. DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT
107862. DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK
107863. DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT
107864. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK
107865. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT
107866. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK
107867. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT
107868. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK
107869. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT
107870. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK
107871. DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT
107872. DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK
107873. DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT
107874. DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK
107875. DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT
107876. DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK
107877. DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT
107878. DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK
107879. DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT
107880. DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK
107881. DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT
107882. DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK
107883. DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT
107884. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK
107885. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT
107886. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK
107887. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT
107888. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK
107889. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT
107890. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK
107891. DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT
107892. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK
107893. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT
107894. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK
107895. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT
107896. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK
107897. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT
107898. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK
107899. DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT
107900. DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK
107901. DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT
107902. DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK
107903. DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT
107904. DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK
107905. DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT
107906. DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK
107907. DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT
107908. DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK
107909. DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT
107910. DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK
107911. DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT
107912. DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK
107913. DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT
107914. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK
107915. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT
107916. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK
107917. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT
107918. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK
107919. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT
107920. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK
107921. DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT
107922. DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK
107923. DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT
107924. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK
107925. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT
107926. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK
107927. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT
107928. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK
107929. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT
107930. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK
107931. DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT
107932. DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK
107933. DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT
107934. DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK
107935. DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT
107936. DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK
107937. DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT
107938. DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK
107939. DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT
107940. DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK
107941. DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT
107942. DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK
107943. DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT
107944. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK
107945. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT
107946. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK
107947. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT
107948. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK
107949. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT
107950. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK
107951. DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT
107952. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK
107953. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT
107954. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK
107955. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT
107956. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK
107957. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT
107958. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK
107959. DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT
107960. DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK
107961. DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT
107962. DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK
107963. DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT
107964. DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK
107965. DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT
107966. DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK
107967. DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT
107968. DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK
107969. DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT
107970. DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK
107971. DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT
107972. DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK
107973. DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT
107974. DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK
107975. DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT
107976. DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK
107977. DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT
107978. DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK
107979. DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT
107980. DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK
107981. DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT
107982. DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK
107983. DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT
107984. DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK
107985. DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT
107986. DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK
107987. DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT
107988. DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK
107989. DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT
107990. DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK
107991. DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT
107992. DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK
107993. DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT
107994. DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK
107995. DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT
107996. DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK
107997. DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT
107998. DMCUB_PROC_ID__DMCUB_PROC_ID_MASK
107999. DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT
108000. DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK
108001. DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT
108002. DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK
108003. DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT
108004. DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK
108005. DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT
108006. DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK
108007. DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT
108008. DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK
108009. DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT
108010. DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK
108011. DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT
108012. DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK
108013. DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT
108014. DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK
108015. DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT
108016. DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK
108017. DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT
108018. DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK
108019. DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT
108020. DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK
108021. DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT
108022. DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK
108023. DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT
108024. DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK
108025. DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT
108026. DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK
108027. DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT
108028. DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK
108029. DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT
108030. DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK
108031. DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT
108032. DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK
108033. DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT
108034. DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK
108035. DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT
108036. DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK
108037. DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT
108038. DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK
108039. DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT
108040. DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK
108041. DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT
108042. DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK
108043. DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT
108044. DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK
108045. DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT
108046. DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK
108047. DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT
108048. DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK
108049. DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT
108050. DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK
108051. DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT
108052. DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK
108053. DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT
108054. DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK
108055. DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT
108056. DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK
108057. DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT
108058. DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK
108059. DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT
108060. DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK
108061. DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT
108062. DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK
108063. DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT
108064. DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK
108065. DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT
108066. DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK
108067. DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT
108068. DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK
108069. DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT
108070. DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK
108071. DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT
108072. DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK
108073. DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT
108074. DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK
108075. DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT
108076. DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK
108077. DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT
108078. DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK
108079. DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT
108080. DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK
108081. DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT
108082. DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK
108083. DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT
108084. DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK
108085. DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT
108086. DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK
108087. DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT
108088. DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK
108089. DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT
108090. DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK
108091. DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT
108092. DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK
108093. DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT
108094. DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK
108095. DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT
108096. DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK
108097. DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT
108098. DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK
108099. DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT
108100. DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK
108101. DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT
108102. DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK
108103. DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT
108104. DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK
108105. DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT
108106. DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK
108107. DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT
108108. DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK
108109. DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT
108110. DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK
108111. DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT
108112. DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK
108113. DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT
108114. DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK
108115. DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT
108116. DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK
108117. DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT
108118. DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK
108119. DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT
108120. DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK
108121. DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT
108122. DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK
108123. DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT
108124. DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK
108125. DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT
108126. DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK
108127. DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT
108128. DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK
108129. DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT
108130. DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK
108131. DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT
108132. DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK
108133. DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT
108134. DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK
108135. DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT
108136. DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK
108137. DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT
108138. DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK
108139. DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT
108140. DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK
108141. DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT
108142. DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK
108143. DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT
108144. DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK
108145. DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT
108146. DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK
108147. DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT
108148. DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK
108149. DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT
108150. DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK
108151. DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT
108152. DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK
108153. DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT
108154. DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK
108155. DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT
108156. DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK
108157. DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT
108158. DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK
108159. DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT
108160. DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK
108161. DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT
108162. DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK
108163. DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT
108164. DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK
108165. DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT
108166. DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK
108167. DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT
108168. DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK
108169. DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT
108170. DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK
108171. DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT
108172. DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK
108173. DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT
108174. DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK
108175. DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT
108176. DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK
108177. DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT
108178. DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK
108179. DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT
108180. DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK
108181. DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK
108182. DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT
108183. DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT
108184. DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK
108185. DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT
108186. DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK
108187. DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT
108188. DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK
108189. DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT
108190. DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK
108191. DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT
108192. DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK
108193. DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT
108194. DMCUSMC_MSG_PSREntry
108195. DMCUSMC_MSG_PSRExit
108196. DMCU_CAN_ACCESS_AUX
108197. DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE
108198. DMCU_COMMON_REG_LIST_DCE_BASE
108199. DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK
108200. DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT
108201. DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK
108202. DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT
108203. DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK
108204. DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT
108205. DMCU_CTRL__DMCU_ENABLE_MASK
108206. DMCU_CTRL__DMCU_ENABLE__SHIFT
108207. DMCU_CTRL__IGNORE_PWRMGT_MASK
108208. DMCU_CTRL__IGNORE_PWRMGT__SHIFT
108209. DMCU_CTRL__RESET_UC_MASK
108210. DMCU_CTRL__RESET_UC__SHIFT
108211. DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK
108212. DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT
108213. DMCU_DCE110_COMMON_REG_LIST
108214. DMCU_DCE80_REG_LIST
108215. DMCU_DCN10_REG_LIST
108216. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK
108217. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT
108218. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK
108219. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT
108220. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK
108221. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT
108222. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK
108223. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT
108224. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK
108225. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT
108226. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK
108227. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT
108228. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK
108229. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT
108230. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK
108231. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT
108232. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK
108233. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT
108234. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK
108235. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT
108236. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK
108237. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT
108238. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK
108239. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT
108240. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK
108241. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT
108242. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK
108243. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT
108244. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108245. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108246. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108247. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108248. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK
108249. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT
108250. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK
108251. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT
108252. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK
108253. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT
108254. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK
108255. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT
108256. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108257. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108258. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108259. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108260. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108261. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108262. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108263. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108264. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK
108265. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT
108266. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK
108267. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT
108268. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK
108269. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT
108270. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK
108271. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT
108272. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK
108273. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT
108274. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK
108275. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT
108276. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108277. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108278. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108279. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108280. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108281. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108282. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108283. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108284. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108285. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108286. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108287. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108288. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK
108289. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT
108290. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK
108291. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT
108292. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK
108293. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT
108294. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK
108295. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT
108296. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK
108297. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT
108298. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK
108299. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT
108300. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK
108301. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT
108302. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK
108303. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT
108304. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK
108305. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT
108306. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK
108307. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT
108308. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK
108309. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT
108310. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK
108311. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT
108312. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK
108313. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT
108314. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK
108315. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT
108316. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK
108317. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT
108318. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK
108319. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT
108320. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK
108321. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT
108322. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK
108323. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT
108324. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK
108325. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT
108326. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK
108327. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT
108328. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK
108329. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT
108330. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK
108331. DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT
108332. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK
108333. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT
108334. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK
108335. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT
108336. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK
108337. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT
108338. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK
108339. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT
108340. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK
108341. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT
108342. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK
108343. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT
108344. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK
108345. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT
108346. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108347. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108348. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK
108349. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT
108350. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK
108351. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT
108352. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108353. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108354. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108355. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108356. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK
108357. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT
108358. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK
108359. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT
108360. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK
108361. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT
108362. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108363. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108364. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108365. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108366. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108367. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108368. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK
108369. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT
108370. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK
108371. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT
108372. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK
108373. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT
108374. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK
108375. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT
108376. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK
108377. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT
108378. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK
108379. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT
108380. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK
108381. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT
108382. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK
108383. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT
108384. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK
108385. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT
108386. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK
108387. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT
108388. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK
108389. DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT
108390. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK
108391. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT
108392. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK
108393. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT
108394. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK
108395. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT
108396. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK
108397. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT
108398. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK
108399. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT
108400. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK
108401. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT
108402. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK
108403. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT
108404. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108405. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108406. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK
108407. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT
108408. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK
108409. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT
108410. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108411. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108412. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108413. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108414. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK
108415. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT
108416. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK
108417. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT
108418. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK
108419. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT
108420. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108421. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108422. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108423. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108424. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108425. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108426. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK
108427. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT
108428. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK
108429. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT
108430. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK
108431. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT
108432. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK
108433. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT
108434. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK
108435. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT
108436. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK
108437. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT
108438. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK
108439. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT
108440. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK
108441. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT
108442. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK
108443. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT
108444. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK
108445. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT
108446. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK
108447. DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT
108448. DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK
108449. DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT
108450. DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK
108451. DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT
108452. DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK
108453. DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT
108454. DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK
108455. DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT
108456. DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK
108457. DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT
108458. DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK
108459. DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT
108460. DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK
108461. DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT
108462. DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK
108463. DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT
108464. DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK
108465. DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT
108466. DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK
108467. DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT
108468. DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK
108469. DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT
108470. DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK
108471. DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT
108472. DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK
108473. DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT
108474. DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK
108475. DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT
108476. DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK
108477. DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT
108478. DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK
108479. DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT
108480. DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK
108481. DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT
108482. DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK
108483. DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT
108484. DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK
108485. DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT
108486. DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK
108487. DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT
108488. DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK
108489. DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT
108490. DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR_MASK
108491. DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108492. DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED_MASK
108493. DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108494. DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR_MASK
108495. DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108496. DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED_MASK
108497. DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108498. DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR_MASK
108499. DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108500. DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED_MASK
108501. DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108502. DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR_MASK
108503. DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108504. DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED_MASK
108505. DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108506. DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR_MASK
108507. DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108508. DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED_MASK
108509. DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108510. DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR_MASK
108511. DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108512. DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED_MASK
108513. DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108514. DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR_MASK
108515. DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR__SHIFT
108516. DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED_MASK
108517. DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED__SHIFT
108518. DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR_MASK
108519. DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR__SHIFT
108520. DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED_MASK
108521. DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED__SHIFT
108522. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK
108523. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT
108524. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK
108525. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT
108526. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK
108527. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT
108528. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK
108529. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT
108530. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR_MASK
108531. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT
108532. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED_MASK
108533. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT
108534. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR_MASK
108535. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR__SHIFT
108536. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED_MASK
108537. DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED__SHIFT
108538. DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK
108539. DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT
108540. DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK
108541. DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT
108542. DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK
108543. DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108544. DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK
108545. DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108546. DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK
108547. DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108548. DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK
108549. DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108550. DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK
108551. DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108552. DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK
108553. DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108554. DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK
108555. DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108556. DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK
108557. DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108558. DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK
108559. DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108560. DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK
108561. DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108562. DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK
108563. DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT
108564. DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK
108565. DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
108566. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK
108567. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT
108568. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK
108569. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT
108570. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK
108571. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT
108572. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK
108573. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT
108574. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK
108575. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT
108576. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK
108577. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT
108578. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK
108579. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT
108580. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK
108581. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT
108582. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK
108583. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT
108584. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK
108585. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT
108586. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK
108587. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT
108588. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK
108589. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT
108590. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK
108591. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT
108592. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK
108593. DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT
108594. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK
108595. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT
108596. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK
108597. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT
108598. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK
108599. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT
108600. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK
108601. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT
108602. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK
108603. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT
108604. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK
108605. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT
108606. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK
108607. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT
108608. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK
108609. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT
108610. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK
108611. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT
108612. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK
108613. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT
108614. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK
108615. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT
108616. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK
108617. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT
108618. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK
108619. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT
108620. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK
108621. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT
108622. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK
108623. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT
108624. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK
108625. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT
108626. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK
108627. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT
108628. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK
108629. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT
108630. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK
108631. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT
108632. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK
108633. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT
108634. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK
108635. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT
108636. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK
108637. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT
108638. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK
108639. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT
108640. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK
108641. DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT
108642. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK
108643. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT
108644. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK
108645. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT
108646. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK
108647. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT
108648. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK
108649. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT
108650. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK
108651. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT
108652. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK
108653. DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT
108654. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK
108655. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT
108656. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK
108657. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT
108658. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK
108659. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT
108660. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK
108661. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT
108662. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK
108663. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT
108664. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK
108665. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT
108666. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK
108667. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT
108668. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK
108669. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT
108670. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK
108671. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT
108672. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK
108673. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT
108674. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK
108675. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT
108676. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK
108677. DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT
108678. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK
108679. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT
108680. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK
108681. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT
108682. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK
108683. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT
108684. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK
108685. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT
108686. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK
108687. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT
108688. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK
108689. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT
108690. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK
108691. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT
108692. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK
108693. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT
108694. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK
108695. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT
108696. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK
108697. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT
108698. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK
108699. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT
108700. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK
108701. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT
108702. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK
108703. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT
108704. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK
108705. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT
108706. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK
108707. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT
108708. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK
108709. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT
108710. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK
108711. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT
108712. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK
108713. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT
108714. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK
108715. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT
108716. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK
108717. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT
108718. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK
108719. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT
108720. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK
108721. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT
108722. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK
108723. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT
108724. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK
108725. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT
108726. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK
108727. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT
108728. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK
108729. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT
108730. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK
108731. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT
108732. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK
108733. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT
108734. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK
108735. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT
108736. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK
108737. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT
108738. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK
108739. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT
108740. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK
108741. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT
108742. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK
108743. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT
108744. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK
108745. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT
108746. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK
108747. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT
108748. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK
108749. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT
108750. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK
108751. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT
108752. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK
108753. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT
108754. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK
108755. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT
108756. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK
108757. DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT
108758. DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK
108759. DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT
108760. DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK
108761. DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT
108762. DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK
108763. DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT
108764. DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK
108765. DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT
108766. DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK
108767. DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT
108768. DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK
108769. DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT
108770. DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR_MASK
108771. DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR__SHIFT
108772. DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED_MASK
108773. DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED__SHIFT
108774. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK
108775. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT
108776. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK
108777. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT
108778. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK
108779. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT
108780. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK
108781. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT
108782. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK
108783. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT
108784. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK
108785. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT
108786. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK
108787. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT
108788. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK
108789. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT
108790. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK
108791. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT
108792. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK
108793. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT
108794. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK
108795. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT
108796. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK
108797. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT
108798. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK
108799. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT
108800. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK
108801. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT
108802. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK
108803. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT
108804. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK
108805. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT
108806. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK
108807. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT
108808. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK
108809. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT
108810. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK
108811. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT
108812. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK
108813. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT
108814. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK
108815. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT
108816. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK
108817. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT
108818. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK
108819. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT
108820. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK
108821. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT
108822. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK
108823. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT
108824. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK
108825. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT
108826. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK
108827. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT
108828. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK
108829. DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT
108830. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK
108831. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT
108832. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK
108833. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT
108834. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK
108835. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT
108836. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK
108837. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT
108838. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK
108839. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT
108840. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK
108841. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT
108842. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK
108843. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT
108844. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK
108845. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT
108846. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK
108847. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT
108848. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK
108849. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT
108850. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK
108851. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT
108852. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK
108853. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT
108854. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK
108855. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT
108856. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK
108857. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT
108858. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK
108859. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT
108860. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK
108861. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT
108862. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK
108863. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT
108864. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK
108865. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT
108866. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK
108867. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT
108868. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK
108869. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT
108870. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK
108871. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT
108872. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK
108873. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT
108874. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK
108875. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT
108876. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK
108877. DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT
108878. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK
108879. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT
108880. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK
108881. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT
108882. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK
108883. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT
108884. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK
108885. DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT
108886. DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK
108887. DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT
108888. DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK
108889. DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT
108890. DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK
108891. DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT
108892. DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK
108893. DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT
108894. DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK
108895. DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT
108896. DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK
108897. DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT
108898. DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK
108899. DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT
108900. DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK
108901. DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT
108902. DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK
108903. DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT
108904. DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK
108905. DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT
108906. DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK
108907. DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT
108908. DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK
108909. DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT
108910. DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK
108911. DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT
108912. DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK
108913. DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT
108914. DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK
108915. DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT
108916. DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK
108917. DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT
108918. DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK
108919. DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT
108920. DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK
108921. DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT
108922. DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK
108923. DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT
108924. DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK
108925. DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT
108926. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK
108927. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT
108928. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK
108929. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT
108930. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK
108931. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT
108932. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK
108933. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT
108934. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK
108935. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT
108936. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK
108937. DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT
108938. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK
108939. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT
108940. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK
108941. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT
108942. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK
108943. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT
108944. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK
108945. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT
108946. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK
108947. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT
108948. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK
108949. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT
108950. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK
108951. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT
108952. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK
108953. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT
108954. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK
108955. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT
108956. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK
108957. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT
108958. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK
108959. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT
108960. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK
108961. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT
108962. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK_MASK
108963. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK__SHIFT
108964. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK_MASK
108965. DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK__SHIFT
108966. DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK
108967. DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT
108968. DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK
108969. DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT
108970. DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK
108971. DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT
108972. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108973. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
108974. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108975. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
108976. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108977. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
108978. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108979. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
108980. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108981. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
108982. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108983. DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
108984. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN_MASK
108985. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT
108986. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN_MASK
108987. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN__SHIFT
108988. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK
108989. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT
108990. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK
108991. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT
108992. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN_MASK
108993. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN__SHIFT
108994. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN_MASK
108995. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN__SHIFT
108996. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK
108997. DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT
108998. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
108999. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
109000. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
109001. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
109002. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
109003. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
109004. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
109005. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
109006. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
109007. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
109008. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK
109009. DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT
109010. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK
109011. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT
109012. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK
109013. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT
109014. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK
109015. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT
109016. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK
109017. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT
109018. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK
109019. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT
109020. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK
109021. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT
109022. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK
109023. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT
109024. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK
109025. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT
109026. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK
109027. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT
109028. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK
109029. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT
109030. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK
109031. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT
109032. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK
109033. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT
109034. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK
109035. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT
109036. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK
109037. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT
109038. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK
109039. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT
109040. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK
109041. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT
109042. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK
109043. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT
109044. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK
109045. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT
109046. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK
109047. DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT
109048. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK
109049. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT
109050. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK
109051. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT
109052. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK
109053. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT
109054. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK
109055. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT
109056. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK
109057. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT
109058. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK
109059. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT
109060. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK
109061. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT
109062. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK
109063. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT
109064. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK
109065. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT
109066. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK
109067. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT
109068. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK
109069. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT
109070. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK
109071. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT
109072. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK
109073. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT
109074. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK
109075. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT
109076. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK
109077. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT
109078. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK
109079. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT
109080. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK
109081. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT
109082. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK
109083. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT
109084. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK
109085. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT
109086. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK
109087. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT
109088. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK
109089. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT
109090. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK
109091. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT
109092. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK
109093. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT
109094. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK
109095. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT
109096. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK
109097. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT
109098. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK
109099. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT
109100. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK
109101. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT
109102. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK
109103. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT
109104. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK
109105. DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT
109106. DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK
109107. DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT
109108. DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK
109109. DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT
109110. DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK
109111. DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT
109112. DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN_MASK
109113. DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT
109114. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK
109115. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT
109116. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK
109117. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT
109118. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK
109119. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT
109120. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK
109121. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT
109122. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK
109123. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT
109124. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK
109125. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT
109126. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK
109127. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT
109128. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK
109129. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT
109130. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK
109131. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT
109132. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK
109133. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT
109134. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK
109135. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT
109136. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK
109137. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT
109138. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK
109139. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT
109140. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK
109141. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT
109142. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK
109143. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT
109144. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK
109145. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT
109146. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK
109147. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT
109148. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK
109149. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT
109150. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK
109151. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT
109152. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK
109153. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT
109154. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK
109155. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT
109156. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK
109157. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT
109158. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK
109159. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT
109160. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK
109161. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT
109162. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK
109163. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT
109164. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK
109165. DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT
109166. DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK
109167. DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT
109168. DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK
109169. DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT
109170. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK
109171. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT
109172. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK
109173. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT
109174. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK
109175. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT
109176. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK
109177. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT
109178. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK
109179. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT
109180. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK
109181. DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT
109182. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK
109183. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT
109184. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK
109185. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT
109186. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK
109187. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT
109188. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK
109189. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT
109190. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK
109191. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT
109192. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK
109193. DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT
109194. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109195. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109196. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109197. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109198. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109199. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109200. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109201. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109202. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109203. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109204. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109205. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109206. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK
109207. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT
109208. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL_MASK
109209. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT
109210. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109211. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109212. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109213. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109214. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109215. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109216. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109217. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109218. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK
109219. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT
109220. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109221. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109222. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109223. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109224. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109225. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109226. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109227. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109228. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109229. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109230. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109231. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109232. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK
109233. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT
109234. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK
109235. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT
109236. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK
109237. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT
109238. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK
109239. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT
109240. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK
109241. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT
109242. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK
109243. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT
109244. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK
109245. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT
109246. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109247. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109248. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109249. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109250. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109251. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109252. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109253. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109254. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109255. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109256. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109257. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109258. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109259. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109260. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109261. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109262. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109263. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109264. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109265. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109266. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109267. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109268. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109269. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109270. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109271. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109272. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK
109273. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT
109274. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK
109275. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT
109276. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK
109277. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT
109278. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK
109279. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT
109280. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK
109281. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT
109282. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK
109283. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT
109284. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK
109285. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT
109286. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK
109287. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT
109288. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109289. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109290. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109291. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109292. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109293. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109294. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109295. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109296. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109297. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109298. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109299. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109300. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109301. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109302. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109303. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109304. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109305. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109306. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109307. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109308. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109309. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109310. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109311. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109312. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109313. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109314. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109315. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109316. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109317. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109318. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109319. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109320. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109321. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109322. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109323. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109324. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109325. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109326. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109327. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109328. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK
109329. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT
109330. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK
109331. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT
109332. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK
109333. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT
109334. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK
109335. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT
109336. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109337. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109338. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109339. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109340. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109341. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109342. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109343. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109344. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109345. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109346. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109347. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109348. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109349. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109350. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109351. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109352. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109353. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109354. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109355. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109356. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109357. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109358. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109359. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109360. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109361. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109362. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109363. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109364. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109365. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109366. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109367. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109368. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109369. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109370. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109371. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109372. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109373. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109374. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109375. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109376. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109377. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109378. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109379. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109380. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109381. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109382. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109383. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109384. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK
109385. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT
109386. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK
109387. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT
109388. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK
109389. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT
109390. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK
109391. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT
109392. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK
109393. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT
109394. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK
109395. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT
109396. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK
109397. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT
109398. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK
109399. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT
109400. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK
109401. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT
109402. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK
109403. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT
109404. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK
109405. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT
109406. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK
109407. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT
109408. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK
109409. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT
109410. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK
109411. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT
109412. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK
109413. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT
109414. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK
109415. DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT
109416. DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK
109417. DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT
109418. DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK
109419. DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT
109420. DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK
109421. DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT
109422. DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK
109423. DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT
109424. DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK
109425. DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT
109426. DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK
109427. DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT
109428. DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK
109429. DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT
109430. DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK
109431. DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT
109432. DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK
109433. DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT
109434. DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK
109435. DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT
109436. DMCU_LOADED_UNINITIALIZED
109437. DMCU_MASK_SH_LIST_DCE110
109438. DMCU_MASK_SH_LIST_DCE80
109439. DMCU_MASK_SH_LIST_DCN10
109440. DMCU_MEM1P1024X32BQS__MEM_PG
109441. DMCU_MEM1P1024X32BQS__MEM_PG__1
109442. DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK
109443. DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT
109444. DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK
109445. DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT
109446. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK
109447. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109448. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK
109449. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109450. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK
109451. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109452. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK
109453. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109454. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK
109455. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109456. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK
109457. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109458. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK
109459. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109460. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK
109461. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109462. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK
109463. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109464. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK
109465. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109466. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK
109467. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109468. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK
109469. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109470. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK
109471. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109472. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK
109473. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109474. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK
109475. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109476. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK
109477. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109478. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK
109479. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT
109480. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK
109481. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109482. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109483. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109484. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109485. DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109486. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK
109487. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109488. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK
109489. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109490. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK
109491. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109492. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK
109493. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109494. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK
109495. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109496. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK
109497. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109498. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK
109499. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109500. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK
109501. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109502. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK
109503. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109504. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK
109505. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109506. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK
109507. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109508. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK
109509. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109510. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK
109511. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109512. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK
109513. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109514. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK
109515. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109516. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK
109517. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109518. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109519. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109520. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109521. DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109522. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK
109523. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109524. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK
109525. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109526. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK
109527. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109528. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK
109529. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109530. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK
109531. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109532. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK
109533. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109534. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK
109535. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109536. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK
109537. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109538. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK
109539. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109540. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK
109541. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109542. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK
109543. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109544. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK
109545. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109546. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK
109547. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109548. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK
109549. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109550. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK
109551. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109552. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK
109553. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109554. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109555. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109556. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109557. DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109558. DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK
109559. DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT
109560. DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK
109561. DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109562. DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK
109563. DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT
109564. DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK
109565. DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109566. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK
109567. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109568. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK
109569. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109570. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK
109571. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109572. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK
109573. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109574. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK
109575. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109576. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK
109577. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109578. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK
109579. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109580. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK
109581. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109582. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK
109583. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109584. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK
109585. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109586. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK
109587. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109588. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK
109589. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109590. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK
109591. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109592. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK
109593. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109594. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK
109595. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109596. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK
109597. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109598. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109599. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109600. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109601. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109602. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK
109603. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109604. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK
109605. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109606. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK
109607. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109608. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK
109609. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109610. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK
109611. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109612. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK
109613. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109614. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK
109615. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109616. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK
109617. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109618. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK
109619. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109620. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK
109621. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109622. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK
109623. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109624. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK
109625. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109626. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK
109627. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109628. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK
109629. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109630. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK
109631. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109632. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK
109633. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109634. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109635. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109636. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109637. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109638. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK
109639. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109640. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK
109641. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109642. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK
109643. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109644. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK
109645. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109646. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK
109647. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109648. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK
109649. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109650. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK
109651. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109652. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK
109653. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109654. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK
109655. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109656. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK
109657. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109658. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK
109659. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109660. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK
109661. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109662. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK
109663. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109664. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK
109665. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109666. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK
109667. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109668. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK
109669. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109670. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109671. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109672. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109673. DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109674. DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK
109675. DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT
109676. DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK
109677. DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109678. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK
109679. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT
109680. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK
109681. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109682. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK
109683. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT
109684. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK
109685. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109686. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK
109687. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT
109688. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK
109689. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109690. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK
109691. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT
109692. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK
109693. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109694. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK
109695. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT
109696. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK
109697. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109698. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK
109699. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT
109700. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK
109701. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109702. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK
109703. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT
109704. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK
109705. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109706. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK
109707. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT
109708. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK
109709. DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109710. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK
109711. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109712. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK
109713. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109714. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK
109715. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109716. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK
109717. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109718. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK
109719. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109720. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK
109721. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109722. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK
109723. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109724. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK
109725. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109726. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK
109727. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109728. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK
109729. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109730. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK
109731. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109732. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK
109733. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109734. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK
109735. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109736. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK
109737. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109738. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK
109739. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109740. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK
109741. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109742. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109743. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109744. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109745. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109746. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK
109747. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109748. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK
109749. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109750. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK
109751. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109752. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK
109753. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109754. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK
109755. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109756. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK
109757. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109758. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK
109759. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109760. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK
109761. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109762. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK
109763. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109764. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK
109765. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109766. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK
109767. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109768. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK
109769. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109770. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK
109771. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109772. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK
109773. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109774. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK
109775. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109776. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK
109777. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109778. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109779. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109780. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109781. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109782. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK
109783. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109784. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK
109785. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109786. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK
109787. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109788. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK
109789. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109790. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK
109791. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109792. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK
109793. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109794. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK
109795. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109796. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK
109797. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109798. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK
109799. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109800. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK
109801. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109802. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK
109803. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109804. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK
109805. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109806. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK
109807. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109808. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK
109809. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109810. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK
109811. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109812. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK
109813. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109814. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109815. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109816. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109817. DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109818. DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK
109819. DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT
109820. DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK
109821. DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109822. DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK
109823. DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT
109824. DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK
109825. DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109826. DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK
109827. DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT
109828. DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK
109829. DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109830. DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK
109831. DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT
109832. DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK
109833. DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109834. DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK
109835. DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT
109836. DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK
109837. DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109838. DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK
109839. DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT
109840. DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK
109841. DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109842. DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK
109843. DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT
109844. DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK
109845. DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109846. DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK
109847. DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT
109848. DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK
109849. DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109850. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR_MASK
109851. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR__SHIFT
109852. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED_MASK
109853. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED__SHIFT
109854. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR_MASK
109855. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR__SHIFT
109856. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED_MASK
109857. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED__SHIFT
109858. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR_MASK
109859. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR__SHIFT
109860. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED_MASK
109861. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED__SHIFT
109862. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR_MASK
109863. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR__SHIFT
109864. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED_MASK
109865. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED__SHIFT
109866. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR_MASK
109867. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR__SHIFT
109868. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED_MASK
109869. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED__SHIFT
109870. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR_MASK
109871. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR__SHIFT
109872. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED_MASK
109873. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED__SHIFT
109874. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR_MASK
109875. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR__SHIFT
109876. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED_MASK
109877. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED__SHIFT
109878. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR_MASK
109879. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR__SHIFT
109880. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED_MASK
109881. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED__SHIFT
109882. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK
109883. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT
109884. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK
109885. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT
109886. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR_MASK
109887. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR__SHIFT
109888. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED_MASK
109889. DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED__SHIFT
109890. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK
109891. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109892. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK
109893. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109894. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK
109895. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109896. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK
109897. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109898. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK
109899. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109900. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK
109901. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109902. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK
109903. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109904. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK
109905. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109906. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK
109907. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109908. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK
109909. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109910. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK
109911. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109912. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK
109913. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109914. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK
109915. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109916. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK
109917. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109918. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK
109919. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109920. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK
109921. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109922. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109923. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109924. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109925. DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109926. DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK
109927. DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT
109928. DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK
109929. DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109930. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR_MASK
109931. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109932. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED_MASK
109933. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109934. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK
109935. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109936. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK
109937. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109938. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR_MASK
109939. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109940. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED_MASK
109941. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109942. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR_MASK
109943. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109944. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED_MASK
109945. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109946. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR_MASK
109947. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109948. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED_MASK
109949. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109950. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR_MASK
109951. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR__SHIFT
109952. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED_MASK
109953. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
109954. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR_MASK
109955. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR__SHIFT
109956. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED_MASK
109957. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
109958. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR_MASK
109959. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR__SHIFT
109960. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED_MASK
109961. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
109962. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
109963. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
109964. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
109965. DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
109966. DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK
109967. DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT
109968. DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK
109969. DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109970. DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK
109971. DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT
109972. DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK
109973. DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109974. DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK
109975. DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT
109976. DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK
109977. DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT
109978. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK
109979. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT
109980. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK
109981. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
109982. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK
109983. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT
109984. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK
109985. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
109986. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK
109987. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT
109988. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK
109989. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
109990. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK
109991. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT
109992. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK
109993. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
109994. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK
109995. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT
109996. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK
109997. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
109998. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK
109999. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT
110000. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK
110001. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
110002. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK
110003. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT
110004. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK
110005. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
110006. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK
110007. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT
110008. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK
110009. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
110010. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
110011. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
110012. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
110013. DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
110014. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR_MASK
110015. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR__SHIFT
110016. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED_MASK
110017. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
110018. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR_MASK
110019. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR__SHIFT
110020. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED_MASK
110021. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
110022. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR_MASK
110023. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR__SHIFT
110024. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED_MASK
110025. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
110026. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR_MASK
110027. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR__SHIFT
110028. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED_MASK
110029. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
110030. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR_MASK
110031. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR__SHIFT
110032. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK
110033. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
110034. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR_MASK
110035. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR__SHIFT
110036. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED_MASK
110037. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
110038. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR_MASK
110039. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR__SHIFT
110040. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED_MASK
110041. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
110042. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR_MASK
110043. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR__SHIFT
110044. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED_MASK
110045. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
110046. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
110047. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
110048. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
110049. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
110050. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR_MASK
110051. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR__SHIFT
110052. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED_MASK
110053. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
110054. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR_MASK
110055. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR__SHIFT
110056. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED_MASK
110057. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
110058. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR_MASK
110059. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR__SHIFT
110060. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED_MASK
110061. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
110062. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR_MASK
110063. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR__SHIFT
110064. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED_MASK
110065. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
110066. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR_MASK
110067. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR__SHIFT
110068. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED_MASK
110069. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
110070. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR_MASK
110071. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR__SHIFT
110072. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED_MASK
110073. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
110074. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR_MASK
110075. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR__SHIFT
110076. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED_MASK
110077. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
110078. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR_MASK
110079. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR__SHIFT
110080. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED_MASK
110081. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
110082. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
110083. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
110084. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
110085. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
110086. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK
110087. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT
110088. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK
110089. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT
110090. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK
110091. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT
110092. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK
110093. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT
110094. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK
110095. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT
110096. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK
110097. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT
110098. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK
110099. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT
110100. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK
110101. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT
110102. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK
110103. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT
110104. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK
110105. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT
110106. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK
110107. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT
110108. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK
110109. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT
110110. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK
110111. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT
110112. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK
110113. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT
110114. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK
110115. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT
110116. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK
110117. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT
110118. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK
110119. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT
110120. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK
110121. DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT
110122. DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK
110123. DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT
110124. DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK
110125. DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110126. DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK
110127. DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT
110128. DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK
110129. DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110130. DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK
110131. DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT
110132. DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK
110133. DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110134. DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK
110135. DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT
110136. DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK
110137. DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110138. DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK
110139. DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT
110140. DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK
110141. DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110142. DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK
110143. DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT
110144. DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK
110145. DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110146. DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK
110147. DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT
110148. DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK
110149. DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110150. DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK
110151. DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT
110152. DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK
110153. DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110154. DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK
110155. DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT
110156. DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK
110157. DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110158. DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK
110159. DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT
110160. DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK
110161. DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT
110162. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK
110163. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT
110164. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK
110165. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT
110166. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK
110167. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT
110168. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK
110169. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT
110170. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK
110171. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT
110172. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK
110173. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT
110174. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK
110175. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT
110176. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK
110177. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT
110178. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK
110179. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110180. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK
110181. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT
110182. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK
110183. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT
110184. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK
110185. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT
110186. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK
110187. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT
110188. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK
110189. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT
110190. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK
110191. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT
110192. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK
110193. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT
110194. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK
110195. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT
110196. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK
110197. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110198. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK
110199. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT
110200. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK
110201. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT
110202. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK
110203. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT
110204. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK
110205. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT
110206. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK
110207. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT
110208. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK
110209. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT
110210. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK
110211. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT
110212. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK
110213. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT
110214. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK
110215. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110216. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK
110217. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT
110218. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK
110219. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT
110220. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK
110221. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT
110222. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK
110223. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT
110224. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK
110225. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT
110226. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK
110227. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT
110228. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK
110229. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT
110230. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK
110231. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT
110232. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK
110233. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110234. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK
110235. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT
110236. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK
110237. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT
110238. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK
110239. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT
110240. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK
110241. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT
110242. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK
110243. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT
110244. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK
110245. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT
110246. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK
110247. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT
110248. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK
110249. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT
110250. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK
110251. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110252. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK
110253. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT
110254. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK
110255. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT
110256. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK
110257. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT
110258. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK
110259. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT
110260. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK
110261. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT
110262. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK
110263. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT
110264. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK
110265. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT
110266. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK
110267. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT
110268. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK
110269. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110270. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK
110271. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT
110272. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK
110273. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT
110274. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK
110275. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT
110276. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK
110277. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT
110278. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK
110279. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT
110280. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK
110281. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT
110282. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK
110283. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT
110284. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK
110285. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT
110286. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK
110287. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110288. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK
110289. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT
110290. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK
110291. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT
110292. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK
110293. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT
110294. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK
110295. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT
110296. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK
110297. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT
110298. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK
110299. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT
110300. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK
110301. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT
110302. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK
110303. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT
110304. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK
110305. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110306. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK
110307. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT
110308. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK
110309. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT
110310. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK
110311. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT
110312. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK
110313. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT
110314. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK
110315. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT
110316. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK
110317. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT
110318. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK
110319. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT
110320. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK
110321. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT
110322. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK
110323. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110324. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK_MASK
110325. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK__SHIFT
110326. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK_MASK
110327. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK__SHIFT
110328. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK_MASK
110329. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK__SHIFT
110330. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK_MASK
110331. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK__SHIFT
110332. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK_MASK
110333. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK__SHIFT
110334. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK_MASK
110335. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK__SHIFT
110336. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK_MASK
110337. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK__SHIFT
110338. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK_MASK
110339. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK__SHIFT
110340. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK_MASK
110341. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110342. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK_MASK
110343. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK__SHIFT
110344. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK
110345. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK__SHIFT
110346. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK_MASK
110347. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT
110348. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK_MASK
110349. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK__SHIFT
110350. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK_MASK
110351. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK__SHIFT
110352. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK_MASK
110353. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK__SHIFT
110354. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK_MASK
110355. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK__SHIFT
110356. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK_MASK
110357. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK__SHIFT
110358. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK_MASK
110359. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110360. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK_MASK
110361. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK__SHIFT
110362. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK_MASK
110363. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK__SHIFT
110364. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK_MASK
110365. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK__SHIFT
110366. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK_MASK
110367. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK__SHIFT
110368. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK_MASK
110369. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK__SHIFT
110370. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK_MASK
110371. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK__SHIFT
110372. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK_MASK
110373. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK__SHIFT
110374. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK_MASK
110375. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK__SHIFT
110376. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK_MASK
110377. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110378. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK_MASK
110379. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK__SHIFT
110380. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK_MASK
110381. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK__SHIFT
110382. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK_MASK
110383. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK__SHIFT
110384. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK_MASK
110385. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK__SHIFT
110386. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK_MASK
110387. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK__SHIFT
110388. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK_MASK
110389. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK__SHIFT
110390. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK_MASK
110391. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK__SHIFT
110392. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK_MASK
110393. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK__SHIFT
110394. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK_MASK
110395. DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK__SHIFT
110396. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110397. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110398. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110399. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110400. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110401. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110402. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110403. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110404. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110405. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110406. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110407. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110408. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110409. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110410. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110411. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110412. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110413. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110414. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110415. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110416. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110417. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110418. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110419. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110420. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110421. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110422. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110423. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110424. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110425. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110426. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110427. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110428. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110429. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110430. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110431. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110432. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110433. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110434. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110435. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110436. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110437. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110438. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110439. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110440. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110441. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110442. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110443. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110444. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110445. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110446. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110447. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110448. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110449. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110450. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110451. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110452. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110453. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110454. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110455. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110456. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110457. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110458. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110459. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110460. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110461. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110462. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110463. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110464. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110465. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110466. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110467. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110468. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110469. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110470. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110471. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110472. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110473. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110474. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110475. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110476. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110477. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110478. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110479. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110480. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110481. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110482. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110483. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110484. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110485. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110486. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110487. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110488. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110489. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110490. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110491. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110492. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110493. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110494. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110495. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110496. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110497. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110498. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110499. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110500. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110501. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110502. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110503. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110504. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110505. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110506. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110507. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110508. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110509. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110510. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110511. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110512. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110513. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110514. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110515. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110516. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110517. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110518. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110519. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110520. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110521. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110522. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110523. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110524. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110525. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110526. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110527. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110528. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110529. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110530. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110531. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110532. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110533. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110534. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110535. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110536. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110537. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110538. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110539. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110540. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110541. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110542. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110543. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110544. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110545. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110546. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110547. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110548. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110549. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110550. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110551. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110552. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110553. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110554. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110555. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110556. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110557. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110558. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110559. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110560. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110561. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110562. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110563. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110564. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110565. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110566. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110567. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110568. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110569. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110570. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110571. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110572. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110573. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110574. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110575. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110576. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110577. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110578. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110579. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110580. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110581. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110582. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110583. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110584. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110585. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110586. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110587. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110588. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110589. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110590. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110591. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110592. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110593. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110594. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110595. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110596. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110597. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110598. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN_MASK
110599. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN__SHIFT
110600. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN_MASK
110601. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN__SHIFT
110602. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN_MASK
110603. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN__SHIFT
110604. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN_MASK
110605. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN__SHIFT
110606. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN_MASK
110607. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN__SHIFT
110608. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN_MASK
110609. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN__SHIFT
110610. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN_MASK
110611. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN__SHIFT
110612. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN_MASK
110613. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN__SHIFT
110614. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK
110615. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT
110616. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN_MASK
110617. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110618. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110619. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110620. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110621. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110622. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110623. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110624. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110625. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110626. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110627. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110628. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110629. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110630. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110631. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110632. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110633. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110634. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110635. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110636. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110637. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110638. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110639. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110640. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110641. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110642. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110643. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110644. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110645. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110646. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110647. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110648. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110649. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110650. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110651. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110652. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110653. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110654. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110655. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110656. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110657. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110658. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110659. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110660. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110661. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110662. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110663. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110664. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110665. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110666. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110667. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110668. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110669. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110670. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110671. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110672. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110673. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110674. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110675. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110676. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110677. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110678. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110679. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110680. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110681. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110682. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110683. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110684. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110685. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110686. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110687. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110688. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110689. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110690. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110691. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110692. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110693. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110694. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110695. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110696. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110697. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110698. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110699. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110700. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110701. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110702. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110703. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110704. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110705. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110706. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110707. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110708. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110709. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110710. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110711. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110712. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110713. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110714. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110715. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110716. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK
110717. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT
110718. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK
110719. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT
110720. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK
110721. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT
110722. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK
110723. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT
110724. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK
110725. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT
110726. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK
110727. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT
110728. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK
110729. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT
110730. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK
110731. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT
110732. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK
110733. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT
110734. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110735. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110736. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110737. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110738. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110739. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110740. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110741. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110742. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110743. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110744. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110745. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110746. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110747. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110748. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110749. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110750. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110751. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110752. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK
110753. DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT
110754. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110755. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110756. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110757. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110758. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110759. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110760. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110761. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110762. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110763. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110764. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110765. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110766. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110767. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110768. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110769. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110770. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110771. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110772. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110773. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110774. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110775. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110776. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110777. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110778. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110779. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110780. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110781. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110782. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110783. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110784. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110785. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110786. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110787. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110788. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110789. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110790. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110791. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110792. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110793. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110794. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110795. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110796. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110797. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110798. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110799. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110800. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110801. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110802. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110803. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110804. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110805. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110806. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110807. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110808. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110809. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110810. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110811. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110812. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110813. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110814. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110815. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110816. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110817. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110818. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110819. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110820. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110821. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110822. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110823. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110824. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110825. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110826. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110827. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110828. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110829. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110830. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110831. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110832. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110833. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110834. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110835. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110836. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110837. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110838. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110839. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110840. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110841. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110842. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110843. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110844. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110845. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110846. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110847. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110848. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110849. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110850. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110851. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110852. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110853. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110854. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110855. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110856. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110857. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110858. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110859. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110860. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110861. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110862. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110863. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110864. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110865. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110866. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110867. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110868. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110869. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110870. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110871. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110872. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110873. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110874. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110875. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110876. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110877. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110878. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110879. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110880. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110881. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110882. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110883. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110884. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110885. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110886. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110887. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110888. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110889. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110890. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110891. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110892. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110893. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110894. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110895. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110896. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110897. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110898. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110899. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110900. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110901. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110902. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110903. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110904. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110905. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110906. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110907. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110908. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110909. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110910. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110911. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110912. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110913. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110914. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110915. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110916. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110917. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110918. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110919. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110920. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110921. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110922. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110923. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110924. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110925. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110926. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110927. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110928. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110929. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110930. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110931. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110932. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110933. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110934. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110935. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110936. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110937. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110938. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110939. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110940. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110941. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110942. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110943. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110944. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110945. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110946. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110947. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110948. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110949. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110950. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110951. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110952. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110953. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110954. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110955. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110956. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110957. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110958. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110959. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110960. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110961. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110962. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110963. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110964. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110965. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110966. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110967. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110968. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110969. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110970. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110971. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110972. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110973. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110974. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110975. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110976. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110977. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110978. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110979. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
110980. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
110981. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
110982. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
110983. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
110984. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
110985. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
110986. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
110987. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
110988. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
110989. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
110990. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
110991. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
110992. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
110993. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
110994. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
110995. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
110996. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
110997. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
110998. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
110999. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
111000. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
111001. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
111002. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
111003. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
111004. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
111005. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
111006. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
111007. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
111008. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
111009. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
111010. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
111011. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
111012. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
111013. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
111014. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111015. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111016. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111017. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111018. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111019. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111020. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
111021. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
111022. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
111023. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
111024. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
111025. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
111026. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
111027. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
111028. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
111029. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
111030. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
111031. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
111032. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
111033. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
111034. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
111035. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
111036. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
111037. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
111038. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
111039. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
111040. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
111041. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
111042. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
111043. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
111044. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
111045. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
111046. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
111047. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
111048. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
111049. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
111050. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
111051. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
111052. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
111053. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
111054. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
111055. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
111056. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
111057. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
111058. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
111059. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
111060. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
111061. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
111062. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
111063. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
111064. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
111065. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
111066. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
111067. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
111068. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
111069. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
111070. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
111071. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
111072. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
111073. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
111074. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK
111075. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT
111076. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK
111077. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT
111078. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK
111079. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT
111080. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK
111081. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT
111082. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK
111083. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT
111084. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK
111085. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT
111086. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK
111087. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT
111088. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK
111089. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT
111090. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK
111091. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT
111092. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111093. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111094. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111095. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111096. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111097. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111098. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111099. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111100. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111101. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111102. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111103. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111104. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111105. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111106. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111107. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111108. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111109. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111110. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK
111111. DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT
111112. DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK
111113. DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT
111114. DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK
111115. DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT
111116. DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK
111117. DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT
111118. DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK
111119. DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT
111120. DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK
111121. DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT
111122. DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK
111123. DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT
111124. DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK
111125. DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT
111126. DMCU_REG_FIELD_LIST
111127. DMCU_RUNNING
111128. DMCU_SF
111129. DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK
111130. DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT
111131. DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK
111132. DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT
111133. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK
111134. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT
111135. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK
111136. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT
111137. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK
111138. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT
111139. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN_MASK
111140. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT
111141. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK
111142. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT
111143. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK
111144. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT
111145. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK
111146. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT
111147. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK
111148. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT
111149. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK
111150. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT
111151. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK
111152. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT
111153. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK
111154. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT
111155. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK
111156. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT
111157. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK
111158. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT
111159. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN_MASK
111160. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT
111161. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK
111162. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT
111163. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK
111164. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT
111165. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK
111166. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT
111167. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK
111168. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT
111169. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN_MASK
111170. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT
111171. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK
111172. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT
111173. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK
111174. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT
111175. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK
111176. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT
111177. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK
111178. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT
111179. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN_MASK
111180. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT
111181. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK
111182. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT
111183. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK
111184. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT
111185. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK
111186. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT
111187. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK
111188. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT
111189. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN_MASK
111190. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT
111191. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK
111192. DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT
111193. DMCU_STATUS__UC_IN_RESET_MASK
111194. DMCU_STATUS__UC_IN_RESET__SHIFT
111195. DMCU_STATUS__UC_IN_STOP_MODE_MASK
111196. DMCU_STATUS__UC_IN_STOP_MODE__SHIFT
111197. DMCU_STATUS__UC_IN_WAIT_MODE_MASK
111198. DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT
111199. DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK
111200. DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT
111201. DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK
111202. DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT
111203. DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK
111204. DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT
111205. DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK
111206. DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT
111207. DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK
111208. DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT
111209. DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK
111210. DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT
111211. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK
111212. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT
111213. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK
111214. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT
111215. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK
111216. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT
111217. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK
111218. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT
111219. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK
111220. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT
111221. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK
111222. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT
111223. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK
111224. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT
111225. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK
111226. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT
111227. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK
111228. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT
111229. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK
111230. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT
111231. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK
111232. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT
111233. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK
111234. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT
111235. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK
111236. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT
111237. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK
111238. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT
111239. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK
111240. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT
111241. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK
111242. DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT
111243. DMCU_UNLOADED
111244. DMC_CAV_LUT_ADDR
111245. DMC_CAV_LUT_DATAH
111246. DMC_CAV_LUT_DATAL
111247. DMC_COUNTER_CTL
111248. DMC_COUNTER_DATA
111249. DMC_EVENT_CFG
111250. DMC_EVENT_COUNT_CYCLES
111251. DMC_EVENT_DATA_TRANSFERS
111252. DMC_EVENT_MAX
111253. DMC_EVENT_READ_TXNS
111254. DMC_EVENT_WRITE_TXNS
111255. DMC_V1_MAX_MMIO_COUNT
111256. DMC_V3_MAX_MMIO_COUNT
111257. DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE
111258. DMD0_SPECTRUM_MIN_GAIN_STATUS
111259. DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE
111260. DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR
111261. DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR
111262. DMDATA_CLEAR_UNDERFLOW_STATUS
111263. DMDATA_DONE
111264. DMDATA_DONT_CLEAR
111265. DMDATA_HARDWARE_UPDATE_MODE
111266. DMDATA_HW_MODE
111267. DMDATA_MODE
111268. DMDATA_NOT_SENT_TO_DIG
111269. DMDATA_NOT_UNDERFLOW
111270. DMDATA_NOT_UPDATED
111271. DMDATA_QOS_LEVEL_FROM_SOFTWARE
111272. DMDATA_QOS_LEVEL_FROM_TTU
111273. DMDATA_QOS_MODE
111274. DMDATA_REPEAT
111275. DMDATA_SENT_TO_DIG
111276. DMDATA_SOFTWARE_UPDATE_MODE
111277. DMDATA_SW_MODE
111278. DMDATA_UNDERFLOW
111279. DMDATA_UNDERFLOWED
111280. DMDATA_UNDERFLOW_CLEAR
111281. DMDATA_UPDATED
111282. DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES
111283. DMDATA_USE_FOR_CURRENT_FRAME_ONLY
111284. DMDATA_WAS_UPDATED
111285. DMDCFG2
111286. DMDCFG3
111287. DMDCFG4
111288. DMDCFGMD
111289. DMDEBUG
111290. DMDEBUG_LIMIT
111291. DMDFLYW
111292. DMDISTATE
111293. DMDMODCOD
111294. DMDN_SZ
111295. DMDPLHSTAT
111296. DMDREG
111297. DMDRESADR
111298. DMDRESCFG
111299. DMDSTATE
111300. DMDT0M
111301. DMD_CTL_FREQ_OFFSET_ADDR
111302. DMD_CYCLE_SLIP_COUNT_ADDR
111303. DMD_DISPLAY_IQ_ADDR
111304. DMD_DVBS2_CRC_ERRORS_ADDR
111305. DMD_DVBS2_PER_COUNT_ADDR
111306. DMD_DVBS2_PER_WINDOW_ADDR
111307. DMD_DVBS2_PILOT_ON_OFF_ADDR
111308. DMD_DVBS_BER_COUNT_ADDR
111309. DMD_DVBS_BER_WINDOW_ADDR
111310. DMD_DVBS_CORR_RS_ERRORS_ADDR
111311. DMD_DVBS_UNCORR_RS_ERRORS_ADDR
111312. DMD_FEC_CODE_RATE_ADDR
111313. DMD_FREQ_OFFSET_ADDR
111314. DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR
111315. DMD_FTL_FREQ_OFFSET_ADDR
111316. DMD_MODULATION_SCHEME_ADDR
111317. DMD_SNR_ADDR
111318. DMD_SPECTRUM_INVERSION_ADDR
111319. DMD_SPECTRUM_ROLL_OFF_ADDR
111320. DMD_STANDARD_ADDR
111321. DMD_STR_FREQ_OFFSET_ADDR
111322. DMD_STR_NBC_SYNC_LOCK_ADDR
111323. DMD_SYMBOL_RATE_ADDR
111324. DMD_TEI_BASEADDR
111325. DMD_TUNER_ID_ADDR
111326. DME1737_COMPANY_SMSC
111327. DME1737_EXTENT
111328. DME1737_ID_1
111329. DME1737_ID_2
111330. DME1737_REG_ALARM1
111331. DME1737_REG_ALARM2
111332. DME1737_REG_ALARM3
111333. DME1737_REG_COMPANY
111334. DME1737_REG_CONFIG
111335. DME1737_REG_CONFIG2
111336. DME1737_REG_DEVICE
111337. DME1737_REG_FAN
111338. DME1737_REG_FAN_MAX
111339. DME1737_REG_FAN_MIN
111340. DME1737_REG_FAN_OPT
111341. DME1737_REG_IN
111342. DME1737_REG_IN_MAX
111343. DME1737_REG_IN_MIN
111344. DME1737_REG_IN_TEMP_LSB
111345. DME1737_REG_PWM
111346. DME1737_REG_PWM_CONFIG
111347. DME1737_REG_PWM_FREQ
111348. DME1737_REG_PWM_MIN
111349. DME1737_REG_PWM_RR
111350. DME1737_REG_TACH_PWM
111351. DME1737_REG_TEMP
111352. DME1737_REG_TEMP_MAX
111353. DME1737_REG_TEMP_MIN
111354. DME1737_REG_TEMP_OFFSET
111355. DME1737_REG_VERSTEP
111356. DME1737_REG_VID
111357. DME1737_REG_ZONE_ABS
111358. DME1737_REG_ZONE_HYST
111359. DME1737_REG_ZONE_LOW
111360. DME1737_VERSTEP
111361. DME1737_VERSTEP_MASK
111362. DMEMC_PHYS
111363. DMEMC_SIZE
111364. DMEMC_VIRT
111365. DMEMIT
111366. DMEMIT_DELAY_CLASS
111367. DMEMIT_SYNC
111368. DMEM_CHUNK_NPAGES
111369. DMEM_CHUNK_SIZE
111370. DMEM_CODE_DONE
111371. DMEM_MAP_ERROR
111372. DMEM_SIZE
111373. DMEN
111374. DMER
111375. DMERR
111376. DMERR_LIMIT
111377. DMER_DME
111378. DMESG
111379. DMESGE
111380. DMESGW
111381. DMEX
111382. DME_DDBL1_MANUFACTURERID
111383. DME_DDBL1_PRODUCTID
111384. DME_LINKSTARTUP_RETRIES
111385. DME_LOCAL
111386. DME_PEER
111387. DME_SELECTOR_INDEX_NULL
111388. DME_STATUS_BRESP_ERR
111389. DME_STATUS_ERROR_MASK
111390. DME_STATUS_FIFO_OVERFLOW
111391. DME_STATUS_FIFO_UNDERFLOW
111392. DME_STATUS_MEM_COR_ERR
111393. DME_STATUS_MEM_UCOR_ERR
111394. DME_STATUS_RRESP_ERR
111395. DME_TOSHIBA_GMP_INIT_STATUS
111396. DME_TOSHIBA_GMP_PID
111397. DME_TOSHIBA_GMP_SN0
111398. DME_TOSHIBA_GMP_SN1
111399. DME_TOSHIBA_GMP_VID
111400. DME_T_TST_SRC_INCREMENT
111401. DME_VS_CORE_CLK_CTRL
111402. DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT
111403. DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK
111404. DMFC_DP_CHAN
111405. DMFC_DP_CHAN_5B_23
111406. DMFC_DP_CHAN_5F_27
111407. DMFC_DP_CHAN_6B_24
111408. DMFC_DP_CHAN_6F_29
111409. DMFC_DP_CHAN_ALT
111410. DMFC_DP_CHAN_DEF
111411. DMFC_DP_CHAN_DEF_ALT
111412. DMFC_GENERAL1
111413. DMFC_GENERAL1_ALT
111414. DMFC_GENERAL2
111415. DMFC_IC_CTRL
111416. DMFC_NUM_CHANNELS
111417. DMFC_RD_CHAN
111418. DMFC_STAT
111419. DMFC_WR_CHAN
111420. DMFC_WR_CHAN_1C_42
111421. DMFC_WR_CHAN_1_28
111422. DMFC_WR_CHAN_2C_43
111423. DMFC_WR_CHAN_2_41
111424. DMFC_WR_CHAN_ALT
111425. DMFC_WR_CHAN_DEF
111426. DMFC_WR_CHAN_DEF_ALT
111427. DMFE_100MFD
111428. DMFE_100MHF
111429. DMFE_10MFD
111430. DMFE_10MHF
111431. DMFE_1M_HPNA
111432. DMFE_AUTO
111433. DMFE_DBUG
111434. DMFE_MAX_MULTICAST
111435. DMFE_TIMER_WUT
111436. DMFE_TXTH_128
111437. DMFE_TXTH_1K
111438. DMFE_TXTH_256
111439. DMFE_TXTH_512
111440. DMFE_TXTH_72
111441. DMFE_TXTH_96
111442. DMFE_TX_KICK
111443. DMFE_TX_TIMEOUT
111444. DMFE_WOL_LINKCHANGE
111445. DMFE_WOL_MAGICPACKET
111446. DMFE_WOL_SAMPLEPACKET
111447. DMF_BLOCK_IO_FOR_SUSPEND
111448. DMF_DEFERRED_REMOVE
111449. DMF_DELETING
111450. DMF_FREEING
111451. DMF_FROZEN
111452. DMF_NOFLUSH_SUSPENDING
111453. DMF_SUSPENDED
111454. DMF_SUSPENDED_INTERNALLY
111455. DMGL_ANSI
111456. DMGL_NO_OPTS
111457. DMGL_PARAMS
111458. DMIC_48K_SEL_CTL_MASK
111459. DMIC_48K_SEL_CTL_MASK_SFT
111460. DMIC_48K_SEL_CTL_SFT
111461. DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE
111462. DMIC_B1_CTL_DMIC0_CLK_EN_MASK
111463. DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16
111464. DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2
111465. DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3
111466. DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4
111467. DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6
111468. DMIC_B1_CTL_DMIC0_CLK_SEL_MASK
111469. DMIC_CH
111470. DMIC_CLK
111471. DMIC_DAI_COUNT
111472. DMIC_LOW_POWER_MODE_CTL_MASK
111473. DMIC_LOW_POWER_MODE_CTL_MASK_SFT
111474. DMIC_LOW_POWER_MODE_CTL_SFT
111475. DMIC_ON_PERIODIC_INVERSE_MASK
111476. DMIC_ON_PERIODIC_INVERSE_MASK_SFT
111477. DMIC_ON_PERIODIC_INVERSE_SFT
111478. DMIC_ON_PERIODIC_MODE_MASK
111479. DMIC_ON_PERIODIC_MODE_MASK_SFT
111480. DMIC_ON_PERIODIC_MODE_SFT
111481. DMIC_ON_PERIODIC_OFF_CYCLE_MASK
111482. DMIC_ON_PERIODIC_OFF_CYCLE_MASK_SFT
111483. DMIC_ON_PERIODIC_OFF_CYCLE_SFT
111484. DMIC_ON_PERIODIC_ON_CYCLE_MASK
111485. DMIC_ON_PERIODIC_ON_CYCLE_MASK_SFT
111486. DMIC_ON_PERIODIC_ON_CYCLE_SFT
111487. DMIEC
111488. DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
111489. DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
111490. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
111491. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
111492. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
111493. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
111494. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
111495. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
111496. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
111497. DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
111498. DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
111499. DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
111500. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
111501. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
111502. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
111503. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
111504. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
111505. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
111506. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
111507. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
111508. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
111509. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
111510. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
111511. DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
111512. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
111513. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
111514. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
111515. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
111516. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
111517. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
111518. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
111519. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
111520. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
111521. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
111522. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
111523. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
111524. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
111525. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
111526. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
111527. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
111528. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
111529. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
111530. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
111531. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
111532. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
111533. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
111534. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
111535. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
111536. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
111537. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
111538. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
111539. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
111540. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
111541. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
111542. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
111543. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
111544. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
111545. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
111546. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
111547. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
111548. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
111549. DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
111550. DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
111551. DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
111552. DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
111553. DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
111554. DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
111555. DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
111556. DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
111557. DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
111558. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
111559. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
111560. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
111561. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
111562. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
111563. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
111564. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
111565. DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
111566. DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
111567. DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
111568. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
111569. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
111570. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
111571. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
111572. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
111573. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
111574. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
111575. DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
111576. DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
111577. DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
111578. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
111579. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
111580. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
111581. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
111582. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
111583. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
111584. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
111585. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
111586. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
111587. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
111588. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
111589. DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
111590. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
111591. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
111592. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
111593. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
111594. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
111595. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
111596. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
111597. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
111598. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
111599. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
111600. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
111601. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
111602. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
111603. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
111604. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
111605. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
111606. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
111607. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
111608. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
111609. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
111610. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
111611. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
111612. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
111613. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
111614. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
111615. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
111616. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
111617. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
111618. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
111619. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
111620. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
111621. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
111622. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
111623. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
111624. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
111625. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
111626. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
111627. DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
111628. DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
111629. DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
111630. DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
111631. DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
111632. DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
111633. DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
111634. DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
111635. DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
111636. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
111637. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
111638. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
111639. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
111640. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
111641. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
111642. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
111643. DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
111644. DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
111645. DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
111646. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
111647. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
111648. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
111649. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
111650. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
111651. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
111652. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
111653. DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
111654. DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
111655. DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
111656. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
111657. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
111658. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
111659. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
111660. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
111661. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
111662. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
111663. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
111664. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
111665. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
111666. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
111667. DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
111668. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
111669. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
111670. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
111671. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
111672. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
111673. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
111674. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
111675. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
111676. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
111677. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
111678. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
111679. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
111680. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
111681. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
111682. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
111683. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
111684. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
111685. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
111686. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
111687. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
111688. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
111689. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
111690. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
111691. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
111692. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
111693. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
111694. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
111695. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
111696. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
111697. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
111698. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
111699. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
111700. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
111701. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
111702. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
111703. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
111704. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
111705. DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
111706. DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
111707. DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
111708. DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
111709. DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
111710. DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
111711. DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
111712. DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
111713. DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
111714. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
111715. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
111716. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
111717. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
111718. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
111719. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
111720. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
111721. DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
111722. DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
111723. DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
111724. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
111725. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
111726. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
111727. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
111728. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
111729. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
111730. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
111731. DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
111732. DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
111733. DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
111734. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
111735. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
111736. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
111737. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
111738. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
111739. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
111740. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
111741. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
111742. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
111743. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
111744. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
111745. DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
111746. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
111747. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
111748. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
111749. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
111750. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
111751. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
111752. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
111753. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
111754. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
111755. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
111756. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
111757. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
111758. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
111759. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
111760. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
111761. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
111762. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
111763. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
111764. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
111765. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
111766. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
111767. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
111768. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
111769. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
111770. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
111771. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
111772. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
111773. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
111774. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
111775. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
111776. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
111777. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
111778. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
111779. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
111780. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
111781. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
111782. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
111783. DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
111784. DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
111785. DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
111786. DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
111787. DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
111788. DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
111789. DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
111790. DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
111791. DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
111792. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
111793. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
111794. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
111795. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
111796. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
111797. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
111798. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
111799. DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
111800. DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE_MASK
111801. DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE__SHIFT
111802. DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE_MASK
111803. DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE__SHIFT
111804. DMIF_ADDR_CALC
111805. DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK
111806. DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT
111807. DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK
111808. DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT
111809. DMIF_ADDR_CONFIG
111810. DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
111811. DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
111812. DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
111813. DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
111814. DMIF_ADDR_CONFIG__NUM_PIPES_MASK
111815. DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT
111816. DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
111817. DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
111818. DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
111819. DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
111820. DMIF_ADDR_CONFIG__ROW_SIZE_MASK
111821. DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT
111822. DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
111823. DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
111824. DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK
111825. DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT
111826. DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK
111827. DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT
111828. DMIF_BUFFERS_ALLOCATED
111829. DMIF_BUFFERS_ALLOCATED_COMPLETED
111830. DMIF_CONTROL__DMIF_BUFF_SIZE_MASK
111831. DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT
111832. DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK
111833. DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT
111834. DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK
111835. DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT
111836. DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK
111837. DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT
111838. DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK
111839. DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT
111840. DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK
111841. DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT
111842. DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK
111843. DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT
111844. DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE_MASK
111845. DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE__SHIFT
111846. DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK
111847. DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT
111848. DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK
111849. DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT
111850. DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK
111851. DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT
111852. DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE_MASK
111853. DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE__SHIFT
111854. DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY_MASK
111855. DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT
111856. DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL_MASK
111857. DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL__SHIFT
111858. DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK
111859. DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT
111860. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS_MASK
111861. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS__SHIFT
111862. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_MASK
111863. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE__SHIFT
111864. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE_MASK
111865. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE__SHIFT
111866. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE_MASK
111867. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE__SHIFT
111868. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE_MASK
111869. DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE__SHIFT
111870. DMIF_DEBUG02_CORE0__DB_DATA_MASK
111871. DMIF_DEBUG02_CORE0__DB_DATA__SHIFT
111872. DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK
111873. DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT
111874. DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK
111875. DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT
111876. DMIF_DEBUG02_CORE1__DB_DATA_MASK
111877. DMIF_DEBUG02_CORE1__DB_DATA__SHIFT
111878. DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK
111879. DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT
111880. DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK
111881. DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT
111882. DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK
111883. DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT
111884. DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
111885. DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
111886. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
111887. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
111888. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
111889. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
111890. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
111891. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
111892. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
111893. DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
111894. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
111895. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
111896. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
111897. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
111898. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
111899. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
111900. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
111901. DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
111902. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK
111903. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT
111904. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK
111905. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT
111906. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK
111907. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT
111908. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK
111909. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT
111910. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
111911. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
111912. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
111913. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
111914. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK
111915. DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT
111916. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK
111917. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT
111918. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
111919. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
111920. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
111921. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK
111922. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT
111923. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
111924. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
111925. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
111926. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
111927. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
111928. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
111929. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK
111930. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
111931. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
111932. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
111933. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK
111934. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
111935. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
111936. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
111937. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK
111938. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
111939. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
111940. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
111941. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
111942. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
111943. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
111944. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
111945. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
111946. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
111947. DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
111948. DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
111949. DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
111950. DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
111951. DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
111952. DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK
111953. DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT
111954. DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK
111955. DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT
111956. DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
111957. DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
111958. DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
111959. DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
111960. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
111961. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
111962. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK
111963. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT
111964. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK
111965. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT
111966. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK
111967. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT
111968. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
111969. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
111970. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
111971. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
111972. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK
111973. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT
111974. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK
111975. DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT
111976. DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
111977. DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
111978. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
111979. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
111980. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
111981. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
111982. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
111983. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
111984. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
111985. DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
111986. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
111987. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
111988. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
111989. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
111990. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
111991. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
111992. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
111993. DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
111994. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK
111995. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT
111996. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK
111997. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT
111998. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK
111999. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT
112000. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK
112001. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT
112002. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
112003. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
112004. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
112005. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
112006. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK
112007. DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT
112008. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK
112009. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT
112010. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
112011. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
112012. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
112013. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK
112014. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT
112015. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
112016. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
112017. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
112018. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
112019. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
112020. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
112021. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK
112022. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
112023. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
112024. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
112025. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK
112026. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
112027. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
112028. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
112029. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK
112030. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
112031. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
112032. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
112033. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
112034. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
112035. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
112036. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
112037. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
112038. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
112039. DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
112040. DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
112041. DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
112042. DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
112043. DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
112044. DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK
112045. DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT
112046. DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK
112047. DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT
112048. DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
112049. DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
112050. DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
112051. DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
112052. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
112053. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
112054. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK
112055. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT
112056. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK
112057. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT
112058. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK
112059. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT
112060. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
112061. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
112062. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
112063. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
112064. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK
112065. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT
112066. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK
112067. DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT
112068. DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
112069. DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
112070. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
112071. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
112072. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
112073. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
112074. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
112075. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
112076. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
112077. DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
112078. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
112079. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
112080. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
112081. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
112082. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
112083. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
112084. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
112085. DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
112086. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK
112087. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT
112088. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK
112089. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT
112090. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK
112091. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT
112092. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK
112093. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT
112094. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
112095. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
112096. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
112097. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
112098. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK
112099. DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT
112100. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK
112101. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT
112102. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
112103. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
112104. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
112105. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK
112106. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT
112107. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
112108. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
112109. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
112110. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
112111. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
112112. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
112113. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK
112114. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
112115. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
112116. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
112117. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK
112118. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
112119. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
112120. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
112121. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK
112122. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
112123. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
112124. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
112125. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
112126. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
112127. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
112128. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
112129. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
112130. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
112131. DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
112132. DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
112133. DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
112134. DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
112135. DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
112136. DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK
112137. DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT
112138. DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK
112139. DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT
112140. DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
112141. DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
112142. DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
112143. DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
112144. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
112145. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
112146. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK
112147. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT
112148. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK
112149. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT
112150. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK
112151. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT
112152. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
112153. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
112154. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
112155. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
112156. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK
112157. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT
112158. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK
112159. DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT
112160. DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
112161. DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
112162. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
112163. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
112164. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
112165. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
112166. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
112167. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
112168. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
112169. DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
112170. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
112171. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
112172. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
112173. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
112174. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
112175. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
112176. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
112177. DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
112178. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK
112179. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT
112180. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK
112181. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT
112182. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK
112183. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT
112184. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK
112185. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT
112186. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
112187. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
112188. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
112189. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
112190. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK
112191. DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT
112192. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK
112193. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT
112194. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
112195. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
112196. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
112197. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK
112198. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT
112199. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
112200. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
112201. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
112202. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
112203. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
112204. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
112205. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK
112206. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
112207. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
112208. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
112209. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK
112210. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
112211. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
112212. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
112213. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK
112214. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
112215. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
112216. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
112217. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
112218. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
112219. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
112220. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
112221. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
112222. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
112223. DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
112224. DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
112225. DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
112226. DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
112227. DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
112228. DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK
112229. DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT
112230. DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK
112231. DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT
112232. DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
112233. DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
112234. DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
112235. DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
112236. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
112237. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
112238. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK
112239. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT
112240. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK
112241. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT
112242. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK
112243. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT
112244. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
112245. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
112246. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
112247. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
112248. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK
112249. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT
112250. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK
112251. DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT
112252. DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
112253. DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
112254. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
112255. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
112256. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
112257. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
112258. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
112259. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
112260. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
112261. DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
112262. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
112263. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
112264. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
112265. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
112266. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
112267. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
112268. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
112269. DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
112270. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK
112271. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT
112272. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK
112273. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT
112274. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK
112275. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT
112276. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK
112277. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT
112278. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
112279. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
112280. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
112281. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
112282. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK
112283. DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT
112284. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK
112285. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT
112286. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
112287. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
112288. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
112289. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK
112290. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT
112291. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
112292. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
112293. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
112294. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
112295. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
112296. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
112297. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK
112298. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
112299. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
112300. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
112301. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK
112302. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
112303. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
112304. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
112305. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK
112306. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
112307. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
112308. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
112309. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
112310. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
112311. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
112312. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
112313. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
112314. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
112315. DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
112316. DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
112317. DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
112318. DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
112319. DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
112320. DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK
112321. DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT
112322. DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK
112323. DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT
112324. DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
112325. DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
112326. DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
112327. DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
112328. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
112329. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
112330. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK
112331. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT
112332. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK
112333. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT
112334. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK
112335. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT
112336. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
112337. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
112338. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
112339. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
112340. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK
112341. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT
112342. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK
112343. DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT
112344. DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
112345. DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
112346. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
112347. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
112348. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
112349. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
112350. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
112351. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
112352. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
112353. DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
112354. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
112355. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
112356. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
112357. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
112358. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
112359. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
112360. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
112361. DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
112362. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK
112363. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT
112364. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK
112365. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT
112366. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK
112367. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT
112368. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK
112369. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT
112370. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
112371. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
112372. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
112373. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
112374. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK
112375. DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT
112376. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK
112377. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT
112378. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
112379. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
112380. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
112381. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK
112382. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT
112383. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
112384. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
112385. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
112386. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
112387. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
112388. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
112389. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK
112390. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
112391. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
112392. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
112393. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK
112394. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
112395. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
112396. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
112397. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK
112398. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
112399. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
112400. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
112401. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
112402. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
112403. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
112404. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
112405. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
112406. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
112407. DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
112408. DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
112409. DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
112410. DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
112411. DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
112412. DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK
112413. DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT
112414. DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK
112415. DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT
112416. DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
112417. DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
112418. DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
112419. DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
112420. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
112421. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
112422. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK
112423. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT
112424. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK
112425. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT
112426. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK
112427. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT
112428. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
112429. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
112430. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
112431. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
112432. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK
112433. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT
112434. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK
112435. DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT
112436. DMIF_P_VMID__P_VMID_PIPE0_MASK
112437. DMIF_P_VMID__P_VMID_PIPE0__SHIFT
112438. DMIF_P_VMID__P_VMID_PIPE1_MASK
112439. DMIF_P_VMID__P_VMID_PIPE1__SHIFT
112440. DMIF_P_VMID__P_VMID_PIPE2_MASK
112441. DMIF_P_VMID__P_VMID_PIPE2__SHIFT
112442. DMIF_P_VMID__P_VMID_PIPE3_MASK
112443. DMIF_P_VMID__P_VMID_PIPE3__SHIFT
112444. DMIF_P_VMID__P_VMID_PIPE4_MASK
112445. DMIF_P_VMID__P_VMID_PIPE4__SHIFT
112446. DMIF_P_VMID__P_VMID_PIPE5_MASK
112447. DMIF_P_VMID__P_VMID_PIPE5__SHIFT
112448. DMIF_P_VMID__P_VMID_PIPE6_MASK
112449. DMIF_P_VMID__P_VMID_PIPE6__SHIFT
112450. DMIF_P_VMID__P_VMID_PIPE7_MASK
112451. DMIF_P_VMID__P_VMID_PIPE7__SHIFT
112452. DMIF_REG
112453. DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK
112454. DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT
112455. DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK
112456. DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT
112457. DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK
112458. DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT
112459. DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK
112460. DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT
112461. DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK
112462. DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT
112463. DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK
112464. DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT
112465. DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK
112466. DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT
112467. DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK
112468. DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT
112469. DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK
112470. DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT
112471. DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK
112472. DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT
112473. DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK
112474. DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT
112475. DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK
112476. DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT
112477. DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK
112478. DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT
112479. DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK
112480. DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT
112481. DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK
112482. DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT
112483. DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK
112484. DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT
112485. DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER_MASK
112486. DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER__SHIFT
112487. DMIF_STATUS__DMIF_UNDERFLOW_MASK
112488. DMIF_STATUS__DMIF_UNDERFLOW__SHIFT
112489. DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK
112490. DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT
112491. DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK
112492. DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT
112493. DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK
112494. DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT
112495. DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK
112496. DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT
112497. DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK
112498. DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT
112499. DMIGR_MINT_G0
112500. DMINFO
112501. DMINFO_LIMIT
112502. DMINT12
112503. DMINT13
112504. DMINT14
112505. DMINT15
112506. DMINT16
112507. DMINT17
112508. DMINT18
112509. DMINT19
112510. DMINT20
112511. DMINT21
112512. DMINT22
112513. DMINT23
112514. DMIPSPLLCFG_6368_NDIV_MASK
112515. DMIPSPLLCFG_6368_NDIV_SHIFT
112516. DMIPSPLLCFG_6368_P1_MASK
112517. DMIPSPLLCFG_6368_P1_SHIFT
112518. DMIPSPLLCFG_6368_P2_MASK
112519. DMIPSPLLCFG_6368_P2_SHIFT
112520. DMIPSPLLCFG_M1_MASK
112521. DMIPSPLLCFG_M1_SHIFT
112522. DMIPSPLLCFG_N1_MASK
112523. DMIPSPLLCFG_N1_SHIFT
112524. DMIPSPLLCFG_N2_MASK
112525. DMIPSPLLCFG_N2_SHIFT
112526. DMIPSPLLDIV_6368_MDIV_MASK
112527. DMIPSPLLDIV_6368_MDIV_SHIFT
112528. DMISGR0_MCX_COMEND
112529. DMISGR0_MCX_IN_INT
112530. DMISGR0_MCX_OUT_INT
112531. DMISGR0_MCX_SETUP_INT
112532. DMISGR1_MF0_IN_INT
112533. DMISGR1_MF0_OUT_INT
112534. DMISGR1_MF0_SPK_INT
112535. DMISGR1_MF1_IN_INT
112536. DMISGR1_MF1_OUT_INT
112537. DMISGR1_MF1_SPK_INT
112538. DMISGR1_MF2_IN_INT
112539. DMISGR1_MF2_OUT_INT
112540. DMISGR1_MF2_SPK_INT
112541. DMISGR1_MF3_IN_INT
112542. DMISGR1_MF3_OUT_INT
112543. DMISGR1_MF3_SPK_INT
112544. DMISGR1_MF_IN_INT
112545. DMISGR1_MF_OUTSPK_INT
112546. DMISGR2_MDMA_CMPLT
112547. DMISGR2_MDMA_ERROR
112548. DMISS
112549. DMISS_ACCESS
112550. DMIX_WANTS_S16
112551. DMI_ATTR
112552. DMI_BIOS_DATE
112553. DMI_BIOS_VENDOR
112554. DMI_BIOS_VERSION
112555. DMI_BLOCK
112556. DMI_BOARD_ASSET_TAG
112557. DMI_BOARD_NAME
112558. DMI_BOARD_SERIAL
112559. DMI_BOARD_VENDOR
112560. DMI_BOARD_VERSION
112561. DMI_BW_LIMIT_IN
112562. DMI_BW_LIMIT_OUT
112563. DMI_CHASSIS_ASSET_TAG
112564. DMI_CHASSIS_SERIAL
112565. DMI_CHASSIS_TYPE
112566. DMI_CHASSIS_VENDOR
112567. DMI_CHASSIS_VERSION
112568. DMI_DEV_TYPE_ANY
112569. DMI_DEV_TYPE_DEV_ONBOARD
112570. DMI_DEV_TYPE_DEV_SLOT
112571. DMI_DEV_TYPE_ETHERNET
112572. DMI_DEV_TYPE_IPMI
112573. DMI_DEV_TYPE_OEM_STRING
112574. DMI_DEV_TYPE_OTHER
112575. DMI_DEV_TYPE_PATA
112576. DMI_DEV_TYPE_SAS
112577. DMI_DEV_TYPE_SATA
112578. DMI_DEV_TYPE_SCSI
112579. DMI_DEV_TYPE_SOUND
112580. DMI_DEV_TYPE_TOKENRING
112581. DMI_DEV_TYPE_UNKNOWN
112582. DMI_DEV_TYPE_VIDEO
112583. DMI_ENTRY_32_MEM_ERROR
112584. DMI_ENTRY_ADDITIONAL
112585. DMI_ENTRY_BASEBOARD
112586. DMI_ENTRY_BIOS
112587. DMI_ENTRY_BIOS_LANG
112588. DMI_ENTRY_BIS_ENTRY
112589. DMI_ENTRY_BUILTIN_POINTING_DEV
112590. DMI_ENTRY_CACHE
112591. DMI_ENTRY_CHASSIS
112592. DMI_ENTRY_COOLING_DEV
112593. DMI_ENTRY_ELECTRICAL_CURRENT_PROBE
112594. DMI_ENTRY_END_OF_TABLE
112595. DMI_ENTRY_GROUP_ASSOC
112596. DMI_ENTRY_HW_SECURITY
112597. DMI_ENTRY_INACTIVE
112598. DMI_ENTRY_IPMI_DEV
112599. DMI_ENTRY_MEM_ARRAY_MAPPED_ADDR
112600. DMI_ENTRY_MEM_CHANNEL
112601. DMI_ENTRY_MEM_CONTROLLER
112602. DMI_ENTRY_MEM_DEVICE
112603. DMI_ENTRY_MEM_DEV_MAPPED_ADDR
112604. DMI_ENTRY_MEM_MODULE
112605. DMI_ENTRY_MGMT_CONTROLLER_HOST
112606. DMI_ENTRY_MGMT_DEV
112607. DMI_ENTRY_MGMT_DEV_COMPONENT
112608. DMI_ENTRY_MGMT_DEV_THRES
112609. DMI_ENTRY_OEMSTRINGS
112610. DMI_ENTRY_ONBOARD_DEVICE
112611. DMI_ENTRY_ONBOARD_DEV_EXT
112612. DMI_ENTRY_OOB_REMOTE_ACCESS
112613. DMI_ENTRY_PHYS_MEM_ARRAY
112614. DMI_ENTRY_PORTABLE_BATTERY
112615. DMI_ENTRY_PORT_CONNECTOR
112616. DMI_ENTRY_PROCESSOR
112617. DMI_ENTRY_PROCESSOR_MIN_LENGTH
112618. DMI_ENTRY_SYSCONF
112619. DMI_ENTRY_SYSTEM
112620. DMI_ENTRY_SYSTEM_BOOT
112621. DMI_ENTRY_SYSTEM_EVENT_LOG
112622. DMI_ENTRY_SYSTEM_POWER_CONTROLS
112623. DMI_ENTRY_SYSTEM_RESET
112624. DMI_ENTRY_SYSTEM_SLOT
112625. DMI_ENTRY_SYS_POWER_SUPPLY
112626. DMI_ENTRY_TEMP_PROBE
112627. DMI_ENTRY_VOLTAGE_PROBE
112628. DMI_EXACT_MATCH
112629. DMI_IPMI_ACCESS
112630. DMI_IPMI_ADDR
112631. DMI_IPMI_IO_MASK
112632. DMI_IPMI_IRQ
112633. DMI_IPMI_MIN_LENGTH
112634. DMI_IPMI_SLAVEADDR
112635. DMI_IPMI_TYPE
112636. DMI_IPMI_VER2_LENGTH
112637. DMI_MATCH
112638. DMI_NONE
112639. DMI_OEM_STRING
112640. DMI_OVERHEAD
112641. DMI_OVERHEAD_BURST
112642. DMI_PROCESSOR_MAX_SPEED
112643. DMI_PRODUCT_FAMILY
112644. DMI_PRODUCT_NAME
112645. DMI_PRODUCT_SERIAL
112646. DMI_PRODUCT_SKU
112647. DMI_PRODUCT_UUID
112648. DMI_PRODUCT_VERSION
112649. DMI_SEL_ACCESS_METHOD_GPNV
112650. DMI_SEL_ACCESS_METHOD_IO16
112651. DMI_SEL_ACCESS_METHOD_IO2x8
112652. DMI_SEL_ACCESS_METHOD_IO8
112653. DMI_SEL_ACCESS_METHOD_PHYS32
112654. DMI_STRING_MAX
112655. DMI_SYSFS_ATTR
112656. DMI_SYSFS_MAPPED_ATTR
112657. DMI_SYSFS_SEL_FIELD
112658. DMI_SYS_VENDOR
112659. DML_CONFIG
112660. DML_CONSUMER_PIPE_LOGICAL_SIZE
112661. DML_CONSUMER_START
112662. DML_FAIL_CURSOR_SUPPORT
112663. DML_FAIL_DIO_SUPPORT
112664. DML_FAIL_DISPCLK_DPPCLK
112665. DML_FAIL_DSC_CLK_REQUIRED
112666. DML_FAIL_DSC_INPUT_BPC
112667. DML_FAIL_DSC_VALIDATION_FAILURE
112668. DML_FAIL_HOST_VM_IMMEDIATE_FLIP
112669. DML_FAIL_NOT_ENOUGH_DSC
112670. DML_FAIL_NUM_OTG
112671. DML_FAIL_PITCH_SUPPORT
112672. DML_FAIL_PREFETCH_SUPPORT
112673. DML_FAIL_PTE_BUFFER_SIZE
112674. DML_FAIL_REORDERING_BUFFER
112675. DML_FAIL_SCALE_RATIO_TAP
112676. DML_FAIL_SOURCE_PIXEL_FORMAT
112677. DML_FAIL_TOTAL_AVAILABLE_PIPES
112678. DML_FAIL_TOTAL_V_ACTIVE_BW
112679. DML_FAIL_URGENT_LATENCY
112680. DML_FAIL_VIEWPORT_SIZE
112681. DML_FAIL_V_RATIO_PREFETCH
112682. DML_FAIL_WRITEBACK_LATENCY
112683. DML_FAIL_WRITEBACK_MODE
112684. DML_FAIL_WRITEBACK_SCALE_RATIO_TAP
112685. DML_OFFSET
112686. DML_PIPE_ID
112687. DML_PRODUCER_BAM_BLOCK_SIZE
112688. DML_PRODUCER_BAM_TRANS_SIZE
112689. DML_PRODUCER_PIPE_LOGICAL_SIZE
112690. DML_PRODUCER_START
112691. DML_PROJECT_DCN21
112692. DML_PROJECT_NAVI10
112693. DML_PROJECT_NAVI10v2
112694. DML_PROJECT_RAVEN1
112695. DML_PROJECT_UNDEFINED
112696. DML_SW_RESET
112697. DML_VALIDATION_OK
112698. DMM32AT_8255_IOBASE
112699. DMM32AT_AI_CFG_ADBU
112700. DMM32AT_AI_CFG_GAIN
112701. DMM32AT_AI_CFG_RANGE
112702. DMM32AT_AI_CFG_REG
112703. DMM32AT_AI_CFG_SCINT
112704. DMM32AT_AI_CFG_SCINT_10US
112705. DMM32AT_AI_CFG_SCINT_15US
112706. DMM32AT_AI_CFG_SCINT_20US
112707. DMM32AT_AI_CFG_SCINT_5US
112708. DMM32AT_AI_HI_CHAN_REG
112709. DMM32AT_AI_LO_CHAN_REG
112710. DMM32AT_AI_LSB_REG
112711. DMM32AT_AI_MSB_REG
112712. DMM32AT_AI_READBACK_ADBU
112713. DMM32AT_AI_READBACK_GAIN_MASK
112714. DMM32AT_AI_READBACK_RANGE
112715. DMM32AT_AI_READBACK_REG
112716. DMM32AT_AI_READBACK_WAIT
112717. DMM32AT_AI_START_CONV_REG
112718. DMM32AT_AI_STATUS_ADCH_MASK
112719. DMM32AT_AI_STATUS_REG
112720. DMM32AT_AI_STATUS_SD0
112721. DMM32AT_AI_STATUS_SD1
112722. DMM32AT_AI_STATUS_STS
112723. DMM32AT_AO_LSB_REG
112724. DMM32AT_AO_MSB_DACH
112725. DMM32AT_AO_MSB_REG
112726. DMM32AT_AUX_DI0
112727. DMM32AT_AUX_DI1
112728. DMM32AT_AUX_DI2
112729. DMM32AT_AUX_DI3
112730. DMM32AT_AUX_DI_CALBUSY
112731. DMM32AT_AUX_DI_DACBUSY
112732. DMM32AT_AUX_DI_REG
112733. DMM32AT_AUX_DOUT0
112734. DMM32AT_AUX_DOUT1
112735. DMM32AT_AUX_DOUT2
112736. DMM32AT_AUX_DOUT_REG
112737. DMM32AT_CLK1
112738. DMM32AT_CLK2
112739. DMM32AT_CLKCT
112740. DMM32AT_CLKCT1
112741. DMM32AT_CLKCT2
112742. DMM32AT_CTRDIO_CFG_FREQ0
112743. DMM32AT_CTRDIO_CFG_FREQ12
112744. DMM32AT_CTRDIO_CFG_GT0EN
112745. DMM32AT_CTRDIO_CFG_GT12EN
112746. DMM32AT_CTRDIO_CFG_OUT0EN
112747. DMM32AT_CTRDIO_CFG_OUT2EN
112748. DMM32AT_CTRDIO_CFG_REG
112749. DMM32AT_CTRDIO_CFG_SRC0
112750. DMM32AT_CTRL_INTRST
112751. DMM32AT_CTRL_PAGE
112752. DMM32AT_CTRL_PAGE_8254
112753. DMM32AT_CTRL_PAGE_8255
112754. DMM32AT_CTRL_PAGE_CALIB
112755. DMM32AT_CTRL_REG
112756. DMM32AT_CTRL_RESETA
112757. DMM32AT_CTRL_RESETD
112758. DMM32AT_FIFO_CTRL_FIFOEN
112759. DMM32AT_FIFO_CTRL_FIFORST
112760. DMM32AT_FIFO_CTRL_REG
112761. DMM32AT_FIFO_CTRL_SCANEN
112762. DMM32AT_FIFO_DEPTH_REG
112763. DMM32AT_FIFO_STATUS_EF
112764. DMM32AT_FIFO_STATUS_FF
112765. DMM32AT_FIFO_STATUS_FIFOEN
112766. DMM32AT_FIFO_STATUS_HF
112767. DMM32AT_FIFO_STATUS_OVF
112768. DMM32AT_FIFO_STATUS_PAGE_MASK
112769. DMM32AT_FIFO_STATUS_REG
112770. DMM32AT_FIFO_STATUS_SCANEN
112771. DMM32AT_INTCLK_ADINT
112772. DMM32AT_INTCLK_CLKEN
112773. DMM32AT_INTCLK_CLKSEL
112774. DMM32AT_INTCLK_DINT
112775. DMM32AT_INTCLK_REG
112776. DMM32AT_INTCLK_TINT
112777. DMM32AT_RANGE_B10
112778. DMM32AT_RANGE_B5
112779. DMM32AT_RANGE_U10
112780. DMM32AT_RANGE_U5
112781. DMMD
112782. DMMU_SFAR
112783. DMM_DMM_SYSCONFIG
112784. DMM_DRIVER_NAME
112785. DMM_FIXED_RETRY_COUNT
112786. DMM_HWINFO
112787. DMM_IRQSTAT_DST
112788. DMM_IRQSTAT_ERR_INV_DATA
112789. DMM_IRQSTAT_ERR_INV_DSC
112790. DMM_IRQSTAT_ERR_LUT_MISS
112791. DMM_IRQSTAT_ERR_MASK
112792. DMM_IRQSTAT_ERR_UPD_AREA
112793. DMM_IRQSTAT_ERR_UPD_CTRL
112794. DMM_IRQSTAT_ERR_UPD_DATA
112795. DMM_IRQSTAT_LST
112796. DMM_LISA_HWINFO
112797. DMM_LISA_LOCK
112798. DMM_LISA_MAP__0
112799. DMM_LISA_MAP__1
112800. DMM_PATSTATUS_BYPASSED
112801. DMM_PATSTATUS_DONE
112802. DMM_PATSTATUS_ERR
112803. DMM_PATSTATUS_ERR_ACCESS
112804. DMM_PATSTATUS_ERR_INV_DATA
112805. DMM_PATSTATUS_ERR_INV_DESCR
112806. DMM_PATSTATUS_ERR_UPD_AREA
112807. DMM_PATSTATUS_ERR_UPD_CTRL
112808. DMM_PATSTATUS_ERR_UPD_DATA
112809. DMM_PATSTATUS_LINKED
112810. DMM_PATSTATUS_READY
112811. DMM_PATSTATUS_RUN
112812. DMM_PATSTATUS_VALID
112813. DMM_PAT_CONFIG
112814. DMM_PAT_DESCR__0
112815. DMM_PAT_DESCR__1
112816. DMM_PAT_DESCR__2
112817. DMM_PAT_DESCR__3
112818. DMM_PAT_GEOMETRY
112819. DMM_PAT_HWINFO
112820. DMM_PAT_IRQENABLE_CLR
112821. DMM_PAT_IRQENABLE_SET
112822. DMM_PAT_IRQSTATUS
112823. DMM_PAT_IRQSTATUS_RAW
112824. DMM_PAT_IRQ_EOI
112825. DMM_PAT_STATUS__0
112826. DMM_PAT_STATUS__1
112827. DMM_PAT_STATUS__2
112828. DMM_PAT_STATUS__3
112829. DMM_PAT_VIEW_MAP_BASE
112830. DMM_PAT_VIEW_MAP__0
112831. DMM_PAT_VIEW__0
112832. DMM_PAT_VIEW__1
112833. DMM_PEG_HWINFO
112834. DMM_PEG_PRIO
112835. DMM_PEG_PRIO_PAT
112836. DMM_REVISION
112837. DMM_TILER_HWINFO
112838. DMM_TILER_OR__0
112839. DMM_TILER_OR__1
112840. DMODE_700_REG
112841. DMODE_710_REG
112842. DMODE_FC1
112843. DMODE_FC2
112844. DMP_COMP_CLASS
112845. DMP_COMP_CLASS_S
112846. DMP_COMP_DESIGNER
112847. DMP_COMP_DESIGNER_S
112848. DMP_COMP_NUM_MPORT
112849. DMP_COMP_NUM_MPORT_S
112850. DMP_COMP_NUM_MWRAP
112851. DMP_COMP_NUM_MWRAP_S
112852. DMP_COMP_NUM_SPORT
112853. DMP_COMP_NUM_SPORT_S
112854. DMP_COMP_NUM_SWRAP
112855. DMP_COMP_NUM_SWRAP_S
112856. DMP_COMP_PARTNUM
112857. DMP_COMP_PARTNUM_S
112858. DMP_COMP_REVISION
112859. DMP_COMP_REVISION_S
112860. DMP_DESC_ADDRESS
112861. DMP_DESC_ADDRSIZE_GT32
112862. DMP_DESC_COMPONENT
112863. DMP_DESC_EMPTY
112864. DMP_DESC_EOT
112865. DMP_DESC_MASTER_PORT
112866. DMP_DESC_TYPE_MSK
112867. DMP_DESC_VALID
112868. DMP_LMSD
112869. DMP_MASTER_PORT_NUM
112870. DMP_MASTER_PORT_NUM_S
112871. DMP_MASTER_PORT_UID
112872. DMP_MASTER_PORT_UID_S
112873. DMP_MBOX_OFFSET_WORD
112874. DMP_MEM_REG
112875. DMP_NV_PARAMS
112876. DMP_P2P_DEVCAP_SUPPORT
112877. DMP_P2P_GRPCAP_SUPPORT
112878. DMP_PAGE_A0
112879. DMP_PAGE_A2
112880. DMP_REGION_23
112881. DMP_REGION_VPD
112882. DMP_REGION_VPORT
112883. DMP_RGN23_SIZE
112884. DMP_RSP_OFFSET
112885. DMP_RSP_SIZE
112886. DMP_SFF_PAGE_A0_SIZE
112887. DMP_SFF_PAGE_A2_SIZE
112888. DMP_SLAVE_ADDR_BASE
112889. DMP_SLAVE_ADDR_BASE_S
112890. DMP_SLAVE_PORT_NUM
112891. DMP_SLAVE_PORT_NUM_S
112892. DMP_SLAVE_SIZE_16K
112893. DMP_SLAVE_SIZE_4K
112894. DMP_SLAVE_SIZE_8K
112895. DMP_SLAVE_SIZE_DESC
112896. DMP_SLAVE_SIZE_TYPE
112897. DMP_SLAVE_SIZE_TYPE_S
112898. DMP_SLAVE_TYPE
112899. DMP_SLAVE_TYPE_BRIDGE
112900. DMP_SLAVE_TYPE_MWRAP
112901. DMP_SLAVE_TYPE_S
112902. DMP_SLAVE_TYPE_SLAVE
112903. DMP_SLAVE_TYPE_SWRAP
112904. DMP_VPD_SIZE
112905. DMP_VPORT_REGION_SIZE
112906. DMP_WELL_KNOWN
112907. DMR
112908. DMR_CNTE
112909. DMR_NF
112910. DMR_RX
112911. DMR_SEOME
112912. DMR_TMOD
112913. DMR_TX
112914. DMSE_INTR_EN
112915. DMSE_INTR_HIGH_SEL
112916. DMSG
112917. DMSR_HP
112918. DMSR_HR
112919. DMSR_SP
112920. DMSR_SR
112921. DMTCLR_REG
112922. DMTCNT_REG
112923. DMTCON_REG
112924. DMTE0_IRQ
112925. DMTE10_IRQ
112926. DMTE11_IRQ
112927. DMTE4_IRQ
112928. DMTE6_IRQ
112929. DMTE8_IRQ
112930. DMTE9_IRQ
112931. DMTPRECLR_REG
112932. DMTPSCNT_REG
112933. DMTPSINTV_REG
112934. DMTSTAT_BAD1
112935. DMTSTAT_BAD2
112936. DMTSTAT_EVENT
112937. DMTSTAT_REG
112938. DMTSTAT_WINOPN
112939. DMT_ON
112940. DMT_SIZE
112941. DMT_STEP1_KEY
112942. DMT_STEP2_KEY
112943. DMU_BASE__INST0_SEG0
112944. DMU_BASE__INST0_SEG1
112945. DMU_BASE__INST0_SEG2
112946. DMU_BASE__INST0_SEG3
112947. DMU_BASE__INST0_SEG4
112948. DMU_BASE__INST1_SEG0
112949. DMU_BASE__INST1_SEG1
112950. DMU_BASE__INST1_SEG2
112951. DMU_BASE__INST1_SEG3
112952. DMU_BASE__INST1_SEG4
112953. DMU_BASE__INST2_SEG0
112954. DMU_BASE__INST2_SEG1
112955. DMU_BASE__INST2_SEG2
112956. DMU_BASE__INST2_SEG3
112957. DMU_BASE__INST2_SEG4
112958. DMU_BASE__INST3_SEG0
112959. DMU_BASE__INST3_SEG1
112960. DMU_BASE__INST3_SEG2
112961. DMU_BASE__INST3_SEG3
112962. DMU_BASE__INST3_SEG4
112963. DMU_BASE__INST4_SEG0
112964. DMU_BASE__INST4_SEG1
112965. DMU_BASE__INST4_SEG2
112966. DMU_BASE__INST4_SEG3
112967. DMU_BASE__INST4_SEG4
112968. DMU_BASE__INST5_SEG0
112969. DMU_BASE__INST5_SEG1
112970. DMU_BASE__INST5_SEG2
112971. DMU_BASE__INST5_SEG3
112972. DMU_BASE__INST5_SEG4
112973. DMU_BASE__INST6_SEG0
112974. DMU_BASE__INST6_SEG1
112975. DMU_BASE__INST6_SEG2
112976. DMU_BASE__INST6_SEG3
112977. DMU_BASE__INST6_SEG4
112978. DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK
112979. DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT
112980. DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK
112981. DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT
112982. DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK
112983. DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT
112984. DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK
112985. DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT
112986. DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK
112987. DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT
112988. DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK
112989. DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT
112990. DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK
112991. DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT
112992. DMU_CLOCK_GATING_DISABLE
112993. DMU_CLOCK_ON
112994. DMU_CLOCK_STATUS_OFF
112995. DMU_CLOCK_STATUS_ON
112996. DMU_DC_GPU_TIMER_READ_SELECT
112997. DMU_DC_GPU_TIMER_START_POSITION
112998. DMU_DISABLE_CLOCK_GATING
112999. DMU_ENABLE_CLOCK_GATING
113000. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48
113001. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76
113002. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36
113003. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24
113004. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12
113005. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0
113006. DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64
113007. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50
113008. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78
113009. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38
113010. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26
113011. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14
113012. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2
113013. DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66
113014. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52
113015. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80
113016. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40
113017. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28
113018. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16
113019. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4
113020. DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68
113021. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54
113022. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82
113023. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42
113024. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30
113025. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18
113026. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6
113027. DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70
113028. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56
113029. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84
113030. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44
113031. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32
113032. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20
113033. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8
113034. DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72
113035. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58
113036. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86
113037. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46
113038. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34
113039. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22
113040. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10
113041. DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74
113042. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49
113043. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77
113044. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37
113045. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25
113046. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13
113047. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1
113048. DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65
113049. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51
113050. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79
113051. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39
113052. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27
113053. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15
113054. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3
113055. DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67
113056. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53
113057. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81
113058. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41
113059. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29
113060. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17
113061. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5
113062. DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69
113063. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55
113064. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83
113065. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43
113066. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31
113067. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19
113068. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7
113069. DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71
113070. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57
113071. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85
113072. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45
113073. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33
113074. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21
113075. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9
113076. DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73
113077. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59
113078. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87
113079. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47
113080. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35
113081. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23
113082. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11
113083. DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75
113084. DMU_GPU_TIMER_START_0_END_27
113085. DMU_GPU_TIMER_START_10_END_37
113086. DMU_GPU_TIMER_START_1_END_28
113087. DMU_GPU_TIMER_START_2_END_29
113088. DMU_GPU_TIMER_START_3_END_30
113089. DMU_GPU_TIMER_START_4_END_31
113090. DMU_GPU_TIMER_START_6_END_33
113091. DMU_GPU_TIMER_START_8_END_35
113092. DMU_HWID
113093. DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK
113094. DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT
113095. DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK
113096. DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT
113097. DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK
113098. DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT
113099. DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK
113100. DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT
113101. DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK
113102. DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT
113103. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK
113104. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT
113105. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK
113106. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT
113107. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK
113108. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT
113109. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK
113110. DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT
113111. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK
113112. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT
113113. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK
113114. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT
113115. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK
113116. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT
113117. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK
113118. DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT
113119. DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK
113120. DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT
113121. DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK
113122. DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT
113123. DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK
113124. DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT
113125. DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK
113126. DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT
113127. DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK
113128. DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT
113129. DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK
113130. DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT
113131. DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK
113132. DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT
113133. DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK
113134. DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT
113135. DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK
113136. DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT
113137. DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK
113138. DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT
113139. DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK
113140. DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT
113141. DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
113142. DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
113143. DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
113144. DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
113145. DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK
113146. DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT
113147. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK
113148. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT
113149. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK
113150. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT
113151. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK
113152. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT
113153. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK
113154. DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT
113155. DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK
113156. DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT
113157. DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK
113158. DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT
113159. DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
113160. DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
113161. DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK
113162. DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT
113163. DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK
113164. DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT
113165. DMWARN
113166. DMWARN_LIMIT
113167. DMX3191D_DRIVER_NAME
113168. DMX3191D_REGION_LEN
113169. DMX6FIRE_CONTROL
113170. DMXDEV_CAP_DUPLEX
113171. DMXDEV_STATE_ALLOCATED
113172. DMXDEV_STATE_DONE
113173. DMXDEV_STATE_FREE
113174. DMXDEV_STATE_GO
113175. DMXDEV_STATE_SET
113176. DMXDEV_STATE_TIMEDOUT
113177. DMXDEV_TYPE_NONE
113178. DMXDEV_TYPE_PES
113179. DMXDEV_TYPE_SEC
113180. DMX_ADD_PID
113181. DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED
113182. DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR
113183. DMX_BUFFER_FLAG_HAD_CRC32_DISCARD
113184. DMX_BUFFER_FLAG_TEI
113185. DMX_BUFFER_PKT_COUNTER_MISMATCH
113186. DMX_CHECK_CRC
113187. DMX_DQBUF
113188. DMX_EXPBUF
113189. DMX_FE_ENTRY
113190. DMX_FILTER_SIZE
113191. DMX_FRONTEND_0
113192. DMX_GET_PES_PIDS
113193. DMX_GET_STC
113194. DMX_IMMEDIATE_START
113195. DMX_IN_DVR
113196. DMX_IN_FRONTEND
113197. DMX_MAX_FILTER_SIZE
113198. DMX_MAX_PID
113199. DMX_MAX_SECFEED_SIZE
113200. DMX_MAX_SECTION_SIZE
113201. DMX_MEMORY_BASED_FILTERING
113202. DMX_MEMORY_FE
113203. DMX_ONESHOT
113204. DMX_OUT_DECODER
113205. DMX_OUT_TAP
113206. DMX_OUT_TSDEMUX_TAP
113207. DMX_OUT_TS_TAP
113208. DMX_PES_AUDIO
113209. DMX_PES_AUDIO0
113210. DMX_PES_AUDIO1
113211. DMX_PES_AUDIO2
113212. DMX_PES_AUDIO3
113213. DMX_PES_OTHER
113214. DMX_PES_PCR
113215. DMX_PES_PCR0
113216. DMX_PES_PCR1
113217. DMX_PES_PCR2
113218. DMX_PES_PCR3
113219. DMX_PES_SUBTITLE
113220. DMX_PES_SUBTITLE0
113221. DMX_PES_SUBTITLE1
113222. DMX_PES_SUBTITLE2
113223. DMX_PES_SUBTITLE3
113224. DMX_PES_TELETEXT
113225. DMX_PES_TELETEXT0
113226. DMX_PES_TELETEXT1
113227. DMX_PES_TELETEXT2
113228. DMX_PES_TELETEXT3
113229. DMX_PES_VIDEO
113230. DMX_PES_VIDEO0
113231. DMX_PES_VIDEO1
113232. DMX_PES_VIDEO2
113233. DMX_PES_VIDEO3
113234. DMX_QBUF
113235. DMX_QUERYBUF
113236. DMX_REMOVE_PID
113237. DMX_REQBUFS
113238. DMX_SECTION_FILTERING
113239. DMX_SET_BUFFER_SIZE
113240. DMX_SET_FILTER
113241. DMX_SET_PES_FILTER
113242. DMX_START
113243. DMX_STATE_ALLOCATED
113244. DMX_STATE_FREE
113245. DMX_STATE_GO
113246. DMX_STATE_READY
113247. DMX_STOP
113248. DMX_TS_FILTERING
113249. DMX_TYPE_SEC
113250. DMX_TYPE_TS
113251. DMZ_ALLOC_RECLAIM
113252. DMZ_ALLOC_RND
113253. DMZ_BDEV_DYING
113254. DMZ_BLOCK_MASK
113255. DMZ_BLOCK_MASK_BITS
113256. DMZ_BLOCK_SECTORS
113257. DMZ_BLOCK_SECTORS_MASK
113258. DMZ_BLOCK_SECTORS_SHIFT
113259. DMZ_BLOCK_SHIFT
113260. DMZ_BLOCK_SHIFT_BITS
113261. DMZ_BLOCK_SIZE
113262. DMZ_BLOCK_SIZE_BITS
113263. DMZ_BUF
113264. DMZ_CHECK_BDEV
113265. DMZ_DATA
113266. DMZ_FLUSH_PERIOD
113267. DMZ_IDLE_PERIOD
113268. DMZ_MAGIC
113269. DMZ_MAP_ENTRIES
113270. DMZ_MAP_ENTRIES_MASK
113271. DMZ_MAP_ENTRIES_SHIFT
113272. DMZ_MAP_UNMAPPED
113273. DMZ_META
113274. DMZ_META_DIRTY
113275. DMZ_META_ERROR
113276. DMZ_META_READING
113277. DMZ_META_VER
113278. DMZ_META_WRITING
113279. DMZ_MIN_BIOS
113280. DMZ_OFFLINE
113281. DMZ_READ_ONLY
113282. DMZ_RECLAIM
113283. DMZ_RECLAIM_HIGH_UNMAP_RND
113284. DMZ_RECLAIM_KCOPY
113285. DMZ_RECLAIM_LOW_UNMAP_RND
113286. DMZ_REPORT_NR_ZONES
113287. DMZ_RND
113288. DMZ_SEQ
113289. DMZ_SEQ_WRITE_ERR
113290. DM_1R_CCA_E
113291. DM_ACTIVE_PRESENT_FLAG
113292. DM_ACT_SIZE
113293. DM_ANY_MINOR
113294. DM_ATTR_CLASS_PORT_INFO
113295. DM_ATTR_IOC_PROFILE
113296. DM_ATTR_IOU_INFO
113297. DM_ATTR_RO
113298. DM_ATTR_RW
113299. DM_ATTR_SVC_ENTRIES
113300. DM_BALLOON_DOWN
113301. DM_BALLOON_REQUEST
113302. DM_BALLOON_RESPONSE
113303. DM_BALLOON_UP
113304. DM_BIO_PRISON_H
113305. DM_BIO_PRISON_V2_H
113306. DM_BIO_RECORD_H
113307. DM_BIT_IGI_11AC
113308. DM_BIT_IGI_11N
113309. DM_BTREE_CURSOR_MAX_DEPTH
113310. DM_BTREE_INTERNAL_H
113311. DM_BUFFER_FULL_FLAG
113312. DM_BUFIO_DEFAULT_AGE_SECS
113313. DM_BUFIO_DEFAULT_RETAIN_BYTES
113314. DM_BUFIO_LOW_WATERMARK_RATIO
113315. DM_BUFIO_MEMORY_PERCENT
113316. DM_BUFIO_MIN_BUFFERS
113317. DM_BUFIO_VMALLOC_PERCENT
113318. DM_BUFIO_WORK_TIMER_SECS
113319. DM_BUFIO_WRITEBACK_RATIO
113320. DM_BUFIO_WRITE_ALIGN
113321. DM_CACHE_BACKGROUND_WORK_H
113322. DM_CACHE_BLOCK_TYPES_H
113323. DM_CACHE_FEATURE_COMPAT_RO_SUPP
113324. DM_CACHE_FEATURE_COMPAT_SUPP
113325. DM_CACHE_FEATURE_INCOMPAT_SUPP
113326. DM_CACHE_METADATA_BLOCK_SIZE
113327. DM_CACHE_METADATA_H
113328. DM_CACHE_METADATA_MAX_SECTORS
113329. DM_CACHE_METADATA_MAX_SECTORS_WARNING
113330. DM_CACHE_POLICY_H
113331. DM_CACHE_POLICY_INTERNAL_H
113332. DM_CAPABILITIES_REPORT
113333. DM_CAPABILITIES_RESPONSE
113334. DM_CHIP_ID
113335. DM_CHUNK_CONSECUTIVE_BITS
113336. DM_CHUNK_NUMBER_BITS
113337. DM_CHUNK_SIZE_DEFAULT_SECTORS
113338. DM_CLONE_DISCARD_PASSDOWN
113339. DM_CLONE_HYDRATION_ENABLED
113340. DM_CLONE_HYDRATION_SUSPENDED
113341. DM_CLONE_MAX_CONCURRENT_LOCKS
113342. DM_CLONE_MAX_METADATA_VERSION
113343. DM_CLONE_METADATA_BLOCK_SIZE
113344. DM_CLONE_METADATA_H
113345. DM_CLONE_METADATA_MAX_SECTORS
113346. DM_CLONE_METADATA_MAX_SECTORS_WARNING
113347. DM_CLONE_MIN_METADATA_VERSION
113348. DM_CM_DTRAN_CTRL
113349. DM_CM_DTRAN_MODE
113350. DM_CM_INFO1
113351. DM_CM_INFO1_MASK
113352. DM_CM_INFO2
113353. DM_CM_INFO2_MASK
113354. DM_CM_RST
113355. DM_CONTROL_NODE
113356. DM_COOKIE_ENV_VAR_NAME
113357. DM_COOKIE_LENGTH
113358. DM_CORE_INTERNAL_H
113359. DM_CRC_NUM_CHANNELS
113360. DM_CRC_REGISTER_SPACING
113361. DM_CRYPT_KEY_VALID
113362. DM_CRYPT_MEMORY_PERCENT
113363. DM_CRYPT_MIN_PAGES_PER_CLIENT
113364. DM_CRYPT_NO_OFFLOAD
113365. DM_CRYPT_SAME_CPU
113366. DM_CRYPT_SUSPENDED
113367. DM_CTRL_WK_CID
113368. DM_DATA_OUT_FLAG
113369. DM_DBG_MAX
113370. DM_DBG_OFF
113371. DM_DBG_ON
113372. DM_DEC
113373. DM_DEFERRED_REMOVE
113374. DM_DEV_ARM_POLL
113375. DM_DEV_ARM_POLL_CMD
113376. DM_DEV_CREATE
113377. DM_DEV_CREATE_CMD
113378. DM_DEV_REMOVE
113379. DM_DEV_REMOVE_CMD
113380. DM_DEV_RENAME
113381. DM_DEV_RENAME_CMD
113382. DM_DEV_SET_GEOMETRY
113383. DM_DEV_SET_GEOMETRY_CMD
113384. DM_DEV_STATUS
113385. DM_DEV_STATUS_CMD
113386. DM_DEV_SUSPEND
113387. DM_DEV_SUSPEND_CMD
113388. DM_DEV_WAIT
113389. DM_DEV_WAIT_CMD
113390. DM_DIG
113391. DM_DIG_BACKOFF
113392. DM_DIG_BACKOFF_DEFAULT
113393. DM_DIG_BACKOFF_MAX
113394. DM_DIG_BACKOFF_MIN
113395. DM_DIG_FA_LOWER
113396. DM_DIG_FA_TH0
113397. DM_DIG_FA_TH0_92D
113398. DM_DIG_FA_TH0_LPS
113399. DM_DIG_FA_TH1
113400. DM_DIG_FA_TH1_92D
113401. DM_DIG_FA_TH1_LPS
113402. DM_DIG_FA_TH2
113403. DM_DIG_FA_TH2_92D
113404. DM_DIG_FA_TH2_LPS
113405. DM_DIG_FA_UPPER
113406. DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND
113407. DM_DIG_HIGH_PWR_IGI_LOWER_BOUND
113408. DM_DIG_HIGH_PWR_THRESHOLD
113409. DM_DIG_HIGH_PWR_THRESH_HIGH
113410. DM_DIG_HIGH_PWR_THRESH_LOW
113411. DM_DIG_LOW_PWR_THRESHOLD
113412. DM_DIG_MAX
113413. DM_DIG_MAX_AP
113414. DM_DIG_MAX_AP_HP
113415. DM_DIG_MAX_NIC
113416. DM_DIG_MAX_NIC_HP
113417. DM_DIG_MAX_OF_MIN
113418. DM_DIG_MAX_OF_MIN_NIC
113419. DM_DIG_MIN
113420. DM_DIG_MIN_AP
113421. DM_DIG_MIN_AP_DFS
113422. DM_DIG_MIN_AP_HP
113423. DM_DIG_MIN_NETCORE
113424. DM_DIG_MIN_NIC
113425. DM_DIG_MIN_NIC_8723
113426. DM_DIG_MIN_NIC_HP
113427. DM_DIG_MIN_Netcore
113428. DM_DIG_OP_E
113429. DM_DIG_THRESH_HIGH
113430. DM_DIG_THRESH_LOW
113431. DM_DIR
113432. DM_DP_CON_SWITCH_AUDIO
113433. DM_DP_CON_SWITCH_OPEN
113434. DM_DP_CON_SWITCH_UART
113435. DM_DP_CON_SWITCH_USB
113436. DM_DP_SWITCH_AUDIO
113437. DM_DP_SWITCH_OPEN
113438. DM_DP_SWITCH_UART
113439. DM_DP_SWITCH_USB
113440. DM_DRIVER_EMAIL
113441. DM_DTRAN_ADDR
113442. DM_EDCA_TURBO
113443. DM_EEPROM_LEN
113444. DM_EEPROM_MAGIC
113445. DM_EN
113446. DM_ENDIO_DELAY_REQUEUE
113447. DM_ENDIO_DONE
113448. DM_ENDIO_INCOMPLETE
113449. DM_ENDIO_REQUEUE
113450. DM_ERA_METADATA_BLOCK_SIZE
113451. DM_ERROR
113452. DM_FALSEALARM_THRESH_HIGH
113453. DM_FALSEALARM_THRESH_LOW
113454. DM_FIX
113455. DM_FMT
113456. DM_GET_TARGET_VERSION
113457. DM_GET_TARGET_VERSION_CMD
113458. DM_GPR_CTRL
113459. DM_GPR_DATA
113460. DM_HASH_MASK
113461. DM_HASH_SIZE
113462. DM_HOT_ADD
113463. DM_I2C_CB_ERR
113464. DM_INACTIVE_PRESENT_FLAG
113465. DM_INC
113466. DM_INFO_CCA_ALL
113467. DM_INFO_CCA_CCK
113468. DM_INFO_CCA_OFDM
113469. DM_INFO_CCK_ENABLE
113470. DM_INFO_CLM_RATIO
113471. DM_INFO_CRC32_ERROR_CCK
113472. DM_INFO_CRC32_ERROR_HT
113473. DM_INFO_CRC32_ERROR_HT_AGG
113474. DM_INFO_CRC32_ERROR_LEGACY
113475. DM_INFO_CRC32_ERROR_VHT
113476. DM_INFO_CRC32_OK_CCK
113477. DM_INFO_CRC32_OK_HT
113478. DM_INFO_CRC32_OK_HT_AGG
113479. DM_INFO_CRC32_OK_LEGACY
113480. DM_INFO_CRC32_OK_VHT
113481. DM_INFO_CURR_IGI
113482. DM_INFO_DBG_PORT_0
113483. DM_INFO_EDCCA_FLAG
113484. DM_INFO_FA_CCK
113485. DM_INFO_FA_OFDM
113486. DM_INFO_FA_TOTAL
113487. DM_INFO_IQK_ALL
113488. DM_INFO_IQK_NG
113489. DM_INFO_IQK_OK
113490. DM_INFO_MESSAGE
113491. DM_INFO_NHM_RATIO
113492. DM_INFO_OFDM_ENABLE
113493. DM_INFO_RSSI_MAX
113494. DM_INFO_RSSI_MIN
113495. DM_INFO_SIZE
113496. DM_INITIALIZED
113497. DM_INITIALIZING
113498. DM_INIT_ERROR
113499. DM_INTERNAL_H
113500. DM_INTERNAL_SUSPEND_FLAG
113501. DM_IN_LPS_WK_CID
113502. DM_IOCTL
113503. DM_IO_BIO
113504. DM_IO_ERROR_THRESHOLD
113505. DM_IO_KMEM
113506. DM_IO_MAGIC
113507. DM_IO_MAX_REGIONS
113508. DM_IO_PAGE_LIST
113509. DM_IO_VMA
113510. DM_IRQ_TABLE_LOCK
113511. DM_IRQ_TABLE_UNLOCK
113512. DM_KCOPYD_IGNORE_ERROR
113513. DM_KCOPYD_MAX_REGIONS
113514. DM_KCOPYD_WRITE_SEQ
113515. DM_LEVEL
113516. DM_LIST_DEVICES
113517. DM_LIST_DEVICES_CMD
113518. DM_LIST_VERSIONS
113519. DM_LIST_VERSIONS_CMD
113520. DM_LNH
113521. DM_LNL
113522. DM_LOG_USERSPACE_VSN
113523. DM_MAD_STATUS_INVALID_FIELD
113524. DM_MAD_STATUS_NO_IOC
113525. DM_MAD_STATUS_UNSUP_METHOD
113526. DM_MAD_STATUS_UNSUP_METHOD_ATTR
113527. DM_MAPIO_DELAY_REQUEUE
113528. DM_MAPIO_KILL
113529. DM_MAPIO_REMAPPED
113530. DM_MAPIO_REQUEUE
113531. DM_MAPIO_SUBMITTED
113532. DM_MAX_DEVICES
113533. DM_MAX_MCAST
113534. DM_MAX_STR_SIZE
113535. DM_MAX_TARGETS
113536. DM_MAX_TYPE_NAME
113537. DM_MCAST_ADDR
113538. DM_MCAST_SIZE
113539. DM_MEM_HOT_ADD_REQUEST
113540. DM_MEM_HOT_ADD_RESPONSE
113541. DM_MODE_CTRL
113542. DM_MONITOR
113543. DM_MPATH_H
113544. DM_MQ_NR_HW_QUEUES
113545. DM_MQ_QUEUE_DEPTH
113546. DM_MSG_PREFIX
113547. DM_NAME
113548. DM_NAME_LEN
113549. DM_NET_CTRL
113550. DM_NOFLUSH_FLAG
113551. DM_NUMA_NODE
113552. DM_NUM_CHANNELS
113553. DM_ODM_T
113554. DM_Out_Source_Dynamic_Mechanism_Structure
113555. DM_PARAMS_MALLOC
113556. DM_PARTIAL_REGISTER_SPACING
113557. DM_PATH_SELECTOR_H
113558. DM_PERSISTENT_DEV_FLAG
113559. DM_PG_INIT_DELAY_DEFAULT
113560. DM_PG_INIT_DELAY_MSECS
113561. DM_PHY_ADDR
113562. DM_PKT_TYPE
113563. DM_PP_CLOCKS_DPM_STATE_LEVEL_0
113564. DM_PP_CLOCKS_DPM_STATE_LEVEL_1
113565. DM_PP_CLOCKS_DPM_STATE_LEVEL_2
113566. DM_PP_CLOCKS_DPM_STATE_LEVEL_3
113567. DM_PP_CLOCKS_DPM_STATE_LEVEL_4
113568. DM_PP_CLOCKS_DPM_STATE_LEVEL_5
113569. DM_PP_CLOCKS_DPM_STATE_LEVEL_6
113570. DM_PP_CLOCKS_DPM_STATE_LEVEL_7
113571. DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID
113572. DM_PP_CLOCKS_MAX_STATES
113573. DM_PP_CLOCKS_STATE_INVALID
113574. DM_PP_CLOCKS_STATE_LOW
113575. DM_PP_CLOCKS_STATE_NOMINAL
113576. DM_PP_CLOCKS_STATE_PERFORMANCE
113577. DM_PP_CLOCKS_STATE_ULTRA_LOW
113578. DM_PP_CLOCK_TYPE_DCEFCLK
113579. DM_PP_CLOCK_TYPE_DCFCLK
113580. DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
113581. DM_PP_CLOCK_TYPE_DISPLAY_CLK
113582. DM_PP_CLOCK_TYPE_DPPCLK
113583. DM_PP_CLOCK_TYPE_ENGINE_CLK
113584. DM_PP_CLOCK_TYPE_FCLK
113585. DM_PP_CLOCK_TYPE_MEMORY_CLK
113586. DM_PP_CLOCK_TYPE_PIXELCLK
113587. DM_PP_CLOCK_TYPE_SOCCLK
113588. DM_PP_MAX_CLOCK_LEVELS
113589. DM_PP_SMU_IF__H
113590. DM_PREFETCH_CHUNKS
113591. DM_PWDB
113592. DM_QUERY_INACTIVE_TABLE_FLAG
113593. DM_RAID1_FLUSH_ERROR
113594. DM_RAID1_HANDLE_ERRORS
113595. DM_RAID1_KEEP_LOG
113596. DM_RAID1_READ_ERROR
113597. DM_RAID1_SYNC_ERROR
113598. DM_RAID1_WRITE_ERROR
113599. DM_RAID_MAGIC
113600. DM_RATR_STA_HIGH
113601. DM_RATR_STA_INIT
113602. DM_RATR_STA_LOW
113603. DM_RATR_STA_MAX
113604. DM_RATR_STA_MIDDLE
113605. DM_RATR_STA_MIDDLEHIGH
113606. DM_RATR_STA_MIDDLELOW
113607. DM_RATR_STA_ULTRALOW
113608. DM_RA_MSK_WK_CID
113609. DM_READONLY_FLAG
113610. DM_READ_MEMS
113611. DM_READ_REGS
113612. DM_REGION_HASH_H
113613. DM_REGISTER_SPACING
113614. DM_REG_ANTDIV_PARA1_11N
113615. DM_REG_ANTDIV_PARA2_11N
113616. DM_REG_ANTDIV_PARA3_11N
113617. DM_REG_ANTSEL_CTRL_11N
113618. DM_REG_ANTSEL_PATH_11N
113619. DM_REG_ANTSEL_PIN_11N
113620. DM_REG_ANT_MAPPING1_11N
113621. DM_REG_ANT_MAPPING2_11N
113622. DM_REG_ANT_TRAIN_PARA1_11N
113623. DM_REG_ANT_TRAIN_PARA2_11N
113624. DM_REG_BB_3WIRE_11N
113625. DM_REG_BB_CTRL_11N
113626. DM_REG_BB_PWR_SAV1_11N
113627. DM_REG_BB_PWR_SAV2_11N
113628. DM_REG_BB_PWR_SAV3_11N
113629. DM_REG_BB_PWR_SAV4_11N
113630. DM_REG_BB_PWR_SAV5_11N
113631. DM_REG_BB_RST_11N
113632. DM_REG_BLUETOOTH_11N
113633. DM_REG_CCK_ANTDIV_PARA1_11N
113634. DM_REG_CCK_ANTDIV_PARA2_11N
113635. DM_REG_CCK_ANTDIV_PARA3_11N
113636. DM_REG_CCK_ANTDIV_PARA4_11N
113637. DM_REG_CCK_CCA_11AC
113638. DM_REG_CCK_CCA_11N
113639. DM_REG_CCK_CCA_CNT_11N
113640. DM_REG_CCK_FA_LSB_11N
113641. DM_REG_CCK_FA_MSB_11N
113642. DM_REG_CCK_FA_RST_11N
113643. DM_REG_CCK_FILTER_PARA1_11N
113644. DM_REG_CCK_FILTER_PARA2_11N
113645. DM_REG_CCK_FILTER_PARA3_11N
113646. DM_REG_CCK_FILTER_PARA4_11N
113647. DM_REG_CCK_FILTER_PARA5_11N
113648. DM_REG_CCK_FILTER_PARA6_11N
113649. DM_REG_CCK_FILTER_PARA7_11N
113650. DM_REG_CCK_FILTER_PARA8_11N
113651. DM_REG_CCK_RPT_FORMAT_11N
113652. DM_REG_CHNBW_11N
113653. DM_REG_CONFIG_ANTA_11N
113654. DM_REG_EARLY_MODE_11N
113655. DM_REG_EDCA_BE_11N
113656. DM_REG_EDCA_BK_11N
113657. DM_REG_EDCA_VI_11N
113658. DM_REG_EDCA_VO_11N
113659. DM_REG_FPGA0_IQK_11N
113660. DM_REG_IGI_A_11AC
113661. DM_REG_IGI_A_11N
113662. DM_REG_IGI_B_11AC
113663. DM_REG_IGI_B_11N
113664. DM_REG_IQK_AGC_PTS_11N
113665. DM_REG_IQK_AGC_RSP_11N
113666. DM_REG_L1SBD_PD_CH_11N
113667. DM_REG_LNA_SWITCH_11N
113668. DM_REG_OFDM_BBON_11N
113669. DM_REG_OFDM_FA_HOLDC_11N
113670. DM_REG_OFDM_FA_RSTC_11N
113671. DM_REG_OFDM_FA_RSTD_11N
113672. DM_REG_OFDM_FA_TYPE1_11N
113673. DM_REG_OFDM_FA_TYPE2_11N
113674. DM_REG_OFDM_FA_TYPE3_11N
113675. DM_REG_OFDM_FA_TYPE4_11N
113676. DM_REG_OFDM_RFON_11N
113677. DM_REG_PATH_SWITCH_11N
113678. DM_REG_PIN_CTRL_11N
113679. DM_REG_PMPD_ANAEN_11N
113680. DM_REG_PSD_CTRL_11N
113681. DM_REG_PSD_DATA_11N
113682. DM_REG_RESP_TX_11N
113683. DM_REG_RF_0B_11N
113684. DM_REG_RF_25_11N
113685. DM_REG_RF_26_11N
113686. DM_REG_RF_27_11N
113687. DM_REG_RF_2B_11N
113688. DM_REG_RF_2C_11N
113689. DM_REG_RF_MODE_11N
113690. DM_REG_RF_PIN_11N
113691. DM_REG_RSSI_BT_11N
113692. DM_REG_RSSI_CTRL_11N
113693. DM_REG_RSSI_MONITOR_11N
113694. DM_REG_RX2RX_11N
113695. DM_REG_RXIQI_MATRIX_11N
113696. DM_REG_RXIQK_11N
113697. DM_REG_RXIQK_MATRIX_LSB_11N
113698. DM_REG_RXIQK_PI_A_11N
113699. DM_REG_RXIQK_TONE_A_11N
113700. DM_REG_RXRF_A3_11N
113701. DM_REG_RX_ANT_CTRL_11N
113702. DM_REG_RX_CCK_11N
113703. DM_REG_RX_DEFAULT_A_11N
113704. DM_REG_RX_DEFAULT_B_11N
113705. DM_REG_RX_DEFUALT_A_11N
113706. DM_REG_RX_DEFUALT_B_11N
113707. DM_REG_RX_OFDM_11N
113708. DM_REG_RX_OFF_11N
113709. DM_REG_RX_PATH_11N
113710. DM_REG_RX_WAIT_CCA_11N
113711. DM_REG_RX_WAIT_RIFS_11N
113712. DM_REG_SC_CNT_11N
113713. DM_REG_SLEEP_11N
113714. DM_REG_STANDBY_11N
113715. DM_REG_TRMUX_11N
113716. DM_REG_TX2RX_11N
113717. DM_REG_TX2TX_11N
113718. DM_REG_TXAGC_A_1_MCS32_11N
113719. DM_REG_TXAGC_A_24_54_11N
113720. DM_REG_TXAGC_A_6_18_11N
113721. DM_REG_TXAGC_A_MCS0_3_11N
113722. DM_REG_TXAGC_A_MCS12_15_11N
113723. DM_REG_TXAGC_A_MCS4_7_11N
113724. DM_REG_TXAGC_A_MCS8_11_11N
113725. DM_REG_TXIQK_11N
113726. DM_REG_TXIQK_MATRIXA_11N
113727. DM_REG_TXIQK_MATRIXA_LSB2_11N
113728. DM_REG_TXIQK_MATRIXB_11N
113729. DM_REG_TXIQK_MATRIXB_LSB2_11N
113730. DM_REG_TXIQK_MATRIX_LSB1_11N
113731. DM_REG_TXIQK_PI_A_11N
113732. DM_REG_TXIQK_TONE_A_11N
113733. DM_REG_TXPAUSE_11N
113734. DM_REG_TX_ANT_CTRL_11N
113735. DM_REG_TX_CCK_BBON_11N
113736. DM_REG_TX_CCK_RFON_11N
113737. DM_REG_T_METER_11N
113738. DM_REG_T_METER_88E_11N
113739. DM_REG_T_METER_92D_11N
113740. DM_REG_T_METER_92E_11N
113741. DM_REMOVE_ALL
113742. DM_REMOVE_ALL_CMD
113743. DM_RESERVED_MAX_IOS
113744. DM_RF_E
113745. DM_RH_CLEAN
113746. DM_RH_DIRTY
113747. DM_RH_NOSYNC
113748. DM_RH_RECOVERING
113749. DM_RQ_INTERNAL_H
113750. DM_RX_CTRL
113751. DM_RX_OVERHEAD
113752. DM_SCAN_RSSI_TH
113753. DM_SECURE_DATA_FLAG
113754. DM_SHARED_ADDR
113755. DM_SHARED_CTRL
113756. DM_SHARED_DATA
113757. DM_SKIP_BDGET_FLAG
113758. DM_SKIP_LOCKFS_FLAG
113759. DM_SM_METADATA_BLOCK_SIZE
113760. DM_SM_METADATA_MAX_BLOCKS
113761. DM_SM_METADATA_MAX_SECTORS
113762. DM_SPACE_MAP_COMMON_H
113763. DM_SPACE_MAP_METADATA_H
113764. DM_STATS_H
113765. DM_STATS_MEMORY_FACTOR
113766. DM_STATS_VMALLOC_FACTOR
113767. DM_STATUS_NOFLUSH_FLAG
113768. DM_STATUS_REPORT
113769. DM_STATUS_TABLE_FLAG
113770. DM_STA_DIG_MAX
113771. DM_STA_DIG_OFF
113772. DM_STA_DIG_ON
113773. DM_SUSPEND_FLAG
113774. DM_SUSPEND_LOCKFS_FLAG
113775. DM_SUSPEND_NOFLUSH_FLAG
113776. DM_SWAS_E
113777. DM_TABLE_CLEAR
113778. DM_TABLE_CLEAR_CMD
113779. DM_TABLE_DEPS
113780. DM_TABLE_DEPS_CMD
113781. DM_TABLE_LOAD
113782. DM_TABLE_LOAD_CMD
113783. DM_TABLE_STATUS
113784. DM_TABLE_STATUS_CMD
113785. DM_TARGET_ALWAYS_WRITEABLE
113786. DM_TARGET_IMMUTABLE
113787. DM_TARGET_INTEGRITY
113788. DM_TARGET_MSG
113789. DM_TARGET_MSG_CMD
113790. DM_TARGET_PASSES_INTEGRITY
113791. DM_TARGET_SINGLETON
113792. DM_TARGET_WILDCARD
113793. DM_TARGET_ZONED_HM
113794. DM_THIN_METADATA_H
113795. DM_TIMEOUT
113796. DM_TIMER_LOAD_MIN
113797. DM_TIMER_MAX
113798. DM_TIO_MAGIC
113799. DM_TRACKED_CHUNK_HASH
113800. DM_TRACKED_CHUNK_HASH_SIZE
113801. DM_TX_OVERHEAD
113802. DM_TYPE_BIO_BASED
113803. DM_TYPE_BYDRIVER
113804. DM_TYPE_BYFW
113805. DM_TYPE_DAX_BIO_BASED
113806. DM_TYPE_NONE
113807. DM_TYPE_NVME_BIO_BASED
113808. DM_TYPE_REQUEST_BASED
113809. DM_Type_ByDriver
113810. DM_Type_ByFW
113811. DM_Type_ByFWi
113812. DM_UEVENT_GENERATED_FLAG
113813. DM_UEVENT_H
113814. DM_UEVENT_PATH_FAILED
113815. DM_UEVENT_PATH_REINSTATED
113816. DM_ULOG_CLEAR_REGION
113817. DM_ULOG_CTR
113818. DM_ULOG_DTR
113819. DM_ULOG_FLUSH
113820. DM_ULOG_GET_REGION_SIZE
113821. DM_ULOG_GET_RESYNC_WORK
113822. DM_ULOG_GET_SYNC_COUNT
113823. DM_ULOG_IN_SYNC
113824. DM_ULOG_IS_CLEAN
113825. DM_ULOG_IS_REMOTE_RECOVERING
113826. DM_ULOG_MARK_REGION
113827. DM_ULOG_POSTSUSPEND
113828. DM_ULOG_PREALLOCED_SIZE
113829. DM_ULOG_PRESUSPEND
113830. DM_ULOG_REQUEST_MASK
113831. DM_ULOG_REQUEST_TYPE
113832. DM_ULOG_REQUEST_VERSION
113833. DM_ULOG_RESUME
113834. DM_ULOG_RETRY_TIMEOUT
113835. DM_ULOG_SET_REGION_SYNC
113836. DM_ULOG_STATUS_INFO
113837. DM_ULOG_STATUS_TABLE
113838. DM_UNBALLOON_REQUEST
113839. DM_UNBALLOON_RESPONSE
113840. DM_UUID_FLAG
113841. DM_UUID_LEN
113842. DM_VERITY_BLOCK_TYPE_DATA
113843. DM_VERITY_BLOCK_TYPE_METADATA
113844. DM_VERITY_DEFAULT_PREFETCH_SIZE
113845. DM_VERITY_ENV_LENGTH
113846. DM_VERITY_ENV_VAR_NAME
113847. DM_VERITY_FEC_BUF_MAX
113848. DM_VERITY_FEC_BUF_PREALLOC
113849. DM_VERITY_FEC_BUF_RS_BITS
113850. DM_VERITY_FEC_H
113851. DM_VERITY_FEC_MAX_RECURSION
113852. DM_VERITY_FEC_MAX_RSN
113853. DM_VERITY_FEC_MIN_RSN
113854. DM_VERITY_FEC_RSM
113855. DM_VERITY_H
113856. DM_VERITY_IS_SIG_FORCE_ENABLED
113857. DM_VERITY_MAX_CORRUPTED_ERRS
113858. DM_VERITY_MAX_LEVELS
113859. DM_VERITY_MODE_EIO
113860. DM_VERITY_MODE_LOGGING
113861. DM_VERITY_MODE_RESTART
113862. DM_VERITY_OPTS_FEC
113863. DM_VERITY_OPTS_MAX
113864. DM_VERITY_OPT_AT_MOST_ONCE
113865. DM_VERITY_OPT_FEC_BLOCKS
113866. DM_VERITY_OPT_FEC_DEV
113867. DM_VERITY_OPT_FEC_ROOTS
113868. DM_VERITY_OPT_FEC_START
113869. DM_VERITY_OPT_IGN_ZEROES
113870. DM_VERITY_OPT_LOGGING
113871. DM_VERITY_OPT_RESTART
113872. DM_VERITY_ROOT_HASH_VERIFICATION
113873. DM_VERITY_ROOT_HASH_VERIFICATION_OPTS
113874. DM_VERITY_ROOT_HASH_VERIFICATION_OPT_SIG_KEY
113875. DM_VERITY_SIG_VERIFICATION_H
113876. DM_VERITY_VERIFY_ERR
113877. DM_VERSION
113878. DM_VERSION_03_MAX
113879. DM_VERSION_1_MAX
113880. DM_VERSION_CMD
113881. DM_VERSION_EXTRA
113882. DM_VERSION_MAJOR
113883. DM_VERSION_MINOR
113884. DM_VERSION_PATCHLEVEL
113885. DM_VERSION_REQUEST
113886. DM_VERSION_RESPONSE
113887. DM_WIPE_BUFFER
113888. DM_WRITECACHE_HANDLE_HARDWARE_ERRORS
113889. DM_WRITECACHE_HAS_PMEM
113890. DM_WRITE_MEM
113891. DM_WRITE_MEMS
113892. DM_WRITE_REG
113893. DM_WRITE_REGS
113894. DM_ZONED_H
113895. DM_ZX296718_GMAC
113896. DM_ZX296718_HDE
113897. DM_ZX296718_HSIC
113898. DM_ZX296718_SAPPU
113899. DM_ZX296718_TS
113900. DM_ZX296718_USB20
113901. DM_ZX296718_USB21
113902. DM_ZX296718_USB30
113903. DM_ZX296718_VCE
113904. DM_ZX296718_VDE
113905. DM_ZX296718_VIU
113906. DM_ZX296718_VOU
113907. DM_false_ALARM_THRESH_HIGH
113908. DM_false_ALARM_THRESH_LOW
113909. DMfalseALARM_THRESH_HIGH
113910. DMfalseALARM_THRESH_LOW
113911. DNA
113912. DNAD_REG
113913. DNAME
113914. DNAME_INLINE_LEN
113915. DNAME_PATH_MAX
113916. DNAND_ALE
113917. DNAND_CEB0
113918. DNAND_CEB1
113919. DNAND_CEB2
113920. DNAND_CEB3
113921. DNAND_CLE
113922. DNAND_D0
113923. DNAND_D1
113924. DNAND_D2
113925. DNAND_D3
113926. DNAND_D4
113927. DNAND_D5
113928. DNAND_D6
113929. DNAND_D7
113930. DNAND_DQS
113931. DNAND_DQSN
113932. DNAND_RB0
113933. DNAND_RDB
113934. DNAND_RDBN
113935. DNAND_WRB
113936. DNA_MASK
113937. DNA_SHIFT
113938. DNBUFSIZE
113939. DND_DONE
113940. DND_END_OF_FRAME
113941. DND_END_OF_XFER
113942. DND_UNUSED
113943. DNET_CAPS_MASK
113944. DNET_CFG_RX_FIFO_FULL_THRES
113945. DNET_CFG_TX_FIFO_FULL_THRES
113946. DNET_FIFO_RX_CMD_AF_TH
113947. DNET_FIFO_SIZE
113948. DNET_FIFO_TX_DATA_AE_TH
113949. DNET_FIFO_TX_DATA_AF_TH
113950. DNET_HAS_DMA
113951. DNET_HAS_GIGABIT
113952. DNET_HAS_IRQ
113953. DNET_HAS_MDIO
113954. DNET_HAS_MII
113955. DNET_HAS_RMII
113956. DNET_INTERNAL_GMII_MNG_CMD_FIN
113957. DNET_INTERNAL_GMII_MNG_CTL_REG
113958. DNET_INTERNAL_GMII_MNG_DAT_REG
113959. DNET_INTERNAL_IGP_REG
113960. DNET_INTERNAL_MAC_ADDR_0_REG
113961. DNET_INTERNAL_MAC_ADDR_1_REG
113962. DNET_INTERNAL_MAC_ADDR_2_REG
113963. DNET_INTERNAL_MAX_PKT_SIZE_REG
113964. DNET_INTERNAL_MODE_FCEN
113965. DNET_INTERNAL_MODE_GBITEN
113966. DNET_INTERNAL_MODE_REG
113967. DNET_INTERNAL_MODE_RXEN
113968. DNET_INTERNAL_MODE_TXEN
113969. DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS
113970. DNET_INTERNAL_RXTX_CONTROL_DISTXFCS
113971. DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL
113972. DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP
113973. DNET_INTERNAL_RXTX_CONTROL_ENPROMISC
113974. DNET_INTERNAL_RXTX_CONTROL_REG
113975. DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST
113976. DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST
113977. DNET_INTERNAL_RXTX_CONTROL_RXPAUSE
113978. DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME
113979. DNET_INTERNAL_TX_RX_STS_REG
113980. DNET_INTERNAL_WRITE
113981. DNET_INTR_ENB
113982. DNET_INTR_ENB_GLOBAL_ENABLE
113983. DNET_INTR_ENB_RX_ERROR
113984. DNET_INTR_ENB_RX_FIFOAE
113985. DNET_INTR_ENB_RX_FIFOAF
113986. DNET_INTR_ENB_RX_FIFOERR
113987. DNET_INTR_ENB_RX_FIFOFULL
113988. DNET_INTR_ENB_RX_PKTRDY
113989. DNET_INTR_ENB_RX_SUMMARY
113990. DNET_INTR_ENB_TX_DISCFRM
113991. DNET_INTR_ENB_TX_FIFOAE
113992. DNET_INTR_ENB_TX_FIFOAF
113993. DNET_INTR_ENB_TX_FIFOFULL
113994. DNET_INTR_ENB_TX_PKTSENT
113995. DNET_INTR_ENB_TX_SUMMARY
113996. DNET_INTR_SRC
113997. DNET_INTR_SRC_PHY
113998. DNET_INTR_SRC_RX_CMDFIFOAF
113999. DNET_INTR_SRC_RX_CMDFIFOFF
114000. DNET_INTR_SRC_RX_DATAFIFOFF
114001. DNET_INTR_SRC_RX_SUMMARY
114002. DNET_INTR_SRC_TX_DISCFRM
114003. DNET_INTR_SRC_TX_FIFOAE
114004. DNET_INTR_SRC_TX_FIFOAF
114005. DNET_INTR_SRC_TX_FIFOFULL
114006. DNET_INTR_SRC_TX_PKTSENT
114007. DNET_INTR_SRC_TX_SUMMARY
114008. DNET_MACREG_ADDR
114009. DNET_MACREG_DATA
114010. DNET_PAUSE_TMR
114011. DNET_RX_BROADCAST_CNT
114012. DNET_RX_BYTE_CNT
114013. DNET_RX_CRC_ERR_CNT
114014. DNET_RX_CTL_FRM_CNT
114015. DNET_RX_DATA_FIFO
114016. DNET_RX_DRIB_NIB_CNT
114017. DNET_RX_FIFO_TH
114018. DNET_RX_FIFO_WCNT
114019. DNET_RX_FRAMES_CNT
114020. DNET_RX_IPG_VIOL_CNT
114021. DNET_RX_LEN_CHK_ERR_CNT
114022. DNET_RX_LEN_FIFO
114023. DNET_RX_LNG_FRM_CNT
114024. DNET_RX_MULTICAST_CNT
114025. DNET_RX_OK_PKT_CNT
114026. DNET_RX_PAUSE_FRM_CNT
114027. DNET_RX_PKT_IGNR_CNT
114028. DNET_RX_PRE_SHRINK_CNT
114029. DNET_RX_SHRT_FRM_CNT
114030. DNET_RX_STATUS
114031. DNET_RX_UNSUP_OPCD_CNT
114032. DNET_RX_VLAN_TAG_CNT
114033. DNET_SYS_CTL
114034. DNET_SYS_CTL_IGNORENEXTPKT
114035. DNET_SYS_CTL_RXFIFOFLUSH
114036. DNET_SYS_CTL_SENDPAUSE
114037. DNET_SYS_CTL_TXFIFOFLUSH
114038. DNET_TX_BAD_FCS_CNT
114039. DNET_TX_BRDCAST_CNT
114040. DNET_TX_BYTE_CNT
114041. DNET_TX_DATA_FIFO
114042. DNET_TX_FIFO_TH
114043. DNET_TX_FIFO_WCNT
114044. DNET_TX_FRAMES_CNT
114045. DNET_TX_JUMBO_CNT
114046. DNET_TX_LEN_FIFO
114047. DNET_TX_MULTICAST_CNT
114048. DNET_TX_PAUSE_FRM_CNT
114049. DNET_TX_STATUS
114050. DNET_TX_STATUS_FIFO_ALMOST_EMPTY
114051. DNET_TX_STATUS_FIFO_ALMOST_FULL
114052. DNET_TX_UNICAST_CNT
114053. DNET_TX_VLAN_TAG_CNT
114054. DNET_VERCAPS
114055. DNLD_BOOTCMD_SENT
114056. DNLD_CMD_SENT
114057. DNLD_DATA_SENT
114058. DNLD_RES_RECEIVED
114059. DNLD_STATE
114060. DNLINK_TRAFFIC
114061. DNLV2PA
114062. DNLV2PA_MASK
114063. DNLV2PA_SHIFT
114064. DNO
114065. DNODE_MAGIC
114066. DNODE_RD_AHEAD
114067. DNOTIFY_ALL_EVENTS
114068. DNPROTO_EVL
114069. DNPROTO_EVR
114070. DNPROTO_NML
114071. DNPROTO_NSP
114072. DNPROTO_NSPT
114073. DNPROTO_ROU
114074. DNRMG_L1_GROUP
114075. DNRMG_L2_GROUP
114076. DNRNG_NLGRP_L1
114077. DNRNG_NLGRP_L2
114078. DNRNG_NLGRP_MAX
114079. DNRNG_NLGRP_NONE
114080. DNS
114081. DNS323C_GPIO_FAN_BIT0
114082. DNS323C_GPIO_FAN_BIT1
114083. DNS323C_GPIO_KEY_POWER
114084. DNS323C_GPIO_LED_LEFT_AMBER
114085. DNS323C_GPIO_LED_POWER
114086. DNS323C_GPIO_LED_RIGHT_AMBER
114087. DNS323C_GPIO_POWER_OFF
114088. DNS323_GPIO_KEY_POWER
114089. DNS323_GPIO_KEY_RESET
114090. DNS323_GPIO_LED_LEFT_AMBER
114091. DNS323_GPIO_LED_POWER1
114092. DNS323_GPIO_LED_POWER2
114093. DNS323_GPIO_LED_RIGHT_AMBER
114094. DNS323_GPIO_OVERTEMP
114095. DNS323_GPIO_POWER_OFF
114096. DNS323_GPIO_RTC
114097. DNS323_GPIO_SYSTEM_UP
114098. DNS323_NOR_BOOT_BASE
114099. DNS323_NOR_BOOT_SIZE
114100. DNS323_REV_A1
114101. DNS323_REV_B1
114102. DNS323_REV_C1
114103. DNSOFF
114104. DNSTH
114105. DNS_ADDRESS_IS_IPV4
114106. DNS_ADDRESS_IS_IPV6
114107. DNS_DELAY
114108. DNS_ERRORNO_OPTION
114109. DNS_LOOKUP_BAD
114110. DNS_LOOKUP_GOOD
114111. DNS_LOOKUP_GOOD_WITH_BAD
114112. DNS_LOOKUP_GOT_LOCAL_FAILURE
114113. DNS_LOOKUP_GOT_NOT_FOUND
114114. DNS_LOOKUP_GOT_NS_FAILURE
114115. DNS_LOOKUP_GOT_TEMP_FAILURE
114116. DNS_LOOKUP_NOT_DONE
114117. DNS_PAYLOAD_IS_SERVER_LIST
114118. DNS_RECORD_FROM_CONFIG
114119. DNS_RECORD_FROM_DNS_A
114120. DNS_RECORD_FROM_DNS_AFSDB
114121. DNS_RECORD_FROM_DNS_SRV
114122. DNS_RECORD_FROM_NSS
114123. DNS_RECORD_UNAVAILABLE
114124. DNS_SERVER_PROTOCOL_TCP
114125. DNS_SERVER_PROTOCOL_UDP
114126. DNS_SERVER_PROTOCOL_UNSPECIFIED
114127. DNV
114128. DNV_ASYMSHIFT
114129. DNV_COMMUNITY
114130. DNV_DMA_CHAN_OFFSET
114131. DNV_GPI_IE
114132. DNV_GPI_IS
114133. DNV_GPP
114134. DNV_HOSTSW_OWN
114135. DNV_LL_MASK
114136. DNV_LL_SHIFT
114137. DNV_MAX_DIMMS
114138. DNV_MCHBAR_SIZE
114139. DNV_NUM_CHANNELS
114140. DNV_PADCFGLOCK
114141. DNV_PAD_OWN
114142. DNV_SB_PORT_SIZE
114143. DNV_SYS_MASK
114144. DNV_SYS_SHIFT
114145. DN_ACCESS
114146. DN_ADDL
114147. DN_ASCBUF_LEN
114148. DN_ATTRIB
114149. DN_BYPASS_AGC_I2C
114150. DN_CACHE_SIZE
114151. DN_CAP_RFLPF
114152. DN_CC
114153. DN_CD
114154. DN_CI
114155. DN_CL
114156. DN_CN
114157. DN_COMPLETE
114158. DN_CR
114159. DN_CREATE
114160. DN_DELETE
114161. DN_DEV_BCAST
114162. DN_DEV_LIST_SIZE
114163. DN_DEV_MPOINT
114164. DN_DEV_PARMS_OFFSET
114165. DN_DEV_S_CR
114166. DN_DEV_S_DS
114167. DN_DEV_S_HA
114168. DN_DEV_S_OF
114169. DN_DEV_S_RC
114170. DN_DEV_S_RI
114171. DN_DEV_S_RU
114172. DN_DEV_S_RV
114173. DN_DEV_UCAST
114174. DN_DI
114175. DN_DIC
114176. DN_DN
114177. DN_DONTSEND
114178. DN_DR
114179. DN_DRC
114180. DN_EN_VHFUHFBAR
114181. DN_FIB_INFO
114182. DN_FIB_RES_DEV
114183. DN_FIB_RES_GW
114184. DN_FIB_RES_NH
114185. DN_FIB_RES_OIF
114186. DN_FIB_RES_PREFSRC
114187. DN_FIB_RES_RESET
114188. DN_FIB_SCAN
114189. DN_FIB_SCAN_KEY
114190. DN_FIB_TABLE_HASHSZ
114191. DN_GAIN_ADJUST
114192. DN_HASHBITS
114193. DN_HASHMAX
114194. DN_IFREQ_SIZE
114195. DN_IQTNBUF_AMP
114196. DN_IQTNGNBFBIAS_BST
114197. DN_IQTN_AMP_CUT
114198. DN_LD_CARD_RDY
114199. DN_LD_CMD_PORT_HOST_INT_STATUS
114200. DN_LD_HOST_INT_MASK
114201. DN_LD_HOST_INT_STATUS
114202. DN_MAXACCL
114203. DN_MAXADDL
114204. DN_MAXALIASL
114205. DN_MAXNODEL
114206. DN_MAXOBJL
114207. DN_MAXOPTL
114208. DN_MAX_DIVISOR
114209. DN_MAX_NSP_DATA_HEADER
114210. DN_MENUVER_ACC
114211. DN_MENUVER_PRX
114212. DN_MENUVER_UIC
114213. DN_MENUVER_USR
114214. DN_MODIFY
114215. DN_MULTISHOT
114216. DN_NC
114217. DN_NDFLAG_P3
114218. DN_NDFLAG_R1
114219. DN_NDFLAG_R2
114220. DN_NOCHANGE
114221. DN_NR
114222. DN_O
114223. DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK
114224. DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK
114225. DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT
114226. DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
114227. DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK
114228. DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
114229. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
114230. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK
114231. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
114232. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
114233. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK
114234. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
114235. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK
114236. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT
114237. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
114238. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK
114239. DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
114240. DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK
114241. DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK
114242. DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
114243. DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
114244. DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK
114245. DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
114246. DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK
114247. DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK
114248. DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT
114249. DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
114250. DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK
114251. DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
114252. DN_PCIE_RESERVED__PCIE_RESERVED_MASK
114253. DN_PCIE_RESERVED__PCIE_RESERVED__MASK
114254. DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT
114255. DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
114256. DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK
114257. DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
114258. DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK
114259. DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK
114260. DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
114261. DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK
114262. DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK
114263. DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT
114264. DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK
114265. DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK
114266. DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT
114267. DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK
114268. DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK
114269. DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT
114270. DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK
114271. DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK
114272. DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT
114273. DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK
114274. DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK
114275. DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT
114276. DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
114277. DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK
114278. DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
114279. DN_POLY
114280. DN_RENAME
114281. DN_RFGAIN
114282. DN_RJ
114283. DN_RT_CNTL_MSK
114284. DN_RT_F_IE
114285. DN_RT_F_PF
114286. DN_RT_F_PID
114287. DN_RT_F_RQR
114288. DN_RT_F_RTS
114289. DN_RT_F_VER
114290. DN_RT_INFO_BLKR
114291. DN_RT_INFO_ENDN
114292. DN_RT_INFO_L1RT
114293. DN_RT_INFO_L2RT
114294. DN_RT_INFO_NOML
114295. DN_RT_INFO_RJCT
114296. DN_RT_INFO_TYPE
114297. DN_RT_INFO_VERI
114298. DN_RT_INFO_VFLD
114299. DN_RT_PKT_CNTL
114300. DN_RT_PKT_EEDH
114301. DN_RT_PKT_ERTH
114302. DN_RT_PKT_HELO
114303. DN_RT_PKT_INIT
114304. DN_RT_PKT_L1RT
114305. DN_RT_PKT_L2RT
114306. DN_RT_PKT_LONG
114307. DN_RT_PKT_MSK
114308. DN_RT_PKT_SHORT
114309. DN_RT_PKT_VERI
114310. DN_RUN
114311. DN_SEL_FREQ
114312. DN_SEND
114313. DN_SK
114314. DN_SKB_CB
114315. DN_SK_HASH_MASK
114316. DN_SK_HASH_SHIFT
114317. DN_SK_HASH_SIZE
114318. DN_S_ACCESSED
114319. DN_S_ZOMBIE
114320. DO
114321. DO01_ACTIVE_MODE
114322. DO0_ACTIVE_MODE
114323. DO1
114324. DO16
114325. DO1_ACTIVE_MODE
114326. DO2
114327. DO4
114328. DO8
114329. DOADR_E
114330. DOASYNC
114331. DOCK_CALL_FIXUP
114332. DOCK_CALL_HANDLER
114333. DOCK_CALL_UEVENT
114334. DOCK_DOCKING
114335. DOCK_EVENT
114336. DOCK_FILENAME
114337. DOCK_IS_ATA
114338. DOCK_IS_BAT
114339. DOCK_IS_DOCK
114340. DOCK_MODE_FLAG
114341. DOCK_UNDOCKING
114342. DOCMD1_E
114343. DOCMD2_E
114344. DOC_ADDR_BLOCK_SHIFT
114345. DOC_ADDR_PAGE_MASK
114346. DOC_ASICMODE
114347. DOC_ASICMODECONFIRM
114348. DOC_ASICMODE_BDETCT_RESET
114349. DOC_ASICMODE_MDWREN
114350. DOC_ASICMODE_NORMAL
114351. DOC_ASICMODE_POWERDOWN
114352. DOC_ASICMODE_RAM_WE
114353. DOC_ASICMODE_RESET
114354. DOC_ASICMODE_RSTIN_RESET
114355. DOC_BCH_HW_ECC
114356. DOC_BUSLOCK
114357. DOC_CHIPID
114358. DOC_CHIPID_G3
114359. DOC_CHIPID_INV
114360. DOC_CMD_ERASECYCLE2
114361. DOC_CMD_FAST_MODE
114362. DOC_CMD_PAGE_SIZE_532
114363. DOC_CMD_PLANES_STATUS
114364. DOC_CMD_PROG_BLOCK_ADDR
114365. DOC_CMD_PROG_CYCLE1
114366. DOC_CMD_PROG_CYCLE2
114367. DOC_CMD_PROG_CYCLE3
114368. DOC_CMD_READ_ALL_PLANES
114369. DOC_CMD_READ_FLASH
114370. DOC_CMD_READ_PLANE1
114371. DOC_CMD_READ_PLANE2
114372. DOC_CMD_READ_STATUS
114373. DOC_CMD_RELIABLE_MODE
114374. DOC_CMD_RESET
114375. DOC_CMD_SET_ADDR_READ
114376. DOC_CONFIGURATION
114377. DOC_CONF_IF_CFG
114378. DOC_CONF_MAX_ID_MASK
114379. DOC_CONF_VCCQ_3V
114380. DOC_CTRL_CE
114381. DOC_CTRL_FLASHREADY
114382. DOC_CTRL_PROTECTION_ERROR
114383. DOC_CTRL_SEQUENCE_ERROR
114384. DOC_CTRL_UNKNOWN_BITS
114385. DOC_CTRL_VIOLATION
114386. DOC_ChipID_Doc2k
114387. DOC_ChipID_Doc2kTSOP
114388. DOC_ChipID_DocMil
114389. DOC_ChipID_DocMilPlus16
114390. DOC_ChipID_DocMilPlus32
114391. DOC_DATAEND
114392. DOC_DEVICESELECT
114393. DOC_DPS0_ADDRHIGH
114394. DOC_DPS0_ADDRLOW
114395. DOC_DPS0_KEY
114396. DOC_DPS0_STATUS
114397. DOC_DPS1_ADDRHIGH
114398. DOC_DPS1_ADDRLOW
114399. DOC_DPS1_KEY
114400. DOC_DPS1_STATUS
114401. DOC_DPS_HW_LOCK_ENABLED
114402. DOC_DPS_KEY_OK
114403. DOC_DPS_OTP_PROTECTED
114404. DOC_DPS_READ_PROTECTED
114405. DOC_DPS_WRITE_PROTECTED
114406. DOC_ECCCONF0
114407. DOC_ECCCONF0_AUTO_ECC_ENABLE
114408. DOC_ECCCONF0_BCH_ENABLE
114409. DOC_ECCCONF0_DATA_BYTES_MASK
114410. DOC_ECCCONF0_HAMMING_ENABLE
114411. DOC_ECCCONF0_READ_MODE
114412. DOC_ECCCONF0_WRITE_MODE
114413. DOC_ECCCONF1
114414. DOC_ECCCONF1_BCH_SYNDROM_ERR
114415. DOC_ECCCONF1_HAMMING_BITS_MASK
114416. DOC_ECCCONF1_PAGE_IS_WRITTEN
114417. DOC_ECCCONF1_UNKOWN1
114418. DOC_ECCCONF1_UNKOWN3
114419. DOC_ECCPRESET
114420. DOC_ECC_BCH_COVERED_BYTES
114421. DOC_ECC_BCH_M
114422. DOC_ECC_BCH_PRIMPOLY
114423. DOC_ECC_BCH_SIZE
114424. DOC_ECC_BCH_T
114425. DOC_ECC_BCH_TOTAL_BYTES
114426. DOC_ECC_DIS
114427. DOC_ECC_EN
114428. DOC_ECC_ERROR
114429. DOC_ECC_IGNORE
114430. DOC_ECC_RESET
114431. DOC_ECC_RESV
114432. DOC_ECC_RW
114433. DOC_ECC__EN
114434. DOC_ENDIANCONTROL
114435. DOC_ERASE_MARK
114436. DOC_FLASHADDRESS
114437. DOC_FLASHCOMMAND
114438. DOC_FLASHCONTROL
114439. DOC_FLASHSEQUENCE
114440. DOC_FLASH_BANK
114441. DOC_FLASH_CE
114442. DOC_FLASH_WP
114443. DOC_HAMMINGPARITY
114444. DOC_INTERRUPTCONTROL
114445. DOC_INTERRUPTSTATUS
114446. DOC_IOREMAP_LEN
114447. DOC_IOSPACE_DATA
114448. DOC_IOSPACE_IPL
114449. DOC_IOSPACE_SIZE
114450. DOC_LAYOUT_BLOCK_BBT
114451. DOC_LAYOUT_BLOCK_FIRST_DATA
114452. DOC_LAYOUT_BLOCK_OTP
114453. DOC_LAYOUT_BLOCK_SIZE
114454. DOC_LAYOUT_DPS_KEY_LENGTH
114455. DOC_LAYOUT_NBPLANES
114456. DOC_LAYOUT_OOB_BCH_OFS
114457. DOC_LAYOUT_OOB_BCH_SZ
114458. DOC_LAYOUT_OOB_HAMMING_OFS
114459. DOC_LAYOUT_OOB_HAMMING_SZ
114460. DOC_LAYOUT_OOB_PAGEINFO_OFS
114461. DOC_LAYOUT_OOB_PAGEINFO_SZ
114462. DOC_LAYOUT_OOB_SIZE
114463. DOC_LAYOUT_OOB_UNUSED_OFS
114464. DOC_LAYOUT_OOB_UNUSED_SZ
114465. DOC_LAYOUT_PAGES_PER_BLOCK
114466. DOC_LAYOUT_PAGE_BBT
114467. DOC_LAYOUT_PAGE_OOB_SIZE
114468. DOC_LAYOUT_PAGE_SIZE
114469. DOC_LAYOUT_WEAR_OFFSET
114470. DOC_LAYOUT_WEAR_SIZE
114471. DOC_MAX_NBFLOORS
114472. DOC_MODE_BDECT
114473. DOC_MODE_CLR_ERR
114474. DOC_MODE_MDWREN
114475. DOC_MODE_NORMAL
114476. DOC_MODE_RESERVED1
114477. DOC_MODE_RESERVED2
114478. DOC_MODE_RESET
114479. DOC_MODE_RST_LAT
114480. DOC_NOP
114481. DOC_PLANES_STATUS_FAIL
114482. DOC_PLANES_STATUS_PLANE0_KO
114483. DOC_PLANES_STATUS_PLANE1_KO
114484. DOC_POWERDOWN_READY
114485. DOC_POWERMODE
114486. DOC_PROTECTION
114487. DOC_PROTECT_CUSTOMER_OTP_LOCK
114488. DOC_PROTECT_FOUNDRY_OTP_LOCK
114489. DOC_PROTECT_IPL_DOWNLOAD_LOCK
114490. DOC_PROTECT_LOCK_INPUT
114491. DOC_PROTECT_PROTECTION_ENABLED
114492. DOC_PROTECT_PROTECTION_ERROR
114493. DOC_PROTECT_STICKY_LOCK
114494. DOC_READADDRESS
114495. DOC_READADDR_ADDR_MASK
114496. DOC_READADDR_INC
114497. DOC_READADDR_ONE_BYTE
114498. DOC_SEQ_ERASE
114499. DOC_SEQ_PAGE_SETUP
114500. DOC_SEQ_PAGE_SIZE_532
114501. DOC_SEQ_PLANES_STATUS
114502. DOC_SEQ_READ
114503. DOC_SEQ_RESET
114504. DOC_SEQ_SET_FASTMODE
114505. DOC_SEQ_SET_PLANE1
114506. DOC_SEQ_SET_PLANE2
114507. DOC_SEQ_SET_RELIABLEMODE
114508. DOC_TEST
114509. DOC_TOGGLE_BIT
114510. DODMSK
114511. DODMSK_BLNK_LVL
114512. DODMSK_MASK_B
114513. DODMSK_MASK_G
114514. DODMSK_MASK_LVL
114515. DODMSK_MASK_R
114516. DOEPCTL
114517. DOEPCTL0
114518. DOEPDMA
114519. DOEPINT
114520. DOEPMSK
114521. DOEPMSK_AHBERRMSK
114522. DOEPMSK_BACK2BACKSETUP
114523. DOEPMSK_BNAMSK
114524. DOEPMSK_EPDISBLDMSK
114525. DOEPMSK_OUTTKNEPDISMSK
114526. DOEPMSK_SETUPMSK
114527. DOEPMSK_STSPHSERCVDMSK
114528. DOEPMSK_XFERCOMPLMSK
114529. DOEPTSIZ
114530. DOEPTSIZ0
114531. DOEPTSIZ0_PKTCNT
114532. DOEPTSIZ0_SUPCNT
114533. DOEPTSIZ0_SUPCNT_LIMIT
114534. DOEPTSIZ0_SUPCNT_MASK
114535. DOEPTSIZ0_SUPCNT_SHIFT
114536. DOEPTSIZ0_XFERSIZE_MASK
114537. DOEPTSIZ0_XFERSIZE_SHIFT
114538. DOESTRAP
114539. DOFLR
114540. DOFLR_CDEFL0
114541. DOFLR_CDEFL1
114542. DOFLR_CODE
114543. DOFLR_DISPFL0
114544. DOFLR_DISPFL1
114545. DOFLR_HSYCFL0
114546. DOFLR_HSYCFL1
114547. DOFLR_ODDFL0
114548. DOFLR_ODDFL1
114549. DOFLR_RGBFL0
114550. DOFLR_RGBFL1
114551. DOFLR_VSYCFL0
114552. DOFLR_VSYCFL1
114553. DOIO_ALLOW_SUSPEND
114554. DOIO_DENY_PREFETCH
114555. DOIO_SUPPRESS_INTER
114556. DOLBY_BYPASS_EN
114557. DOLBY_CORE2A_SWAP_CTRL1
114558. DOLBY_CORE2A_SWAP_CTRL2
114559. DOLBY_PATH_CTRL
114560. DOLBY_VISION_DISABLED
114561. DOLBY_VISION_ENABLE
114562. DOLBY_VISION_ENABLED
114563. DOLPHIN_COUNT_PER_ELECTRODE
114564. DOLPHIN_PROFILE_XOFFSET
114565. DOLPHIN_PROFILE_YOFFSET
114566. DOMAIN
114567. DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK
114568. DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT
114569. DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK
114570. DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT
114571. DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK
114572. DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT
114573. DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK
114574. DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT
114575. DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON_MASK
114576. DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON__SHIFT
114577. DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE_MASK
114578. DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE__SHIFT
114579. DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE_MASK
114580. DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE__SHIFT
114581. DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS_MASK
114582. DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS__SHIFT
114583. DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON_MASK
114584. DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON__SHIFT
114585. DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE_MASK
114586. DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE__SHIFT
114587. DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE_MASK
114588. DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE__SHIFT
114589. DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS_MASK
114590. DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS__SHIFT
114591. DOMAIN12_PG_CONFIG__DOMAIN12_POWER_FORCEON_MASK
114592. DOMAIN12_PG_CONFIG__DOMAIN12_POWER_FORCEON__SHIFT
114593. DOMAIN12_PG_CONFIG__DOMAIN12_POWER_GATE_MASK
114594. DOMAIN12_PG_CONFIG__DOMAIN12_POWER_GATE__SHIFT
114595. DOMAIN12_PG_STATUS__DOMAIN12_DESIRED_PWR_STATE_MASK
114596. DOMAIN12_PG_STATUS__DOMAIN12_DESIRED_PWR_STATE__SHIFT
114597. DOMAIN12_PG_STATUS__DOMAIN12_PGFSM_PWR_STATUS_MASK
114598. DOMAIN12_PG_STATUS__DOMAIN12_PGFSM_PWR_STATUS__SHIFT
114599. DOMAIN13_PG_CONFIG__DOMAIN13_POWER_FORCEON_MASK
114600. DOMAIN13_PG_CONFIG__DOMAIN13_POWER_FORCEON__SHIFT
114601. DOMAIN13_PG_CONFIG__DOMAIN13_POWER_GATE_MASK
114602. DOMAIN13_PG_CONFIG__DOMAIN13_POWER_GATE__SHIFT
114603. DOMAIN13_PG_STATUS__DOMAIN13_DESIRED_PWR_STATE_MASK
114604. DOMAIN13_PG_STATUS__DOMAIN13_DESIRED_PWR_STATE__SHIFT
114605. DOMAIN13_PG_STATUS__DOMAIN13_PGFSM_PWR_STATUS_MASK
114606. DOMAIN13_PG_STATUS__DOMAIN13_PGFSM_PWR_STATUS__SHIFT
114607. DOMAIN14_PG_CONFIG__DOMAIN14_POWER_FORCEON_MASK
114608. DOMAIN14_PG_CONFIG__DOMAIN14_POWER_FORCEON__SHIFT
114609. DOMAIN14_PG_CONFIG__DOMAIN14_POWER_GATE_MASK
114610. DOMAIN14_PG_CONFIG__DOMAIN14_POWER_GATE__SHIFT
114611. DOMAIN14_PG_STATUS__DOMAIN14_DESIRED_PWR_STATE_MASK
114612. DOMAIN14_PG_STATUS__DOMAIN14_DESIRED_PWR_STATE__SHIFT
114613. DOMAIN14_PG_STATUS__DOMAIN14_PGFSM_PWR_STATUS_MASK
114614. DOMAIN14_PG_STATUS__DOMAIN14_PGFSM_PWR_STATUS__SHIFT
114615. DOMAIN15_PG_CONFIG__DOMAIN15_POWER_FORCEON_MASK
114616. DOMAIN15_PG_CONFIG__DOMAIN15_POWER_FORCEON__SHIFT
114617. DOMAIN15_PG_CONFIG__DOMAIN15_POWER_GATE_MASK
114618. DOMAIN15_PG_CONFIG__DOMAIN15_POWER_GATE__SHIFT
114619. DOMAIN15_PG_STATUS__DOMAIN15_DESIRED_PWR_STATE_MASK
114620. DOMAIN15_PG_STATUS__DOMAIN15_DESIRED_PWR_STATE__SHIFT
114621. DOMAIN15_PG_STATUS__DOMAIN15_PGFSM_PWR_STATUS_MASK
114622. DOMAIN15_PG_STATUS__DOMAIN15_PGFSM_PWR_STATUS__SHIFT
114623. DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK
114624. DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT
114625. DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK
114626. DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT
114627. DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK
114628. DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT
114629. DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK
114630. DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT
114631. DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK
114632. DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT
114633. DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK
114634. DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT
114635. DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK
114636. DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT
114637. DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK
114638. DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT
114639. DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK
114640. DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT
114641. DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK
114642. DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT
114643. DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK
114644. DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT
114645. DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK
114646. DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT
114647. DOMAIN19_PG_CONFIG__DOMAIN19_POWER_FORCEON_MASK
114648. DOMAIN19_PG_CONFIG__DOMAIN19_POWER_FORCEON__SHIFT
114649. DOMAIN19_PG_CONFIG__DOMAIN19_POWER_GATE_MASK
114650. DOMAIN19_PG_CONFIG__DOMAIN19_POWER_GATE__SHIFT
114651. DOMAIN19_PG_STATUS__DOMAIN19_DESIRED_PWR_STATE_MASK
114652. DOMAIN19_PG_STATUS__DOMAIN19_DESIRED_PWR_STATE__SHIFT
114653. DOMAIN19_PG_STATUS__DOMAIN19_PGFSM_PWR_STATUS_MASK
114654. DOMAIN19_PG_STATUS__DOMAIN19_PGFSM_PWR_STATUS__SHIFT
114655. DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK
114656. DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT
114657. DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK
114658. DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT
114659. DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK
114660. DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT
114661. DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK
114662. DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT
114663. DOMAIN20_PG_CONFIG__DOMAIN20_POWER_FORCEON_MASK
114664. DOMAIN20_PG_CONFIG__DOMAIN20_POWER_FORCEON__SHIFT
114665. DOMAIN20_PG_CONFIG__DOMAIN20_POWER_GATE_MASK
114666. DOMAIN20_PG_CONFIG__DOMAIN20_POWER_GATE__SHIFT
114667. DOMAIN20_PG_STATUS__DOMAIN20_DESIRED_PWR_STATE_MASK
114668. DOMAIN20_PG_STATUS__DOMAIN20_DESIRED_PWR_STATE__SHIFT
114669. DOMAIN20_PG_STATUS__DOMAIN20_PGFSM_PWR_STATUS_MASK
114670. DOMAIN20_PG_STATUS__DOMAIN20_PGFSM_PWR_STATUS__SHIFT
114671. DOMAIN21_PG_CONFIG__DOMAIN21_POWER_FORCEON_MASK
114672. DOMAIN21_PG_CONFIG__DOMAIN21_POWER_FORCEON__SHIFT
114673. DOMAIN21_PG_CONFIG__DOMAIN21_POWER_GATE_MASK
114674. DOMAIN21_PG_CONFIG__DOMAIN21_POWER_GATE__SHIFT
114675. DOMAIN21_PG_STATUS__DOMAIN21_DESIRED_PWR_STATE_MASK
114676. DOMAIN21_PG_STATUS__DOMAIN21_DESIRED_PWR_STATE__SHIFT
114677. DOMAIN21_PG_STATUS__DOMAIN21_PGFSM_PWR_STATUS_MASK
114678. DOMAIN21_PG_STATUS__DOMAIN21_PGFSM_PWR_STATUS__SHIFT
114679. DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK
114680. DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT
114681. DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK
114682. DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT
114683. DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK
114684. DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT
114685. DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK
114686. DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT
114687. DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK
114688. DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT
114689. DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK
114690. DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT
114691. DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK
114692. DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT
114693. DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK
114694. DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT
114695. DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK
114696. DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT
114697. DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK
114698. DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT
114699. DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK
114700. DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT
114701. DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK
114702. DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT
114703. DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK
114704. DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT
114705. DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK
114706. DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT
114707. DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK
114708. DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT
114709. DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK
114710. DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT
114711. DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK
114712. DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT
114713. DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK
114714. DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT
114715. DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK
114716. DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT
114717. DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK
114718. DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT
114719. DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK
114720. DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT
114721. DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK
114722. DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT
114723. DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK
114724. DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT
114725. DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK
114726. DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT
114727. DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON_MASK
114728. DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON__SHIFT
114729. DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE_MASK
114730. DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE__SHIFT
114731. DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE_MASK
114732. DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE__SHIFT
114733. DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS_MASK
114734. DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS__SHIFT
114735. DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON_MASK
114736. DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON__SHIFT
114737. DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE_MASK
114738. DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE__SHIFT
114739. DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE_MASK
114740. DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE__SHIFT
114741. DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS_MASK
114742. DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS__SHIFT
114743. DOMAIN_ALIAS_RID_ACCOUNT_OPS
114744. DOMAIN_ALIAS_RID_ADMINS
114745. DOMAIN_ALIAS_RID_BACKUP_OPS
114746. DOMAIN_ALIAS_RID_GUESTS
114747. DOMAIN_ALIAS_RID_POWER_USERS
114748. DOMAIN_ALIAS_RID_PREW2KCOMPACCESS
114749. DOMAIN_ALIAS_RID_PRINT_OPS
114750. DOMAIN_ALIAS_RID_RAS_SERVERS
114751. DOMAIN_ALIAS_RID_REPLICATOR
114752. DOMAIN_ALIAS_RID_SYSTEM_OPS
114753. DOMAIN_ALIAS_RID_USERS
114754. DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
114755. DOMAIN_ATTR_FSL_PAMUV1
114756. DOMAIN_ATTR_FSL_PAMU_ENABLE
114757. DOMAIN_ATTR_FSL_PAMU_STASH
114758. DOMAIN_ATTR_GEOMETRY
114759. DOMAIN_ATTR_MAX
114760. DOMAIN_ATTR_NESTING
114761. DOMAIN_ATTR_PAGING
114762. DOMAIN_ATTR_WINDOWS
114763. DOMAIN_BUS_ANY
114764. DOMAIN_BUS_FSL_MC_MSI
114765. DOMAIN_BUS_GENERIC_MSI
114766. DOMAIN_BUS_IPI
114767. DOMAIN_BUS_NEXUS
114768. DOMAIN_BUS_PCI_MSI
114769. DOMAIN_BUS_PLATFORM_MSI
114770. DOMAIN_BUS_TI_SCI_INTA_MSI
114771. DOMAIN_BUS_WIRED
114772. DOMAIN_CLIENT
114773. DOMAIN_COORD_TYPE_HW_ALL
114774. DOMAIN_COORD_TYPE_SW_ALL
114775. DOMAIN_COORD_TYPE_SW_ANY
114776. DOMAIN_EN
114777. DOMAIN_ETSI
114778. DOMAIN_FCC
114779. DOMAIN_FLAG_LOSE_CHILDREN
114780. DOMAIN_FLAG_STATIC_IDENTITY
114781. DOMAIN_FRANCE
114782. DOMAIN_GROUP_RID_ADMINS
114783. DOMAIN_GROUP_RID_CERT_ADMINS
114784. DOMAIN_GROUP_RID_COMPUTERS
114785. DOMAIN_GROUP_RID_CONTROLLERS
114786. DOMAIN_GROUP_RID_ENTERPRISE_ADMINS
114787. DOMAIN_GROUP_RID_GUESTS
114788. DOMAIN_GROUP_RID_POLICY_ADMINS
114789. DOMAIN_GROUP_RID_SCHEMA_ADMINS
114790. DOMAIN_GROUP_RID_USERS
114791. DOMAIN_IC
114792. DOMAIN_IO
114793. DOMAIN_ISRAEL
114794. DOMAIN_KERNEL
114795. DOMAIN_LEN
114796. DOMAIN_M
114797. DOMAIN_MANAGER
114798. DOMAIN_MAX
114799. DOMAIN_MAX_ADDR
114800. DOMAIN_MAX_PFN
114801. DOMAIN_MKK
114802. DOMAIN_MKK1
114803. DOMAIN_MKK2
114804. DOMAIN_MKK3
114805. DOMAIN_NOACCESS
114806. DOMAIN_OUTER_SHAREABLE
114807. DOMAIN_PX30
114808. DOMAIN_RK3036
114809. DOMAIN_RK3288
114810. DOMAIN_RK3328
114811. DOMAIN_RK3368
114812. DOMAIN_RK3399
114813. DOMAIN_SPA
114814. DOMAIN_SPAIN
114815. DOMAIN_STATE_BIOS_LOCKED
114816. DOMAIN_STATE_INACTIVE
114817. DOMAIN_STATE_POWER_LIMIT_SET
114818. DOMAIN_USER
114819. DOMAIN_USER_RID_ADMIN
114820. DOMAIN_USER_RID_GUEST
114821. DOMAIN_USER_RID_KRBTGT
114822. DOMAIN_VAPE
114823. DOMAIN_VECTORS
114824. DOMD
114825. DOMID_COW
114826. DOMID_FIRST_RESERVED
114827. DOMID_IDLE
114828. DOMID_INVALID
114829. DOMID_IO
114830. DOMID_SELF
114831. DOMID_XEN
114832. DOMNAME_LENGTH
114833. DOM_MSTR
114834. DONE
114835. DONELISTEND
114836. DONELISTSIZE_1024ELEM
114837. DONELISTSIZE_128ELEM
114838. DONELISTSIZE_16384ELEM
114839. DONELISTSIZE_16ELEM
114840. DONELISTSIZE_2048ELEM
114841. DONELISTSIZE_256ELEM
114842. DONELISTSIZE_32ELEM
114843. DONELISTSIZE_4096ELEM
114844. DONELISTSIZE_512ELEM
114845. DONELISTSIZE_64ELEM
114846. DONELISTSIZE_8192ELEM
114847. DONELISTSIZE_8ELEM
114848. DONELISTSIZE_MASK
114849. DONE_FIFO_HIWATER
114850. DONE_FLG
114851. DONE_INTERRUPT_ENABLE
114852. DONE_IRQ
114853. DONE_IRQ_0_3
114854. DONE_IRQ_4_7
114855. DONE_IRQ_EN
114856. DONE_Q_SIZE
114857. DONE_READ
114858. DONE_READ_TO
114859. DONE_RECEIVED_TIME
114860. DONE_REG
114861. DONE_SC
114862. DONE_STOP
114863. DONE_TO_HPI_ENABLE
114864. DONE_WRITE
114865. DONE_WRITE_TO
114866. DONGLE_CALIBRATING
114867. DONGLE_CONNECTED
114868. DONGLE_DISABLED
114869. DONGLE_DISCONNECTED
114870. DONTALLOC
114871. DONTRESET_BIT0
114872. DONT_APPRAISE
114873. DONT_CARE_DA
114874. DONT_DS_ICON
114875. DONT_HASH
114876. DONT_MEASURE
114877. DONT_PROCESS_STATE
114878. DONT_SHADOW_VPAR
114879. DONT_SPLIT_AHB_WR
114880. DONT_TEST_IN_ITBLOCK
114881. DONT_UPDATE_DCB_DSCP
114882. DONT_USE_SPLL
114883. DONT_USE_XDLL
114884. DONT_WAIT_FOR_FBDIV_WRAP
114885. DONUTS
114886. DOOR
114887. DOORBELL
114888. DOORBELL_0
114889. DOORBELL_1
114890. DOORBELL_2
114891. DOORBELL_3
114892. DOORBELL_4
114893. DOORBELL_5
114894. DOORBELL_6
114895. DOORBELL_CLEAR_EVENTS
114896. DOORBELL_CLR_TOUT_US
114897. DOORBELL_CTLR_RESET
114898. DOORBELL_CTLR_RESET2
114899. DOORBELL_DMR_DI
114900. DOORBELL_DSR_DIQI
114901. DOORBELL_DSR_QFI
114902. DOORBELL_DSR_TE
114903. DOORBELL_EN
114904. DOORBELL_ENABLE_DESTRUCTIVE_DIAGS
114905. DOORBELL_FROM_CARD_CABLE_0
114906. DOORBELL_FROM_CARD_CABLE_1
114907. DOORBELL_FROM_CARD_CABLE_2
114908. DOORBELL_FROM_CARD_CABLE_3
114909. DOORBELL_FROM_CARD_RX
114910. DOORBELL_FROM_CARD_TX_0
114911. DOORBELL_FROM_CARD_TX_1
114912. DOORBELL_FROM_CARD_TX_2
114913. DOORBELL_FROM_CARD_TX_3
114914. DOORBELL_GENERATE_CHKPT
114915. DOORBELL_HDR_CONN_TYPE
114916. DOORBELL_HDR_CONN_TYPE_SHIFT
114917. DOORBELL_HDR_DB_TYPE
114918. DOORBELL_HDR_DB_TYPE_SHIFT
114919. DOORBELL_HDR_DPM_SIZE
114920. DOORBELL_HDR_DPM_SIZE_SHIFT
114921. DOORBELL_HDR_RX
114922. DOORBELL_HDR_RX_SHIFT
114923. DOORBELL_HIT
114924. DOORBELL_INT
114925. DOORBELL_INTR_MODE_MSIX
114926. DOORBELL_INTR_MSIX_CLR
114927. DOORBELL_IOA_DEBUG_ALERT
114928. DOORBELL_IOA_RESET_ALERT
114929. DOORBELL_IOA_START_BIST
114930. DOORBELL_MESSAGE_SIZE
114931. DOORBELL_OFFSET
114932. DOORBELL_OFFSET_MASK
114933. DOORBELL_REG_WIDTH
114934. DOORBELL_RELAXED
114935. DOORBELL_RESET_IOA
114936. DOORBELL_ROWAR_EN
114937. DOORBELL_ROWAR_MAINTRD
114938. DOORBELL_ROWAR_MAINTWD
114939. DOORBELL_ROWAR_NREAD
114940. DOORBELL_ROWAR_PCI
114941. DOORBELL_ROWAR_RES
114942. DOORBELL_ROWAR_SIZE
114943. DOORBELL_ROWAR_TFLOWLV
114944. DOORBELL_RUNTIME_RESET
114945. DOORBELL_SCHD_HIT
114946. DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
114947. DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK
114948. DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
114949. DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
114950. DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK
114951. DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
114952. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
114953. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK
114954. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
114955. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
114956. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
114957. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
114958. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK
114959. DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
114960. DOORBELL_SETUP
114961. DOORBELL_SOURCE
114962. DOORBELL_TO_CARD_CLOSE_0
114963. DOORBELL_TO_CARD_CLOSE_1
114964. DOORBELL_TO_CARD_CLOSE_2
114965. DOORBELL_TO_CARD_CLOSE_3
114966. DOORBELL_TO_CARD_OPEN_0
114967. DOORBELL_TO_CARD_OPEN_1
114968. DOORBELL_TO_CARD_OPEN_2
114969. DOORBELL_TO_CARD_OPEN_3
114970. DOORBELL_TO_CARD_TX_0
114971. DOORBELL_TO_CARD_TX_1
114972. DOORBELL_TO_CARD_TX_2
114973. DOORBELL_TO_CARD_TX_3
114974. DOORBELL_VAL_MASK
114975. DOOR_BELL_TARGET
114976. DOOR_EXPLICITLY_LOCKED
114977. DOOR_LOCKED
114978. DOOR_RGB
114979. DOOR_UNLOCKED
114980. DOP_CLOCK_GATING_DISABLE
114981. DOR
114982. DORCR
114983. DORCR_DK2S
114984. DORCR_DPRS
114985. DORCR_DR1D
114986. DORCR_PG1D_DOOR
114987. DORCR_PG1D_DS1
114988. DORCR_PG1D_DS2
114989. DORCR_PG1D_FIX0
114990. DORCR_PG1D_MASK
114991. DORCR_PG2D_DOOR
114992. DORCR_PG2D_DS1
114993. DORCR_PG2D_DS2
114994. DORCR_PG2D_FIX0
114995. DORCR_PG2D_MASK
114996. DORCR_PG2T
114997. DORCR_RGPV
114998. DORQ_REG_AGG_CMD0
114999. DORQ_REG_AGG_CMD1
115000. DORQ_REG_AGG_CMD2
115001. DORQ_REG_AGG_CMD3
115002. DORQ_REG_CMHEAD_RX
115003. DORQ_REG_DBG_DWORD_ENABLE
115004. DORQ_REG_DBG_FORCE_FRAME
115005. DORQ_REG_DBG_FORCE_VALID
115006. DORQ_REG_DBG_SELECT
115007. DORQ_REG_DBG_SHIFT
115008. DORQ_REG_DB_ADDR0
115009. DORQ_REG_DB_DROP_DETAILS
115010. DORQ_REG_DB_DROP_DETAILS_ADDRESS
115011. DORQ_REG_DB_DROP_DETAILS_REASON
115012. DORQ_REG_DB_DROP_DETAILS_REL
115013. DORQ_REG_DB_DROP_REASON
115014. DORQ_REG_DORQ_INT_MASK
115015. DORQ_REG_DORQ_INT_STS
115016. DORQ_REG_DORQ_INT_STS_CLR
115017. DORQ_REG_DORQ_PRTY_MASK
115018. DORQ_REG_DORQ_PRTY_STS
115019. DORQ_REG_DORQ_PRTY_STS_CLR
115020. DORQ_REG_DPM_CID_ADDR
115021. DORQ_REG_DPM_CID_OFST
115022. DORQ_REG_DPM_FORCE_ABORT
115023. DORQ_REG_DQ_FIFO_AFULL_TH
115024. DORQ_REG_DQ_FIFO_FULL_TH
115025. DORQ_REG_DQ_FILL_LVLF
115026. DORQ_REG_DQ_FULL_ST
115027. DORQ_REG_ERR_CMHEAD
115028. DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET
115029. DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET
115030. DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET
115031. DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET
115032. DORQ_REG_IFEN
115033. DORQ_REG_IF_EN
115034. DORQ_REG_INT_STS
115035. DORQ_REG_INT_STS_ADDRESS_ERROR
115036. DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT
115037. DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR
115038. DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT
115039. DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR
115040. DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT
115041. DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR
115042. DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT
115043. DORQ_REG_INT_STS_CFC_LD_RESP_ERR
115044. DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT
115045. DORQ_REG_INT_STS_DB_DROP
115046. DORQ_REG_INT_STS_DB_DROP_SHIFT
115047. DORQ_REG_INT_STS_DORQ_FIFO_AFULL
115048. DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT
115049. DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR
115050. DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT
115051. DORQ_REG_INT_STS_WR
115052. DORQ_REG_INT_STS_XCM_DONE_CNT_ERR
115053. DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT
115054. DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN
115055. DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN
115056. DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5
115057. DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5
115058. DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN
115059. DORQ_REG_MAX_RVFID_SIZE
115060. DORQ_REG_MODE_ACT
115061. DORQ_REG_NORM_CID_OFST
115062. DORQ_REG_NORM_CMHEAD_TX
115063. DORQ_REG_OUTST_REQ
115064. DORQ_REG_PF_DB_ENABLE
115065. DORQ_REG_PF_DPI_BIT_SHIFT
115066. DORQ_REG_PF_DPM_ENABLE
115067. DORQ_REG_PF_EXT_VID_BB_K2
115068. DORQ_REG_PF_ICID_BIT_SHIFT_NORM
115069. DORQ_REG_PF_MAX_ICID_0_RT_OFFSET
115070. DORQ_REG_PF_MAX_ICID_1_RT_OFFSET
115071. DORQ_REG_PF_MAX_ICID_2_RT_OFFSET
115072. DORQ_REG_PF_MAX_ICID_3_RT_OFFSET
115073. DORQ_REG_PF_MAX_ICID_4_RT_OFFSET
115074. DORQ_REG_PF_MAX_ICID_5_RT_OFFSET
115075. DORQ_REG_PF_MAX_ICID_6_RT_OFFSET
115076. DORQ_REG_PF_MAX_ICID_7_RT_OFFSET
115077. DORQ_REG_PF_MIN_ADDR_REG1
115078. DORQ_REG_PF_OVFL_STICKY
115079. DORQ_REG_PF_PCP_BB_K2
115080. DORQ_REG_PF_USAGE_CNT
115081. DORQ_REG_PF_WAKE_ALL_RT_OFFSET
115082. DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET
115083. DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET
115084. DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET
115085. DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET
115086. DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET
115087. DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET
115088. DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET
115089. DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET
115090. DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET
115091. DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET
115092. DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET
115093. DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET
115094. DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET
115095. DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET
115096. DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET
115097. DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET
115098. DORQ_REG_REGN
115099. DORQ_REG_RSPA_CRD_CNT
115100. DORQ_REG_RSPB_CRD_CNT
115101. DORQ_REG_RSP_INIT_CRD
115102. DORQ_REG_SHRT_ACT_CNT
115103. DORQ_REG_SHRT_CMHEAD
115104. DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET
115105. DORQ_REG_TAG1_OVRD_MODE
115106. DORQ_REG_VF_MAX_ICID_0_RT_OFFSET
115107. DORQ_REG_VF_MAX_ICID_1_RT_OFFSET
115108. DORQ_REG_VF_MAX_ICID_2_RT_OFFSET
115109. DORQ_REG_VF_MAX_ICID_3_RT_OFFSET
115110. DORQ_REG_VF_MAX_ICID_4_RT_OFFSET
115111. DORQ_REG_VF_MAX_ICID_5_RT_OFFSET
115112. DORQ_REG_VF_MAX_ICID_6_RT_OFFSET
115113. DORQ_REG_VF_MAX_ICID_7_RT_OFFSET
115114. DORQ_REG_VF_NORM_CID_BASE
115115. DORQ_REG_VF_NORM_CID_OFST
115116. DORQ_REG_VF_NORM_CID_WND_SIZE
115117. DORQ_REG_VF_NORM_MAX_CID_COUNT
115118. DORQ_REG_VF_NORM_VF_BASE
115119. DORQ_REG_VF_TYPE_MASK_0
115120. DORQ_REG_VF_TYPE_MAX_MCID_0
115121. DORQ_REG_VF_TYPE_MIN_MCID_0
115122. DORQ_REG_VF_TYPE_VALUE_0
115123. DORQ_REG_VF_USAGE_CNT
115124. DORQ_REG_VF_USAGE_CT_LIMIT
115125. DOSET1_S
115126. DOSET1_T
115127. DOSR_E
115128. DOS_CUR_DIR_NAME
115129. DOS_EXTENDED_PARTITION
115130. DOS_GCLK_EN0
115131. DOS_GCLK_EN3
115132. DOS_GEN_CTRL0
115133. DOS_Info_S
115134. DOS_MEM_PD_HEVC
115135. DOS_MEM_PD_VDEC
115136. DOS_NAME_LENGTH
115137. DOS_PAR_DIR_NAME
115138. DOS_PATH_LENGTH
115139. DOS_SW_RESET0
115140. DOS_SW_RESET3
115141. DOS_VDEC_MCRCC_STALL_CTRL
115142. DOT11AC
115143. DOT11AC_OPMODE
115144. DOT11D_I
115145. DOT11D_STATE_DONE
115146. DOT11D_STATE_LEARNED
115147. DOT11D_STATE_NONE
115148. DOT11H_CHANNEL_SWITCH
115149. DOT11H_I
115150. DOT11_A4_HDR_LEN
115151. DOT11_ACK_LEN
115152. DOT11_ACTION_ACT_OFF
115153. DOT11_ACTION_CAT_OFF
115154. DOT11_ACTION_HDR_LEN
115155. DOT11_AUTH_BOTH
115156. DOT11_AUTH_NONE
115157. DOT11_AUTH_OS
115158. DOT11_AUTH_SK
115159. DOT11_BA_BITMAP_LEN
115160. DOT11_BA_LEN
115161. DOT11_BCN_PRB_FIXED_LEN
115162. DOT11_BSSTYPE_ANY
115163. DOT11_BSSTYPE_IBSS
115164. DOT11_BSSTYPE_INFRA
115165. DOT11_BSSTYPE_NONE
115166. DOT11_CTS_LEN
115167. DOT11_CURRENT_CHANNEL
115168. DOT11_CUR_TX_PWR
115169. DOT11_DEFAULT_FRAG_LEN
115170. DOT11_DEFAULT_KEY
115171. DOT11_DEFAULT_RTS_LEN
115172. DOT11_DESIRED_SSID
115173. DOT11_ERPSTAT_NONEPRESENT
115174. DOT11_ERPSTAT_USEPROTECTION
115175. DOT11_FRAGMENTATION_THRESHOLD
115176. DOT11_GMK1_TSC
115177. DOT11_GMK2_TSC
115178. DOT11_GMK3_TSC
115179. DOT11_GROUP_ADDRESS_TBL
115180. DOT11_ICV_AES_LEN
115181. DOT11_IV_MAX_LEN
115182. DOT11_MAC_ADDRESS
115183. DOT11_MAC_HDR_LEN
115184. DOT11_MAXFRAMEBURST_IDEAL
115185. DOT11_MAXFRAMEBURST_MAX
115186. DOT11_MAXFRAMEBURST_MIXED_SAFE
115187. DOT11_MAXFRAMEBURST_OFF
115188. DOT11_MAXNUMFRAGS
115189. DOT11_MAX_FRAG_LEN
115190. DOT11_MGMT_HDR_LEN
115191. DOT11_MIN_FRAG_LEN
115192. DOT11_MLME_AUTO
115193. DOT11_MLME_EXTENDED
115194. DOT11_MLME_INTERMEDIATE
115195. DOT11_NONERP_ALWAYS
115196. DOT11_NONERP_DYNAMIC
115197. DOT11_NONERP_NEVER
115198. DOT11_OFDM_SIGNAL_EXTENSION
115199. DOT11_OID_ACKFAILED
115200. DOT11_OID_ACKWINDOW
115201. DOT11_OID_AID
115202. DOT11_OID_ALOFT_CONFIG
115203. DOT11_OID_ALOFT_CTRL_TABLE
115204. DOT11_OID_ALOFT_FIXEDRATE
115205. DOT11_OID_ALOFT_PROGRESS
115206. DOT11_OID_ALOFT_RETREAT
115207. DOT11_OID_ALOFT_RSSIGRAPH
115208. DOT11_OID_ALOFT_TABLE
115209. DOT11_OID_ANTENNADIVERSITY
115210. DOT11_OID_ANTENNARX
115211. DOT11_OID_ANTENNATX
115212. DOT11_OID_ASSOCIATE
115213. DOT11_OID_ASSOCIATEEX
115214. DOT11_OID_ASSOCRESPTIMEOUT
115215. DOT11_OID_ATIMWINDOW
115216. DOT11_OID_ATTACHMENT
115217. DOT11_OID_AUTHENABLE
115218. DOT11_OID_AUTHENTICATE
115219. DOT11_OID_AUTHENTICATEEX
115220. DOT11_OID_AUTHRESPTIMEOUT
115221. DOT11_OID_BEACON
115222. DOT11_OID_BEACONPERIOD
115223. DOT11_OID_BRIDGELOCAL
115224. DOT11_OID_BSSFIND
115225. DOT11_OID_BSSID
115226. DOT11_OID_BSSLIST
115227. DOT11_OID_BSSS
115228. DOT11_OID_BSSTIMEOUT
115229. DOT11_OID_BSSTYPE
115230. DOT11_OID_BSSX
115231. DOT11_OID_CAMTIMEOUT
115232. DOT11_OID_CCAMODE
115233. DOT11_OID_CCAMODESUPPORTED
115234. DOT11_OID_CFPDURATION
115235. DOT11_OID_CFPPERIOD
115236. DOT11_OID_CHANNEL
115237. DOT11_OID_CLIENTFIND
115238. DOT11_OID_CLIENTS
115239. DOT11_OID_CLIENTSASSOCIATED
115240. DOT11_OID_CLIENTX
115241. DOT11_OID_COUNTRYSTRING
115242. DOT11_OID_CWMAX
115243. DOT11_OID_CWMIN
115244. DOT11_OID_DEAUTHENTICATE
115245. DOT11_OID_DEAUTHENTICATEEX
115246. DOT11_OID_DEFKEYID
115247. DOT11_OID_DEFKEYX
115248. DOT11_OID_DISASSOCIATE
115249. DOT11_OID_DISASSOCIATEEX
115250. DOT11_OID_DOT1XENABLE
115251. DOT11_OID_DTIMPERIOD
115252. DOT11_OID_EAPAUTHSTA
115253. DOT11_OID_EAPUNAUTHSTA
115254. DOT11_OID_EDTHRESHOLD
115255. DOT11_OID_EXTENDEDRATES
115256. DOT11_OID_EXUNENCRYPTED
115257. DOT11_OID_FRAGTHRESH
115258. DOT11_OID_FRAMEABORTS
115259. DOT11_OID_FRAMEABORTSPHY
115260. DOT11_OID_FRAMEERRORS
115261. DOT11_OID_FRAMERECEIVES
115262. DOT11_OID_FREQUENCY
115263. DOT11_OID_FREQUENCYACTIVITY
115264. DOT11_OID_IQCALIBRATIONTABLE
115265. DOT11_OID_LISTENINTERVAL
115266. DOT11_OID_LONGRETRIES
115267. DOT11_OID_MAXFRAMEBURST
115268. DOT11_OID_MAXRXLIFETIME
115269. DOT11_OID_MAXTXLIFETIME
115270. DOT11_OID_MEDIUMLIMIT
115271. DOT11_OID_MICFAILURE
115272. DOT11_OID_MLMEAUTOLEVEL
115273. DOT11_OID_MPDURXDUPS
115274. DOT11_OID_MPDURXSUCCESSFUL
115275. DOT11_OID_MPDUTXFAILED
115276. DOT11_OID_MPDUTXMULTIPLERETRIES
115277. DOT11_OID_MPDUTXONERETRY
115278. DOT11_OID_MPDUTXSUCCESSFUL
115279. DOT11_OID_NOISEFLOOR
115280. DOT11_OID_NONERPPROTECTION
115281. DOT11_OID_NONERPSTATUS
115282. DOT11_OID_NONERPTIMEOUT
115283. DOT11_OID_OUTPUTPOWER
115284. DOT11_OID_OUTPUTPOWERTABLE
115285. DOT11_OID_PREAMBLESETTINGS
115286. DOT11_OID_PRIVACYINVOKED
115287. DOT11_OID_PRIVRXFAILED
115288. DOT11_OID_PRIVRXNOKEY
115289. DOT11_OID_PRIVRXPLAIN
115290. DOT11_OID_PRIVTXREJECTED
115291. DOT11_OID_PROBE
115292. DOT11_OID_PROFILES
115293. DOT11_OID_PSM
115294. DOT11_OID_PSMBUFFER
115295. DOT11_OID_RATES
115296. DOT11_OID_REASSOCIATE
115297. DOT11_OID_REASSOCIATEEX
115298. DOT11_OID_RECEIVEDTIMS
115299. DOT11_OID_REKEYINDICATE
115300. DOT11_OID_REKEYTHRESHOLD
115301. DOT11_OID_ROAMPREFERENCE
115302. DOT11_OID_RSSIVECTOR
115303. DOT11_OID_RTSFAILED
115304. DOT11_OID_RTSSUCCESSFUL
115305. DOT11_OID_RTSTHRESH
115306. DOT11_OID_SCAN
115307. DOT11_OID_SHORTRETRIES
115308. DOT11_OID_SLOTSETTINGS
115309. DOT11_OID_SLOTTIME
115310. DOT11_OID_SSID
115311. DOT11_OID_SSIDOVERRIDE
115312. DOT11_OID_STAKEY
115313. DOT11_OID_STASC
115314. DOT11_OID_STATE
115315. DOT11_OID_STATIMEOUT
115316. DOT11_OID_SUPPORTEDFREQUENCIES
115317. DOT11_OID_SUPPORTEDRATES
115318. DOT11_OID_VDCFX
115319. DOT11_OID_WDSLINKADD
115320. DOT11_OID_WDSLINKREMOVE
115321. DOT11_OPERATION_RATE_SET
115322. DOT11_PMK_TSC
115323. DOT11_PREAMBLESETTING_DYNAMIC
115324. DOT11_PREAMBLESETTING_LONG
115325. DOT11_PREAMBLESETTING_SHORT
115326. DOT11_PRIVACY_INVOKED
115327. DOT11_PRIV_TKIP
115328. DOT11_PRIV_WEP
115329. DOT11_PRODUCT_VERSION
115330. DOT11_PROFILE_A_ONLY
115331. DOT11_PROFILE_B_ONLY
115332. DOT11_PROFILE_B_WIFI
115333. DOT11_PROFILE_G_ONLY
115334. DOT11_PROFILE_MIXED_G_WIFI
115335. DOT11_PROFILE_MIXED_LONG
115336. DOT11_PROFILE_MIXED_SHORT
115337. DOT11_PROFILE_TEST
115338. DOT11_QOS_LEN
115339. DOT11_RATE5_ISBASIC_GET
115340. DOT11_RSN_CONFIG_AUTH_SUITE
115341. DOT11_RSN_CONFIG_MULTICAST_CIPHER
115342. DOT11_RSN_CONFIG_UNICAST_CIPHER
115343. DOT11_RSN_CONFIG_VERSION
115344. DOT11_RSN_ENABLED
115345. DOT11_RTS_LEN
115346. DOT11_RTS_THRESHOLD
115347. DOT11_RX_DOT11_MODE
115348. DOT11_RX_MSDU_LIFE_TIME
115349. DOT11_SLOTSETTINGS_DYNAMIC
115350. DOT11_SLOTSETTINGS_LONG
115351. DOT11_SLOTSETTINGS_SHORT
115352. DOT11_STATE_ASSOC
115353. DOT11_STATE_ASSOCING
115354. DOT11_STATE_AUTH
115355. DOT11_STATE_AUTHING
115356. DOT11_STATE_IBSS
115357. DOT11_STATE_NONE
115358. DOT11_STATE_WDS
115359. DOT11_STATION_ID
115360. DOT11_WEP_DEFAULT_KEY_ID
115361. DOT11_WEP_DEFAULT_KEY_VALUE1
115362. DOT11_WEP_DEFAULT_KEY_VALUE2
115363. DOT11_WEP_DEFAULT_KEY_VALUE3
115364. DOT11_WEP_DEFAULT_KEY_VALUE4
115365. DOT11_WEP_LIST
115366. DOTS
115367. DOTSYM
115368. DOT_DOT_OFFSET
115369. DOT_HZ
115370. DOT_MIDI_IN_PORTS
115371. DOT_MIDI_OUT_PORTS
115372. DOT_OFFSET
115373. DOU
115374. DOUBLEEXC_VECTOR_VADDR
115375. DOUBLEFAULT_STACKSIZE
115376. DOUBLE_BAI
115377. DOUBLE_CHECK__
115378. DOUBLE_EDGE
115379. DOUBLE_Ebias
115380. DOUBLE_Emax
115381. DOUBLE_Emin
115382. DOUBLE_REPORT_ID
115383. DOUBLE_TAP
115384. DOUT_A2M
115385. DOUT_ACLK_CCORE_133
115386. DOUT_ACLK_FSYS0_200
115387. DOUT_ACLK_FSYS1_200
115388. DOUT_ACLK_MSCL_532
115389. DOUT_ACLK_PERIC0
115390. DOUT_ACLK_PERIC1
115391. DOUT_ACLK_PERIS
115392. DOUT_APLL
115393. DOUT_APLL_CLKOUT
115394. DOUT_AUDIO0
115395. DOUT_AUDIO1
115396. DOUT_AUDIO2
115397. DOUT_CAM
115398. DOUT_CAM0
115399. DOUT_CAM1
115400. DOUT_CLKOUT
115401. DOUT_COPY
115402. DOUT_CSIS
115403. DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK
115404. DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT
115405. DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK
115406. DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT
115407. DOUT_DMC0
115408. DOUT_DPM
115409. DOUT_DVSEM
115410. DOUT_ERR_SHIFT
115411. DOUT_FIMC
115412. DOUT_FIMC0
115413. DOUT_FIMC1
115414. DOUT_FIMC2
115415. DOUT_FIMD
115416. DOUT_FLASH
115417. DOUT_G2D
115418. DOUT_G3D
115419. DOUT_HCLKD
115420. DOUT_HCLKM
115421. DOUT_HCLKP
115422. DOUT_HPM
115423. DOUT_I2C_ACK
115424. DOUT_I2C_ACK_TO_CLEAN
115425. DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER
115426. DOUT_I2C_ARBITRATION_ABORT_XFER
115427. DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG
115428. DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG
115429. DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG
115430. DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER
115431. DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO
115432. DOUT_I2C_ARBITRATION_SW_PRIORITY
115433. DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED
115434. DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED
115435. DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH
115436. DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL
115437. DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED
115438. DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED
115439. DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ
115440. DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ
115441. DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ
115442. DOUT_I2C_CONTROL_DBG_REF_SEL
115443. DOUT_I2C_CONTROL_DDC_SELECT
115444. DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG
115445. DOUT_I2C_CONTROL_GO
115446. DOUT_I2C_CONTROL_NORMAL_DEBUG
115447. DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER
115448. DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS
115449. DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER
115450. DOUT_I2C_CONTROL_RESET_SW_STATUS
115451. DOUT_I2C_CONTROL_SELECT_DDC1
115452. DOUT_I2C_CONTROL_SELECT_DDC2
115453. DOUT_I2C_CONTROL_SELECT_DDC3
115454. DOUT_I2C_CONTROL_SELECT_DDC4
115455. DOUT_I2C_CONTROL_SELECT_DDC5
115456. DOUT_I2C_CONTROL_SELECT_DDC6
115457. DOUT_I2C_CONTROL_SELECT_DDCVGA
115458. DOUT_I2C_CONTROL_SEND_RESET
115459. DOUT_I2C_CONTROL_SEND_RESET_LENGTH
115460. DOUT_I2C_CONTROL_SOFT_RESET
115461. DOUT_I2C_CONTROL_START_TRANSFER
115462. DOUT_I2C_CONTROL_STOP_TRANSFER
115463. DOUT_I2C_CONTROL_SW_STATUS_RESET
115464. DOUT_I2C_CONTROL_TRANS0
115465. DOUT_I2C_CONTROL_TRANS0_TRANS1
115466. DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2
115467. DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3
115468. DOUT_I2C_CONTROL_TRANSACTION_COUNT
115469. DOUT_I2C_CONTROL__NOT_SEND_RESET
115470. DOUT_I2C_CONTROL__SEND_RESET
115471. DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10
115472. DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9
115473. DOUT_I2C_DATA_INDEX_WRITE
115474. DOUT_I2C_DATA__INDEX_WRITE
115475. DOUT_I2C_DATA__NOT_INDEX_WRITE
115476. DOUT_I2C_DDC_EDID_DETECT_STATUS
115477. DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR
115478. DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN
115479. DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR
115480. DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN
115481. DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS
115482. DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS
115483. DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL
115484. DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED
115485. DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT
115486. DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT
115487. DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE
115488. DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED
115489. DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL
115490. DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA
115491. DOUT_I2C_DDC_SPEED_THRESHOLD
115492. DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO
115493. DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE
115494. DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE
115495. DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE
115496. DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET
115497. DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION
115498. DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION
115499. DOUT_I2C_NO_ACK
115500. DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE
115501. DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL
115502. DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE
115503. DOUT_I2C_TRANSACTION_STOP_ALL_TRANS
115504. DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS
115505. DOUT_I2C_TRANSACTION_STOP_ON_NACK
115506. DOUT_INTR_SHIFT
115507. DOUT_IRDA
115508. DOUT_JPEG
115509. DOUT_LCD
115510. DOUT_MFC
115511. DOUT_MIXER
115512. DOUT_MMC0
115513. DOUT_MMC1
115514. DOUT_MMC2
115515. DOUT_MMC3
115516. DOUT_MPLL
115517. DOUT_PCLKD
115518. DOUT_PCLKM
115519. DOUT_PCLKP
115520. DOUT_PCLK_FSYS1
115521. DOUT_PCLK_MSCL
115522. DOUT_POWER_MANAGEMENT_CNTL
115523. DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK
115524. DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT
115525. DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK
115526. DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT
115527. DOUT_PWI
115528. DOUT_PWM
115529. DOUT_RDY_SHIFT
115530. DOUT_SCALER
115531. DOUT_SCLK_AUD_PLL
115532. DOUT_SCLK_BUS0_PLL
115533. DOUT_SCLK_BUS1_PLL
115534. DOUT_SCLK_CC_PLL
115535. DOUT_SCLK_MFC_PLL
115536. DOUT_SCLK_MMC0
115537. DOUT_SCLK_MMC1
115538. DOUT_SCLK_MMC2
115539. DOUT_SCLK_PHY_FSYS1
115540. DOUT_SCLK_PHY_FSYS1_26M
115541. DOUT_SCLK_UFSUNIPRO20
115542. DOUT_SCRATCH0__DOUT_SCRATCH0_MASK
115543. DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT
115544. DOUT_SCRATCH1__DOUT_SCRATCH1_MASK
115545. DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT
115546. DOUT_SCRATCH2__DOUT_SCRATCH2_MASK
115547. DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT
115548. DOUT_SCRATCH3
115549. DOUT_SCRATCH3__DOUT_SCRATCH3_MASK
115550. DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT
115551. DOUT_SCRATCH4__DOUT_SCRATCH4_MASK
115552. DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT
115553. DOUT_SCRATCH5__DOUT_SCRATCH5_MASK
115554. DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT
115555. DOUT_SCRATCH6__DOUT_SCRATCH6_MASK
115556. DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT
115557. DOUT_SCRATCH7__DOUT_SCRATCH7_MASK
115558. DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT
115559. DOUT_SECUR
115560. DOUT_SIZE_AVAIL_MASK
115561. DOUT_SIZE_AVAIL_SHIFT
115562. DOUT_SPI0
115563. DOUT_SPI1
115564. DOUT_TBLK
115565. DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK
115566. DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT
115567. DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK
115568. DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT
115569. DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK
115570. DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT
115571. DOUT_TRISTATE
115572. DOUT_UART
115573. DOUT_UART0
115574. DOUT_UART1
115575. DOUT_UART2
115576. DOUT_UART3
115577. DOUT_UHOST
115578. DOU_IRQ_ERR
115579. DOU_IRQ_PL0
115580. DOU_IRQ_PL1
115581. DOU_IRQ_UND
115582. DOU_STATUS_ACTIVE
115583. DOU_STATUS_CSCE
115584. DOU_STATUS_DRIFTTO
115585. DOU_STATUS_FRAMETO
115586. DOU_STATUS_TETO
115587. DOVE_AC97_PHYS_BASE
115588. DOVE_AC97_VIRT_BASE
115589. DOVE_AU1_GPIO_SEL
115590. DOVE_AU1_SPDIFO_GPIO_EN
115591. DOVE_AUD0_PHYS_BASE
115592. DOVE_AUD1_PHYS_BASE
115593. DOVE_BOOTROM_PHYS_BASE
115594. DOVE_BOOTROM_SIZE
115595. DOVE_CAFE_WIN_PHYS_BASE
115596. DOVE_CAM_GPIO_SEL
115597. DOVE_CAM_PHYS_BASE
115598. DOVE_CESA_PHYS_BASE
115599. DOVE_CESA_SIZE
115600. DOVE_CESA_VIRT_BASE
115601. DOVE_CPU_TO_DDR
115602. DOVE_CPU_TO_L2
115603. DOVE_CRYPT_PHYS_BASE
115604. DOVE_DDR_BASE_CS_OFF
115605. DOVE_DIVIDER_H
115606. DOVE_GE00_PHYS_BASE
115607. DOVE_GLOBAL_CONFIG_1
115608. DOVE_GLOBAL_CONFIG_2
115609. DOVE_GPIO2_VIRT_BASE
115610. DOVE_GPIO_HI_VIRT_BASE
115611. DOVE_GPIO_LO_VIRT_BASE
115612. DOVE_GPU_PHYS_BASE
115613. DOVE_I2C_PHYS_BASE
115614. DOVE_LCD1_PHYS_BASE
115615. DOVE_LCD2_PHYS_BASE
115616. DOVE_LCD_DCON_PHYS_BASE
115617. DOVE_LCD_PHYS_BASE
115618. DOVE_MBUS_BOOTROM_ATTR
115619. DOVE_MBUS_BOOTROM_TARGET
115620. DOVE_MBUS_CESA_ATTR
115621. DOVE_MBUS_CESA_TARGET
115622. DOVE_MBUS_PCIE0_IO_ATTR
115623. DOVE_MBUS_PCIE0_IO_TARGET
115624. DOVE_MBUS_PCIE0_MEM_ATTR
115625. DOVE_MBUS_PCIE0_MEM_TARGET
115626. DOVE_MBUS_PCIE1_IO_ATTR
115627. DOVE_MBUS_PCIE1_IO_TARGET
115628. DOVE_MBUS_PCIE1_MEM_ATTR
115629. DOVE_MBUS_PCIE1_MEM_TARGET
115630. DOVE_MBUS_SCRATCHPAD_ATTR
115631. DOVE_MBUS_SCRATCHPAD_TARGET
115632. DOVE_MC_PHYS_BASE
115633. DOVE_MC_VIRT_BASE
115634. DOVE_MC_WINS_BASE
115635. DOVE_MC_WINS_SZ
115636. DOVE_MPP_CTRL4_VIRT_BASE
115637. DOVE_MPP_GENERAL_VIRT_BASE
115638. DOVE_MPP_VIRT_BASE
115639. DOVE_NAND_GPIO_EN
115640. DOVE_NB_REGS_PHYS_BASE
115641. DOVE_NB_REGS_SIZE
115642. DOVE_NB_REGS_VIRT_BASE
115643. DOVE_NFC_PHYS_BASE
115644. DOVE_NR_IRQS
115645. DOVE_PCIE0_IO_BUS_BASE
115646. DOVE_PCIE0_IO_PHYS_BASE
115647. DOVE_PCIE0_IO_SIZE
115648. DOVE_PCIE0_MEM_PHYS_BASE
115649. DOVE_PCIE0_MEM_SIZE
115650. DOVE_PCIE0_VIRT_BASE
115651. DOVE_PCIE1_IO_BUS_BASE
115652. DOVE_PCIE1_IO_PHYS_BASE
115653. DOVE_PCIE1_IO_SIZE
115654. DOVE_PCIE1_MEM_PHYS_BASE
115655. DOVE_PCIE1_MEM_SIZE
115656. DOVE_PCIE1_VIRT_BASE
115657. DOVE_PDMA_PHYS_BASE
115658. DOVE_PDMA_VIRT_BASE
115659. DOVE_PMU_MPP_GENERAL_CTRL
115660. DOVE_PMU_SIG_CTRL
115661. DOVE_PMU_VIRT_BASE
115662. DOVE_RESET_SAMPLE_HI
115663. DOVE_RESET_SAMPLE_LO
115664. DOVE_RTC_PHYS_BASE
115665. DOVE_SATA_PHYS_BASE
115666. DOVE_SB_REGS_PHYS_BASE
115667. DOVE_SB_REGS_SIZE
115668. DOVE_SB_REGS_VIRT_BASE
115669. DOVE_SCRATCHPAD_PHYS_BASE
115670. DOVE_SCRATCHPAD_SIZE
115671. DOVE_SCRATCHPAD_VIRT_BASE
115672. DOVE_SD0_GPIO_SEL
115673. DOVE_SD1_GPIO_SEL
115674. DOVE_SDIO0_PHYS_BASE
115675. DOVE_SDIO1_PHYS_BASE
115676. DOVE_SPI0_PHYS_BASE
115677. DOVE_SPI1_PHYS_BASE
115678. DOVE_SPI_GPIO_SEL
115679. DOVE_SSP_BPB_CLOCK_SRC_SSP
115680. DOVE_SSP_CLOCK_ENABLE
115681. DOVE_SSP_CTRL_STATUS_1
115682. DOVE_SSP_ON_AU1
115683. DOVE_SSP_PHYS_BASE
115684. DOVE_THERMAL_TEMP_MASK
115685. DOVE_THERMAL_TEMP_OFFSET
115686. DOVE_TWSI_ENABLE_OPTION1
115687. DOVE_TWSI_ENABLE_OPTION2
115688. DOVE_TWSI_ENABLE_OPTION3
115689. DOVE_TWSI_OPTION3_GPIO
115690. DOVE_UART0_PHYS_BASE
115691. DOVE_UART0_VIRT_BASE
115692. DOVE_UART1_GPIO_SEL
115693. DOVE_UART1_PHYS_BASE
115694. DOVE_UART1_VIRT_BASE
115695. DOVE_UART2_PHYS_BASE
115696. DOVE_UART2_VIRT_BASE
115697. DOVE_UART3_PHYS_BASE
115698. DOVE_UART3_VIRT_BASE
115699. DOVE_USB0_PHYS_BASE
115700. DOVE_USB1_PHYS_BASE
115701. DOVE_VPU_PHYS_BASE
115702. DOVE_XOR0_HIGH_PHYS_BASE
115703. DOVE_XOR0_HIGH_VIRT_BASE
115704. DOVE_XOR0_PHYS_BASE
115705. DOVE_XOR0_VIRT_BASE
115706. DOVE_XOR1_HIGH_PHYS_BASE
115707. DOVE_XOR1_HIGH_VIRT_BASE
115708. DOVE_XOR1_PHYS_BASE
115709. DOVE_XOR1_VIRT_BASE
115710. DOVOSTA
115711. DOVSTA
115712. DOWAIT
115713. DOWN
115714. DOWNCALL
115715. DOWNLOAD
115716. DOWNLOAD_ARE_YOU_HERE
115717. DOWNLOAD_BLOCK_SIZE
115718. DOWNLOAD_BLOCK_SIZE_WR
115719. DOWNLOAD_BOOT_LOADER_OFFSET
115720. DOWNLOAD_CONST
115721. DOWNLOAD_CTRL_DATA_DWORDS
115722. DOWNLOAD_CTRL_OFFSET
115723. DOWNLOAD_DEBUG_DATA_LEN
115724. DOWNLOAD_DEBUG_DATA_REG
115725. DOWNLOAD_ERR_ABORT
115726. DOWNLOAD_ERR_CHECKSUM
115727. DOWNLOAD_ERR_FILE_SIZE
115728. DOWNLOAD_ERR_HOST
115729. DOWNLOAD_ERR_IMAGE
115730. DOWNLOAD_ERR_MEM_1
115731. DOWNLOAD_ERR_MEM_2
115732. DOWNLOAD_ERR_OVERFLOW
115733. DOWNLOAD_ERR_SOFTWARE
115734. DOWNLOAD_EXCEPTION
115735. DOWNLOAD_FIFO_OFFSET
115736. DOWNLOAD_FIFO_SIZE
115737. DOWNLOAD_FIRMWARE
115738. DOWNLOAD_FLAGS_REG
115739. DOWNLOAD_GET_REG
115740. DOWNLOAD_IMAGE
115741. DOWNLOAD_IMAGE_SIZE_REG
115742. DOWNLOAD_I_AM_HERE
115743. DOWNLOAD_PENDING
115744. DOWNLOAD_PUT_REG
115745. DOWNLOAD_STATUS_REG
115746. DOWNLOAD_SUBCH
115747. DOWNLOAD_SUCCESS
115748. DOWNLOAD_TRACE_PC_REG
115749. DOWNSAMPLE_1_2
115750. DOWNSAMPLE_1_4
115751. DOWNSAMPLE_DISABLE
115752. DOWNSCALE_PREFETCH_DIS
115753. DOWNSCALE_PREFETCH_EN
115754. DOWNSHIFT_CNTL_MASK
115755. DOWNSHIFT_CNTL_POS
115756. DOWNSHIFT_COUNT_MAX
115757. DOWNSHIFT_DEV_DEFAULT_COUNT
115758. DOWNSHIFT_DEV_DISABLE
115759. DOWNSHIFT_EN
115760. DOWNSTREAM_DP
115761. DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS
115762. DOWNSTREAM_NONDDC
115763. DOWNSTREAM_VGA
115764. DOWN_BLOCK_SIZE
115765. DOWN_LINK
115766. DOWN_LINK_VAR
115767. DOWN_OR_CHOP
115768. DOWN_REMOTE_REASON_MASK
115769. DOWN_REMOTE_REASON_SHIFT
115770. DOWN_SCALE_MAX
115771. DOWN_SCALE_RATIO_MAX
115772. DOWN_STREAM_DETAILED_DP
115773. DOWN_STREAM_DETAILED_DP_PLUS_PLUS
115774. DOWN_STREAM_DETAILED_DVI
115775. DOWN_STREAM_DETAILED_HDMI
115776. DOWN_STREAM_DETAILED_NONDDC
115777. DOWN_STREAM_DETAILED_VGA
115778. DOWN_STREAM_MAX_10BPC
115779. DOWN_STREAM_MAX_12BPC
115780. DOWN_STREAM_MAX_16BPC
115781. DOWN_STREAM_MAX_8BPC
115782. DOZE
115783. DOZEPIU_IRQ
115784. DO_4ROUNDS
115785. DO_ACTION
115786. DO_APECS_IO
115787. DO_ATTACH
115788. DO_BIC
115789. DO_BIC_READ
115790. DO_BSD_COMPRESS
115791. DO_CIA_IO
115792. DO_CLRATN
115793. DO_CLRFIFO
115794. DO_CMDABORT
115795. DO_CRC
115796. DO_CRC4
115797. DO_CRC8
115798. DO_DATALATCH
115799. DO_DEFAULT_RTC
115800. DO_DEFLATE
115801. DO_DELAY
115802. DO_DELETE
115803. DO_DIRECTION
115804. DO_ERROR
115805. DO_ERROR_INFO
115806. DO_EV4_MMU
115807. DO_EV5_MMU
115808. DO_EV6_MMU
115809. DO_EV7_MMU
115810. DO_GENERIC_SYNC
115811. DO_HWRESELECT
115812. DO_INDEX
115813. DO_IRONGATE_IO
115814. DO_LCA_IO
115815. DO_LOAD_SWITCH_STACK
115816. DO_LOCK
115817. DO_LOOKUP
115818. DO_MAP_REGION_FAILURE
115819. DO_MAP_REGION_INVALID
115820. DO_MAP_REGION_SUCCESS
115821. DO_MARVEL_IO
115822. DO_MCKINLEY_E9_WORKAROUND
115823. DO_MCPCIA_IO
115824. DO_NOTHING
115825. DO_NOTHING_CALL_SCALAR
115826. DO_NOTHING_CALL_STRING
115827. DO_NOTHING_CALL_STRUCT
115828. DO_NOTHING_IN_SUSPEND
115829. DO_NOTHING_RETURN_SCALAR
115830. DO_NOTHING_RETURN_STRING
115831. DO_NOTHING_RETURN_STRUCT
115832. DO_NOTHING_TYPE_SCALAR
115833. DO_NOTHING_TYPE_STRING
115834. DO_NOTHING_TYPE_STRUCT
115835. DO_NOT_DRIVE_TX
115836. DO_NOT_FORCE_LINK_FAIL
115837. DO_NOT_PAD
115838. DO_NOT_QUEUE_DMA
115839. DO_NUMA
115840. DO_ONCE
115841. DO_PAD
115842. DO_PAGES_STAT_CHUNK_NR
115843. DO_POLARIS_IO
115844. DO_PREDICTOR_1
115845. DO_PREDICTOR_2
115846. DO_PYXIS_IO
115847. DO_REG
115848. DO_REPORT
115849. DO_REST_ALIGNED_DN
115850. DO_REST_ALIGNED_UP
115851. DO_REST_DN
115852. DO_REST_UP
115853. DO_RING_IDLE
115854. DO_ROUND
115855. DO_RSTMODULE
115856. DO_RSTSCSI
115857. DO_SAVE_MIN
115858. DO_SAVE_SWITCH_STACK
115859. DO_SEEK
115860. DO_SETATN
115861. DO_SETLINK_MODIFIED
115862. DO_SETLINK_NOTIFY
115863. DO_SLEEP
115864. DO_SMC
115865. DO_STATS
115866. DO_STORE
115867. DO_SWITCH_STACK
115868. DO_SYNC
115869. DO_T2_IO
115870. DO_TEST
115871. DO_TESTCASE_1
115872. DO_TESTCASE_1B
115873. DO_TESTCASE_2I
115874. DO_TESTCASE_2IB
115875. DO_TESTCASE_2x3
115876. DO_TESTCASE_2x6
115877. DO_TESTCASE_3
115878. DO_TESTCASE_3RW
115879. DO_TESTCASE_6
115880. DO_TESTCASE_6I
115881. DO_TESTCASE_6IRW
115882. DO_TESTCASE_6R
115883. DO_TESTCASE_6_SUCCESS
115884. DO_TESTCASE_6x2
115885. DO_TESTCASE_6x2B
115886. DO_TESTCASE_6x6
115887. DO_TESTCASE_6x6RW
115888. DO_TITAN_IO
115889. DO_TRACE
115890. DO_TSUNAMI_IO
115891. DO_TX
115892. DO_UNLOCK
115893. DO_UPDATE
115894. DO_WILDFIRE_IO
115895. DO_WRITE_THROUGH
115896. DO_XXLOCK_LOCK
115897. DO_XXLOCK_ONEBLOCK_GETLOCK
115898. DO_XXLOCK_ONEBLOCK_LOCK
115899. DO_XXLOCK_ONEBLOCK_UNLOCK
115900. DO_XXLOCK_UNLOCK
115901. DO_ZEROCOPY
115902. DP
115903. DP0CTL
115904. DP0_ACTIVEVAL
115905. DP0_AUDSRC_I2S_RX
115906. DP0_AUDSRC_NO_INPUT
115907. DP0_AUXADDR
115908. DP0_AUXCFG0
115909. DP0_AUXCFG0_ADDR_ONLY
115910. DP0_AUXCFG0_BSIZE
115911. DP0_AUXCFG1
115912. DP0_AUXI2CADR
115913. DP0_AUXRDATA
115914. DP0_AUXSTATUS
115915. DP0_AUXWDATA
115916. DP0_DEBUG_A
115917. DP0_DEBUG_B
115918. DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK
115919. DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT
115920. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK
115921. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT
115922. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK
115923. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT
115924. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK
115925. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT
115926. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK
115927. DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT
115928. DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK
115929. DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT
115930. DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK
115931. DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT
115932. DP0_DP_CONFIG__DP_UDI_LANES_MASK
115933. DP0_DP_CONFIG__DP_UDI_LANES__SHIFT
115934. DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK
115935. DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
115936. DP0_DP_DB_CNTL__DP_DB_LOCK_MASK
115937. DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT
115938. DP0_DP_DB_CNTL__DP_DB_PENDING_MASK
115939. DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT
115940. DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
115941. DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
115942. DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK
115943. DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
115944. DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK
115945. DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT
115946. DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK
115947. DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT
115948. DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK
115949. DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT
115950. DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
115951. DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
115952. DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
115953. DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
115954. DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
115955. DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
115956. DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
115957. DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
115958. DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
115959. DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
115960. DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
115961. DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
115962. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
115963. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
115964. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
115965. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
115966. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
115967. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
115968. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
115969. DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
115970. DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK
115971. DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
115972. DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK
115973. DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT
115974. DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK
115975. DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT
115976. DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK
115977. DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT
115978. DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
115979. DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
115980. DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
115981. DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
115982. DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
115983. DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
115984. DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
115985. DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
115986. DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
115987. DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
115988. DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
115989. DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
115990. DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
115991. DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
115992. DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
115993. DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
115994. DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
115995. DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
115996. DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
115997. DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
115998. DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
115999. DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
116000. DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
116001. DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
116002. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
116003. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
116004. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
116005. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
116006. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
116007. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
116008. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
116009. DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
116010. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
116011. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
116012. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
116013. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
116014. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
116015. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
116016. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
116017. DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
116018. DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
116019. DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
116020. DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
116021. DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
116022. DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
116023. DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
116024. DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
116025. DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
116026. DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
116027. DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
116028. DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
116029. DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
116030. DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
116031. DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
116032. DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
116033. DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
116034. DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
116035. DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
116036. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
116037. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
116038. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
116039. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
116040. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
116041. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
116042. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
116043. DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
116044. DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK
116045. DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
116046. DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK
116047. DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
116048. DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK
116049. DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
116050. DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK
116051. DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
116052. DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK
116053. DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
116054. DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK
116055. DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
116056. DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK
116057. DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
116058. DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK
116059. DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
116060. DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
116061. DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
116062. DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK
116063. DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT
116064. DP0_DP_DSC_CNTL__DP_DSC_EN_MASK
116065. DP0_DP_DSC_CNTL__DP_DSC_EN__SHIFT
116066. DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK
116067. DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT
116068. DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK
116069. DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT
116070. DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
116071. DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
116072. DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
116073. DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
116074. DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK
116075. DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
116076. DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
116077. DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
116078. DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
116079. DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
116080. DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
116081. DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
116082. DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
116083. DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
116084. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
116085. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
116086. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
116087. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
116088. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
116089. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
116090. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
116091. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
116092. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
116093. DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
116094. DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK
116095. DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
116096. DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK
116097. DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
116098. DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK
116099. DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
116100. DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK
116101. DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
116102. DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
116103. DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
116104. DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
116105. DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
116106. DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
116107. DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
116108. DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
116109. DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
116110. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
116111. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
116112. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
116113. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
116114. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
116115. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
116116. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
116117. DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
116118. DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
116119. DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
116120. DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
116121. DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
116122. DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
116123. DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
116124. DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
116125. DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
116126. DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
116127. DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
116128. DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
116129. DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
116130. DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
116131. DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
116132. DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
116133. DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
116134. DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK
116135. DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT
116136. DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK
116137. DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT
116138. DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
116139. DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
116140. DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
116141. DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
116142. DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
116143. DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
116144. DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
116145. DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
116146. DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
116147. DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
116148. DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
116149. DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
116150. DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
116151. DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
116152. DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
116153. DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
116154. DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
116155. DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
116156. DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
116157. DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
116158. DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
116159. DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
116160. DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
116161. DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
116162. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
116163. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
116164. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
116165. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
116166. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
116167. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
116168. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
116169. DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
116170. DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
116171. DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
116172. DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
116173. DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
116174. DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
116175. DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
116176. DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
116177. DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
116178. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
116179. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
116180. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
116181. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
116182. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
116183. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
116184. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
116185. DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
116186. DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
116187. DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
116188. DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
116189. DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
116190. DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
116191. DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
116192. DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
116193. DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
116194. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
116195. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
116196. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
116197. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
116198. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
116199. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
116200. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
116201. DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
116202. DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
116203. DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
116204. DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
116205. DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
116206. DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
116207. DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
116208. DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
116209. DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
116210. DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
116211. DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
116212. DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
116213. DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
116214. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
116215. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
116216. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
116217. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
116218. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
116219. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
116220. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
116221. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
116222. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
116223. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
116224. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
116225. DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
116226. DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
116227. DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
116228. DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
116229. DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
116230. DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
116231. DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
116232. DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
116233. DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
116234. DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
116235. DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
116236. DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
116237. DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
116238. DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
116239. DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
116240. DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
116241. DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
116242. DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
116243. DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
116244. DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
116245. DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
116246. DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
116247. DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
116248. DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
116249. DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
116250. DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
116251. DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
116252. DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
116253. DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
116254. DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
116255. DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
116256. DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
116257. DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
116258. DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
116259. DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
116260. DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
116261. DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
116262. DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
116263. DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
116264. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
116265. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
116266. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK
116267. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT
116268. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
116269. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
116270. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
116271. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
116272. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
116273. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
116274. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
116275. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
116276. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
116277. DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
116278. DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK
116279. DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT
116280. DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK
116281. DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT
116282. DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK
116283. DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT
116284. DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK
116285. DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT
116286. DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK
116287. DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT
116288. DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK
116289. DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT
116290. DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK
116291. DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT
116292. DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
116293. DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
116294. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
116295. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
116296. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
116297. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
116298. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
116299. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
116300. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
116301. DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
116302. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
116303. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
116304. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
116305. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
116306. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
116307. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
116308. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
116309. DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
116310. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
116311. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
116312. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
116313. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
116314. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
116315. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
116316. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
116317. DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
116318. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
116319. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
116320. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
116321. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
116322. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
116323. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
116324. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
116325. DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
116326. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
116327. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
116328. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
116329. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
116330. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
116331. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
116332. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
116333. DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
116334. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
116335. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
116336. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
116337. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
116338. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
116339. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
116340. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
116341. DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
116342. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
116343. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
116344. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
116345. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
116346. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
116347. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
116348. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
116349. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
116350. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
116351. DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
116352. DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
116353. DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
116354. DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
116355. DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
116356. DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
116357. DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
116358. DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
116359. DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
116360. DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
116361. DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
116362. DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
116363. DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
116364. DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
116365. DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
116366. DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
116367. DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
116368. DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK
116369. DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT
116370. DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
116371. DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
116372. DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK
116373. DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT
116374. DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
116375. DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
116376. DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK
116377. DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT
116378. DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
116379. DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
116380. DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK
116381. DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT
116382. DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
116383. DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
116384. DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK
116385. DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT
116386. DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
116387. DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
116388. DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK
116389. DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT
116390. DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
116391. DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
116392. DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK
116393. DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT
116394. DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
116395. DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
116396. DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK
116397. DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT
116398. DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
116399. DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
116400. DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
116401. DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
116402. DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
116403. DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
116404. DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
116405. DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
116406. DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
116407. DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
116408. DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
116409. DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
116410. DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
116411. DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
116412. DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
116413. DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
116414. DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
116415. DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
116416. DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
116417. DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
116418. DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
116419. DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
116420. DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
116421. DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
116422. DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
116423. DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
116424. DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
116425. DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
116426. DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
116427. DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
116428. DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
116429. DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
116430. DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
116431. DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
116432. DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
116433. DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
116434. DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
116435. DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
116436. DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
116437. DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
116438. DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
116439. DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
116440. DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
116441. DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
116442. DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
116443. DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
116444. DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
116445. DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
116446. DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
116447. DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
116448. DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK
116449. DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT
116450. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK
116451. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT
116452. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK
116453. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK
116454. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT
116455. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT
116456. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK
116457. DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT
116458. DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
116459. DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
116460. DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
116461. DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
116462. DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
116463. DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
116464. DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
116465. DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
116466. DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
116467. DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
116468. DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
116469. DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
116470. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
116471. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
116472. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
116473. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
116474. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
116475. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
116476. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
116477. DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
116478. DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
116479. DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
116480. DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
116481. DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
116482. DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
116483. DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
116484. DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
116485. DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
116486. DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
116487. DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
116488. DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
116489. DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
116490. DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
116491. DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
116492. DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
116493. DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
116494. DP0_DP_VID_M__DP_VID_M_MASK
116495. DP0_DP_VID_M__DP_VID_M__SHIFT
116496. DP0_DP_VID_N__DP_VID_N_MASK
116497. DP0_DP_VID_N__DP_VID_N__SHIFT
116498. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
116499. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
116500. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
116501. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
116502. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
116503. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
116504. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
116505. DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
116506. DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK
116507. DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
116508. DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
116509. DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
116510. DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
116511. DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
116512. DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
116513. DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
116514. DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK
116515. DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
116516. DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK
116517. DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
116518. DP0_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
116519. DP0_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
116520. DP0_LTLOOPCTRL
116521. DP0_LTSTAT
116522. DP0_MEM_ACCESS
116523. DP0_MISC
116524. DP0_PLLCTRL
116525. DP0_SECSAMPLE
116526. DP0_SNKLTCHGREQ
116527. DP0_SNKLTCTRL
116528. DP0_SRCCTRL
116529. DP0_SRCCTRL_AUTOCORRECT
116530. DP0_SRCCTRL_BW162
116531. DP0_SRCCTRL_BW27
116532. DP0_SRCCTRL_EN810B
116533. DP0_SRCCTRL_LANESKEW
116534. DP0_SRCCTRL_LANES_1
116535. DP0_SRCCTRL_LANES_2
116536. DP0_SRCCTRL_NOTP
116537. DP0_SRCCTRL_SCRMBLDIS
116538. DP0_SRCCTRL_SSCG
116539. DP0_SRCCTRL_TP1
116540. DP0_SRCCTRL_TP2
116541. DP0_STARTVAL
116542. DP0_SYNCVAL
116543. DP0_TOTALVAL
116544. DP0_VIDMNGEN0
116545. DP0_VIDMNGEN1
116546. DP0_VIDSRC_COLOR_BAR
116547. DP0_VIDSRC_DPI_RX
116548. DP0_VIDSRC_DSI_RX
116549. DP0_VIDSRC_NO_INPUT
116550. DP0_VIDSYNCDELAY
116551. DP0_VMNGENSTATUS
116552. DP1_DEBUG_A
116553. DP1_DEBUG_B
116554. DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK
116555. DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT
116556. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK
116557. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT
116558. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK
116559. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT
116560. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK
116561. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT
116562. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK
116563. DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT
116564. DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK
116565. DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT
116566. DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK
116567. DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT
116568. DP1_DP_CONFIG__DP_UDI_LANES_MASK
116569. DP1_DP_CONFIG__DP_UDI_LANES__SHIFT
116570. DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK
116571. DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
116572. DP1_DP_DB_CNTL__DP_DB_LOCK_MASK
116573. DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT
116574. DP1_DP_DB_CNTL__DP_DB_PENDING_MASK
116575. DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT
116576. DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
116577. DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
116578. DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK
116579. DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
116580. DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK
116581. DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT
116582. DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK
116583. DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT
116584. DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK
116585. DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT
116586. DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
116587. DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
116588. DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
116589. DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
116590. DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
116591. DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
116592. DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
116593. DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
116594. DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
116595. DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
116596. DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
116597. DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
116598. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
116599. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
116600. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
116601. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
116602. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
116603. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
116604. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
116605. DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
116606. DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK
116607. DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
116608. DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK
116609. DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT
116610. DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK
116611. DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT
116612. DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK
116613. DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT
116614. DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
116615. DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
116616. DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
116617. DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
116618. DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
116619. DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
116620. DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
116621. DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
116622. DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
116623. DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
116624. DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
116625. DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
116626. DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
116627. DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
116628. DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
116629. DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
116630. DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
116631. DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
116632. DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
116633. DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
116634. DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
116635. DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
116636. DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
116637. DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
116638. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
116639. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
116640. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
116641. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
116642. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
116643. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
116644. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
116645. DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
116646. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
116647. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
116648. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
116649. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
116650. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
116651. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
116652. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
116653. DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
116654. DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
116655. DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
116656. DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
116657. DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
116658. DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
116659. DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
116660. DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
116661. DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
116662. DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
116663. DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
116664. DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
116665. DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
116666. DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
116667. DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
116668. DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
116669. DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
116670. DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
116671. DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
116672. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
116673. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
116674. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
116675. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
116676. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
116677. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
116678. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
116679. DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
116680. DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK
116681. DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
116682. DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK
116683. DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
116684. DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK
116685. DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
116686. DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK
116687. DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
116688. DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK
116689. DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
116690. DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK
116691. DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
116692. DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK
116693. DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
116694. DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK
116695. DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
116696. DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
116697. DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
116698. DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK
116699. DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT
116700. DP1_DP_DSC_CNTL__DP_DSC_EN_MASK
116701. DP1_DP_DSC_CNTL__DP_DSC_EN__SHIFT
116702. DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK
116703. DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT
116704. DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK
116705. DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT
116706. DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
116707. DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
116708. DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
116709. DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
116710. DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK
116711. DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
116712. DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
116713. DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
116714. DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
116715. DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
116716. DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
116717. DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
116718. DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
116719. DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
116720. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
116721. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
116722. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
116723. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
116724. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
116725. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
116726. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
116727. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
116728. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
116729. DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
116730. DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK
116731. DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
116732. DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK
116733. DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
116734. DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK
116735. DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
116736. DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK
116737. DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
116738. DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
116739. DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
116740. DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
116741. DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
116742. DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
116743. DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
116744. DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
116745. DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
116746. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
116747. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
116748. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
116749. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
116750. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
116751. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
116752. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
116753. DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
116754. DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
116755. DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
116756. DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
116757. DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
116758. DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
116759. DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
116760. DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
116761. DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
116762. DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
116763. DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
116764. DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
116765. DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
116766. DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
116767. DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
116768. DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
116769. DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
116770. DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK
116771. DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT
116772. DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK
116773. DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT
116774. DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
116775. DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
116776. DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
116777. DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
116778. DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
116779. DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
116780. DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
116781. DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
116782. DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
116783. DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
116784. DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
116785. DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
116786. DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
116787. DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
116788. DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
116789. DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
116790. DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
116791. DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
116792. DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
116793. DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
116794. DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
116795. DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
116796. DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
116797. DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
116798. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
116799. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
116800. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
116801. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
116802. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
116803. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
116804. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
116805. DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
116806. DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
116807. DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
116808. DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
116809. DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
116810. DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
116811. DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
116812. DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
116813. DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
116814. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
116815. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
116816. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
116817. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
116818. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
116819. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
116820. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
116821. DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
116822. DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
116823. DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
116824. DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
116825. DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
116826. DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
116827. DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
116828. DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
116829. DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
116830. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
116831. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
116832. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
116833. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
116834. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
116835. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
116836. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
116837. DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
116838. DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
116839. DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
116840. DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
116841. DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
116842. DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
116843. DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
116844. DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
116845. DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
116846. DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
116847. DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
116848. DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
116849. DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
116850. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
116851. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
116852. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
116853. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
116854. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
116855. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
116856. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
116857. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
116858. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
116859. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
116860. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
116861. DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
116862. DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
116863. DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
116864. DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
116865. DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
116866. DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
116867. DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
116868. DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
116869. DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
116870. DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
116871. DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
116872. DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
116873. DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
116874. DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
116875. DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
116876. DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
116877. DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
116878. DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
116879. DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
116880. DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
116881. DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
116882. DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
116883. DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
116884. DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
116885. DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
116886. DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
116887. DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
116888. DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
116889. DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
116890. DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
116891. DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
116892. DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
116893. DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
116894. DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
116895. DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
116896. DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
116897. DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
116898. DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
116899. DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
116900. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
116901. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
116902. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK
116903. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT
116904. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
116905. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
116906. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
116907. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
116908. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
116909. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
116910. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
116911. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
116912. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
116913. DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
116914. DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK
116915. DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT
116916. DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK
116917. DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT
116918. DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK
116919. DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT
116920. DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK
116921. DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT
116922. DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK
116923. DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT
116924. DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK
116925. DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT
116926. DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK
116927. DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT
116928. DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
116929. DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
116930. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
116931. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
116932. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
116933. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
116934. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
116935. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
116936. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
116937. DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
116938. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
116939. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
116940. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
116941. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
116942. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
116943. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
116944. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
116945. DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
116946. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
116947. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
116948. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
116949. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
116950. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
116951. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
116952. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
116953. DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
116954. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
116955. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
116956. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
116957. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
116958. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
116959. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
116960. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
116961. DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
116962. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
116963. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
116964. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
116965. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
116966. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
116967. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
116968. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
116969. DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
116970. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
116971. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
116972. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
116973. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
116974. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
116975. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
116976. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
116977. DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
116978. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
116979. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
116980. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
116981. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
116982. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
116983. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
116984. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
116985. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
116986. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
116987. DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
116988. DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
116989. DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
116990. DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
116991. DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
116992. DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
116993. DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
116994. DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
116995. DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
116996. DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
116997. DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
116998. DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
116999. DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
117000. DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
117001. DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
117002. DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
117003. DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
117004. DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK
117005. DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT
117006. DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
117007. DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
117008. DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK
117009. DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT
117010. DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
117011. DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
117012. DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK
117013. DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT
117014. DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
117015. DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
117016. DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK
117017. DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT
117018. DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
117019. DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
117020. DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK
117021. DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT
117022. DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
117023. DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
117024. DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK
117025. DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT
117026. DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
117027. DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
117028. DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK
117029. DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT
117030. DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
117031. DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
117032. DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK
117033. DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT
117034. DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
117035. DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
117036. DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
117037. DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
117038. DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
117039. DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
117040. DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
117041. DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
117042. DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
117043. DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
117044. DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
117045. DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
117046. DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
117047. DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
117048. DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
117049. DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
117050. DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
117051. DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
117052. DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
117053. DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
117054. DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
117055. DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
117056. DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
117057. DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
117058. DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
117059. DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
117060. DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
117061. DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
117062. DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
117063. DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
117064. DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
117065. DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
117066. DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
117067. DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
117068. DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
117069. DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
117070. DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
117071. DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
117072. DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
117073. DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
117074. DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
117075. DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
117076. DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
117077. DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
117078. DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
117079. DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
117080. DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
117081. DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
117082. DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
117083. DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
117084. DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK
117085. DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT
117086. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK
117087. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT
117088. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK
117089. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK
117090. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT
117091. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT
117092. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK
117093. DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT
117094. DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
117095. DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
117096. DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
117097. DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
117098. DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
117099. DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
117100. DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
117101. DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
117102. DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
117103. DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
117104. DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
117105. DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
117106. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
117107. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
117108. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
117109. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
117110. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
117111. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
117112. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
117113. DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
117114. DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
117115. DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
117116. DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
117117. DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
117118. DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
117119. DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
117120. DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
117121. DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
117122. DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
117123. DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
117124. DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
117125. DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
117126. DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
117127. DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
117128. DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
117129. DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
117130. DP1_DP_VID_M__DP_VID_M_MASK
117131. DP1_DP_VID_M__DP_VID_M__SHIFT
117132. DP1_DP_VID_N__DP_VID_N_MASK
117133. DP1_DP_VID_N__DP_VID_N__SHIFT
117134. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
117135. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
117136. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
117137. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
117138. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
117139. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
117140. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
117141. DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
117142. DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK
117143. DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
117144. DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
117145. DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
117146. DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
117147. DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
117148. DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
117149. DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
117150. DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK
117151. DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
117152. DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK
117153. DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
117154. DP1_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
117155. DP1_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
117156. DP1_MEM_ACCESS
117157. DP1_PLLCTRL
117158. DP1_SRCCTRL
117159. DP27x1
117160. DP27x2
117161. DP27x4
117162. DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK
117163. DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT
117164. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK
117165. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT
117166. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK
117167. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT
117168. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK
117169. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT
117170. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK
117171. DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT
117172. DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK
117173. DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT
117174. DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK
117175. DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT
117176. DP2_DP_CONFIG__DP_UDI_LANES_MASK
117177. DP2_DP_CONFIG__DP_UDI_LANES__SHIFT
117178. DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK
117179. DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
117180. DP2_DP_DB_CNTL__DP_DB_LOCK_MASK
117181. DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT
117182. DP2_DP_DB_CNTL__DP_DB_PENDING_MASK
117183. DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT
117184. DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
117185. DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
117186. DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK
117187. DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
117188. DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK
117189. DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT
117190. DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK
117191. DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT
117192. DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK
117193. DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT
117194. DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
117195. DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
117196. DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
117197. DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
117198. DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
117199. DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
117200. DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
117201. DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
117202. DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
117203. DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
117204. DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
117205. DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
117206. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
117207. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
117208. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
117209. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
117210. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
117211. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
117212. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
117213. DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
117214. DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK
117215. DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
117216. DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK
117217. DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT
117218. DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK
117219. DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT
117220. DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK
117221. DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT
117222. DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
117223. DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
117224. DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
117225. DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
117226. DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
117227. DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
117228. DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
117229. DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
117230. DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
117231. DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
117232. DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
117233. DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
117234. DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
117235. DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
117236. DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
117237. DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
117238. DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
117239. DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
117240. DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
117241. DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
117242. DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
117243. DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
117244. DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
117245. DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
117246. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
117247. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
117248. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
117249. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
117250. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
117251. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
117252. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
117253. DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
117254. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
117255. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
117256. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
117257. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
117258. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
117259. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
117260. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
117261. DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
117262. DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
117263. DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
117264. DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
117265. DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
117266. DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
117267. DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
117268. DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
117269. DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
117270. DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
117271. DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
117272. DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
117273. DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
117274. DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
117275. DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
117276. DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
117277. DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
117278. DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
117279. DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
117280. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
117281. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
117282. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
117283. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
117284. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
117285. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
117286. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
117287. DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
117288. DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK
117289. DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
117290. DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK
117291. DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
117292. DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK
117293. DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
117294. DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK
117295. DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
117296. DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK
117297. DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
117298. DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK
117299. DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
117300. DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK
117301. DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
117302. DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK
117303. DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
117304. DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
117305. DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
117306. DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK
117307. DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT
117308. DP2_DP_DSC_CNTL__DP_DSC_EN_MASK
117309. DP2_DP_DSC_CNTL__DP_DSC_EN__SHIFT
117310. DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK
117311. DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT
117312. DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK
117313. DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT
117314. DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
117315. DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
117316. DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
117317. DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
117318. DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK
117319. DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
117320. DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
117321. DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
117322. DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
117323. DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
117324. DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
117325. DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
117326. DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
117327. DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
117328. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
117329. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
117330. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
117331. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
117332. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
117333. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
117334. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
117335. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
117336. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
117337. DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
117338. DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK
117339. DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
117340. DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK
117341. DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
117342. DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK
117343. DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
117344. DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK
117345. DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
117346. DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
117347. DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
117348. DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
117349. DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
117350. DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
117351. DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
117352. DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
117353. DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
117354. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
117355. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
117356. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
117357. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
117358. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
117359. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
117360. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
117361. DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
117362. DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
117363. DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
117364. DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
117365. DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
117366. DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
117367. DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
117368. DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
117369. DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
117370. DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
117371. DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
117372. DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
117373. DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
117374. DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
117375. DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
117376. DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
117377. DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
117378. DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK
117379. DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT
117380. DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK
117381. DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT
117382. DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
117383. DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
117384. DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
117385. DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
117386. DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
117387. DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
117388. DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
117389. DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
117390. DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
117391. DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
117392. DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
117393. DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
117394. DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
117395. DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
117396. DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
117397. DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
117398. DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
117399. DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
117400. DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
117401. DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
117402. DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
117403. DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
117404. DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
117405. DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
117406. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
117407. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
117408. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
117409. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
117410. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
117411. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
117412. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
117413. DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
117414. DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
117415. DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
117416. DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
117417. DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
117418. DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
117419. DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
117420. DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
117421. DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
117422. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
117423. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
117424. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
117425. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
117426. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
117427. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
117428. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
117429. DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
117430. DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
117431. DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
117432. DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
117433. DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
117434. DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
117435. DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
117436. DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
117437. DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
117438. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
117439. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
117440. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
117441. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
117442. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
117443. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
117444. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
117445. DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
117446. DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
117447. DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
117448. DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
117449. DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
117450. DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
117451. DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
117452. DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
117453. DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
117454. DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
117455. DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
117456. DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
117457. DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
117458. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
117459. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
117460. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
117461. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
117462. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
117463. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
117464. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
117465. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
117466. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
117467. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
117468. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
117469. DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
117470. DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
117471. DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
117472. DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
117473. DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
117474. DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
117475. DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
117476. DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
117477. DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
117478. DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
117479. DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
117480. DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
117481. DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
117482. DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
117483. DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
117484. DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
117485. DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
117486. DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
117487. DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
117488. DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
117489. DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
117490. DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
117491. DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
117492. DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
117493. DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
117494. DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
117495. DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
117496. DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
117497. DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
117498. DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
117499. DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
117500. DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
117501. DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
117502. DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
117503. DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
117504. DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
117505. DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
117506. DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
117507. DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
117508. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
117509. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
117510. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK
117511. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT
117512. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
117513. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
117514. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
117515. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
117516. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
117517. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
117518. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
117519. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
117520. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
117521. DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
117522. DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK
117523. DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT
117524. DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK
117525. DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT
117526. DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK
117527. DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT
117528. DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK
117529. DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT
117530. DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK
117531. DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT
117532. DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK
117533. DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT
117534. DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK
117535. DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT
117536. DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
117537. DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
117538. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
117539. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
117540. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
117541. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
117542. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
117543. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
117544. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
117545. DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
117546. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
117547. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
117548. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
117549. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
117550. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
117551. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
117552. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
117553. DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
117554. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
117555. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
117556. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
117557. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
117558. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
117559. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
117560. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
117561. DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
117562. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
117563. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
117564. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
117565. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
117566. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
117567. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
117568. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
117569. DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
117570. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
117571. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
117572. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
117573. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
117574. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
117575. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
117576. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
117577. DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
117578. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
117579. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
117580. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
117581. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
117582. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
117583. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
117584. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
117585. DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
117586. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
117587. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
117588. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
117589. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
117590. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
117591. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
117592. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
117593. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
117594. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
117595. DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
117596. DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
117597. DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
117598. DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
117599. DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
117600. DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
117601. DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
117602. DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
117603. DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
117604. DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
117605. DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
117606. DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
117607. DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
117608. DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
117609. DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
117610. DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
117611. DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
117612. DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK
117613. DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT
117614. DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
117615. DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
117616. DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK
117617. DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT
117618. DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
117619. DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
117620. DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK
117621. DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT
117622. DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
117623. DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
117624. DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK
117625. DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT
117626. DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
117627. DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
117628. DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK
117629. DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT
117630. DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
117631. DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
117632. DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK
117633. DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT
117634. DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
117635. DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
117636. DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK
117637. DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT
117638. DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
117639. DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
117640. DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK
117641. DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT
117642. DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
117643. DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
117644. DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
117645. DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
117646. DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
117647. DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
117648. DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
117649. DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
117650. DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
117651. DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
117652. DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
117653. DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
117654. DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
117655. DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
117656. DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
117657. DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
117658. DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
117659. DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
117660. DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
117661. DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
117662. DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
117663. DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
117664. DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
117665. DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
117666. DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
117667. DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
117668. DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
117669. DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
117670. DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
117671. DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
117672. DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
117673. DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
117674. DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
117675. DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
117676. DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
117677. DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
117678. DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
117679. DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
117680. DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
117681. DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
117682. DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
117683. DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
117684. DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
117685. DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
117686. DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
117687. DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
117688. DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
117689. DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
117690. DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
117691. DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
117692. DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK
117693. DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT
117694. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK
117695. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT
117696. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK
117697. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK
117698. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT
117699. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT
117700. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK
117701. DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT
117702. DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
117703. DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
117704. DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
117705. DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
117706. DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
117707. DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
117708. DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
117709. DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
117710. DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
117711. DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
117712. DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
117713. DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
117714. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
117715. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
117716. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
117717. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
117718. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
117719. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
117720. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
117721. DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
117722. DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
117723. DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
117724. DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
117725. DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
117726. DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
117727. DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
117728. DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
117729. DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
117730. DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
117731. DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
117732. DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
117733. DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
117734. DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
117735. DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
117736. DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
117737. DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
117738. DP2_DP_VID_M__DP_VID_M_MASK
117739. DP2_DP_VID_M__DP_VID_M__SHIFT
117740. DP2_DP_VID_N__DP_VID_N_MASK
117741. DP2_DP_VID_N__DP_VID_N__SHIFT
117742. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
117743. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
117744. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
117745. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
117746. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
117747. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
117748. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
117749. DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
117750. DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK
117751. DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
117752. DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
117753. DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
117754. DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
117755. DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
117756. DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
117757. DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
117758. DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK
117759. DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
117760. DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK
117761. DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
117762. DP2_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
117763. DP2_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
117764. DP324x1
117765. DP324x2
117766. DP324x4
117767. DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK
117768. DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT
117769. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK
117770. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT
117771. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK
117772. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT
117773. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK
117774. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT
117775. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK
117776. DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT
117777. DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK
117778. DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT
117779. DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK
117780. DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT
117781. DP3_DP_CONFIG__DP_UDI_LANES_MASK
117782. DP3_DP_CONFIG__DP_UDI_LANES__SHIFT
117783. DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK
117784. DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
117785. DP3_DP_DB_CNTL__DP_DB_LOCK_MASK
117786. DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT
117787. DP3_DP_DB_CNTL__DP_DB_PENDING_MASK
117788. DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT
117789. DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
117790. DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
117791. DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK
117792. DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
117793. DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK
117794. DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT
117795. DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK
117796. DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT
117797. DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK
117798. DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT
117799. DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
117800. DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
117801. DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
117802. DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
117803. DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
117804. DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
117805. DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
117806. DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
117807. DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
117808. DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
117809. DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
117810. DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
117811. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
117812. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
117813. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
117814. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
117815. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
117816. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
117817. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
117818. DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
117819. DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK
117820. DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
117821. DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK
117822. DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT
117823. DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK
117824. DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT
117825. DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK
117826. DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT
117827. DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
117828. DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
117829. DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
117830. DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
117831. DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
117832. DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
117833. DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
117834. DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
117835. DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
117836. DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
117837. DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
117838. DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
117839. DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
117840. DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
117841. DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
117842. DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
117843. DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
117844. DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
117845. DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
117846. DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
117847. DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
117848. DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
117849. DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
117850. DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
117851. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
117852. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
117853. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
117854. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
117855. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
117856. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
117857. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
117858. DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
117859. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
117860. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
117861. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
117862. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
117863. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
117864. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
117865. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
117866. DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
117867. DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
117868. DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
117869. DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
117870. DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
117871. DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
117872. DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
117873. DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
117874. DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
117875. DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
117876. DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
117877. DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
117878. DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
117879. DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
117880. DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
117881. DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
117882. DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
117883. DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
117884. DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
117885. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
117886. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
117887. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
117888. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
117889. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
117890. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
117891. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
117892. DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
117893. DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK
117894. DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
117895. DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK
117896. DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
117897. DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK
117898. DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
117899. DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK
117900. DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
117901. DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK
117902. DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
117903. DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK
117904. DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
117905. DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK
117906. DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
117907. DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK
117908. DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
117909. DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
117910. DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
117911. DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK
117912. DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT
117913. DP3_DP_DSC_CNTL__DP_DSC_EN_MASK
117914. DP3_DP_DSC_CNTL__DP_DSC_EN__SHIFT
117915. DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK
117916. DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT
117917. DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK
117918. DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT
117919. DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
117920. DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
117921. DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
117922. DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
117923. DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK
117924. DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
117925. DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
117926. DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
117927. DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
117928. DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
117929. DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
117930. DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
117931. DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
117932. DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
117933. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
117934. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
117935. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
117936. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
117937. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
117938. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
117939. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
117940. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
117941. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
117942. DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
117943. DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK
117944. DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
117945. DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK
117946. DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
117947. DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK
117948. DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
117949. DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK
117950. DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
117951. DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
117952. DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
117953. DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
117954. DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
117955. DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
117956. DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
117957. DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
117958. DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
117959. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
117960. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
117961. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
117962. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
117963. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
117964. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
117965. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
117966. DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
117967. DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
117968. DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
117969. DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
117970. DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
117971. DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
117972. DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
117973. DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
117974. DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
117975. DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
117976. DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
117977. DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
117978. DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
117979. DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
117980. DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
117981. DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
117982. DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
117983. DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK
117984. DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT
117985. DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK
117986. DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT
117987. DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
117988. DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
117989. DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
117990. DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
117991. DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
117992. DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
117993. DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
117994. DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
117995. DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
117996. DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
117997. DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
117998. DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
117999. DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
118000. DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
118001. DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
118002. DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
118003. DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
118004. DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
118005. DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
118006. DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
118007. DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
118008. DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
118009. DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
118010. DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
118011. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
118012. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
118013. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
118014. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
118015. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
118016. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
118017. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
118018. DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
118019. DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
118020. DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
118021. DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
118022. DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
118023. DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
118024. DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
118025. DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
118026. DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
118027. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
118028. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
118029. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
118030. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
118031. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
118032. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
118033. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
118034. DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
118035. DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
118036. DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
118037. DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
118038. DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
118039. DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
118040. DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
118041. DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
118042. DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
118043. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
118044. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
118045. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
118046. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
118047. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
118048. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
118049. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
118050. DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
118051. DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
118052. DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
118053. DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
118054. DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
118055. DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
118056. DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
118057. DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
118058. DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
118059. DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
118060. DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
118061. DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
118062. DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
118063. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
118064. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
118065. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
118066. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
118067. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
118068. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
118069. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
118070. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
118071. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
118072. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
118073. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
118074. DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
118075. DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
118076. DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
118077. DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
118078. DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
118079. DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
118080. DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
118081. DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
118082. DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
118083. DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
118084. DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
118085. DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
118086. DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
118087. DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
118088. DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
118089. DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
118090. DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
118091. DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
118092. DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
118093. DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
118094. DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
118095. DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
118096. DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
118097. DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
118098. DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
118099. DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
118100. DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
118101. DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
118102. DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
118103. DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
118104. DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
118105. DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
118106. DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
118107. DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
118108. DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
118109. DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
118110. DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
118111. DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
118112. DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
118113. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
118114. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
118115. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK
118116. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT
118117. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
118118. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
118119. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
118120. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
118121. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
118122. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
118123. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
118124. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
118125. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
118126. DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
118127. DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK
118128. DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT
118129. DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK
118130. DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT
118131. DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK
118132. DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT
118133. DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK
118134. DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT
118135. DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK
118136. DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT
118137. DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK
118138. DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT
118139. DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK
118140. DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT
118141. DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
118142. DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
118143. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
118144. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
118145. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
118146. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
118147. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
118148. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
118149. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
118150. DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
118151. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
118152. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
118153. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
118154. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
118155. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
118156. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
118157. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
118158. DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
118159. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
118160. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
118161. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
118162. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
118163. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
118164. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
118165. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
118166. DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
118167. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
118168. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
118169. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
118170. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
118171. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
118172. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
118173. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
118174. DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
118175. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
118176. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
118177. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
118178. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
118179. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
118180. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
118181. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
118182. DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
118183. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
118184. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
118185. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
118186. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
118187. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
118188. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
118189. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
118190. DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
118191. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
118192. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
118193. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
118194. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
118195. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
118196. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
118197. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
118198. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
118199. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
118200. DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
118201. DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
118202. DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
118203. DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
118204. DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
118205. DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
118206. DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
118207. DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
118208. DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
118209. DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
118210. DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
118211. DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
118212. DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
118213. DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
118214. DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
118215. DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
118216. DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
118217. DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK
118218. DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT
118219. DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
118220. DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
118221. DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK
118222. DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT
118223. DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
118224. DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
118225. DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK
118226. DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT
118227. DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
118228. DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
118229. DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK
118230. DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT
118231. DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
118232. DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
118233. DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK
118234. DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT
118235. DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
118236. DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
118237. DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK
118238. DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT
118239. DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
118240. DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
118241. DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK
118242. DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT
118243. DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
118244. DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
118245. DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK
118246. DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT
118247. DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
118248. DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
118249. DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
118250. DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
118251. DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
118252. DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
118253. DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
118254. DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
118255. DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
118256. DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
118257. DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
118258. DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
118259. DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
118260. DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
118261. DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
118262. DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
118263. DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
118264. DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
118265. DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
118266. DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
118267. DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
118268. DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
118269. DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
118270. DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
118271. DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
118272. DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
118273. DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
118274. DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
118275. DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
118276. DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
118277. DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
118278. DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
118279. DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
118280. DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
118281. DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
118282. DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
118283. DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
118284. DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
118285. DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
118286. DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
118287. DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
118288. DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
118289. DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
118290. DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
118291. DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
118292. DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
118293. DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
118294. DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
118295. DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
118296. DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
118297. DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK
118298. DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT
118299. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK
118300. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT
118301. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK
118302. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK
118303. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT
118304. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT
118305. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK
118306. DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT
118307. DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
118308. DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
118309. DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
118310. DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
118311. DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
118312. DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
118313. DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
118314. DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
118315. DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
118316. DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
118317. DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
118318. DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
118319. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
118320. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
118321. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
118322. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
118323. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
118324. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
118325. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
118326. DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
118327. DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
118328. DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
118329. DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
118330. DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
118331. DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
118332. DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
118333. DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
118334. DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
118335. DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
118336. DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
118337. DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
118338. DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
118339. DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
118340. DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
118341. DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
118342. DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
118343. DP3_DP_VID_M__DP_VID_M_MASK
118344. DP3_DP_VID_M__DP_VID_M__SHIFT
118345. DP3_DP_VID_N__DP_VID_N_MASK
118346. DP3_DP_VID_N__DP_VID_N__SHIFT
118347. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
118348. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
118349. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
118350. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
118351. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
118352. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
118353. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
118354. DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
118355. DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK
118356. DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
118357. DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
118358. DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
118359. DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
118360. DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
118361. DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
118362. DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
118363. DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK
118364. DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
118365. DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK
118366. DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
118367. DP3_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
118368. DP3_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
118369. DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK
118370. DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT
118371. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK
118372. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT
118373. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK
118374. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT
118375. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK
118376. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT
118377. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK
118378. DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT
118379. DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK
118380. DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT
118381. DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK
118382. DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT
118383. DP4_DP_CONFIG__DP_UDI_LANES_MASK
118384. DP4_DP_CONFIG__DP_UDI_LANES__SHIFT
118385. DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK
118386. DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
118387. DP4_DP_DB_CNTL__DP_DB_LOCK_MASK
118388. DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT
118389. DP4_DP_DB_CNTL__DP_DB_PENDING_MASK
118390. DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT
118391. DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
118392. DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
118393. DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK
118394. DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
118395. DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK
118396. DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT
118397. DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK
118398. DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT
118399. DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK
118400. DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT
118401. DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
118402. DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
118403. DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
118404. DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
118405. DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
118406. DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
118407. DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
118408. DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
118409. DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
118410. DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
118411. DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
118412. DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
118413. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
118414. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
118415. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
118416. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
118417. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
118418. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
118419. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
118420. DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
118421. DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK
118422. DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
118423. DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK
118424. DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT
118425. DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK
118426. DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT
118427. DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK
118428. DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT
118429. DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
118430. DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
118431. DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
118432. DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
118433. DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
118434. DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
118435. DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
118436. DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
118437. DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
118438. DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
118439. DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
118440. DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
118441. DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
118442. DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
118443. DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
118444. DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
118445. DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
118446. DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
118447. DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
118448. DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
118449. DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
118450. DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
118451. DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
118452. DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
118453. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
118454. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
118455. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
118456. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
118457. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
118458. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
118459. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
118460. DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
118461. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
118462. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
118463. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
118464. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
118465. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
118466. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
118467. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
118468. DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
118469. DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
118470. DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
118471. DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
118472. DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
118473. DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
118474. DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
118475. DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
118476. DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
118477. DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
118478. DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
118479. DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
118480. DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
118481. DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
118482. DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
118483. DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
118484. DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
118485. DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
118486. DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
118487. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
118488. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
118489. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
118490. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
118491. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
118492. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
118493. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
118494. DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
118495. DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK
118496. DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
118497. DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK
118498. DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
118499. DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK
118500. DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
118501. DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK
118502. DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
118503. DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK
118504. DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
118505. DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK
118506. DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
118507. DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK
118508. DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
118509. DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK
118510. DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
118511. DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
118512. DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
118513. DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK
118514. DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT
118515. DP4_DP_DSC_CNTL__DP_DSC_EN_MASK
118516. DP4_DP_DSC_CNTL__DP_DSC_EN__SHIFT
118517. DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK
118518. DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT
118519. DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK
118520. DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT
118521. DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
118522. DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
118523. DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
118524. DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
118525. DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK
118526. DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
118527. DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
118528. DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
118529. DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
118530. DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
118531. DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
118532. DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
118533. DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
118534. DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
118535. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
118536. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
118537. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
118538. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
118539. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
118540. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
118541. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
118542. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
118543. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
118544. DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
118545. DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK
118546. DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
118547. DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK
118548. DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
118549. DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK
118550. DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
118551. DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK
118552. DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
118553. DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
118554. DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
118555. DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
118556. DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
118557. DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
118558. DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
118559. DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
118560. DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
118561. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
118562. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
118563. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
118564. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
118565. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
118566. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
118567. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
118568. DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
118569. DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
118570. DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
118571. DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
118572. DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
118573. DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
118574. DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
118575. DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
118576. DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
118577. DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
118578. DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
118579. DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
118580. DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
118581. DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
118582. DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
118583. DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
118584. DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
118585. DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK
118586. DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT
118587. DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK
118588. DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT
118589. DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
118590. DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
118591. DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
118592. DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
118593. DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
118594. DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
118595. DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
118596. DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
118597. DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
118598. DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
118599. DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
118600. DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
118601. DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
118602. DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
118603. DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
118604. DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
118605. DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
118606. DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
118607. DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
118608. DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
118609. DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
118610. DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
118611. DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
118612. DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
118613. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
118614. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
118615. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
118616. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
118617. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
118618. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
118619. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
118620. DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
118621. DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
118622. DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
118623. DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
118624. DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
118625. DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
118626. DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
118627. DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
118628. DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
118629. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
118630. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
118631. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
118632. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
118633. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
118634. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
118635. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
118636. DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
118637. DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
118638. DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
118639. DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
118640. DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
118641. DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
118642. DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
118643. DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
118644. DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
118645. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
118646. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
118647. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
118648. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
118649. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
118650. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
118651. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
118652. DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
118653. DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
118654. DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
118655. DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
118656. DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
118657. DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
118658. DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
118659. DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
118660. DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
118661. DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
118662. DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
118663. DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
118664. DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
118665. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
118666. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
118667. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
118668. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
118669. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
118670. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
118671. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
118672. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
118673. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
118674. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
118675. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
118676. DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
118677. DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
118678. DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
118679. DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
118680. DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
118681. DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
118682. DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
118683. DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
118684. DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
118685. DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
118686. DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
118687. DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
118688. DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
118689. DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
118690. DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
118691. DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
118692. DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
118693. DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
118694. DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
118695. DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
118696. DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
118697. DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
118698. DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
118699. DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
118700. DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
118701. DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
118702. DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
118703. DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
118704. DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
118705. DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
118706. DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
118707. DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
118708. DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
118709. DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
118710. DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
118711. DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
118712. DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
118713. DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
118714. DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
118715. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
118716. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
118717. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK
118718. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT
118719. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
118720. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
118721. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
118722. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
118723. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
118724. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
118725. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
118726. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
118727. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
118728. DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
118729. DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK
118730. DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT
118731. DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK
118732. DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT
118733. DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK
118734. DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT
118735. DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK
118736. DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT
118737. DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK
118738. DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT
118739. DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK
118740. DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT
118741. DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK
118742. DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT
118743. DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
118744. DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
118745. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
118746. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
118747. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
118748. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
118749. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
118750. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
118751. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
118752. DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
118753. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
118754. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
118755. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
118756. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
118757. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
118758. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
118759. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
118760. DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
118761. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
118762. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
118763. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
118764. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
118765. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
118766. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
118767. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
118768. DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
118769. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
118770. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
118771. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
118772. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
118773. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
118774. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
118775. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
118776. DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
118777. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
118778. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
118779. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
118780. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
118781. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
118782. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
118783. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
118784. DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
118785. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
118786. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
118787. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
118788. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
118789. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
118790. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
118791. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
118792. DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
118793. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
118794. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
118795. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
118796. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
118797. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
118798. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
118799. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
118800. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
118801. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
118802. DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
118803. DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
118804. DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
118805. DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
118806. DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
118807. DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
118808. DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
118809. DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
118810. DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
118811. DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
118812. DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
118813. DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
118814. DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
118815. DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
118816. DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
118817. DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
118818. DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
118819. DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK
118820. DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT
118821. DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
118822. DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
118823. DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK
118824. DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT
118825. DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
118826. DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
118827. DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK
118828. DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT
118829. DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
118830. DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
118831. DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK
118832. DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT
118833. DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
118834. DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
118835. DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK
118836. DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT
118837. DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
118838. DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
118839. DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK
118840. DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT
118841. DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
118842. DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
118843. DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK
118844. DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT
118845. DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
118846. DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
118847. DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK
118848. DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT
118849. DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
118850. DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
118851. DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
118852. DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
118853. DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
118854. DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
118855. DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
118856. DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
118857. DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
118858. DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
118859. DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
118860. DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
118861. DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
118862. DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
118863. DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
118864. DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
118865. DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
118866. DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
118867. DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
118868. DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
118869. DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
118870. DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
118871. DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
118872. DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
118873. DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
118874. DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
118875. DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
118876. DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
118877. DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
118878. DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
118879. DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
118880. DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
118881. DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
118882. DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
118883. DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
118884. DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
118885. DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
118886. DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
118887. DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
118888. DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
118889. DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
118890. DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
118891. DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
118892. DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
118893. DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
118894. DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
118895. DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
118896. DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
118897. DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
118898. DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
118899. DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK
118900. DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT
118901. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK
118902. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT
118903. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK
118904. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK
118905. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT
118906. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT
118907. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK
118908. DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT
118909. DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
118910. DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
118911. DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
118912. DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
118913. DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
118914. DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
118915. DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
118916. DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
118917. DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
118918. DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
118919. DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
118920. DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
118921. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
118922. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
118923. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
118924. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
118925. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
118926. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
118927. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
118928. DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
118929. DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
118930. DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
118931. DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
118932. DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
118933. DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
118934. DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
118935. DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
118936. DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
118937. DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
118938. DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
118939. DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
118940. DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
118941. DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
118942. DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
118943. DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
118944. DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
118945. DP4_DP_VID_M__DP_VID_M_MASK
118946. DP4_DP_VID_M__DP_VID_M__SHIFT
118947. DP4_DP_VID_N__DP_VID_N_MASK
118948. DP4_DP_VID_N__DP_VID_N__SHIFT
118949. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
118950. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
118951. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
118952. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
118953. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
118954. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
118955. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
118956. DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
118957. DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK
118958. DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
118959. DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
118960. DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
118961. DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
118962. DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
118963. DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
118964. DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
118965. DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK
118966. DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
118967. DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK
118968. DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
118969. DP4_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
118970. DP4_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
118971. DP54x1
118972. DP54x2
118973. DP54x4
118974. DP5_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK
118975. DP5_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT
118976. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK
118977. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT
118978. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK
118979. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT
118980. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK
118981. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT
118982. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK
118983. DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT
118984. DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK
118985. DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT
118986. DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK
118987. DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT
118988. DP5_DP_CONFIG__DP_UDI_LANES_MASK
118989. DP5_DP_CONFIG__DP_UDI_LANES__SHIFT
118990. DP5_DP_DB_CNTL__DP_DB_DISABLE_MASK
118991. DP5_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
118992. DP5_DP_DB_CNTL__DP_DB_LOCK_MASK
118993. DP5_DP_DB_CNTL__DP_DB_LOCK__SHIFT
118994. DP5_DP_DB_CNTL__DP_DB_PENDING_MASK
118995. DP5_DP_DB_CNTL__DP_DB_PENDING__SHIFT
118996. DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
118997. DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
118998. DP5_DP_DB_CNTL__DP_DB_TAKEN_MASK
118999. DP5_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
119000. DP5_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK
119001. DP5_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT
119002. DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK
119003. DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT
119004. DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK
119005. DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT
119006. DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
119007. DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
119008. DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
119009. DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
119010. DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
119011. DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
119012. DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
119013. DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
119014. DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
119015. DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
119016. DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
119017. DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
119018. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
119019. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
119020. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
119021. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
119022. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
119023. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
119024. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
119025. DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
119026. DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK
119027. DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
119028. DP5_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK
119029. DP5_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT
119030. DP5_DP_DPHY_CNTL__DPHY_FEC_EN_MASK
119031. DP5_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT
119032. DP5_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK
119033. DP5_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT
119034. DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
119035. DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
119036. DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
119037. DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
119038. DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
119039. DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
119040. DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
119041. DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
119042. DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
119043. DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
119044. DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
119045. DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
119046. DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
119047. DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
119048. DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
119049. DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
119050. DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
119051. DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
119052. DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
119053. DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
119054. DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
119055. DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
119056. DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
119057. DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
119058. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
119059. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
119060. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
119061. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
119062. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
119063. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
119064. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
119065. DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
119066. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
119067. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
119068. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
119069. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
119070. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
119071. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
119072. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
119073. DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
119074. DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
119075. DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
119076. DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
119077. DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
119078. DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
119079. DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
119080. DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
119081. DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
119082. DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
119083. DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
119084. DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
119085. DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
119086. DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
119087. DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
119088. DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
119089. DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
119090. DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
119091. DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
119092. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
119093. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
119094. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
119095. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
119096. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
119097. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
119098. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
119099. DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
119100. DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK
119101. DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
119102. DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK
119103. DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
119104. DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK
119105. DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
119106. DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK
119107. DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
119108. DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK
119109. DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
119110. DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK
119111. DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
119112. DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK
119113. DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
119114. DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK
119115. DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
119116. DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
119117. DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
119118. DP5_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK
119119. DP5_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT
119120. DP5_DP_DSC_CNTL__DP_DSC_EN_MASK
119121. DP5_DP_DSC_CNTL__DP_DSC_EN__SHIFT
119122. DP5_DP_DSC_CNTL__DP_DSC_MODE_MASK
119123. DP5_DP_DSC_CNTL__DP_DSC_MODE__SHIFT
119124. DP5_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK
119125. DP5_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT
119126. DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
119127. DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
119128. DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
119129. DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
119130. DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK
119131. DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
119132. DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
119133. DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
119134. DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
119135. DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
119136. DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
119137. DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
119138. DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
119139. DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
119140. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
119141. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
119142. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
119143. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
119144. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
119145. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
119146. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
119147. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
119148. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
119149. DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
119150. DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK
119151. DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
119152. DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK
119153. DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
119154. DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK
119155. DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
119156. DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK
119157. DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
119158. DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
119159. DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
119160. DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
119161. DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
119162. DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
119163. DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
119164. DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
119165. DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
119166. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
119167. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
119168. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
119169. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
119170. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
119171. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
119172. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
119173. DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
119174. DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
119175. DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
119176. DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
119177. DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
119178. DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
119179. DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
119180. DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
119181. DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
119182. DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
119183. DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
119184. DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
119185. DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
119186. DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
119187. DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
119188. DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
119189. DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
119190. DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK
119191. DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT
119192. DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK
119193. DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT
119194. DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
119195. DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
119196. DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
119197. DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
119198. DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
119199. DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
119200. DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
119201. DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
119202. DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
119203. DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
119204. DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
119205. DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
119206. DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
119207. DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
119208. DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
119209. DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
119210. DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
119211. DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
119212. DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
119213. DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
119214. DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
119215. DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
119216. DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
119217. DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
119218. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
119219. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
119220. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
119221. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
119222. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
119223. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
119224. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
119225. DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
119226. DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
119227. DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
119228. DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
119229. DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
119230. DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
119231. DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
119232. DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
119233. DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
119234. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
119235. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
119236. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
119237. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
119238. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
119239. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
119240. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
119241. DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
119242. DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
119243. DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
119244. DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
119245. DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
119246. DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
119247. DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
119248. DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
119249. DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
119250. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
119251. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
119252. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
119253. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
119254. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
119255. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
119256. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
119257. DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
119258. DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
119259. DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
119260. DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
119261. DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
119262. DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
119263. DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
119264. DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
119265. DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
119266. DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
119267. DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
119268. DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
119269. DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
119270. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
119271. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
119272. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
119273. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
119274. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
119275. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
119276. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
119277. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
119278. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
119279. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
119280. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
119281. DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
119282. DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
119283. DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
119284. DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
119285. DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
119286. DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
119287. DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
119288. DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
119289. DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
119290. DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
119291. DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
119292. DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
119293. DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
119294. DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
119295. DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
119296. DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
119297. DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
119298. DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
119299. DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
119300. DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
119301. DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
119302. DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
119303. DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
119304. DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
119305. DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
119306. DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
119307. DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
119308. DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
119309. DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
119310. DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
119311. DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
119312. DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
119313. DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
119314. DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
119315. DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
119316. DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
119317. DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
119318. DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
119319. DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
119320. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
119321. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
119322. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK
119323. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT
119324. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
119325. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
119326. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
119327. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
119328. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
119329. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
119330. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
119331. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
119332. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
119333. DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
119334. DP5_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK
119335. DP5_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT
119336. DP5_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK
119337. DP5_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT
119338. DP5_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK
119339. DP5_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT
119340. DP5_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK
119341. DP5_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT
119342. DP5_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK
119343. DP5_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT
119344. DP5_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK
119345. DP5_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT
119346. DP5_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK
119347. DP5_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT
119348. DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
119349. DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
119350. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
119351. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
119352. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
119353. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
119354. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
119355. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
119356. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
119357. DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
119358. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
119359. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
119360. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
119361. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
119362. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
119363. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
119364. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
119365. DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
119366. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
119367. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
119368. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
119369. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
119370. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
119371. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
119372. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
119373. DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
119374. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
119375. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
119376. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
119377. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
119378. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
119379. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
119380. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
119381. DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
119382. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
119383. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
119384. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
119385. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
119386. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
119387. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
119388. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
119389. DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
119390. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
119391. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
119392. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
119393. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
119394. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
119395. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
119396. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
119397. DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
119398. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
119399. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
119400. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
119401. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
119402. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
119403. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
119404. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
119405. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
119406. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
119407. DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
119408. DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
119409. DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
119410. DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
119411. DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
119412. DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
119413. DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
119414. DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
119415. DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
119416. DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
119417. DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
119418. DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
119419. DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
119420. DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
119421. DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
119422. DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
119423. DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
119424. DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK
119425. DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT
119426. DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
119427. DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
119428. DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK
119429. DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT
119430. DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
119431. DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
119432. DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK
119433. DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT
119434. DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
119435. DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
119436. DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK
119437. DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT
119438. DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
119439. DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
119440. DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK
119441. DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT
119442. DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
119443. DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
119444. DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK
119445. DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT
119446. DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
119447. DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
119448. DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK
119449. DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT
119450. DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
119451. DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
119452. DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK
119453. DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT
119454. DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
119455. DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
119456. DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
119457. DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
119458. DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
119459. DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
119460. DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
119461. DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
119462. DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
119463. DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
119464. DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
119465. DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
119466. DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
119467. DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
119468. DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
119469. DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
119470. DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
119471. DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
119472. DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
119473. DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
119474. DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
119475. DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
119476. DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
119477. DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
119478. DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
119479. DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
119480. DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
119481. DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
119482. DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
119483. DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
119484. DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
119485. DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
119486. DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
119487. DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
119488. DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
119489. DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
119490. DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
119491. DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
119492. DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
119493. DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
119494. DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
119495. DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
119496. DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
119497. DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
119498. DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
119499. DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
119500. DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
119501. DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
119502. DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
119503. DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
119504. DP5_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK
119505. DP5_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT
119506. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK
119507. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT
119508. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK
119509. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK
119510. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT
119511. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT
119512. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK
119513. DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT
119514. DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
119515. DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
119516. DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
119517. DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
119518. DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
119519. DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
119520. DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
119521. DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
119522. DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
119523. DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
119524. DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
119525. DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
119526. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
119527. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
119528. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
119529. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
119530. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
119531. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
119532. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
119533. DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
119534. DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
119535. DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
119536. DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
119537. DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
119538. DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
119539. DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
119540. DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
119541. DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
119542. DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
119543. DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
119544. DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
119545. DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
119546. DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
119547. DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
119548. DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
119549. DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
119550. DP5_DP_VID_M__DP_VID_M_MASK
119551. DP5_DP_VID_M__DP_VID_M__SHIFT
119552. DP5_DP_VID_N__DP_VID_N_MASK
119553. DP5_DP_VID_N__DP_VID_N__SHIFT
119554. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
119555. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
119556. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
119557. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
119558. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
119559. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
119560. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
119561. DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
119562. DP5_DP_VID_TIMING__DP_VID_M_DIV_MASK
119563. DP5_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
119564. DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
119565. DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
119566. DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
119567. DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
119568. DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
119569. DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
119570. DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK
119571. DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
119572. DP5_DP_VID_TIMING__DP_VID_N_MUL_MASK
119573. DP5_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
119574. DP5_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
119575. DP5_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
119576. DP6_DP_CONFIG__DP_UDI_LANES_MASK
119577. DP6_DP_CONFIG__DP_UDI_LANES__SHIFT
119578. DP6_DP_DB_CNTL__DP_DB_DISABLE_MASK
119579. DP6_DP_DB_CNTL__DP_DB_DISABLE__SHIFT
119580. DP6_DP_DB_CNTL__DP_DB_LOCK_MASK
119581. DP6_DP_DB_CNTL__DP_DB_LOCK__SHIFT
119582. DP6_DP_DB_CNTL__DP_DB_PENDING_MASK
119583. DP6_DP_DB_CNTL__DP_DB_PENDING__SHIFT
119584. DP6_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK
119585. DP6_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT
119586. DP6_DP_DB_CNTL__DP_DB_TAKEN_MASK
119587. DP6_DP_DB_CNTL__DP_DB_TAKEN__SHIFT
119588. DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
119589. DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
119590. DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
119591. DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
119592. DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
119593. DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
119594. DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
119595. DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
119596. DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
119597. DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
119598. DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
119599. DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
119600. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
119601. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
119602. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
119603. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
119604. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
119605. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
119606. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
119607. DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
119608. DP6_DP_DPHY_CNTL__DPHY_BYPASS_MASK
119609. DP6_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
119610. DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
119611. DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
119612. DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
119613. DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
119614. DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
119615. DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
119616. DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
119617. DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
119618. DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
119619. DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
119620. DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
119621. DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
119622. DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
119623. DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
119624. DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
119625. DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
119626. DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
119627. DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
119628. DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
119629. DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
119630. DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
119631. DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
119632. DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
119633. DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
119634. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
119635. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
119636. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
119637. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
119638. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
119639. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
119640. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
119641. DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
119642. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
119643. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
119644. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
119645. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
119646. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
119647. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
119648. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
119649. DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
119650. DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
119651. DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
119652. DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
119653. DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
119654. DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
119655. DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
119656. DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
119657. DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
119658. DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
119659. DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
119660. DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
119661. DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
119662. DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
119663. DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
119664. DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
119665. DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
119666. DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
119667. DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
119668. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
119669. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
119670. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
119671. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
119672. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK
119673. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT
119674. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK
119675. DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT
119676. DP6_DP_DPHY_SYM0__DPHY_SYM1_MASK
119677. DP6_DP_DPHY_SYM0__DPHY_SYM1__SHIFT
119678. DP6_DP_DPHY_SYM0__DPHY_SYM2_MASK
119679. DP6_DP_DPHY_SYM0__DPHY_SYM2__SHIFT
119680. DP6_DP_DPHY_SYM0__DPHY_SYM3_MASK
119681. DP6_DP_DPHY_SYM0__DPHY_SYM3__SHIFT
119682. DP6_DP_DPHY_SYM1__DPHY_SYM4_MASK
119683. DP6_DP_DPHY_SYM1__DPHY_SYM4__SHIFT
119684. DP6_DP_DPHY_SYM1__DPHY_SYM5_MASK
119685. DP6_DP_DPHY_SYM1__DPHY_SYM5__SHIFT
119686. DP6_DP_DPHY_SYM1__DPHY_SYM6_MASK
119687. DP6_DP_DPHY_SYM1__DPHY_SYM6__SHIFT
119688. DP6_DP_DPHY_SYM2__DPHY_SYM7_MASK
119689. DP6_DP_DPHY_SYM2__DPHY_SYM7__SHIFT
119690. DP6_DP_DPHY_SYM2__DPHY_SYM8_MASK
119691. DP6_DP_DPHY_SYM2__DPHY_SYM8__SHIFT
119692. DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
119693. DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
119694. DP6_DP_DSC_CNTL__DP_DSC_EN_MASK
119695. DP6_DP_DSC_CNTL__DP_DSC_EN__SHIFT
119696. DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
119697. DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
119698. DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
119699. DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
119700. DP6_DP_LINK_CNTL__DP_LINK_STATUS_MASK
119701. DP6_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
119702. DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
119703. DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
119704. DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
119705. DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
119706. DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
119707. DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
119708. DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
119709. DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
119710. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK
119711. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
119712. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
119713. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
119714. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
119715. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT
119716. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
119717. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
119718. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
119719. DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
119720. DP6_DP_MSA_MISC__DP_MSA_MISC1_MASK
119721. DP6_DP_MSA_MISC__DP_MSA_MISC1__SHIFT
119722. DP6_DP_MSA_MISC__DP_MSA_MISC2_MASK
119723. DP6_DP_MSA_MISC__DP_MSA_MISC2__SHIFT
119724. DP6_DP_MSA_MISC__DP_MSA_MISC3_MASK
119725. DP6_DP_MSA_MISC__DP_MSA_MISC3__SHIFT
119726. DP6_DP_MSA_MISC__DP_MSA_MISC4_MASK
119727. DP6_DP_MSA_MISC__DP_MSA_MISC4__SHIFT
119728. DP6_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK
119729. DP6_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT
119730. DP6_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK
119731. DP6_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT
119732. DP6_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK
119733. DP6_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT
119734. DP6_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK
119735. DP6_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT
119736. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK
119737. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT
119738. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK
119739. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT
119740. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK
119741. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT
119742. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK
119743. DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT
119744. DP6_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK
119745. DP6_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT
119746. DP6_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK
119747. DP6_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT
119748. DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK
119749. DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT
119750. DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK
119751. DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT
119752. DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK
119753. DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT
119754. DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK
119755. DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT
119756. DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK
119757. DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT
119758. DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK
119759. DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT
119760. DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
119761. DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
119762. DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
119763. DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
119764. DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
119765. DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
119766. DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
119767. DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
119768. DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
119769. DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
119770. DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
119771. DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
119772. DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
119773. DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
119774. DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
119775. DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
119776. DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
119777. DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
119778. DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
119779. DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
119780. DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
119781. DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
119782. DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
119783. DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
119784. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
119785. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
119786. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
119787. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
119788. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
119789. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
119790. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
119791. DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
119792. DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
119793. DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
119794. DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
119795. DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
119796. DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
119797. DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
119798. DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
119799. DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
119800. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
119801. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
119802. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
119803. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
119804. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
119805. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
119806. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
119807. DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
119808. DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
119809. DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
119810. DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
119811. DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
119812. DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
119813. DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
119814. DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
119815. DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
119816. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
119817. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
119818. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
119819. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
119820. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
119821. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
119822. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
119823. DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
119824. DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
119825. DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
119826. DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
119827. DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
119828. DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
119829. DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
119830. DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
119831. DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
119832. DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
119833. DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
119834. DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
119835. DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
119836. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK
119837. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT
119838. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK
119839. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT
119840. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK
119841. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT
119842. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK
119843. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT
119844. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK
119845. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT
119846. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK
119847. DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT
119848. DP6_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK
119849. DP6_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT
119850. DP6_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK
119851. DP6_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT
119852. DP6_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK
119853. DP6_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT
119854. DP6_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK
119855. DP6_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT
119856. DP6_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK
119857. DP6_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT
119858. DP6_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK
119859. DP6_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT
119860. DP6_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK
119861. DP6_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT
119862. DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK
119863. DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT
119864. DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK
119865. DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT
119866. DP6_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK
119867. DP6_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT
119868. DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
119869. DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
119870. DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
119871. DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
119872. DP6_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK
119873. DP6_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT
119874. DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
119875. DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
119876. DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
119877. DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
119878. DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
119879. DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
119880. DP6_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
119881. DP6_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
119882. DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
119883. DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
119884. DP6_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
119885. DP6_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
119886. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
119887. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
119888. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
119889. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
119890. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK
119891. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT
119892. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
119893. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
119894. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
119895. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
119896. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
119897. DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
119898. DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
119899. DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
119900. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK
119901. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT
119902. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK
119903. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT
119904. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK
119905. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK
119906. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT
119907. DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT
119908. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK
119909. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT
119910. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK
119911. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT
119912. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK
119913. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK
119914. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT
119915. DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT
119916. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK
119917. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT
119918. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK
119919. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT
119920. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK
119921. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK
119922. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT
119923. DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT
119924. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK
119925. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT
119926. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK
119927. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT
119928. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK
119929. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK
119930. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT
119931. DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT
119932. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK
119933. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT
119934. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK
119935. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT
119936. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK
119937. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK
119938. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT
119939. DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT
119940. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK
119941. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT
119942. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK
119943. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT
119944. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK
119945. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK
119946. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT
119947. DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT
119948. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK
119949. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT
119950. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK
119951. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT
119952. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK
119953. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT
119954. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK
119955. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK
119956. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT
119957. DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT
119958. DP6_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK
119959. DP6_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT
119960. DP6_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK
119961. DP6_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT
119962. DP6_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK
119963. DP6_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT
119964. DP6_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK
119965. DP6_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT
119966. DP6_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK
119967. DP6_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT
119968. DP6_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK
119969. DP6_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT
119970. DP6_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK
119971. DP6_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT
119972. DP6_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK
119973. DP6_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT
119974. DP6_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK
119975. DP6_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT
119976. DP6_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK
119977. DP6_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT
119978. DP6_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK
119979. DP6_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT
119980. DP6_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK
119981. DP6_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT
119982. DP6_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK
119983. DP6_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT
119984. DP6_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK
119985. DP6_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT
119986. DP6_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK
119987. DP6_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT
119988. DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
119989. DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
119990. DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
119991. DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
119992. DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
119993. DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
119994. DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
119995. DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
119996. DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
119997. DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
119998. DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
119999. DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
120000. DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
120001. DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
120002. DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
120003. DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
120004. DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
120005. DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
120006. DP6_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK
120007. DP6_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT
120008. DP6_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK
120009. DP6_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT
120010. DP6_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK
120011. DP6_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT
120012. DP6_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK
120013. DP6_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT
120014. DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
120015. DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
120016. DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
120017. DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
120018. DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
120019. DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
120020. DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
120021. DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
120022. DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
120023. DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
120024. DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
120025. DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
120026. DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
120027. DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
120028. DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
120029. DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
120030. DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
120031. DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
120032. DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
120033. DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
120034. DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
120035. DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
120036. DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
120037. DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
120038. DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
120039. DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
120040. DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
120041. DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
120042. DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
120043. DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
120044. DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
120045. DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
120046. DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
120047. DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
120048. DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
120049. DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
120050. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
120051. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
120052. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
120053. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
120054. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
120055. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
120056. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
120057. DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
120058. DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
120059. DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
120060. DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
120061. DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
120062. DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
120063. DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
120064. DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
120065. DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
120066. DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
120067. DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
120068. DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
120069. DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
120070. DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
120071. DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
120072. DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
120073. DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
120074. DP6_DP_VID_M__DP_VID_M_MASK
120075. DP6_DP_VID_M__DP_VID_M__SHIFT
120076. DP6_DP_VID_N__DP_VID_N_MASK
120077. DP6_DP_VID_N__DP_VID_N__SHIFT
120078. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
120079. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
120080. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
120081. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
120082. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
120083. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
120084. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
120085. DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
120086. DP6_DP_VID_TIMING__DP_VID_M_DIV_MASK
120087. DP6_DP_VID_TIMING__DP_VID_M_DIV__SHIFT
120088. DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
120089. DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
120090. DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
120091. DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
120092. DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
120093. DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
120094. DP6_DP_VID_TIMING__DP_VID_N_DIV_MASK
120095. DP6_DP_VID_TIMING__DP_VID_N_DIV__SHIFT
120096. DP6_DP_VID_TIMING__DP_VID_N_MUL_MASK
120097. DP6_DP_VID_TIMING__DP_VID_N_MUL__SHIFT
120098. DP6_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
120099. DP6_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
120100. DP83065_MII_MEM
120101. DP83065_MII_REGD
120102. DP83065_MII_REGE
120103. DP83640_N_PINS
120104. DP83640_PACKET_HASH_LEN
120105. DP83640_PACKET_HASH_OFFSET
120106. DP83640_PHY_ID
120107. DP83811_ANEG_COMPLETE_INT_EN
120108. DP83811_DEVADDR
120109. DP83811_ENERGY_DET_INT_EN
120110. DP83811_ESD_EVENT_INT_EN
120111. DP83811_HW_RESET
120112. DP83811_JABBER_DET_INT_EN
120113. DP83811_LINK_QUAL_INT_EN
120114. DP83811_LINK_STAT_INT_EN
120115. DP83811_LPS_INT_EN
120116. DP83811_MS_TRAINING_INT_EN
120117. DP83811_NO_FRAME_INT_EN
120118. DP83811_OVERTEMP_INT_EN
120119. DP83811_OVERVOLTAGE_INT_EN
120120. DP83811_POLARITY_INT_EN
120121. DP83811_POR_DONE_INT_EN
120122. DP83811_RX_ERR_HF_INT_EN
120123. DP83811_SGMII_AUTO_NEG_EN
120124. DP83811_SGMII_EN
120125. DP83811_SGMII_SOFT_RESET
120126. DP83811_SGMII_TX_ERR_DIS
120127. DP83811_SLEEP_MODE_INT_EN
120128. DP83811_SW_RESET
120129. DP83811_TDR_AUTO
120130. DP83811_UNDERVOLTAGE_INT_EN
120131. DP83811_WOL_CLR_INDICATION
120132. DP83811_WOL_EN
120133. DP83811_WOL_INDICATION_SEL
120134. DP83811_WOL_INT_EN
120135. DP83811_WOL_MAGIC_EN
120136. DP83811_WOL_SECURE_ON
120137. DP83822_ANEG_COMPLETE_INT_EN
120138. DP83822_ANEG_ERR_INT_EN
120139. DP83822_DEVADDR
120140. DP83822_DUP_MODE_CHANGE_INT_EN
120141. DP83822_EEE_ERROR_CHANGE_INT_EN
120142. DP83822_ENERGY_DET_INT_EN
120143. DP83822_FALSE_CARRIER_HF_INT_EN
120144. DP83822_HW_RESET
120145. DP83822_JABBER_DET_INT_EN
120146. DP83822_LB_FIFO_INT_EN
120147. DP83822_LINK_QUAL_INT_EN
120148. DP83822_LINK_STAT_INT_EN
120149. DP83822_MDI_XOVER_INT_EN
120150. DP83822_PAGE_RX_INT_EN
120151. DP83822_PHYSCR_INTEN
120152. DP83822_PHYSCR_INT_OE
120153. DP83822_PHY_DRIVER
120154. DP83822_PHY_ID
120155. DP83822_RX_ERR_HF_INT_EN
120156. DP83822_SLEEP_MODE_INT_EN
120157. DP83822_SPEED_CHANGED_INT_EN
120158. DP83822_SW_RESET
120159. DP83822_WOL_CLR_INDICATION
120160. DP83822_WOL_EN
120161. DP83822_WOL_INDICATION_SEL
120162. DP83822_WOL_INT_EN
120163. DP83822_WOL_INT_STAT
120164. DP83822_WOL_MAGIC_EN
120165. DP83822_WOL_PKT_INT_EN
120166. DP83822_WOL_SECURE_ON
120167. DP83825I_PHY_ID
120168. DP83840
120169. DP83840A
120170. DP83840_CSCONFIG
120171. DP83848_INT_EN_MASK
120172. DP83848_MICR
120173. DP83848_MICR_INTEN
120174. DP83848_MICR_INT_OE
120175. DP83848_MISR
120176. DP83848_MISR_ANC_INT_EN
120177. DP83848_MISR_DUP_INT_EN
120178. DP83848_MISR_ED_INT_EN
120179. DP83848_MISR_FHF_INT_EN
120180. DP83848_MISR_LINK_INT_EN
120181. DP83848_MISR_LQM_INT_EN
120182. DP83848_MISR_RHF_INT_EN
120183. DP83848_MISR_SPD_INT_EN
120184. DP83848_PHY_DRIVER
120185. DP83865_INT_ANE_COMPLETED
120186. DP83865_INT_CLEAR
120187. DP83865_INT_LINK_CHANGE
120188. DP83865_INT_MASK
120189. DP83865_INT_MASK_DEFAULT
120190. DP83865_INT_REMOTE_FAULT
120191. DP83865_INT_STATUS
120192. DP83865_PHY_ID
120193. DP83867_10M_SGMII_CFG
120194. DP83867_10M_SGMII_RATE_ADAPT_MASK
120195. DP83867_CFG3
120196. DP83867_CFG3_INT_OE
120197. DP83867_CFG3_ROBUST_AUTO_MDIX
120198. DP83867_CFG4
120199. DP83867_CFG4_PORT_MIRROR_EN
120200. DP83867_CFG4_SGMII_ANEG_MASK
120201. DP83867_CFG4_SGMII_ANEG_TIMER_11MS
120202. DP83867_CFG4_SGMII_ANEG_TIMER_16MS
120203. DP83867_CFG4_SGMII_ANEG_TIMER_2US
120204. DP83867_CFG4_SGMII_ANEG_TIMER_800US
120205. DP83867_CLK_O_SEL_CHN_A_RCLK
120206. DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5
120207. DP83867_CLK_O_SEL_CHN_A_TCLK
120208. DP83867_CLK_O_SEL_CHN_B_RCLK
120209. DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5
120210. DP83867_CLK_O_SEL_CHN_B_TCLK
120211. DP83867_CLK_O_SEL_CHN_C_RCLK
120212. DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5
120213. DP83867_CLK_O_SEL_CHN_C_TCLK
120214. DP83867_CLK_O_SEL_CHN_D_RCLK
120215. DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5
120216. DP83867_CLK_O_SEL_CHN_D_TCLK
120217. DP83867_CLK_O_SEL_OFF
120218. DP83867_CLK_O_SEL_REF_CLK
120219. DP83867_CTRL
120220. DP83867_DEVADDR
120221. DP83867_FLD_THR_CFG
120222. DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK
120223. DP83867_IO_MUX_CFG
120224. DP83867_IO_MUX_CFG_CLK_O_DISABLE
120225. DP83867_IO_MUX_CFG_CLK_O_SEL_MASK
120226. DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT
120227. DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK
120228. DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX
120229. DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN
120230. DP83867_PHYCR_FIFO_DEPTH_3_B_NIB
120231. DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
120232. DP83867_PHYCR_FIFO_DEPTH_6_B_NIB
120233. DP83867_PHYCR_FIFO_DEPTH_8_B_NIB
120234. DP83867_PHYCR_FIFO_DEPTH_MASK
120235. DP83867_PHYCR_FIFO_DEPTH_MAX
120236. DP83867_PHYCR_FIFO_DEPTH_SHIFT
120237. DP83867_PHYCR_FORCE_LINK_GOOD
120238. DP83867_PHYCR_RESERVED_MASK
120239. DP83867_PHY_ID
120240. DP83867_PORT_MIRROING_DIS
120241. DP83867_PORT_MIRROING_EN
120242. DP83867_PORT_MIRROING_KEEP
120243. DP83867_RGMIICTL
120244. DP83867_RGMIIDCTL
120245. DP83867_RGMIIDCTL_1_25_NS
120246. DP83867_RGMIIDCTL_1_50_NS
120247. DP83867_RGMIIDCTL_1_75_NS
120248. DP83867_RGMIIDCTL_1_NS
120249. DP83867_RGMIIDCTL_250_PS
120250. DP83867_RGMIIDCTL_2_00_NS
120251. DP83867_RGMIIDCTL_2_25_NS
120252. DP83867_RGMIIDCTL_2_50_NS
120253. DP83867_RGMIIDCTL_2_75_NS
120254. DP83867_RGMIIDCTL_3_00_NS
120255. DP83867_RGMIIDCTL_3_25_NS
120256. DP83867_RGMIIDCTL_3_50_NS
120257. DP83867_RGMIIDCTL_3_75_NS
120258. DP83867_RGMIIDCTL_4_00_NS
120259. DP83867_RGMIIDCTL_500_PS
120260. DP83867_RGMIIDCTL_750_PS
120261. DP83867_RGMII_RX_CLK_DELAY_EN
120262. DP83867_RGMII_RX_CLK_DELAY_MAX
120263. DP83867_RGMII_RX_CLK_DELAY_SHIFT
120264. DP83867_RGMII_TX_CLK_DELAY_EN
120265. DP83867_RGMII_TX_CLK_DELAY_MAX
120266. DP83867_RGMII_TX_CLK_DELAY_SHIFT
120267. DP83867_SGMIICTL
120268. DP83867_SGMII_TYPE
120269. DP83867_STRAP_STS1
120270. DP83867_STRAP_STS1_RESERVED
120271. DP83867_STRAP_STS2
120272. DP83867_STRAP_STS2_CLK_SKEW_NONE
120273. DP83867_STRAP_STS2_CLK_SKEW_RX_MASK
120274. DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT
120275. DP83867_STRAP_STS2_CLK_SKEW_TX_MASK
120276. DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT
120277. DP83867_STRAP_STS2_STRAP_FLD
120278. DP83867_SW_RESET
120279. DP83867_SW_RESTART
120280. DP83TC811_PHY_ID
120281. DPAA2_CAAM_NAPI_WEIGHT
120282. DPAA2_CAAM_STORE_SIZE
120283. DPAA2_CLASSIFIER_DMA_SIZE
120284. DPAA2_CSCN_ALIGN
120285. DPAA2_CSCN_SIZE
120286. DPAA2_CSCN_STATE_CG
120287. DPAA2_DQ_STAT_EXPIRED
120288. DPAA2_DQ_STAT_FORCEELIGIBLE
120289. DPAA2_DQ_STAT_FQEMPTY
120290. DPAA2_DQ_STAT_HELDACTIVE
120291. DPAA2_DQ_STAT_ODPVALID
120292. DPAA2_DQ_STAT_VALIDFRAME
120293. DPAA2_DQ_STAT_VOLATILE
120294. DPAA2_ETH_BUFS_PER_CMD
120295. DPAA2_ETH_DBG_ROOT
120296. DPAA2_ETH_DEBUGFS_H
120297. DPAA2_ETH_DIST_ALL
120298. DPAA2_ETH_DIST_ETHDST
120299. DPAA2_ETH_DIST_ETHSRC
120300. DPAA2_ETH_DIST_ETHTYPE
120301. DPAA2_ETH_DIST_IPDST
120302. DPAA2_ETH_DIST_IPPROTO
120303. DPAA2_ETH_DIST_IPSRC
120304. DPAA2_ETH_DIST_L4DST
120305. DPAA2_ETH_DIST_L4SRC
120306. DPAA2_ETH_DIST_VLAN
120307. DPAA2_ETH_ENQUEUE_RETRIES
120308. DPAA2_ETH_L2_MAX_FRM
120309. DPAA2_ETH_LINK_STATE_REFRESH
120310. DPAA2_ETH_MAX_DPCONS
120311. DPAA2_ETH_MAX_FRAMES_PER_QUEUE
120312. DPAA2_ETH_MAX_MTU
120313. DPAA2_ETH_MAX_NETDEV_QUEUES
120314. DPAA2_ETH_MAX_QUEUES
120315. DPAA2_ETH_MAX_RX_QUEUES
120316. DPAA2_ETH_MAX_SG_ENTRIES
120317. DPAA2_ETH_MAX_TCS
120318. DPAA2_ETH_MAX_TX_QUEUES
120319. DPAA2_ETH_MFL
120320. DPAA2_ETH_NUM_BUFS
120321. DPAA2_ETH_NUM_EXTRA_STATS
120322. DPAA2_ETH_NUM_STATS
120323. DPAA2_ETH_REFILL_THRESH
120324. DPAA2_ETH_RX_BUF_ALIGN
120325. DPAA2_ETH_RX_BUF_ALIGN_REV1
120326. DPAA2_ETH_RX_BUF_RAW_SIZE
120327. DPAA2_ETH_RX_BUF_SIZE
120328. DPAA2_ETH_RX_BUF_TAILROOM
120329. DPAA2_ETH_RX_DIST_CLS
120330. DPAA2_ETH_RX_DIST_HASH
120331. DPAA2_ETH_RX_HWA_SIZE
120332. DPAA2_ETH_STORE_SIZE
120333. DPAA2_ETH_SWA_SG
120334. DPAA2_ETH_SWA_SINGLE
120335. DPAA2_ETH_SWA_SIZE
120336. DPAA2_ETH_SWA_XDP
120337. DPAA2_ETH_TAILDROP_THRESH
120338. DPAA2_ETH_TXCONF_PER_NAPI
120339. DPAA2_ETH_TX_BUF_ALIGN
120340. DPAA2_ETH_TX_HWA_SIZE
120341. DPAA2_FAEAD_A2V
120342. DPAA2_FAEAD_A4V
120343. DPAA2_FAEAD_EBDDV
120344. DPAA2_FAEAD_OFFSET
120345. DPAA2_FAEAD_UPD
120346. DPAA2_FAEAD_UPDV
120347. DPAA2_FAS_BC
120348. DPAA2_FAS_BLE
120349. DPAA2_FAS_DISC
120350. DPAA2_FAS_EOFHE
120351. DPAA2_FAS_FLE
120352. DPAA2_FAS_FPE
120353. DPAA2_FAS_ISP
120354. DPAA2_FAS_KSE
120355. DPAA2_FAS_L3CE
120356. DPAA2_FAS_L3CV
120357. DPAA2_FAS_L4CE
120358. DPAA2_FAS_L4CV
120359. DPAA2_FAS_MC
120360. DPAA2_FAS_MNLE
120361. DPAA2_FAS_MS
120362. DPAA2_FAS_OFFSET
120363. DPAA2_FAS_PHE
120364. DPAA2_FAS_PIEE
120365. DPAA2_FAS_PTE
120366. DPAA2_FAS_PTP
120367. DPAA2_FAS_RX_ERR_MASK
120368. DPAA2_FAS_SIZE
120369. DPAA2_FAS_TIDE
120370. DPAA2_FD_CTRL_ASAL
120371. DPAA2_FD_FRC_FAEADV
120372. DPAA2_FD_FRC_FAIADV
120373. DPAA2_FD_FRC_FAICFDV
120374. DPAA2_FD_FRC_FAPRV
120375. DPAA2_FD_FRC_FASV
120376. DPAA2_FD_FRC_FASWOV
120377. DPAA2_FD_RX_ERR_MASK
120378. DPAA2_FD_TX_ERR_MASK
120379. DPAA2_IO_ANY_CPU
120380. DPAA2_MFL
120381. DPAA2_PTP_CLK_PERIOD_NS
120382. DPAA2_RXH_DEFAULT
120383. DPAA2_RXH_SUPPORTED
120384. DPAA2_RX_FQ
120385. DPAA2_SEC_CONG_ENTRY_THRESH
120386. DPAA2_SEC_CONG_EXIT_THRESH
120387. DPAA2_TS_OFFSET
120388. DPAA2_TX_CONF_FQ
120389. DPAA2_WRIOP_VERSION
120390. DPAA_ASSERT
120391. DPAA_BPS_NUM
120392. DPAA_BP_RAW_SIZE
120393. DPAA_BUFF_RELEASE_MAX
120394. DPAA_CS_THRESHOLD_10G
120395. DPAA_CS_THRESHOLD_1G
120396. DPAA_ENQUEUE_RETRIES
120397. DPAA_ETH_PCD_RXQ_NUM
120398. DPAA_ETH_TXQ_NUM
120399. DPAA_FD_DATA_ALIGNMENT
120400. DPAA_FQ_TD
120401. DPAA_GENALLOC_OFF
120402. DPAA_HASH_RESULTS_SIZE
120403. DPAA_INGRESS_CS_THRESHOLD
120404. DPAA_MSG_DEFAULT
120405. DPAA_PARSE_RESULTS_SIZE
120406. DPAA_POLL_MAX
120407. DPAA_PORTAL_CE
120408. DPAA_PORTAL_CI
120409. DPAA_RX_PRIV_DATA_SIZE
120410. DPAA_SGT_MAX_ENTRIES
120411. DPAA_SGT_SIZE
120412. DPAA_STATS_GLOBAL_LEN
120413. DPAA_STATS_PERCPU_LEN
120414. DPAA_TC_NUM
120415. DPAA_TC_TXQ_NUM
120416. DPAA_TIME_STAMP_SIZE
120417. DPAA_TX_PRIV_DATA_SIZE
120418. DPAUX_CTXSW
120419. DPAUX_DP_AUXADDR
120420. DPAUX_DP_AUXCTL
120421. DPAUX_DP_AUXCTL_CMDLEN
120422. DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY
120423. DPAUX_DP_AUXCTL_CMD_AUX_RD
120424. DPAUX_DP_AUXCTL_CMD_AUX_WR
120425. DPAUX_DP_AUXCTL_CMD_I2C_RD
120426. DPAUX_DP_AUXCTL_CMD_I2C_RQ
120427. DPAUX_DP_AUXCTL_CMD_I2C_WR
120428. DPAUX_DP_AUXCTL_CMD_MOT_RD
120429. DPAUX_DP_AUXCTL_CMD_MOT_RQ
120430. DPAUX_DP_AUXCTL_CMD_MOT_WR
120431. DPAUX_DP_AUXCTL_TRANSACTREQ
120432. DPAUX_DP_AUXDATA_READ
120433. DPAUX_DP_AUXDATA_WRITE
120434. DPAUX_DP_AUXSTAT
120435. DPAUX_DP_AUXSTAT_HPD_STATUS
120436. DPAUX_DP_AUXSTAT_NO_STOP_ERROR
120437. DPAUX_DP_AUXSTAT_REPLY_MASK
120438. DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK
120439. DPAUX_DP_AUXSTAT_RX_ERROR
120440. DPAUX_DP_AUXSTAT_SINKSTAT_ERROR
120441. DPAUX_DP_AUXSTAT_TIMEOUT_ERROR
120442. DPAUX_DP_AUX_CONFIG
120443. DPAUX_DP_AUX_SINKSTAT_HI
120444. DPAUX_DP_AUX_SINKSTAT_LO
120445. DPAUX_HPD_CONFIG
120446. DPAUX_HPD_CONFIG_PLUG_MIN_TIME
120447. DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME
120448. DPAUX_HPD_IRQ_CONFIG
120449. DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME
120450. DPAUX_HYBRID_PADCTL
120451. DPAUX_HYBRID_PADCTL_AUX_CMH
120452. DPAUX_HYBRID_PADCTL_AUX_DRVI
120453. DPAUX_HYBRID_PADCTL_AUX_DRVZ
120454. DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV
120455. DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV
120456. DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV
120457. DPAUX_HYBRID_PADCTL_MODE_AUX
120458. DPAUX_HYBRID_PADCTL_MODE_I2C
120459. DPAUX_HYBRID_SPARE
120460. DPAUX_HYBRID_SPARE_PAD_POWER_DOWN
120461. DPAUX_INTR_AUX
120462. DPAUX_INTR_AUX_DONE
120463. DPAUX_INTR_EN_AUX
120464. DPAUX_INTR_IRQ_EVENT
120465. DPAUX_INTR_PLUG_EVENT
120466. DPAUX_INTR_UNPLUG_EVENT
120467. DPAUX_PADCTL_FUNC_AUX
120468. DPAUX_PADCTL_FUNC_I2C
120469. DPAUX_PADCTL_FUNC_OFF
120470. DPAUX_SCRATCH_REG0
120471. DPAUX_SCRATCH_REG1
120472. DPAUX_SCRATCH_REG2
120473. DPA_CLK_100M
120474. DPA_CLK_150M
120475. DPA_CLK_30M
120476. DPA_CLK_50M
120477. DPA_CLK_70M
120478. DPA_CLK_RANGE_100_150M
120479. DPA_CLK_RANGE_150M
120480. DPA_CLK_RANGE_30M
120481. DPA_CLK_RANGE_30_50M
120482. DPA_CLK_RANGE_50_70M
120483. DPA_CLK_RANGE_70_100M
120484. DPA_CMD
120485. DPA_MASK_VBLANK_SRD
120486. DPA_RANGE
120487. DPA_RESOURCE_ADJUSTED
120488. DPBEXP
120489. DPBMUNIT_CLOCK_GATE_DISABLE
120490. DPBP_CMD
120491. DPBP_CMDID_CLOSE
120492. DPBP_CMDID_DISABLE
120493. DPBP_CMDID_ENABLE
120494. DPBP_CMDID_GET_ATTR
120495. DPBP_CMDID_OPEN
120496. DPBP_CMDID_RESET
120497. DPBP_CMD_BASE_VERSION
120498. DPBP_CMD_ID_OFFSET
120499. DPBP_ENABLE
120500. DPBP_VER_MAJOR
120501. DPBP_VER_MINOR
120502. DPBUNIT_CLOCK_GATE_DISABLE
120503. DPB_AUX_CH_CTL
120504. DPB_AUX_CH_DATA1
120505. DPB_AUX_CH_DATA2
120506. DPB_AUX_CH_DATA3
120507. DPB_AUX_CH_DATA4
120508. DPB_AUX_CH_DATA5
120509. DPC
120510. DPCD_AUDIO_TEST_PATTERN_PERIOD_12
120511. DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
120512. DPCD_AUDIO_TEST_PATTERN_PERIOD_192
120513. DPCD_AUDIO_TEST_PATTERN_PERIOD_24
120514. DPCD_AUDIO_TEST_PATTERN_PERIOD_3
120515. DPCD_AUDIO_TEST_PATTERN_PERIOD_384
120516. DPCD_AUDIO_TEST_PATTERN_PERIOD_48
120517. DPCD_AUDIO_TEST_PATTERN_PERIOD_6
120518. DPCD_AUDIO_TEST_PATTERN_PERIOD_768
120519. DPCD_AUDIO_TEST_PATTERN_PERIOD_96
120520. DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED
120521. DPCD_CP_READY_MASK
120522. DPCD_ENHANCED_FRAME_CAP
120523. DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR
120524. DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR
120525. DPCD_HEADER_SIZE
120526. DPCD_INTERLANE_ALIGN_DONE
120527. DPCD_LANE0_1_STATUS
120528. DPCD_LANE2_3_STATUS
120529. DPCD_LANES_CR_DONE
120530. DPCD_LANES_EQ_DONE
120531. DPCD_LANE_ALIGN_STATUS_UPDATED
120532. DPCD_LANE_COUNT_SET
120533. DPCD_LC00_LINK_BW_SET
120534. DPCD_LC01
120535. DPCD_LC01_ENHANCED_FRAME_EN
120536. DPCD_LC01_LANE_COUNT_SET
120537. DPCD_LC02
120538. DPCD_LC02_TRAINING_PATTERN_SET
120539. DPCD_LC03
120540. DPCD_LC03_MAX_PRE_EMPHASIS_REACHED
120541. DPCD_LC03_MAX_SWING_REACHED
120542. DPCD_LC03_PRE_EMPHASIS_SET
120543. DPCD_LC03_VOLTAGE_SWING_SET
120544. DPCD_LC0F
120545. DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED
120546. DPCD_LC0F_LANE0_POST_CURSOR2_SET
120547. DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED
120548. DPCD_LC0F_LANE1_POST_CURSOR2_SET
120549. DPCD_LC10
120550. DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED
120551. DPCD_LC10_LANE2_POST_CURSOR2_SET
120552. DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED
120553. DPCD_LC10_LANE3_POST_CURSOR2_SET
120554. DPCD_LINK_PRE_EMPHASIS_MAX
120555. DPCD_LINK_TRAINING_DISABLED
120556. DPCD_LINK_VOLTAGE_MAX
120557. DPCD_LS02
120558. DPCD_LS02_LANE0_CHANNEL_EQ_DONE
120559. DPCD_LS02_LANE0_CR_DONE
120560. DPCD_LS02_LANE0_SYMBOL_LOCKED
120561. DPCD_LS02_LANE1_CHANNEL_EQ_DONE
120562. DPCD_LS02_LANE1_CR_DONE
120563. DPCD_LS02_LANE1_SYMBOL_LOCKED
120564. DPCD_LS03
120565. DPCD_LS03_LANE2_CHANNEL_EQ_DONE
120566. DPCD_LS03_LANE2_CR_DONE
120567. DPCD_LS03_LANE2_SYMBOL_LOCKED
120568. DPCD_LS03_LANE3_CHANNEL_EQ_DONE
120569. DPCD_LS03_LANE3_CR_DONE
120570. DPCD_LS03_LANE3_SYMBOL_LOCKED
120571. DPCD_LS04
120572. DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED
120573. DPCD_LS04_INTERLANE_ALIGN_DONE
120574. DPCD_LS04_LINK_STATUS_UPDATED
120575. DPCD_LS06
120576. DPCD_LS06_LANE0_PRE_EMPHASIS
120577. DPCD_LS06_LANE0_VOLTAGE_SWING
120578. DPCD_LS06_LANE1_PRE_EMPHASIS
120579. DPCD_LS06_LANE1_VOLTAGE_SWING
120580. DPCD_LS07
120581. DPCD_LS07_LANE2_PRE_EMPHASIS
120582. DPCD_LS07_LANE2_VOLTAGE_SWING
120583. DPCD_LS07_LANE3_PRE_EMPHASIS
120584. DPCD_LS07_LANE3_VOLTAGE_SWING
120585. DPCD_LS0C
120586. DPCD_LS0C_LANE0_POST_CURSOR2
120587. DPCD_LS0C_LANE1_POST_CURSOR2
120588. DPCD_LS0C_LANE2_POST_CURSOR2
120589. DPCD_LS0C_LANE3_POST_CURSOR2
120590. DPCD_MAX_LANE_COUNT
120591. DPCD_MAX_LINK_RATE
120592. DPCD_PRE_EMPHASIS_GET
120593. DPCD_PRE_EMPHASIS_SET
120594. DPCD_RC00_DPCD_REV
120595. DPCD_RC01_MAX_LINK_RATE
120596. DPCD_RC02
120597. DPCD_RC02_ENHANCED_FRAME_CAP
120598. DPCD_RC02_MAX_LANE_COUNT
120599. DPCD_RC02_TPS3_SUPPORTED
120600. DPCD_RC03
120601. DPCD_RC03_MAX_DOWNSPREAD
120602. DPCD_RC0E_AUX_RD_INTERVAL
120603. DPCD_REV
120604. DPCD_REV_10
120605. DPCD_REV_11
120606. DPCD_REV_12
120607. DPCD_REV_13
120608. DPCD_REV_14
120609. DPCD_SC00
120610. DPCD_SC00_SET_POWER
120611. DPCD_SC00_SET_POWER_D0
120612. DPCD_SC00_SET_POWER_D3
120613. DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR
120614. DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR
120615. DPCD_SET_SS_CNTL_TBL_ADDR
120616. DPCD_SET_TRAINING_PATTERN0_TBL_ADDR
120617. DPCD_SET_TRAINING_PATTERN2_TBL_ADDR
120618. DPCD_SINK_COUNT
120619. DPCD_SINK_IN_SYNC
120620. DPCD_SINK_STATUS
120621. DPCD_SIZE
120622. DPCD_SYMBOL_LOCKED
120623. DPCD_TRAINING_PATTERN_1
120624. DPCD_TRAINING_PATTERN_2
120625. DPCD_TRAINING_PATTERN_3
120626. DPCD_TRAINING_PATTERN_4
120627. DPCD_TRAINING_PATTERN_SET
120628. DPCD_TRAINING_PATTERN_SET_MASK
120629. DPCD_TRAINING_PATTERN_VIDEOIDLE
120630. DPCD_VOLTAGE_SWING_GET
120631. DPCD_VOLTAGE_SWING_SET
120632. DPCIA_A_MASK
120633. DPCIA_A_SHIFT
120634. DPCIC_BE_MASK
120635. DPCIC_C_IOREAD
120636. DPCIC_C_IOWRITE
120637. DPCIC_C_MASK
120638. DPCID_D_MASK
120639. DPCID_D_SHIFT
120640. DPCLKA_CFGCR0
120641. DPCLKA_CFGCR0_DDI_CLK_OFF
120642. DPCLKA_CFGCR0_DDI_CLK_SEL
120643. DPCLKA_CFGCR0_DDI_CLK_SEL_MASK
120644. DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT
120645. DPCM_MAX_BE_USERS
120646. DPCM_SELECTABLE
120647. DPCNST
120648. DPCON_CMD
120649. DPCON_CMDID_CLOSE
120650. DPCON_CMDID_DISABLE
120651. DPCON_CMDID_ENABLE
120652. DPCON_CMDID_GET_ATTR
120653. DPCON_CMDID_OPEN
120654. DPCON_CMDID_RESET
120655. DPCON_CMDID_SET_NOTIFICATION
120656. DPCON_CMD_BASE_VERSION
120657. DPCON_CMD_ID_OFFSET
120658. DPCON_ENABLE
120659. DPCON_INVALID_DPIO_ID
120660. DPCON_VER_MAJOR
120661. DPCON_VER_MINOR
120662. DPCR
120663. DPCSRX_BPHY_PCS_RX0_CLK
120664. DPCSRX_BPHY_PCS_RX1_CLK
120665. DPCSRX_BPHY_PCS_RX2_CLK
120666. DPCSRX_BPHY_PCS_RX3_CLK
120667. DPCSRX_DBG_CFGCLK_SEL
120668. DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER
120669. DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE
120670. DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF
120671. DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF
120672. DPCSRX_DBG_RX_SYMCLK_SEL_INT
120673. DPCSRX_DBG_RX_SYMCLK_SEL_OUT0
120674. DPCSRX_DBG_RX_SYMCLK_SEL_OUT1
120675. DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL
120676. DPCSRX_RX_SYMCLK_SEL
120677. DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
120678. DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
120679. DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK
120680. DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
120681. DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
120682. DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
120683. DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK
120684. DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
120685. DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
120686. DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
120687. DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK
120688. DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
120689. DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
120690. DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
120691. DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK
120692. DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
120693. DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
120694. DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
120695. DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK
120696. DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
120697. DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK
120698. DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT
120699. DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK
120700. DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT
120701. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK
120702. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT
120703. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK
120704. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT
120705. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK
120706. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT
120707. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK
120708. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT
120709. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK
120710. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT
120711. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK
120712. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT
120713. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK
120714. DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT
120715. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK
120716. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT
120717. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK
120718. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT
120719. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK
120720. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT
120721. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK
120722. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT
120723. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK
120724. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT
120725. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK
120726. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT
120727. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK
120728. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT
120729. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK
120730. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT
120731. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK
120732. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT
120733. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK
120734. DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT
120735. DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK
120736. DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT
120737. DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK
120738. DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT
120739. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK
120740. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT
120741. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK
120742. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
120743. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK
120744. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT
120745. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK
120746. DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT
120747. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK
120748. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT
120749. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK
120750. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT
120751. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK
120752. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT
120753. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK
120754. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT
120755. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK
120756. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT
120757. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK
120758. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT
120759. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK
120760. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT
120761. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK
120762. DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT
120763. DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK
120764. DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT
120765. DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK
120766. DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT
120767. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK
120768. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT
120769. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK
120770. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT
120771. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK
120772. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT
120773. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK
120774. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT
120775. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK
120776. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT
120777. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK
120778. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT
120779. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK
120780. DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT
120781. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK
120782. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT
120783. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK
120784. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT
120785. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK
120786. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT
120787. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK
120788. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT
120789. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK
120790. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT
120791. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK
120792. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT
120793. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK
120794. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT
120795. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK
120796. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT
120797. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK
120798. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT
120799. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK
120800. DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT
120801. DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK
120802. DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT
120803. DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK
120804. DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT
120805. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK
120806. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT
120807. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK
120808. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
120809. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK
120810. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT
120811. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK
120812. DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT
120813. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK
120814. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT
120815. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK
120816. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT
120817. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK
120818. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT
120819. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK
120820. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT
120821. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK
120822. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT
120823. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK
120824. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT
120825. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK
120826. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT
120827. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK
120828. DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT
120829. DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK
120830. DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT
120831. DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK
120832. DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT
120833. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK
120834. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT
120835. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK
120836. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT
120837. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK
120838. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT
120839. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK
120840. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT
120841. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK
120842. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT
120843. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK
120844. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT
120845. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK
120846. DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT
120847. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK
120848. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT
120849. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK
120850. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT
120851. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK
120852. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT
120853. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK
120854. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT
120855. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK
120856. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT
120857. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK
120858. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT
120859. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK
120860. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT
120861. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK
120862. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT
120863. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK
120864. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT
120865. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK
120866. DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT
120867. DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK
120868. DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT
120869. DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK
120870. DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT
120871. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK
120872. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT
120873. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK
120874. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
120875. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK
120876. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT
120877. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK
120878. DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT
120879. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK
120880. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT
120881. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK
120882. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT
120883. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK
120884. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT
120885. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK
120886. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT
120887. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK
120888. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT
120889. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK
120890. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT
120891. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK
120892. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT
120893. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK
120894. DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT
120895. DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK
120896. DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT
120897. DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK
120898. DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT
120899. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK
120900. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT
120901. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK
120902. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT
120903. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK
120904. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT
120905. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK
120906. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT
120907. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK
120908. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT
120909. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK
120910. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT
120911. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK
120912. DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT
120913. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK
120914. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT
120915. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK
120916. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT
120917. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK
120918. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT
120919. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK
120920. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT
120921. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK
120922. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT
120923. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK
120924. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT
120925. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK
120926. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT
120927. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK
120928. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT
120929. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK
120930. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT
120931. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK
120932. DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT
120933. DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK
120934. DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT
120935. DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK
120936. DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT
120937. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK
120938. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT
120939. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK
120940. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
120941. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK
120942. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT
120943. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK
120944. DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT
120945. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK
120946. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT
120947. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK
120948. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT
120949. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK
120950. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT
120951. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK
120952. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT
120953. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK
120954. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT
120955. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK
120956. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT
120957. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK
120958. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT
120959. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK
120960. DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT
120961. DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK
120962. DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT
120963. DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK
120964. DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT
120965. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK
120966. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT
120967. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK
120968. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT
120969. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK
120970. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT
120971. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK
120972. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT
120973. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK
120974. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT
120975. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK
120976. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT
120977. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK
120978. DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT
120979. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK
120980. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT
120981. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK
120982. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT
120983. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK
120984. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT
120985. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK
120986. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT
120987. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK
120988. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT
120989. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK
120990. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT
120991. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK
120992. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT
120993. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK
120994. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT
120995. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK
120996. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT
120997. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK
120998. DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT
120999. DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK
121000. DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT
121001. DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK
121002. DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT
121003. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK
121004. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT
121005. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK
121006. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
121007. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK
121008. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT
121009. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK
121010. DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT
121011. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK
121012. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT
121013. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK
121014. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT
121015. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK
121016. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT
121017. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK
121018. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT
121019. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK
121020. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT
121021. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK
121022. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT
121023. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK
121024. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT
121025. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK
121026. DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT
121027. DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK
121028. DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT
121029. DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK
121030. DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT
121031. DPCSTX_CBUS_CNTL__DPCS_PHY_MASTER_REQ_DELAY_MASK
121032. DPCSTX_CBUS_CNTL__DPCS_PHY_MASTER_REQ_DELAY__SHIFT
121033. DPCSTX_DBG_CFGCLK_SEL
121034. DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER
121035. DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE
121036. DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF
121037. DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF
121038. DPCSTX_DBG_CLOCK_SEL
121039. DPCSTX_DBG_CLOCK_SEL_DC_CFGCLK
121040. DPCSTX_DBG_CLOCK_SEL_PHY_CFGCLK
121041. DPCSTX_DBG_CLOCK_SEL_TXSYMCLK
121042. DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD
121043. DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT
121044. DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0
121045. DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1
121046. DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2
121047. DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3
121048. DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR
121049. DPCSTX_DBG_TX_SYMCLK_SEL_IN0
121050. DPCSTX_DBG_TX_SYMCLK_SEL_IN1
121051. DPCSTX_DEBUG_CONFIG__DPCS_DBG_BLOCK_SEL_MASK
121052. DPCSTX_DEBUG_CONFIG__DPCS_DBG_BLOCK_SEL__SHIFT
121053. DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK
121054. DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT
121055. DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK
121056. DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT
121057. DPCSTX_DEBUG_CONFIG__DPCS_DBG_CLOCK_SEL_MASK
121058. DPCSTX_DEBUG_CONFIG__DPCS_DBG_CLOCK_SEL__SHIFT
121059. DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK
121060. DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT
121061. DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK
121062. DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT
121063. DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK
121064. DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT
121065. DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK
121066. DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT
121067. DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK
121068. DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT
121069. DPCSTX_DVI_LINK_MODE
121070. DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER
121071. DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER
121072. DPCSTX_DVI_LINK_MODE_NORMAL
121073. DPCSTX_INDEX_MODE_ADDR__DPCS_INDEX_MODE_ADDR_MASK
121074. DPCSTX_INDEX_MODE_ADDR__DPCS_INDEX_MODE_ADDR__SHIFT
121075. DPCSTX_INDEX_MODE_DATA__DPCS_INDEX_MODE_DATA_MASK
121076. DPCSTX_INDEX_MODE_DATA__DPCS_INDEX_MODE_DATA__SHIFT
121077. DPCSTX_PHY_CNTL__DPCS_PHY_RESET_MASK
121078. DPCSTX_PHY_CNTL__DPCS_PHY_RESET__SHIFT
121079. DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK
121080. DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT
121081. DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK
121082. DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT
121083. DPCSTX_REG_ERROR_STATUS__DPCS_REG_ERROR_CLR_MASK
121084. DPCSTX_REG_ERROR_STATUS__DPCS_REG_ERROR_CLR__SHIFT
121085. DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_ERROR_MASK_MASK
121086. DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_ERROR_MASK__SHIFT
121087. DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_OVERFLOW_MASK
121088. DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_OVERFLOW__SHIFT
121089. DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA_MASK
121090. DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA__SHIFT
121091. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK
121092. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT
121093. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK
121094. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
121095. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX0_EN_MASK
121096. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX0_EN__SHIFT
121097. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX1_EN_MASK
121098. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX1_EN__SHIFT
121099. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX2_EN_MASK
121100. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX2_EN__SHIFT
121101. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX3_EN_MASK
121102. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX3_EN__SHIFT
121103. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK
121104. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT
121105. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK
121106. DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT
121107. DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK
121108. DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT
121109. DPCSTX_TX_CNTL__DPCS_TX_DVI_LINK_MODE_MASK
121110. DPCSTX_TX_CNTL__DPCS_TX_DVI_LINK_MODE__SHIFT
121111. DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK
121112. DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT
121113. DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK
121114. DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT
121115. DPCSTX_TX_CNTL__DPCS_TX_FIFO_WR_START_DELAY_MASK
121116. DPCSTX_TX_CNTL__DPCS_TX_FIFO_WR_START_DELAY__SHIFT
121117. DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_MASK
121118. DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN_MASK
121119. DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN__SHIFT
121120. DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE__SHIFT
121121. DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK
121122. DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT
121123. DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK
121124. DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT
121125. DPCSTX_TX_CNTL__DPCS_TX_RESYNC_MASK
121126. DPCSTX_TX_CNTL__DPCS_TX_RESYNC__SHIFT
121127. DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK
121128. DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT
121129. DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_DELAY_MASK
121130. DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_DELAY__SHIFT
121131. DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_EN_MASK
121132. DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_EN__SHIFT
121133. DPCSTX_TX_ERROR_STATUS__DPCS_TX0_FIFO_ERROR_MASK
121134. DPCSTX_TX_ERROR_STATUS__DPCS_TX0_FIFO_ERROR__SHIFT
121135. DPCSTX_TX_ERROR_STATUS__DPCS_TX1_FIFO_ERROR_MASK
121136. DPCSTX_TX_ERROR_STATUS__DPCS_TX1_FIFO_ERROR__SHIFT
121137. DPCSTX_TX_ERROR_STATUS__DPCS_TX2_FIFO_ERROR_MASK
121138. DPCSTX_TX_ERROR_STATUS__DPCS_TX2_FIFO_ERROR__SHIFT
121139. DPCSTX_TX_ERROR_STATUS__DPCS_TX3_FIFO_ERROR_MASK
121140. DPCSTX_TX_ERROR_STATUS__DPCS_TX3_FIFO_ERROR__SHIFT
121141. DPCSTX_TX_ERROR_STATUS__DPCS_TX_ERROR_CLR_MASK
121142. DPCSTX_TX_ERROR_STATUS__DPCS_TX_ERROR_CLR__SHIFT
121143. DPCSTX_TX_ERROR_STATUS__DPCS_TX_FIFO_ERROR_MASK_MASK
121144. DPCSTX_TX_ERROR_STATUS__DPCS_TX_FIFO_ERROR_MASK__SHIFT
121145. DPCSTX_TX_SYMCLK_DIV2_SEL
121146. DPCSTX_TX_SYMCLK_SEL
121147. DPCS_BASE__INST0_SEG0
121148. DPCS_BASE__INST0_SEG1
121149. DPCS_BASE__INST0_SEG2
121150. DPCS_BASE__INST0_SEG3
121151. DPCS_BASE__INST0_SEG4
121152. DPCS_BASE__INST1_SEG0
121153. DPCS_BASE__INST1_SEG1
121154. DPCS_BASE__INST1_SEG2
121155. DPCS_BASE__INST1_SEG3
121156. DPCS_BASE__INST1_SEG4
121157. DPCS_BASE__INST2_SEG0
121158. DPCS_BASE__INST2_SEG1
121159. DPCS_BASE__INST2_SEG2
121160. DPCS_BASE__INST2_SEG3
121161. DPCS_BASE__INST2_SEG4
121162. DPCS_BASE__INST3_SEG0
121163. DPCS_BASE__INST3_SEG1
121164. DPCS_BASE__INST3_SEG2
121165. DPCS_BASE__INST3_SEG3
121166. DPCS_BASE__INST3_SEG4
121167. DPCS_BASE__INST4_SEG0
121168. DPCS_BASE__INST4_SEG1
121169. DPCS_BASE__INST4_SEG2
121170. DPCS_BASE__INST4_SEG3
121171. DPCS_BASE__INST4_SEG4
121172. DPCS_BASE__INST5_SEG0
121173. DPCS_BASE__INST5_SEG1
121174. DPCS_BASE__INST5_SEG2
121175. DPCS_BASE__INST5_SEG3
121176. DPCS_BASE__INST5_SEG4
121177. DPCS_BASE__INST6_SEG0
121178. DPCS_BASE__INST6_SEG1
121179. DPCS_BASE__INST6_SEG2
121180. DPCS_BASE__INST6_SEG3
121181. DPCS_BASE__INST6_SEG4
121182. DPCTRL_DEBUG_A
121183. DPCTRL_DEBUG_B
121184. DPCUNIT_CLOCK_GATE_DISABLE
121185. DPC_AEN
121186. DPC_AUX_CH_CTL
121187. DPC_AUX_CH_DATA1
121188. DPC_AUX_CH_DATA2
121189. DPC_AUX_CH_DATA3
121190. DPC_AUX_CH_DATA4
121191. DPC_AUX_CH_DATA5
121192. DPC_BUFFER_SIZE
121193. DPC_FATAL
121194. DPC_GET_DHCP_IP_ADDR
121195. DPC_HA_NEED_QUIESCENT
121196. DPC_HA_UNRECOVERABLE
121197. DPC_ISNS_RESTART
121198. DPC_LINK_CHANGED
121199. DPC_POST_IDC_ACK
121200. DPC_RELOGIN_DEVICE
121201. DPC_RESET_ACTIVE
121202. DPC_RESET_HA
121203. DPC_RESET_HA_FW_CONTEXT
121204. DPC_RESET_HA_INTR
121205. DPC_RESTORE_ACB
121206. DPC_RETRY_RESET_HA
121207. DPC_SYSFS_DDB_EXPORT
121208. DPD
121209. DPD1
121210. DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK
121211. DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT
121212. DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK
121213. DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT
121214. DPDBG_CLK_FORCE_EN
121215. DPDBG_CLK_FORCE_EN_DISABLE
121216. DPDBG_CLK_FORCE_EN_ENABLE
121217. DPDBG_CNTL__DPDBG_ENABLE_MASK
121218. DPDBG_CNTL__DPDBG_ENABLE__SHIFT
121219. DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK
121220. DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT
121221. DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK
121222. DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT
121223. DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK
121224. DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT
121225. DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK
121226. DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT
121227. DPDBG_DISABLE
121228. DPDBG_EN
121229. DPDBG_ENABLE
121230. DPDBG_ERROR_DETECTION_MODE
121231. DPDBG_ERROR_DETECTION_MODE_CSC
121232. DPDBG_ERROR_DETECTION_MODE_RS_ENCODING
121233. DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK
121234. DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK
121235. DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE
121236. DPDBG_FIFO_OVERFLOW_INT_CLEAR
121237. DPDBG_FIFO_OVERFLOW_INT_DISABLE
121238. DPDBG_FIFO_OVERFLOW_INT_ENABLE
121239. DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED
121240. DPDBG_FIFO_OVERFLOW_INT_NO_ACK
121241. DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED
121242. DPDBG_INPUT_DISABLE
121243. DPDBG_INPUT_EN
121244. DPDBG_INPUT_ENABLE
121245. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK
121246. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT
121247. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK
121248. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT
121249. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK
121250. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT
121251. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK
121252. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT
121253. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK
121254. DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT
121255. DPDBG_SOFT_RESET
121256. DPDBG_SOFT_RESET_0
121257. DPDBG_SOFT_RESET_1
121258. DPDC
121259. DPDMA_REF
121260. DPDNORMX
121261. DPDNORMY
121262. DPDNORMZ
121263. DPDNORMx
121264. DPD_BIT
121265. DPD_DISABLE
121266. DPD_ENABLE
121267. DPD_EN_MASK
121268. DPD_EN_SHIFT
121269. DPD_SAMPLE
121270. DPD_SAMPLE_DISABLE
121271. DPD_SAMPLE_ENABLE
121272. DPE
121273. DPE1
121274. DPERR
121275. DPERR_DET
121276. DPFC_CB_BASE
121277. DPFC_CHICKEN
121278. DPFC_COMP_SEG_MASK
121279. DPFC_COMP_SEG_SHIFT
121280. DPFC_CONTROL
121281. DPFC_CPU_FENCE_OFFSET
121282. DPFC_CTL_EN
121283. DPFC_CTL_FENCE_EN
121284. DPFC_CTL_LIMIT_1X
121285. DPFC_CTL_LIMIT_2X
121286. DPFC_CTL_LIMIT_4X
121287. DPFC_CTL_PERSISTENT_MODE
121288. DPFC_CTL_PLANE
121289. DPFC_FENCE_YOFF
121290. DPFC_HT_MODIFY
121291. DPFC_INVAL_SEG_MASK
121292. DPFC_INVAL_SEG_SHIFT
121293. DPFC_RECOMP_CTL
121294. DPFC_RECOMP_STALL_EN
121295. DPFC_RECOMP_STALL_WM_MASK
121296. DPFC_RECOMP_STALL_WM_SHIFT
121297. DPFC_RECOMP_TIMER_COUNT_MASK
121298. DPFC_RECOMP_TIMER_COUNT_SHIFT
121299. DPFC_RESERVED
121300. DPFC_SR_EN
121301. DPFC_STATUS
121302. DPFC_STATUS2
121303. DPFE_BE_MAGIC
121304. DPFE_CMD_GET_INFO
121305. DPFE_CMD_GET_REFRESH
121306. DPFE_CMD_GET_VENDOR
121307. DPFE_CMD_MAX
121308. DPFE_LE_MAGIC
121309. DPFE_MSG_TYPE_COMMAND
121310. DPFE_MSG_TYPE_RESPONSE
121311. DPFP
121312. DPFROMREG
121313. DPFR_GATING_DIS
121314. DPFUNIT_CLOCK_GATE_DISABLE
121315. DPFX
121316. DPF_GATING_DIS
121317. DPF_RAM_GATING_DIS
121318. DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK
121319. DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT
121320. DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK
121321. DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT
121322. DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK
121323. DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT
121324. DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK
121325. DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT
121326. DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK
121327. DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT
121328. DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK
121329. DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT
121330. DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK
121331. DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT
121332. DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK
121333. DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT
121334. DPG0_DPG_CONTROL__DPG_EN_MASK
121335. DPG0_DPG_CONTROL__DPG_EN__SHIFT
121336. DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK
121337. DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT
121338. DPG0_DPG_CONTROL__DPG_HRES_MASK
121339. DPG0_DPG_CONTROL__DPG_HRES__SHIFT
121340. DPG0_DPG_CONTROL__DPG_MODE_MASK
121341. DPG0_DPG_CONTROL__DPG_MODE__SHIFT
121342. DPG0_DPG_CONTROL__DPG_VRES_MASK
121343. DPG0_DPG_CONTROL__DPG_VRES__SHIFT
121344. DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK
121345. DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT
121346. DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK
121347. DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT
121348. DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK
121349. DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT
121350. DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK
121351. DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT
121352. DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK
121353. DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT
121354. DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK
121355. DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT
121356. DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK
121357. DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT
121358. DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK
121359. DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT
121360. DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK
121361. DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT
121362. DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK
121363. DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT
121364. DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK
121365. DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT
121366. DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK
121367. DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT
121368. DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK
121369. DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT
121370. DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK
121371. DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT
121372. DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK
121373. DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT
121374. DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK
121375. DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT
121376. DPG1_DPG_CONTROL__DPG_EN_MASK
121377. DPG1_DPG_CONTROL__DPG_EN__SHIFT
121378. DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK
121379. DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT
121380. DPG1_DPG_CONTROL__DPG_HRES_MASK
121381. DPG1_DPG_CONTROL__DPG_HRES__SHIFT
121382. DPG1_DPG_CONTROL__DPG_MODE_MASK
121383. DPG1_DPG_CONTROL__DPG_MODE__SHIFT
121384. DPG1_DPG_CONTROL__DPG_VRES_MASK
121385. DPG1_DPG_CONTROL__DPG_VRES__SHIFT
121386. DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK
121387. DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT
121388. DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK
121389. DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT
121390. DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK
121391. DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT
121392. DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK
121393. DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT
121394. DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK
121395. DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT
121396. DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK
121397. DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT
121398. DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK
121399. DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT
121400. DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK
121401. DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT
121402. DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK
121403. DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT
121404. DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK
121405. DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT
121406. DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK
121407. DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT
121408. DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK
121409. DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT
121410. DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK
121411. DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT
121412. DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK
121413. DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT
121414. DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK
121415. DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT
121416. DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK
121417. DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT
121418. DPG2_DPG_CONTROL__DPG_EN_MASK
121419. DPG2_DPG_CONTROL__DPG_EN__SHIFT
121420. DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK
121421. DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT
121422. DPG2_DPG_CONTROL__DPG_HRES_MASK
121423. DPG2_DPG_CONTROL__DPG_HRES__SHIFT
121424. DPG2_DPG_CONTROL__DPG_MODE_MASK
121425. DPG2_DPG_CONTROL__DPG_MODE__SHIFT
121426. DPG2_DPG_CONTROL__DPG_VRES_MASK
121427. DPG2_DPG_CONTROL__DPG_VRES__SHIFT
121428. DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK
121429. DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT
121430. DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK
121431. DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT
121432. DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK
121433. DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT
121434. DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK
121435. DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT
121436. DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK
121437. DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT
121438. DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK
121439. DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT
121440. DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK
121441. DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT
121442. DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK
121443. DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT
121444. DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK
121445. DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT
121446. DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK
121447. DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT
121448. DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK
121449. DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT
121450. DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK
121451. DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT
121452. DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK
121453. DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT
121454. DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK
121455. DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT
121456. DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK
121457. DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT
121458. DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK
121459. DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT
121460. DPG3_DPG_CONTROL__DPG_EN_MASK
121461. DPG3_DPG_CONTROL__DPG_EN__SHIFT
121462. DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK
121463. DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT
121464. DPG3_DPG_CONTROL__DPG_HRES_MASK
121465. DPG3_DPG_CONTROL__DPG_HRES__SHIFT
121466. DPG3_DPG_CONTROL__DPG_MODE_MASK
121467. DPG3_DPG_CONTROL__DPG_MODE__SHIFT
121468. DPG3_DPG_CONTROL__DPG_VRES_MASK
121469. DPG3_DPG_CONTROL__DPG_VRES__SHIFT
121470. DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK
121471. DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT
121472. DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK
121473. DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT
121474. DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK
121475. DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT
121476. DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK
121477. DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT
121478. DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK
121479. DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT
121480. DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK
121481. DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT
121482. DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK
121483. DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT
121484. DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK
121485. DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT
121486. DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK
121487. DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT
121488. DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK
121489. DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT
121490. DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK
121491. DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT
121492. DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK
121493. DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT
121494. DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK
121495. DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT
121496. DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK
121497. DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT
121498. DPG4_DPG_CONTROL__DPG_BIT_DEPTH_MASK
121499. DPG4_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT
121500. DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK
121501. DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT
121502. DPG4_DPG_CONTROL__DPG_EN_MASK
121503. DPG4_DPG_CONTROL__DPG_EN__SHIFT
121504. DPG4_DPG_CONTROL__DPG_FIELD_POLARITY_MASK
121505. DPG4_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT
121506. DPG4_DPG_CONTROL__DPG_HRES_MASK
121507. DPG4_DPG_CONTROL__DPG_HRES__SHIFT
121508. DPG4_DPG_CONTROL__DPG_MODE_MASK
121509. DPG4_DPG_CONTROL__DPG_MODE__SHIFT
121510. DPG4_DPG_CONTROL__DPG_VRES_MASK
121511. DPG4_DPG_CONTROL__DPG_VRES__SHIFT
121512. DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK
121513. DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT
121514. DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK
121515. DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT
121516. DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK
121517. DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT
121518. DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK
121519. DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT
121520. DPG4_DPG_RAMP_CONTROL__DPG_INC0_MASK
121521. DPG4_DPG_RAMP_CONTROL__DPG_INC0__SHIFT
121522. DPG4_DPG_RAMP_CONTROL__DPG_INC1_MASK
121523. DPG4_DPG_RAMP_CONTROL__DPG_INC1__SHIFT
121524. DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK
121525. DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT
121526. DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK
121527. DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT
121528. DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK
121529. DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT
121530. DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK
121531. DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT
121532. DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK
121533. DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT
121534. DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK
121535. DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT
121536. DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK
121537. DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT
121538. DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK
121539. DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT
121540. DPG5_DPG_CONTROL__DPG_BIT_DEPTH_MASK
121541. DPG5_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT
121542. DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK
121543. DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT
121544. DPG5_DPG_CONTROL__DPG_EN_MASK
121545. DPG5_DPG_CONTROL__DPG_EN__SHIFT
121546. DPG5_DPG_CONTROL__DPG_FIELD_POLARITY_MASK
121547. DPG5_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT
121548. DPG5_DPG_CONTROL__DPG_HRES_MASK
121549. DPG5_DPG_CONTROL__DPG_HRES__SHIFT
121550. DPG5_DPG_CONTROL__DPG_MODE_MASK
121551. DPG5_DPG_CONTROL__DPG_MODE__SHIFT
121552. DPG5_DPG_CONTROL__DPG_VRES_MASK
121553. DPG5_DPG_CONTROL__DPG_VRES__SHIFT
121554. DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK
121555. DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT
121556. DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK
121557. DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT
121558. DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK
121559. DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT
121560. DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK
121561. DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT
121562. DPG5_DPG_RAMP_CONTROL__DPG_INC0_MASK
121563. DPG5_DPG_RAMP_CONTROL__DPG_INC0__SHIFT
121564. DPG5_DPG_RAMP_CONTROL__DPG_INC1_MASK
121565. DPG5_DPG_RAMP_CONTROL__DPG_INC1__SHIFT
121566. DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK
121567. DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT
121568. DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK
121569. DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT
121570. DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
121571. DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
121572. DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK
121573. DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT
121574. DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK
121575. DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT
121576. DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK
121577. DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT
121578. DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
121579. DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
121580. DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
121581. DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
121582. DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
121583. DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
121584. DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
121585. DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
121586. DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
121587. DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
121588. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK
121589. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT
121590. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK
121591. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT
121592. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK
121593. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK
121594. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT
121595. DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT
121596. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
121597. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
121598. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
121599. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
121600. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
121601. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
121602. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
121603. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
121604. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
121605. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
121606. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
121607. DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
121608. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
121609. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
121610. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
121611. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
121612. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
121613. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
121614. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
121615. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
121616. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
121617. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
121618. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
121619. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
121620. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
121621. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
121622. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
121623. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
121624. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
121625. DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
121626. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
121627. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
121628. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
121629. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
121630. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
121631. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
121632. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
121633. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
121634. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
121635. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
121636. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
121637. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
121638. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
121639. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
121640. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
121641. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
121642. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
121643. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
121644. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
121645. DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
121646. DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
121647. DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
121648. DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
121649. DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
121650. DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
121651. DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
121652. DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
121653. DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
121654. DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
121655. DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
121656. DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
121657. DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
121658. DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
121659. DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
121660. DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
121661. DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
121662. DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
121663. DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
121664. DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK
121665. DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT
121666. DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK
121667. DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT
121668. DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK
121669. DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT
121670. DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
121671. DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
121672. DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
121673. DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
121674. DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
121675. DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
121676. DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
121677. DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
121678. DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
121679. DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
121680. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK
121681. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT
121682. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK
121683. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT
121684. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK
121685. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK
121686. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT
121687. DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT
121688. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
121689. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
121690. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
121691. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
121692. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
121693. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
121694. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
121695. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
121696. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
121697. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
121698. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
121699. DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
121700. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
121701. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
121702. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
121703. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
121704. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
121705. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
121706. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
121707. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
121708. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
121709. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
121710. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
121711. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
121712. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
121713. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
121714. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
121715. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
121716. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
121717. DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
121718. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
121719. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
121720. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
121721. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
121722. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
121723. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
121724. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
121725. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
121726. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
121727. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
121728. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
121729. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
121730. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
121731. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
121732. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
121733. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
121734. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
121735. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
121736. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
121737. DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
121738. DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
121739. DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
121740. DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
121741. DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
121742. DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
121743. DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
121744. DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
121745. DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
121746. DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
121747. DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
121748. DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
121749. DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
121750. DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
121751. DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
121752. DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
121753. DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
121754. DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK
121755. DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT
121756. DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK
121757. DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT
121758. DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK
121759. DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT
121760. DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK
121761. DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT
121762. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK
121763. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT
121764. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK
121765. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT
121766. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK
121767. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT
121768. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK
121769. DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT
121770. DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK
121771. DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT
121772. DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK
121773. DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT
121774. DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK
121775. DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT
121776. DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK
121777. DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT
121778. DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK
121779. DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT
121780. DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK
121781. DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT
121782. DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK
121783. DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT
121784. DPG_PIPE_ARBITRATION_CONTROL3
121785. DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK
121786. DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT
121787. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK
121788. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT
121789. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK
121790. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT
121791. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK
121792. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK
121793. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT
121794. DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT
121795. DPG_PIPE_LATENCY_CONTROL
121796. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK
121797. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT
121798. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK
121799. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT
121800. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK
121801. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT
121802. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK
121803. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT
121804. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK
121805. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT
121806. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK
121807. DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT
121808. DPG_PIPE_STUTTER_CONTROL
121809. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK
121810. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT
121811. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK
121812. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT
121813. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK
121814. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT
121815. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK
121816. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT
121817. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK
121818. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT
121819. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK
121820. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT
121821. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK
121822. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT
121823. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK
121824. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT
121825. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK
121826. DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT
121827. DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
121828. DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT
121829. DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
121830. DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT
121831. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK
121832. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT
121833. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK
121834. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT
121835. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK
121836. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT
121837. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK
121838. DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT
121839. DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK
121840. DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT
121841. DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK
121842. DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT
121843. DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK
121844. DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT
121845. DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK
121846. DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT
121847. DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK
121848. DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
121849. DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK
121850. DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
121851. DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK
121852. DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT
121853. DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK
121854. DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT
121855. DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK
121856. DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT
121857. DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK
121858. DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT
121859. DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK
121860. DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT
121861. DPG_WATERMARK_MASK_CONTROL
121862. DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK
121863. DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT
121864. DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK
121865. DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT
121866. DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK
121867. DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT
121868. DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK
121869. DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
121870. DPHY3_ALGO_DEFAULT
121871. DPHY3_ALGO_PXA2128
121872. DPHY3_ALGO_PXA910
121873. DPHY_8B10B_CUR_DISP
121874. DPHY_8B10B_CUR_DISP_ONE
121875. DPHY_8B10B_CUR_DISP_ZERO
121876. DPHY_8B10B_NOT_RESET
121877. DPHY_8B10B_OUTPUT
121878. DPHY_8B10B_RESET
121879. DPHY_8B10B_RESETET
121880. DPHY_ALL_D_PDN
121881. DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION
121882. DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE
121883. DPHY_ALT_SCRAMBLER_RESET_EN
121884. DPHY_ALT_SCRAMBLER_RESET_SEL
121885. DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE
121886. DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE
121887. DPHY_ATEST_LANE0_PRBS_PATTERN
121888. DPHY_ATEST_LANE0_REG_PATTERN
121889. DPHY_ATEST_LANE1_PRBS_PATTERN
121890. DPHY_ATEST_LANE1_REG_PATTERN
121891. DPHY_ATEST_LANE2_PRBS_PATTERN
121892. DPHY_ATEST_LANE2_REG_PATTERN
121893. DPHY_ATEST_LANE3_PRBS_PATTERN
121894. DPHY_ATEST_LANE3_REG_PATTERN
121895. DPHY_ATEST_SEL_LANE0
121896. DPHY_ATEST_SEL_LANE1
121897. DPHY_ATEST_SEL_LANE2
121898. DPHY_ATEST_SEL_LANE3
121899. DPHY_BYPASS
121900. DPHY_CLK_CFG_LEFT_DRIVES_ALL
121901. DPHY_CLK_CFG_LEFT_DRIVES_LEFT
121902. DPHY_CLK_CFG_LEFT_DRIVES_RIGHT
121903. DPHY_CLK_CFG_RIGHT_DRIVES_ALL
121904. DPHY_CLK_TIMING_PARAM
121905. DPHY_CM
121906. DPHY_CMN_FBDIV
121907. DPHY_CMN_FBDIV_FROM_REG
121908. DPHY_CMN_FBDIV_VAL
121909. DPHY_CMN_IPDIV
121910. DPHY_CMN_IPDIV_FROM_REG
121911. DPHY_CMN_OPDIV
121912. DPHY_CMN_OPDIV_FROM_REG
121913. DPHY_CMN_OPIPDIV
121914. DPHY_CMN_PDN
121915. DPHY_CMN_PSO
121916. DPHY_CMN_PWM
121917. DPHY_CMN_PWM_DIV
121918. DPHY_CMN_PWM_HIGH
121919. DPHY_CMN_PWM_LOW
121920. DPHY_CMN_SSM
121921. DPHY_CMN_SSM_EN
121922. DPHY_CMN_TX_MODE_EN
121923. DPHY_CN
121924. DPHY_CO
121925. DPHY_CRC_CONTINUOUS
121926. DPHY_CRC_CONT_EN
121927. DPHY_CRC_DISABLED
121928. DPHY_CRC_EN
121929. DPHY_CRC_ENABLED
121930. DPHY_CRC_FIELD
121931. DPHY_CRC_LANE0_SELECTED
121932. DPHY_CRC_LANE1_SELECTED
121933. DPHY_CRC_LANE2_SELECTED
121934. DPHY_CRC_LANE3_SELECTED
121935. DPHY_CRC_MST_PHASE_ERROR_ACK
121936. DPHY_CRC_MST_PHASE_ERROR_ACKED
121937. DPHY_CRC_MST_PHASE_ERROR_NO_ACK
121938. DPHY_CRC_ONE_SHOT
121939. DPHY_CRC_SEL
121940. DPHY_CRC_START_FROM_BOTTOM_FIELD
121941. DPHY_CRC_START_FROM_TOP_FIELD
121942. DPHY_C_PDN
121943. DPHY_C_RSTB
121944. DPHY_DATA_TIMING_PARAM
121945. DPHY_DBG_OUTPUT
121946. DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY
121947. DPHY_D_PDN
121948. DPHY_D_RSTB
121949. DPHY_ELEC_PARA
121950. DPHY_FAST_TRAINING_CAPABLE
121951. DPHY_FAST_TRAINING_NOT_CAPABLE_0
121952. DPHY_FEC_ACTIVE
121953. DPHY_FEC_DISABLED
121954. DPHY_FEC_ENABLE
121955. DPHY_FEC_ENABLED
121956. DPHY_FEC_NOT_ACTIVE
121957. DPHY_FEC_READY
121958. DPHY_FEC_READY_DIS
121959. DPHY_FEC_READY_EN
121960. DPHY_LANES_MAP
121961. DPHY_LOAD_BS_COUNT_NOT_STARTED
121962. DPHY_LOAD_BS_COUNT_START
121963. DPHY_LOAD_BS_COUNT_STARTED
121964. DPHY_LOCK
121965. DPHY_LOCK_BYP
121966. DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK
121967. DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT
121968. DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK
121969. DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT
121970. DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK
121971. DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT
121972. DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK
121973. DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT
121974. DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK
121975. DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT
121976. DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK
121977. DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT
121978. DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK
121979. DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT
121980. DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK
121981. DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT
121982. DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK
121983. DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT
121984. DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK
121985. DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT
121986. DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK
121987. DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT
121988. DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK
121989. DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT
121990. DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK
121991. DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT
121992. DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK
121993. DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT
121994. DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK
121995. DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT
121996. DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK
121997. DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT
121998. DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK
121999. DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT
122000. DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK
122001. DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT
122002. DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK
122003. DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT
122004. DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK
122005. DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT
122006. DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK
122007. DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT
122008. DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK
122009. DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT
122010. DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK
122011. DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT
122012. DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK
122013. DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT
122014. DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK
122015. DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT
122016. DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK
122017. DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT
122018. DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK
122019. DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT
122020. DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK
122021. DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT
122022. DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK
122023. DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT
122024. DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK
122025. DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT
122026. DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK
122027. DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT
122028. DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK
122029. DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT
122030. DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK
122031. DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT
122032. DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK
122033. DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT
122034. DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK
122035. DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT
122036. DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK
122037. DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT
122038. DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK
122039. DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT
122040. DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK
122041. DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT
122042. DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK
122043. DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT
122044. DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK
122045. DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT
122046. DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK
122047. DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT
122048. DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK
122049. DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT
122050. DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK
122051. DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT
122052. DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK
122053. DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT
122054. DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK
122055. DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT
122056. DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK
122057. DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT
122058. DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK
122059. DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT
122060. DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK
122061. DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT
122062. DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK
122063. DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT
122064. DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK
122065. DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT
122066. DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK
122067. DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT
122068. DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK
122069. DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT
122070. DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK
122071. DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT
122072. DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK
122073. DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT
122074. DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK
122075. DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT
122076. DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK
122077. DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT
122078. DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK
122079. DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT
122080. DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK
122081. DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT
122082. DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK
122083. DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT
122084. DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK
122085. DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT
122086. DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK
122087. DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT
122088. DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK
122089. DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT
122090. DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK
122091. DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT
122092. DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK
122093. DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT
122094. DPHY_MC_PRG_HS_PREPARE
122095. DPHY_MC_PRG_HS_TRAIL
122096. DPHY_MC_PRG_HS_ZERO
122097. DPHY_M_PRG_HS_PREPARE
122098. DPHY_M_PRG_HS_TRAIL
122099. DPHY_M_PRG_HS_ZERO
122100. DPHY_NO_SKEW
122101. DPHY_PARAM_REG
122102. DPHY_PCS
122103. DPHY_PD_DPHY
122104. DPHY_PD_PLL
122105. DPHY_PLL_LOCK
122106. DPHY_PLL_PDN
122107. DPHY_PLL_PSO
122108. DPHY_PLL_RATE_HZ
122109. DPHY_PMA_CMN
122110. DPHY_PMA_LCLK
122111. DPHY_PMA_LDATA
122112. DPHY_PMA_RCLK
122113. DPHY_PMA_RDATA
122114. DPHY_PRBS11_SELECTED
122115. DPHY_PRBS23_SELECTED
122116. DPHY_PRBS7_SELECTED
122117. DPHY_PRBS_DISABLE
122118. DPHY_PRBS_EN
122119. DPHY_PRBS_ENABLE
122120. DPHY_PRBS_SEL
122121. DPHY_PSM_CFG
122122. DPHY_PSM_CFG_FROM_REG
122123. DPHY_PSM_CLK_DIV
122124. DPHY_REG_BYPASS_PLL
122125. DPHY_RX_FAST_TRAINING_CAPABLE
122126. DPHY_SCRAMBLER_ADVANCE
122127. DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL
122128. DPHY_SCRAMBLER_DIS
122129. DPHY_SCRAMBLER_KCODE
122130. DPHY_SCRAMBLER_KCODE_DISABLED
122131. DPHY_SCRAMBLER_KCODE_ENABLED
122132. DPHY_SCRAMBLER_SEL
122133. DPHY_SCRAMBLER_SEL_DBG_DATA
122134. DPHY_SCRAMBLER_SEL_LANE_DATA
122135. DPHY_SCR_DISABLED
122136. DPHY_SCR_ENABLED
122137. DPHY_SKEW_BYPASS
122138. DPHY_SW_FAST_TRAINING_NOT_STARTED
122139. DPHY_SW_FAST_TRAINING_START
122140. DPHY_SW_FAST_TRAINING_STARTED
122141. DPHY_TA_TIMING_PARAM
122142. DPHY_TIMING_PARA
122143. DPHY_TRAINING_PATTERN_1
122144. DPHY_TRAINING_PATTERN_2
122145. DPHY_TRAINING_PATTERN_3
122146. DPHY_TRAINING_PATTERN_4
122147. DPHY_TRAINING_PATTERN_SEL
122148. DPHY_TST
122149. DPHY_WITH_SKEW
122150. DPI
122151. DPI0_SEL_IN_RDMA1
122152. DPI0_SEL_IN_RDMA2
122153. DPI1_SEL_IN_RDMA1
122154. DPI1_SEL_IN_RDMA2
122155. DPIBLKRST
122156. DPINVGTT
122157. DPINVGTT_EN_MASK
122158. DPINVGTT_EN_MASK_CHV
122159. DPINVGTT_STATUS_MASK
122160. DPINVGTT_STATUS_MASK_CHV
122161. DPIOUNIT_CLOCK_GATE_DISABLE
122162. DPIO_AFC_RECAL
122163. DPIO_ALLDL_POWERDOWN
122164. DPIO_ALLDL_POWERDOWN_SHIFT_CH0
122165. DPIO_ALLDL_POWERDOWN_SHIFT_CH1
122166. DPIO_ANYDL_POWERDOWN
122167. DPIO_ANYDL_POWERDOWN_SHIFT_CH0
122168. DPIO_ANYDL_POWERDOWN_SHIFT_CH1
122169. DPIO_BIAS_CURRENT_CTL_SHIFT
122170. DPIO_CFG
122171. DPIO_CH0
122172. DPIO_CH1
122173. DPIO_CHANNEL_MODE_MASK
122174. DPIO_CHV_FEEDFWD_GAIN_MASK
122175. DPIO_CHV_FEEDFWD_GAIN_SHIFT
122176. DPIO_CHV_FIRST_MOD
122177. DPIO_CHV_FRAC_DIV_EN
122178. DPIO_CHV_GAIN_CTRL_SHIFT
122179. DPIO_CHV_INT_COEFF_SHIFT
122180. DPIO_CHV_INT_LOCK_THRESHOLD_MASK
122181. DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
122182. DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
122183. DPIO_CHV_K_DIV_SHIFT
122184. DPIO_CHV_M1_DIV_BY_2
122185. DPIO_CHV_N_DIV_SHIFT
122186. DPIO_CHV_P1_DIV_SHIFT
122187. DPIO_CHV_P2_DIV_SHIFT
122188. DPIO_CHV_PROP_COEFF_SHIFT
122189. DPIO_CHV_S1_DIV_SHIFT
122190. DPIO_CHV_SECOND_MOD
122191. DPIO_CHV_TDC_TARGET_CNT_MASK
122192. DPIO_CHV_TDC_TARGET_CNT_SHIFT
122193. DPIO_CL1POWERDOWNEN
122194. DPIO_CL2_LDOFUSE_PWRENB
122195. DPIO_CLK_BIAS_CTL_SHIFT
122196. DPIO_CMD
122197. DPIO_CMDID_CLOSE
122198. DPIO_CMDID_DISABLE
122199. DPIO_CMDID_ENABLE
122200. DPIO_CMDID_GET_API_VERSION
122201. DPIO_CMDID_GET_ATTR
122202. DPIO_CMDID_OPEN
122203. DPIO_CMDID_RESET
122204. DPIO_CMDID_SET_STASHING_DEST
122205. DPIO_CMD_BASE_VERSION
122206. DPIO_CMD_ID_OFFSET
122207. DPIO_CMNRST
122208. DPIO_CMN_RESET_N
122209. DPIO_CTL
122210. DPIO_DCLKP_EN
122211. DPIO_DEVFN
122212. DPIO_DRIVER_CTL_SHIFT
122213. DPIO_DYNPWRDOWNEN_CH0
122214. DPIO_DYNPWRDOWNEN_CH1
122215. DPIO_ENABLE_CALIBRATION
122216. DPIO_FRC_LATENCY_SHFIT
122217. DPIO_K_SHIFT
122218. DPIO_LANEDESKEW_STRAP_OVRD
122219. DPIO_LANESTAGGER_STRAP
122220. DPIO_LANESTAGGER_STRAP_OVRD
122221. DPIO_LEFT_TXFIFO_RST_MASTER
122222. DPIO_LEFT_TXFIFO_RST_MASTER2
122223. DPIO_LOCAL_CHANNEL
122224. DPIO_LRC_BYPASS
122225. DPIO_M1DIV_SHIFT
122226. DPIO_M2DIV_MASK
122227. DPIO_MODE_SELECT_0
122228. DPIO_MODE_SELECT_1
122229. DPIO_MODSEL0
122230. DPIO_MODSEL1
122231. DPIO_NO_CHANNEL
122232. DPIO_N_SHIFT
122233. DPIO_P1_SHIFT
122234. DPIO_P2_SHIFT
122235. DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
122236. DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
122237. DPIO_PCS_CLK_DATAWIDTH_SHIFT
122238. DPIO_PCS_CLK_SOFT_RESET
122239. DPIO_PCS_SWING_CALC_TX0_TX2
122240. DPIO_PCS_SWING_CALC_TX1_TX3
122241. DPIO_PCS_TX1DEEMP_6P0
122242. DPIO_PCS_TX1DEEMP_9P5
122243. DPIO_PCS_TX1DEEMP_MASK
122244. DPIO_PCS_TX1MARGIN_000
122245. DPIO_PCS_TX1MARGIN_101
122246. DPIO_PCS_TX1MARGIN_MASK
122247. DPIO_PCS_TX2DEEMP_6P0
122248. DPIO_PCS_TX2DEEMP_9P5
122249. DPIO_PCS_TX2DEEMP_MASK
122250. DPIO_PCS_TX2MARGIN_000
122251. DPIO_PCS_TX2MARGIN_101
122252. DPIO_PCS_TX2MARGIN_MASK
122253. DPIO_PCS_TX_LANE1_RESET
122254. DPIO_PCS_TX_LANE2_RESET
122255. DPIO_PHY
122256. DPIO_PHY0
122257. DPIO_PHY1
122258. DPIO_PHY2
122259. DPIO_PHY_IOSF_PORT
122260. DPIO_PHY_STATUS
122261. DPIO_PLL_FREQLOCK
122262. DPIO_PLL_LOCK
122263. DPIO_PLL_MODESEL_SHIFT
122264. DPIO_PLL_REFCLK_SEL_MASK
122265. DPIO_PLL_REFCLK_SEL_SHIFT
122266. DPIO_POST_DIV_DAC
122267. DPIO_POST_DIV_HDMIDP
122268. DPIO_POST_DIV_LVDS1
122269. DPIO_POST_DIV_LVDS2
122270. DPIO_POST_DIV_SHIFT
122271. DPIO_REFSEL_OVERRIDE
122272. DPIO_RIGHT_TXFIFO_RST_MASTER
122273. DPIO_RIGHT_TXFIFO_RST_MASTER2
122274. DPIO_SFR_BYPASS
122275. DPIO_SUS_CLK_CONFIG_CLKREQ
122276. DPIO_SUS_CLK_CONFIG_GATE
122277. DPIO_SUS_CLK_CONFIG_GATE_CLKREQ
122278. DPIO_SUS_CLK_CONFIG_ON
122279. DPIO_SWING_DEEMPH6P0_MASK
122280. DPIO_SWING_DEEMPH6P0_SHIFT
122281. DPIO_SWING_DEEMPH9P5_MASK
122282. DPIO_SWING_DEEMPH9P5_SHIFT
122283. DPIO_SWING_MARGIN000_MASK
122284. DPIO_SWING_MARGIN000_SHIFT
122285. DPIO_SWING_MARGIN101_MASK
122286. DPIO_SWING_MARGIN101_SHIFT
122287. DPIO_TX1_STAGGER_MASK
122288. DPIO_TX1_STAGGER_MULT
122289. DPIO_TX2_STAGGER_MASK
122290. DPIO_TX2_STAGGER_MULT
122291. DPIO_TX_OCALINIT_EN
122292. DPIO_TX_UNIQ_TRANS_SCALE_EN
122293. DPIO_UNIQ_TRANS_SCALE_SHIFT
122294. DPIO_UPAR_SHIFT
122295. DPIO_VER_MAJOR
122296. DPIO_VER_MINOR
122297. DPIPXLFMT
122298. DPI_BACK_LIGHT_OFF
122299. DPI_BACK_LIGHT_OFF_DATA
122300. DPI_BACK_LIGHT_ON
122301. DPI_BACK_LIGHT_ON_DATA
122302. DPI_BG_COLOR
122303. DPI_BG_HCNTL
122304. DPI_BG_VCNTL
122305. DPI_BPP_RGB565
122306. DPI_BPP_RGB666
122307. DPI_BPP_RGB888
122308. DPI_BUSY
122309. DPI_C
122310. DPI_CFG
122311. DPI_CFG_FIFO_DEPTH
122312. DPI_CFG_FIFO_LEVEL
122313. DPI_CFG_POL
122314. DPI_CHANNEL_NUMBER_POS
122315. DPI_CHECKSUM
122316. DPI_CHECKSUM_EN
122317. DPI_CHECKSUM_MASK
122318. DPI_CHECKSUM_READY
122319. DPI_CLPF_SETTING
122320. DPI_COLOR_CODING
122321. DPI_COLOR_CODING_16BIT_1
122322. DPI_COLOR_CODING_16BIT_2
122323. DPI_COLOR_CODING_16BIT_3
122324. DPI_COLOR_CODING_18BIT_1
122325. DPI_COLOR_CODING_18BIT_2
122326. DPI_COLOR_CODING_24BIT
122327. DPI_COLOR_MODE_OFF
122328. DPI_COLOR_MODE_ON
122329. DPI_CON
122330. DPI_CONTROL_REG
122331. DPI_C_LIMIT
122332. DPI_DATA_REG
122333. DPI_DDR_SETTING
122334. DPI_DUMMY
122335. DPI_DUMMY_MASK
122336. DPI_EMBSYNC_SETTING
122337. DPI_EN
122338. DPI_ENABLE
122339. DPI_ESAV_CODE_SET0
122340. DPI_ESAV_CODE_SET1
122341. DPI_ESAV_FTIMING
122342. DPI_ESAV_VTIMING_LEVEN
122343. DPI_ESAV_VTIMING_LODD
122344. DPI_ESAV_VTIMING_REVEN
122345. DPI_ESAV_VTIMING_RODD
122346. DPI_FIFO_CTL
122347. DPI_FIFO_EMPTY
122348. DPI_FIFO_UNDERRUN
122349. DPI_FIFO_UNDER_RUN
122350. DPI_FORMAT_16BIT_565_RGB_1
122351. DPI_FORMAT_16BIT_565_RGB_2
122352. DPI_FORMAT_16BIT_565_RGB_3
122353. DPI_FORMAT_18BIT_666_RGB_1
122354. DPI_FORMAT_18BIT_666_RGB_2
122355. DPI_FORMAT_24BIT_888_RGB
122356. DPI_FORMAT_9BIT_666_RGB
122357. DPI_FORMAT_MASK
122358. DPI_FORMAT_SHIFT
122359. DPI_HSYNC_DISABLE
122360. DPI_HSYNC_INVERT
122361. DPI_HSYNC_NEGATE
122362. DPI_ID
122363. DPI_ID_VALUE
122364. DPI_INTEN
122365. DPI_INTSTA
122366. DPI_IRQ_CLR
122367. DPI_IRQ_EN
122368. DPI_IRQ_STS
122369. DPI_LP
122370. DPI_LP_MODE
122371. DPI_OEN_ON
122372. DPI_ORDER_BGR
122373. DPI_ORDER_BRG
122374. DPI_ORDER_GRB
122375. DPI_ORDER_MASK
122376. DPI_ORDER_RGB
122377. DPI_ORDER_SHIFT
122378. DPI_OUTPUT_ENABLE_DISABLE
122379. DPI_OUTPUT_ENABLE_INVERT
122380. DPI_OUTPUT_ENABLE_MODE
122381. DPI_OUTPUT_ENABLE_NEGATE
122382. DPI_OUTPUT_SETTING
122383. DPI_PIXEL_CLK_INVERT
122384. DPI_READ
122385. DPI_RESOLUTION_REG
122386. DPI_RET
122387. DPI_SEL_IN_BLS
122388. DPI_SHUT_DOWN
122389. DPI_SIZE
122390. DPI_STATUS
122391. DPI_TGEN_HPORCH
122392. DPI_TGEN_HWIDTH
122393. DPI_TGEN_VPORCH
122394. DPI_TGEN_VPORCH_LEVEN
122395. DPI_TGEN_VPORCH_REVEN
122396. DPI_TGEN_VPORCH_RODD
122397. DPI_TGEN_VWIDTH
122398. DPI_TGEN_VWIDTH_LEVEN
122399. DPI_TGEN_VWIDTH_REVEN
122400. DPI_TGEN_VWIDTH_RODD
122401. DPI_TMODE
122402. DPI_TURN_ON
122403. DPI_VCID
122404. DPI_VSYNC_DISABLE
122405. DPI_VSYNC_INVERT
122406. DPI_VSYNC_NEGATE
122407. DPI_WRITE
122408. DPI_YUV422_SETTING
122409. DPI_Y_LIMIT
122410. DPKG_EXTRACT_FROM_DATA
122411. DPKG_EXTRACT_FROM_HDR
122412. DPKG_EXTRACT_FROM_PARSE
122413. DPKG_FROM_FIELD
122414. DPKG_FROM_HDR
122415. DPKG_FULL_FIELD
122416. DPKG_MAX_NUM_OF_EXTRACTS
122417. DPKG_NUM_OF_MASKS
122418. DPK_BB_REG_NUM
122419. DPK_CHANNEL_WIDTH_80
122420. DPK_DELTA_MAPPING_NUM
122421. DPK_RF_PATH_NUM
122422. DPK_RF_REG_NUM
122423. DPK_THRESHOLD
122424. DPL
122425. DPL0
122426. DPL1
122427. DPL3
122428. DPLL
122429. DPLL0_ENABLE
122430. DPLL1_ENABLE
122431. DPLLA_INPUT_BUFFER_ENABLE
122432. DPLLA_MODE_LVDS
122433. DPLLA_TEST_M_BYPASS
122434. DPLLA_TEST_N_BYPASS
122435. DPLLB_INPUT_BUFFER_ENABLE
122436. DPLLB_LVDS_P2_CLOCK_DIV_14
122437. DPLLB_LVDS_P2_CLOCK_DIV_7
122438. DPLLB_MODE_DAC_SERIAL
122439. DPLLB_MODE_LVDS
122440. DPLLB_TEST_M_BYPASS
122441. DPLLB_TEST_N_BYPASS
122442. DPLLB_TEST_SDVO_DIV_1
122443. DPLLB_TEST_SDVO_DIV_2
122444. DPLLB_TEST_SDVO_DIV_4
122445. DPLLB_TEST_SDVO_DIV_MASK
122446. DPLLC2R
122447. DPLLC2R_CODE
122448. DPLLC2R_FDPLL
122449. DPLLC2R_M
122450. DPLLC2R_SELC
122451. DPLLCR
122452. DPLLCR_CLKE
122453. DPLLCR_CODE
122454. DPLLCR_FDPLL
122455. DPLLCR_INCS_DOTCLKIN0
122456. DPLLCR_INCS_DOTCLKIN1
122457. DPLLCR_M
122458. DPLLCR_N
122459. DPLLCR_PLCS0
122460. DPLLCR_PLCS1
122461. DPLLCR_STBY
122462. DPLL_2X_CLOCK_ENABLE
122463. DPLL_A
122464. DPLL_ADJUST
122465. DPLL_AUTOIDLE_DISABLE
122466. DPLL_AUTOIDLE_LOW_POWER_STOP
122467. DPLL_A_MD
122468. DPLL_B
122469. DPLL_B_MD
122470. DPLL_CFGCR0_DCO_FRACTION
122471. DPLL_CFGCR0_DCO_FRACTION_MASK
122472. DPLL_CFGCR0_DCO_FRACTION_SHIFT
122473. DPLL_CFGCR0_DCO_INTEGER_MASK
122474. DPLL_CFGCR0_HDMI_MODE
122475. DPLL_CFGCR0_LINK_RATE_1080
122476. DPLL_CFGCR0_LINK_RATE_1350
122477. DPLL_CFGCR0_LINK_RATE_1620
122478. DPLL_CFGCR0_LINK_RATE_2160
122479. DPLL_CFGCR0_LINK_RATE_2700
122480. DPLL_CFGCR0_LINK_RATE_3240
122481. DPLL_CFGCR0_LINK_RATE_4050
122482. DPLL_CFGCR0_LINK_RATE_810
122483. DPLL_CFGCR0_LINK_RATE_MASK
122484. DPLL_CFGCR0_SSC_ENABLE
122485. DPLL_CFGCR0_SSC_ENABLE_ICL
122486. DPLL_CFGCR1
122487. DPLL_CFGCR1_CENTRAL_FREQ
122488. DPLL_CFGCR1_CENTRAL_FREQ_8400
122489. DPLL_CFGCR1_DCO_FRACTION
122490. DPLL_CFGCR1_DCO_FRACTION_MASK
122491. DPLL_CFGCR1_DCO_INTEGER_MASK
122492. DPLL_CFGCR1_FREQ_ENABLE
122493. DPLL_CFGCR1_KDIV
122494. DPLL_CFGCR1_KDIV_1
122495. DPLL_CFGCR1_KDIV_2
122496. DPLL_CFGCR1_KDIV_3
122497. DPLL_CFGCR1_KDIV_MASK
122498. DPLL_CFGCR1_KDIV_SHIFT
122499. DPLL_CFGCR1_PDIV
122500. DPLL_CFGCR1_PDIV_2
122501. DPLL_CFGCR1_PDIV_3
122502. DPLL_CFGCR1_PDIV_5
122503. DPLL_CFGCR1_PDIV_7
122504. DPLL_CFGCR1_PDIV_MASK
122505. DPLL_CFGCR1_PDIV_SHIFT
122506. DPLL_CFGCR1_QDIV_MODE
122507. DPLL_CFGCR1_QDIV_MODE_SHIFT
122508. DPLL_CFGCR1_QDIV_RATIO
122509. DPLL_CFGCR1_QDIV_RATIO_MASK
122510. DPLL_CFGCR1_QDIV_RATIO_SHIFT
122511. DPLL_CFGCR2
122512. DPLL_CFGCR2_CENTRAL_FREQ_MASK
122513. DPLL_CFGCR2_KDIV
122514. DPLL_CFGCR2_KDIV_1
122515. DPLL_CFGCR2_KDIV_2
122516. DPLL_CFGCR2_KDIV_3
122517. DPLL_CFGCR2_KDIV_5
122518. DPLL_CFGCR2_KDIV_MASK
122519. DPLL_CFGCR2_PDIV
122520. DPLL_CFGCR2_PDIV_1
122521. DPLL_CFGCR2_PDIV_2
122522. DPLL_CFGCR2_PDIV_3
122523. DPLL_CFGCR2_PDIV_7
122524. DPLL_CFGCR2_PDIV_MASK
122525. DPLL_CFGCR2_QDIV_MODE
122526. DPLL_CFGCR2_QDIV_RATIO
122527. DPLL_CFGCR2_QDIV_RATIO_MASK
122528. DPLL_CLKF_MASK
122529. DPLL_CLKR_MASK
122530. DPLL_CLK_ENABLE
122531. DPLL_CON0
122532. DPLL_CTL
122533. DPLL_CTRL
122534. DPLL_CTRL1
122535. DPLL_CTRL1_HDMI_MODE
122536. DPLL_CTRL1_LINK_RATE
122537. DPLL_CTRL1_LINK_RATE_1080
122538. DPLL_CTRL1_LINK_RATE_1350
122539. DPLL_CTRL1_LINK_RATE_1620
122540. DPLL_CTRL1_LINK_RATE_2160
122541. DPLL_CTRL1_LINK_RATE_2700
122542. DPLL_CTRL1_LINK_RATE_810
122543. DPLL_CTRL1_LINK_RATE_MASK
122544. DPLL_CTRL1_LINK_RATE_SHIFT
122545. DPLL_CTRL1_OVERRIDE
122546. DPLL_CTRL1_SSC
122547. DPLL_CTRL2
122548. DPLL_CTRL2_DDI_CLK_OFF
122549. DPLL_CTRL2_DDI_CLK_SEL
122550. DPLL_CTRL2_DDI_CLK_SEL_MASK
122551. DPLL_CTRL2_DDI_CLK_SEL_SHIFT
122552. DPLL_CTRL2_DDI_SEL_OVERRIDE
122553. DPLL_CTRL3
122554. DPLL_CTRL4
122555. DPLL_CTRL5
122556. DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
122557. DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
122558. DPLL_DFT
122559. DPLL_DITHEN
122560. DPLL_DIV_CTRL
122561. DPLL_DVO_2X_MODE
122562. DPLL_DVO_HIGH_SPEED
122563. DPLL_ENSTAT
122564. DPLL_EN_DISP
122565. DPLL_EN_HDMI
122566. DPLL_EN_VGA
122567. DPLL_EXT_BUFFER_ENABLE_VLV
122568. DPLL_FASTEN
122569. DPLL_FINT_INVALID
122570. DPLL_FINT_UNDERFLOW
122571. DPLL_FPA01_P1_POST_DIV_MASK
122572. DPLL_FPA01_P1_POST_DIV_MASK_I830
122573. DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
122574. DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
122575. DPLL_FPA01_P1_POST_DIV_SHIFT
122576. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
122577. DPLL_FPA0h1_P1_POST_DIV_MASK
122578. DPLL_FPA1_P1_POST_DIV_MASK
122579. DPLL_FPA1_P1_POST_DIV_SHIFT
122580. DPLL_HALF
122581. DPLL_I9XX_P2_SHIFT
122582. DPLL_ID_EHL_DPLL4
122583. DPLL_ID_ICL_DPLL0
122584. DPLL_ID_ICL_DPLL1
122585. DPLL_ID_ICL_MGPLL1
122586. DPLL_ID_ICL_MGPLL2
122587. DPLL_ID_ICL_MGPLL3
122588. DPLL_ID_ICL_MGPLL4
122589. DPLL_ID_ICL_TBTPLL
122590. DPLL_ID_LCPLL_1350
122591. DPLL_ID_LCPLL_2700
122592. DPLL_ID_LCPLL_810
122593. DPLL_ID_PCH_PLL_A
122594. DPLL_ID_PCH_PLL_B
122595. DPLL_ID_PRIVATE
122596. DPLL_ID_SKL_DPLL0
122597. DPLL_ID_SKL_DPLL1
122598. DPLL_ID_SKL_DPLL2
122599. DPLL_ID_SKL_DPLL3
122600. DPLL_ID_SPLL
122601. DPLL_ID_TGL_MGPLL5
122602. DPLL_ID_TGL_MGPLL6
122603. DPLL_ID_WRPLL1
122604. DPLL_ID_WRPLL2
122605. DPLL_INT
122606. DPLL_INTEGRATED_CRI_CLK_VLV
122607. DPLL_INTEGRATED_REF_CLK_VLV
122608. DPLL_INT_MUX
122609. DPLL_IOB
122610. DPLL_J_TYPE
122611. DPLL_LOCK
122612. DPLL_LOCKED
122613. DPLL_LOCK_VLV
122614. DPLL_LOW_POWER_BYPASS
122615. DPLL_LOW_POWER_STOP
122616. DPLL_MD
122617. DPLL_MD_UDI_DIVIDER_MASK
122618. DPLL_MD_UDI_DIVIDER_SHIFT
122619. DPLL_MD_UDI_MULTIPLIER_MASK
122620. DPLL_MD_UDI_MULTIPLIER_SHIFT
122621. DPLL_MD_VGA_UDI_DIVIDER_MASK
122622. DPLL_MD_VGA_UDI_DIVIDER_SHIFT
122623. DPLL_MD_VGA_UDI_MULTIPLIER_MASK
122624. DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT
122625. DPLL_MIN_DIVIDER
122626. DPLL_MIN_MULTIPLIER
122627. DPLL_MODE_MASK
122628. DPLL_MON
122629. DPLL_MULT_UNDERFLOW
122630. DPLL_P1_FORCE_DIV2
122631. DPLL_P1_MASK
122632. DPLL_P1_SHIFT
122633. DPLL_P2_CLOCK_DIV_MASK
122634. DPLL_P2_MASK
122635. DPLL_P2_SHIFT
122636. DPLL_PDIV_MASK
122637. DPLL_PDIV_SHIFT
122638. DPLL_PLL_ENABLE
122639. DPLL_PORTB_READY_MASK
122640. DPLL_PORTC_READY_MASK
122641. DPLL_PORTD_READY_MASK
122642. DPLL_POST_SRC
122643. DPLL_PRE_SRC
122644. DPLL_PWRDN
122645. DPLL_RATE_SELECT_FP0
122646. DPLL_RATE_SELECT_FP1
122647. DPLL_RATE_SELECT_MASK
122648. DPLL_REFERENCE_DEFAULT
122649. DPLL_REFERENCE_SELECT_MASK
122650. DPLL_REFERENCE_TVCLK
122651. DPLL_REF_CLK_ENABLE_VLV
122652. DPLL_RESET
122653. DPLL_ROUNDING_VAL
122654. DPLL_SCALE_BASE
122655. DPLL_SCALE_FACTOR
122656. DPLL_SDVO_HIGH_SPEED
122657. DPLL_SEL_HDMI
122658. DPLL_SSC_REF_CLK_CHV
122659. DPLL_STATUS
122660. DPLL_SYNCLOCK_ENABLE
122661. DPLL_TEST
122662. DPLL_TO_LPD
122663. DPLL_UPDATE
122664. DPLL_VCO_ENABLE
122665. DPLL_VGA_MODE_DIS
122666. DPLL_VGA_MODE_DISABLE
122667. DPLSUNIT_CLOCK_GATE_DISABLE
122668. DPLS_EDP_PPS_FIX_DIS
122669. DPLUNIT_CLOCK_GATE_DISABLE
122670. DPLX_DET_FULL
122671. DPLX_FULL
122672. DPLYBASE
122673. DPLYSTAS
122674. DPM
122675. DPMANT
122676. DPMCP_CMD
122677. DPMCP_CMDID_CLOSE
122678. DPMCP_CMDID_OPEN
122679. DPMCP_CMDID_RESET
122680. DPMCP_CMD_BASE_VERSION
122681. DPMCP_CMD_ID_OFFSET
122682. DPMCP_MIN_VER_MAJOR
122683. DPMCP_MIN_VER_MINOR
122684. DPMEM_COMMAND_OFFSET
122685. DPMEM_MAGIC
122686. DPMFlags_ACP_Enabled
122687. DPMFlags_Debug
122688. DPMFlags_ForceHighestValid
122689. DPMFlags_SCLK_Enabled
122690. DPMFlags_UVD_Enabled
122691. DPMFlags_VCE_Enabled
122692. DPMNG_CMD
122693. DPMNG_CMDID_GET_VERSION
122694. DPMNG_CMD_BASE_VERSION
122695. DPMNG_CMD_ID_OFFSET
122696. DPMS_ACTIVE_OFF
122697. DPMS_FLAGS
122698. DPMS_MASK
122699. DPMS_OFF
122700. DPMS_OFFSET
122701. DPMS_ON
122702. DPMS_STANDBY
122703. DPMS_SUSPEND
122704. DPMS_SYNC_SELECT
122705. DPMS_USAGE
122706. DPMTABLE_OD_UPDATE_MCLK
122707. DPMTABLE_OD_UPDATE_MCLK_MASK
122708. DPMTABLE_OD_UPDATE_SCLK
122709. DPMTABLE_OD_UPDATE_SCLK_MASK
122710. DPMTABLE_OD_UPDATE_VDDC
122711. DPMTABLE_UPDATE_MCLK
122712. DPMTABLE_UPDATE_SCLK
122713. DPMTABLE_UPDATE_SOCCLK
122714. DPMTuning_Activity_Shift
122715. DPMTuning_Downhyst_Shift
122716. DPMTuning_Uphyst_Shift
122717. DPM_ARRAY
122718. DPM_ARRAY_HARD_MAX
122719. DPM_ARRAY_HARD_MIN
122720. DPM_ARRAY_SOFT_MAX
122721. DPM_ARRAY_SOFT_MIN
122722. DPM_ENABLED
122723. DPM_EVENT_SRC
122724. DPM_EVENT_SRC_ANALOG
122725. DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
122726. DPM_EVENT_SRC_DIGITAL
122727. DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
122728. DPM_EVENT_SRC_EXTERNAL
122729. DPM_EVENT_SRC_MASK
122730. DPM_FLAG_LEAVE_SUSPENDED
122731. DPM_FLAG_NEVER_SKIP
122732. DPM_FLAG_SMART_PREPARE
122733. DPM_FLAG_SMART_SUSPEND
122734. DPM_FREE_START
122735. DPM_GO_DOWN
122736. DPM_GO_UP
122737. DPM_HOST_INT_EN0
122738. DPM_HOST_INT_GLOBAL_EN
122739. DPM_HOST_INT_MASK
122740. DPM_HOST_INT_STAT0
122741. DPM_HOST_WIN0_OFFSET
122742. DPM_L2_BD
122743. DPM_L2_INLINE
122744. DPM_LEGACY
122745. DPM_NO_LIMIT
122746. DPM_NO_UP
122747. DPM_NUM_PAGES
122748. DPM_ORDER_DEV_AFTER_PARENT
122749. DPM_ORDER_DEV_LAST
122750. DPM_ORDER_NONE
122751. DPM_ORDER_PARENT_BEFORE_DEV
122752. DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN
122753. DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ
122754. DPM_OVERRIDE_DISABLE_SOCCLK_PID
122755. DPM_OVERRIDE_DISABLE_UCLK_PID
122756. DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_SOCCLK
122757. DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK
122758. DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_SOCCLK
122759. DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK
122760. DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK
122761. DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK
122762. DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK
122763. DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK
122764. DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK
122765. DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK
122766. DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK
122767. DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH
122768. DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH
122769. DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH
122770. DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH
122771. DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK
122772. DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK
122773. DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK
122774. DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK
122775. DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK
122776. DPM_PAGE_ADDR
122777. DPM_PAGE_SIZE
122778. DPM_RDMA
122779. DPM_SCLK_ENABLE
122780. DPM_STATE0_LEVEL_MASK
122781. DPM_STATE0_LEVEL_SHIFT
122782. DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK
122783. DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT
122784. DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK
122785. DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT
122786. DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK
122787. DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT
122788. DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK
122789. DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT
122790. DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK
122791. DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT
122792. DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK
122793. DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT
122794. DPM_TABLE_100__UvdLevel_4_DclkFrequency_MASK
122795. DPM_TABLE_100__UvdLevel_4_DclkFrequency__SHIFT
122796. DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK
122797. DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT
122798. DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK
122799. DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT
122800. DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK
122801. DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT
122802. DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK
122803. DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT
122804. DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK
122805. DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT
122806. DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK
122807. DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT
122808. DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK
122809. DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT
122810. DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK
122811. DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT
122812. DPM_TABLE_101__UvdLevel_4_DclkDivider_MASK
122813. DPM_TABLE_101__UvdLevel_4_DclkDivider__SHIFT
122814. DPM_TABLE_101__UvdLevel_4_MinVddNb_MASK
122815. DPM_TABLE_101__UvdLevel_4_MinVddNb__SHIFT
122816. DPM_TABLE_101__UvdLevel_4_VclkDivider_MASK
122817. DPM_TABLE_101__UvdLevel_4_VclkDivider__SHIFT
122818. DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK
122819. DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT
122820. DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK
122821. DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT
122822. DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK
122823. DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT
122824. DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK
122825. DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT
122826. DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK
122827. DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT
122828. DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK
122829. DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT
122830. DPM_TABLE_102__UvdLevel_4_DClkBypassCntl_MASK
122831. DPM_TABLE_102__UvdLevel_4_DClkBypassCntl__SHIFT
122832. DPM_TABLE_102__UvdLevel_4_VClkBypassCntl_MASK
122833. DPM_TABLE_102__UvdLevel_4_VClkBypassCntl__SHIFT
122834. DPM_TABLE_102__UvdLevel_4_padding_0_MASK
122835. DPM_TABLE_102__UvdLevel_4_padding_0__SHIFT
122836. DPM_TABLE_102__UvdLevel_4_padding_1_MASK
122837. DPM_TABLE_102__UvdLevel_4_padding_1__SHIFT
122838. DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK
122839. DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT
122840. DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK
122841. DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT
122842. DPM_TABLE_103__GraphicsLevel_2_Flags_MASK
122843. DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT
122844. DPM_TABLE_103__UvdLevel_5_VclkFrequency_MASK
122845. DPM_TABLE_103__UvdLevel_5_VclkFrequency__SHIFT
122846. DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK
122847. DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT
122848. DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK
122849. DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT
122850. DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK
122851. DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT
122852. DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK
122853. DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT
122854. DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK
122855. DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT
122856. DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK
122857. DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT
122858. DPM_TABLE_104__UvdLevel_5_DclkFrequency_MASK
122859. DPM_TABLE_104__UvdLevel_5_DclkFrequency__SHIFT
122860. DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK
122861. DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT
122862. DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK
122863. DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT
122864. DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK
122865. DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT
122866. DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK
122867. DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT
122868. DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK
122869. DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT
122870. DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK
122871. DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT
122872. DPM_TABLE_105__UvdLevel_5_DclkDivider_MASK
122873. DPM_TABLE_105__UvdLevel_5_DclkDivider__SHIFT
122874. DPM_TABLE_105__UvdLevel_5_MinVddNb_MASK
122875. DPM_TABLE_105__UvdLevel_5_MinVddNb__SHIFT
122876. DPM_TABLE_105__UvdLevel_5_VclkDivider_MASK
122877. DPM_TABLE_105__UvdLevel_5_VclkDivider__SHIFT
122878. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK
122879. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT
122880. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK
122881. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT
122882. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK
122883. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT
122884. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK
122885. DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT
122886. DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK
122887. DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT
122888. DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK
122889. DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT
122890. DPM_TABLE_106__UvdLevel_5_DClkBypassCntl_MASK
122891. DPM_TABLE_106__UvdLevel_5_DClkBypassCntl__SHIFT
122892. DPM_TABLE_106__UvdLevel_5_VClkBypassCntl_MASK
122893. DPM_TABLE_106__UvdLevel_5_VClkBypassCntl__SHIFT
122894. DPM_TABLE_106__UvdLevel_5_padding_0_MASK
122895. DPM_TABLE_106__UvdLevel_5_padding_0__SHIFT
122896. DPM_TABLE_106__UvdLevel_5_padding_1_MASK
122897. DPM_TABLE_106__UvdLevel_5_padding_1__SHIFT
122898. DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK
122899. DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT
122900. DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK
122901. DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT
122902. DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK
122903. DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT
122904. DPM_TABLE_107__GraphicsLevel_2_padding1_0_MASK
122905. DPM_TABLE_107__GraphicsLevel_2_padding1_0__SHIFT
122906. DPM_TABLE_107__GraphicsLevel_2_padding1_1_MASK
122907. DPM_TABLE_107__GraphicsLevel_2_padding1_1__SHIFT
122908. DPM_TABLE_107__GraphicsLevel_2_padding1_MASK
122909. DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT
122910. DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK
122911. DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT
122912. DPM_TABLE_107__UvdLevel_6_VclkFrequency_MASK
122913. DPM_TABLE_107__UvdLevel_6_VclkFrequency__SHIFT
122914. DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK
122915. DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT
122916. DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK
122917. DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT
122918. DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK
122919. DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT
122920. DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK
122921. DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT
122922. DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK
122923. DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT
122924. DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK
122925. DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT
122926. DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK
122927. DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT
122928. DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK
122929. DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT
122930. DPM_TABLE_108__UvdLevel_6_DclkFrequency_MASK
122931. DPM_TABLE_108__UvdLevel_6_DclkFrequency__SHIFT
122932. DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK
122933. DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT
122934. DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK
122935. DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT
122936. DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK
122937. DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT
122938. DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK
122939. DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT
122940. DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK
122941. DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT
122942. DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK
122943. DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT
122944. DPM_TABLE_109__UvdLevel_6_DclkDivider_MASK
122945. DPM_TABLE_109__UvdLevel_6_DclkDivider__SHIFT
122946. DPM_TABLE_109__UvdLevel_6_MinVddNb_MASK
122947. DPM_TABLE_109__UvdLevel_6_MinVddNb__SHIFT
122948. DPM_TABLE_109__UvdLevel_6_VclkDivider_MASK
122949. DPM_TABLE_109__UvdLevel_6_VclkDivider__SHIFT
122950. DPM_TABLE_10__GraphicsPIDController_StateShift_MASK
122951. DPM_TABLE_10__GraphicsPIDController_StateShift__SHIFT
122952. DPM_TABLE_10__MemoryPIDController_Ki_MASK
122953. DPM_TABLE_10__MemoryPIDController_Ki__SHIFT
122954. DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK
122955. DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT
122956. DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK
122957. DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT
122958. DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK
122959. DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT
122960. DPM_TABLE_110__UvdLevel_6_DClkBypassCntl_MASK
122961. DPM_TABLE_110__UvdLevel_6_DClkBypassCntl__SHIFT
122962. DPM_TABLE_110__UvdLevel_6_VClkBypassCntl_MASK
122963. DPM_TABLE_110__UvdLevel_6_VClkBypassCntl__SHIFT
122964. DPM_TABLE_110__UvdLevel_6_padding_0_MASK
122965. DPM_TABLE_110__UvdLevel_6_padding_0__SHIFT
122966. DPM_TABLE_110__UvdLevel_6_padding_1_MASK
122967. DPM_TABLE_110__UvdLevel_6_padding_1__SHIFT
122968. DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK
122969. DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT
122970. DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK
122971. DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT
122972. DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK
122973. DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT
122974. DPM_TABLE_111__UvdLevel_7_VclkFrequency_MASK
122975. DPM_TABLE_111__UvdLevel_7_VclkFrequency__SHIFT
122976. DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK
122977. DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT
122978. DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK
122979. DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT
122980. DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK
122981. DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT
122982. DPM_TABLE_112__UvdLevel_7_DclkFrequency_MASK
122983. DPM_TABLE_112__UvdLevel_7_DclkFrequency__SHIFT
122984. DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK
122985. DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT
122986. DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK
122987. DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT
122988. DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK
122989. DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT
122990. DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK
122991. DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT
122992. DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK
122993. DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT
122994. DPM_TABLE_113__UvdLevel_7_DclkDivider_MASK
122995. DPM_TABLE_113__UvdLevel_7_DclkDivider__SHIFT
122996. DPM_TABLE_113__UvdLevel_7_MinVddNb_MASK
122997. DPM_TABLE_113__UvdLevel_7_MinVddNb__SHIFT
122998. DPM_TABLE_113__UvdLevel_7_VclkDivider_MASK
122999. DPM_TABLE_113__UvdLevel_7_VclkDivider__SHIFT
123000. DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK
123001. DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT
123002. DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK
123003. DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT
123004. DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK
123005. DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT
123006. DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK
123007. DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT
123008. DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK
123009. DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT
123010. DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK
123011. DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT
123012. DPM_TABLE_114__UvdLevel_7_DClkBypassCntl_MASK
123013. DPM_TABLE_114__UvdLevel_7_DClkBypassCntl__SHIFT
123014. DPM_TABLE_114__UvdLevel_7_VClkBypassCntl_MASK
123015. DPM_TABLE_114__UvdLevel_7_VClkBypassCntl__SHIFT
123016. DPM_TABLE_114__UvdLevel_7_padding_0_MASK
123017. DPM_TABLE_114__UvdLevel_7_padding_0__SHIFT
123018. DPM_TABLE_114__UvdLevel_7_padding_1_MASK
123019. DPM_TABLE_114__UvdLevel_7_padding_1__SHIFT
123020. DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK
123021. DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT
123022. DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK
123023. DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT
123024. DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK
123025. DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT
123026. DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK
123027. DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT
123028. DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK
123029. DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT
123030. DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK
123031. DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT
123032. DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK
123033. DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT
123034. DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK
123035. DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT
123036. DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK
123037. DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT
123038. DPM_TABLE_115__VceLevel_0_Frequency_MASK
123039. DPM_TABLE_115__VceLevel_0_Frequency__SHIFT
123040. DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK
123041. DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT
123042. DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK
123043. DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT
123044. DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK
123045. DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT
123046. DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK
123047. DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT
123048. DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK
123049. DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT
123050. DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK
123051. DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT
123052. DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK
123053. DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT
123054. DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK
123055. DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT
123056. DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK
123057. DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT
123058. DPM_TABLE_116__VceLevel_0_ClkBypassCntl_MASK
123059. DPM_TABLE_116__VceLevel_0_ClkBypassCntl__SHIFT
123060. DPM_TABLE_116__VceLevel_0_Divider_MASK
123061. DPM_TABLE_116__VceLevel_0_Divider__SHIFT
123062. DPM_TABLE_116__VceLevel_0_MinVoltage_MASK
123063. DPM_TABLE_116__VceLevel_0_MinVoltage__SHIFT
123064. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK
123065. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT
123066. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK
123067. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT
123068. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK
123069. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT
123070. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK
123071. DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT
123072. DPM_TABLE_117__GraphicsLevel_3_Flags_MASK
123073. DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT
123074. DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK
123075. DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT
123076. DPM_TABLE_117__VceLevel_0_Reserved_MASK
123077. DPM_TABLE_117__VceLevel_0_Reserved__SHIFT
123078. DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK
123079. DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT
123080. DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK
123081. DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT
123082. DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK
123083. DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT
123084. DPM_TABLE_118__VceLevel_1_Frequency_MASK
123085. DPM_TABLE_118__VceLevel_1_Frequency__SHIFT
123086. DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK
123087. DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT
123088. DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK
123089. DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT
123090. DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK
123091. DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT
123092. DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK
123093. DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT
123094. DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK
123095. DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT
123096. DPM_TABLE_119__VceLevel_1_ClkBypassCntl_MASK
123097. DPM_TABLE_119__VceLevel_1_ClkBypassCntl__SHIFT
123098. DPM_TABLE_119__VceLevel_1_Divider_MASK
123099. DPM_TABLE_119__VceLevel_1_Divider__SHIFT
123100. DPM_TABLE_119__VceLevel_1_MinVoltage_MASK
123101. DPM_TABLE_119__VceLevel_1_MinVoltage__SHIFT
123102. DPM_TABLE_11__GioPIDController_Ki_MASK
123103. DPM_TABLE_11__GioPIDController_Ki__SHIFT
123104. DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK
123105. DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT
123106. DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK
123107. DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT
123108. DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK
123109. DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT
123110. DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK
123111. DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT
123112. DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK
123113. DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT
123114. DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK
123115. DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT
123116. DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK
123117. DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT
123118. DPM_TABLE_120__VceLevel_1_Reserved_MASK
123119. DPM_TABLE_120__VceLevel_1_Reserved__SHIFT
123120. DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK
123121. DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT
123122. DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK
123123. DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT
123124. DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK
123125. DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT
123126. DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK
123127. DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT
123128. DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK
123129. DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT
123130. DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK
123131. DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT
123132. DPM_TABLE_121__GraphicsLevel_3_padding1_0_MASK
123133. DPM_TABLE_121__GraphicsLevel_3_padding1_0__SHIFT
123134. DPM_TABLE_121__GraphicsLevel_3_padding1_1_MASK
123135. DPM_TABLE_121__GraphicsLevel_3_padding1_1__SHIFT
123136. DPM_TABLE_121__GraphicsLevel_3_padding1_MASK
123137. DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT
123138. DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK
123139. DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT
123140. DPM_TABLE_121__VceLevel_2_Frequency_MASK
123141. DPM_TABLE_121__VceLevel_2_Frequency__SHIFT
123142. DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK
123143. DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT
123144. DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK
123145. DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT
123146. DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK
123147. DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT
123148. DPM_TABLE_122__VceLevel_2_ClkBypassCntl_MASK
123149. DPM_TABLE_122__VceLevel_2_ClkBypassCntl__SHIFT
123150. DPM_TABLE_122__VceLevel_2_Divider_MASK
123151. DPM_TABLE_122__VceLevel_2_Divider__SHIFT
123152. DPM_TABLE_122__VceLevel_2_MinVoltage_MASK
123153. DPM_TABLE_122__VceLevel_2_MinVoltage__SHIFT
123154. DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK
123155. DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT
123156. DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK
123157. DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT
123158. DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK
123159. DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT
123160. DPM_TABLE_123__VceLevel_2_Reserved_MASK
123161. DPM_TABLE_123__VceLevel_2_Reserved__SHIFT
123162. DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK
123163. DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT
123164. DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK
123165. DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT
123166. DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK
123167. DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT
123168. DPM_TABLE_124__VceLevel_3_Frequency_MASK
123169. DPM_TABLE_124__VceLevel_3_Frequency__SHIFT
123170. DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK
123171. DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT
123172. DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK
123173. DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT
123174. DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK
123175. DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT
123176. DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK
123177. DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT
123178. DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK
123179. DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT
123180. DPM_TABLE_125__VceLevel_3_ClkBypassCntl_MASK
123181. DPM_TABLE_125__VceLevel_3_ClkBypassCntl__SHIFT
123182. DPM_TABLE_125__VceLevel_3_Divider_MASK
123183. DPM_TABLE_125__VceLevel_3_Divider__SHIFT
123184. DPM_TABLE_125__VceLevel_3_MinVoltage_MASK
123185. DPM_TABLE_125__VceLevel_3_MinVoltage__SHIFT
123186. DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK
123187. DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT
123188. DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK
123189. DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT
123190. DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK
123191. DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT
123192. DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK
123193. DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT
123194. DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK
123195. DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT
123196. DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK
123197. DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT
123198. DPM_TABLE_126__VceLevel_3_Reserved_MASK
123199. DPM_TABLE_126__VceLevel_3_Reserved__SHIFT
123200. DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK
123201. DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT
123202. DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK
123203. DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT
123204. DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK
123205. DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT
123206. DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK
123207. DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT
123208. DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK
123209. DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT
123210. DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK
123211. DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT
123212. DPM_TABLE_127__VceLevel_4_Frequency_MASK
123213. DPM_TABLE_127__VceLevel_4_Frequency__SHIFT
123214. DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK
123215. DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT
123216. DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK
123217. DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT
123218. DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK
123219. DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT
123220. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK
123221. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT
123222. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK
123223. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT
123224. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK
123225. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT
123226. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK
123227. DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT
123228. DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK
123229. DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT
123230. DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK
123231. DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT
123232. DPM_TABLE_128__VceLevel_4_ClkBypassCntl_MASK
123233. DPM_TABLE_128__VceLevel_4_ClkBypassCntl__SHIFT
123234. DPM_TABLE_128__VceLevel_4_Divider_MASK
123235. DPM_TABLE_128__VceLevel_4_Divider__SHIFT
123236. DPM_TABLE_128__VceLevel_4_MinVoltage_MASK
123237. DPM_TABLE_128__VceLevel_4_MinVoltage__SHIFT
123238. DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK
123239. DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT
123240. DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK
123241. DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT
123242. DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK
123243. DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT
123244. DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK
123245. DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT
123246. DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK
123247. DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT
123248. DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK
123249. DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT
123250. DPM_TABLE_129__VceLevel_4_Reserved_MASK
123251. DPM_TABLE_129__VceLevel_4_Reserved__SHIFT
123252. DPM_TABLE_12__GioPIDController_LFWindupUpperLim_MASK
123253. DPM_TABLE_12__GioPIDController_LFWindupUpperLim__SHIFT
123254. DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK
123255. DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT
123256. DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK
123257. DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT
123258. DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK
123259. DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT
123260. DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK
123261. DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT
123262. DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK
123263. DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT
123264. DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK
123265. DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT
123266. DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK
123267. DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT
123268. DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK
123269. DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT
123270. DPM_TABLE_130__VceLevel_5_Frequency_MASK
123271. DPM_TABLE_130__VceLevel_5_Frequency__SHIFT
123272. DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK
123273. DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT
123274. DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK
123275. DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT
123276. DPM_TABLE_131__GraphicsLevel_4_Flags_MASK
123277. DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT
123278. DPM_TABLE_131__VceLevel_5_ClkBypassCntl_MASK
123279. DPM_TABLE_131__VceLevel_5_ClkBypassCntl__SHIFT
123280. DPM_TABLE_131__VceLevel_5_Divider_MASK
123281. DPM_TABLE_131__VceLevel_5_Divider__SHIFT
123282. DPM_TABLE_131__VceLevel_5_MinVoltage_MASK
123283. DPM_TABLE_131__VceLevel_5_MinVoltage__SHIFT
123284. DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK
123285. DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT
123286. DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK
123287. DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT
123288. DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK
123289. DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT
123290. DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK
123291. DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT
123292. DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK
123293. DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT
123294. DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK
123295. DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT
123296. DPM_TABLE_132__VceLevel_5_Reserved_MASK
123297. DPM_TABLE_132__VceLevel_5_Reserved__SHIFT
123298. DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK
123299. DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT
123300. DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK
123301. DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT
123302. DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK
123303. DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT
123304. DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK
123305. DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT
123306. DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK
123307. DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT
123308. DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK
123309. DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT
123310. DPM_TABLE_133__VceLevel_6_Frequency_MASK
123311. DPM_TABLE_133__VceLevel_6_Frequency__SHIFT
123312. DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK
123313. DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT
123314. DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK
123315. DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT
123316. DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK
123317. DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT
123318. DPM_TABLE_134__VceLevel_6_ClkBypassCntl_MASK
123319. DPM_TABLE_134__VceLevel_6_ClkBypassCntl__SHIFT
123320. DPM_TABLE_134__VceLevel_6_Divider_MASK
123321. DPM_TABLE_134__VceLevel_6_Divider__SHIFT
123322. DPM_TABLE_134__VceLevel_6_MinVoltage_MASK
123323. DPM_TABLE_134__VceLevel_6_MinVoltage__SHIFT
123324. DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK
123325. DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT
123326. DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK
123327. DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT
123328. DPM_TABLE_135__GraphicsLevel_4_padding1_0_MASK
123329. DPM_TABLE_135__GraphicsLevel_4_padding1_0__SHIFT
123330. DPM_TABLE_135__GraphicsLevel_4_padding1_1_MASK
123331. DPM_TABLE_135__GraphicsLevel_4_padding1_1__SHIFT
123332. DPM_TABLE_135__GraphicsLevel_4_padding1_MASK
123333. DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT
123334. DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK
123335. DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT
123336. DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK
123337. DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT
123338. DPM_TABLE_135__VceLevel_6_Reserved_MASK
123339. DPM_TABLE_135__VceLevel_6_Reserved__SHIFT
123340. DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK
123341. DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT
123342. DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK
123343. DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT
123344. DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK
123345. DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT
123346. DPM_TABLE_136__VceLevel_7_Frequency_MASK
123347. DPM_TABLE_136__VceLevel_7_Frequency__SHIFT
123348. DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK
123349. DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT
123350. DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK
123351. DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT
123352. DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK
123353. DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT
123354. DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK
123355. DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT
123356. DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK
123357. DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT
123358. DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK
123359. DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT
123360. DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK
123361. DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT
123362. DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK
123363. DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT
123364. DPM_TABLE_137__VceLevel_7_ClkBypassCntl_MASK
123365. DPM_TABLE_137__VceLevel_7_ClkBypassCntl__SHIFT
123366. DPM_TABLE_137__VceLevel_7_Divider_MASK
123367. DPM_TABLE_137__VceLevel_7_Divider__SHIFT
123368. DPM_TABLE_137__VceLevel_7_MinVoltage_MASK
123369. DPM_TABLE_137__VceLevel_7_MinVoltage__SHIFT
123370. DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK
123371. DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT
123372. DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK
123373. DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT
123374. DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK
123375. DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT
123376. DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK
123377. DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT
123378. DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK
123379. DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT
123380. DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK
123381. DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT
123382. DPM_TABLE_138__VceLevel_7_Reserved_MASK
123383. DPM_TABLE_138__VceLevel_7_Reserved__SHIFT
123384. DPM_TABLE_139__AcpLevel_0_Frequency_MASK
123385. DPM_TABLE_139__AcpLevel_0_Frequency__SHIFT
123386. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK
123387. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT
123388. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK
123389. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT
123390. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK
123391. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT
123392. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK
123393. DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT
123394. DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK
123395. DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT
123396. DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK
123397. DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT
123398. DPM_TABLE_13__GioPIDController_LFWindupLowerLim_MASK
123399. DPM_TABLE_13__GioPIDController_LFWindupLowerLim__SHIFT
123400. DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK
123401. DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT
123402. DPM_TABLE_140__AcpLevel_0_ClkBypassCntl_MASK
123403. DPM_TABLE_140__AcpLevel_0_ClkBypassCntl__SHIFT
123404. DPM_TABLE_140__AcpLevel_0_Divider_MASK
123405. DPM_TABLE_140__AcpLevel_0_Divider__SHIFT
123406. DPM_TABLE_140__AcpLevel_0_MinVoltage_MASK
123407. DPM_TABLE_140__AcpLevel_0_MinVoltage__SHIFT
123408. DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK
123409. DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT
123410. DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK
123411. DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT
123412. DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK
123413. DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT
123414. DPM_TABLE_141__AcpLevel_0_Reserved_MASK
123415. DPM_TABLE_141__AcpLevel_0_Reserved__SHIFT
123416. DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK
123417. DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT
123418. DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK
123419. DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT
123420. DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK
123421. DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT
123422. DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK
123423. DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT
123424. DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK
123425. DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT
123426. DPM_TABLE_142__AcpLevel_1_Frequency_MASK
123427. DPM_TABLE_142__AcpLevel_1_Frequency__SHIFT
123428. DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK
123429. DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT
123430. DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK
123431. DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT
123432. DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK
123433. DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT
123434. DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK
123435. DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT
123436. DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK
123437. DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT
123438. DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK
123439. DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT
123440. DPM_TABLE_143__AcpLevel_1_ClkBypassCntl_MASK
123441. DPM_TABLE_143__AcpLevel_1_ClkBypassCntl__SHIFT
123442. DPM_TABLE_143__AcpLevel_1_Divider_MASK
123443. DPM_TABLE_143__AcpLevel_1_Divider__SHIFT
123444. DPM_TABLE_143__AcpLevel_1_MinVoltage_MASK
123445. DPM_TABLE_143__AcpLevel_1_MinVoltage__SHIFT
123446. DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK
123447. DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT
123448. DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK
123449. DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT
123450. DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK
123451. DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT
123452. DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK
123453. DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT
123454. DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK
123455. DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT
123456. DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK
123457. DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT
123458. DPM_TABLE_144__AcpLevel_1_Reserved_MASK
123459. DPM_TABLE_144__AcpLevel_1_Reserved__SHIFT
123460. DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK
123461. DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT
123462. DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK
123463. DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT
123464. DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK
123465. DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT
123466. DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK
123467. DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT
123468. DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK
123469. DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT
123470. DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK
123471. DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT
123472. DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK
123473. DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT
123474. DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK
123475. DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT
123476. DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK
123477. DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT
123478. DPM_TABLE_145__AcpLevel_2_Frequency_MASK
123479. DPM_TABLE_145__AcpLevel_2_Frequency__SHIFT
123480. DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK
123481. DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT
123482. DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK
123483. DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT
123484. DPM_TABLE_145__GraphicsLevel_5_Flags_MASK
123485. DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT
123486. DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK
123487. DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT
123488. DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK
123489. DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT
123490. DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK
123491. DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT
123492. DPM_TABLE_146__AcpLevel_2_ClkBypassCntl_MASK
123493. DPM_TABLE_146__AcpLevel_2_ClkBypassCntl__SHIFT
123494. DPM_TABLE_146__AcpLevel_2_Divider_MASK
123495. DPM_TABLE_146__AcpLevel_2_Divider__SHIFT
123496. DPM_TABLE_146__AcpLevel_2_MinVoltage_MASK
123497. DPM_TABLE_146__AcpLevel_2_MinVoltage__SHIFT
123498. DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK
123499. DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT
123500. DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK
123501. DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT
123502. DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK
123503. DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT
123504. DPM_TABLE_147__AcpLevel_2_Reserved_MASK
123505. DPM_TABLE_147__AcpLevel_2_Reserved__SHIFT
123506. DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK
123507. DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT
123508. DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK
123509. DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT
123510. DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK
123511. DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT
123512. DPM_TABLE_148__AcpLevel_3_Frequency_MASK
123513. DPM_TABLE_148__AcpLevel_3_Frequency__SHIFT
123514. DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK
123515. DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT
123516. DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK
123517. DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT
123518. DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK
123519. DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT
123520. DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK
123521. DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT
123522. DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK
123523. DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT
123524. DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK
123525. DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT
123526. DPM_TABLE_149__AcpLevel_3_ClkBypassCntl_MASK
123527. DPM_TABLE_149__AcpLevel_3_ClkBypassCntl__SHIFT
123528. DPM_TABLE_149__AcpLevel_3_Divider_MASK
123529. DPM_TABLE_149__AcpLevel_3_Divider__SHIFT
123530. DPM_TABLE_149__AcpLevel_3_MinVoltage_MASK
123531. DPM_TABLE_149__AcpLevel_3_MinVoltage__SHIFT
123532. DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK
123533. DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT
123534. DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK
123535. DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT
123536. DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK
123537. DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT
123538. DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK
123539. DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT
123540. DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK
123541. DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT
123542. DPM_TABLE_149__GraphicsLevel_5_padding1_0_MASK
123543. DPM_TABLE_149__GraphicsLevel_5_padding1_0__SHIFT
123544. DPM_TABLE_149__GraphicsLevel_5_padding1_1_MASK
123545. DPM_TABLE_149__GraphicsLevel_5_padding1_1__SHIFT
123546. DPM_TABLE_149__GraphicsLevel_5_padding1_MASK
123547. DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT
123548. DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK
123549. DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT
123550. DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK
123551. DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT
123552. DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK
123553. DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT
123554. DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK
123555. DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT
123556. DPM_TABLE_14__GioPIDController_StatePrecision_MASK
123557. DPM_TABLE_14__GioPIDController_StatePrecision__SHIFT
123558. DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK
123559. DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT
123560. DPM_TABLE_150__AcpLevel_3_Reserved_MASK
123561. DPM_TABLE_150__AcpLevel_3_Reserved__SHIFT
123562. DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK
123563. DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT
123564. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK
123565. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT
123566. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK
123567. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT
123568. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK
123569. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT
123570. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK
123571. DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT
123572. DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK
123573. DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT
123574. DPM_TABLE_151__AcpLevel_4_Frequency_MASK
123575. DPM_TABLE_151__AcpLevel_4_Frequency__SHIFT
123576. DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK
123577. DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT
123578. DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK
123579. DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT
123580. DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK
123581. DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT
123582. DPM_TABLE_152__AcpLevel_4_ClkBypassCntl_MASK
123583. DPM_TABLE_152__AcpLevel_4_ClkBypassCntl__SHIFT
123584. DPM_TABLE_152__AcpLevel_4_Divider_MASK
123585. DPM_TABLE_152__AcpLevel_4_Divider__SHIFT
123586. DPM_TABLE_152__AcpLevel_4_MinVoltage_MASK
123587. DPM_TABLE_152__AcpLevel_4_MinVoltage__SHIFT
123588. DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK
123589. DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT
123590. DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK
123591. DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT
123592. DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK
123593. DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT
123594. DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK
123595. DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT
123596. DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK
123597. DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT
123598. DPM_TABLE_153__AcpLevel_4_Reserved_MASK
123599. DPM_TABLE_153__AcpLevel_4_Reserved__SHIFT
123600. DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK
123601. DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT
123602. DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK
123603. DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT
123604. DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK
123605. DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT
123606. DPM_TABLE_154__AcpLevel_5_Frequency_MASK
123607. DPM_TABLE_154__AcpLevel_5_Frequency__SHIFT
123608. DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK
123609. DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT
123610. DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK
123611. DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT
123612. DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK
123613. DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT
123614. DPM_TABLE_155__AcpLevel_5_ClkBypassCntl_MASK
123615. DPM_TABLE_155__AcpLevel_5_ClkBypassCntl__SHIFT
123616. DPM_TABLE_155__AcpLevel_5_Divider_MASK
123617. DPM_TABLE_155__AcpLevel_5_Divider__SHIFT
123618. DPM_TABLE_155__AcpLevel_5_MinVoltage_MASK
123619. DPM_TABLE_155__AcpLevel_5_MinVoltage__SHIFT
123620. DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK
123621. DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT
123622. DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK
123623. DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT
123624. DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK
123625. DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT
123626. DPM_TABLE_156__AcpLevel_5_Reserved_MASK
123627. DPM_TABLE_156__AcpLevel_5_Reserved__SHIFT
123628. DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK
123629. DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT
123630. DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK
123631. DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT
123632. DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK
123633. DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT
123634. DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK
123635. DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT
123636. DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK
123637. DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT
123638. DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK
123639. DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT
123640. DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK
123641. DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT
123642. DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK
123643. DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT
123644. DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK
123645. DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT
123646. DPM_TABLE_157__AcpLevel_6_Frequency_MASK
123647. DPM_TABLE_157__AcpLevel_6_Frequency__SHIFT
123648. DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK
123649. DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT
123650. DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK
123651. DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT
123652. DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK
123653. DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT
123654. DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK
123655. DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT
123656. DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK
123657. DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT
123658. DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK
123659. DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT
123660. DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK
123661. DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT
123662. DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK
123663. DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT
123664. DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK
123665. DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT
123666. DPM_TABLE_158__AcpLevel_6_ClkBypassCntl_MASK
123667. DPM_TABLE_158__AcpLevel_6_ClkBypassCntl__SHIFT
123668. DPM_TABLE_158__AcpLevel_6_Divider_MASK
123669. DPM_TABLE_158__AcpLevel_6_Divider__SHIFT
123670. DPM_TABLE_158__AcpLevel_6_MinVoltage_MASK
123671. DPM_TABLE_158__AcpLevel_6_MinVoltage__SHIFT
123672. DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK
123673. DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT
123674. DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK
123675. DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT
123676. DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK
123677. DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT
123678. DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK
123679. DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT
123680. DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK
123681. DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT
123682. DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK
123683. DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT
123684. DPM_TABLE_159__AcpLevel_6_Reserved_MASK
123685. DPM_TABLE_159__AcpLevel_6_Reserved__SHIFT
123686. DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK
123687. DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT
123688. DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK
123689. DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT
123690. DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK
123691. DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT
123692. DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK
123693. DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT
123694. DPM_TABLE_159__GraphicsLevel_6_Flags_MASK
123695. DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT
123696. DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK
123697. DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT
123698. DPM_TABLE_15__GioPIDController_LfPrecision_MASK
123699. DPM_TABLE_15__GioPIDController_LfPrecision__SHIFT
123700. DPM_TABLE_15__MemoryPIDController_LfOffset_MASK
123701. DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT
123702. DPM_TABLE_160__AcpLevel_7_Frequency_MASK
123703. DPM_TABLE_160__AcpLevel_7_Frequency__SHIFT
123704. DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK
123705. DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT
123706. DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK
123707. DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT
123708. DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK
123709. DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT
123710. DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK
123711. DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT
123712. DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK
123713. DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT
123714. DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK
123715. DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT
123716. DPM_TABLE_161__AcpLevel_7_ClkBypassCntl_MASK
123717. DPM_TABLE_161__AcpLevel_7_ClkBypassCntl__SHIFT
123718. DPM_TABLE_161__AcpLevel_7_Divider_MASK
123719. DPM_TABLE_161__AcpLevel_7_Divider__SHIFT
123720. DPM_TABLE_161__AcpLevel_7_MinVoltage_MASK
123721. DPM_TABLE_161__AcpLevel_7_MinVoltage__SHIFT
123722. DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK
123723. DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT
123724. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK
123725. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT
123726. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK
123727. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT
123728. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK
123729. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT
123730. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK
123731. DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT
123732. DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK
123733. DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT
123734. DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK
123735. DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT
123736. DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK
123737. DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT
123738. DPM_TABLE_162__AcpLevel_7_Reserved_MASK
123739. DPM_TABLE_162__AcpLevel_7_Reserved__SHIFT
123740. DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK
123741. DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT
123742. DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK
123743. DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT
123744. DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK
123745. DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT
123746. DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK
123747. DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT
123748. DPM_TABLE_163__GraphicsLevel_6_padding1_0_MASK
123749. DPM_TABLE_163__GraphicsLevel_6_padding1_0__SHIFT
123750. DPM_TABLE_163__GraphicsLevel_6_padding1_1_MASK
123751. DPM_TABLE_163__GraphicsLevel_6_padding1_1__SHIFT
123752. DPM_TABLE_163__GraphicsLevel_6_padding1_MASK
123753. DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT
123754. DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK
123755. DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT
123756. DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK
123757. DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT
123758. DPM_TABLE_163__SamuLevel_0_Frequency_MASK
123759. DPM_TABLE_163__SamuLevel_0_Frequency__SHIFT
123760. DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK
123761. DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT
123762. DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK
123763. DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT
123764. DPM_TABLE_164__SamuLevel_0_ClkBypassCntl_MASK
123765. DPM_TABLE_164__SamuLevel_0_ClkBypassCntl__SHIFT
123766. DPM_TABLE_164__SamuLevel_0_Divider_MASK
123767. DPM_TABLE_164__SamuLevel_0_Divider__SHIFT
123768. DPM_TABLE_164__SamuLevel_0_MinVoltage_MASK
123769. DPM_TABLE_164__SamuLevel_0_MinVoltage__SHIFT
123770. DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK
123771. DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT
123772. DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK
123773. DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT
123774. DPM_TABLE_165__SamuLevel_0_Reserved_MASK
123775. DPM_TABLE_165__SamuLevel_0_Reserved__SHIFT
123776. DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK
123777. DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT
123778. DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK
123779. DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT
123780. DPM_TABLE_166__SamuLevel_1_Frequency_MASK
123781. DPM_TABLE_166__SamuLevel_1_Frequency__SHIFT
123782. DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK
123783. DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT
123784. DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK
123785. DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT
123786. DPM_TABLE_167__SamuLevel_1_ClkBypassCntl_MASK
123787. DPM_TABLE_167__SamuLevel_1_ClkBypassCntl__SHIFT
123788. DPM_TABLE_167__SamuLevel_1_Divider_MASK
123789. DPM_TABLE_167__SamuLevel_1_Divider__SHIFT
123790. DPM_TABLE_167__SamuLevel_1_MinVoltage_MASK
123791. DPM_TABLE_167__SamuLevel_1_MinVoltage__SHIFT
123792. DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK
123793. DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT
123794. DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK
123795. DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT
123796. DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK
123797. DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT
123798. DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK
123799. DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT
123800. DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK
123801. DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT
123802. DPM_TABLE_168__SamuLevel_1_Reserved_MASK
123803. DPM_TABLE_168__SamuLevel_1_Reserved__SHIFT
123804. DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK
123805. DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT
123806. DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK
123807. DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT
123808. DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK
123809. DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT
123810. DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK
123811. DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT
123812. DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK
123813. DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT
123814. DPM_TABLE_169__SamuLevel_2_Frequency_MASK
123815. DPM_TABLE_169__SamuLevel_2_Frequency__SHIFT
123816. DPM_TABLE_16__GioPIDController_LfOffset_MASK
123817. DPM_TABLE_16__GioPIDController_LfOffset__SHIFT
123818. DPM_TABLE_16__MemoryPIDController_MaxState_MASK
123819. DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT
123820. DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK
123821. DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT
123822. DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK
123823. DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT
123824. DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK
123825. DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT
123826. DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK
123827. DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT
123828. DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK
123829. DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT
123830. DPM_TABLE_170__SamuLevel_2_ClkBypassCntl_MASK
123831. DPM_TABLE_170__SamuLevel_2_ClkBypassCntl__SHIFT
123832. DPM_TABLE_170__SamuLevel_2_Divider_MASK
123833. DPM_TABLE_170__SamuLevel_2_Divider__SHIFT
123834. DPM_TABLE_170__SamuLevel_2_MinVoltage_MASK
123835. DPM_TABLE_170__SamuLevel_2_MinVoltage__SHIFT
123836. DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK
123837. DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT
123838. DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK
123839. DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT
123840. DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK
123841. DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT
123842. DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK
123843. DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT
123844. DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK
123845. DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT
123846. DPM_TABLE_171__SamuLevel_2_Reserved_MASK
123847. DPM_TABLE_171__SamuLevel_2_Reserved__SHIFT
123848. DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK
123849. DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT
123850. DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK
123851. DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT
123852. DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK
123853. DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT
123854. DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK
123855. DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT
123856. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK
123857. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT
123858. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK
123859. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT
123860. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK
123861. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT
123862. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK
123863. DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT
123864. DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK
123865. DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT
123866. DPM_TABLE_172__SamuLevel_3_Frequency_MASK
123867. DPM_TABLE_172__SamuLevel_3_Frequency__SHIFT
123868. DPM_TABLE_173__GraphicsLevel_7_Flags_MASK
123869. DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT
123870. DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK
123871. DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT
123872. DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK
123873. DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT
123874. DPM_TABLE_173__SamuLevel_3_ClkBypassCntl_MASK
123875. DPM_TABLE_173__SamuLevel_3_ClkBypassCntl__SHIFT
123876. DPM_TABLE_173__SamuLevel_3_Divider_MASK
123877. DPM_TABLE_173__SamuLevel_3_Divider__SHIFT
123878. DPM_TABLE_173__SamuLevel_3_MinVoltage_MASK
123879. DPM_TABLE_173__SamuLevel_3_MinVoltage__SHIFT
123880. DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK
123881. DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT
123882. DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK
123883. DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT
123884. DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK
123885. DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT
123886. DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK
123887. DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT
123888. DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK
123889. DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT
123890. DPM_TABLE_174__SamuLevel_3_Reserved_MASK
123891. DPM_TABLE_174__SamuLevel_3_Reserved__SHIFT
123892. DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK
123893. DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT
123894. DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK
123895. DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT
123896. DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK
123897. DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT
123898. DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK
123899. DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT
123900. DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK
123901. DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT
123902. DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK
123903. DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT
123904. DPM_TABLE_175__SamuLevel_4_Frequency_MASK
123905. DPM_TABLE_175__SamuLevel_4_Frequency__SHIFT
123906. DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK
123907. DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT
123908. DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK
123909. DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT
123910. DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK
123911. DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT
123912. DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK
123913. DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT
123914. DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK
123915. DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT
123916. DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK
123917. DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT
123918. DPM_TABLE_176__SamuLevel_4_ClkBypassCntl_MASK
123919. DPM_TABLE_176__SamuLevel_4_ClkBypassCntl__SHIFT
123920. DPM_TABLE_176__SamuLevel_4_Divider_MASK
123921. DPM_TABLE_176__SamuLevel_4_Divider__SHIFT
123922. DPM_TABLE_176__SamuLevel_4_MinVoltage_MASK
123923. DPM_TABLE_176__SamuLevel_4_MinVoltage__SHIFT
123924. DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK
123925. DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT
123926. DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK
123927. DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT
123928. DPM_TABLE_177__GraphicsLevel_7_padding1_0_MASK
123929. DPM_TABLE_177__GraphicsLevel_7_padding1_0__SHIFT
123930. DPM_TABLE_177__GraphicsLevel_7_padding1_1_MASK
123931. DPM_TABLE_177__GraphicsLevel_7_padding1_1__SHIFT
123932. DPM_TABLE_177__GraphicsLevel_7_padding1_MASK
123933. DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT
123934. DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK
123935. DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT
123936. DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK
123937. DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT
123938. DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK
123939. DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT
123940. DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK
123941. DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT
123942. DPM_TABLE_177__MemoryACPILevel_padding_MASK
123943. DPM_TABLE_177__MemoryACPILevel_padding__SHIFT
123944. DPM_TABLE_177__SamuLevel_4_Reserved_MASK
123945. DPM_TABLE_177__SamuLevel_4_Reserved__SHIFT
123946. DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK
123947. DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT
123948. DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK
123949. DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT
123950. DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK
123951. DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT
123952. DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK
123953. DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT
123954. DPM_TABLE_178__MemoryACPILevel_padding1_MASK
123955. DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT
123956. DPM_TABLE_178__SamuLevel_5_Frequency_MASK
123957. DPM_TABLE_178__SamuLevel_5_Frequency__SHIFT
123958. DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK
123959. DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT
123960. DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK
123961. DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT
123962. DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK
123963. DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT
123964. DPM_TABLE_179__SamuLevel_5_ClkBypassCntl_MASK
123965. DPM_TABLE_179__SamuLevel_5_ClkBypassCntl__SHIFT
123966. DPM_TABLE_179__SamuLevel_5_Divider_MASK
123967. DPM_TABLE_179__SamuLevel_5_Divider__SHIFT
123968. DPM_TABLE_179__SamuLevel_5_MinVoltage_MASK
123969. DPM_TABLE_179__SamuLevel_5_MinVoltage__SHIFT
123970. DPM_TABLE_17__GioPIDController_MaxState_MASK
123971. DPM_TABLE_17__GioPIDController_MaxState__SHIFT
123972. DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK
123973. DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT
123974. DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK
123975. DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT
123976. DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK
123977. DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT
123978. DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK
123979. DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT
123980. DPM_TABLE_180__SamuLevel_5_Reserved_MASK
123981. DPM_TABLE_180__SamuLevel_5_Reserved__SHIFT
123982. DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK
123983. DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT
123984. DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK
123985. DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT
123986. DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK
123987. DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT
123988. DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK
123989. DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT
123990. DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK
123991. DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT
123992. DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK
123993. DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT
123994. DPM_TABLE_181__SamuLevel_6_Frequency_MASK
123995. DPM_TABLE_181__SamuLevel_6_Frequency__SHIFT
123996. DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK
123997. DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT
123998. DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK
123999. DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT
124000. DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK
124001. DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT
124002. DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK
124003. DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT
124004. DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK
124005. DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT
124006. DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK
124007. DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT
124008. DPM_TABLE_182__SamuLevel_6_ClkBypassCntl_MASK
124009. DPM_TABLE_182__SamuLevel_6_ClkBypassCntl__SHIFT
124010. DPM_TABLE_182__SamuLevel_6_Divider_MASK
124011. DPM_TABLE_182__SamuLevel_6_Divider__SHIFT
124012. DPM_TABLE_182__SamuLevel_6_MinVoltage_MASK
124013. DPM_TABLE_182__SamuLevel_6_MinVoltage__SHIFT
124014. DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK
124015. DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT
124016. DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK
124017. DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT
124018. DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK
124019. DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT
124020. DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK
124021. DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT
124022. DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK
124023. DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT
124024. DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK
124025. DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT
124026. DPM_TABLE_183__SamuLevel_6_Reserved_MASK
124027. DPM_TABLE_183__SamuLevel_6_Reserved__SHIFT
124028. DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK
124029. DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT
124030. DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK
124031. DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT
124032. DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK
124033. DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT
124034. DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK
124035. DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT
124036. DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK
124037. DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT
124038. DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK
124039. DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT
124040. DPM_TABLE_184__SamuLevel_7_Frequency_MASK
124041. DPM_TABLE_184__SamuLevel_7_Frequency__SHIFT
124042. DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK
124043. DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT
124044. DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK
124045. DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT
124046. DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK
124047. DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT
124048. DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK
124049. DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT
124050. DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK
124051. DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT
124052. DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK
124053. DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT
124054. DPM_TABLE_185__SamuLevel_7_ClkBypassCntl_MASK
124055. DPM_TABLE_185__SamuLevel_7_ClkBypassCntl__SHIFT
124056. DPM_TABLE_185__SamuLevel_7_Divider_MASK
124057. DPM_TABLE_185__SamuLevel_7_Divider__SHIFT
124058. DPM_TABLE_185__SamuLevel_7_MinVoltage_MASK
124059. DPM_TABLE_185__SamuLevel_7_MinVoltage__SHIFT
124060. DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK
124061. DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT
124062. DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK
124063. DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT
124064. DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK
124065. DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT
124066. DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK
124067. DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT
124068. DPM_TABLE_186__MemoryACPILevel_EdcReadEnable_MASK
124069. DPM_TABLE_186__MemoryACPILevel_EdcReadEnable__SHIFT
124070. DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable_MASK
124071. DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable__SHIFT
124072. DPM_TABLE_186__MemoryACPILevel_EnabledForActivity_MASK
124073. DPM_TABLE_186__MemoryACPILevel_EnabledForActivity__SHIFT
124074. DPM_TABLE_186__MemoryACPILevel_EnabledForThrottle_MASK
124075. DPM_TABLE_186__MemoryACPILevel_EnabledForThrottle__SHIFT
124076. DPM_TABLE_186__MemoryACPILevel_FreqRange_MASK
124077. DPM_TABLE_186__MemoryACPILevel_FreqRange__SHIFT
124078. DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK
124079. DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT
124080. DPM_TABLE_186__MemoryACPILevel_RttEnable_MASK
124081. DPM_TABLE_186__MemoryACPILevel_RttEnable__SHIFT
124082. DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK
124083. DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT
124084. DPM_TABLE_186__SamuLevel_7_Reserved_MASK
124085. DPM_TABLE_186__SamuLevel_7_Reserved__SHIFT
124086. DPM_TABLE_187__AcpBootLevel_MASK
124087. DPM_TABLE_187__AcpBootLevel__SHIFT
124088. DPM_TABLE_187__MemoryACPILevel_DownHyst_MASK
124089. DPM_TABLE_187__MemoryACPILevel_DownHyst__SHIFT
124090. DPM_TABLE_187__MemoryACPILevel_EnabledForActivity_MASK
124091. DPM_TABLE_187__MemoryACPILevel_EnabledForActivity__SHIFT
124092. DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle_MASK
124093. DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle__SHIFT
124094. DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK
124095. DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT
124096. DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK
124097. DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT
124098. DPM_TABLE_187__MemoryACPILevel_StrobeEnable_MASK
124099. DPM_TABLE_187__MemoryACPILevel_StrobeEnable__SHIFT
124100. DPM_TABLE_187__MemoryACPILevel_StrobeRatio_MASK
124101. DPM_TABLE_187__MemoryACPILevel_StrobeRatio__SHIFT
124102. DPM_TABLE_187__MemoryACPILevel_UpHyst_MASK
124103. DPM_TABLE_187__MemoryACPILevel_UpHyst__SHIFT
124104. DPM_TABLE_187__MemoryACPILevel_VoltageDownHyst_MASK
124105. DPM_TABLE_187__MemoryACPILevel_VoltageDownHyst__SHIFT
124106. DPM_TABLE_187__MemoryACPILevel_padding_MASK
124107. DPM_TABLE_187__MemoryACPILevel_padding__SHIFT
124108. DPM_TABLE_187__SamuBootLevel_MASK
124109. DPM_TABLE_187__SamuBootLevel__SHIFT
124110. DPM_TABLE_187__UvdBootLevel_MASK
124111. DPM_TABLE_187__UvdBootLevel__SHIFT
124112. DPM_TABLE_187__VceBootLevel_MASK
124113. DPM_TABLE_187__VceBootLevel__SHIFT
124114. DPM_TABLE_188__ACPInterval_MASK
124115. DPM_TABLE_188__ACPInterval__SHIFT
124116. DPM_TABLE_188__MemoryACPILevel_ActivityLevel_MASK
124117. DPM_TABLE_188__MemoryACPILevel_ActivityLevel__SHIFT
124118. DPM_TABLE_188__MemoryACPILevel_DisplayWatermark_MASK
124119. DPM_TABLE_188__MemoryACPILevel_DisplayWatermark__SHIFT
124120. DPM_TABLE_188__MemoryACPILevel_DownHyst_MASK
124121. DPM_TABLE_188__MemoryACPILevel_DownHyst__SHIFT
124122. DPM_TABLE_188__MemoryACPILevel_MclkDivider_MASK
124123. DPM_TABLE_188__MemoryACPILevel_MclkDivider__SHIFT
124124. DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK
124125. DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT
124126. DPM_TABLE_188__MemoryACPILevel_UpHyst_MASK
124127. DPM_TABLE_188__MemoryACPILevel_UpHyst__SHIFT
124128. DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst_MASK
124129. DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst__SHIFT
124130. DPM_TABLE_188__MemoryACPILevel_padding_MASK
124131. DPM_TABLE_188__MemoryACPILevel_padding__SHIFT
124132. DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK
124133. DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT
124134. DPM_TABLE_188__SAMUInterval_MASK
124135. DPM_TABLE_188__SAMUInterval__SHIFT
124136. DPM_TABLE_188__UVDInterval_MASK
124137. DPM_TABLE_188__UVDInterval__SHIFT
124138. DPM_TABLE_188__VCEInterval_MASK
124139. DPM_TABLE_188__VCEInterval__SHIFT
124140. DPM_TABLE_189__GraphicsBootLevel_MASK
124141. DPM_TABLE_189__GraphicsBootLevel__SHIFT
124142. DPM_TABLE_189__GraphicsInterval_MASK
124143. DPM_TABLE_189__GraphicsInterval__SHIFT
124144. DPM_TABLE_189__GraphicsThermThrottleEnable_MASK
124145. DPM_TABLE_189__GraphicsThermThrottleEnable__SHIFT
124146. DPM_TABLE_189__GraphicsVoltageChangeEnable_MASK
124147. DPM_TABLE_189__GraphicsVoltageChangeEnable__SHIFT
124148. DPM_TABLE_189__MemoryACPILevel_ActivityLevel_MASK
124149. DPM_TABLE_189__MemoryACPILevel_ActivityLevel__SHIFT
124150. DPM_TABLE_189__MemoryACPILevel_DisplayWatermark_MASK
124151. DPM_TABLE_189__MemoryACPILevel_DisplayWatermark__SHIFT
124152. DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK
124153. DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT
124154. DPM_TABLE_189__MemoryACPILevel_padding1_MASK
124155. DPM_TABLE_189__MemoryACPILevel_padding1__SHIFT
124156. DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK
124157. DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT
124158. DPM_TABLE_189__MemoryLevel_0_MinVoltage_Phases_MASK
124159. DPM_TABLE_189__MemoryLevel_0_MinVoltage_Phases__SHIFT
124160. DPM_TABLE_189__MemoryLevel_0_MinVoltage_VddGfx_MASK
124161. DPM_TABLE_189__MemoryLevel_0_MinVoltage_VddGfx__SHIFT
124162. DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddc_MASK
124163. DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddc__SHIFT
124164. DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddci_MASK
124165. DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddci__SHIFT
124166. DPM_TABLE_18__GioPIDController_MaxLfFraction_MASK
124167. DPM_TABLE_18__GioPIDController_MaxLfFraction__SHIFT
124168. DPM_TABLE_18__MemoryPIDController_StateShift_MASK
124169. DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT
124170. DPM_TABLE_190__FpsLowThreshold_MASK
124171. DPM_TABLE_190__FpsLowThreshold__SHIFT
124172. DPM_TABLE_190__GraphicsClkSlowDivider_MASK
124173. DPM_TABLE_190__GraphicsClkSlowDivider__SHIFT
124174. DPM_TABLE_190__GraphicsClkSlowEnable_MASK
124175. DPM_TABLE_190__GraphicsClkSlowEnable__SHIFT
124176. DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK
124177. DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT
124178. DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl_MASK
124179. DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl__SHIFT
124180. DPM_TABLE_190__MemoryLevel_0_MinMvdd_MASK
124181. DPM_TABLE_190__MemoryLevel_0_MinMvdd__SHIFT
124182. DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK
124183. DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT
124184. DPM_TABLE_191__DisplayCac_MASK
124185. DPM_TABLE_191__DisplayCac__SHIFT
124186. DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK
124187. DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT
124188. DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1_MASK
124189. DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1__SHIFT
124190. DPM_TABLE_191__MemoryLevel_0_MclkFrequency_MASK
124191. DPM_TABLE_191__MemoryLevel_0_MclkFrequency__SHIFT
124192. DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK
124193. DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT
124194. DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK
124195. DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT
124196. DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK
124197. DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT
124198. DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2_MASK
124199. DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2__SHIFT
124200. DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK
124201. DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT
124202. DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK
124203. DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT
124204. DPM_TABLE_192__MemoryLevel_0_EnabledForActivity_MASK
124205. DPM_TABLE_192__MemoryLevel_0_EnabledForActivity__SHIFT
124206. DPM_TABLE_192__MemoryLevel_0_EnabledForThrottle_MASK
124207. DPM_TABLE_192__MemoryLevel_0_EnabledForThrottle__SHIFT
124208. DPM_TABLE_192__MemoryLevel_0_FreqRange_MASK
124209. DPM_TABLE_192__MemoryLevel_0_FreqRange__SHIFT
124210. DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK
124211. DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT
124212. DPM_TABLE_192__MemoryLevel_0_StutterEnable_MASK
124213. DPM_TABLE_192__MemoryLevel_0_StutterEnable__SHIFT
124214. DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK
124215. DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT
124216. DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK
124217. DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT
124218. DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl_MASK
124219. DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl__SHIFT
124220. DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK
124221. DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT
124222. DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK
124223. DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT
124224. DPM_TABLE_193__MemoryLevel_0_DownHyst_MASK
124225. DPM_TABLE_193__MemoryLevel_0_DownHyst__SHIFT
124226. DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK
124227. DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT
124228. DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK
124229. DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT
124230. DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK
124231. DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT
124232. DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK
124233. DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT
124234. DPM_TABLE_193__MemoryLevel_0_UpHyst_MASK
124235. DPM_TABLE_193__MemoryLevel_0_UpHyst__SHIFT
124236. DPM_TABLE_193__MemoryLevel_0_VoltageDownHyst_MASK
124237. DPM_TABLE_193__MemoryLevel_0_VoltageDownHyst__SHIFT
124238. DPM_TABLE_193__MemoryLevel_0_padding_MASK
124239. DPM_TABLE_193__MemoryLevel_0_padding__SHIFT
124240. DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK
124241. DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT
124242. DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl_MASK
124243. DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl__SHIFT
124244. DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK
124245. DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT
124246. DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK
124247. DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT
124248. DPM_TABLE_194__MemoryACPILevel_padding_MASK
124249. DPM_TABLE_194__MemoryACPILevel_padding__SHIFT
124250. DPM_TABLE_194__MemoryLevel_0_ActivityLevel_MASK
124251. DPM_TABLE_194__MemoryLevel_0_ActivityLevel__SHIFT
124252. DPM_TABLE_194__MemoryLevel_0_DisplayWatermark_MASK
124253. DPM_TABLE_194__MemoryLevel_0_DisplayWatermark__SHIFT
124254. DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK
124255. DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT
124256. DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK
124257. DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT
124258. DPM_TABLE_194__MemoryLevel_0_MclkDivider_MASK
124259. DPM_TABLE_194__MemoryLevel_0_MclkDivider__SHIFT
124260. DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK
124261. DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT
124262. DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK
124263. DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT
124264. DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK
124265. DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT
124266. DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK
124267. DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT
124268. DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl_MASK
124269. DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl__SHIFT
124270. DPM_TABLE_195__MemoryACPILevel_padding1_0_MASK
124271. DPM_TABLE_195__MemoryACPILevel_padding1_0__SHIFT
124272. DPM_TABLE_195__MemoryACPILevel_padding1_1_MASK
124273. DPM_TABLE_195__MemoryACPILevel_padding1_1__SHIFT
124274. DPM_TABLE_195__MemoryACPILevel_padding1_MASK
124275. DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT
124276. DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK
124277. DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT
124278. DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK
124279. DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT
124280. DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK
124281. DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT
124282. DPM_TABLE_195__MemoryLevel_0_padding_MASK
124283. DPM_TABLE_195__MemoryLevel_0_padding__SHIFT
124284. DPM_TABLE_195__MemoryLevel_1_MinVoltage_Phases_MASK
124285. DPM_TABLE_195__MemoryLevel_1_MinVoltage_Phases__SHIFT
124286. DPM_TABLE_195__MemoryLevel_1_MinVoltage_VddGfx_MASK
124287. DPM_TABLE_195__MemoryLevel_1_MinVoltage_VddGfx__SHIFT
124288. DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddc_MASK
124289. DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddc__SHIFT
124290. DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddci_MASK
124291. DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddci__SHIFT
124292. DPM_TABLE_196__MemoryACPILevel_DllCntl_MASK
124293. DPM_TABLE_196__MemoryACPILevel_DllCntl__SHIFT
124294. DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK
124295. DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT
124296. DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK
124297. DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT
124298. DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK
124299. DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT
124300. DPM_TABLE_196__MemoryLevel_0_padding1_MASK
124301. DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT
124302. DPM_TABLE_196__MemoryLevel_1_MinMvdd_MASK
124303. DPM_TABLE_196__MemoryLevel_1_MinMvdd__SHIFT
124304. DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK
124305. DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT
124306. DPM_TABLE_197__MemoryACPILevel_MpllSs1_MASK
124307. DPM_TABLE_197__MemoryACPILevel_MpllSs1__SHIFT
124308. DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK
124309. DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT
124310. DPM_TABLE_197__MemoryLevel_1_MclkFrequency_MASK
124311. DPM_TABLE_197__MemoryLevel_1_MclkFrequency__SHIFT
124312. DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK
124313. DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT
124314. DPM_TABLE_198__MemoryACPILevel_MpllSs2_MASK
124315. DPM_TABLE_198__MemoryACPILevel_MpllSs2__SHIFT
124316. DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK
124317. DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT
124318. DPM_TABLE_198__MemoryLevel_1_EnabledForActivity_MASK
124319. DPM_TABLE_198__MemoryLevel_1_EnabledForActivity__SHIFT
124320. DPM_TABLE_198__MemoryLevel_1_EnabledForThrottle_MASK
124321. DPM_TABLE_198__MemoryLevel_1_EnabledForThrottle__SHIFT
124322. DPM_TABLE_198__MemoryLevel_1_FreqRange_MASK
124323. DPM_TABLE_198__MemoryLevel_1_FreqRange__SHIFT
124324. DPM_TABLE_198__MemoryLevel_1_StutterEnable_MASK
124325. DPM_TABLE_198__MemoryLevel_1_StutterEnable__SHIFT
124326. DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK
124327. DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT
124328. DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases_MASK
124329. DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases__SHIFT
124330. DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx_MASK
124331. DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx__SHIFT
124332. DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc_MASK
124333. DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc__SHIFT
124334. DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci_MASK
124335. DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci__SHIFT
124336. DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK
124337. DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT
124338. DPM_TABLE_199__MemoryLevel_1_DownHyst_MASK
124339. DPM_TABLE_199__MemoryLevel_1_DownHyst__SHIFT
124340. DPM_TABLE_199__MemoryLevel_1_UpHyst_MASK
124341. DPM_TABLE_199__MemoryLevel_1_UpHyst__SHIFT
124342. DPM_TABLE_199__MemoryLevel_1_VoltageDownHyst_MASK
124343. DPM_TABLE_199__MemoryLevel_1_VoltageDownHyst__SHIFT
124344. DPM_TABLE_199__MemoryLevel_1_padding_MASK
124345. DPM_TABLE_199__MemoryLevel_1_padding__SHIFT
124346. DPM_TABLE_19__GioPIDController_StateShift_MASK
124347. DPM_TABLE_19__GioPIDController_StateShift__SHIFT
124348. DPM_TABLE_19__LinkPIDController_Ki_MASK
124349. DPM_TABLE_19__LinkPIDController_Ki__SHIFT
124350. DPM_TABLE_1__GraphicsPIDController_Ki_MASK
124351. DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT
124352. DPM_TABLE_1__SystemFlags_MASK
124353. DPM_TABLE_1__SystemFlags__SHIFT
124354. DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK
124355. DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT
124356. DPM_TABLE_200__MemoryLevel_0_MinMvdd_MASK
124357. DPM_TABLE_200__MemoryLevel_0_MinMvdd__SHIFT
124358. DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK
124359. DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT
124360. DPM_TABLE_200__MemoryLevel_1_ActivityLevel_MASK
124361. DPM_TABLE_200__MemoryLevel_1_ActivityLevel__SHIFT
124362. DPM_TABLE_200__MemoryLevel_1_DisplayWatermark_MASK
124363. DPM_TABLE_200__MemoryLevel_1_DisplayWatermark__SHIFT
124364. DPM_TABLE_200__MemoryLevel_1_MclkDivider_MASK
124365. DPM_TABLE_200__MemoryLevel_1_MclkDivider__SHIFT
124366. DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK
124367. DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT
124368. DPM_TABLE_201__MemoryLevel_0_MclkFrequency_MASK
124369. DPM_TABLE_201__MemoryLevel_0_MclkFrequency__SHIFT
124370. DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK
124371. DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT
124372. DPM_TABLE_201__MemoryLevel_2_MinVoltage_Phases_MASK
124373. DPM_TABLE_201__MemoryLevel_2_MinVoltage_Phases__SHIFT
124374. DPM_TABLE_201__MemoryLevel_2_MinVoltage_VddGfx_MASK
124375. DPM_TABLE_201__MemoryLevel_2_MinVoltage_VddGfx__SHIFT
124376. DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddc_MASK
124377. DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddc__SHIFT
124378. DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddci_MASK
124379. DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddci__SHIFT
124380. DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK
124381. DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT
124382. DPM_TABLE_202__MemoryLevel_0_EdcReadEnable_MASK
124383. DPM_TABLE_202__MemoryLevel_0_EdcReadEnable__SHIFT
124384. DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable_MASK
124385. DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable__SHIFT
124386. DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK
124387. DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT
124388. DPM_TABLE_202__MemoryLevel_0_RttEnable_MASK
124389. DPM_TABLE_202__MemoryLevel_0_RttEnable__SHIFT
124390. DPM_TABLE_202__MemoryLevel_0_StutterEnable_MASK
124391. DPM_TABLE_202__MemoryLevel_0_StutterEnable__SHIFT
124392. DPM_TABLE_202__MemoryLevel_2_MinMvdd_MASK
124393. DPM_TABLE_202__MemoryLevel_2_MinMvdd__SHIFT
124394. DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK
124395. DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT
124396. DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK
124397. DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT
124398. DPM_TABLE_203__MemoryLevel_0_EnabledForActivity_MASK
124399. DPM_TABLE_203__MemoryLevel_0_EnabledForActivity__SHIFT
124400. DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle_MASK
124401. DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle__SHIFT
124402. DPM_TABLE_203__MemoryLevel_0_StrobeEnable_MASK
124403. DPM_TABLE_203__MemoryLevel_0_StrobeEnable__SHIFT
124404. DPM_TABLE_203__MemoryLevel_0_StrobeRatio_MASK
124405. DPM_TABLE_203__MemoryLevel_0_StrobeRatio__SHIFT
124406. DPM_TABLE_203__MemoryLevel_2_MclkFrequency_MASK
124407. DPM_TABLE_203__MemoryLevel_2_MclkFrequency__SHIFT
124408. DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK
124409. DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT
124410. DPM_TABLE_204__MemoryLevel_0_DownHyst_MASK
124411. DPM_TABLE_204__MemoryLevel_0_DownHyst__SHIFT
124412. DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK
124413. DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT
124414. DPM_TABLE_204__MemoryLevel_0_UpHyst_MASK
124415. DPM_TABLE_204__MemoryLevel_0_UpHyst__SHIFT
124416. DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst_MASK
124417. DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst__SHIFT
124418. DPM_TABLE_204__MemoryLevel_0_padding_MASK
124419. DPM_TABLE_204__MemoryLevel_0_padding__SHIFT
124420. DPM_TABLE_204__MemoryLevel_2_EnabledForActivity_MASK
124421. DPM_TABLE_204__MemoryLevel_2_EnabledForActivity__SHIFT
124422. DPM_TABLE_204__MemoryLevel_2_EnabledForThrottle_MASK
124423. DPM_TABLE_204__MemoryLevel_2_EnabledForThrottle__SHIFT
124424. DPM_TABLE_204__MemoryLevel_2_FreqRange_MASK
124425. DPM_TABLE_204__MemoryLevel_2_FreqRange__SHIFT
124426. DPM_TABLE_204__MemoryLevel_2_StutterEnable_MASK
124427. DPM_TABLE_204__MemoryLevel_2_StutterEnable__SHIFT
124428. DPM_TABLE_205__MemoryLevel_0_ActivityLevel_MASK
124429. DPM_TABLE_205__MemoryLevel_0_ActivityLevel__SHIFT
124430. DPM_TABLE_205__MemoryLevel_0_DisplayWatermark_MASK
124431. DPM_TABLE_205__MemoryLevel_0_DisplayWatermark__SHIFT
124432. DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK
124433. DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT
124434. DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK
124435. DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT
124436. DPM_TABLE_205__MemoryLevel_0_padding1_MASK
124437. DPM_TABLE_205__MemoryLevel_0_padding1__SHIFT
124438. DPM_TABLE_205__MemoryLevel_2_DownHyst_MASK
124439. DPM_TABLE_205__MemoryLevel_2_DownHyst__SHIFT
124440. DPM_TABLE_205__MemoryLevel_2_UpHyst_MASK
124441. DPM_TABLE_205__MemoryLevel_2_UpHyst__SHIFT
124442. DPM_TABLE_205__MemoryLevel_2_VoltageDownHyst_MASK
124443. DPM_TABLE_205__MemoryLevel_2_VoltageDownHyst__SHIFT
124444. DPM_TABLE_205__MemoryLevel_2_padding_MASK
124445. DPM_TABLE_205__MemoryLevel_2_padding__SHIFT
124446. DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK
124447. DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT
124448. DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl_MASK
124449. DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl__SHIFT
124450. DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK
124451. DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT
124452. DPM_TABLE_206__MemoryLevel_2_ActivityLevel_MASK
124453. DPM_TABLE_206__MemoryLevel_2_ActivityLevel__SHIFT
124454. DPM_TABLE_206__MemoryLevel_2_DisplayWatermark_MASK
124455. DPM_TABLE_206__MemoryLevel_2_DisplayWatermark__SHIFT
124456. DPM_TABLE_206__MemoryLevel_2_MclkDivider_MASK
124457. DPM_TABLE_206__MemoryLevel_2_MclkDivider__SHIFT
124458. DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK
124459. DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT
124460. DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1_MASK
124461. DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1__SHIFT
124462. DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK
124463. DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT
124464. DPM_TABLE_207__MemoryLevel_3_MinVoltage_Phases_MASK
124465. DPM_TABLE_207__MemoryLevel_3_MinVoltage_Phases__SHIFT
124466. DPM_TABLE_207__MemoryLevel_3_MinVoltage_VddGfx_MASK
124467. DPM_TABLE_207__MemoryLevel_3_MinVoltage_VddGfx__SHIFT
124468. DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddc_MASK
124469. DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddc__SHIFT
124470. DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddci_MASK
124471. DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddci__SHIFT
124472. DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK
124473. DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT
124474. DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2_MASK
124475. DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2__SHIFT
124476. DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK
124477. DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT
124478. DPM_TABLE_208__MemoryLevel_3_MinMvdd_MASK
124479. DPM_TABLE_208__MemoryLevel_3_MinMvdd__SHIFT
124480. DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK
124481. DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT
124482. DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl_MASK
124483. DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl__SHIFT
124484. DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK
124485. DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT
124486. DPM_TABLE_209__MemoryLevel_3_MclkFrequency_MASK
124487. DPM_TABLE_209__MemoryLevel_3_MclkFrequency__SHIFT
124488. DPM_TABLE_20__GIOLevelCount_MASK
124489. DPM_TABLE_20__GIOLevelCount__SHIFT
124490. DPM_TABLE_20__GraphicsDpmLevelCount_MASK
124491. DPM_TABLE_20__GraphicsDpmLevelCount__SHIFT
124492. DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK
124493. DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT
124494. DPM_TABLE_20__UvdLevelCount_MASK
124495. DPM_TABLE_20__UvdLevelCount__SHIFT
124496. DPM_TABLE_20__VceLevelCount_MASK
124497. DPM_TABLE_20__VceLevelCount__SHIFT
124498. DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK
124499. DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT
124500. DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK
124501. DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT
124502. DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl_MASK
124503. DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl__SHIFT
124504. DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK
124505. DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT
124506. DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK
124507. DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT
124508. DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK
124509. DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT
124510. DPM_TABLE_210__MemoryLevel_3_EnabledForActivity_MASK
124511. DPM_TABLE_210__MemoryLevel_3_EnabledForActivity__SHIFT
124512. DPM_TABLE_210__MemoryLevel_3_EnabledForThrottle_MASK
124513. DPM_TABLE_210__MemoryLevel_3_EnabledForThrottle__SHIFT
124514. DPM_TABLE_210__MemoryLevel_3_FreqRange_MASK
124515. DPM_TABLE_210__MemoryLevel_3_FreqRange__SHIFT
124516. DPM_TABLE_210__MemoryLevel_3_StutterEnable_MASK
124517. DPM_TABLE_210__MemoryLevel_3_StutterEnable__SHIFT
124518. DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK
124519. DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT
124520. DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK
124521. DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT
124522. DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl_MASK
124523. DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl__SHIFT
124524. DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK
124525. DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT
124526. DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK
124527. DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT
124528. DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK
124529. DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT
124530. DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK
124531. DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT
124532. DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK
124533. DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT
124534. DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK
124535. DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT
124536. DPM_TABLE_211__MemoryLevel_3_DownHyst_MASK
124537. DPM_TABLE_211__MemoryLevel_3_DownHyst__SHIFT
124538. DPM_TABLE_211__MemoryLevel_3_UpHyst_MASK
124539. DPM_TABLE_211__MemoryLevel_3_UpHyst__SHIFT
124540. DPM_TABLE_211__MemoryLevel_3_VoltageDownHyst_MASK
124541. DPM_TABLE_211__MemoryLevel_3_VoltageDownHyst__SHIFT
124542. DPM_TABLE_211__MemoryLevel_3_padding_MASK
124543. DPM_TABLE_211__MemoryLevel_3_padding__SHIFT
124544. DPM_TABLE_212__MemoryLevel_0_DllCntl_MASK
124545. DPM_TABLE_212__MemoryLevel_0_DllCntl__SHIFT
124546. DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK
124547. DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT
124548. DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK
124549. DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT
124550. DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK
124551. DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT
124552. DPM_TABLE_212__MemoryLevel_0_padding_MASK
124553. DPM_TABLE_212__MemoryLevel_0_padding__SHIFT
124554. DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK
124555. DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT
124556. DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK
124557. DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT
124558. DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK
124559. DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT
124560. DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK
124561. DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT
124562. DPM_TABLE_212__MemoryLevel_3_ActivityLevel_MASK
124563. DPM_TABLE_212__MemoryLevel_3_ActivityLevel__SHIFT
124564. DPM_TABLE_212__MemoryLevel_3_DisplayWatermark_MASK
124565. DPM_TABLE_212__MemoryLevel_3_DisplayWatermark__SHIFT
124566. DPM_TABLE_212__MemoryLevel_3_MclkDivider_MASK
124567. DPM_TABLE_212__MemoryLevel_3_MclkDivider__SHIFT
124568. DPM_TABLE_213__LinkLevel_0_EnabledForActivity_MASK
124569. DPM_TABLE_213__LinkLevel_0_EnabledForActivity__SHIFT
124570. DPM_TABLE_213__LinkLevel_0_PcieGenSpeed_MASK
124571. DPM_TABLE_213__LinkLevel_0_PcieGenSpeed__SHIFT
124572. DPM_TABLE_213__LinkLevel_0_PcieLaneCount_MASK
124573. DPM_TABLE_213__LinkLevel_0_PcieLaneCount__SHIFT
124574. DPM_TABLE_213__LinkLevel_0_SPC_MASK
124575. DPM_TABLE_213__LinkLevel_0_SPC__SHIFT
124576. DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK
124577. DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT
124578. DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK
124579. DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT
124580. DPM_TABLE_213__MemoryLevel_0_MpllSs1_MASK
124581. DPM_TABLE_213__MemoryLevel_0_MpllSs1__SHIFT
124582. DPM_TABLE_213__MemoryLevel_0_padding1_0_MASK
124583. DPM_TABLE_213__MemoryLevel_0_padding1_0__SHIFT
124584. DPM_TABLE_213__MemoryLevel_0_padding1_1_MASK
124585. DPM_TABLE_213__MemoryLevel_0_padding1_1__SHIFT
124586. DPM_TABLE_213__MemoryLevel_0_padding1_MASK
124587. DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT
124588. DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK
124589. DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT
124590. DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK
124591. DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT
124592. DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK
124593. DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT
124594. DPM_TABLE_213__MemoryLevel_1_padding_MASK
124595. DPM_TABLE_213__MemoryLevel_1_padding__SHIFT
124596. DPM_TABLE_214__LinkLevel_0_DownThreshold_MASK
124597. DPM_TABLE_214__LinkLevel_0_DownThreshold__SHIFT
124598. DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK
124599. DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT
124600. DPM_TABLE_214__MemoryLevel_0_MpllSs2_MASK
124601. DPM_TABLE_214__MemoryLevel_0_MpllSs2__SHIFT
124602. DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK
124603. DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT
124604. DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK
124605. DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT
124606. DPM_TABLE_214__MemoryLevel_1_padding1_MASK
124607. DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT
124608. DPM_TABLE_215__LinkLevel_0_UpThreshold_MASK
124609. DPM_TABLE_215__LinkLevel_0_UpThreshold__SHIFT
124610. DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK
124611. DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT
124612. DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases_MASK
124613. DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases__SHIFT
124614. DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx_MASK
124615. DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx__SHIFT
124616. DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc_MASK
124617. DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc__SHIFT
124618. DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci_MASK
124619. DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci__SHIFT
124620. DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK
124621. DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT
124622. DPM_TABLE_216__LinkLevel_0_Reserved_MASK
124623. DPM_TABLE_216__LinkLevel_0_Reserved__SHIFT
124624. DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK
124625. DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT
124626. DPM_TABLE_216__MemoryLevel_1_MinMvdd_MASK
124627. DPM_TABLE_216__MemoryLevel_1_MinMvdd__SHIFT
124628. DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK
124629. DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT
124630. DPM_TABLE_217__LinkLevel_1_EnabledForActivity_MASK
124631. DPM_TABLE_217__LinkLevel_1_EnabledForActivity__SHIFT
124632. DPM_TABLE_217__LinkLevel_1_PcieGenSpeed_MASK
124633. DPM_TABLE_217__LinkLevel_1_PcieGenSpeed__SHIFT
124634. DPM_TABLE_217__LinkLevel_1_PcieLaneCount_MASK
124635. DPM_TABLE_217__LinkLevel_1_PcieLaneCount__SHIFT
124636. DPM_TABLE_217__LinkLevel_1_SPC_MASK
124637. DPM_TABLE_217__LinkLevel_1_SPC__SHIFT
124638. DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK
124639. DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT
124640. DPM_TABLE_217__MemoryLevel_1_MclkFrequency_MASK
124641. DPM_TABLE_217__MemoryLevel_1_MclkFrequency__SHIFT
124642. DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK
124643. DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT
124644. DPM_TABLE_218__LinkLevel_1_DownThreshold_MASK
124645. DPM_TABLE_218__LinkLevel_1_DownThreshold__SHIFT
124646. DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK
124647. DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT
124648. DPM_TABLE_218__MemoryLevel_1_EdcReadEnable_MASK
124649. DPM_TABLE_218__MemoryLevel_1_EdcReadEnable__SHIFT
124650. DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable_MASK
124651. DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable__SHIFT
124652. DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK
124653. DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT
124654. DPM_TABLE_218__MemoryLevel_1_RttEnable_MASK
124655. DPM_TABLE_218__MemoryLevel_1_RttEnable__SHIFT
124656. DPM_TABLE_218__MemoryLevel_1_StutterEnable_MASK
124657. DPM_TABLE_218__MemoryLevel_1_StutterEnable__SHIFT
124658. DPM_TABLE_219__LinkLevel_1_UpThreshold_MASK
124659. DPM_TABLE_219__LinkLevel_1_UpThreshold__SHIFT
124660. DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK
124661. DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT
124662. DPM_TABLE_219__MemoryLevel_1_EnabledForActivity_MASK
124663. DPM_TABLE_219__MemoryLevel_1_EnabledForActivity__SHIFT
124664. DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle_MASK
124665. DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle__SHIFT
124666. DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK
124667. DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT
124668. DPM_TABLE_219__MemoryLevel_1_StrobeEnable_MASK
124669. DPM_TABLE_219__MemoryLevel_1_StrobeEnable__SHIFT
124670. DPM_TABLE_219__MemoryLevel_1_StrobeRatio_MASK
124671. DPM_TABLE_219__MemoryLevel_1_StrobeRatio__SHIFT
124672. DPM_TABLE_21__AcpLevelCount_MASK
124673. DPM_TABLE_21__AcpLevelCount__SHIFT
124674. DPM_TABLE_21__FpsHighThreshold_MASK
124675. DPM_TABLE_21__FpsHighThreshold__SHIFT
124676. DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK
124677. DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT
124678. DPM_TABLE_21__SamuLevelCount_MASK
124679. DPM_TABLE_21__SamuLevelCount__SHIFT
124680. DPM_TABLE_220__LinkLevel_1_Reserved_MASK
124681. DPM_TABLE_220__LinkLevel_1_Reserved__SHIFT
124682. DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK
124683. DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT
124684. DPM_TABLE_220__MemoryLevel_1_DownHyst_MASK
124685. DPM_TABLE_220__MemoryLevel_1_DownHyst__SHIFT
124686. DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK
124687. DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT
124688. DPM_TABLE_220__MemoryLevel_1_UpHyst_MASK
124689. DPM_TABLE_220__MemoryLevel_1_UpHyst__SHIFT
124690. DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst_MASK
124691. DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst__SHIFT
124692. DPM_TABLE_220__MemoryLevel_1_padding_MASK
124693. DPM_TABLE_220__MemoryLevel_1_padding__SHIFT
124694. DPM_TABLE_221__LinkLevel_2_EnabledForActivity_MASK
124695. DPM_TABLE_221__LinkLevel_2_EnabledForActivity__SHIFT
124696. DPM_TABLE_221__LinkLevel_2_PcieGenSpeed_MASK
124697. DPM_TABLE_221__LinkLevel_2_PcieGenSpeed__SHIFT
124698. DPM_TABLE_221__LinkLevel_2_PcieLaneCount_MASK
124699. DPM_TABLE_221__LinkLevel_2_PcieLaneCount__SHIFT
124700. DPM_TABLE_221__LinkLevel_2_SPC_MASK
124701. DPM_TABLE_221__LinkLevel_2_SPC__SHIFT
124702. DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK
124703. DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT
124704. DPM_TABLE_221__MemoryLevel_1_ActivityLevel_MASK
124705. DPM_TABLE_221__MemoryLevel_1_ActivityLevel__SHIFT
124706. DPM_TABLE_221__MemoryLevel_1_DisplayWatermark_MASK
124707. DPM_TABLE_221__MemoryLevel_1_DisplayWatermark__SHIFT
124708. DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK
124709. DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT
124710. DPM_TABLE_221__MemoryLevel_1_padding1_MASK
124711. DPM_TABLE_221__MemoryLevel_1_padding1__SHIFT
124712. DPM_TABLE_222__LinkLevel_2_DownThreshold_MASK
124713. DPM_TABLE_222__LinkLevel_2_DownThreshold__SHIFT
124714. DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK
124715. DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT
124716. DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl_MASK
124717. DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl__SHIFT
124718. DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK
124719. DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT
124720. DPM_TABLE_223__LinkLevel_2_UpThreshold_MASK
124721. DPM_TABLE_223__LinkLevel_2_UpThreshold__SHIFT
124722. DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK
124723. DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT
124724. DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1_MASK
124725. DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1__SHIFT
124726. DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK
124727. DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT
124728. DPM_TABLE_224__LinkLevel_2_Reserved_MASK
124729. DPM_TABLE_224__LinkLevel_2_Reserved__SHIFT
124730. DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK
124731. DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT
124732. DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2_MASK
124733. DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2__SHIFT
124734. DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK
124735. DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT
124736. DPM_TABLE_225__LinkLevel_3_EnabledForActivity_MASK
124737. DPM_TABLE_225__LinkLevel_3_EnabledForActivity__SHIFT
124738. DPM_TABLE_225__LinkLevel_3_PcieGenSpeed_MASK
124739. DPM_TABLE_225__LinkLevel_3_PcieGenSpeed__SHIFT
124740. DPM_TABLE_225__LinkLevel_3_PcieLaneCount_MASK
124741. DPM_TABLE_225__LinkLevel_3_PcieLaneCount__SHIFT
124742. DPM_TABLE_225__LinkLevel_3_SPC_MASK
124743. DPM_TABLE_225__LinkLevel_3_SPC__SHIFT
124744. DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK
124745. DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT
124746. DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl_MASK
124747. DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl__SHIFT
124748. DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK
124749. DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT
124750. DPM_TABLE_226__LinkLevel_3_DownThreshold_MASK
124751. DPM_TABLE_226__LinkLevel_3_DownThreshold__SHIFT
124752. DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK
124753. DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT
124754. DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl_MASK
124755. DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl__SHIFT
124756. DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK
124757. DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT
124758. DPM_TABLE_227__LinkLevel_3_UpThreshold_MASK
124759. DPM_TABLE_227__LinkLevel_3_UpThreshold__SHIFT
124760. DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK
124761. DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT
124762. DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl_MASK
124763. DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl__SHIFT
124764. DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK
124765. DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT
124766. DPM_TABLE_228__LinkLevel_3_Reserved_MASK
124767. DPM_TABLE_228__LinkLevel_3_Reserved__SHIFT
124768. DPM_TABLE_228__MemoryLevel_1_DllCntl_MASK
124769. DPM_TABLE_228__MemoryLevel_1_DllCntl__SHIFT
124770. DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK
124771. DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT
124772. DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK
124773. DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT
124774. DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK
124775. DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT
124776. DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK
124777. DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT
124778. DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK
124779. DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT
124780. DPM_TABLE_229__LinkLevel_4_EnabledForActivity_MASK
124781. DPM_TABLE_229__LinkLevel_4_EnabledForActivity__SHIFT
124782. DPM_TABLE_229__LinkLevel_4_PcieGenSpeed_MASK
124783. DPM_TABLE_229__LinkLevel_4_PcieGenSpeed__SHIFT
124784. DPM_TABLE_229__LinkLevel_4_PcieLaneCount_MASK
124785. DPM_TABLE_229__LinkLevel_4_PcieLaneCount__SHIFT
124786. DPM_TABLE_229__LinkLevel_4_SPC_MASK
124787. DPM_TABLE_229__LinkLevel_4_SPC__SHIFT
124788. DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK
124789. DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT
124790. DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK
124791. DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT
124792. DPM_TABLE_229__MemoryLevel_1_MpllSs1_MASK
124793. DPM_TABLE_229__MemoryLevel_1_MpllSs1__SHIFT
124794. DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK
124795. DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT
124796. DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK
124797. DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT
124798. DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK
124799. DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT
124800. DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK
124801. DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT
124802. DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK
124803. DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT
124804. DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK
124805. DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT
124806. DPM_TABLE_22__GraphicsLevel_0_MinVddNb_MASK
124807. DPM_TABLE_22__GraphicsLevel_0_MinVddNb__SHIFT
124808. DPM_TABLE_22__LinkPIDController_StatePrecision_MASK
124809. DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT
124810. DPM_TABLE_230__LinkLevel_4_DownThreshold_MASK
124811. DPM_TABLE_230__LinkLevel_4_DownThreshold__SHIFT
124812. DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK
124813. DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT
124814. DPM_TABLE_230__MemoryLevel_1_MpllSs2_MASK
124815. DPM_TABLE_230__MemoryLevel_1_MpllSs2__SHIFT
124816. DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK
124817. DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT
124818. DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK
124819. DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT
124820. DPM_TABLE_230__MemoryLevel_1_padding_MASK
124821. DPM_TABLE_230__MemoryLevel_1_padding__SHIFT
124822. DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK
124823. DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT
124824. DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK
124825. DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT
124826. DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK
124827. DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT
124828. DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK
124829. DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT
124830. DPM_TABLE_231__LinkLevel_4_UpThreshold_MASK
124831. DPM_TABLE_231__LinkLevel_4_UpThreshold__SHIFT
124832. DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK
124833. DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT
124834. DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK
124835. DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT
124836. DPM_TABLE_231__MemoryLevel_1_padding1_0_MASK
124837. DPM_TABLE_231__MemoryLevel_1_padding1_0__SHIFT
124838. DPM_TABLE_231__MemoryLevel_1_padding1_1_MASK
124839. DPM_TABLE_231__MemoryLevel_1_padding1_1__SHIFT
124840. DPM_TABLE_231__MemoryLevel_1_padding1_MASK
124841. DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT
124842. DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK
124843. DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT
124844. DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases_MASK
124845. DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases__SHIFT
124846. DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx_MASK
124847. DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx__SHIFT
124848. DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc_MASK
124849. DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc__SHIFT
124850. DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci_MASK
124851. DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci__SHIFT
124852. DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK
124853. DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT
124854. DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK
124855. DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT
124856. DPM_TABLE_231__MemoryLevel_2_padding_MASK
124857. DPM_TABLE_231__MemoryLevel_2_padding__SHIFT
124858. DPM_TABLE_232__LinkLevel_4_Reserved_MASK
124859. DPM_TABLE_232__LinkLevel_4_Reserved__SHIFT
124860. DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK
124861. DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT
124862. DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK
124863. DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT
124864. DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK
124865. DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT
124866. DPM_TABLE_232__MemoryLevel_2_MinMvdd_MASK
124867. DPM_TABLE_232__MemoryLevel_2_MinMvdd__SHIFT
124868. DPM_TABLE_232__MemoryLevel_2_padding1_MASK
124869. DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT
124870. DPM_TABLE_233__LinkLevel_5_EnabledForActivity_MASK
124871. DPM_TABLE_233__LinkLevel_5_EnabledForActivity__SHIFT
124872. DPM_TABLE_233__LinkLevel_5_PcieGenSpeed_MASK
124873. DPM_TABLE_233__LinkLevel_5_PcieGenSpeed__SHIFT
124874. DPM_TABLE_233__LinkLevel_5_PcieLaneCount_MASK
124875. DPM_TABLE_233__LinkLevel_5_PcieLaneCount__SHIFT
124876. DPM_TABLE_233__LinkLevel_5_SPC_MASK
124877. DPM_TABLE_233__LinkLevel_5_SPC__SHIFT
124878. DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK
124879. DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT
124880. DPM_TABLE_233__MemoryLevel_2_MclkFrequency_MASK
124881. DPM_TABLE_233__MemoryLevel_2_MclkFrequency__SHIFT
124882. DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK
124883. DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT
124884. DPM_TABLE_234__LinkLevel_5_DownThreshold_MASK
124885. DPM_TABLE_234__LinkLevel_5_DownThreshold__SHIFT
124886. DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK
124887. DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT
124888. DPM_TABLE_234__MemoryLevel_2_EdcReadEnable_MASK
124889. DPM_TABLE_234__MemoryLevel_2_EdcReadEnable__SHIFT
124890. DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable_MASK
124891. DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable__SHIFT
124892. DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK
124893. DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT
124894. DPM_TABLE_234__MemoryLevel_2_RttEnable_MASK
124895. DPM_TABLE_234__MemoryLevel_2_RttEnable__SHIFT
124896. DPM_TABLE_234__MemoryLevel_2_StutterEnable_MASK
124897. DPM_TABLE_234__MemoryLevel_2_StutterEnable__SHIFT
124898. DPM_TABLE_235__LinkLevel_5_UpThreshold_MASK
124899. DPM_TABLE_235__LinkLevel_5_UpThreshold__SHIFT
124900. DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK
124901. DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT
124902. DPM_TABLE_235__MemoryLevel_2_EnabledForActivity_MASK
124903. DPM_TABLE_235__MemoryLevel_2_EnabledForActivity__SHIFT
124904. DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle_MASK
124905. DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle__SHIFT
124906. DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK
124907. DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT
124908. DPM_TABLE_235__MemoryLevel_2_StrobeEnable_MASK
124909. DPM_TABLE_235__MemoryLevel_2_StrobeEnable__SHIFT
124910. DPM_TABLE_235__MemoryLevel_2_StrobeRatio_MASK
124911. DPM_TABLE_235__MemoryLevel_2_StrobeRatio__SHIFT
124912. DPM_TABLE_236__LinkLevel_5_Reserved_MASK
124913. DPM_TABLE_236__LinkLevel_5_Reserved__SHIFT
124914. DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK
124915. DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT
124916. DPM_TABLE_236__MemoryLevel_2_DownHyst_MASK
124917. DPM_TABLE_236__MemoryLevel_2_DownHyst__SHIFT
124918. DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK
124919. DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT
124920. DPM_TABLE_236__MemoryLevel_2_UpHyst_MASK
124921. DPM_TABLE_236__MemoryLevel_2_UpHyst__SHIFT
124922. DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst_MASK
124923. DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst__SHIFT
124924. DPM_TABLE_236__MemoryLevel_2_padding_MASK
124925. DPM_TABLE_236__MemoryLevel_2_padding__SHIFT
124926. DPM_TABLE_237__LinkLevel_6_EnabledForActivity_MASK
124927. DPM_TABLE_237__LinkLevel_6_EnabledForActivity__SHIFT
124928. DPM_TABLE_237__LinkLevel_6_PcieGenSpeed_MASK
124929. DPM_TABLE_237__LinkLevel_6_PcieGenSpeed__SHIFT
124930. DPM_TABLE_237__LinkLevel_6_PcieLaneCount_MASK
124931. DPM_TABLE_237__LinkLevel_6_PcieLaneCount__SHIFT
124932. DPM_TABLE_237__LinkLevel_6_SPC_MASK
124933. DPM_TABLE_237__LinkLevel_6_SPC__SHIFT
124934. DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK
124935. DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT
124936. DPM_TABLE_237__MemoryLevel_2_ActivityLevel_MASK
124937. DPM_TABLE_237__MemoryLevel_2_ActivityLevel__SHIFT
124938. DPM_TABLE_237__MemoryLevel_2_DisplayWatermark_MASK
124939. DPM_TABLE_237__MemoryLevel_2_DisplayWatermark__SHIFT
124940. DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK
124941. DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT
124942. DPM_TABLE_237__MemoryLevel_2_padding1_MASK
124943. DPM_TABLE_237__MemoryLevel_2_padding1__SHIFT
124944. DPM_TABLE_238__LinkLevel_6_DownThreshold_MASK
124945. DPM_TABLE_238__LinkLevel_6_DownThreshold__SHIFT
124946. DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK
124947. DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT
124948. DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK
124949. DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT
124950. DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl_MASK
124951. DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl__SHIFT
124952. DPM_TABLE_239__LinkLevel_6_UpThreshold_MASK
124953. DPM_TABLE_239__LinkLevel_6_UpThreshold__SHIFT
124954. DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK
124955. DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT
124956. DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK
124957. DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT
124958. DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1_MASK
124959. DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1__SHIFT
124960. DPM_TABLE_23__GraphicsLevel_0_SclkFrequency_MASK
124961. DPM_TABLE_23__GraphicsLevel_0_SclkFrequency__SHIFT
124962. DPM_TABLE_23__LinkPIDController_LfPrecision_MASK
124963. DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT
124964. DPM_TABLE_240__LinkLevel_6_Reserved_MASK
124965. DPM_TABLE_240__LinkLevel_6_Reserved__SHIFT
124966. DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK
124967. DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT
124968. DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2_MASK
124969. DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2__SHIFT
124970. DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK
124971. DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT
124972. DPM_TABLE_241__LinkLevel_7_EnabledForActivity_MASK
124973. DPM_TABLE_241__LinkLevel_7_EnabledForActivity__SHIFT
124974. DPM_TABLE_241__LinkLevel_7_PcieGenSpeed_MASK
124975. DPM_TABLE_241__LinkLevel_7_PcieGenSpeed__SHIFT
124976. DPM_TABLE_241__LinkLevel_7_PcieLaneCount_MASK
124977. DPM_TABLE_241__LinkLevel_7_PcieLaneCount__SHIFT
124978. DPM_TABLE_241__LinkLevel_7_SPC_MASK
124979. DPM_TABLE_241__LinkLevel_7_SPC__SHIFT
124980. DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK
124981. DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT
124982. DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl_MASK
124983. DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl__SHIFT
124984. DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK
124985. DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT
124986. DPM_TABLE_242__LinkLevel_7_DownThreshold_MASK
124987. DPM_TABLE_242__LinkLevel_7_DownThreshold__SHIFT
124988. DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK
124989. DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT
124990. DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl_MASK
124991. DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl__SHIFT
124992. DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK
124993. DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT
124994. DPM_TABLE_243__LinkLevel_7_UpThreshold_MASK
124995. DPM_TABLE_243__LinkLevel_7_UpThreshold__SHIFT
124996. DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl_MASK
124997. DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl__SHIFT
124998. DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK
124999. DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT
125000. DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK
125001. DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT
125002. DPM_TABLE_244__LinkLevel_7_Reserved_MASK
125003. DPM_TABLE_244__LinkLevel_7_Reserved__SHIFT
125004. DPM_TABLE_244__MemoryLevel_2_DllCntl_MASK
125005. DPM_TABLE_244__MemoryLevel_2_DllCntl__SHIFT
125006. DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK
125007. DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT
125008. DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK
125009. DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT
125010. DPM_TABLE_245__ACPILevel_Flags_MASK
125011. DPM_TABLE_245__ACPILevel_Flags__SHIFT
125012. DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK
125013. DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT
125014. DPM_TABLE_245__MemoryLevel_2_MpllSs1_MASK
125015. DPM_TABLE_245__MemoryLevel_2_MpllSs1__SHIFT
125016. DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK
125017. DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT
125018. DPM_TABLE_246__ACPILevel_MinVoltage_Phases_MASK
125019. DPM_TABLE_246__ACPILevel_MinVoltage_Phases__SHIFT
125020. DPM_TABLE_246__ACPILevel_MinVoltage_VddGfx_MASK
125021. DPM_TABLE_246__ACPILevel_MinVoltage_VddGfx__SHIFT
125022. DPM_TABLE_246__ACPILevel_MinVoltage_Vddc_MASK
125023. DPM_TABLE_246__ACPILevel_MinVoltage_Vddc__SHIFT
125024. DPM_TABLE_246__ACPILevel_MinVoltage_Vddci_MASK
125025. DPM_TABLE_246__ACPILevel_MinVoltage_Vddci__SHIFT
125026. DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK
125027. DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT
125028. DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK
125029. DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT
125030. DPM_TABLE_246__MemoryLevel_2_MpllSs2_MASK
125031. DPM_TABLE_246__MemoryLevel_2_MpllSs2__SHIFT
125032. DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK
125033. DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT
125034. DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK
125035. DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT
125036. DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK
125037. DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT
125038. DPM_TABLE_247__ACPILevel_SclkFrequency_MASK
125039. DPM_TABLE_247__ACPILevel_SclkFrequency__SHIFT
125040. DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK
125041. DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT
125042. DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK
125043. DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT
125044. DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK
125045. DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT
125046. DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK
125047. DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT
125048. DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK
125049. DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT
125050. DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK
125051. DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT
125052. DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases_MASK
125053. DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases__SHIFT
125054. DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx_MASK
125055. DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx__SHIFT
125056. DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc_MASK
125057. DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc__SHIFT
125058. DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci_MASK
125059. DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci__SHIFT
125060. DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK
125061. DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT
125062. DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK
125063. DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT
125064. DPM_TABLE_248__ACPILevel_DeepSleepDivId_MASK
125065. DPM_TABLE_248__ACPILevel_DeepSleepDivId__SHIFT
125066. DPM_TABLE_248__ACPILevel_DisplayWatermark_MASK
125067. DPM_TABLE_248__ACPILevel_DisplayWatermark__SHIFT
125068. DPM_TABLE_248__ACPILevel_SclkDid_MASK
125069. DPM_TABLE_248__ACPILevel_SclkDid__SHIFT
125070. DPM_TABLE_248__ACPILevel_padding_MASK
125071. DPM_TABLE_248__ACPILevel_padding__SHIFT
125072. DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK
125073. DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT
125074. DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK
125075. DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT
125076. DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK
125077. DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT
125078. DPM_TABLE_248__MemoryLevel_2_padding_MASK
125079. DPM_TABLE_248__MemoryLevel_2_padding__SHIFT
125080. DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK
125081. DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT
125082. DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK
125083. DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT
125084. DPM_TABLE_248__MemoryLevel_3_MinMvdd_MASK
125085. DPM_TABLE_248__MemoryLevel_3_MinMvdd__SHIFT
125086. DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK
125087. DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT
125088. DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK
125089. DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT
125090. DPM_TABLE_249__ACPILevel_CgSpllFuncCntl_MASK
125091. DPM_TABLE_249__ACPILevel_CgSpllFuncCntl__SHIFT
125092. DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK
125093. DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT
125094. DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK
125095. DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT
125096. DPM_TABLE_249__MemoryLevel_2_padding1_0_MASK
125097. DPM_TABLE_249__MemoryLevel_2_padding1_0__SHIFT
125098. DPM_TABLE_249__MemoryLevel_2_padding1_1_MASK
125099. DPM_TABLE_249__MemoryLevel_2_padding1_1__SHIFT
125100. DPM_TABLE_249__MemoryLevel_2_padding1_MASK
125101. DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT
125102. DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK
125103. DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT
125104. DPM_TABLE_249__MemoryLevel_3_MclkFrequency_MASK
125105. DPM_TABLE_249__MemoryLevel_3_MclkFrequency__SHIFT
125106. DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK
125107. DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT
125108. DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK
125109. DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT
125110. DPM_TABLE_249__MemoryLevel_3_padding_MASK
125111. DPM_TABLE_249__MemoryLevel_3_padding__SHIFT
125112. DPM_TABLE_24__GraphicsLevel_0_ActivityLevel_MASK
125113. DPM_TABLE_24__GraphicsLevel_0_ActivityLevel__SHIFT
125114. DPM_TABLE_24__GraphicsLevel_0_VidOffset_MASK
125115. DPM_TABLE_24__GraphicsLevel_0_VidOffset__SHIFT
125116. DPM_TABLE_24__GraphicsLevel_0_Vid_MASK
125117. DPM_TABLE_24__GraphicsLevel_0_Vid__SHIFT
125118. DPM_TABLE_24__LinkPIDController_LfOffset_MASK
125119. DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT
125120. DPM_TABLE_250__ACPILevel_CgSpllFuncCntl2_MASK
125121. DPM_TABLE_250__ACPILevel_CgSpllFuncCntl2__SHIFT
125122. DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK
125123. DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT
125124. DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK
125125. DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT
125126. DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK
125127. DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT
125128. DPM_TABLE_250__MemoryLevel_3_EdcReadEnable_MASK
125129. DPM_TABLE_250__MemoryLevel_3_EdcReadEnable__SHIFT
125130. DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable_MASK
125131. DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable__SHIFT
125132. DPM_TABLE_250__MemoryLevel_3_RttEnable_MASK
125133. DPM_TABLE_250__MemoryLevel_3_RttEnable__SHIFT
125134. DPM_TABLE_250__MemoryLevel_3_StutterEnable_MASK
125135. DPM_TABLE_250__MemoryLevel_3_StutterEnable__SHIFT
125136. DPM_TABLE_250__MemoryLevel_3_padding1_MASK
125137. DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT
125138. DPM_TABLE_251__ACPILevel_CgSpllFuncCntl3_MASK
125139. DPM_TABLE_251__ACPILevel_CgSpllFuncCntl3__SHIFT
125140. DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK
125141. DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT
125142. DPM_TABLE_251__MemoryLevel_3_EnabledForActivity_MASK
125143. DPM_TABLE_251__MemoryLevel_3_EnabledForActivity__SHIFT
125144. DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle_MASK
125145. DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle__SHIFT
125146. DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK
125147. DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT
125148. DPM_TABLE_251__MemoryLevel_3_StrobeEnable_MASK
125149. DPM_TABLE_251__MemoryLevel_3_StrobeEnable__SHIFT
125150. DPM_TABLE_251__MemoryLevel_3_StrobeRatio_MASK
125151. DPM_TABLE_251__MemoryLevel_3_StrobeRatio__SHIFT
125152. DPM_TABLE_252__ACPILevel_CgSpllFuncCntl4_MASK
125153. DPM_TABLE_252__ACPILevel_CgSpllFuncCntl4__SHIFT
125154. DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK
125155. DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT
125156. DPM_TABLE_252__MemoryLevel_3_DownHyst_MASK
125157. DPM_TABLE_252__MemoryLevel_3_DownHyst__SHIFT
125158. DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK
125159. DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT
125160. DPM_TABLE_252__MemoryLevel_3_UpHyst_MASK
125161. DPM_TABLE_252__MemoryLevel_3_UpHyst__SHIFT
125162. DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst_MASK
125163. DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst__SHIFT
125164. DPM_TABLE_252__MemoryLevel_3_padding_MASK
125165. DPM_TABLE_252__MemoryLevel_3_padding__SHIFT
125166. DPM_TABLE_253__ACPILevel_SpllSpreadSpectrum_MASK
125167. DPM_TABLE_253__ACPILevel_SpllSpreadSpectrum__SHIFT
125168. DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK
125169. DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT
125170. DPM_TABLE_253__MemoryLevel_3_ActivityLevel_MASK
125171. DPM_TABLE_253__MemoryLevel_3_ActivityLevel__SHIFT
125172. DPM_TABLE_253__MemoryLevel_3_DisplayWatermark_MASK
125173. DPM_TABLE_253__MemoryLevel_3_DisplayWatermark__SHIFT
125174. DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK
125175. DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT
125176. DPM_TABLE_253__MemoryLevel_3_padding1_MASK
125177. DPM_TABLE_253__MemoryLevel_3_padding1__SHIFT
125178. DPM_TABLE_254__ACPILevel_SpllSpreadSpectrum2_MASK
125179. DPM_TABLE_254__ACPILevel_SpllSpreadSpectrum2__SHIFT
125180. DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK
125181. DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT
125182. DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK
125183. DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT
125184. DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl_MASK
125185. DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl__SHIFT
125186. DPM_TABLE_255__ACPILevel_CcPwrDynRm_MASK
125187. DPM_TABLE_255__ACPILevel_CcPwrDynRm__SHIFT
125188. DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK
125189. DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT
125190. DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK
125191. DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT
125192. DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1_MASK
125193. DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1__SHIFT
125194. DPM_TABLE_256__ACPILevel_CcPwrDynRm1_MASK
125195. DPM_TABLE_256__ACPILevel_CcPwrDynRm1__SHIFT
125196. DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK
125197. DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT
125198. DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK
125199. DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT
125200. DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2_MASK
125201. DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2__SHIFT
125202. DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK
125203. DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT
125204. DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK
125205. DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT
125206. DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl_MASK
125207. DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl__SHIFT
125208. DPM_TABLE_257__UvdLevel_0_VclkFrequency_MASK
125209. DPM_TABLE_257__UvdLevel_0_VclkFrequency__SHIFT
125210. DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK
125211. DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT
125212. DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl_MASK
125213. DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl__SHIFT
125214. DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK
125215. DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT
125216. DPM_TABLE_258__UvdLevel_0_DclkFrequency_MASK
125217. DPM_TABLE_258__UvdLevel_0_DclkFrequency__SHIFT
125218. DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl_MASK
125219. DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl__SHIFT
125220. DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK
125221. DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT
125222. DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK
125223. DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT
125224. DPM_TABLE_259__UvdLevel_0_MinVoltage_Phases_MASK
125225. DPM_TABLE_259__UvdLevel_0_MinVoltage_Phases__SHIFT
125226. DPM_TABLE_259__UvdLevel_0_MinVoltage_VddGfx_MASK
125227. DPM_TABLE_259__UvdLevel_0_MinVoltage_VddGfx__SHIFT
125228. DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddc_MASK
125229. DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddc__SHIFT
125230. DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddci_MASK
125231. DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddci__SHIFT
125232. DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1_MASK
125233. DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1__SHIFT
125234. DPM_TABLE_25__GraphicsLevel_0_GnbSlow_MASK
125235. DPM_TABLE_25__GraphicsLevel_0_GnbSlow__SHIFT
125236. DPM_TABLE_25__GraphicsLevel_0_PowerThrottle_MASK
125237. DPM_TABLE_25__GraphicsLevel_0_PowerThrottle__SHIFT
125238. DPM_TABLE_25__GraphicsLevel_0_SclkDid_MASK
125239. DPM_TABLE_25__GraphicsLevel_0_SclkDid__SHIFT
125240. DPM_TABLE_25__LinkPIDController_MaxState_MASK
125241. DPM_TABLE_25__LinkPIDController_MaxState__SHIFT
125242. DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK
125243. DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT
125244. DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK
125245. DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT
125246. DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK
125247. DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT
125248. DPM_TABLE_260__LinkLevel_0_SPC_MASK
125249. DPM_TABLE_260__LinkLevel_0_SPC__SHIFT
125250. DPM_TABLE_260__MemoryLevel_3_DllCntl_MASK
125251. DPM_TABLE_260__MemoryLevel_3_DllCntl__SHIFT
125252. DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK
125253. DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT
125254. DPM_TABLE_260__UvdLevel_0_DclkDivider_MASK
125255. DPM_TABLE_260__UvdLevel_0_DclkDivider__SHIFT
125256. DPM_TABLE_260__UvdLevel_0_VclkDivider_MASK
125257. DPM_TABLE_260__UvdLevel_0_VclkDivider__SHIFT
125258. DPM_TABLE_260__UvdLevel_0_padding_0_MASK
125259. DPM_TABLE_260__UvdLevel_0_padding_0__SHIFT
125260. DPM_TABLE_260__UvdLevel_0_padding_1_MASK
125261. DPM_TABLE_260__UvdLevel_0_padding_1__SHIFT
125262. DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK
125263. DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT
125264. DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK
125265. DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT
125266. DPM_TABLE_261__MemoryLevel_3_MpllSs1_MASK
125267. DPM_TABLE_261__MemoryLevel_3_MpllSs1__SHIFT
125268. DPM_TABLE_261__UvdLevel_1_VclkFrequency_MASK
125269. DPM_TABLE_261__UvdLevel_1_VclkFrequency__SHIFT
125270. DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK
125271. DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT
125272. DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK
125273. DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT
125274. DPM_TABLE_262__MemoryLevel_3_MpllSs2_MASK
125275. DPM_TABLE_262__MemoryLevel_3_MpllSs2__SHIFT
125276. DPM_TABLE_262__UvdLevel_1_DclkFrequency_MASK
125277. DPM_TABLE_262__UvdLevel_1_DclkFrequency__SHIFT
125278. DPM_TABLE_263__LinkLevel_0_EnabledForActivity_MASK
125279. DPM_TABLE_263__LinkLevel_0_EnabledForActivity__SHIFT
125280. DPM_TABLE_263__LinkLevel_0_PcieGenSpeed_MASK
125281. DPM_TABLE_263__LinkLevel_0_PcieGenSpeed__SHIFT
125282. DPM_TABLE_263__LinkLevel_0_PcieLaneCount_MASK
125283. DPM_TABLE_263__LinkLevel_0_PcieLaneCount__SHIFT
125284. DPM_TABLE_263__LinkLevel_0_Reserved_MASK
125285. DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT
125286. DPM_TABLE_263__LinkLevel_0_SPC_MASK
125287. DPM_TABLE_263__LinkLevel_0_SPC__SHIFT
125288. DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK
125289. DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT
125290. DPM_TABLE_263__UvdLevel_1_MinVoltage_Phases_MASK
125291. DPM_TABLE_263__UvdLevel_1_MinVoltage_Phases__SHIFT
125292. DPM_TABLE_263__UvdLevel_1_MinVoltage_VddGfx_MASK
125293. DPM_TABLE_263__UvdLevel_1_MinVoltage_VddGfx__SHIFT
125294. DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddc_MASK
125295. DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddc__SHIFT
125296. DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddci_MASK
125297. DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddci__SHIFT
125298. DPM_TABLE_264__LinkLevel_0_DownThreshold_MASK
125299. DPM_TABLE_264__LinkLevel_0_DownThreshold__SHIFT
125300. DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK
125301. DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT
125302. DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK
125303. DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT
125304. DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK
125305. DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT
125306. DPM_TABLE_264__LinkLevel_1_SPC_MASK
125307. DPM_TABLE_264__LinkLevel_1_SPC__SHIFT
125308. DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK
125309. DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT
125310. DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK
125311. DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT
125312. DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK
125313. DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT
125314. DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK
125315. DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT
125316. DPM_TABLE_264__UvdLevel_1_DclkDivider_MASK
125317. DPM_TABLE_264__UvdLevel_1_DclkDivider__SHIFT
125318. DPM_TABLE_264__UvdLevel_1_VclkDivider_MASK
125319. DPM_TABLE_264__UvdLevel_1_VclkDivider__SHIFT
125320. DPM_TABLE_264__UvdLevel_1_padding_0_MASK
125321. DPM_TABLE_264__UvdLevel_1_padding_0__SHIFT
125322. DPM_TABLE_264__UvdLevel_1_padding_1_MASK
125323. DPM_TABLE_264__UvdLevel_1_padding_1__SHIFT
125324. DPM_TABLE_265__LinkLevel_0_UpThreshold_MASK
125325. DPM_TABLE_265__LinkLevel_0_UpThreshold__SHIFT
125326. DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK
125327. DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT
125328. DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK
125329. DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT
125330. DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK
125331. DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT
125332. DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK
125333. DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT
125334. DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK
125335. DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT
125336. DPM_TABLE_265__UvdLevel_2_VclkFrequency_MASK
125337. DPM_TABLE_265__UvdLevel_2_VclkFrequency__SHIFT
125338. DPM_TABLE_266__LinkLevel_0_Reserved_MASK
125339. DPM_TABLE_266__LinkLevel_0_Reserved__SHIFT
125340. DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK
125341. DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT
125342. DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK
125343. DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT
125344. DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK
125345. DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT
125346. DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK
125347. DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT
125348. DPM_TABLE_266__MemoryLevel_3_padding_MASK
125349. DPM_TABLE_266__MemoryLevel_3_padding__SHIFT
125350. DPM_TABLE_266__UvdLevel_2_DclkFrequency_MASK
125351. DPM_TABLE_266__UvdLevel_2_DclkFrequency__SHIFT
125352. DPM_TABLE_267__LinkLevel_1_EnabledForActivity_MASK
125353. DPM_TABLE_267__LinkLevel_1_EnabledForActivity__SHIFT
125354. DPM_TABLE_267__LinkLevel_1_PcieGenSpeed_MASK
125355. DPM_TABLE_267__LinkLevel_1_PcieGenSpeed__SHIFT
125356. DPM_TABLE_267__LinkLevel_1_PcieLaneCount_MASK
125357. DPM_TABLE_267__LinkLevel_1_PcieLaneCount__SHIFT
125358. DPM_TABLE_267__LinkLevel_1_Reserved_MASK
125359. DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT
125360. DPM_TABLE_267__LinkLevel_1_SPC_MASK
125361. DPM_TABLE_267__LinkLevel_1_SPC__SHIFT
125362. DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK
125363. DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT
125364. DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK
125365. DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT
125366. DPM_TABLE_267__MemoryLevel_3_padding1_0_MASK
125367. DPM_TABLE_267__MemoryLevel_3_padding1_0__SHIFT
125368. DPM_TABLE_267__MemoryLevel_3_padding1_1_MASK
125369. DPM_TABLE_267__MemoryLevel_3_padding1_1__SHIFT
125370. DPM_TABLE_267__MemoryLevel_3_padding1_MASK
125371. DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT
125372. DPM_TABLE_267__UvdLevel_2_MinVoltage_Phases_MASK
125373. DPM_TABLE_267__UvdLevel_2_MinVoltage_Phases__SHIFT
125374. DPM_TABLE_267__UvdLevel_2_MinVoltage_VddGfx_MASK
125375. DPM_TABLE_267__UvdLevel_2_MinVoltage_VddGfx__SHIFT
125376. DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddc_MASK
125377. DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddc__SHIFT
125378. DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddci_MASK
125379. DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddci__SHIFT
125380. DPM_TABLE_268__LinkLevel_1_DownThreshold_MASK
125381. DPM_TABLE_268__LinkLevel_1_DownThreshold__SHIFT
125382. DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK
125383. DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT
125384. DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK
125385. DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT
125386. DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK
125387. DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT
125388. DPM_TABLE_268__LinkLevel_2_SPC_MASK
125389. DPM_TABLE_268__LinkLevel_2_SPC__SHIFT
125390. DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK
125391. DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT
125392. DPM_TABLE_268__UvdLevel_2_DclkDivider_MASK
125393. DPM_TABLE_268__UvdLevel_2_DclkDivider__SHIFT
125394. DPM_TABLE_268__UvdLevel_2_VclkDivider_MASK
125395. DPM_TABLE_268__UvdLevel_2_VclkDivider__SHIFT
125396. DPM_TABLE_268__UvdLevel_2_padding_0_MASK
125397. DPM_TABLE_268__UvdLevel_2_padding_0__SHIFT
125398. DPM_TABLE_268__UvdLevel_2_padding_1_MASK
125399. DPM_TABLE_268__UvdLevel_2_padding_1__SHIFT
125400. DPM_TABLE_269__LinkLevel_1_UpThreshold_MASK
125401. DPM_TABLE_269__LinkLevel_1_UpThreshold__SHIFT
125402. DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK
125403. DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT
125404. DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK
125405. DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT
125406. DPM_TABLE_269__UvdLevel_3_VclkFrequency_MASK
125407. DPM_TABLE_269__UvdLevel_3_VclkFrequency__SHIFT
125408. DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark_MASK
125409. DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark__SHIFT
125410. DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity_MASK
125411. DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity__SHIFT
125412. DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle_MASK
125413. DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle__SHIFT
125414. DPM_TABLE_26__GraphicsLevel_0_UpHyst_MASK
125415. DPM_TABLE_26__GraphicsLevel_0_UpHyst__SHIFT
125416. DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK
125417. DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT
125418. DPM_TABLE_270__LinkLevel_1_Reserved_MASK
125419. DPM_TABLE_270__LinkLevel_1_Reserved__SHIFT
125420. DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK
125421. DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT
125422. DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK
125423. DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT
125424. DPM_TABLE_270__UvdLevel_3_DclkFrequency_MASK
125425. DPM_TABLE_270__UvdLevel_3_DclkFrequency__SHIFT
125426. DPM_TABLE_271__LinkLevel_2_EnabledForActivity_MASK
125427. DPM_TABLE_271__LinkLevel_2_EnabledForActivity__SHIFT
125428. DPM_TABLE_271__LinkLevel_2_PcieGenSpeed_MASK
125429. DPM_TABLE_271__LinkLevel_2_PcieGenSpeed__SHIFT
125430. DPM_TABLE_271__LinkLevel_2_PcieLaneCount_MASK
125431. DPM_TABLE_271__LinkLevel_2_PcieLaneCount__SHIFT
125432. DPM_TABLE_271__LinkLevel_2_Reserved_MASK
125433. DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT
125434. DPM_TABLE_271__LinkLevel_2_SPC_MASK
125435. DPM_TABLE_271__LinkLevel_2_SPC__SHIFT
125436. DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK
125437. DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT
125438. DPM_TABLE_271__UvdLevel_3_MinVoltage_Phases_MASK
125439. DPM_TABLE_271__UvdLevel_3_MinVoltage_Phases__SHIFT
125440. DPM_TABLE_271__UvdLevel_3_MinVoltage_VddGfx_MASK
125441. DPM_TABLE_271__UvdLevel_3_MinVoltage_VddGfx__SHIFT
125442. DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddc_MASK
125443. DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddc__SHIFT
125444. DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddci_MASK
125445. DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddci__SHIFT
125446. DPM_TABLE_272__LinkLevel_2_DownThreshold_MASK
125447. DPM_TABLE_272__LinkLevel_2_DownThreshold__SHIFT
125448. DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK
125449. DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT
125450. DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK
125451. DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT
125452. DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK
125453. DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT
125454. DPM_TABLE_272__LinkLevel_3_SPC_MASK
125455. DPM_TABLE_272__LinkLevel_3_SPC__SHIFT
125456. DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK
125457. DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT
125458. DPM_TABLE_272__UvdLevel_3_DclkDivider_MASK
125459. DPM_TABLE_272__UvdLevel_3_DclkDivider__SHIFT
125460. DPM_TABLE_272__UvdLevel_3_VclkDivider_MASK
125461. DPM_TABLE_272__UvdLevel_3_VclkDivider__SHIFT
125462. DPM_TABLE_272__UvdLevel_3_padding_0_MASK
125463. DPM_TABLE_272__UvdLevel_3_padding_0__SHIFT
125464. DPM_TABLE_272__UvdLevel_3_padding_1_MASK
125465. DPM_TABLE_272__UvdLevel_3_padding_1__SHIFT
125466. DPM_TABLE_273__LinkLevel_2_UpThreshold_MASK
125467. DPM_TABLE_273__LinkLevel_2_UpThreshold__SHIFT
125468. DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK
125469. DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT
125470. DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK
125471. DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT
125472. DPM_TABLE_273__UvdLevel_4_VclkFrequency_MASK
125473. DPM_TABLE_273__UvdLevel_4_VclkFrequency__SHIFT
125474. DPM_TABLE_274__LinkLevel_2_Reserved_MASK
125475. DPM_TABLE_274__LinkLevel_2_Reserved__SHIFT
125476. DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK
125477. DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT
125478. DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK
125479. DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT
125480. DPM_TABLE_274__UvdLevel_4_DclkFrequency_MASK
125481. DPM_TABLE_274__UvdLevel_4_DclkFrequency__SHIFT
125482. DPM_TABLE_275__LinkLevel_3_EnabledForActivity_MASK
125483. DPM_TABLE_275__LinkLevel_3_EnabledForActivity__SHIFT
125484. DPM_TABLE_275__LinkLevel_3_PcieGenSpeed_MASK
125485. DPM_TABLE_275__LinkLevel_3_PcieGenSpeed__SHIFT
125486. DPM_TABLE_275__LinkLevel_3_PcieLaneCount_MASK
125487. DPM_TABLE_275__LinkLevel_3_PcieLaneCount__SHIFT
125488. DPM_TABLE_275__LinkLevel_3_Reserved_MASK
125489. DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT
125490. DPM_TABLE_275__LinkLevel_3_SPC_MASK
125491. DPM_TABLE_275__LinkLevel_3_SPC__SHIFT
125492. DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK
125493. DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT
125494. DPM_TABLE_275__UvdLevel_4_MinVoltage_Phases_MASK
125495. DPM_TABLE_275__UvdLevel_4_MinVoltage_Phases__SHIFT
125496. DPM_TABLE_275__UvdLevel_4_MinVoltage_VddGfx_MASK
125497. DPM_TABLE_275__UvdLevel_4_MinVoltage_VddGfx__SHIFT
125498. DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddc_MASK
125499. DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddc__SHIFT
125500. DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddci_MASK
125501. DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddci__SHIFT
125502. DPM_TABLE_276__LinkLevel_3_DownThreshold_MASK
125503. DPM_TABLE_276__LinkLevel_3_DownThreshold__SHIFT
125504. DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK
125505. DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT
125506. DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK
125507. DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT
125508. DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK
125509. DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT
125510. DPM_TABLE_276__LinkLevel_4_SPC_MASK
125511. DPM_TABLE_276__LinkLevel_4_SPC__SHIFT
125512. DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK
125513. DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT
125514. DPM_TABLE_276__UvdLevel_4_DclkDivider_MASK
125515. DPM_TABLE_276__UvdLevel_4_DclkDivider__SHIFT
125516. DPM_TABLE_276__UvdLevel_4_VclkDivider_MASK
125517. DPM_TABLE_276__UvdLevel_4_VclkDivider__SHIFT
125518. DPM_TABLE_276__UvdLevel_4_padding_0_MASK
125519. DPM_TABLE_276__UvdLevel_4_padding_0__SHIFT
125520. DPM_TABLE_276__UvdLevel_4_padding_1_MASK
125521. DPM_TABLE_276__UvdLevel_4_padding_1__SHIFT
125522. DPM_TABLE_277__LinkLevel_3_UpThreshold_MASK
125523. DPM_TABLE_277__LinkLevel_3_UpThreshold__SHIFT
125524. DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK
125525. DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT
125526. DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK
125527. DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT
125528. DPM_TABLE_277__UvdLevel_5_VclkFrequency_MASK
125529. DPM_TABLE_277__UvdLevel_5_VclkFrequency__SHIFT
125530. DPM_TABLE_278__LinkLevel_3_Reserved_MASK
125531. DPM_TABLE_278__LinkLevel_3_Reserved__SHIFT
125532. DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK
125533. DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT
125534. DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK
125535. DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT
125536. DPM_TABLE_278__UvdLevel_5_DclkFrequency_MASK
125537. DPM_TABLE_278__UvdLevel_5_DclkFrequency__SHIFT
125538. DPM_TABLE_279__LinkLevel_4_EnabledForActivity_MASK
125539. DPM_TABLE_279__LinkLevel_4_EnabledForActivity__SHIFT
125540. DPM_TABLE_279__LinkLevel_4_PcieGenSpeed_MASK
125541. DPM_TABLE_279__LinkLevel_4_PcieGenSpeed__SHIFT
125542. DPM_TABLE_279__LinkLevel_4_PcieLaneCount_MASK
125543. DPM_TABLE_279__LinkLevel_4_PcieLaneCount__SHIFT
125544. DPM_TABLE_279__LinkLevel_4_Reserved_MASK
125545. DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT
125546. DPM_TABLE_279__LinkLevel_4_SPC_MASK
125547. DPM_TABLE_279__LinkLevel_4_SPC__SHIFT
125548. DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK
125549. DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT
125550. DPM_TABLE_279__UvdLevel_5_MinVoltage_Phases_MASK
125551. DPM_TABLE_279__UvdLevel_5_MinVoltage_Phases__SHIFT
125552. DPM_TABLE_279__UvdLevel_5_MinVoltage_VddGfx_MASK
125553. DPM_TABLE_279__UvdLevel_5_MinVoltage_VddGfx__SHIFT
125554. DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddc_MASK
125555. DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddc__SHIFT
125556. DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddci_MASK
125557. DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddci__SHIFT
125558. DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl_MASK
125559. DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl__SHIFT
125560. DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId_MASK
125561. DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId__SHIFT
125562. DPM_TABLE_27__GraphicsLevel_0_DownHyst_MASK
125563. DPM_TABLE_27__GraphicsLevel_0_DownHyst__SHIFT
125564. DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst_MASK
125565. DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst__SHIFT
125566. DPM_TABLE_27__LinkPIDController_StateShift_MASK
125567. DPM_TABLE_27__LinkPIDController_StateShift__SHIFT
125568. DPM_TABLE_280__LinkLevel_4_DownThreshold_MASK
125569. DPM_TABLE_280__LinkLevel_4_DownThreshold__SHIFT
125570. DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK
125571. DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT
125572. DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK
125573. DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT
125574. DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK
125575. DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT
125576. DPM_TABLE_280__LinkLevel_5_SPC_MASK
125577. DPM_TABLE_280__LinkLevel_5_SPC__SHIFT
125578. DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK
125579. DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT
125580. DPM_TABLE_280__UvdLevel_5_DclkDivider_MASK
125581. DPM_TABLE_280__UvdLevel_5_DclkDivider__SHIFT
125582. DPM_TABLE_280__UvdLevel_5_VclkDivider_MASK
125583. DPM_TABLE_280__UvdLevel_5_VclkDivider__SHIFT
125584. DPM_TABLE_280__UvdLevel_5_padding_0_MASK
125585. DPM_TABLE_280__UvdLevel_5_padding_0__SHIFT
125586. DPM_TABLE_280__UvdLevel_5_padding_1_MASK
125587. DPM_TABLE_280__UvdLevel_5_padding_1__SHIFT
125588. DPM_TABLE_281__LinkLevel_4_UpThreshold_MASK
125589. DPM_TABLE_281__LinkLevel_4_UpThreshold__SHIFT
125590. DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK
125591. DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT
125592. DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK
125593. DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT
125594. DPM_TABLE_281__UvdLevel_6_VclkFrequency_MASK
125595. DPM_TABLE_281__UvdLevel_6_VclkFrequency__SHIFT
125596. DPM_TABLE_282__LinkLevel_4_Reserved_MASK
125597. DPM_TABLE_282__LinkLevel_4_Reserved__SHIFT
125598. DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK
125599. DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT
125600. DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK
125601. DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT
125602. DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK
125603. DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT
125604. DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK
125605. DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT
125606. DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK
125607. DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT
125608. DPM_TABLE_282__UvdLevel_6_DclkFrequency_MASK
125609. DPM_TABLE_282__UvdLevel_6_DclkFrequency__SHIFT
125610. DPM_TABLE_283__LinkLevel_5_EnabledForActivity_MASK
125611. DPM_TABLE_283__LinkLevel_5_EnabledForActivity__SHIFT
125612. DPM_TABLE_283__LinkLevel_5_PcieGenSpeed_MASK
125613. DPM_TABLE_283__LinkLevel_5_PcieGenSpeed__SHIFT
125614. DPM_TABLE_283__LinkLevel_5_PcieLaneCount_MASK
125615. DPM_TABLE_283__LinkLevel_5_PcieLaneCount__SHIFT
125616. DPM_TABLE_283__LinkLevel_5_Reserved_MASK
125617. DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT
125618. DPM_TABLE_283__LinkLevel_5_SPC_MASK
125619. DPM_TABLE_283__LinkLevel_5_SPC__SHIFT
125620. DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK
125621. DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT
125622. DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK
125623. DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT
125624. DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK
125625. DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT
125626. DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK
125627. DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT
125628. DPM_TABLE_283__UvdLevel_6_MinVoltage_Phases_MASK
125629. DPM_TABLE_283__UvdLevel_6_MinVoltage_Phases__SHIFT
125630. DPM_TABLE_283__UvdLevel_6_MinVoltage_VddGfx_MASK
125631. DPM_TABLE_283__UvdLevel_6_MinVoltage_VddGfx__SHIFT
125632. DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddc_MASK
125633. DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddc__SHIFT
125634. DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddci_MASK
125635. DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddci__SHIFT
125636. DPM_TABLE_284__LinkLevel_5_DownThreshold_MASK
125637. DPM_TABLE_284__LinkLevel_5_DownThreshold__SHIFT
125638. DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK
125639. DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT
125640. DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK
125641. DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT
125642. DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK
125643. DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT
125644. DPM_TABLE_284__LinkLevel_6_SPC_MASK
125645. DPM_TABLE_284__LinkLevel_6_SPC__SHIFT
125646. DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK
125647. DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT
125648. DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK
125649. DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT
125650. DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK
125651. DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT
125652. DPM_TABLE_284__MemoryLevel_4_padding_MASK
125653. DPM_TABLE_284__MemoryLevel_4_padding__SHIFT
125654. DPM_TABLE_284__UvdLevel_6_DclkDivider_MASK
125655. DPM_TABLE_284__UvdLevel_6_DclkDivider__SHIFT
125656. DPM_TABLE_284__UvdLevel_6_VclkDivider_MASK
125657. DPM_TABLE_284__UvdLevel_6_VclkDivider__SHIFT
125658. DPM_TABLE_284__UvdLevel_6_padding_0_MASK
125659. DPM_TABLE_284__UvdLevel_6_padding_0__SHIFT
125660. DPM_TABLE_284__UvdLevel_6_padding_1_MASK
125661. DPM_TABLE_284__UvdLevel_6_padding_1__SHIFT
125662. DPM_TABLE_285__LinkLevel_5_UpThreshold_MASK
125663. DPM_TABLE_285__LinkLevel_5_UpThreshold__SHIFT
125664. DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK
125665. DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT
125666. DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK
125667. DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT
125668. DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK
125669. DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT
125670. DPM_TABLE_285__MemoryLevel_4_padding1_0_MASK
125671. DPM_TABLE_285__MemoryLevel_4_padding1_0__SHIFT
125672. DPM_TABLE_285__MemoryLevel_4_padding1_1_MASK
125673. DPM_TABLE_285__MemoryLevel_4_padding1_1__SHIFT
125674. DPM_TABLE_285__MemoryLevel_4_padding1_MASK
125675. DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT
125676. DPM_TABLE_285__UvdLevel_7_VclkFrequency_MASK
125677. DPM_TABLE_285__UvdLevel_7_VclkFrequency__SHIFT
125678. DPM_TABLE_286__LinkLevel_5_Reserved_MASK
125679. DPM_TABLE_286__LinkLevel_5_Reserved__SHIFT
125680. DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK
125681. DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT
125682. DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK
125683. DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT
125684. DPM_TABLE_286__UvdLevel_7_DclkFrequency_MASK
125685. DPM_TABLE_286__UvdLevel_7_DclkFrequency__SHIFT
125686. DPM_TABLE_287__LinkLevel_6_EnabledForActivity_MASK
125687. DPM_TABLE_287__LinkLevel_6_EnabledForActivity__SHIFT
125688. DPM_TABLE_287__LinkLevel_6_PcieGenSpeed_MASK
125689. DPM_TABLE_287__LinkLevel_6_PcieGenSpeed__SHIFT
125690. DPM_TABLE_287__LinkLevel_6_PcieLaneCount_MASK
125691. DPM_TABLE_287__LinkLevel_6_PcieLaneCount__SHIFT
125692. DPM_TABLE_287__LinkLevel_6_Reserved_MASK
125693. DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT
125694. DPM_TABLE_287__LinkLevel_6_SPC_MASK
125695. DPM_TABLE_287__LinkLevel_6_SPC__SHIFT
125696. DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK
125697. DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT
125698. DPM_TABLE_287__UvdLevel_7_MinVoltage_Phases_MASK
125699. DPM_TABLE_287__UvdLevel_7_MinVoltage_Phases__SHIFT
125700. DPM_TABLE_287__UvdLevel_7_MinVoltage_VddGfx_MASK
125701. DPM_TABLE_287__UvdLevel_7_MinVoltage_VddGfx__SHIFT
125702. DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddc_MASK
125703. DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddc__SHIFT
125704. DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddci_MASK
125705. DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddci__SHIFT
125706. DPM_TABLE_288__LinkLevel_6_DownThreshold_MASK
125707. DPM_TABLE_288__LinkLevel_6_DownThreshold__SHIFT
125708. DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK
125709. DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT
125710. DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK
125711. DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT
125712. DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK
125713. DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT
125714. DPM_TABLE_288__LinkLevel_7_SPC_MASK
125715. DPM_TABLE_288__LinkLevel_7_SPC__SHIFT
125716. DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK
125717. DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT
125718. DPM_TABLE_288__UvdLevel_7_DclkDivider_MASK
125719. DPM_TABLE_288__UvdLevel_7_DclkDivider__SHIFT
125720. DPM_TABLE_288__UvdLevel_7_VclkDivider_MASK
125721. DPM_TABLE_288__UvdLevel_7_VclkDivider__SHIFT
125722. DPM_TABLE_288__UvdLevel_7_padding_0_MASK
125723. DPM_TABLE_288__UvdLevel_7_padding_0__SHIFT
125724. DPM_TABLE_288__UvdLevel_7_padding_1_MASK
125725. DPM_TABLE_288__UvdLevel_7_padding_1__SHIFT
125726. DPM_TABLE_289__LinkLevel_6_UpThreshold_MASK
125727. DPM_TABLE_289__LinkLevel_6_UpThreshold__SHIFT
125728. DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK
125729. DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT
125730. DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK
125731. DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT
125732. DPM_TABLE_289__VceLevel_0_Frequency_MASK
125733. DPM_TABLE_289__VceLevel_0_Frequency__SHIFT
125734. DPM_TABLE_28__GraphicsLevel_0_reserved_MASK
125735. DPM_TABLE_28__GraphicsLevel_0_reserved__SHIFT
125736. DPM_TABLE_28__SystemFlags_MASK
125737. DPM_TABLE_28__SystemFlags__SHIFT
125738. DPM_TABLE_290__LinkLevel_6_Reserved_MASK
125739. DPM_TABLE_290__LinkLevel_6_Reserved__SHIFT
125740. DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK
125741. DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT
125742. DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK
125743. DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT
125744. DPM_TABLE_290__VceLevel_0_MinVoltage_Phases_MASK
125745. DPM_TABLE_290__VceLevel_0_MinVoltage_Phases__SHIFT
125746. DPM_TABLE_290__VceLevel_0_MinVoltage_VddGfx_MASK
125747. DPM_TABLE_290__VceLevel_0_MinVoltage_VddGfx__SHIFT
125748. DPM_TABLE_290__VceLevel_0_MinVoltage_Vddc_MASK
125749. DPM_TABLE_290__VceLevel_0_MinVoltage_Vddc__SHIFT
125750. DPM_TABLE_290__VceLevel_0_MinVoltage_Vddci_MASK
125751. DPM_TABLE_290__VceLevel_0_MinVoltage_Vddci__SHIFT
125752. DPM_TABLE_291__LinkLevel_7_EnabledForActivity_MASK
125753. DPM_TABLE_291__LinkLevel_7_EnabledForActivity__SHIFT
125754. DPM_TABLE_291__LinkLevel_7_PcieGenSpeed_MASK
125755. DPM_TABLE_291__LinkLevel_7_PcieGenSpeed__SHIFT
125756. DPM_TABLE_291__LinkLevel_7_PcieLaneCount_MASK
125757. DPM_TABLE_291__LinkLevel_7_PcieLaneCount__SHIFT
125758. DPM_TABLE_291__LinkLevel_7_Reserved_MASK
125759. DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT
125760. DPM_TABLE_291__LinkLevel_7_SPC_MASK
125761. DPM_TABLE_291__LinkLevel_7_SPC__SHIFT
125762. DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK
125763. DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT
125764. DPM_TABLE_291__VceLevel_0_Divider_MASK
125765. DPM_TABLE_291__VceLevel_0_Divider__SHIFT
125766. DPM_TABLE_291__VceLevel_0_padding_0_MASK
125767. DPM_TABLE_291__VceLevel_0_padding_0__SHIFT
125768. DPM_TABLE_291__VceLevel_0_padding_1_MASK
125769. DPM_TABLE_291__VceLevel_0_padding_1__SHIFT
125770. DPM_TABLE_291__VceLevel_0_padding_2_MASK
125771. DPM_TABLE_291__VceLevel_0_padding_2__SHIFT
125772. DPM_TABLE_292__ACPILevel_Flags_MASK
125773. DPM_TABLE_292__ACPILevel_Flags__SHIFT
125774. DPM_TABLE_292__LinkLevel_7_DownThreshold_MASK
125775. DPM_TABLE_292__LinkLevel_7_DownThreshold__SHIFT
125776. DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK
125777. DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT
125778. DPM_TABLE_292__VceLevel_1_Frequency_MASK
125779. DPM_TABLE_292__VceLevel_1_Frequency__SHIFT
125780. DPM_TABLE_293__ACPILevel_MinVddc_MASK
125781. DPM_TABLE_293__ACPILevel_MinVddc__SHIFT
125782. DPM_TABLE_293__LinkLevel_7_UpThreshold_MASK
125783. DPM_TABLE_293__LinkLevel_7_UpThreshold__SHIFT
125784. DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK
125785. DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT
125786. DPM_TABLE_293__VceLevel_1_MinVoltage_Phases_MASK
125787. DPM_TABLE_293__VceLevel_1_MinVoltage_Phases__SHIFT
125788. DPM_TABLE_293__VceLevel_1_MinVoltage_VddGfx_MASK
125789. DPM_TABLE_293__VceLevel_1_MinVoltage_VddGfx__SHIFT
125790. DPM_TABLE_293__VceLevel_1_MinVoltage_Vddc_MASK
125791. DPM_TABLE_293__VceLevel_1_MinVoltage_Vddc__SHIFT
125792. DPM_TABLE_293__VceLevel_1_MinVoltage_Vddci_MASK
125793. DPM_TABLE_293__VceLevel_1_MinVoltage_Vddci__SHIFT
125794. DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK
125795. DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT
125796. DPM_TABLE_294__LinkLevel_7_Reserved_MASK
125797. DPM_TABLE_294__LinkLevel_7_Reserved__SHIFT
125798. DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK
125799. DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT
125800. DPM_TABLE_294__VceLevel_1_Divider_MASK
125801. DPM_TABLE_294__VceLevel_1_Divider__SHIFT
125802. DPM_TABLE_294__VceLevel_1_padding_0_MASK
125803. DPM_TABLE_294__VceLevel_1_padding_0__SHIFT
125804. DPM_TABLE_294__VceLevel_1_padding_1_MASK
125805. DPM_TABLE_294__VceLevel_1_padding_1__SHIFT
125806. DPM_TABLE_294__VceLevel_1_padding_2_MASK
125807. DPM_TABLE_294__VceLevel_1_padding_2__SHIFT
125808. DPM_TABLE_295__ACPILevel_Flags_MASK
125809. DPM_TABLE_295__ACPILevel_Flags__SHIFT
125810. DPM_TABLE_295__ACPILevel_SclkFrequency_MASK
125811. DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT
125812. DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK
125813. DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT
125814. DPM_TABLE_295__VceLevel_2_Frequency_MASK
125815. DPM_TABLE_295__VceLevel_2_Frequency__SHIFT
125816. DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK
125817. DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT
125818. DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK
125819. DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT
125820. DPM_TABLE_296__ACPILevel_MinVoltage_Phases_MASK
125821. DPM_TABLE_296__ACPILevel_MinVoltage_Phases__SHIFT
125822. DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx_MASK
125823. DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx__SHIFT
125824. DPM_TABLE_296__ACPILevel_MinVoltage_Vddc_MASK
125825. DPM_TABLE_296__ACPILevel_MinVoltage_Vddc__SHIFT
125826. DPM_TABLE_296__ACPILevel_MinVoltage_Vddci_MASK
125827. DPM_TABLE_296__ACPILevel_MinVoltage_Vddci__SHIFT
125828. DPM_TABLE_296__ACPILevel_SclkDid_MASK
125829. DPM_TABLE_296__ACPILevel_SclkDid__SHIFT
125830. DPM_TABLE_296__ACPILevel_padding_MASK
125831. DPM_TABLE_296__ACPILevel_padding__SHIFT
125832. DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK
125833. DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT
125834. DPM_TABLE_296__VceLevel_2_MinVoltage_Phases_MASK
125835. DPM_TABLE_296__VceLevel_2_MinVoltage_Phases__SHIFT
125836. DPM_TABLE_296__VceLevel_2_MinVoltage_VddGfx_MASK
125837. DPM_TABLE_296__VceLevel_2_MinVoltage_VddGfx__SHIFT
125838. DPM_TABLE_296__VceLevel_2_MinVoltage_Vddc_MASK
125839. DPM_TABLE_296__VceLevel_2_MinVoltage_Vddc__SHIFT
125840. DPM_TABLE_296__VceLevel_2_MinVoltage_Vddci_MASK
125841. DPM_TABLE_296__VceLevel_2_MinVoltage_Vddci__SHIFT
125842. DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK
125843. DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT
125844. DPM_TABLE_297__ACPILevel_SclkFrequency_MASK
125845. DPM_TABLE_297__ACPILevel_SclkFrequency__SHIFT
125846. DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK
125847. DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT
125848. DPM_TABLE_297__VceLevel_2_Divider_MASK
125849. DPM_TABLE_297__VceLevel_2_Divider__SHIFT
125850. DPM_TABLE_297__VceLevel_2_padding_0_MASK
125851. DPM_TABLE_297__VceLevel_2_padding_0__SHIFT
125852. DPM_TABLE_297__VceLevel_2_padding_1_MASK
125853. DPM_TABLE_297__VceLevel_2_padding_1__SHIFT
125854. DPM_TABLE_297__VceLevel_2_padding_2_MASK
125855. DPM_TABLE_297__VceLevel_2_padding_2__SHIFT
125856. DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK
125857. DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT
125858. DPM_TABLE_298__ACPILevel_DeepSleepDivId_MASK
125859. DPM_TABLE_298__ACPILevel_DeepSleepDivId__SHIFT
125860. DPM_TABLE_298__ACPILevel_DisplayWatermark_MASK
125861. DPM_TABLE_298__ACPILevel_DisplayWatermark__SHIFT
125862. DPM_TABLE_298__ACPILevel_SclkDid_MASK
125863. DPM_TABLE_298__ACPILevel_SclkDid__SHIFT
125864. DPM_TABLE_298__ACPILevel_padding_MASK
125865. DPM_TABLE_298__ACPILevel_padding__SHIFT
125866. DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK
125867. DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT
125868. DPM_TABLE_298__VceLevel_3_Frequency_MASK
125869. DPM_TABLE_298__VceLevel_3_Frequency__SHIFT
125870. DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK
125871. DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT
125872. DPM_TABLE_299__ACPILevel_CgSpllFuncCntl_MASK
125873. DPM_TABLE_299__ACPILevel_CgSpllFuncCntl__SHIFT
125874. DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK
125875. DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT
125876. DPM_TABLE_299__VceLevel_3_MinVoltage_Phases_MASK
125877. DPM_TABLE_299__VceLevel_3_MinVoltage_Phases__SHIFT
125878. DPM_TABLE_299__VceLevel_3_MinVoltage_VddGfx_MASK
125879. DPM_TABLE_299__VceLevel_3_MinVoltage_VddGfx__SHIFT
125880. DPM_TABLE_299__VceLevel_3_MinVoltage_Vddc_MASK
125881. DPM_TABLE_299__VceLevel_3_MinVoltage_Vddc__SHIFT
125882. DPM_TABLE_299__VceLevel_3_MinVoltage_Vddci_MASK
125883. DPM_TABLE_299__VceLevel_3_MinVoltage_Vddci__SHIFT
125884. DPM_TABLE_29__GraphicsLevel_1_MinVddNb_MASK
125885. DPM_TABLE_29__GraphicsLevel_1_MinVddNb__SHIFT
125886. DPM_TABLE_29__SmioMaskVddcVid_MASK
125887. DPM_TABLE_29__SmioMaskVddcVid__SHIFT
125888. DPM_TABLE_29__VRConfig_MASK
125889. DPM_TABLE_29__VRConfig__SHIFT
125890. DPM_TABLE_2__GraphicsPIDController_Ki_MASK
125891. DPM_TABLE_2__GraphicsPIDController_Ki__SHIFT
125892. DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK
125893. DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT
125894. DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2_MASK
125895. DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2__SHIFT
125896. DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK
125897. DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT
125898. DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK
125899. DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT
125900. DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK
125901. DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT
125902. DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK
125903. DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT
125904. DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK
125905. DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT
125906. DPM_TABLE_300__VceLevel_3_Divider_MASK
125907. DPM_TABLE_300__VceLevel_3_Divider__SHIFT
125908. DPM_TABLE_300__VceLevel_3_padding_0_MASK
125909. DPM_TABLE_300__VceLevel_3_padding_0__SHIFT
125910. DPM_TABLE_300__VceLevel_3_padding_1_MASK
125911. DPM_TABLE_300__VceLevel_3_padding_1__SHIFT
125912. DPM_TABLE_300__VceLevel_3_padding_2_MASK
125913. DPM_TABLE_300__VceLevel_3_padding_2__SHIFT
125914. DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3_MASK
125915. DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3__SHIFT
125916. DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK
125917. DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT
125918. DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK
125919. DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT
125920. DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK
125921. DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT
125922. DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK
125923. DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT
125924. DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK
125925. DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT
125926. DPM_TABLE_301__VceLevel_4_Frequency_MASK
125927. DPM_TABLE_301__VceLevel_4_Frequency__SHIFT
125928. DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4_MASK
125929. DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4__SHIFT
125930. DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK
125931. DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT
125932. DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK
125933. DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT
125934. DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK
125935. DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT
125936. DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK
125937. DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT
125938. DPM_TABLE_302__MemoryLevel_5_padding_MASK
125939. DPM_TABLE_302__MemoryLevel_5_padding__SHIFT
125940. DPM_TABLE_302__VceLevel_4_MinVoltage_Phases_MASK
125941. DPM_TABLE_302__VceLevel_4_MinVoltage_Phases__SHIFT
125942. DPM_TABLE_302__VceLevel_4_MinVoltage_VddGfx_MASK
125943. DPM_TABLE_302__VceLevel_4_MinVoltage_VddGfx__SHIFT
125944. DPM_TABLE_302__VceLevel_4_MinVoltage_Vddc_MASK
125945. DPM_TABLE_302__VceLevel_4_MinVoltage_Vddc__SHIFT
125946. DPM_TABLE_302__VceLevel_4_MinVoltage_Vddci_MASK
125947. DPM_TABLE_302__VceLevel_4_MinVoltage_Vddci__SHIFT
125948. DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK
125949. DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT
125950. DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum_MASK
125951. DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum__SHIFT
125952. DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK
125953. DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT
125954. DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK
125955. DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT
125956. DPM_TABLE_303__MemoryLevel_5_padding1_0_MASK
125957. DPM_TABLE_303__MemoryLevel_5_padding1_0__SHIFT
125958. DPM_TABLE_303__MemoryLevel_5_padding1_1_MASK
125959. DPM_TABLE_303__MemoryLevel_5_padding1_1__SHIFT
125960. DPM_TABLE_303__MemoryLevel_5_padding1_MASK
125961. DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT
125962. DPM_TABLE_303__VceLevel_4_Divider_MASK
125963. DPM_TABLE_303__VceLevel_4_Divider__SHIFT
125964. DPM_TABLE_303__VceLevel_4_padding_0_MASK
125965. DPM_TABLE_303__VceLevel_4_padding_0__SHIFT
125966. DPM_TABLE_303__VceLevel_4_padding_1_MASK
125967. DPM_TABLE_303__VceLevel_4_padding_1__SHIFT
125968. DPM_TABLE_303__VceLevel_4_padding_2_MASK
125969. DPM_TABLE_303__VceLevel_4_padding_2__SHIFT
125970. DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK
125971. DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT
125972. DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2_MASK
125973. DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2__SHIFT
125974. DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK
125975. DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT
125976. DPM_TABLE_304__VceLevel_5_Frequency_MASK
125977. DPM_TABLE_304__VceLevel_5_Frequency__SHIFT
125978. DPM_TABLE_305__ACPILevel_CcPwrDynRm_MASK
125979. DPM_TABLE_305__ACPILevel_CcPwrDynRm__SHIFT
125980. DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK
125981. DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT
125982. DPM_TABLE_305__SclkStepSize_MASK
125983. DPM_TABLE_305__SclkStepSize__SHIFT
125984. DPM_TABLE_305__VceLevel_5_MinVoltage_Phases_MASK
125985. DPM_TABLE_305__VceLevel_5_MinVoltage_Phases__SHIFT
125986. DPM_TABLE_305__VceLevel_5_MinVoltage_VddGfx_MASK
125987. DPM_TABLE_305__VceLevel_5_MinVoltage_VddGfx__SHIFT
125988. DPM_TABLE_305__VceLevel_5_MinVoltage_Vddc_MASK
125989. DPM_TABLE_305__VceLevel_5_MinVoltage_Vddc__SHIFT
125990. DPM_TABLE_305__VceLevel_5_MinVoltage_Vddci_MASK
125991. DPM_TABLE_305__VceLevel_5_MinVoltage_Vddci__SHIFT
125992. DPM_TABLE_306__ACPILevel_CcPwrDynRm1_MASK
125993. DPM_TABLE_306__ACPILevel_CcPwrDynRm1__SHIFT
125994. DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK
125995. DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT
125996. DPM_TABLE_306__Smio_0_MASK
125997. DPM_TABLE_306__Smio_0__SHIFT
125998. DPM_TABLE_306__VceLevel_5_Divider_MASK
125999. DPM_TABLE_306__VceLevel_5_Divider__SHIFT
126000. DPM_TABLE_306__VceLevel_5_padding_0_MASK
126001. DPM_TABLE_306__VceLevel_5_padding_0__SHIFT
126002. DPM_TABLE_306__VceLevel_5_padding_1_MASK
126003. DPM_TABLE_306__VceLevel_5_padding_1__SHIFT
126004. DPM_TABLE_306__VceLevel_5_padding_2_MASK
126005. DPM_TABLE_306__VceLevel_5_padding_2__SHIFT
126006. DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK
126007. DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT
126008. DPM_TABLE_307__Smio_1_MASK
126009. DPM_TABLE_307__Smio_1__SHIFT
126010. DPM_TABLE_307__UvdLevel_0_VclkFrequency_MASK
126011. DPM_TABLE_307__UvdLevel_0_VclkFrequency__SHIFT
126012. DPM_TABLE_307__VceLevel_6_Frequency_MASK
126013. DPM_TABLE_307__VceLevel_6_Frequency__SHIFT
126014. DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK
126015. DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT
126016. DPM_TABLE_308__Smio_2_MASK
126017. DPM_TABLE_308__Smio_2__SHIFT
126018. DPM_TABLE_308__UvdLevel_0_DclkFrequency_MASK
126019. DPM_TABLE_308__UvdLevel_0_DclkFrequency__SHIFT
126020. DPM_TABLE_308__VceLevel_6_MinVoltage_Phases_MASK
126021. DPM_TABLE_308__VceLevel_6_MinVoltage_Phases__SHIFT
126022. DPM_TABLE_308__VceLevel_6_MinVoltage_VddGfx_MASK
126023. DPM_TABLE_308__VceLevel_6_MinVoltage_VddGfx__SHIFT
126024. DPM_TABLE_308__VceLevel_6_MinVoltage_Vddc_MASK
126025. DPM_TABLE_308__VceLevel_6_MinVoltage_Vddc__SHIFT
126026. DPM_TABLE_308__VceLevel_6_MinVoltage_Vddci_MASK
126027. DPM_TABLE_308__VceLevel_6_MinVoltage_Vddci__SHIFT
126028. DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK
126029. DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT
126030. DPM_TABLE_309__Smio_3_MASK
126031. DPM_TABLE_309__Smio_3__SHIFT
126032. DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases_MASK
126033. DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases__SHIFT
126034. DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx_MASK
126035. DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx__SHIFT
126036. DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc_MASK
126037. DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc__SHIFT
126038. DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci_MASK
126039. DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci__SHIFT
126040. DPM_TABLE_309__VceLevel_6_Divider_MASK
126041. DPM_TABLE_309__VceLevel_6_Divider__SHIFT
126042. DPM_TABLE_309__VceLevel_6_padding_0_MASK
126043. DPM_TABLE_309__VceLevel_6_padding_0__SHIFT
126044. DPM_TABLE_309__VceLevel_6_padding_1_MASK
126045. DPM_TABLE_309__VceLevel_6_padding_1__SHIFT
126046. DPM_TABLE_309__VceLevel_6_padding_2_MASK
126047. DPM_TABLE_309__VceLevel_6_padding_2__SHIFT
126048. DPM_TABLE_30__GraphicsLevel_1_SclkFrequency_MASK
126049. DPM_TABLE_30__GraphicsLevel_1_SclkFrequency__SHIFT
126050. DPM_TABLE_30__SmioMask1_MASK
126051. DPM_TABLE_30__SmioMask1__SHIFT
126052. DPM_TABLE_30__SmioMaskVddcPhase_MASK
126053. DPM_TABLE_30__SmioMaskVddcPhase__SHIFT
126054. DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK
126055. DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT
126056. DPM_TABLE_310__Smio_4_MASK
126057. DPM_TABLE_310__Smio_4__SHIFT
126058. DPM_TABLE_310__UvdLevel_0_DclkDivider_MASK
126059. DPM_TABLE_310__UvdLevel_0_DclkDivider__SHIFT
126060. DPM_TABLE_310__UvdLevel_0_VclkDivider_MASK
126061. DPM_TABLE_310__UvdLevel_0_VclkDivider__SHIFT
126062. DPM_TABLE_310__UvdLevel_0_padding_0_MASK
126063. DPM_TABLE_310__UvdLevel_0_padding_0__SHIFT
126064. DPM_TABLE_310__UvdLevel_0_padding_1_MASK
126065. DPM_TABLE_310__UvdLevel_0_padding_1__SHIFT
126066. DPM_TABLE_310__VceLevel_7_Frequency_MASK
126067. DPM_TABLE_310__VceLevel_7_Frequency__SHIFT
126068. DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK
126069. DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT
126070. DPM_TABLE_311__Smio_5_MASK
126071. DPM_TABLE_311__Smio_5__SHIFT
126072. DPM_TABLE_311__UvdLevel_1_VclkFrequency_MASK
126073. DPM_TABLE_311__UvdLevel_1_VclkFrequency__SHIFT
126074. DPM_TABLE_311__VceLevel_7_MinVoltage_Phases_MASK
126075. DPM_TABLE_311__VceLevel_7_MinVoltage_Phases__SHIFT
126076. DPM_TABLE_311__VceLevel_7_MinVoltage_VddGfx_MASK
126077. DPM_TABLE_311__VceLevel_7_MinVoltage_VddGfx__SHIFT
126078. DPM_TABLE_311__VceLevel_7_MinVoltage_Vddc_MASK
126079. DPM_TABLE_311__VceLevel_7_MinVoltage_Vddc__SHIFT
126080. DPM_TABLE_311__VceLevel_7_MinVoltage_Vddci_MASK
126081. DPM_TABLE_311__VceLevel_7_MinVoltage_Vddci__SHIFT
126082. DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK
126083. DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT
126084. DPM_TABLE_312__Smio_6_MASK
126085. DPM_TABLE_312__Smio_6__SHIFT
126086. DPM_TABLE_312__UvdLevel_1_DclkFrequency_MASK
126087. DPM_TABLE_312__UvdLevel_1_DclkFrequency__SHIFT
126088. DPM_TABLE_312__VceLevel_7_Divider_MASK
126089. DPM_TABLE_312__VceLevel_7_Divider__SHIFT
126090. DPM_TABLE_312__VceLevel_7_padding_0_MASK
126091. DPM_TABLE_312__VceLevel_7_padding_0__SHIFT
126092. DPM_TABLE_312__VceLevel_7_padding_1_MASK
126093. DPM_TABLE_312__VceLevel_7_padding_1__SHIFT
126094. DPM_TABLE_312__VceLevel_7_padding_2_MASK
126095. DPM_TABLE_312__VceLevel_7_padding_2__SHIFT
126096. DPM_TABLE_313__AcpLevel_0_Frequency_MASK
126097. DPM_TABLE_313__AcpLevel_0_Frequency__SHIFT
126098. DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK
126099. DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT
126100. DPM_TABLE_313__LinkLevel_0_Padding_MASK
126101. DPM_TABLE_313__LinkLevel_0_Padding__SHIFT
126102. DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK
126103. DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT
126104. DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK
126105. DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT
126106. DPM_TABLE_313__Smio_7_MASK
126107. DPM_TABLE_313__Smio_7__SHIFT
126108. DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases_MASK
126109. DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases__SHIFT
126110. DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx_MASK
126111. DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx__SHIFT
126112. DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc_MASK
126113. DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc__SHIFT
126114. DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci_MASK
126115. DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci__SHIFT
126116. DPM_TABLE_314__AcpLevel_0_MinVoltage_Phases_MASK
126117. DPM_TABLE_314__AcpLevel_0_MinVoltage_Phases__SHIFT
126118. DPM_TABLE_314__AcpLevel_0_MinVoltage_VddGfx_MASK
126119. DPM_TABLE_314__AcpLevel_0_MinVoltage_VddGfx__SHIFT
126120. DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddc_MASK
126121. DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddc__SHIFT
126122. DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddci_MASK
126123. DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddci__SHIFT
126124. DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK
126125. DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT
126126. DPM_TABLE_314__Smio_8_MASK
126127. DPM_TABLE_314__Smio_8__SHIFT
126128. DPM_TABLE_314__UvdLevel_1_DclkDivider_MASK
126129. DPM_TABLE_314__UvdLevel_1_DclkDivider__SHIFT
126130. DPM_TABLE_314__UvdLevel_1_VclkDivider_MASK
126131. DPM_TABLE_314__UvdLevel_1_VclkDivider__SHIFT
126132. DPM_TABLE_314__UvdLevel_1_padding_0_MASK
126133. DPM_TABLE_314__UvdLevel_1_padding_0__SHIFT
126134. DPM_TABLE_314__UvdLevel_1_padding_1_MASK
126135. DPM_TABLE_314__UvdLevel_1_padding_1__SHIFT
126136. DPM_TABLE_315__AcpLevel_0_Divider_MASK
126137. DPM_TABLE_315__AcpLevel_0_Divider__SHIFT
126138. DPM_TABLE_315__AcpLevel_0_padding_0_MASK
126139. DPM_TABLE_315__AcpLevel_0_padding_0__SHIFT
126140. DPM_TABLE_315__AcpLevel_0_padding_1_MASK
126141. DPM_TABLE_315__AcpLevel_0_padding_1__SHIFT
126142. DPM_TABLE_315__AcpLevel_0_padding_2_MASK
126143. DPM_TABLE_315__AcpLevel_0_padding_2__SHIFT
126144. DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK
126145. DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT
126146. DPM_TABLE_315__Smio_9_MASK
126147. DPM_TABLE_315__Smio_9__SHIFT
126148. DPM_TABLE_315__UvdLevel_2_VclkFrequency_MASK
126149. DPM_TABLE_315__UvdLevel_2_VclkFrequency__SHIFT
126150. DPM_TABLE_316__AcpLevel_1_Frequency_MASK
126151. DPM_TABLE_316__AcpLevel_1_Frequency__SHIFT
126152. DPM_TABLE_316__LinkLevel_0_Reserved_MASK
126153. DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT
126154. DPM_TABLE_316__Smio_10_MASK
126155. DPM_TABLE_316__Smio_10__SHIFT
126156. DPM_TABLE_316__UvdLevel_2_DclkFrequency_MASK
126157. DPM_TABLE_316__UvdLevel_2_DclkFrequency__SHIFT
126158. DPM_TABLE_317__AcpLevel_1_MinVoltage_Phases_MASK
126159. DPM_TABLE_317__AcpLevel_1_MinVoltage_Phases__SHIFT
126160. DPM_TABLE_317__AcpLevel_1_MinVoltage_VddGfx_MASK
126161. DPM_TABLE_317__AcpLevel_1_MinVoltage_VddGfx__SHIFT
126162. DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddc_MASK
126163. DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddc__SHIFT
126164. DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddci_MASK
126165. DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddci__SHIFT
126166. DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK
126167. DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT
126168. DPM_TABLE_317__LinkLevel_1_Padding_MASK
126169. DPM_TABLE_317__LinkLevel_1_Padding__SHIFT
126170. DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK
126171. DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT
126172. DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK
126173. DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT
126174. DPM_TABLE_317__Smio_11_MASK
126175. DPM_TABLE_317__Smio_11__SHIFT
126176. DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases_MASK
126177. DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases__SHIFT
126178. DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx_MASK
126179. DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx__SHIFT
126180. DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc_MASK
126181. DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc__SHIFT
126182. DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci_MASK
126183. DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci__SHIFT
126184. DPM_TABLE_318__AcpLevel_1_Divider_MASK
126185. DPM_TABLE_318__AcpLevel_1_Divider__SHIFT
126186. DPM_TABLE_318__AcpLevel_1_padding_0_MASK
126187. DPM_TABLE_318__AcpLevel_1_padding_0__SHIFT
126188. DPM_TABLE_318__AcpLevel_1_padding_1_MASK
126189. DPM_TABLE_318__AcpLevel_1_padding_1__SHIFT
126190. DPM_TABLE_318__AcpLevel_1_padding_2_MASK
126191. DPM_TABLE_318__AcpLevel_1_padding_2__SHIFT
126192. DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK
126193. DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT
126194. DPM_TABLE_318__Smio_12_MASK
126195. DPM_TABLE_318__Smio_12__SHIFT
126196. DPM_TABLE_318__UvdLevel_2_DclkDivider_MASK
126197. DPM_TABLE_318__UvdLevel_2_DclkDivider__SHIFT
126198. DPM_TABLE_318__UvdLevel_2_VclkDivider_MASK
126199. DPM_TABLE_318__UvdLevel_2_VclkDivider__SHIFT
126200. DPM_TABLE_318__UvdLevel_2_padding_0_MASK
126201. DPM_TABLE_318__UvdLevel_2_padding_0__SHIFT
126202. DPM_TABLE_318__UvdLevel_2_padding_1_MASK
126203. DPM_TABLE_318__UvdLevel_2_padding_1__SHIFT
126204. DPM_TABLE_319__AcpLevel_2_Frequency_MASK
126205. DPM_TABLE_319__AcpLevel_2_Frequency__SHIFT
126206. DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK
126207. DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT
126208. DPM_TABLE_319__Smio_13_MASK
126209. DPM_TABLE_319__Smio_13__SHIFT
126210. DPM_TABLE_319__UvdLevel_3_VclkFrequency_MASK
126211. DPM_TABLE_319__UvdLevel_3_VclkFrequency__SHIFT
126212. DPM_TABLE_31__GraphicsLevel_1_ActivityLevel_MASK
126213. DPM_TABLE_31__GraphicsLevel_1_ActivityLevel__SHIFT
126214. DPM_TABLE_31__GraphicsLevel_1_VidOffset_MASK
126215. DPM_TABLE_31__GraphicsLevel_1_VidOffset__SHIFT
126216. DPM_TABLE_31__GraphicsLevel_1_Vid_MASK
126217. DPM_TABLE_31__GraphicsLevel_1_Vid__SHIFT
126218. DPM_TABLE_31__SmioMask2_MASK
126219. DPM_TABLE_31__SmioMask2__SHIFT
126220. DPM_TABLE_31__SmioMaskVddciVid_MASK
126221. DPM_TABLE_31__SmioMaskVddciVid__SHIFT
126222. DPM_TABLE_320__AcpLevel_2_MinVoltage_Phases_MASK
126223. DPM_TABLE_320__AcpLevel_2_MinVoltage_Phases__SHIFT
126224. DPM_TABLE_320__AcpLevel_2_MinVoltage_VddGfx_MASK
126225. DPM_TABLE_320__AcpLevel_2_MinVoltage_VddGfx__SHIFT
126226. DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddc_MASK
126227. DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddc__SHIFT
126228. DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddci_MASK
126229. DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddci__SHIFT
126230. DPM_TABLE_320__LinkLevel_1_Reserved_MASK
126231. DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT
126232. DPM_TABLE_320__Smio_14_MASK
126233. DPM_TABLE_320__Smio_14__SHIFT
126234. DPM_TABLE_320__UvdLevel_3_DclkFrequency_MASK
126235. DPM_TABLE_320__UvdLevel_3_DclkFrequency__SHIFT
126236. DPM_TABLE_321__AcpLevel_2_Divider_MASK
126237. DPM_TABLE_321__AcpLevel_2_Divider__SHIFT
126238. DPM_TABLE_321__AcpLevel_2_padding_0_MASK
126239. DPM_TABLE_321__AcpLevel_2_padding_0__SHIFT
126240. DPM_TABLE_321__AcpLevel_2_padding_1_MASK
126241. DPM_TABLE_321__AcpLevel_2_padding_1__SHIFT
126242. DPM_TABLE_321__AcpLevel_2_padding_2_MASK
126243. DPM_TABLE_321__AcpLevel_2_padding_2__SHIFT
126244. DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK
126245. DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT
126246. DPM_TABLE_321__LinkLevel_2_Padding_MASK
126247. DPM_TABLE_321__LinkLevel_2_Padding__SHIFT
126248. DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK
126249. DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT
126250. DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK
126251. DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT
126252. DPM_TABLE_321__Smio_15_MASK
126253. DPM_TABLE_321__Smio_15__SHIFT
126254. DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases_MASK
126255. DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases__SHIFT
126256. DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx_MASK
126257. DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx__SHIFT
126258. DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc_MASK
126259. DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc__SHIFT
126260. DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci_MASK
126261. DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci__SHIFT
126262. DPM_TABLE_322__AcpLevel_3_Frequency_MASK
126263. DPM_TABLE_322__AcpLevel_3_Frequency__SHIFT
126264. DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK
126265. DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT
126266. DPM_TABLE_322__Smio_16_MASK
126267. DPM_TABLE_322__Smio_16__SHIFT
126268. DPM_TABLE_322__UvdLevel_3_DclkDivider_MASK
126269. DPM_TABLE_322__UvdLevel_3_DclkDivider__SHIFT
126270. DPM_TABLE_322__UvdLevel_3_VclkDivider_MASK
126271. DPM_TABLE_322__UvdLevel_3_VclkDivider__SHIFT
126272. DPM_TABLE_322__UvdLevel_3_padding_0_MASK
126273. DPM_TABLE_322__UvdLevel_3_padding_0__SHIFT
126274. DPM_TABLE_322__UvdLevel_3_padding_1_MASK
126275. DPM_TABLE_322__UvdLevel_3_padding_1__SHIFT
126276. DPM_TABLE_323__AcpLevel_3_MinVoltage_Phases_MASK
126277. DPM_TABLE_323__AcpLevel_3_MinVoltage_Phases__SHIFT
126278. DPM_TABLE_323__AcpLevel_3_MinVoltage_VddGfx_MASK
126279. DPM_TABLE_323__AcpLevel_3_MinVoltage_VddGfx__SHIFT
126280. DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddc_MASK
126281. DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddc__SHIFT
126282. DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddci_MASK
126283. DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddci__SHIFT
126284. DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK
126285. DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT
126286. DPM_TABLE_323__Smio_17_MASK
126287. DPM_TABLE_323__Smio_17__SHIFT
126288. DPM_TABLE_323__UvdLevel_4_VclkFrequency_MASK
126289. DPM_TABLE_323__UvdLevel_4_VclkFrequency__SHIFT
126290. DPM_TABLE_324__AcpLevel_3_Divider_MASK
126291. DPM_TABLE_324__AcpLevel_3_Divider__SHIFT
126292. DPM_TABLE_324__AcpLevel_3_padding_0_MASK
126293. DPM_TABLE_324__AcpLevel_3_padding_0__SHIFT
126294. DPM_TABLE_324__AcpLevel_3_padding_1_MASK
126295. DPM_TABLE_324__AcpLevel_3_padding_1__SHIFT
126296. DPM_TABLE_324__AcpLevel_3_padding_2_MASK
126297. DPM_TABLE_324__AcpLevel_3_padding_2__SHIFT
126298. DPM_TABLE_324__LinkLevel_2_Reserved_MASK
126299. DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT
126300. DPM_TABLE_324__Smio_18_MASK
126301. DPM_TABLE_324__Smio_18__SHIFT
126302. DPM_TABLE_324__UvdLevel_4_DclkFrequency_MASK
126303. DPM_TABLE_324__UvdLevel_4_DclkFrequency__SHIFT
126304. DPM_TABLE_325__AcpLevel_4_Frequency_MASK
126305. DPM_TABLE_325__AcpLevel_4_Frequency__SHIFT
126306. DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK
126307. DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT
126308. DPM_TABLE_325__LinkLevel_3_Padding_MASK
126309. DPM_TABLE_325__LinkLevel_3_Padding__SHIFT
126310. DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK
126311. DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT
126312. DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK
126313. DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT
126314. DPM_TABLE_325__Smio_19_MASK
126315. DPM_TABLE_325__Smio_19__SHIFT
126316. DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases_MASK
126317. DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases__SHIFT
126318. DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx_MASK
126319. DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx__SHIFT
126320. DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc_MASK
126321. DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc__SHIFT
126322. DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci_MASK
126323. DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci__SHIFT
126324. DPM_TABLE_326__AcpLevel_4_MinVoltage_Phases_MASK
126325. DPM_TABLE_326__AcpLevel_4_MinVoltage_Phases__SHIFT
126326. DPM_TABLE_326__AcpLevel_4_MinVoltage_VddGfx_MASK
126327. DPM_TABLE_326__AcpLevel_4_MinVoltage_VddGfx__SHIFT
126328. DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddc_MASK
126329. DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddc__SHIFT
126330. DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddci_MASK
126331. DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddci__SHIFT
126332. DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK
126333. DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT
126334. DPM_TABLE_326__Smio_20_MASK
126335. DPM_TABLE_326__Smio_20__SHIFT
126336. DPM_TABLE_326__UvdLevel_4_DclkDivider_MASK
126337. DPM_TABLE_326__UvdLevel_4_DclkDivider__SHIFT
126338. DPM_TABLE_326__UvdLevel_4_VclkDivider_MASK
126339. DPM_TABLE_326__UvdLevel_4_VclkDivider__SHIFT
126340. DPM_TABLE_326__UvdLevel_4_padding_0_MASK
126341. DPM_TABLE_326__UvdLevel_4_padding_0__SHIFT
126342. DPM_TABLE_326__UvdLevel_4_padding_1_MASK
126343. DPM_TABLE_326__UvdLevel_4_padding_1__SHIFT
126344. DPM_TABLE_327__AcpLevel_4_Divider_MASK
126345. DPM_TABLE_327__AcpLevel_4_Divider__SHIFT
126346. DPM_TABLE_327__AcpLevel_4_padding_0_MASK
126347. DPM_TABLE_327__AcpLevel_4_padding_0__SHIFT
126348. DPM_TABLE_327__AcpLevel_4_padding_1_MASK
126349. DPM_TABLE_327__AcpLevel_4_padding_1__SHIFT
126350. DPM_TABLE_327__AcpLevel_4_padding_2_MASK
126351. DPM_TABLE_327__AcpLevel_4_padding_2__SHIFT
126352. DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK
126353. DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT
126354. DPM_TABLE_327__Smio_21_MASK
126355. DPM_TABLE_327__Smio_21__SHIFT
126356. DPM_TABLE_327__UvdLevel_5_VclkFrequency_MASK
126357. DPM_TABLE_327__UvdLevel_5_VclkFrequency__SHIFT
126358. DPM_TABLE_328__AcpLevel_5_Frequency_MASK
126359. DPM_TABLE_328__AcpLevel_5_Frequency__SHIFT
126360. DPM_TABLE_328__LinkLevel_3_Reserved_MASK
126361. DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT
126362. DPM_TABLE_328__Smio_22_MASK
126363. DPM_TABLE_328__Smio_22__SHIFT
126364. DPM_TABLE_328__UvdLevel_5_DclkFrequency_MASK
126365. DPM_TABLE_328__UvdLevel_5_DclkFrequency__SHIFT
126366. DPM_TABLE_329__AcpLevel_5_MinVoltage_Phases_MASK
126367. DPM_TABLE_329__AcpLevel_5_MinVoltage_Phases__SHIFT
126368. DPM_TABLE_329__AcpLevel_5_MinVoltage_VddGfx_MASK
126369. DPM_TABLE_329__AcpLevel_5_MinVoltage_VddGfx__SHIFT
126370. DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddc_MASK
126371. DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddc__SHIFT
126372. DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddci_MASK
126373. DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddci__SHIFT
126374. DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK
126375. DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT
126376. DPM_TABLE_329__LinkLevel_4_Padding_MASK
126377. DPM_TABLE_329__LinkLevel_4_Padding__SHIFT
126378. DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK
126379. DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT
126380. DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK
126381. DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT
126382. DPM_TABLE_329__Smio_23_MASK
126383. DPM_TABLE_329__Smio_23__SHIFT
126384. DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases_MASK
126385. DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases__SHIFT
126386. DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx_MASK
126387. DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx__SHIFT
126388. DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc_MASK
126389. DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc__SHIFT
126390. DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci_MASK
126391. DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci__SHIFT
126392. DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1_MASK
126393. DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1__SHIFT
126394. DPM_TABLE_32__GraphicsLevel_1_GnbSlow_MASK
126395. DPM_TABLE_32__GraphicsLevel_1_GnbSlow__SHIFT
126396. DPM_TABLE_32__GraphicsLevel_1_PowerThrottle_MASK
126397. DPM_TABLE_32__GraphicsLevel_1_PowerThrottle__SHIFT
126398. DPM_TABLE_32__GraphicsLevel_1_SclkDid_MASK
126399. DPM_TABLE_32__GraphicsLevel_1_SclkDid__SHIFT
126400. DPM_TABLE_32__SmioMaskMvddVid_MASK
126401. DPM_TABLE_32__SmioMaskMvddVid__SHIFT
126402. DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK
126403. DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT
126404. DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK
126405. DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT
126406. DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK
126407. DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT
126408. DPM_TABLE_330__AcpLevel_5_Divider_MASK
126409. DPM_TABLE_330__AcpLevel_5_Divider__SHIFT
126410. DPM_TABLE_330__AcpLevel_5_padding_0_MASK
126411. DPM_TABLE_330__AcpLevel_5_padding_0__SHIFT
126412. DPM_TABLE_330__AcpLevel_5_padding_1_MASK
126413. DPM_TABLE_330__AcpLevel_5_padding_1__SHIFT
126414. DPM_TABLE_330__AcpLevel_5_padding_2_MASK
126415. DPM_TABLE_330__AcpLevel_5_padding_2__SHIFT
126416. DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK
126417. DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT
126418. DPM_TABLE_330__Smio_24_MASK
126419. DPM_TABLE_330__Smio_24__SHIFT
126420. DPM_TABLE_330__UvdLevel_5_DclkDivider_MASK
126421. DPM_TABLE_330__UvdLevel_5_DclkDivider__SHIFT
126422. DPM_TABLE_330__UvdLevel_5_VclkDivider_MASK
126423. DPM_TABLE_330__UvdLevel_5_VclkDivider__SHIFT
126424. DPM_TABLE_330__UvdLevel_5_padding_0_MASK
126425. DPM_TABLE_330__UvdLevel_5_padding_0__SHIFT
126426. DPM_TABLE_330__UvdLevel_5_padding_1_MASK
126427. DPM_TABLE_330__UvdLevel_5_padding_1__SHIFT
126428. DPM_TABLE_331__AcpLevel_6_Frequency_MASK
126429. DPM_TABLE_331__AcpLevel_6_Frequency__SHIFT
126430. DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK
126431. DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT
126432. DPM_TABLE_331__Smio_25_MASK
126433. DPM_TABLE_331__Smio_25__SHIFT
126434. DPM_TABLE_331__UvdLevel_6_VclkFrequency_MASK
126435. DPM_TABLE_331__UvdLevel_6_VclkFrequency__SHIFT
126436. DPM_TABLE_332__AcpLevel_6_MinVoltage_Phases_MASK
126437. DPM_TABLE_332__AcpLevel_6_MinVoltage_Phases__SHIFT
126438. DPM_TABLE_332__AcpLevel_6_MinVoltage_VddGfx_MASK
126439. DPM_TABLE_332__AcpLevel_6_MinVoltage_VddGfx__SHIFT
126440. DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddc_MASK
126441. DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddc__SHIFT
126442. DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddci_MASK
126443. DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddci__SHIFT
126444. DPM_TABLE_332__LinkLevel_4_Reserved_MASK
126445. DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT
126446. DPM_TABLE_332__Smio_26_MASK
126447. DPM_TABLE_332__Smio_26__SHIFT
126448. DPM_TABLE_332__UvdLevel_6_DclkFrequency_MASK
126449. DPM_TABLE_332__UvdLevel_6_DclkFrequency__SHIFT
126450. DPM_TABLE_333__AcpLevel_6_Divider_MASK
126451. DPM_TABLE_333__AcpLevel_6_Divider__SHIFT
126452. DPM_TABLE_333__AcpLevel_6_padding_0_MASK
126453. DPM_TABLE_333__AcpLevel_6_padding_0__SHIFT
126454. DPM_TABLE_333__AcpLevel_6_padding_1_MASK
126455. DPM_TABLE_333__AcpLevel_6_padding_1__SHIFT
126456. DPM_TABLE_333__AcpLevel_6_padding_2_MASK
126457. DPM_TABLE_333__AcpLevel_6_padding_2__SHIFT
126458. DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK
126459. DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT
126460. DPM_TABLE_333__LinkLevel_5_Padding_MASK
126461. DPM_TABLE_333__LinkLevel_5_Padding__SHIFT
126462. DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK
126463. DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT
126464. DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK
126465. DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT
126466. DPM_TABLE_333__Smio_27_MASK
126467. DPM_TABLE_333__Smio_27__SHIFT
126468. DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases_MASK
126469. DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases__SHIFT
126470. DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx_MASK
126471. DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx__SHIFT
126472. DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc_MASK
126473. DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc__SHIFT
126474. DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci_MASK
126475. DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci__SHIFT
126476. DPM_TABLE_334__AcpLevel_7_Frequency_MASK
126477. DPM_TABLE_334__AcpLevel_7_Frequency__SHIFT
126478. DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK
126479. DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT
126480. DPM_TABLE_334__Smio_28_MASK
126481. DPM_TABLE_334__Smio_28__SHIFT
126482. DPM_TABLE_334__UvdLevel_6_DclkDivider_MASK
126483. DPM_TABLE_334__UvdLevel_6_DclkDivider__SHIFT
126484. DPM_TABLE_334__UvdLevel_6_VclkDivider_MASK
126485. DPM_TABLE_334__UvdLevel_6_VclkDivider__SHIFT
126486. DPM_TABLE_334__UvdLevel_6_padding_0_MASK
126487. DPM_TABLE_334__UvdLevel_6_padding_0__SHIFT
126488. DPM_TABLE_334__UvdLevel_6_padding_1_MASK
126489. DPM_TABLE_334__UvdLevel_6_padding_1__SHIFT
126490. DPM_TABLE_335__AcpLevel_7_MinVoltage_Phases_MASK
126491. DPM_TABLE_335__AcpLevel_7_MinVoltage_Phases__SHIFT
126492. DPM_TABLE_335__AcpLevel_7_MinVoltage_VddGfx_MASK
126493. DPM_TABLE_335__AcpLevel_7_MinVoltage_VddGfx__SHIFT
126494. DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddc_MASK
126495. DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddc__SHIFT
126496. DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddci_MASK
126497. DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddci__SHIFT
126498. DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK
126499. DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT
126500. DPM_TABLE_335__Smio_29_MASK
126501. DPM_TABLE_335__Smio_29__SHIFT
126502. DPM_TABLE_335__UvdLevel_7_VclkFrequency_MASK
126503. DPM_TABLE_335__UvdLevel_7_VclkFrequency__SHIFT
126504. DPM_TABLE_336__AcpLevel_7_Divider_MASK
126505. DPM_TABLE_336__AcpLevel_7_Divider__SHIFT
126506. DPM_TABLE_336__AcpLevel_7_padding_0_MASK
126507. DPM_TABLE_336__AcpLevel_7_padding_0__SHIFT
126508. DPM_TABLE_336__AcpLevel_7_padding_1_MASK
126509. DPM_TABLE_336__AcpLevel_7_padding_1__SHIFT
126510. DPM_TABLE_336__AcpLevel_7_padding_2_MASK
126511. DPM_TABLE_336__AcpLevel_7_padding_2__SHIFT
126512. DPM_TABLE_336__LinkLevel_5_Reserved_MASK
126513. DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT
126514. DPM_TABLE_336__Smio_30_MASK
126515. DPM_TABLE_336__Smio_30__SHIFT
126516. DPM_TABLE_336__UvdLevel_7_DclkFrequency_MASK
126517. DPM_TABLE_336__UvdLevel_7_DclkFrequency__SHIFT
126518. DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK
126519. DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT
126520. DPM_TABLE_337__LinkLevel_6_Padding_MASK
126521. DPM_TABLE_337__LinkLevel_6_Padding__SHIFT
126522. DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK
126523. DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT
126524. DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK
126525. DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT
126526. DPM_TABLE_337__SamuLevel_0_Frequency_MASK
126527. DPM_TABLE_337__SamuLevel_0_Frequency__SHIFT
126528. DPM_TABLE_337__Smio_31_MASK
126529. DPM_TABLE_337__Smio_31__SHIFT
126530. DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases_MASK
126531. DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases__SHIFT
126532. DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx_MASK
126533. DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx__SHIFT
126534. DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc_MASK
126535. DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc__SHIFT
126536. DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci_MASK
126537. DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci__SHIFT
126538. DPM_TABLE_338__GraphicsBootLevel_MASK
126539. DPM_TABLE_338__GraphicsBootLevel__SHIFT
126540. DPM_TABLE_338__GraphicsInterval_MASK
126541. DPM_TABLE_338__GraphicsInterval__SHIFT
126542. DPM_TABLE_338__GraphicsThermThrottleEnable_MASK
126543. DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT
126544. DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK
126545. DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT
126546. DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK
126547. DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT
126548. DPM_TABLE_338__SamuLevel_0_MinVoltage_Phases_MASK
126549. DPM_TABLE_338__SamuLevel_0_MinVoltage_Phases__SHIFT
126550. DPM_TABLE_338__SamuLevel_0_MinVoltage_VddGfx_MASK
126551. DPM_TABLE_338__SamuLevel_0_MinVoltage_VddGfx__SHIFT
126552. DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddc_MASK
126553. DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddc__SHIFT
126554. DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddci_MASK
126555. DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddci__SHIFT
126556. DPM_TABLE_338__UvdLevel_7_DclkDivider_MASK
126557. DPM_TABLE_338__UvdLevel_7_DclkDivider__SHIFT
126558. DPM_TABLE_338__UvdLevel_7_VclkDivider_MASK
126559. DPM_TABLE_338__UvdLevel_7_VclkDivider__SHIFT
126560. DPM_TABLE_338__UvdLevel_7_padding_0_MASK
126561. DPM_TABLE_338__UvdLevel_7_padding_0__SHIFT
126562. DPM_TABLE_338__UvdLevel_7_padding_1_MASK
126563. DPM_TABLE_338__UvdLevel_7_padding_1__SHIFT
126564. DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK
126565. DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT
126566. DPM_TABLE_339__SamuLevel_0_Divider_MASK
126567. DPM_TABLE_339__SamuLevel_0_Divider__SHIFT
126568. DPM_TABLE_339__SamuLevel_0_padding_0_MASK
126569. DPM_TABLE_339__SamuLevel_0_padding_0__SHIFT
126570. DPM_TABLE_339__SamuLevel_0_padding_1_MASK
126571. DPM_TABLE_339__SamuLevel_0_padding_1__SHIFT
126572. DPM_TABLE_339__SamuLevel_0_padding_2_MASK
126573. DPM_TABLE_339__SamuLevel_0_padding_2__SHIFT
126574. DPM_TABLE_339__TemperatureLimitHigh_MASK
126575. DPM_TABLE_339__TemperatureLimitHigh__SHIFT
126576. DPM_TABLE_339__ThermalInterval_MASK
126577. DPM_TABLE_339__ThermalInterval__SHIFT
126578. DPM_TABLE_339__VceLevel_0_Frequency_MASK
126579. DPM_TABLE_339__VceLevel_0_Frequency__SHIFT
126580. DPM_TABLE_339__VoltageInterval_MASK
126581. DPM_TABLE_339__VoltageInterval__SHIFT
126582. DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark_MASK
126583. DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark__SHIFT
126584. DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity_MASK
126585. DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity__SHIFT
126586. DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle_MASK
126587. DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle__SHIFT
126588. DPM_TABLE_33__GraphicsLevel_1_UpHyst_MASK
126589. DPM_TABLE_33__GraphicsLevel_1_UpHyst__SHIFT
126590. DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK
126591. DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT
126592. DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK
126593. DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT
126594. DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK
126595. DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT
126596. DPM_TABLE_33__VddcLevelCount_MASK
126597. DPM_TABLE_33__VddcLevelCount__SHIFT
126598. DPM_TABLE_340__LinkLevel_6_Reserved_MASK
126599. DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT
126600. DPM_TABLE_340__MemoryBootLevel_MASK
126601. DPM_TABLE_340__MemoryBootLevel__SHIFT
126602. DPM_TABLE_340__MemoryVoltageChangeEnable_MASK
126603. DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT
126604. DPM_TABLE_340__SamuLevel_1_Frequency_MASK
126605. DPM_TABLE_340__SamuLevel_1_Frequency__SHIFT
126606. DPM_TABLE_340__TemperatureLimitLow_MASK
126607. DPM_TABLE_340__TemperatureLimitLow__SHIFT
126608. DPM_TABLE_340__VceLevel_0_MinVoltage_Phases_MASK
126609. DPM_TABLE_340__VceLevel_0_MinVoltage_Phases__SHIFT
126610. DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx_MASK
126611. DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx__SHIFT
126612. DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc_MASK
126613. DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc__SHIFT
126614. DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci_MASK
126615. DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci__SHIFT
126616. DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK
126617. DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT
126618. DPM_TABLE_341__LinkLevel_7_Padding_MASK
126619. DPM_TABLE_341__LinkLevel_7_Padding__SHIFT
126620. DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK
126621. DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT
126622. DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK
126623. DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT
126624. DPM_TABLE_341__MemoryInterval_MASK
126625. DPM_TABLE_341__MemoryInterval__SHIFT
126626. DPM_TABLE_341__MemoryThermThrottleEnable_MASK
126627. DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT
126628. DPM_TABLE_341__MergedVddci_MASK
126629. DPM_TABLE_341__MergedVddci__SHIFT
126630. DPM_TABLE_341__SamuLevel_1_MinVoltage_Phases_MASK
126631. DPM_TABLE_341__SamuLevel_1_MinVoltage_Phases__SHIFT
126632. DPM_TABLE_341__SamuLevel_1_MinVoltage_VddGfx_MASK
126633. DPM_TABLE_341__SamuLevel_1_MinVoltage_VddGfx__SHIFT
126634. DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddc_MASK
126635. DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddc__SHIFT
126636. DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddci_MASK
126637. DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddci__SHIFT
126638. DPM_TABLE_341__VceLevel_0_Divider_MASK
126639. DPM_TABLE_341__VceLevel_0_Divider__SHIFT
126640. DPM_TABLE_341__VceLevel_0_padding_0_MASK
126641. DPM_TABLE_341__VceLevel_0_padding_0__SHIFT
126642. DPM_TABLE_341__VceLevel_0_padding_1_MASK
126643. DPM_TABLE_341__VceLevel_0_padding_1__SHIFT
126644. DPM_TABLE_341__VceLevel_0_padding_2_MASK
126645. DPM_TABLE_341__VceLevel_0_padding_2__SHIFT
126646. DPM_TABLE_341__padding2_MASK
126647. DPM_TABLE_341__padding2__SHIFT
126648. DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK
126649. DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT
126650. DPM_TABLE_342__PhaseResponseTime_MASK
126651. DPM_TABLE_342__PhaseResponseTime__SHIFT
126652. DPM_TABLE_342__SamuLevel_1_Divider_MASK
126653. DPM_TABLE_342__SamuLevel_1_Divider__SHIFT
126654. DPM_TABLE_342__SamuLevel_1_padding_0_MASK
126655. DPM_TABLE_342__SamuLevel_1_padding_0__SHIFT
126656. DPM_TABLE_342__SamuLevel_1_padding_1_MASK
126657. DPM_TABLE_342__SamuLevel_1_padding_1__SHIFT
126658. DPM_TABLE_342__SamuLevel_1_padding_2_MASK
126659. DPM_TABLE_342__SamuLevel_1_padding_2__SHIFT
126660. DPM_TABLE_342__VceLevel_1_Frequency_MASK
126661. DPM_TABLE_342__VceLevel_1_Frequency__SHIFT
126662. DPM_TABLE_342__VoltageResponseTime_MASK
126663. DPM_TABLE_342__VoltageResponseTime__SHIFT
126664. DPM_TABLE_343__DTEInterval_MASK
126665. DPM_TABLE_343__DTEInterval__SHIFT
126666. DPM_TABLE_343__DTEMode_MASK
126667. DPM_TABLE_343__DTEMode__SHIFT
126668. DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK
126669. DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT
126670. DPM_TABLE_343__PCIeBootLinkLevel_MASK
126671. DPM_TABLE_343__PCIeBootLinkLevel__SHIFT
126672. DPM_TABLE_343__PCIeGenInterval_MASK
126673. DPM_TABLE_343__PCIeGenInterval__SHIFT
126674. DPM_TABLE_343__SamuLevel_2_Frequency_MASK
126675. DPM_TABLE_343__SamuLevel_2_Frequency__SHIFT
126676. DPM_TABLE_343__VceLevel_1_MinVoltage_Phases_MASK
126677. DPM_TABLE_343__VceLevel_1_MinVoltage_Phases__SHIFT
126678. DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx_MASK
126679. DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx__SHIFT
126680. DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc_MASK
126681. DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc__SHIFT
126682. DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci_MASK
126683. DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci__SHIFT
126684. DPM_TABLE_344__AcDcGpio_MASK
126685. DPM_TABLE_344__AcDcGpio__SHIFT
126686. DPM_TABLE_344__LinkLevel_7_Reserved_MASK
126687. DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT
126688. DPM_TABLE_344__SVI2Enable_MASK
126689. DPM_TABLE_344__SVI2Enable__SHIFT
126690. DPM_TABLE_344__SamuLevel_2_MinVoltage_Phases_MASK
126691. DPM_TABLE_344__SamuLevel_2_MinVoltage_Phases__SHIFT
126692. DPM_TABLE_344__SamuLevel_2_MinVoltage_VddGfx_MASK
126693. DPM_TABLE_344__SamuLevel_2_MinVoltage_VddGfx__SHIFT
126694. DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddc_MASK
126695. DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddc__SHIFT
126696. DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddci_MASK
126697. DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddci__SHIFT
126698. DPM_TABLE_344__ThermGpio_MASK
126699. DPM_TABLE_344__ThermGpio__SHIFT
126700. DPM_TABLE_344__VRHotGpio_MASK
126701. DPM_TABLE_344__VRHotGpio__SHIFT
126702. DPM_TABLE_344__VceLevel_1_Divider_MASK
126703. DPM_TABLE_344__VceLevel_1_Divider__SHIFT
126704. DPM_TABLE_344__VceLevel_1_padding_0_MASK
126705. DPM_TABLE_344__VceLevel_1_padding_0__SHIFT
126706. DPM_TABLE_344__VceLevel_1_padding_1_MASK
126707. DPM_TABLE_344__VceLevel_1_padding_1__SHIFT
126708. DPM_TABLE_344__VceLevel_1_padding_2_MASK
126709. DPM_TABLE_344__VceLevel_1_padding_2__SHIFT
126710. DPM_TABLE_345__ACPILevel_Flags_MASK
126711. DPM_TABLE_345__ACPILevel_Flags__SHIFT
126712. DPM_TABLE_345__DisplayCac_MASK
126713. DPM_TABLE_345__DisplayCac__SHIFT
126714. DPM_TABLE_345__SamuLevel_2_Divider_MASK
126715. DPM_TABLE_345__SamuLevel_2_Divider__SHIFT
126716. DPM_TABLE_345__SamuLevel_2_padding_0_MASK
126717. DPM_TABLE_345__SamuLevel_2_padding_0__SHIFT
126718. DPM_TABLE_345__SamuLevel_2_padding_1_MASK
126719. DPM_TABLE_345__SamuLevel_2_padding_1__SHIFT
126720. DPM_TABLE_345__SamuLevel_2_padding_2_MASK
126721. DPM_TABLE_345__SamuLevel_2_padding_2__SHIFT
126722. DPM_TABLE_345__VceLevel_2_Frequency_MASK
126723. DPM_TABLE_345__VceLevel_2_Frequency__SHIFT
126724. DPM_TABLE_346__ACPILevel_MinVddc_MASK
126725. DPM_TABLE_346__ACPILevel_MinVddc__SHIFT
126726. DPM_TABLE_346__MaxPwr_MASK
126727. DPM_TABLE_346__MaxPwr__SHIFT
126728. DPM_TABLE_346__NomPwr_MASK
126729. DPM_TABLE_346__NomPwr__SHIFT
126730. DPM_TABLE_346__SamuLevel_3_Frequency_MASK
126731. DPM_TABLE_346__SamuLevel_3_Frequency__SHIFT
126732. DPM_TABLE_346__VceLevel_2_MinVoltage_Phases_MASK
126733. DPM_TABLE_346__VceLevel_2_MinVoltage_Phases__SHIFT
126734. DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx_MASK
126735. DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx__SHIFT
126736. DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc_MASK
126737. DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc__SHIFT
126738. DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci_MASK
126739. DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci__SHIFT
126740. DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK
126741. DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT
126742. DPM_TABLE_347__FpsHighThreshold_MASK
126743. DPM_TABLE_347__FpsHighThreshold__SHIFT
126744. DPM_TABLE_347__FpsLowThreshold_MASK
126745. DPM_TABLE_347__FpsLowThreshold__SHIFT
126746. DPM_TABLE_347__SamuLevel_3_MinVoltage_Phases_MASK
126747. DPM_TABLE_347__SamuLevel_3_MinVoltage_Phases__SHIFT
126748. DPM_TABLE_347__SamuLevel_3_MinVoltage_VddGfx_MASK
126749. DPM_TABLE_347__SamuLevel_3_MinVoltage_VddGfx__SHIFT
126750. DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddc_MASK
126751. DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddc__SHIFT
126752. DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddci_MASK
126753. DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddci__SHIFT
126754. DPM_TABLE_347__VceLevel_2_Divider_MASK
126755. DPM_TABLE_347__VceLevel_2_Divider__SHIFT
126756. DPM_TABLE_347__VceLevel_2_padding_0_MASK
126757. DPM_TABLE_347__VceLevel_2_padding_0__SHIFT
126758. DPM_TABLE_347__VceLevel_2_padding_1_MASK
126759. DPM_TABLE_347__VceLevel_2_padding_1__SHIFT
126760. DPM_TABLE_347__VceLevel_2_padding_2_MASK
126761. DPM_TABLE_347__VceLevel_2_padding_2__SHIFT
126762. DPM_TABLE_348__ACPILevel_SclkFrequency_MASK
126763. DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT
126764. DPM_TABLE_348__BAPMTI_R_0_0_0_MASK
126765. DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT
126766. DPM_TABLE_348__BAPMTI_R_0_1_0_MASK
126767. DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT
126768. DPM_TABLE_348__SamuLevel_3_Divider_MASK
126769. DPM_TABLE_348__SamuLevel_3_Divider__SHIFT
126770. DPM_TABLE_348__SamuLevel_3_padding_0_MASK
126771. DPM_TABLE_348__SamuLevel_3_padding_0__SHIFT
126772. DPM_TABLE_348__SamuLevel_3_padding_1_MASK
126773. DPM_TABLE_348__SamuLevel_3_padding_1__SHIFT
126774. DPM_TABLE_348__SamuLevel_3_padding_2_MASK
126775. DPM_TABLE_348__SamuLevel_3_padding_2__SHIFT
126776. DPM_TABLE_348__VceLevel_3_Frequency_MASK
126777. DPM_TABLE_348__VceLevel_3_Frequency__SHIFT
126778. DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK
126779. DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT
126780. DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK
126781. DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT
126782. DPM_TABLE_349__ACPILevel_SclkDid_MASK
126783. DPM_TABLE_349__ACPILevel_SclkDid__SHIFT
126784. DPM_TABLE_349__ACPILevel_padding_MASK
126785. DPM_TABLE_349__ACPILevel_padding__SHIFT
126786. DPM_TABLE_349__BAPMTI_R_0_2_0_MASK
126787. DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT
126788. DPM_TABLE_349__BAPMTI_R_1_0_0_MASK
126789. DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT
126790. DPM_TABLE_349__SamuLevel_4_Frequency_MASK
126791. DPM_TABLE_349__SamuLevel_4_Frequency__SHIFT
126792. DPM_TABLE_349__VceLevel_3_MinVoltage_Phases_MASK
126793. DPM_TABLE_349__VceLevel_3_MinVoltage_Phases__SHIFT
126794. DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx_MASK
126795. DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx__SHIFT
126796. DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc_MASK
126797. DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc__SHIFT
126798. DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci_MASK
126799. DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci__SHIFT
126800. DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl_MASK
126801. DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl__SHIFT
126802. DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId_MASK
126803. DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId__SHIFT
126804. DPM_TABLE_34__GraphicsLevel_1_DownHyst_MASK
126805. DPM_TABLE_34__GraphicsLevel_1_DownHyst__SHIFT
126806. DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst_MASK
126807. DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst__SHIFT
126808. DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK
126809. DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT
126810. DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK
126811. DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT
126812. DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK
126813. DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT
126814. DPM_TABLE_34__VddciLevelCount_MASK
126815. DPM_TABLE_34__VddciLevelCount__SHIFT
126816. DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK
126817. DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT
126818. DPM_TABLE_350__BAPMTI_R_1_1_0_MASK
126819. DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT
126820. DPM_TABLE_350__BAPMTI_R_1_2_0_MASK
126821. DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT
126822. DPM_TABLE_350__SamuLevel_4_MinVoltage_Phases_MASK
126823. DPM_TABLE_350__SamuLevel_4_MinVoltage_Phases__SHIFT
126824. DPM_TABLE_350__SamuLevel_4_MinVoltage_VddGfx_MASK
126825. DPM_TABLE_350__SamuLevel_4_MinVoltage_VddGfx__SHIFT
126826. DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddc_MASK
126827. DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddc__SHIFT
126828. DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddci_MASK
126829. DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddci__SHIFT
126830. DPM_TABLE_350__VceLevel_3_Divider_MASK
126831. DPM_TABLE_350__VceLevel_3_Divider__SHIFT
126832. DPM_TABLE_350__VceLevel_3_padding_0_MASK
126833. DPM_TABLE_350__VceLevel_3_padding_0__SHIFT
126834. DPM_TABLE_350__VceLevel_3_padding_1_MASK
126835. DPM_TABLE_350__VceLevel_3_padding_1__SHIFT
126836. DPM_TABLE_350__VceLevel_3_padding_2_MASK
126837. DPM_TABLE_350__VceLevel_3_padding_2__SHIFT
126838. DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK
126839. DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT
126840. DPM_TABLE_351__BAPMTI_R_2_0_0_MASK
126841. DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT
126842. DPM_TABLE_351__BAPMTI_R_2_1_0_MASK
126843. DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT
126844. DPM_TABLE_351__SamuLevel_4_Divider_MASK
126845. DPM_TABLE_351__SamuLevel_4_Divider__SHIFT
126846. DPM_TABLE_351__SamuLevel_4_padding_0_MASK
126847. DPM_TABLE_351__SamuLevel_4_padding_0__SHIFT
126848. DPM_TABLE_351__SamuLevel_4_padding_1_MASK
126849. DPM_TABLE_351__SamuLevel_4_padding_1__SHIFT
126850. DPM_TABLE_351__SamuLevel_4_padding_2_MASK
126851. DPM_TABLE_351__SamuLevel_4_padding_2__SHIFT
126852. DPM_TABLE_351__VceLevel_4_Frequency_MASK
126853. DPM_TABLE_351__VceLevel_4_Frequency__SHIFT
126854. DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK
126855. DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT
126856. DPM_TABLE_352__BAPMTI_R_2_2_0_MASK
126857. DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT
126858. DPM_TABLE_352__BAPMTI_R_3_0_0_MASK
126859. DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT
126860. DPM_TABLE_352__SamuLevel_5_Frequency_MASK
126861. DPM_TABLE_352__SamuLevel_5_Frequency__SHIFT
126862. DPM_TABLE_352__VceLevel_4_MinVoltage_Phases_MASK
126863. DPM_TABLE_352__VceLevel_4_MinVoltage_Phases__SHIFT
126864. DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx_MASK
126865. DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx__SHIFT
126866. DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc_MASK
126867. DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc__SHIFT
126868. DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci_MASK
126869. DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci__SHIFT
126870. DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK
126871. DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT
126872. DPM_TABLE_353__BAPMTI_R_3_1_0_MASK
126873. DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT
126874. DPM_TABLE_353__BAPMTI_R_3_2_0_MASK
126875. DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT
126876. DPM_TABLE_353__SamuLevel_5_MinVoltage_Phases_MASK
126877. DPM_TABLE_353__SamuLevel_5_MinVoltage_Phases__SHIFT
126878. DPM_TABLE_353__SamuLevel_5_MinVoltage_VddGfx_MASK
126879. DPM_TABLE_353__SamuLevel_5_MinVoltage_VddGfx__SHIFT
126880. DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddc_MASK
126881. DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddc__SHIFT
126882. DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddci_MASK
126883. DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddci__SHIFT
126884. DPM_TABLE_353__VceLevel_4_Divider_MASK
126885. DPM_TABLE_353__VceLevel_4_Divider__SHIFT
126886. DPM_TABLE_353__VceLevel_4_padding_0_MASK
126887. DPM_TABLE_353__VceLevel_4_padding_0__SHIFT
126888. DPM_TABLE_353__VceLevel_4_padding_1_MASK
126889. DPM_TABLE_353__VceLevel_4_padding_1__SHIFT
126890. DPM_TABLE_353__VceLevel_4_padding_2_MASK
126891. DPM_TABLE_353__VceLevel_4_padding_2__SHIFT
126892. DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK
126893. DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT
126894. DPM_TABLE_354__BAPMTI_R_4_0_0_MASK
126895. DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT
126896. DPM_TABLE_354__BAPMTI_R_4_1_0_MASK
126897. DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT
126898. DPM_TABLE_354__SamuLevel_5_Divider_MASK
126899. DPM_TABLE_354__SamuLevel_5_Divider__SHIFT
126900. DPM_TABLE_354__SamuLevel_5_padding_0_MASK
126901. DPM_TABLE_354__SamuLevel_5_padding_0__SHIFT
126902. DPM_TABLE_354__SamuLevel_5_padding_1_MASK
126903. DPM_TABLE_354__SamuLevel_5_padding_1__SHIFT
126904. DPM_TABLE_354__SamuLevel_5_padding_2_MASK
126905. DPM_TABLE_354__SamuLevel_5_padding_2__SHIFT
126906. DPM_TABLE_354__VceLevel_5_Frequency_MASK
126907. DPM_TABLE_354__VceLevel_5_Frequency__SHIFT
126908. DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK
126909. DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT
126910. DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK
126911. DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT
126912. DPM_TABLE_355__BAPMTI_R_4_2_0_MASK
126913. DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT
126914. DPM_TABLE_355__SamuLevel_6_Frequency_MASK
126915. DPM_TABLE_355__SamuLevel_6_Frequency__SHIFT
126916. DPM_TABLE_355__VceLevel_5_MinVoltage_Phases_MASK
126917. DPM_TABLE_355__VceLevel_5_MinVoltage_Phases__SHIFT
126918. DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx_MASK
126919. DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx__SHIFT
126920. DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc_MASK
126921. DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc__SHIFT
126922. DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci_MASK
126923. DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci__SHIFT
126924. DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK
126925. DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT
126926. DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK
126927. DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT
126928. DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK
126929. DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT
126930. DPM_TABLE_356__SamuLevel_6_MinVoltage_Phases_MASK
126931. DPM_TABLE_356__SamuLevel_6_MinVoltage_Phases__SHIFT
126932. DPM_TABLE_356__SamuLevel_6_MinVoltage_VddGfx_MASK
126933. DPM_TABLE_356__SamuLevel_6_MinVoltage_VddGfx__SHIFT
126934. DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddc_MASK
126935. DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddc__SHIFT
126936. DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddci_MASK
126937. DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddci__SHIFT
126938. DPM_TABLE_356__VceLevel_5_Divider_MASK
126939. DPM_TABLE_356__VceLevel_5_Divider__SHIFT
126940. DPM_TABLE_356__VceLevel_5_padding_0_MASK
126941. DPM_TABLE_356__VceLevel_5_padding_0__SHIFT
126942. DPM_TABLE_356__VceLevel_5_padding_1_MASK
126943. DPM_TABLE_356__VceLevel_5_padding_1__SHIFT
126944. DPM_TABLE_356__VceLevel_5_padding_2_MASK
126945. DPM_TABLE_356__VceLevel_5_padding_2__SHIFT
126946. DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK
126947. DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT
126948. DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK
126949. DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT
126950. DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK
126951. DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT
126952. DPM_TABLE_357__SamuLevel_6_Divider_MASK
126953. DPM_TABLE_357__SamuLevel_6_Divider__SHIFT
126954. DPM_TABLE_357__SamuLevel_6_padding_0_MASK
126955. DPM_TABLE_357__SamuLevel_6_padding_0__SHIFT
126956. DPM_TABLE_357__SamuLevel_6_padding_1_MASK
126957. DPM_TABLE_357__SamuLevel_6_padding_1__SHIFT
126958. DPM_TABLE_357__SamuLevel_6_padding_2_MASK
126959. DPM_TABLE_357__SamuLevel_6_padding_2__SHIFT
126960. DPM_TABLE_357__VceLevel_6_Frequency_MASK
126961. DPM_TABLE_357__VceLevel_6_Frequency__SHIFT
126962. DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK
126963. DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT
126964. DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK
126965. DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT
126966. DPM_TABLE_358__SamuLevel_7_Frequency_MASK
126967. DPM_TABLE_358__SamuLevel_7_Frequency__SHIFT
126968. DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK
126969. DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT
126970. DPM_TABLE_358__VceLevel_6_MinVoltage_Phases_MASK
126971. DPM_TABLE_358__VceLevel_6_MinVoltage_Phases__SHIFT
126972. DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx_MASK
126973. DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx__SHIFT
126974. DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc_MASK
126975. DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc__SHIFT
126976. DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci_MASK
126977. DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci__SHIFT
126978. DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK
126979. DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT
126980. DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK
126981. DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT
126982. DPM_TABLE_359__SamuLevel_7_MinVoltage_Phases_MASK
126983. DPM_TABLE_359__SamuLevel_7_MinVoltage_Phases__SHIFT
126984. DPM_TABLE_359__SamuLevel_7_MinVoltage_VddGfx_MASK
126985. DPM_TABLE_359__SamuLevel_7_MinVoltage_VddGfx__SHIFT
126986. DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddc_MASK
126987. DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddc__SHIFT
126988. DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddci_MASK
126989. DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddci__SHIFT
126990. DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK
126991. DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT
126992. DPM_TABLE_359__VceLevel_6_Divider_MASK
126993. DPM_TABLE_359__VceLevel_6_Divider__SHIFT
126994. DPM_TABLE_359__VceLevel_6_padding_0_MASK
126995. DPM_TABLE_359__VceLevel_6_padding_0__SHIFT
126996. DPM_TABLE_359__VceLevel_6_padding_1_MASK
126997. DPM_TABLE_359__VceLevel_6_padding_1__SHIFT
126998. DPM_TABLE_359__VceLevel_6_padding_2_MASK
126999. DPM_TABLE_359__VceLevel_6_padding_2__SHIFT
127000. DPM_TABLE_35__GraphicsLevel_1_reserved_MASK
127001. DPM_TABLE_35__GraphicsLevel_1_reserved__SHIFT
127002. DPM_TABLE_35__MvddLevelCount_MASK
127003. DPM_TABLE_35__MvddLevelCount__SHIFT
127004. DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK
127005. DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT
127006. DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK
127007. DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT
127008. DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK
127009. DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT
127010. DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK
127011. DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT
127012. DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK
127013. DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT
127014. DPM_TABLE_360__SamuLevel_7_Divider_MASK
127015. DPM_TABLE_360__SamuLevel_7_Divider__SHIFT
127016. DPM_TABLE_360__SamuLevel_7_padding_0_MASK
127017. DPM_TABLE_360__SamuLevel_7_padding_0__SHIFT
127018. DPM_TABLE_360__SamuLevel_7_padding_1_MASK
127019. DPM_TABLE_360__SamuLevel_7_padding_1__SHIFT
127020. DPM_TABLE_360__SamuLevel_7_padding_2_MASK
127021. DPM_TABLE_360__SamuLevel_7_padding_2__SHIFT
127022. DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK
127023. DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT
127024. DPM_TABLE_360__UvdLevel_0_MinVddc_MASK
127025. DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT
127026. DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK
127027. DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT
127028. DPM_TABLE_360__VceLevel_7_Frequency_MASK
127029. DPM_TABLE_360__VceLevel_7_Frequency__SHIFT
127030. DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK
127031. DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT
127032. DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK
127033. DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT
127034. DPM_TABLE_361__Ulv_CcPwrDynRm_MASK
127035. DPM_TABLE_361__Ulv_CcPwrDynRm__SHIFT
127036. DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK
127037. DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT
127038. DPM_TABLE_361__UvdLevel_0_padding_0_MASK
127039. DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT
127040. DPM_TABLE_361__UvdLevel_0_padding_1_MASK
127041. DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT
127042. DPM_TABLE_361__UvdLevel_0_padding_2_MASK
127043. DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT
127044. DPM_TABLE_361__VceLevel_7_MinVoltage_Phases_MASK
127045. DPM_TABLE_361__VceLevel_7_MinVoltage_Phases__SHIFT
127046. DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx_MASK
127047. DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx__SHIFT
127048. DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc_MASK
127049. DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc__SHIFT
127050. DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci_MASK
127051. DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci__SHIFT
127052. DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK
127053. DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT
127054. DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK
127055. DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT
127056. DPM_TABLE_362__Ulv_CcPwrDynRm1_MASK
127057. DPM_TABLE_362__Ulv_CcPwrDynRm1__SHIFT
127058. DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK
127059. DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT
127060. DPM_TABLE_362__VceLevel_7_Divider_MASK
127061. DPM_TABLE_362__VceLevel_7_Divider__SHIFT
127062. DPM_TABLE_362__VceLevel_7_padding_0_MASK
127063. DPM_TABLE_362__VceLevel_7_padding_0__SHIFT
127064. DPM_TABLE_362__VceLevel_7_padding_1_MASK
127065. DPM_TABLE_362__VceLevel_7_padding_1__SHIFT
127066. DPM_TABLE_362__VceLevel_7_padding_2_MASK
127067. DPM_TABLE_362__VceLevel_7_padding_2__SHIFT
127068. DPM_TABLE_363__AcpLevel_0_Frequency_MASK
127069. DPM_TABLE_363__AcpLevel_0_Frequency__SHIFT
127070. DPM_TABLE_363__DTEAmbientTempBase_MASK
127071. DPM_TABLE_363__DTEAmbientTempBase__SHIFT
127072. DPM_TABLE_363__DTETjOffset_MASK
127073. DPM_TABLE_363__DTETjOffset__SHIFT
127074. DPM_TABLE_363__GpuTjHyst_MASK
127075. DPM_TABLE_363__GpuTjHyst__SHIFT
127076. DPM_TABLE_363__GpuTjMax_MASK
127077. DPM_TABLE_363__GpuTjMax__SHIFT
127078. DPM_TABLE_363__Ulv_VddcOffsetVid_MASK
127079. DPM_TABLE_363__Ulv_VddcOffsetVid__SHIFT
127080. DPM_TABLE_363__Ulv_VddcOffset_MASK
127081. DPM_TABLE_363__Ulv_VddcOffset__SHIFT
127082. DPM_TABLE_363__Ulv_VddcPhase_MASK
127083. DPM_TABLE_363__Ulv_VddcPhase__SHIFT
127084. DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK
127085. DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT
127086. DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases_MASK
127087. DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases__SHIFT
127088. DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx_MASK
127089. DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx__SHIFT
127090. DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc_MASK
127091. DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc__SHIFT
127092. DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci_MASK
127093. DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci__SHIFT
127094. DPM_TABLE_364__BootVddc_MASK
127095. DPM_TABLE_364__BootVddc__SHIFT
127096. DPM_TABLE_364__BootVddci_MASK
127097. DPM_TABLE_364__BootVddci__SHIFT
127098. DPM_TABLE_364__Ulv_Reserved_MASK
127099. DPM_TABLE_364__Ulv_Reserved__SHIFT
127100. DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK
127101. DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT
127102. DPM_TABLE_364__UvdLevel_1_MinVddc_MASK
127103. DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT
127104. DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK
127105. DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT
127106. DPM_TABLE_365__AcpLevel_0_Divider_MASK
127107. DPM_TABLE_365__AcpLevel_0_Divider__SHIFT
127108. DPM_TABLE_365__AcpLevel_0_padding_0_MASK
127109. DPM_TABLE_365__AcpLevel_0_padding_0__SHIFT
127110. DPM_TABLE_365__AcpLevel_0_padding_1_MASK
127111. DPM_TABLE_365__AcpLevel_0_padding_1__SHIFT
127112. DPM_TABLE_365__AcpLevel_0_padding_2_MASK
127113. DPM_TABLE_365__AcpLevel_0_padding_2__SHIFT
127114. DPM_TABLE_365__BootMVdd_MASK
127115. DPM_TABLE_365__BootMVdd__SHIFT
127116. DPM_TABLE_365__SclkStepSize_MASK
127117. DPM_TABLE_365__SclkStepSize__SHIFT
127118. DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK
127119. DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT
127120. DPM_TABLE_365__UvdLevel_1_padding_0_MASK
127121. DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT
127122. DPM_TABLE_365__UvdLevel_1_padding_1_MASK
127123. DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT
127124. DPM_TABLE_365__UvdLevel_1_padding_2_MASK
127125. DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT
127126. DPM_TABLE_365__padding_MASK
127127. DPM_TABLE_365__padding__SHIFT
127128. DPM_TABLE_366__AcpLevel_1_Frequency_MASK
127129. DPM_TABLE_366__AcpLevel_1_Frequency__SHIFT
127130. DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK
127131. DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT
127132. DPM_TABLE_366__Smio_0_MASK
127133. DPM_TABLE_366__Smio_0__SHIFT
127134. DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK
127135. DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT
127136. DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases_MASK
127137. DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases__SHIFT
127138. DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx_MASK
127139. DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx__SHIFT
127140. DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc_MASK
127141. DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc__SHIFT
127142. DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci_MASK
127143. DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci__SHIFT
127144. DPM_TABLE_367__LowSclkInterruptThreshold_MASK
127145. DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT
127146. DPM_TABLE_367__Smio_1_MASK
127147. DPM_TABLE_367__Smio_1__SHIFT
127148. DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK
127149. DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT
127150. DPM_TABLE_368__AcpLevel_1_Divider_MASK
127151. DPM_TABLE_368__AcpLevel_1_Divider__SHIFT
127152. DPM_TABLE_368__AcpLevel_1_padding_0_MASK
127153. DPM_TABLE_368__AcpLevel_1_padding_0__SHIFT
127154. DPM_TABLE_368__AcpLevel_1_padding_1_MASK
127155. DPM_TABLE_368__AcpLevel_1_padding_1__SHIFT
127156. DPM_TABLE_368__AcpLevel_1_padding_2_MASK
127157. DPM_TABLE_368__AcpLevel_1_padding_2__SHIFT
127158. DPM_TABLE_368__Smio_2_MASK
127159. DPM_TABLE_368__Smio_2__SHIFT
127160. DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK
127161. DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT
127162. DPM_TABLE_368__UvdLevel_2_MinVddc_MASK
127163. DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT
127164. DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK
127165. DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT
127166. DPM_TABLE_368__VddGfxReChkWait_MASK
127167. DPM_TABLE_368__VddGfxReChkWait__SHIFT
127168. DPM_TABLE_369__AcpLevel_2_Frequency_MASK
127169. DPM_TABLE_369__AcpLevel_2_Frequency__SHIFT
127170. DPM_TABLE_369__PPM_PkgPwrLimit_MASK
127171. DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT
127172. DPM_TABLE_369__PPM_TemperatureLimit_MASK
127173. DPM_TABLE_369__PPM_TemperatureLimit__SHIFT
127174. DPM_TABLE_369__Smio_3_MASK
127175. DPM_TABLE_369__Smio_3__SHIFT
127176. DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK
127177. DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT
127178. DPM_TABLE_369__UvdLevel_2_padding_0_MASK
127179. DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT
127180. DPM_TABLE_369__UvdLevel_2_padding_1_MASK
127181. DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT
127182. DPM_TABLE_369__UvdLevel_2_padding_2_MASK
127183. DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT
127184. DPM_TABLE_36__GraphicsLevel_2_MinVddNb_MASK
127185. DPM_TABLE_36__GraphicsLevel_2_MinVddNb__SHIFT
127186. DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK
127187. DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT
127188. DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK
127189. DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT
127190. DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK
127191. DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT
127192. DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK
127193. DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT
127194. DPM_TABLE_36__VddcLevel_0_Voltage_MASK
127195. DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT
127196. DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases_MASK
127197. DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases__SHIFT
127198. DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx_MASK
127199. DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx__SHIFT
127200. DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc_MASK
127201. DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc__SHIFT
127202. DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci_MASK
127203. DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci__SHIFT
127204. DPM_TABLE_370__DefaultTdp_MASK
127205. DPM_TABLE_370__DefaultTdp__SHIFT
127206. DPM_TABLE_370__Smio_4_MASK
127207. DPM_TABLE_370__Smio_4__SHIFT
127208. DPM_TABLE_370__TargetTdp_MASK
127209. DPM_TABLE_370__TargetTdp__SHIFT
127210. DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK
127211. DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT
127212. DPM_TABLE_371__AcpLevel_2_Divider_MASK
127213. DPM_TABLE_371__AcpLevel_2_Divider__SHIFT
127214. DPM_TABLE_371__AcpLevel_2_padding_0_MASK
127215. DPM_TABLE_371__AcpLevel_2_padding_0__SHIFT
127216. DPM_TABLE_371__AcpLevel_2_padding_1_MASK
127217. DPM_TABLE_371__AcpLevel_2_padding_1__SHIFT
127218. DPM_TABLE_371__AcpLevel_2_padding_2_MASK
127219. DPM_TABLE_371__AcpLevel_2_padding_2__SHIFT
127220. DPM_TABLE_371__Smio_5_MASK
127221. DPM_TABLE_371__Smio_5__SHIFT
127222. DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK
127223. DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT
127224. DPM_TABLE_372__AcpLevel_3_Frequency_MASK
127225. DPM_TABLE_372__AcpLevel_3_Frequency__SHIFT
127226. DPM_TABLE_372__Smio_6_MASK
127227. DPM_TABLE_372__Smio_6__SHIFT
127228. DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK
127229. DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT
127230. DPM_TABLE_372__UvdLevel_3_MinVddc_MASK
127231. DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT
127232. DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK
127233. DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT
127234. DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases_MASK
127235. DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases__SHIFT
127236. DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx_MASK
127237. DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx__SHIFT
127238. DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc_MASK
127239. DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc__SHIFT
127240. DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci_MASK
127241. DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci__SHIFT
127242. DPM_TABLE_373__Smio_7_MASK
127243. DPM_TABLE_373__Smio_7__SHIFT
127244. DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK
127245. DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT
127246. DPM_TABLE_373__UvdLevel_3_padding_0_MASK
127247. DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT
127248. DPM_TABLE_373__UvdLevel_3_padding_1_MASK
127249. DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT
127250. DPM_TABLE_373__UvdLevel_3_padding_2_MASK
127251. DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT
127252. DPM_TABLE_374__AcpLevel_3_Divider_MASK
127253. DPM_TABLE_374__AcpLevel_3_Divider__SHIFT
127254. DPM_TABLE_374__AcpLevel_3_padding_0_MASK
127255. DPM_TABLE_374__AcpLevel_3_padding_0__SHIFT
127256. DPM_TABLE_374__AcpLevel_3_padding_1_MASK
127257. DPM_TABLE_374__AcpLevel_3_padding_1__SHIFT
127258. DPM_TABLE_374__AcpLevel_3_padding_2_MASK
127259. DPM_TABLE_374__AcpLevel_3_padding_2__SHIFT
127260. DPM_TABLE_374__Smio_8_MASK
127261. DPM_TABLE_374__Smio_8__SHIFT
127262. DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK
127263. DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT
127264. DPM_TABLE_375__AcpLevel_4_Frequency_MASK
127265. DPM_TABLE_375__AcpLevel_4_Frequency__SHIFT
127266. DPM_TABLE_375__Smio_9_MASK
127267. DPM_TABLE_375__Smio_9__SHIFT
127268. DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK
127269. DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT
127270. DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases_MASK
127271. DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases__SHIFT
127272. DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx_MASK
127273. DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx__SHIFT
127274. DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc_MASK
127275. DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc__SHIFT
127276. DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci_MASK
127277. DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci__SHIFT
127278. DPM_TABLE_376__Smio_10_MASK
127279. DPM_TABLE_376__Smio_10__SHIFT
127280. DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK
127281. DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT
127282. DPM_TABLE_376__UvdLevel_4_MinVddc_MASK
127283. DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT
127284. DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK
127285. DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT
127286. DPM_TABLE_377__AcpLevel_4_Divider_MASK
127287. DPM_TABLE_377__AcpLevel_4_Divider__SHIFT
127288. DPM_TABLE_377__AcpLevel_4_padding_0_MASK
127289. DPM_TABLE_377__AcpLevel_4_padding_0__SHIFT
127290. DPM_TABLE_377__AcpLevel_4_padding_1_MASK
127291. DPM_TABLE_377__AcpLevel_4_padding_1__SHIFT
127292. DPM_TABLE_377__AcpLevel_4_padding_2_MASK
127293. DPM_TABLE_377__AcpLevel_4_padding_2__SHIFT
127294. DPM_TABLE_377__Smio_11_MASK
127295. DPM_TABLE_377__Smio_11__SHIFT
127296. DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK
127297. DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT
127298. DPM_TABLE_377__UvdLevel_4_padding_0_MASK
127299. DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT
127300. DPM_TABLE_377__UvdLevel_4_padding_1_MASK
127301. DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT
127302. DPM_TABLE_377__UvdLevel_4_padding_2_MASK
127303. DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT
127304. DPM_TABLE_378__AcpLevel_5_Frequency_MASK
127305. DPM_TABLE_378__AcpLevel_5_Frequency__SHIFT
127306. DPM_TABLE_378__Smio_12_MASK
127307. DPM_TABLE_378__Smio_12__SHIFT
127308. DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK
127309. DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT
127310. DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases_MASK
127311. DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases__SHIFT
127312. DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx_MASK
127313. DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx__SHIFT
127314. DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc_MASK
127315. DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc__SHIFT
127316. DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci_MASK
127317. DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci__SHIFT
127318. DPM_TABLE_379__Smio_13_MASK
127319. DPM_TABLE_379__Smio_13__SHIFT
127320. DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK
127321. DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT
127322. DPM_TABLE_37__GraphicsLevel_2_SclkFrequency_MASK
127323. DPM_TABLE_37__GraphicsLevel_2_SclkFrequency__SHIFT
127324. DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK
127325. DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT
127326. DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK
127327. DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT
127328. DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK
127329. DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT
127330. DPM_TABLE_37__VddcLevel_0_Smio_MASK
127331. DPM_TABLE_37__VddcLevel_0_Smio__SHIFT
127332. DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK
127333. DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT
127334. DPM_TABLE_37__VddcLevel_0_padding_MASK
127335. DPM_TABLE_37__VddcLevel_0_padding__SHIFT
127336. DPM_TABLE_380__AcpLevel_5_Divider_MASK
127337. DPM_TABLE_380__AcpLevel_5_Divider__SHIFT
127338. DPM_TABLE_380__AcpLevel_5_padding_0_MASK
127339. DPM_TABLE_380__AcpLevel_5_padding_0__SHIFT
127340. DPM_TABLE_380__AcpLevel_5_padding_1_MASK
127341. DPM_TABLE_380__AcpLevel_5_padding_1__SHIFT
127342. DPM_TABLE_380__AcpLevel_5_padding_2_MASK
127343. DPM_TABLE_380__AcpLevel_5_padding_2__SHIFT
127344. DPM_TABLE_380__Smio_14_MASK
127345. DPM_TABLE_380__Smio_14__SHIFT
127346. DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK
127347. DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT
127348. DPM_TABLE_380__UvdLevel_5_MinVddc_MASK
127349. DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT
127350. DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK
127351. DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT
127352. DPM_TABLE_381__AcpLevel_6_Frequency_MASK
127353. DPM_TABLE_381__AcpLevel_6_Frequency__SHIFT
127354. DPM_TABLE_381__Smio_15_MASK
127355. DPM_TABLE_381__Smio_15__SHIFT
127356. DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK
127357. DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT
127358. DPM_TABLE_381__UvdLevel_5_padding_0_MASK
127359. DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT
127360. DPM_TABLE_381__UvdLevel_5_padding_1_MASK
127361. DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT
127362. DPM_TABLE_381__UvdLevel_5_padding_2_MASK
127363. DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT
127364. DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases_MASK
127365. DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases__SHIFT
127366. DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx_MASK
127367. DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx__SHIFT
127368. DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc_MASK
127369. DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc__SHIFT
127370. DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci_MASK
127371. DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci__SHIFT
127372. DPM_TABLE_382__Smio_16_MASK
127373. DPM_TABLE_382__Smio_16__SHIFT
127374. DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK
127375. DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT
127376. DPM_TABLE_383__AcpLevel_6_Divider_MASK
127377. DPM_TABLE_383__AcpLevel_6_Divider__SHIFT
127378. DPM_TABLE_383__AcpLevel_6_padding_0_MASK
127379. DPM_TABLE_383__AcpLevel_6_padding_0__SHIFT
127380. DPM_TABLE_383__AcpLevel_6_padding_1_MASK
127381. DPM_TABLE_383__AcpLevel_6_padding_1__SHIFT
127382. DPM_TABLE_383__AcpLevel_6_padding_2_MASK
127383. DPM_TABLE_383__AcpLevel_6_padding_2__SHIFT
127384. DPM_TABLE_383__Smio_17_MASK
127385. DPM_TABLE_383__Smio_17__SHIFT
127386. DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK
127387. DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT
127388. DPM_TABLE_384__AcpLevel_7_Frequency_MASK
127389. DPM_TABLE_384__AcpLevel_7_Frequency__SHIFT
127390. DPM_TABLE_384__Smio_18_MASK
127391. DPM_TABLE_384__Smio_18__SHIFT
127392. DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK
127393. DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT
127394. DPM_TABLE_384__UvdLevel_6_MinVddc_MASK
127395. DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT
127396. DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK
127397. DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT
127398. DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases_MASK
127399. DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases__SHIFT
127400. DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx_MASK
127401. DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx__SHIFT
127402. DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc_MASK
127403. DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc__SHIFT
127404. DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci_MASK
127405. DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci__SHIFT
127406. DPM_TABLE_385__Smio_19_MASK
127407. DPM_TABLE_385__Smio_19__SHIFT
127408. DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK
127409. DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT
127410. DPM_TABLE_385__UvdLevel_6_padding_0_MASK
127411. DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT
127412. DPM_TABLE_385__UvdLevel_6_padding_1_MASK
127413. DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT
127414. DPM_TABLE_385__UvdLevel_6_padding_2_MASK
127415. DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT
127416. DPM_TABLE_386__AcpLevel_7_Divider_MASK
127417. DPM_TABLE_386__AcpLevel_7_Divider__SHIFT
127418. DPM_TABLE_386__AcpLevel_7_padding_0_MASK
127419. DPM_TABLE_386__AcpLevel_7_padding_0__SHIFT
127420. DPM_TABLE_386__AcpLevel_7_padding_1_MASK
127421. DPM_TABLE_386__AcpLevel_7_padding_1__SHIFT
127422. DPM_TABLE_386__AcpLevel_7_padding_2_MASK
127423. DPM_TABLE_386__AcpLevel_7_padding_2__SHIFT
127424. DPM_TABLE_386__Smio_20_MASK
127425. DPM_TABLE_386__Smio_20__SHIFT
127426. DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK
127427. DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT
127428. DPM_TABLE_387__SamuLevel_0_Frequency_MASK
127429. DPM_TABLE_387__SamuLevel_0_Frequency__SHIFT
127430. DPM_TABLE_387__Smio_21_MASK
127431. DPM_TABLE_387__Smio_21__SHIFT
127432. DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK
127433. DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT
127434. DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases_MASK
127435. DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases__SHIFT
127436. DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx_MASK
127437. DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx__SHIFT
127438. DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc_MASK
127439. DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc__SHIFT
127440. DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci_MASK
127441. DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci__SHIFT
127442. DPM_TABLE_388__Smio_22_MASK
127443. DPM_TABLE_388__Smio_22__SHIFT
127444. DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK
127445. DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT
127446. DPM_TABLE_388__UvdLevel_7_MinVddc_MASK
127447. DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT
127448. DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK
127449. DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT
127450. DPM_TABLE_389__SamuLevel_0_Divider_MASK
127451. DPM_TABLE_389__SamuLevel_0_Divider__SHIFT
127452. DPM_TABLE_389__SamuLevel_0_padding_0_MASK
127453. DPM_TABLE_389__SamuLevel_0_padding_0__SHIFT
127454. DPM_TABLE_389__SamuLevel_0_padding_1_MASK
127455. DPM_TABLE_389__SamuLevel_0_padding_1__SHIFT
127456. DPM_TABLE_389__SamuLevel_0_padding_2_MASK
127457. DPM_TABLE_389__SamuLevel_0_padding_2__SHIFT
127458. DPM_TABLE_389__Smio_23_MASK
127459. DPM_TABLE_389__Smio_23__SHIFT
127460. DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK
127461. DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT
127462. DPM_TABLE_389__UvdLevel_7_padding_0_MASK
127463. DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT
127464. DPM_TABLE_389__UvdLevel_7_padding_1_MASK
127465. DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT
127466. DPM_TABLE_389__UvdLevel_7_padding_2_MASK
127467. DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT
127468. DPM_TABLE_38__GraphicsLevel_2_ActivityLevel_MASK
127469. DPM_TABLE_38__GraphicsLevel_2_ActivityLevel__SHIFT
127470. DPM_TABLE_38__GraphicsLevel_2_VidOffset_MASK
127471. DPM_TABLE_38__GraphicsLevel_2_VidOffset__SHIFT
127472. DPM_TABLE_38__GraphicsLevel_2_Vid_MASK
127473. DPM_TABLE_38__GraphicsLevel_2_Vid__SHIFT
127474. DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK
127475. DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT
127476. DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK
127477. DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT
127478. DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK
127479. DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT
127480. DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK
127481. DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT
127482. DPM_TABLE_38__VddcLevel_1_Voltage_MASK
127483. DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT
127484. DPM_TABLE_390__SamuLevel_1_Frequency_MASK
127485. DPM_TABLE_390__SamuLevel_1_Frequency__SHIFT
127486. DPM_TABLE_390__Smio_24_MASK
127487. DPM_TABLE_390__Smio_24__SHIFT
127488. DPM_TABLE_390__VceLevel_0_Frequency_MASK
127489. DPM_TABLE_390__VceLevel_0_Frequency__SHIFT
127490. DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases_MASK
127491. DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases__SHIFT
127492. DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx_MASK
127493. DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx__SHIFT
127494. DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc_MASK
127495. DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc__SHIFT
127496. DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci_MASK
127497. DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci__SHIFT
127498. DPM_TABLE_391__Smio_25_MASK
127499. DPM_TABLE_391__Smio_25__SHIFT
127500. DPM_TABLE_391__VceLevel_0_Divider_MASK
127501. DPM_TABLE_391__VceLevel_0_Divider__SHIFT
127502. DPM_TABLE_391__VceLevel_0_MinPhases_MASK
127503. DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT
127504. DPM_TABLE_391__VceLevel_0_MinVoltage_MASK
127505. DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT
127506. DPM_TABLE_392__SamuLevel_1_Divider_MASK
127507. DPM_TABLE_392__SamuLevel_1_Divider__SHIFT
127508. DPM_TABLE_392__SamuLevel_1_padding_0_MASK
127509. DPM_TABLE_392__SamuLevel_1_padding_0__SHIFT
127510. DPM_TABLE_392__SamuLevel_1_padding_1_MASK
127511. DPM_TABLE_392__SamuLevel_1_padding_1__SHIFT
127512. DPM_TABLE_392__SamuLevel_1_padding_2_MASK
127513. DPM_TABLE_392__SamuLevel_1_padding_2__SHIFT
127514. DPM_TABLE_392__Smio_26_MASK
127515. DPM_TABLE_392__Smio_26__SHIFT
127516. DPM_TABLE_392__VceLevel_1_Frequency_MASK
127517. DPM_TABLE_392__VceLevel_1_Frequency__SHIFT
127518. DPM_TABLE_393__SamuLevel_2_Frequency_MASK
127519. DPM_TABLE_393__SamuLevel_2_Frequency__SHIFT
127520. DPM_TABLE_393__Smio_27_MASK
127521. DPM_TABLE_393__Smio_27__SHIFT
127522. DPM_TABLE_393__VceLevel_1_Divider_MASK
127523. DPM_TABLE_393__VceLevel_1_Divider__SHIFT
127524. DPM_TABLE_393__VceLevel_1_MinPhases_MASK
127525. DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT
127526. DPM_TABLE_393__VceLevel_1_MinVoltage_MASK
127527. DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT
127528. DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases_MASK
127529. DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases__SHIFT
127530. DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx_MASK
127531. DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx__SHIFT
127532. DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc_MASK
127533. DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc__SHIFT
127534. DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci_MASK
127535. DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci__SHIFT
127536. DPM_TABLE_394__Smio_28_MASK
127537. DPM_TABLE_394__Smio_28__SHIFT
127538. DPM_TABLE_394__VceLevel_2_Frequency_MASK
127539. DPM_TABLE_394__VceLevel_2_Frequency__SHIFT
127540. DPM_TABLE_395__SamuLevel_2_Divider_MASK
127541. DPM_TABLE_395__SamuLevel_2_Divider__SHIFT
127542. DPM_TABLE_395__SamuLevel_2_padding_0_MASK
127543. DPM_TABLE_395__SamuLevel_2_padding_0__SHIFT
127544. DPM_TABLE_395__SamuLevel_2_padding_1_MASK
127545. DPM_TABLE_395__SamuLevel_2_padding_1__SHIFT
127546. DPM_TABLE_395__SamuLevel_2_padding_2_MASK
127547. DPM_TABLE_395__SamuLevel_2_padding_2__SHIFT
127548. DPM_TABLE_395__Smio_29_MASK
127549. DPM_TABLE_395__Smio_29__SHIFT
127550. DPM_TABLE_395__VceLevel_2_Divider_MASK
127551. DPM_TABLE_395__VceLevel_2_Divider__SHIFT
127552. DPM_TABLE_395__VceLevel_2_MinPhases_MASK
127553. DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT
127554. DPM_TABLE_395__VceLevel_2_MinVoltage_MASK
127555. DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT
127556. DPM_TABLE_396__SamuLevel_3_Frequency_MASK
127557. DPM_TABLE_396__SamuLevel_3_Frequency__SHIFT
127558. DPM_TABLE_396__Smio_30_MASK
127559. DPM_TABLE_396__Smio_30__SHIFT
127560. DPM_TABLE_396__VceLevel_3_Frequency_MASK
127561. DPM_TABLE_396__VceLevel_3_Frequency__SHIFT
127562. DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases_MASK
127563. DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases__SHIFT
127564. DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx_MASK
127565. DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx__SHIFT
127566. DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc_MASK
127567. DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc__SHIFT
127568. DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci_MASK
127569. DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci__SHIFT
127570. DPM_TABLE_397__Smio_31_MASK
127571. DPM_TABLE_397__Smio_31__SHIFT
127572. DPM_TABLE_397__VceLevel_3_Divider_MASK
127573. DPM_TABLE_397__VceLevel_3_Divider__SHIFT
127574. DPM_TABLE_397__VceLevel_3_MinPhases_MASK
127575. DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT
127576. DPM_TABLE_397__VceLevel_3_MinVoltage_MASK
127577. DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT
127578. DPM_TABLE_398__AcpBootLevel_MASK
127579. DPM_TABLE_398__AcpBootLevel__SHIFT
127580. DPM_TABLE_398__SamuBootLevel_MASK
127581. DPM_TABLE_398__SamuBootLevel__SHIFT
127582. DPM_TABLE_398__SamuLevel_3_Divider_MASK
127583. DPM_TABLE_398__SamuLevel_3_Divider__SHIFT
127584. DPM_TABLE_398__SamuLevel_3_padding_0_MASK
127585. DPM_TABLE_398__SamuLevel_3_padding_0__SHIFT
127586. DPM_TABLE_398__SamuLevel_3_padding_1_MASK
127587. DPM_TABLE_398__SamuLevel_3_padding_1__SHIFT
127588. DPM_TABLE_398__SamuLevel_3_padding_2_MASK
127589. DPM_TABLE_398__SamuLevel_3_padding_2__SHIFT
127590. DPM_TABLE_398__UvdBootLevel_MASK
127591. DPM_TABLE_398__UvdBootLevel__SHIFT
127592. DPM_TABLE_398__VceBootLevel_MASK
127593. DPM_TABLE_398__VceBootLevel__SHIFT
127594. DPM_TABLE_398__VceLevel_4_Frequency_MASK
127595. DPM_TABLE_398__VceLevel_4_Frequency__SHIFT
127596. DPM_TABLE_399__GraphicsBootLevel_MASK
127597. DPM_TABLE_399__GraphicsBootLevel__SHIFT
127598. DPM_TABLE_399__GraphicsInterval_MASK
127599. DPM_TABLE_399__GraphicsInterval__SHIFT
127600. DPM_TABLE_399__GraphicsThermThrottleEnable_MASK
127601. DPM_TABLE_399__GraphicsThermThrottleEnable__SHIFT
127602. DPM_TABLE_399__GraphicsVoltageChangeEnable_MASK
127603. DPM_TABLE_399__GraphicsVoltageChangeEnable__SHIFT
127604. DPM_TABLE_399__SamuLevel_4_Frequency_MASK
127605. DPM_TABLE_399__SamuLevel_4_Frequency__SHIFT
127606. DPM_TABLE_399__VceLevel_4_Divider_MASK
127607. DPM_TABLE_399__VceLevel_4_Divider__SHIFT
127608. DPM_TABLE_399__VceLevel_4_MinPhases_MASK
127609. DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT
127610. DPM_TABLE_399__VceLevel_4_MinVoltage_MASK
127611. DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT
127612. DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1_MASK
127613. DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1__SHIFT
127614. DPM_TABLE_39__GraphicsLevel_2_GnbSlow_MASK
127615. DPM_TABLE_39__GraphicsLevel_2_GnbSlow__SHIFT
127616. DPM_TABLE_39__GraphicsLevel_2_PowerThrottle_MASK
127617. DPM_TABLE_39__GraphicsLevel_2_PowerThrottle__SHIFT
127618. DPM_TABLE_39__GraphicsLevel_2_SclkDid_MASK
127619. DPM_TABLE_39__GraphicsLevel_2_SclkDid__SHIFT
127620. DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK
127621. DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT
127622. DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK
127623. DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT
127624. DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK
127625. DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT
127626. DPM_TABLE_39__VddcLevel_1_Smio_MASK
127627. DPM_TABLE_39__VddcLevel_1_Smio__SHIFT
127628. DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK
127629. DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT
127630. DPM_TABLE_39__VddcLevel_1_padding_MASK
127631. DPM_TABLE_39__VddcLevel_1_padding__SHIFT
127632. DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK
127633. DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT
127634. DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim_MASK
127635. DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim__SHIFT
127636. DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases_MASK
127637. DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases__SHIFT
127638. DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx_MASK
127639. DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx__SHIFT
127640. DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc_MASK
127641. DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc__SHIFT
127642. DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci_MASK
127643. DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci__SHIFT
127644. DPM_TABLE_400__TemperatureLimitHigh_MASK
127645. DPM_TABLE_400__TemperatureLimitHigh__SHIFT
127646. DPM_TABLE_400__ThermalInterval_MASK
127647. DPM_TABLE_400__ThermalInterval__SHIFT
127648. DPM_TABLE_400__VceLevel_5_Frequency_MASK
127649. DPM_TABLE_400__VceLevel_5_Frequency__SHIFT
127650. DPM_TABLE_400__VoltageInterval_MASK
127651. DPM_TABLE_400__VoltageInterval__SHIFT
127652. DPM_TABLE_401__MemoryBootLevel_MASK
127653. DPM_TABLE_401__MemoryBootLevel__SHIFT
127654. DPM_TABLE_401__MemoryVoltageChangeEnable_MASK
127655. DPM_TABLE_401__MemoryVoltageChangeEnable__SHIFT
127656. DPM_TABLE_401__SamuLevel_4_Divider_MASK
127657. DPM_TABLE_401__SamuLevel_4_Divider__SHIFT
127658. DPM_TABLE_401__SamuLevel_4_padding_0_MASK
127659. DPM_TABLE_401__SamuLevel_4_padding_0__SHIFT
127660. DPM_TABLE_401__SamuLevel_4_padding_1_MASK
127661. DPM_TABLE_401__SamuLevel_4_padding_1__SHIFT
127662. DPM_TABLE_401__SamuLevel_4_padding_2_MASK
127663. DPM_TABLE_401__SamuLevel_4_padding_2__SHIFT
127664. DPM_TABLE_401__TemperatureLimitLow_MASK
127665. DPM_TABLE_401__TemperatureLimitLow__SHIFT
127666. DPM_TABLE_401__VceLevel_5_Divider_MASK
127667. DPM_TABLE_401__VceLevel_5_Divider__SHIFT
127668. DPM_TABLE_401__VceLevel_5_MinPhases_MASK
127669. DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT
127670. DPM_TABLE_401__VceLevel_5_MinVoltage_MASK
127671. DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT
127672. DPM_TABLE_402__BootMVdd_MASK
127673. DPM_TABLE_402__BootMVdd__SHIFT
127674. DPM_TABLE_402__MemoryInterval_MASK
127675. DPM_TABLE_402__MemoryInterval__SHIFT
127676. DPM_TABLE_402__MemoryThermThrottleEnable_MASK
127677. DPM_TABLE_402__MemoryThermThrottleEnable__SHIFT
127678. DPM_TABLE_402__SamuLevel_5_Frequency_MASK
127679. DPM_TABLE_402__SamuLevel_5_Frequency__SHIFT
127680. DPM_TABLE_402__VceLevel_6_Frequency_MASK
127681. DPM_TABLE_402__VceLevel_6_Frequency__SHIFT
127682. DPM_TABLE_403__PhaseResponseTime_MASK
127683. DPM_TABLE_403__PhaseResponseTime__SHIFT
127684. DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases_MASK
127685. DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases__SHIFT
127686. DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx_MASK
127687. DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx__SHIFT
127688. DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc_MASK
127689. DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc__SHIFT
127690. DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci_MASK
127691. DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci__SHIFT
127692. DPM_TABLE_403__VceLevel_6_Divider_MASK
127693. DPM_TABLE_403__VceLevel_6_Divider__SHIFT
127694. DPM_TABLE_403__VceLevel_6_MinPhases_MASK
127695. DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT
127696. DPM_TABLE_403__VceLevel_6_MinVoltage_MASK
127697. DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT
127698. DPM_TABLE_403__VoltageResponseTime_MASK
127699. DPM_TABLE_403__VoltageResponseTime__SHIFT
127700. DPM_TABLE_404__DTEInterval_MASK
127701. DPM_TABLE_404__DTEInterval__SHIFT
127702. DPM_TABLE_404__DTEMode_MASK
127703. DPM_TABLE_404__DTEMode__SHIFT
127704. DPM_TABLE_404__PCIeBootLinkLevel_MASK
127705. DPM_TABLE_404__PCIeBootLinkLevel__SHIFT
127706. DPM_TABLE_404__PCIeGenInterval_MASK
127707. DPM_TABLE_404__PCIeGenInterval__SHIFT
127708. DPM_TABLE_404__SamuLevel_5_Divider_MASK
127709. DPM_TABLE_404__SamuLevel_5_Divider__SHIFT
127710. DPM_TABLE_404__SamuLevel_5_padding_0_MASK
127711. DPM_TABLE_404__SamuLevel_5_padding_0__SHIFT
127712. DPM_TABLE_404__SamuLevel_5_padding_1_MASK
127713. DPM_TABLE_404__SamuLevel_5_padding_1__SHIFT
127714. DPM_TABLE_404__SamuLevel_5_padding_2_MASK
127715. DPM_TABLE_404__SamuLevel_5_padding_2__SHIFT
127716. DPM_TABLE_404__VceLevel_7_Frequency_MASK
127717. DPM_TABLE_404__VceLevel_7_Frequency__SHIFT
127718. DPM_TABLE_405__AcDcGpio_MASK
127719. DPM_TABLE_405__AcDcGpio__SHIFT
127720. DPM_TABLE_405__SVI2Enable_MASK
127721. DPM_TABLE_405__SVI2Enable__SHIFT
127722. DPM_TABLE_405__SamuLevel_6_Frequency_MASK
127723. DPM_TABLE_405__SamuLevel_6_Frequency__SHIFT
127724. DPM_TABLE_405__ThermGpio_MASK
127725. DPM_TABLE_405__ThermGpio__SHIFT
127726. DPM_TABLE_405__VRHotGpio_MASK
127727. DPM_TABLE_405__VRHotGpio__SHIFT
127728. DPM_TABLE_405__VceLevel_7_Divider_MASK
127729. DPM_TABLE_405__VceLevel_7_Divider__SHIFT
127730. DPM_TABLE_405__VceLevel_7_MinPhases_MASK
127731. DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT
127732. DPM_TABLE_405__VceLevel_7_MinVoltage_MASK
127733. DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT
127734. DPM_TABLE_406__AcpLevel_0_Frequency_MASK
127735. DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT
127736. DPM_TABLE_406__PPM_PkgPwrLimit_MASK
127737. DPM_TABLE_406__PPM_PkgPwrLimit__SHIFT
127738. DPM_TABLE_406__PPM_TemperatureLimit_MASK
127739. DPM_TABLE_406__PPM_TemperatureLimit__SHIFT
127740. DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases_MASK
127741. DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases__SHIFT
127742. DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx_MASK
127743. DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx__SHIFT
127744. DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc_MASK
127745. DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc__SHIFT
127746. DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci_MASK
127747. DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci__SHIFT
127748. DPM_TABLE_407__AcpLevel_0_Divider_MASK
127749. DPM_TABLE_407__AcpLevel_0_Divider__SHIFT
127750. DPM_TABLE_407__AcpLevel_0_MinPhases_MASK
127751. DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT
127752. DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK
127753. DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT
127754. DPM_TABLE_407__DefaultTdp_MASK
127755. DPM_TABLE_407__DefaultTdp__SHIFT
127756. DPM_TABLE_407__SamuLevel_6_Divider_MASK
127757. DPM_TABLE_407__SamuLevel_6_Divider__SHIFT
127758. DPM_TABLE_407__SamuLevel_6_padding_0_MASK
127759. DPM_TABLE_407__SamuLevel_6_padding_0__SHIFT
127760. DPM_TABLE_407__SamuLevel_6_padding_1_MASK
127761. DPM_TABLE_407__SamuLevel_6_padding_1__SHIFT
127762. DPM_TABLE_407__SamuLevel_6_padding_2_MASK
127763. DPM_TABLE_407__SamuLevel_6_padding_2__SHIFT
127764. DPM_TABLE_407__TargetTdp_MASK
127765. DPM_TABLE_407__TargetTdp__SHIFT
127766. DPM_TABLE_408__AcpLevel_1_Frequency_MASK
127767. DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT
127768. DPM_TABLE_408__FpsHighThreshold_MASK
127769. DPM_TABLE_408__FpsHighThreshold__SHIFT
127770. DPM_TABLE_408__FpsLowThreshold_MASK
127771. DPM_TABLE_408__FpsLowThreshold__SHIFT
127772. DPM_TABLE_408__SamuLevel_7_Frequency_MASK
127773. DPM_TABLE_408__SamuLevel_7_Frequency__SHIFT
127774. DPM_TABLE_409__AcpLevel_1_Divider_MASK
127775. DPM_TABLE_409__AcpLevel_1_Divider__SHIFT
127776. DPM_TABLE_409__AcpLevel_1_MinPhases_MASK
127777. DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT
127778. DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK
127779. DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT
127780. DPM_TABLE_409__BAPMTI_R_0_0_0_MASK
127781. DPM_TABLE_409__BAPMTI_R_0_0_0__SHIFT
127782. DPM_TABLE_409__BAPMTI_R_0_1_0_MASK
127783. DPM_TABLE_409__BAPMTI_R_0_1_0__SHIFT
127784. DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases_MASK
127785. DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases__SHIFT
127786. DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx_MASK
127787. DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx__SHIFT
127788. DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc_MASK
127789. DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc__SHIFT
127790. DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci_MASK
127791. DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci__SHIFT
127792. DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark_MASK
127793. DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark__SHIFT
127794. DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity_MASK
127795. DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity__SHIFT
127796. DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle_MASK
127797. DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle__SHIFT
127798. DPM_TABLE_40__GraphicsLevel_2_UpHyst_MASK
127799. DPM_TABLE_40__GraphicsLevel_2_UpHyst__SHIFT
127800. DPM_TABLE_40__VddcLevelCount_MASK
127801. DPM_TABLE_40__VddcLevelCount__SHIFT
127802. DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK
127803. DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT
127804. DPM_TABLE_40__VddcLevel_2_Voltage_MASK
127805. DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT
127806. DPM_TABLE_410__AcpLevel_2_Frequency_MASK
127807. DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT
127808. DPM_TABLE_410__BAPMTI_R_0_2_0_MASK
127809. DPM_TABLE_410__BAPMTI_R_0_2_0__SHIFT
127810. DPM_TABLE_410__BAPMTI_R_1_0_0_MASK
127811. DPM_TABLE_410__BAPMTI_R_1_0_0__SHIFT
127812. DPM_TABLE_410__SamuLevel_7_Divider_MASK
127813. DPM_TABLE_410__SamuLevel_7_Divider__SHIFT
127814. DPM_TABLE_410__SamuLevel_7_padding_0_MASK
127815. DPM_TABLE_410__SamuLevel_7_padding_0__SHIFT
127816. DPM_TABLE_410__SamuLevel_7_padding_1_MASK
127817. DPM_TABLE_410__SamuLevel_7_padding_1__SHIFT
127818. DPM_TABLE_410__SamuLevel_7_padding_2_MASK
127819. DPM_TABLE_410__SamuLevel_7_padding_2__SHIFT
127820. DPM_TABLE_411__AcpLevel_2_Divider_MASK
127821. DPM_TABLE_411__AcpLevel_2_Divider__SHIFT
127822. DPM_TABLE_411__AcpLevel_2_MinPhases_MASK
127823. DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT
127824. DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK
127825. DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT
127826. DPM_TABLE_411__BAPMTI_R_1_1_0_MASK
127827. DPM_TABLE_411__BAPMTI_R_1_1_0__SHIFT
127828. DPM_TABLE_411__BAPMTI_R_1_2_0_MASK
127829. DPM_TABLE_411__BAPMTI_R_1_2_0__SHIFT
127830. DPM_TABLE_411__Ulv_CcPwrDynRm_MASK
127831. DPM_TABLE_411__Ulv_CcPwrDynRm__SHIFT
127832. DPM_TABLE_412__AcpLevel_3_Frequency_MASK
127833. DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT
127834. DPM_TABLE_412__BAPMTI_R_2_0_0_MASK
127835. DPM_TABLE_412__BAPMTI_R_2_0_0__SHIFT
127836. DPM_TABLE_412__BAPMTI_R_2_1_0_MASK
127837. DPM_TABLE_412__BAPMTI_R_2_1_0__SHIFT
127838. DPM_TABLE_412__Ulv_CcPwrDynRm1_MASK
127839. DPM_TABLE_412__Ulv_CcPwrDynRm1__SHIFT
127840. DPM_TABLE_413__AcpLevel_3_Divider_MASK
127841. DPM_TABLE_413__AcpLevel_3_Divider__SHIFT
127842. DPM_TABLE_413__AcpLevel_3_MinPhases_MASK
127843. DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT
127844. DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK
127845. DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT
127846. DPM_TABLE_413__BAPMTI_R_2_2_0_MASK
127847. DPM_TABLE_413__BAPMTI_R_2_2_0__SHIFT
127848. DPM_TABLE_413__BAPMTI_R_3_0_0_MASK
127849. DPM_TABLE_413__BAPMTI_R_3_0_0__SHIFT
127850. DPM_TABLE_413__Ulv_VddcOffsetVid_MASK
127851. DPM_TABLE_413__Ulv_VddcOffsetVid__SHIFT
127852. DPM_TABLE_413__Ulv_VddcOffset_MASK
127853. DPM_TABLE_413__Ulv_VddcOffset__SHIFT
127854. DPM_TABLE_413__Ulv_VddcPhase_MASK
127855. DPM_TABLE_413__Ulv_VddcPhase__SHIFT
127856. DPM_TABLE_414__AcpLevel_4_Frequency_MASK
127857. DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT
127858. DPM_TABLE_414__BAPMTI_R_3_1_0_MASK
127859. DPM_TABLE_414__BAPMTI_R_3_1_0__SHIFT
127860. DPM_TABLE_414__BAPMTI_R_3_2_0_MASK
127861. DPM_TABLE_414__BAPMTI_R_3_2_0__SHIFT
127862. DPM_TABLE_414__Ulv_Reserved_MASK
127863. DPM_TABLE_414__Ulv_Reserved__SHIFT
127864. DPM_TABLE_415__AcpLevel_4_Divider_MASK
127865. DPM_TABLE_415__AcpLevel_4_Divider__SHIFT
127866. DPM_TABLE_415__AcpLevel_4_MinPhases_MASK
127867. DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT
127868. DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK
127869. DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT
127870. DPM_TABLE_415__BAPMTI_R_4_0_0_MASK
127871. DPM_TABLE_415__BAPMTI_R_4_0_0__SHIFT
127872. DPM_TABLE_415__BAPMTI_R_4_1_0_MASK
127873. DPM_TABLE_415__BAPMTI_R_4_1_0__SHIFT
127874. DPM_TABLE_415__SclkStepSize_MASK
127875. DPM_TABLE_415__SclkStepSize__SHIFT
127876. DPM_TABLE_416__AcpLevel_5_Frequency_MASK
127877. DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT
127878. DPM_TABLE_416__BAPMTI_RC_0_0_0_MASK
127879. DPM_TABLE_416__BAPMTI_RC_0_0_0__SHIFT
127880. DPM_TABLE_416__BAPMTI_R_4_2_0_MASK
127881. DPM_TABLE_416__BAPMTI_R_4_2_0__SHIFT
127882. DPM_TABLE_416__Smio_0_MASK
127883. DPM_TABLE_416__Smio_0__SHIFT
127884. DPM_TABLE_417__AcpLevel_5_Divider_MASK
127885. DPM_TABLE_417__AcpLevel_5_Divider__SHIFT
127886. DPM_TABLE_417__AcpLevel_5_MinPhases_MASK
127887. DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT
127888. DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK
127889. DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT
127890. DPM_TABLE_417__BAPMTI_RC_0_1_0_MASK
127891. DPM_TABLE_417__BAPMTI_RC_0_1_0__SHIFT
127892. DPM_TABLE_417__BAPMTI_RC_0_2_0_MASK
127893. DPM_TABLE_417__BAPMTI_RC_0_2_0__SHIFT
127894. DPM_TABLE_417__Smio_1_MASK
127895. DPM_TABLE_417__Smio_1__SHIFT
127896. DPM_TABLE_418__AcpLevel_6_Frequency_MASK
127897. DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT
127898. DPM_TABLE_418__BAPMTI_RC_1_0_0_MASK
127899. DPM_TABLE_418__BAPMTI_RC_1_0_0__SHIFT
127900. DPM_TABLE_418__BAPMTI_RC_1_1_0_MASK
127901. DPM_TABLE_418__BAPMTI_RC_1_1_0__SHIFT
127902. DPM_TABLE_418__Smio_2_MASK
127903. DPM_TABLE_418__Smio_2__SHIFT
127904. DPM_TABLE_419__AcpLevel_6_Divider_MASK
127905. DPM_TABLE_419__AcpLevel_6_Divider__SHIFT
127906. DPM_TABLE_419__AcpLevel_6_MinPhases_MASK
127907. DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT
127908. DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK
127909. DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT
127910. DPM_TABLE_419__BAPMTI_RC_1_2_0_MASK
127911. DPM_TABLE_419__BAPMTI_RC_1_2_0__SHIFT
127912. DPM_TABLE_419__BAPMTI_RC_2_0_0_MASK
127913. DPM_TABLE_419__BAPMTI_RC_2_0_0__SHIFT
127914. DPM_TABLE_419__Smio_3_MASK
127915. DPM_TABLE_419__Smio_3__SHIFT
127916. DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl_MASK
127917. DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl__SHIFT
127918. DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId_MASK
127919. DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId__SHIFT
127920. DPM_TABLE_41__GraphicsLevel_2_DownHyst_MASK
127921. DPM_TABLE_41__GraphicsLevel_2_DownHyst__SHIFT
127922. DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst_MASK
127923. DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst__SHIFT
127924. DPM_TABLE_41__VddcLevel_2_Smio_MASK
127925. DPM_TABLE_41__VddcLevel_2_Smio__SHIFT
127926. DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK
127927. DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT
127928. DPM_TABLE_41__VddcLevel_2_padding_MASK
127929. DPM_TABLE_41__VddcLevel_2_padding__SHIFT
127930. DPM_TABLE_41__VddciLevelCount_MASK
127931. DPM_TABLE_41__VddciLevelCount__SHIFT
127932. DPM_TABLE_420__AcpLevel_7_Frequency_MASK
127933. DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT
127934. DPM_TABLE_420__BAPMTI_RC_2_1_0_MASK
127935. DPM_TABLE_420__BAPMTI_RC_2_1_0__SHIFT
127936. DPM_TABLE_420__BAPMTI_RC_2_2_0_MASK
127937. DPM_TABLE_420__BAPMTI_RC_2_2_0__SHIFT
127938. DPM_TABLE_420__Smio_4_MASK
127939. DPM_TABLE_420__Smio_4__SHIFT
127940. DPM_TABLE_421__AcpLevel_7_Divider_MASK
127941. DPM_TABLE_421__AcpLevel_7_Divider__SHIFT
127942. DPM_TABLE_421__AcpLevel_7_MinPhases_MASK
127943. DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT
127944. DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK
127945. DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT
127946. DPM_TABLE_421__BAPMTI_RC_3_0_0_MASK
127947. DPM_TABLE_421__BAPMTI_RC_3_0_0__SHIFT
127948. DPM_TABLE_421__BAPMTI_RC_3_1_0_MASK
127949. DPM_TABLE_421__BAPMTI_RC_3_1_0__SHIFT
127950. DPM_TABLE_421__Smio_5_MASK
127951. DPM_TABLE_421__Smio_5__SHIFT
127952. DPM_TABLE_422__BAPMTI_RC_3_2_0_MASK
127953. DPM_TABLE_422__BAPMTI_RC_3_2_0__SHIFT
127954. DPM_TABLE_422__BAPMTI_RC_4_0_0_MASK
127955. DPM_TABLE_422__BAPMTI_RC_4_0_0__SHIFT
127956. DPM_TABLE_422__SamuLevel_0_Frequency_MASK
127957. DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT
127958. DPM_TABLE_422__Smio_6_MASK
127959. DPM_TABLE_422__Smio_6__SHIFT
127960. DPM_TABLE_423__BAPMTI_RC_4_1_0_MASK
127961. DPM_TABLE_423__BAPMTI_RC_4_1_0__SHIFT
127962. DPM_TABLE_423__BAPMTI_RC_4_2_0_MASK
127963. DPM_TABLE_423__BAPMTI_RC_4_2_0__SHIFT
127964. DPM_TABLE_423__SamuLevel_0_Divider_MASK
127965. DPM_TABLE_423__SamuLevel_0_Divider__SHIFT
127966. DPM_TABLE_423__SamuLevel_0_MinPhases_MASK
127967. DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT
127968. DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK
127969. DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT
127970. DPM_TABLE_423__Smio_7_MASK
127971. DPM_TABLE_423__Smio_7__SHIFT
127972. DPM_TABLE_424__DTEAmbientTempBase_MASK
127973. DPM_TABLE_424__DTEAmbientTempBase__SHIFT
127974. DPM_TABLE_424__DTETjOffset_MASK
127975. DPM_TABLE_424__DTETjOffset__SHIFT
127976. DPM_TABLE_424__GpuTjHyst_MASK
127977. DPM_TABLE_424__GpuTjHyst__SHIFT
127978. DPM_TABLE_424__GpuTjMax_MASK
127979. DPM_TABLE_424__GpuTjMax__SHIFT
127980. DPM_TABLE_424__SamuLevel_1_Frequency_MASK
127981. DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT
127982. DPM_TABLE_424__Smio_8_MASK
127983. DPM_TABLE_424__Smio_8__SHIFT
127984. DPM_TABLE_425__BootVoltage_Phases_MASK
127985. DPM_TABLE_425__BootVoltage_Phases__SHIFT
127986. DPM_TABLE_425__BootVoltage_VddGfx_MASK
127987. DPM_TABLE_425__BootVoltage_VddGfx__SHIFT
127988. DPM_TABLE_425__BootVoltage_Vddc_MASK
127989. DPM_TABLE_425__BootVoltage_Vddc__SHIFT
127990. DPM_TABLE_425__BootVoltage_Vddci_MASK
127991. DPM_TABLE_425__BootVoltage_Vddci__SHIFT
127992. DPM_TABLE_425__SamuLevel_1_Divider_MASK
127993. DPM_TABLE_425__SamuLevel_1_Divider__SHIFT
127994. DPM_TABLE_425__SamuLevel_1_MinPhases_MASK
127995. DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT
127996. DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK
127997. DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT
127998. DPM_TABLE_425__Smio_9_MASK
127999. DPM_TABLE_425__Smio_9__SHIFT
128000. DPM_TABLE_426__BAPM_TEMP_GRADIENT_MASK
128001. DPM_TABLE_426__BAPM_TEMP_GRADIENT__SHIFT
128002. DPM_TABLE_426__SamuLevel_2_Frequency_MASK
128003. DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT
128004. DPM_TABLE_426__Smio_10_MASK
128005. DPM_TABLE_426__Smio_10__SHIFT
128006. DPM_TABLE_427__LowSclkInterruptThreshold_MASK
128007. DPM_TABLE_427__LowSclkInterruptThreshold__SHIFT
128008. DPM_TABLE_427__SamuLevel_2_Divider_MASK
128009. DPM_TABLE_427__SamuLevel_2_Divider__SHIFT
128010. DPM_TABLE_427__SamuLevel_2_MinPhases_MASK
128011. DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT
128012. DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK
128013. DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT
128014. DPM_TABLE_427__Smio_11_MASK
128015. DPM_TABLE_427__Smio_11__SHIFT
128016. DPM_TABLE_428__SamuLevel_3_Frequency_MASK
128017. DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT
128018. DPM_TABLE_428__Smio_12_MASK
128019. DPM_TABLE_428__Smio_12__SHIFT
128020. DPM_TABLE_428__VddGfxReChkWait_MASK
128021. DPM_TABLE_428__VddGfxReChkWait__SHIFT
128022. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK
128023. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT
128024. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK
128025. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT
128026. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK
128027. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT
128028. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK
128029. DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT
128030. DPM_TABLE_429__SamuLevel_3_Divider_MASK
128031. DPM_TABLE_429__SamuLevel_3_Divider__SHIFT
128032. DPM_TABLE_429__SamuLevel_3_MinPhases_MASK
128033. DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT
128034. DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK
128035. DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT
128036. DPM_TABLE_429__Smio_13_MASK
128037. DPM_TABLE_429__Smio_13__SHIFT
128038. DPM_TABLE_42__GraphicsLevel_2_reserved_MASK
128039. DPM_TABLE_42__GraphicsLevel_2_reserved__SHIFT
128040. DPM_TABLE_42__VddGfxLevelCount_MASK
128041. DPM_TABLE_42__VddGfxLevelCount__SHIFT
128042. DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK
128043. DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT
128044. DPM_TABLE_42__VddcLevel_3_Voltage_MASK
128045. DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT
128046. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK
128047. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT
128048. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK
128049. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT
128050. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK
128051. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT
128052. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK
128053. DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT
128054. DPM_TABLE_430__SamuLevel_4_Frequency_MASK
128055. DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT
128056. DPM_TABLE_430__Smio_14_MASK
128057. DPM_TABLE_430__Smio_14__SHIFT
128058. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK
128059. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT
128060. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK
128061. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT
128062. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK
128063. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT
128064. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK
128065. DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT
128066. DPM_TABLE_431__SamuLevel_4_Divider_MASK
128067. DPM_TABLE_431__SamuLevel_4_Divider__SHIFT
128068. DPM_TABLE_431__SamuLevel_4_MinPhases_MASK
128069. DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT
128070. DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK
128071. DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT
128072. DPM_TABLE_431__Smio_15_MASK
128073. DPM_TABLE_431__Smio_15__SHIFT
128074. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK
128075. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT
128076. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK
128077. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT
128078. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK
128079. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT
128080. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK
128081. DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT
128082. DPM_TABLE_432__SamuLevel_5_Frequency_MASK
128083. DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT
128084. DPM_TABLE_432__Smio_16_MASK
128085. DPM_TABLE_432__Smio_16__SHIFT
128086. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK
128087. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT
128088. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK
128089. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT
128090. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK
128091. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT
128092. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK
128093. DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT
128094. DPM_TABLE_433__SamuLevel_5_Divider_MASK
128095. DPM_TABLE_433__SamuLevel_5_Divider__SHIFT
128096. DPM_TABLE_433__SamuLevel_5_MinPhases_MASK
128097. DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT
128098. DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK
128099. DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT
128100. DPM_TABLE_433__Smio_17_MASK
128101. DPM_TABLE_433__Smio_17__SHIFT
128102. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK
128103. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT
128104. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK
128105. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT
128106. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK
128107. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT
128108. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK
128109. DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT
128110. DPM_TABLE_434__SamuLevel_6_Frequency_MASK
128111. DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT
128112. DPM_TABLE_434__Smio_18_MASK
128113. DPM_TABLE_434__Smio_18__SHIFT
128114. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK
128115. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT
128116. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK
128117. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT
128118. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK
128119. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT
128120. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK
128121. DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT
128122. DPM_TABLE_435__SamuLevel_6_Divider_MASK
128123. DPM_TABLE_435__SamuLevel_6_Divider__SHIFT
128124. DPM_TABLE_435__SamuLevel_6_MinPhases_MASK
128125. DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT
128126. DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK
128127. DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT
128128. DPM_TABLE_435__Smio_19_MASK
128129. DPM_TABLE_435__Smio_19__SHIFT
128130. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK
128131. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT
128132. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK
128133. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT
128134. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK
128135. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT
128136. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK
128137. DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT
128138. DPM_TABLE_436__SamuLevel_7_Frequency_MASK
128139. DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT
128140. DPM_TABLE_436__Smio_20_MASK
128141. DPM_TABLE_436__Smio_20__SHIFT
128142. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK
128143. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT
128144. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK
128145. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT
128146. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK
128147. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT
128148. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK
128149. DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT
128150. DPM_TABLE_437__SamuLevel_7_Divider_MASK
128151. DPM_TABLE_437__SamuLevel_7_Divider__SHIFT
128152. DPM_TABLE_437__SamuLevel_7_MinPhases_MASK
128153. DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT
128154. DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK
128155. DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT
128156. DPM_TABLE_437__Smio_21_MASK
128157. DPM_TABLE_437__Smio_21__SHIFT
128158. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK
128159. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT
128160. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK
128161. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT
128162. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK
128163. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT
128164. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK
128165. DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT
128166. DPM_TABLE_438__Smio_22_MASK
128167. DPM_TABLE_438__Smio_22__SHIFT
128168. DPM_TABLE_438__Ulv_CcPwrDynRm_MASK
128169. DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT
128170. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK
128171. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT
128172. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK
128173. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT
128174. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK
128175. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT
128176. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK
128177. DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT
128178. DPM_TABLE_439__Smio_23_MASK
128179. DPM_TABLE_439__Smio_23__SHIFT
128180. DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK
128181. DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT
128182. DPM_TABLE_43__GraphicsLevel_3_MinVddNb_MASK
128183. DPM_TABLE_43__GraphicsLevel_3_MinVddNb__SHIFT
128184. DPM_TABLE_43__MvddLevelCount_MASK
128185. DPM_TABLE_43__MvddLevelCount__SHIFT
128186. DPM_TABLE_43__VddcLevel_3_Smio_MASK
128187. DPM_TABLE_43__VddcLevel_3_Smio__SHIFT
128188. DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK
128189. DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT
128190. DPM_TABLE_43__VddcLevel_3_padding_MASK
128191. DPM_TABLE_43__VddcLevel_3_padding__SHIFT
128192. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK
128193. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT
128194. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK
128195. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT
128196. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK
128197. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT
128198. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK
128199. DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT
128200. DPM_TABLE_440__Smio_24_MASK
128201. DPM_TABLE_440__Smio_24__SHIFT
128202. DPM_TABLE_440__Ulv_VddcOffsetVid_MASK
128203. DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT
128204. DPM_TABLE_440__Ulv_VddcOffset_MASK
128205. DPM_TABLE_440__Ulv_VddcOffset__SHIFT
128206. DPM_TABLE_440__Ulv_VddcPhase_MASK
128207. DPM_TABLE_440__Ulv_VddcPhase__SHIFT
128208. DPM_TABLE_441__Smio_25_MASK
128209. DPM_TABLE_441__Smio_25__SHIFT
128210. DPM_TABLE_441__Ulv_Reserved_MASK
128211. DPM_TABLE_441__Ulv_Reserved__SHIFT
128212. DPM_TABLE_442__SclkStepSize_MASK
128213. DPM_TABLE_442__SclkStepSize__SHIFT
128214. DPM_TABLE_442__Smio_26_MASK
128215. DPM_TABLE_442__Smio_26__SHIFT
128216. DPM_TABLE_443__Smio_0_MASK
128217. DPM_TABLE_443__Smio_0__SHIFT
128218. DPM_TABLE_443__Smio_27_MASK
128219. DPM_TABLE_443__Smio_27__SHIFT
128220. DPM_TABLE_444__Smio_1_MASK
128221. DPM_TABLE_444__Smio_1__SHIFT
128222. DPM_TABLE_444__Smio_28_MASK
128223. DPM_TABLE_444__Smio_28__SHIFT
128224. DPM_TABLE_445__Smio_29_MASK
128225. DPM_TABLE_445__Smio_29__SHIFT
128226. DPM_TABLE_445__Smio_2_MASK
128227. DPM_TABLE_445__Smio_2__SHIFT
128228. DPM_TABLE_446__Smio_30_MASK
128229. DPM_TABLE_446__Smio_30__SHIFT
128230. DPM_TABLE_446__Smio_3_MASK
128231. DPM_TABLE_446__Smio_3__SHIFT
128232. DPM_TABLE_447__Smio_31_MASK
128233. DPM_TABLE_447__Smio_31__SHIFT
128234. DPM_TABLE_447__Smio_4_MASK
128235. DPM_TABLE_447__Smio_4__SHIFT
128236. DPM_TABLE_448__AcpBootLevel_MASK
128237. DPM_TABLE_448__AcpBootLevel__SHIFT
128238. DPM_TABLE_448__SamuBootLevel_MASK
128239. DPM_TABLE_448__SamuBootLevel__SHIFT
128240. DPM_TABLE_448__Smio_5_MASK
128241. DPM_TABLE_448__Smio_5__SHIFT
128242. DPM_TABLE_448__UvdBootLevel_MASK
128243. DPM_TABLE_448__UvdBootLevel__SHIFT
128244. DPM_TABLE_448__VceBootLevel_MASK
128245. DPM_TABLE_448__VceBootLevel__SHIFT
128246. DPM_TABLE_449__GraphicsBootLevel_MASK
128247. DPM_TABLE_449__GraphicsBootLevel__SHIFT
128248. DPM_TABLE_449__GraphicsInterval_MASK
128249. DPM_TABLE_449__GraphicsInterval__SHIFT
128250. DPM_TABLE_449__GraphicsThermThrottleEnable_MASK
128251. DPM_TABLE_449__GraphicsThermThrottleEnable__SHIFT
128252. DPM_TABLE_449__GraphicsVoltageChangeEnable_MASK
128253. DPM_TABLE_449__GraphicsVoltageChangeEnable__SHIFT
128254. DPM_TABLE_449__Smio_6_MASK
128255. DPM_TABLE_449__Smio_6__SHIFT
128256. DPM_TABLE_44__GraphicsLevel_3_SclkFrequency_MASK
128257. DPM_TABLE_44__GraphicsLevel_3_SclkFrequency__SHIFT
128258. DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK
128259. DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT
128260. DPM_TABLE_44__VddcLevel_4_Voltage_MASK
128261. DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT
128262. DPM_TABLE_44__VddcTable_0_MASK
128263. DPM_TABLE_44__VddcTable_0__SHIFT
128264. DPM_TABLE_44__VddcTable_1_MASK
128265. DPM_TABLE_44__VddcTable_1__SHIFT
128266. DPM_TABLE_450__Smio_7_MASK
128267. DPM_TABLE_450__Smio_7__SHIFT
128268. DPM_TABLE_450__TemperatureLimitHigh_MASK
128269. DPM_TABLE_450__TemperatureLimitHigh__SHIFT
128270. DPM_TABLE_450__ThermalInterval_MASK
128271. DPM_TABLE_450__ThermalInterval__SHIFT
128272. DPM_TABLE_450__VoltageInterval_MASK
128273. DPM_TABLE_450__VoltageInterval__SHIFT
128274. DPM_TABLE_451__MemoryBootLevel_MASK
128275. DPM_TABLE_451__MemoryBootLevel__SHIFT
128276. DPM_TABLE_451__MemoryVoltageChangeEnable_MASK
128277. DPM_TABLE_451__MemoryVoltageChangeEnable__SHIFT
128278. DPM_TABLE_451__Smio_8_MASK
128279. DPM_TABLE_451__Smio_8__SHIFT
128280. DPM_TABLE_451__TemperatureLimitLow_MASK
128281. DPM_TABLE_451__TemperatureLimitLow__SHIFT
128282. DPM_TABLE_452__BootMVdd_MASK
128283. DPM_TABLE_452__BootMVdd__SHIFT
128284. DPM_TABLE_452__MemoryInterval_MASK
128285. DPM_TABLE_452__MemoryInterval__SHIFT
128286. DPM_TABLE_452__MemoryThermThrottleEnable_MASK
128287. DPM_TABLE_452__MemoryThermThrottleEnable__SHIFT
128288. DPM_TABLE_452__Smio_9_MASK
128289. DPM_TABLE_452__Smio_9__SHIFT
128290. DPM_TABLE_453__PhaseResponseTime_MASK
128291. DPM_TABLE_453__PhaseResponseTime__SHIFT
128292. DPM_TABLE_453__Smio_10_MASK
128293. DPM_TABLE_453__Smio_10__SHIFT
128294. DPM_TABLE_453__VoltageResponseTime_MASK
128295. DPM_TABLE_453__VoltageResponseTime__SHIFT
128296. DPM_TABLE_454__DTEInterval_MASK
128297. DPM_TABLE_454__DTEInterval__SHIFT
128298. DPM_TABLE_454__DTEMode_MASK
128299. DPM_TABLE_454__DTEMode__SHIFT
128300. DPM_TABLE_454__PCIeBootLinkLevel_MASK
128301. DPM_TABLE_454__PCIeBootLinkLevel__SHIFT
128302. DPM_TABLE_454__PCIeGenInterval_MASK
128303. DPM_TABLE_454__PCIeGenInterval__SHIFT
128304. DPM_TABLE_454__Smio_11_MASK
128305. DPM_TABLE_454__Smio_11__SHIFT
128306. DPM_TABLE_455__AcDcGpio_MASK
128307. DPM_TABLE_455__AcDcGpio__SHIFT
128308. DPM_TABLE_455__SVI2Enable_MASK
128309. DPM_TABLE_455__SVI2Enable__SHIFT
128310. DPM_TABLE_455__Smio_12_MASK
128311. DPM_TABLE_455__Smio_12__SHIFT
128312. DPM_TABLE_455__ThermGpio_MASK
128313. DPM_TABLE_455__ThermGpio__SHIFT
128314. DPM_TABLE_455__VRHotGpio_MASK
128315. DPM_TABLE_455__VRHotGpio__SHIFT
128316. DPM_TABLE_456__PPM_PkgPwrLimit_MASK
128317. DPM_TABLE_456__PPM_PkgPwrLimit__SHIFT
128318. DPM_TABLE_456__PPM_TemperatureLimit_MASK
128319. DPM_TABLE_456__PPM_TemperatureLimit__SHIFT
128320. DPM_TABLE_456__Smio_13_MASK
128321. DPM_TABLE_456__Smio_13__SHIFT
128322. DPM_TABLE_457__DefaultTdp_MASK
128323. DPM_TABLE_457__DefaultTdp__SHIFT
128324. DPM_TABLE_457__Smio_14_MASK
128325. DPM_TABLE_457__Smio_14__SHIFT
128326. DPM_TABLE_457__TargetTdp_MASK
128327. DPM_TABLE_457__TargetTdp__SHIFT
128328. DPM_TABLE_458__FpsHighThreshold_MASK
128329. DPM_TABLE_458__FpsHighThreshold__SHIFT
128330. DPM_TABLE_458__FpsLowThreshold_MASK
128331. DPM_TABLE_458__FpsLowThreshold__SHIFT
128332. DPM_TABLE_458__Smio_15_MASK
128333. DPM_TABLE_458__Smio_15__SHIFT
128334. DPM_TABLE_459__BAPMTI_R_0_0_0_MASK
128335. DPM_TABLE_459__BAPMTI_R_0_0_0__SHIFT
128336. DPM_TABLE_459__BAPMTI_R_0_1_0_MASK
128337. DPM_TABLE_459__BAPMTI_R_0_1_0__SHIFT
128338. DPM_TABLE_459__Smio_16_MASK
128339. DPM_TABLE_459__Smio_16__SHIFT
128340. DPM_TABLE_45__GraphicsLevel_3_ActivityLevel_MASK
128341. DPM_TABLE_45__GraphicsLevel_3_ActivityLevel__SHIFT
128342. DPM_TABLE_45__GraphicsLevel_3_VidOffset_MASK
128343. DPM_TABLE_45__GraphicsLevel_3_VidOffset__SHIFT
128344. DPM_TABLE_45__GraphicsLevel_3_Vid_MASK
128345. DPM_TABLE_45__GraphicsLevel_3_Vid__SHIFT
128346. DPM_TABLE_45__VddcLevel_4_Smio_MASK
128347. DPM_TABLE_45__VddcLevel_4_Smio__SHIFT
128348. DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK
128349. DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT
128350. DPM_TABLE_45__VddcLevel_4_padding_MASK
128351. DPM_TABLE_45__VddcLevel_4_padding__SHIFT
128352. DPM_TABLE_45__VddcTable_2_MASK
128353. DPM_TABLE_45__VddcTable_2__SHIFT
128354. DPM_TABLE_45__VddcTable_3_MASK
128355. DPM_TABLE_45__VddcTable_3__SHIFT
128356. DPM_TABLE_460__BAPMTI_R_0_2_0_MASK
128357. DPM_TABLE_460__BAPMTI_R_0_2_0__SHIFT
128358. DPM_TABLE_460__BAPMTI_R_1_0_0_MASK
128359. DPM_TABLE_460__BAPMTI_R_1_0_0__SHIFT
128360. DPM_TABLE_460__Smio_17_MASK
128361. DPM_TABLE_460__Smio_17__SHIFT
128362. DPM_TABLE_461__BAPMTI_R_1_1_0_MASK
128363. DPM_TABLE_461__BAPMTI_R_1_1_0__SHIFT
128364. DPM_TABLE_461__BAPMTI_R_1_2_0_MASK
128365. DPM_TABLE_461__BAPMTI_R_1_2_0__SHIFT
128366. DPM_TABLE_461__Smio_18_MASK
128367. DPM_TABLE_461__Smio_18__SHIFT
128368. DPM_TABLE_462__BAPMTI_R_2_0_0_MASK
128369. DPM_TABLE_462__BAPMTI_R_2_0_0__SHIFT
128370. DPM_TABLE_462__BAPMTI_R_2_1_0_MASK
128371. DPM_TABLE_462__BAPMTI_R_2_1_0__SHIFT
128372. DPM_TABLE_462__Smio_19_MASK
128373. DPM_TABLE_462__Smio_19__SHIFT
128374. DPM_TABLE_463__BAPMTI_R_2_2_0_MASK
128375. DPM_TABLE_463__BAPMTI_R_2_2_0__SHIFT
128376. DPM_TABLE_463__BAPMTI_R_3_0_0_MASK
128377. DPM_TABLE_463__BAPMTI_R_3_0_0__SHIFT
128378. DPM_TABLE_463__Smio_20_MASK
128379. DPM_TABLE_463__Smio_20__SHIFT
128380. DPM_TABLE_464__BAPMTI_R_3_1_0_MASK
128381. DPM_TABLE_464__BAPMTI_R_3_1_0__SHIFT
128382. DPM_TABLE_464__BAPMTI_R_3_2_0_MASK
128383. DPM_TABLE_464__BAPMTI_R_3_2_0__SHIFT
128384. DPM_TABLE_464__Smio_21_MASK
128385. DPM_TABLE_464__Smio_21__SHIFT
128386. DPM_TABLE_465__BAPMTI_R_4_0_0_MASK
128387. DPM_TABLE_465__BAPMTI_R_4_0_0__SHIFT
128388. DPM_TABLE_465__BAPMTI_R_4_1_0_MASK
128389. DPM_TABLE_465__BAPMTI_R_4_1_0__SHIFT
128390. DPM_TABLE_465__Smio_22_MASK
128391. DPM_TABLE_465__Smio_22__SHIFT
128392. DPM_TABLE_466__BAPMTI_RC_0_0_0_MASK
128393. DPM_TABLE_466__BAPMTI_RC_0_0_0__SHIFT
128394. DPM_TABLE_466__BAPMTI_R_4_2_0_MASK
128395. DPM_TABLE_466__BAPMTI_R_4_2_0__SHIFT
128396. DPM_TABLE_466__Smio_23_MASK
128397. DPM_TABLE_466__Smio_23__SHIFT
128398. DPM_TABLE_467__BAPMTI_RC_0_1_0_MASK
128399. DPM_TABLE_467__BAPMTI_RC_0_1_0__SHIFT
128400. DPM_TABLE_467__BAPMTI_RC_0_2_0_MASK
128401. DPM_TABLE_467__BAPMTI_RC_0_2_0__SHIFT
128402. DPM_TABLE_467__Smio_24_MASK
128403. DPM_TABLE_467__Smio_24__SHIFT
128404. DPM_TABLE_468__BAPMTI_RC_1_0_0_MASK
128405. DPM_TABLE_468__BAPMTI_RC_1_0_0__SHIFT
128406. DPM_TABLE_468__BAPMTI_RC_1_1_0_MASK
128407. DPM_TABLE_468__BAPMTI_RC_1_1_0__SHIFT
128408. DPM_TABLE_468__Smio_25_MASK
128409. DPM_TABLE_468__Smio_25__SHIFT
128410. DPM_TABLE_469__BAPMTI_RC_1_2_0_MASK
128411. DPM_TABLE_469__BAPMTI_RC_1_2_0__SHIFT
128412. DPM_TABLE_469__BAPMTI_RC_2_0_0_MASK
128413. DPM_TABLE_469__BAPMTI_RC_2_0_0__SHIFT
128414. DPM_TABLE_469__Smio_26_MASK
128415. DPM_TABLE_469__Smio_26__SHIFT
128416. DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1_MASK
128417. DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1__SHIFT
128418. DPM_TABLE_46__GraphicsLevel_3_GnbSlow_MASK
128419. DPM_TABLE_46__GraphicsLevel_3_GnbSlow__SHIFT
128420. DPM_TABLE_46__GraphicsLevel_3_PowerThrottle_MASK
128421. DPM_TABLE_46__GraphicsLevel_3_PowerThrottle__SHIFT
128422. DPM_TABLE_46__GraphicsLevel_3_SclkDid_MASK
128423. DPM_TABLE_46__GraphicsLevel_3_SclkDid__SHIFT
128424. DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK
128425. DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT
128426. DPM_TABLE_46__VddcLevel_5_Voltage_MASK
128427. DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT
128428. DPM_TABLE_46__VddcTable_4_MASK
128429. DPM_TABLE_46__VddcTable_4__SHIFT
128430. DPM_TABLE_46__VddcTable_5_MASK
128431. DPM_TABLE_46__VddcTable_5__SHIFT
128432. DPM_TABLE_470__BAPMTI_RC_2_1_0_MASK
128433. DPM_TABLE_470__BAPMTI_RC_2_1_0__SHIFT
128434. DPM_TABLE_470__BAPMTI_RC_2_2_0_MASK
128435. DPM_TABLE_470__BAPMTI_RC_2_2_0__SHIFT
128436. DPM_TABLE_470__Smio_27_MASK
128437. DPM_TABLE_470__Smio_27__SHIFT
128438. DPM_TABLE_471__BAPMTI_RC_3_0_0_MASK
128439. DPM_TABLE_471__BAPMTI_RC_3_0_0__SHIFT
128440. DPM_TABLE_471__BAPMTI_RC_3_1_0_MASK
128441. DPM_TABLE_471__BAPMTI_RC_3_1_0__SHIFT
128442. DPM_TABLE_471__Smio_28_MASK
128443. DPM_TABLE_471__Smio_28__SHIFT
128444. DPM_TABLE_472__BAPMTI_RC_3_2_0_MASK
128445. DPM_TABLE_472__BAPMTI_RC_3_2_0__SHIFT
128446. DPM_TABLE_472__BAPMTI_RC_4_0_0_MASK
128447. DPM_TABLE_472__BAPMTI_RC_4_0_0__SHIFT
128448. DPM_TABLE_472__Smio_29_MASK
128449. DPM_TABLE_472__Smio_29__SHIFT
128450. DPM_TABLE_473__BAPMTI_RC_4_1_0_MASK
128451. DPM_TABLE_473__BAPMTI_RC_4_1_0__SHIFT
128452. DPM_TABLE_473__BAPMTI_RC_4_2_0_MASK
128453. DPM_TABLE_473__BAPMTI_RC_4_2_0__SHIFT
128454. DPM_TABLE_473__Smio_30_MASK
128455. DPM_TABLE_473__Smio_30__SHIFT
128456. DPM_TABLE_474__DTEAmbientTempBase_MASK
128457. DPM_TABLE_474__DTEAmbientTempBase__SHIFT
128458. DPM_TABLE_474__DTETjOffset_MASK
128459. DPM_TABLE_474__DTETjOffset__SHIFT
128460. DPM_TABLE_474__GpuTjHyst_MASK
128461. DPM_TABLE_474__GpuTjHyst__SHIFT
128462. DPM_TABLE_474__GpuTjMax_MASK
128463. DPM_TABLE_474__GpuTjMax__SHIFT
128464. DPM_TABLE_474__Smio_31_MASK
128465. DPM_TABLE_474__Smio_31__SHIFT
128466. DPM_TABLE_475
128467. DPM_TABLE_475__AcpBootLevel_MASK
128468. DPM_TABLE_475__AcpBootLevel__SHIFT
128469. DPM_TABLE_475__BootVoltage_Phases_MASK
128470. DPM_TABLE_475__BootVoltage_Phases__SHIFT
128471. DPM_TABLE_475__BootVoltage_VddGfx_MASK
128472. DPM_TABLE_475__BootVoltage_VddGfx__SHIFT
128473. DPM_TABLE_475__BootVoltage_Vddc_MASK
128474. DPM_TABLE_475__BootVoltage_Vddc__SHIFT
128475. DPM_TABLE_475__BootVoltage_Vddci_MASK
128476. DPM_TABLE_475__BootVoltage_Vddci__SHIFT
128477. DPM_TABLE_475__SamuBootLevel_MASK
128478. DPM_TABLE_475__SamuBootLevel__SHIFT
128479. DPM_TABLE_475__UvdBootLevel_MASK
128480. DPM_TABLE_475__UvdBootLevel__SHIFT
128481. DPM_TABLE_475__VceBootLevel_MASK
128482. DPM_TABLE_475__VceBootLevel__SHIFT
128483. DPM_TABLE_476__ACPInterval_MASK
128484. DPM_TABLE_476__ACPInterval__SHIFT
128485. DPM_TABLE_476__BAPM_TEMP_GRADIENT_MASK
128486. DPM_TABLE_476__BAPM_TEMP_GRADIENT__SHIFT
128487. DPM_TABLE_476__SAMUInterval_MASK
128488. DPM_TABLE_476__SAMUInterval__SHIFT
128489. DPM_TABLE_476__UVDInterval_MASK
128490. DPM_TABLE_476__UVDInterval__SHIFT
128491. DPM_TABLE_476__VCEInterval_MASK
128492. DPM_TABLE_476__VCEInterval__SHIFT
128493. DPM_TABLE_477__GraphicsBootLevel_MASK
128494. DPM_TABLE_477__GraphicsBootLevel__SHIFT
128495. DPM_TABLE_477__GraphicsInterval_MASK
128496. DPM_TABLE_477__GraphicsInterval__SHIFT
128497. DPM_TABLE_477__GraphicsThermThrottleEnable_MASK
128498. DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT
128499. DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK
128500. DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT
128501. DPM_TABLE_477__LowSclkInterruptThreshold_MASK
128502. DPM_TABLE_477__LowSclkInterruptThreshold__SHIFT
128503. DPM_TABLE_478__TemperatureLimitHigh_MASK
128504. DPM_TABLE_478__TemperatureLimitHigh__SHIFT
128505. DPM_TABLE_478__ThermalInterval_MASK
128506. DPM_TABLE_478__ThermalInterval__SHIFT
128507. DPM_TABLE_478__VddGfxReChkWait_MASK
128508. DPM_TABLE_478__VddGfxReChkWait__SHIFT
128509. DPM_TABLE_478__VoltageInterval_MASK
128510. DPM_TABLE_478__VoltageInterval__SHIFT
128511. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK
128512. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT
128513. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK
128514. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT
128515. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK
128516. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT
128517. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK
128518. DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT
128519. DPM_TABLE_479__MemoryBootLevel_MASK
128520. DPM_TABLE_479__MemoryBootLevel__SHIFT
128521. DPM_TABLE_479__MemoryVoltageChangeEnable_MASK
128522. DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT
128523. DPM_TABLE_479__TemperatureLimitLow_MASK
128524. DPM_TABLE_479__TemperatureLimitLow__SHIFT
128525. DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark_MASK
128526. DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark__SHIFT
128527. DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity_MASK
128528. DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity__SHIFT
128529. DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle_MASK
128530. DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle__SHIFT
128531. DPM_TABLE_47__GraphicsLevel_3_UpHyst_MASK
128532. DPM_TABLE_47__GraphicsLevel_3_UpHyst__SHIFT
128533. DPM_TABLE_47__VddcLevel_5_Smio_MASK
128534. DPM_TABLE_47__VddcLevel_5_Smio__SHIFT
128535. DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK
128536. DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT
128537. DPM_TABLE_47__VddcLevel_5_padding_MASK
128538. DPM_TABLE_47__VddcLevel_5_padding__SHIFT
128539. DPM_TABLE_47__VddcTable_6_MASK
128540. DPM_TABLE_47__VddcTable_6__SHIFT
128541. DPM_TABLE_47__VddcTable_7_MASK
128542. DPM_TABLE_47__VddcTable_7__SHIFT
128543. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK
128544. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT
128545. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK
128546. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT
128547. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK
128548. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT
128549. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK
128550. DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT
128551. DPM_TABLE_480__MemoryInterval_MASK
128552. DPM_TABLE_480__MemoryInterval__SHIFT
128553. DPM_TABLE_480__MemoryThermThrottleEnable_MASK
128554. DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT
128555. DPM_TABLE_480__VddcVddciDelta_MASK
128556. DPM_TABLE_480__VddcVddciDelta__SHIFT
128557. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK
128558. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT
128559. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK
128560. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT
128561. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK
128562. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT
128563. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK
128564. DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT
128565. DPM_TABLE_481__PhaseResponseTime_MASK
128566. DPM_TABLE_481__PhaseResponseTime__SHIFT
128567. DPM_TABLE_481__VoltageResponseTime_MASK
128568. DPM_TABLE_481__VoltageResponseTime__SHIFT
128569. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK
128570. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT
128571. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK
128572. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT
128573. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK
128574. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT
128575. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK
128576. DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT
128577. DPM_TABLE_482__DTEInterval_MASK
128578. DPM_TABLE_482__DTEInterval__SHIFT
128579. DPM_TABLE_482__DTEMode_MASK
128580. DPM_TABLE_482__DTEMode__SHIFT
128581. DPM_TABLE_482__PCIeBootLinkLevel_MASK
128582. DPM_TABLE_482__PCIeBootLinkLevel__SHIFT
128583. DPM_TABLE_482__PCIeGenInterval_MASK
128584. DPM_TABLE_482__PCIeGenInterval__SHIFT
128585. DPM_TABLE_483__AcDcGpio_MASK
128586. DPM_TABLE_483__AcDcGpio__SHIFT
128587. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK
128588. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT
128589. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK
128590. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT
128591. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK
128592. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT
128593. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK
128594. DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT
128595. DPM_TABLE_483__SVI2Enable_MASK
128596. DPM_TABLE_483__SVI2Enable__SHIFT
128597. DPM_TABLE_483__ThermGpio_MASK
128598. DPM_TABLE_483__ThermGpio__SHIFT
128599. DPM_TABLE_483__VRHotGpio_MASK
128600. DPM_TABLE_483__VRHotGpio__SHIFT
128601. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK
128602. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT
128603. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK
128604. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT
128605. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK
128606. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT
128607. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK
128608. DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT
128609. DPM_TABLE_484__DisplayCac_MASK
128610. DPM_TABLE_484__DisplayCac__SHIFT
128611. DPM_TABLE_484__PPM_PkgPwrLimit_MASK
128612. DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT
128613. DPM_TABLE_484__PPM_TemperatureLimit_MASK
128614. DPM_TABLE_484__PPM_TemperatureLimit__SHIFT
128615. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK
128616. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT
128617. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK
128618. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT
128619. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK
128620. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT
128621. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK
128622. DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT
128623. DPM_TABLE_485__DefaultTdp_MASK
128624. DPM_TABLE_485__DefaultTdp__SHIFT
128625. DPM_TABLE_485__MaxPwr_MASK
128626. DPM_TABLE_485__MaxPwr__SHIFT
128627. DPM_TABLE_485__NomPwr_MASK
128628. DPM_TABLE_485__NomPwr__SHIFT
128629. DPM_TABLE_485__TargetTdp_MASK
128630. DPM_TABLE_485__TargetTdp__SHIFT
128631. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK
128632. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT
128633. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK
128634. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT
128635. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK
128636. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT
128637. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK
128638. DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT
128639. DPM_TABLE_486__FpsHighThreshold_MASK
128640. DPM_TABLE_486__FpsHighThreshold__SHIFT
128641. DPM_TABLE_486__FpsLowThreshold_MASK
128642. DPM_TABLE_486__FpsLowThreshold__SHIFT
128643. DPM_TABLE_487__BAPMTI_R_0_0_0_MASK
128644. DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT
128645. DPM_TABLE_487__BAPMTI_R_0_1_0_MASK
128646. DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT
128647. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK
128648. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT
128649. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK
128650. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT
128651. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK
128652. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT
128653. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK
128654. DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT
128655. DPM_TABLE_488__BAPMTI_R_0_2_0_MASK
128656. DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT
128657. DPM_TABLE_488__BAPMTI_R_1_0_0_MASK
128658. DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT
128659. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK
128660. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT
128661. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK
128662. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT
128663. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK
128664. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT
128665. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK
128666. DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT
128667. DPM_TABLE_489__BAPMTI_R_1_1_0_MASK
128668. DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT
128669. DPM_TABLE_489__BAPMTI_R_1_2_0_MASK
128670. DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT
128671. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK
128672. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT
128673. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK
128674. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT
128675. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK
128676. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT
128677. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK
128678. DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT
128679. DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl_MASK
128680. DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl__SHIFT
128681. DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId_MASK
128682. DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId__SHIFT
128683. DPM_TABLE_48__GraphicsLevel_3_DownHyst_MASK
128684. DPM_TABLE_48__GraphicsLevel_3_DownHyst__SHIFT
128685. DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst_MASK
128686. DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst__SHIFT
128687. DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK
128688. DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT
128689. DPM_TABLE_48__VddcLevel_6_Voltage_MASK
128690. DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT
128691. DPM_TABLE_48__VddcTable_8_MASK
128692. DPM_TABLE_48__VddcTable_8__SHIFT
128693. DPM_TABLE_48__VddcTable_9_MASK
128694. DPM_TABLE_48__VddcTable_9__SHIFT
128695. DPM_TABLE_490__BAPMTI_R_2_0_0_MASK
128696. DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT
128697. DPM_TABLE_490__BAPMTI_R_2_1_0_MASK
128698. DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT
128699. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK
128700. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT
128701. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK
128702. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT
128703. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK
128704. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT
128705. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK
128706. DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT
128707. DPM_TABLE_491__BAPMTI_R_2_2_0_MASK
128708. DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT
128709. DPM_TABLE_491__BAPMTI_R_3_0_0_MASK
128710. DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT
128711. DPM_TABLE_492__BAPMTI_R_3_1_0_MASK
128712. DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT
128713. DPM_TABLE_492__BAPMTI_R_3_2_0_MASK
128714. DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT
128715. DPM_TABLE_493__BAPMTI_R_4_0_0_MASK
128716. DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT
128717. DPM_TABLE_493__BAPMTI_R_4_1_0_MASK
128718. DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT
128719. DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK
128720. DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT
128721. DPM_TABLE_494__BAPMTI_R_4_2_0_MASK
128722. DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT
128723. DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK
128724. DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT
128725. DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK
128726. DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT
128727. DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK
128728. DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT
128729. DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK
128730. DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT
128731. DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK
128732. DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT
128733. DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK
128734. DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT
128735. DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK
128736. DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT
128737. DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK
128738. DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT
128739. DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK
128740. DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT
128741. DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK
128742. DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT
128743. DPM_TABLE_49__GraphicsLevel_3_reserved_MASK
128744. DPM_TABLE_49__GraphicsLevel_3_reserved__SHIFT
128745. DPM_TABLE_49__VddcLevel_6_Smio_MASK
128746. DPM_TABLE_49__VddcLevel_6_Smio__SHIFT
128747. DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK
128748. DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT
128749. DPM_TABLE_49__VddcLevel_6_padding_MASK
128750. DPM_TABLE_49__VddcLevel_6_padding__SHIFT
128751. DPM_TABLE_49__VddcTable_10_MASK
128752. DPM_TABLE_49__VddcTable_10__SHIFT
128753. DPM_TABLE_49__VddcTable_11_MASK
128754. DPM_TABLE_49__VddcTable_11__SHIFT
128755. DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim_MASK
128756. DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim__SHIFT
128757. DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK
128758. DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT
128759. DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK
128760. DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT
128761. DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK
128762. DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT
128763. DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK
128764. DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT
128765. DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK
128766. DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT
128767. DPM_TABLE_502__DTEAmbientTempBase_MASK
128768. DPM_TABLE_502__DTEAmbientTempBase__SHIFT
128769. DPM_TABLE_502__DTETjOffset_MASK
128770. DPM_TABLE_502__DTETjOffset__SHIFT
128771. DPM_TABLE_502__GpuTjHyst_MASK
128772. DPM_TABLE_502__GpuTjHyst__SHIFT
128773. DPM_TABLE_502__GpuTjMax_MASK
128774. DPM_TABLE_502__GpuTjMax__SHIFT
128775. DPM_TABLE_503__BootVddc_MASK
128776. DPM_TABLE_503__BootVddc__SHIFT
128777. DPM_TABLE_503__BootVddci_MASK
128778. DPM_TABLE_503__BootVddci__SHIFT
128779. DPM_TABLE_504__BootMVdd_MASK
128780. DPM_TABLE_504__BootMVdd__SHIFT
128781. DPM_TABLE_504__PccGpio_MASK
128782. DPM_TABLE_504__PccGpio__SHIFT
128783. DPM_TABLE_504__padding_MASK
128784. DPM_TABLE_504__padding__SHIFT
128785. DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK
128786. DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT
128787. DPM_TABLE_505__DRAM_LOG_ADDR_H_MASK
128788. DPM_TABLE_505__DRAM_LOG_ADDR_H__SHIFT
128789. DPM_TABLE_506__DRAM_LOG_ADDR_L_MASK
128790. DPM_TABLE_506__DRAM_LOG_ADDR_L__SHIFT
128791. DPM_TABLE_506__LowSclkInterruptThreshold_MASK
128792. DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT
128793. DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H_MASK
128794. DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H__SHIFT
128795. DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L_MASK
128796. DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L__SHIFT
128797. DPM_TABLE_509__DRAM_LOG_BUFF_SIZE_MASK
128798. DPM_TABLE_509__DRAM_LOG_BUFF_SIZE__SHIFT
128799. DPM_TABLE_50__GraphicsLevel_4_MinVddNb_MASK
128800. DPM_TABLE_50__GraphicsLevel_4_MinVddNb__SHIFT
128801. DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK
128802. DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT
128803. DPM_TABLE_50__VddcLevel_7_Voltage_MASK
128804. DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT
128805. DPM_TABLE_50__VddcTable_12_MASK
128806. DPM_TABLE_50__VddcTable_12__SHIFT
128807. DPM_TABLE_50__VddcTable_13_MASK
128808. DPM_TABLE_50__VddcTable_13__SHIFT
128809. DPM_TABLE_510__BAPM_TEMP_GRADIENT_MASK
128810. DPM_TABLE_510__BAPM_TEMP_GRADIENT__SHIFT
128811. DPM_TABLE_51__GraphicsLevel_4_SclkFrequency_MASK
128812. DPM_TABLE_51__GraphicsLevel_4_SclkFrequency__SHIFT
128813. DPM_TABLE_51__VddcLevel_7_Smio_MASK
128814. DPM_TABLE_51__VddcLevel_7_Smio__SHIFT
128815. DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK
128816. DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT
128817. DPM_TABLE_51__VddcLevel_7_padding_MASK
128818. DPM_TABLE_51__VddcLevel_7_padding__SHIFT
128819. DPM_TABLE_51__VddcTable_14_MASK
128820. DPM_TABLE_51__VddcTable_14__SHIFT
128821. DPM_TABLE_51__VddcTable_15_MASK
128822. DPM_TABLE_51__VddcTable_15__SHIFT
128823. DPM_TABLE_52__GraphicsLevel_4_ActivityLevel_MASK
128824. DPM_TABLE_52__GraphicsLevel_4_ActivityLevel__SHIFT
128825. DPM_TABLE_52__GraphicsLevel_4_VidOffset_MASK
128826. DPM_TABLE_52__GraphicsLevel_4_VidOffset__SHIFT
128827. DPM_TABLE_52__GraphicsLevel_4_Vid_MASK
128828. DPM_TABLE_52__GraphicsLevel_4_Vid__SHIFT
128829. DPM_TABLE_52__VddGfxTable_0_MASK
128830. DPM_TABLE_52__VddGfxTable_0__SHIFT
128831. DPM_TABLE_52__VddGfxTable_1_MASK
128832. DPM_TABLE_52__VddGfxTable_1__SHIFT
128833. DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK
128834. DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT
128835. DPM_TABLE_52__VddciLevel_0_Voltage_MASK
128836. DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT
128837. DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1_MASK
128838. DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1__SHIFT
128839. DPM_TABLE_53__GraphicsLevel_4_GnbSlow_MASK
128840. DPM_TABLE_53__GraphicsLevel_4_GnbSlow__SHIFT
128841. DPM_TABLE_53__GraphicsLevel_4_PowerThrottle_MASK
128842. DPM_TABLE_53__GraphicsLevel_4_PowerThrottle__SHIFT
128843. DPM_TABLE_53__GraphicsLevel_4_SclkDid_MASK
128844. DPM_TABLE_53__GraphicsLevel_4_SclkDid__SHIFT
128845. DPM_TABLE_53__VddGfxTable_2_MASK
128846. DPM_TABLE_53__VddGfxTable_2__SHIFT
128847. DPM_TABLE_53__VddGfxTable_3_MASK
128848. DPM_TABLE_53__VddGfxTable_3__SHIFT
128849. DPM_TABLE_53__VddciLevel_0_Smio_MASK
128850. DPM_TABLE_53__VddciLevel_0_Smio__SHIFT
128851. DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK
128852. DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT
128853. DPM_TABLE_53__VddciLevel_0_padding_MASK
128854. DPM_TABLE_53__VddciLevel_0_padding__SHIFT
128855. DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark_MASK
128856. DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark__SHIFT
128857. DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity_MASK
128858. DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity__SHIFT
128859. DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle_MASK
128860. DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle__SHIFT
128861. DPM_TABLE_54__GraphicsLevel_4_UpHyst_MASK
128862. DPM_TABLE_54__GraphicsLevel_4_UpHyst__SHIFT
128863. DPM_TABLE_54__VddGfxTable_4_MASK
128864. DPM_TABLE_54__VddGfxTable_4__SHIFT
128865. DPM_TABLE_54__VddGfxTable_5_MASK
128866. DPM_TABLE_54__VddGfxTable_5__SHIFT
128867. DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK
128868. DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT
128869. DPM_TABLE_54__VddciLevel_1_Voltage_MASK
128870. DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT
128871. DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl_MASK
128872. DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl__SHIFT
128873. DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId_MASK
128874. DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId__SHIFT
128875. DPM_TABLE_55__GraphicsLevel_4_DownHyst_MASK
128876. DPM_TABLE_55__GraphicsLevel_4_DownHyst__SHIFT
128877. DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst_MASK
128878. DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst__SHIFT
128879. DPM_TABLE_55__VddGfxTable_6_MASK
128880. DPM_TABLE_55__VddGfxTable_6__SHIFT
128881. DPM_TABLE_55__VddGfxTable_7_MASK
128882. DPM_TABLE_55__VddGfxTable_7__SHIFT
128883. DPM_TABLE_55__VddciLevel_1_Smio_MASK
128884. DPM_TABLE_55__VddciLevel_1_Smio__SHIFT
128885. DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK
128886. DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT
128887. DPM_TABLE_55__VddciLevel_1_padding_MASK
128888. DPM_TABLE_55__VddciLevel_1_padding__SHIFT
128889. DPM_TABLE_56__GraphicsLevel_4_reserved_MASK
128890. DPM_TABLE_56__GraphicsLevel_4_reserved__SHIFT
128891. DPM_TABLE_56__VddGfxTable_8_MASK
128892. DPM_TABLE_56__VddGfxTable_8__SHIFT
128893. DPM_TABLE_56__VddGfxTable_9_MASK
128894. DPM_TABLE_56__VddGfxTable_9__SHIFT
128895. DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK
128896. DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT
128897. DPM_TABLE_56__VddciLevel_2_Voltage_MASK
128898. DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT
128899. DPM_TABLE_57__GraphicsLevel_5_MinVddNb_MASK
128900. DPM_TABLE_57__GraphicsLevel_5_MinVddNb__SHIFT
128901. DPM_TABLE_57__VddGfxTable_10_MASK
128902. DPM_TABLE_57__VddGfxTable_10__SHIFT
128903. DPM_TABLE_57__VddGfxTable_11_MASK
128904. DPM_TABLE_57__VddGfxTable_11__SHIFT
128905. DPM_TABLE_57__VddciLevel_2_Smio_MASK
128906. DPM_TABLE_57__VddciLevel_2_Smio__SHIFT
128907. DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK
128908. DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT
128909. DPM_TABLE_57__VddciLevel_2_padding_MASK
128910. DPM_TABLE_57__VddciLevel_2_padding__SHIFT
128911. DPM_TABLE_58__GraphicsLevel_5_SclkFrequency_MASK
128912. DPM_TABLE_58__GraphicsLevel_5_SclkFrequency__SHIFT
128913. DPM_TABLE_58__VddGfxTable_12_MASK
128914. DPM_TABLE_58__VddGfxTable_12__SHIFT
128915. DPM_TABLE_58__VddGfxTable_13_MASK
128916. DPM_TABLE_58__VddGfxTable_13__SHIFT
128917. DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK
128918. DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT
128919. DPM_TABLE_58__VddciLevel_3_Voltage_MASK
128920. DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT
128921. DPM_TABLE_59__GraphicsLevel_5_ActivityLevel_MASK
128922. DPM_TABLE_59__GraphicsLevel_5_ActivityLevel__SHIFT
128923. DPM_TABLE_59__GraphicsLevel_5_VidOffset_MASK
128924. DPM_TABLE_59__GraphicsLevel_5_VidOffset__SHIFT
128925. DPM_TABLE_59__GraphicsLevel_5_Vid_MASK
128926. DPM_TABLE_59__GraphicsLevel_5_Vid__SHIFT
128927. DPM_TABLE_59__VddGfxTable_14_MASK
128928. DPM_TABLE_59__VddGfxTable_14__SHIFT
128929. DPM_TABLE_59__VddGfxTable_15_MASK
128930. DPM_TABLE_59__VddGfxTable_15__SHIFT
128931. DPM_TABLE_59__VddciLevel_3_Smio_MASK
128932. DPM_TABLE_59__VddciLevel_3_Smio__SHIFT
128933. DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK
128934. DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT
128935. DPM_TABLE_59__VddciLevel_3_padding_MASK
128936. DPM_TABLE_59__VddciLevel_3_padding__SHIFT
128937. DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK
128938. DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT
128939. DPM_TABLE_5__GraphicsPIDController_StatePrecision_MASK
128940. DPM_TABLE_5__GraphicsPIDController_StatePrecision__SHIFT
128941. DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1_MASK
128942. DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1__SHIFT
128943. DPM_TABLE_60__GraphicsLevel_5_GnbSlow_MASK
128944. DPM_TABLE_60__GraphicsLevel_5_GnbSlow__SHIFT
128945. DPM_TABLE_60__GraphicsLevel_5_PowerThrottle_MASK
128946. DPM_TABLE_60__GraphicsLevel_5_PowerThrottle__SHIFT
128947. DPM_TABLE_60__GraphicsLevel_5_SclkDid_MASK
128948. DPM_TABLE_60__GraphicsLevel_5_SclkDid__SHIFT
128949. DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK
128950. DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT
128951. DPM_TABLE_60__MvddLevel_0_Voltage_MASK
128952. DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT
128953. DPM_TABLE_60__VddciTable_0_MASK
128954. DPM_TABLE_60__VddciTable_0__SHIFT
128955. DPM_TABLE_60__VddciTable_1_MASK
128956. DPM_TABLE_60__VddciTable_1__SHIFT
128957. DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark_MASK
128958. DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark__SHIFT
128959. DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity_MASK
128960. DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity__SHIFT
128961. DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle_MASK
128962. DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle__SHIFT
128963. DPM_TABLE_61__GraphicsLevel_5_UpHyst_MASK
128964. DPM_TABLE_61__GraphicsLevel_5_UpHyst__SHIFT
128965. DPM_TABLE_61__MvddLevel_0_Smio_MASK
128966. DPM_TABLE_61__MvddLevel_0_Smio__SHIFT
128967. DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK
128968. DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT
128969. DPM_TABLE_61__MvddLevel_0_padding_MASK
128970. DPM_TABLE_61__MvddLevel_0_padding__SHIFT
128971. DPM_TABLE_61__VddciTable_2_MASK
128972. DPM_TABLE_61__VddciTable_2__SHIFT
128973. DPM_TABLE_61__VddciTable_3_MASK
128974. DPM_TABLE_61__VddciTable_3__SHIFT
128975. DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl_MASK
128976. DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl__SHIFT
128977. DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId_MASK
128978. DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId__SHIFT
128979. DPM_TABLE_62__GraphicsLevel_5_DownHyst_MASK
128980. DPM_TABLE_62__GraphicsLevel_5_DownHyst__SHIFT
128981. DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst_MASK
128982. DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst__SHIFT
128983. DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK
128984. DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT
128985. DPM_TABLE_62__MvddLevel_1_Voltage_MASK
128986. DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT
128987. DPM_TABLE_62__VddciTable_4_MASK
128988. DPM_TABLE_62__VddciTable_4__SHIFT
128989. DPM_TABLE_62__VddciTable_5_MASK
128990. DPM_TABLE_62__VddciTable_5__SHIFT
128991. DPM_TABLE_63__GraphicsLevel_5_reserved_MASK
128992. DPM_TABLE_63__GraphicsLevel_5_reserved__SHIFT
128993. DPM_TABLE_63__MvddLevel_1_Smio_MASK
128994. DPM_TABLE_63__MvddLevel_1_Smio__SHIFT
128995. DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK
128996. DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT
128997. DPM_TABLE_63__MvddLevel_1_padding_MASK
128998. DPM_TABLE_63__MvddLevel_1_padding__SHIFT
128999. DPM_TABLE_63__VddciTable_6_MASK
129000. DPM_TABLE_63__VddciTable_6__SHIFT
129001. DPM_TABLE_63__VddciTable_7_MASK
129002. DPM_TABLE_63__VddciTable_7__SHIFT
129003. DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK
129004. DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT
129005. DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK
129006. DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT
129007. DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK
129008. DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT
129009. DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK
129010. DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT
129011. DPM_TABLE_64__GraphicsLevel_6_MinVddNb_MASK
129012. DPM_TABLE_64__GraphicsLevel_6_MinVddNb__SHIFT
129013. DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK
129014. DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT
129015. DPM_TABLE_64__MvddLevel_2_Voltage_MASK
129016. DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT
129017. DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK
129018. DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT
129019. DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK
129020. DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT
129021. DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK
129022. DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT
129023. DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK
129024. DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT
129025. DPM_TABLE_65__GraphicsLevel_6_SclkFrequency_MASK
129026. DPM_TABLE_65__GraphicsLevel_6_SclkFrequency__SHIFT
129027. DPM_TABLE_65__MvddLevel_2_Smio_MASK
129028. DPM_TABLE_65__MvddLevel_2_Smio__SHIFT
129029. DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK
129030. DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT
129031. DPM_TABLE_65__MvddLevel_2_padding_MASK
129032. DPM_TABLE_65__MvddLevel_2_padding__SHIFT
129033. DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK
129034. DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT
129035. DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK
129036. DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT
129037. DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK
129038. DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT
129039. DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK
129040. DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT
129041. DPM_TABLE_66__GraphicsLevel_6_ActivityLevel_MASK
129042. DPM_TABLE_66__GraphicsLevel_6_ActivityLevel__SHIFT
129043. DPM_TABLE_66__GraphicsLevel_6_VidOffset_MASK
129044. DPM_TABLE_66__GraphicsLevel_6_VidOffset__SHIFT
129045. DPM_TABLE_66__GraphicsLevel_6_Vid_MASK
129046. DPM_TABLE_66__GraphicsLevel_6_Vid__SHIFT
129047. DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK
129048. DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT
129049. DPM_TABLE_66__MvddLevel_3_Voltage_MASK
129050. DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT
129051. DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK
129052. DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT
129053. DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK
129054. DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT
129055. DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK
129056. DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT
129057. DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK
129058. DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT
129059. DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1_MASK
129060. DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1__SHIFT
129061. DPM_TABLE_67__GraphicsLevel_6_GnbSlow_MASK
129062. DPM_TABLE_67__GraphicsLevel_6_GnbSlow__SHIFT
129063. DPM_TABLE_67__GraphicsLevel_6_PowerThrottle_MASK
129064. DPM_TABLE_67__GraphicsLevel_6_PowerThrottle__SHIFT
129065. DPM_TABLE_67__GraphicsLevel_6_SclkDid_MASK
129066. DPM_TABLE_67__GraphicsLevel_6_SclkDid__SHIFT
129067. DPM_TABLE_67__MvddLevel_3_Smio_MASK
129068. DPM_TABLE_67__MvddLevel_3_Smio__SHIFT
129069. DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK
129070. DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT
129071. DPM_TABLE_67__MvddLevel_3_padding_MASK
129072. DPM_TABLE_67__MvddLevel_3_padding__SHIFT
129073. DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK
129074. DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT
129075. DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK
129076. DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT
129077. DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK
129078. DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT
129079. DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK
129080. DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT
129081. DPM_TABLE_68__GraphicsDpmLevelCount_MASK
129082. DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT
129083. DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark_MASK
129084. DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark__SHIFT
129085. DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity_MASK
129086. DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity__SHIFT
129087. DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle_MASK
129088. DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle__SHIFT
129089. DPM_TABLE_68__GraphicsLevel_6_UpHyst_MASK
129090. DPM_TABLE_68__GraphicsLevel_6_UpHyst__SHIFT
129091. DPM_TABLE_68__LinkLevelCount_MASK
129092. DPM_TABLE_68__LinkLevelCount__SHIFT
129093. DPM_TABLE_68__MasterDeepSleepControl_MASK
129094. DPM_TABLE_68__MasterDeepSleepControl__SHIFT
129095. DPM_TABLE_68__MemoryDpmLevelCount_MASK
129096. DPM_TABLE_68__MemoryDpmLevelCount__SHIFT
129097. DPM_TABLE_68__UvdLevelCount_MASK
129098. DPM_TABLE_68__UvdLevelCount__SHIFT
129099. DPM_TABLE_69__AcpLevelCount_MASK
129100. DPM_TABLE_69__AcpLevelCount__SHIFT
129101. DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK
129102. DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT
129103. DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK
129104. DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT
129105. DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK
129106. DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT
129107. DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK
129108. DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT
129109. DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl_MASK
129110. DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl__SHIFT
129111. DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId_MASK
129112. DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId__SHIFT
129113. DPM_TABLE_69__GraphicsLevel_6_DownHyst_MASK
129114. DPM_TABLE_69__GraphicsLevel_6_DownHyst__SHIFT
129115. DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst_MASK
129116. DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst__SHIFT
129117. DPM_TABLE_69__MasterDeepSleepControl_MASK
129118. DPM_TABLE_69__MasterDeepSleepControl__SHIFT
129119. DPM_TABLE_69__Reserved_0_MASK
129120. DPM_TABLE_69__Reserved_0__SHIFT
129121. DPM_TABLE_69__SamuLevelCount_MASK
129122. DPM_TABLE_69__SamuLevelCount__SHIFT
129123. DPM_TABLE_69__VceLevelCount_MASK
129124. DPM_TABLE_69__VceLevelCount__SHIFT
129125. DPM_TABLE_69__padding2_MASK
129126. DPM_TABLE_69__padding2__SHIFT
129127. DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK
129128. DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT
129129. DPM_TABLE_6__GraphicsPIDController_LfPrecision_MASK
129130. DPM_TABLE_6__GraphicsPIDController_LfPrecision__SHIFT
129131. DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK
129132. DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT
129133. DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK
129134. DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT
129135. DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK
129136. DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT
129137. DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK
129138. DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT
129139. DPM_TABLE_70__DefaultTdp_MASK
129140. DPM_TABLE_70__DefaultTdp__SHIFT
129141. DPM_TABLE_70__GraphicsLevel_6_reserved_MASK
129142. DPM_TABLE_70__GraphicsLevel_6_reserved__SHIFT
129143. DPM_TABLE_70__Reserved_0_MASK
129144. DPM_TABLE_70__Reserved_0__SHIFT
129145. DPM_TABLE_70__Reserved_1_MASK
129146. DPM_TABLE_70__Reserved_1__SHIFT
129147. DPM_TABLE_70__TargetTdp_MASK
129148. DPM_TABLE_70__TargetTdp__SHIFT
129149. DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK
129150. DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT
129151. DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK
129152. DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT
129153. DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK
129154. DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT
129155. DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK
129156. DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT
129157. DPM_TABLE_71__GraphicsLevel_7_MinVddNb_MASK
129158. DPM_TABLE_71__GraphicsLevel_7_MinVddNb__SHIFT
129159. DPM_TABLE_71__Reserved_1_MASK
129160. DPM_TABLE_71__Reserved_1__SHIFT
129161. DPM_TABLE_71__Reserved_2_MASK
129162. DPM_TABLE_71__Reserved_2__SHIFT
129163. DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK
129164. DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT
129165. DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK
129166. DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT
129167. DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK
129168. DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT
129169. DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK
129170. DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT
129171. DPM_TABLE_72__GraphicsLevel_7_SclkFrequency_MASK
129172. DPM_TABLE_72__GraphicsLevel_7_SclkFrequency__SHIFT
129173. DPM_TABLE_72__Reserved_2_MASK
129174. DPM_TABLE_72__Reserved_2__SHIFT
129175. DPM_TABLE_72__Reserved_3_MASK
129176. DPM_TABLE_72__Reserved_3__SHIFT
129177. DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK
129178. DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT
129179. DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK
129180. DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT
129181. DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK
129182. DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT
129183. DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK
129184. DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT
129185. DPM_TABLE_73__GraphicsLevel_7_ActivityLevel_MASK
129186. DPM_TABLE_73__GraphicsLevel_7_ActivityLevel__SHIFT
129187. DPM_TABLE_73__GraphicsLevel_7_VidOffset_MASK
129188. DPM_TABLE_73__GraphicsLevel_7_VidOffset__SHIFT
129189. DPM_TABLE_73__GraphicsLevel_7_Vid_MASK
129190. DPM_TABLE_73__GraphicsLevel_7_Vid__SHIFT
129191. DPM_TABLE_73__Reserved_3_MASK
129192. DPM_TABLE_73__Reserved_3__SHIFT
129193. DPM_TABLE_73__Reserved_4_MASK
129194. DPM_TABLE_73__Reserved_4__SHIFT
129195. DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK
129196. DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT
129197. DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK
129198. DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT
129199. DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK
129200. DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT
129201. DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK
129202. DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT
129203. DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK
129204. DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT
129205. DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1_MASK
129206. DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1__SHIFT
129207. DPM_TABLE_74__GraphicsLevel_7_GnbSlow_MASK
129208. DPM_TABLE_74__GraphicsLevel_7_GnbSlow__SHIFT
129209. DPM_TABLE_74__GraphicsLevel_7_PowerThrottle_MASK
129210. DPM_TABLE_74__GraphicsLevel_7_PowerThrottle__SHIFT
129211. DPM_TABLE_74__GraphicsLevel_7_SclkDid_MASK
129212. DPM_TABLE_74__GraphicsLevel_7_SclkDid__SHIFT
129213. DPM_TABLE_74__Reserved_4_MASK
129214. DPM_TABLE_74__Reserved_4__SHIFT
129215. DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK
129216. DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT
129217. DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK
129218. DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT
129219. DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK
129220. DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT
129221. DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK
129222. DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT
129223. DPM_TABLE_75__GraphicsLevel_0_Flags_MASK
129224. DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT
129225. DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK
129226. DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT
129227. DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark_MASK
129228. DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark__SHIFT
129229. DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity_MASK
129230. DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity__SHIFT
129231. DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle_MASK
129232. DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle__SHIFT
129233. DPM_TABLE_75__GraphicsLevel_7_UpHyst_MASK
129234. DPM_TABLE_75__GraphicsLevel_7_UpHyst__SHIFT
129235. DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK
129236. DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT
129237. DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK
129238. DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT
129239. DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK
129240. DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT
129241. DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK
129242. DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT
129243. DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK
129244. DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT
129245. DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK
129246. DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT
129247. DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl_MASK
129248. DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl__SHIFT
129249. DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId_MASK
129250. DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId__SHIFT
129251. DPM_TABLE_76__GraphicsLevel_7_DownHyst_MASK
129252. DPM_TABLE_76__GraphicsLevel_7_DownHyst__SHIFT
129253. DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst_MASK
129254. DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst__SHIFT
129255. DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK
129256. DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT
129257. DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK
129258. DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT
129259. DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK
129260. DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT
129261. DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK
129262. DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT
129263. DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK
129264. DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT
129265. DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK
129266. DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT
129267. DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK
129268. DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT
129269. DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK
129270. DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT
129271. DPM_TABLE_77__GraphicsLevel_7_reserved_MASK
129272. DPM_TABLE_77__GraphicsLevel_7_reserved__SHIFT
129273. DPM_TABLE_78__ACPILevel_Flags_MASK
129274. DPM_TABLE_78__ACPILevel_Flags__SHIFT
129275. DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK
129276. DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT
129277. DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK
129278. DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT
129279. DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK
129280. DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT
129281. DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK
129282. DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT
129283. DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK
129284. DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT
129285. DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK
129286. DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT
129287. DPM_TABLE_79__ACPILevel_MinVddNb_MASK
129288. DPM_TABLE_79__ACPILevel_MinVddNb__SHIFT
129289. DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK
129290. DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT
129291. DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK
129292. DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT
129293. DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK
129294. DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT
129295. DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK
129296. DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT
129297. DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK
129298. DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT
129299. DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK
129300. DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT
129301. DPM_TABLE_79__GraphicsLevel_0_padding1_0_MASK
129302. DPM_TABLE_79__GraphicsLevel_0_padding1_0__SHIFT
129303. DPM_TABLE_79__GraphicsLevel_0_padding1_1_MASK
129304. DPM_TABLE_79__GraphicsLevel_0_padding1_1__SHIFT
129305. DPM_TABLE_79__GraphicsLevel_0_padding1_MASK
129306. DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT
129307. DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK
129308. DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT
129309. DPM_TABLE_7__GraphicsPIDController_LfOffset_MASK
129310. DPM_TABLE_7__GraphicsPIDController_LfOffset__SHIFT
129311. DPM_TABLE_7__GraphicsPIDController_MaxState_MASK
129312. DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT
129313. DPM_TABLE_80__ACPILevel_SclkFrequency_MASK
129314. DPM_TABLE_80__ACPILevel_SclkFrequency__SHIFT
129315. DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK
129316. DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT
129317. DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK
129318. DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT
129319. DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK
129320. DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT
129321. DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK
129322. DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT
129323. DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK
129324. DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT
129325. DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK
129326. DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT
129327. DPM_TABLE_81__ACPILevel_DisplayWatermark_MASK
129328. DPM_TABLE_81__ACPILevel_DisplayWatermark__SHIFT
129329. DPM_TABLE_81__ACPILevel_ForceNbPs1_MASK
129330. DPM_TABLE_81__ACPILevel_ForceNbPs1__SHIFT
129331. DPM_TABLE_81__ACPILevel_GnbSlow_MASK
129332. DPM_TABLE_81__ACPILevel_GnbSlow__SHIFT
129333. DPM_TABLE_81__ACPILevel_SclkDid_MASK
129334. DPM_TABLE_81__ACPILevel_SclkDid__SHIFT
129335. DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK
129336. DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT
129337. DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK
129338. DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT
129339. DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK
129340. DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT
129341. DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK
129342. DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT
129343. DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK
129344. DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT
129345. DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK
129346. DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT
129347. DPM_TABLE_82__ACPILevel_DeepSleepDivId_MASK
129348. DPM_TABLE_82__ACPILevel_DeepSleepDivId__SHIFT
129349. DPM_TABLE_82__ACPILevel_padding_0_MASK
129350. DPM_TABLE_82__ACPILevel_padding_0__SHIFT
129351. DPM_TABLE_82__ACPILevel_padding_1_MASK
129352. DPM_TABLE_82__ACPILevel_padding_1__SHIFT
129353. DPM_TABLE_82__ACPILevel_padding_2_MASK
129354. DPM_TABLE_82__ACPILevel_padding_2__SHIFT
129355. DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK
129356. DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT
129357. DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK
129358. DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT
129359. DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK
129360. DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT
129361. DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK
129362. DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT
129363. DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK
129364. DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT
129365. DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK
129366. DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT
129367. DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK
129368. DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT
129369. DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK
129370. DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT
129371. DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK
129372. DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT
129373. DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK
129374. DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT
129375. DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK
129376. DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT
129377. DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK
129378. DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT
129379. DPM_TABLE_83__UvdLevel_0_VclkFrequency_MASK
129380. DPM_TABLE_83__UvdLevel_0_VclkFrequency__SHIFT
129381. DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK
129382. DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT
129383. DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK
129384. DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT
129385. DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK
129386. DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT
129387. DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK
129388. DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT
129389. DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK
129390. DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT
129391. DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK
129392. DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT
129393. DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK
129394. DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT
129395. DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK
129396. DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT
129397. DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK
129398. DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT
129399. DPM_TABLE_84__UvdLevel_0_DclkFrequency_MASK
129400. DPM_TABLE_84__UvdLevel_0_DclkFrequency__SHIFT
129401. DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK
129402. DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT
129403. DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK
129404. DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT
129405. DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK
129406. DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT
129407. DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK
129408. DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT
129409. DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK
129410. DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT
129411. DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK
129412. DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT
129413. DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK
129414. DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT
129415. DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK
129416. DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT
129417. DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK
129418. DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT
129419. DPM_TABLE_85__UvdLevel_0_DclkDivider_MASK
129420. DPM_TABLE_85__UvdLevel_0_DclkDivider__SHIFT
129421. DPM_TABLE_85__UvdLevel_0_MinVddNb_MASK
129422. DPM_TABLE_85__UvdLevel_0_MinVddNb__SHIFT
129423. DPM_TABLE_85__UvdLevel_0_VclkDivider_MASK
129424. DPM_TABLE_85__UvdLevel_0_VclkDivider__SHIFT
129425. DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK
129426. DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT
129427. DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK
129428. DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT
129429. DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK
129430. DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT
129431. DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK
129432. DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT
129433. DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK
129434. DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT
129435. DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK
129436. DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT
129437. DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK
129438. DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT
129439. DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK
129440. DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT
129441. DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK
129442. DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT
129443. DPM_TABLE_86__UvdLevel_0_DClkBypassCntl_MASK
129444. DPM_TABLE_86__UvdLevel_0_DClkBypassCntl__SHIFT
129445. DPM_TABLE_86__UvdLevel_0_VClkBypassCntl_MASK
129446. DPM_TABLE_86__UvdLevel_0_VClkBypassCntl__SHIFT
129447. DPM_TABLE_86__UvdLevel_0_padding_0_MASK
129448. DPM_TABLE_86__UvdLevel_0_padding_0__SHIFT
129449. DPM_TABLE_86__UvdLevel_0_padding_1_MASK
129450. DPM_TABLE_86__UvdLevel_0_padding_1__SHIFT
129451. DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK
129452. DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT
129453. DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK
129454. DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT
129455. DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK
129456. DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT
129457. DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK
129458. DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT
129459. DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK
129460. DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT
129461. DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK
129462. DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT
129463. DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK
129464. DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT
129465. DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK
129466. DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT
129467. DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK
129468. DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT
129469. DPM_TABLE_87__UvdLevel_1_VclkFrequency_MASK
129470. DPM_TABLE_87__UvdLevel_1_VclkFrequency__SHIFT
129471. DPM_TABLE_88__GraphicsDpmLevelCount_MASK
129472. DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT
129473. DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK
129474. DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT
129475. DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK
129476. DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT
129477. DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK
129478. DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT
129479. DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK
129480. DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT
129481. DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK
129482. DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT
129483. DPM_TABLE_88__LinkLevelCount_MASK
129484. DPM_TABLE_88__LinkLevelCount__SHIFT
129485. DPM_TABLE_88__MasterDeepSleepControl_MASK
129486. DPM_TABLE_88__MasterDeepSleepControl__SHIFT
129487. DPM_TABLE_88__MemoryDpmLevelCount_MASK
129488. DPM_TABLE_88__MemoryDpmLevelCount__SHIFT
129489. DPM_TABLE_88__UvdLevel_1_DclkFrequency_MASK
129490. DPM_TABLE_88__UvdLevel_1_DclkFrequency__SHIFT
129491. DPM_TABLE_89__AcpLevelCount_MASK
129492. DPM_TABLE_89__AcpLevelCount__SHIFT
129493. DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK
129494. DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT
129495. DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK
129496. DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT
129497. DPM_TABLE_89__GraphicsLevel_1_Flags_MASK
129498. DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT
129499. DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK
129500. DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT
129501. DPM_TABLE_89__SamuLevelCount_MASK
129502. DPM_TABLE_89__SamuLevelCount__SHIFT
129503. DPM_TABLE_89__UvdLevelCount_MASK
129504. DPM_TABLE_89__UvdLevelCount__SHIFT
129505. DPM_TABLE_89__UvdLevel_1_DclkDivider_MASK
129506. DPM_TABLE_89__UvdLevel_1_DclkDivider__SHIFT
129507. DPM_TABLE_89__UvdLevel_1_MinVddNb_MASK
129508. DPM_TABLE_89__UvdLevel_1_MinVddNb__SHIFT
129509. DPM_TABLE_89__UvdLevel_1_VclkDivider_MASK
129510. DPM_TABLE_89__UvdLevel_1_VclkDivider__SHIFT
129511. DPM_TABLE_89__VceLevelCount_MASK
129512. DPM_TABLE_89__VceLevelCount__SHIFT
129513. DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK
129514. DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT
129515. DPM_TABLE_8__GraphicsPIDController_MaxState_MASK
129516. DPM_TABLE_8__GraphicsPIDController_MaxState__SHIFT
129517. DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK
129518. DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT
129519. DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK
129520. DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT
129521. DPM_TABLE_90__Reserved_0_MASK
129522. DPM_TABLE_90__Reserved_0__SHIFT
129523. DPM_TABLE_90__ThermOutGpio_MASK
129524. DPM_TABLE_90__ThermOutGpio__SHIFT
129525. DPM_TABLE_90__ThermOutMode_MASK
129526. DPM_TABLE_90__ThermOutMode__SHIFT
129527. DPM_TABLE_90__ThermOutPolarity_MASK
129528. DPM_TABLE_90__ThermOutPolarity__SHIFT
129529. DPM_TABLE_90__UvdLevel_1_DClkBypassCntl_MASK
129530. DPM_TABLE_90__UvdLevel_1_DClkBypassCntl__SHIFT
129531. DPM_TABLE_90__UvdLevel_1_VClkBypassCntl_MASK
129532. DPM_TABLE_90__UvdLevel_1_VClkBypassCntl__SHIFT
129533. DPM_TABLE_90__UvdLevel_1_padding_0_MASK
129534. DPM_TABLE_90__UvdLevel_1_padding_0__SHIFT
129535. DPM_TABLE_90__UvdLevel_1_padding_1_MASK
129536. DPM_TABLE_90__UvdLevel_1_padding_1__SHIFT
129537. DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK
129538. DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT
129539. DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK
129540. DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT
129541. DPM_TABLE_91__Reserved_0_MASK
129542. DPM_TABLE_91__Reserved_0__SHIFT
129543. DPM_TABLE_91__Reserved_1_MASK
129544. DPM_TABLE_91__Reserved_1__SHIFT
129545. DPM_TABLE_91__UvdLevel_2_VclkFrequency_MASK
129546. DPM_TABLE_91__UvdLevel_2_VclkFrequency__SHIFT
129547. DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK
129548. DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT
129549. DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK
129550. DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT
129551. DPM_TABLE_92__Reserved_1_MASK
129552. DPM_TABLE_92__Reserved_1__SHIFT
129553. DPM_TABLE_92__Reserved_2_MASK
129554. DPM_TABLE_92__Reserved_2__SHIFT
129555. DPM_TABLE_92__UvdLevel_2_DclkFrequency_MASK
129556. DPM_TABLE_92__UvdLevel_2_DclkFrequency__SHIFT
129557. DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK
129558. DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT
129559. DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK
129560. DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT
129561. DPM_TABLE_93__GraphicsLevel_1_padding1_0_MASK
129562. DPM_TABLE_93__GraphicsLevel_1_padding1_0__SHIFT
129563. DPM_TABLE_93__GraphicsLevel_1_padding1_1_MASK
129564. DPM_TABLE_93__GraphicsLevel_1_padding1_1__SHIFT
129565. DPM_TABLE_93__GraphicsLevel_1_padding1_MASK
129566. DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT
129567. DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK
129568. DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT
129569. DPM_TABLE_93__Reserved_2_MASK
129570. DPM_TABLE_93__Reserved_2__SHIFT
129571. DPM_TABLE_93__Reserved_3_MASK
129572. DPM_TABLE_93__Reserved_3__SHIFT
129573. DPM_TABLE_93__UvdLevel_2_DclkDivider_MASK
129574. DPM_TABLE_93__UvdLevel_2_DclkDivider__SHIFT
129575. DPM_TABLE_93__UvdLevel_2_MinVddNb_MASK
129576. DPM_TABLE_93__UvdLevel_2_MinVddNb__SHIFT
129577. DPM_TABLE_93__UvdLevel_2_VclkDivider_MASK
129578. DPM_TABLE_93__UvdLevel_2_VclkDivider__SHIFT
129579. DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK
129580. DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT
129581. DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK
129582. DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT
129583. DPM_TABLE_94__Reserved_3_MASK
129584. DPM_TABLE_94__Reserved_3__SHIFT
129585. DPM_TABLE_94__Reserved_4_MASK
129586. DPM_TABLE_94__Reserved_4__SHIFT
129587. DPM_TABLE_94__UvdLevel_2_DClkBypassCntl_MASK
129588. DPM_TABLE_94__UvdLevel_2_DClkBypassCntl__SHIFT
129589. DPM_TABLE_94__UvdLevel_2_VClkBypassCntl_MASK
129590. DPM_TABLE_94__UvdLevel_2_VClkBypassCntl__SHIFT
129591. DPM_TABLE_94__UvdLevel_2_padding_0_MASK
129592. DPM_TABLE_94__UvdLevel_2_padding_0__SHIFT
129593. DPM_TABLE_94__UvdLevel_2_padding_1_MASK
129594. DPM_TABLE_94__UvdLevel_2_padding_1__SHIFT
129595. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK
129596. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT
129597. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK
129598. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT
129599. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK
129600. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT
129601. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK
129602. DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT
129603. DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK
129604. DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT
129605. DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK
129606. DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT
129607. DPM_TABLE_95__UvdLevel_3_VclkFrequency_MASK
129608. DPM_TABLE_95__UvdLevel_3_VclkFrequency__SHIFT
129609. DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK
129610. DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT
129611. DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK
129612. DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT
129613. DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK
129614. DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT
129615. DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK
129616. DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT
129617. DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK
129618. DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT
129619. DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK
129620. DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT
129621. DPM_TABLE_96__UvdLevel_3_DclkFrequency_MASK
129622. DPM_TABLE_96__UvdLevel_3_DclkFrequency__SHIFT
129623. DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK
129624. DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT
129625. DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK
129626. DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT
129627. DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK
129628. DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT
129629. DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK
129630. DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT
129631. DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK
129632. DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT
129633. DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK
129634. DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT
129635. DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK
129636. DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT
129637. DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK
129638. DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT
129639. DPM_TABLE_97__UvdLevel_3_DclkDivider_MASK
129640. DPM_TABLE_97__UvdLevel_3_DclkDivider__SHIFT
129641. DPM_TABLE_97__UvdLevel_3_MinVddNb_MASK
129642. DPM_TABLE_97__UvdLevel_3_MinVddNb__SHIFT
129643. DPM_TABLE_97__UvdLevel_3_VclkDivider_MASK
129644. DPM_TABLE_97__UvdLevel_3_VclkDivider__SHIFT
129645. DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK
129646. DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT
129647. DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK
129648. DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT
129649. DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK
129650. DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT
129651. DPM_TABLE_98__UvdLevel_3_DClkBypassCntl_MASK
129652. DPM_TABLE_98__UvdLevel_3_DClkBypassCntl__SHIFT
129653. DPM_TABLE_98__UvdLevel_3_VClkBypassCntl_MASK
129654. DPM_TABLE_98__UvdLevel_3_VClkBypassCntl__SHIFT
129655. DPM_TABLE_98__UvdLevel_3_padding_0_MASK
129656. DPM_TABLE_98__UvdLevel_3_padding_0__SHIFT
129657. DPM_TABLE_98__UvdLevel_3_padding_1_MASK
129658. DPM_TABLE_98__UvdLevel_3_padding_1__SHIFT
129659. DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK
129660. DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT
129661. DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK
129662. DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT
129663. DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK
129664. DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT
129665. DPM_TABLE_99__UvdLevel_4_VclkFrequency_MASK
129666. DPM_TABLE_99__UvdLevel_4_VclkFrequency__SHIFT
129667. DPM_TABLE_9__GraphicsPIDController_MaxLfFraction_MASK
129668. DPM_TABLE_9__GraphicsPIDController_MaxLfFraction__SHIFT
129669. DPM_TABLE_9__GraphicsPIDController_StateShift_MASK
129670. DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT
129671. DPM_TRIGER_TYPE
129672. DPM_VOLTAGE_EN
129673. DPNI_ALL_TCS
129674. DPNI_ALL_TC_FLOWS
129675. DPNI_BACKUP_POOL
129676. DPNI_BUF_LAYOUT_OPT_DATA_ALIGN
129677. DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM
129678. DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM
129679. DPNI_BUF_LAYOUT_OPT_FRAME_STATUS
129680. DPNI_BUF_LAYOUT_OPT_PARSER_RESULT
129681. DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE
129682. DPNI_BUF_LAYOUT_OPT_TIMESTAMP
129683. DPNI_CMD
129684. DPNI_CMDID_ADD_FS_ENT
129685. DPNI_CMDID_ADD_MAC_ADDR
129686. DPNI_CMDID_CLEAR_IRQ_STATUS
129687. DPNI_CMDID_CLOSE
129688. DPNI_CMDID_CLR_FS_ENT
129689. DPNI_CMDID_CLR_MAC_FILTERS
129690. DPNI_CMDID_CREATE
129691. DPNI_CMDID_DESTROY
129692. DPNI_CMDID_DISABLE
129693. DPNI_CMDID_ENABLE
129694. DPNI_CMDID_GET_API_VERSION
129695. DPNI_CMDID_GET_ATTR
129696. DPNI_CMDID_GET_BUFFER_LAYOUT
129697. DPNI_CMDID_GET_CONGESTION_NOTIFICATION
129698. DPNI_CMDID_GET_EARLY_DROP
129699. DPNI_CMDID_GET_IRQ
129700. DPNI_CMDID_GET_IRQ_ENABLE
129701. DPNI_CMDID_GET_IRQ_MASK
129702. DPNI_CMDID_GET_IRQ_STATUS
129703. DPNI_CMDID_GET_LINK_CFG
129704. DPNI_CMDID_GET_LINK_STATE
129705. DPNI_CMDID_GET_MAX_FRAME_LENGTH
129706. DPNI_CMDID_GET_MCAST_PROMISC
129707. DPNI_CMDID_GET_OFFLOAD
129708. DPNI_CMDID_GET_PORT_MAC_ADDR
129709. DPNI_CMDID_GET_PRIM_MAC
129710. DPNI_CMDID_GET_QDID
129711. DPNI_CMDID_GET_QUEUE
129712. DPNI_CMDID_GET_STATISTICS
129713. DPNI_CMDID_GET_TAILDROP
129714. DPNI_CMDID_GET_TX_DATA_OFFSET
129715. DPNI_CMDID_GET_UNICAST_PROMISC
129716. DPNI_CMDID_IS_ENABLED
129717. DPNI_CMDID_OPEN
129718. DPNI_CMDID_REMOVE_FS_ENT
129719. DPNI_CMDID_REMOVE_MAC_ADDR
129720. DPNI_CMDID_RESET
129721. DPNI_CMDID_SET_BUFFER_LAYOUT
129722. DPNI_CMDID_SET_CONGESTION_NOTIFICATION
129723. DPNI_CMDID_SET_EARLY_DROP
129724. DPNI_CMDID_SET_ERRORS_BEHAVIOR
129725. DPNI_CMDID_SET_IRQ
129726. DPNI_CMDID_SET_IRQ_ENABLE
129727. DPNI_CMDID_SET_IRQ_MASK
129728. DPNI_CMDID_SET_LINK_CFG
129729. DPNI_CMDID_SET_MAX_FRAME_LENGTH
129730. DPNI_CMDID_SET_MCAST_PROMISC
129731. DPNI_CMDID_SET_OFFLOAD
129732. DPNI_CMDID_SET_POOLS
129733. DPNI_CMDID_SET_PRIM_MAC
129734. DPNI_CMDID_SET_QUEUE
129735. DPNI_CMDID_SET_RX_FS_DIST
129736. DPNI_CMDID_SET_RX_HASH_DIST
129737. DPNI_CMDID_SET_RX_TC_DIST
129738. DPNI_CMDID_SET_TAILDROP
129739. DPNI_CMDID_SET_TX_CONFIRMATION_MODE
129740. DPNI_CMDID_SET_TX_SHAPING
129741. DPNI_CMDID_SET_UNICAST_PROMISC
129742. DPNI_CMD_BASE_VERSION
129743. DPNI_CMD_ID_OFFSET
129744. DPNI_CONGESTION_UNIT_BYTES
129745. DPNI_CONGESTION_UNIT_FRAMES
129746. DPNI_CP_GROUP
129747. DPNI_CP_QUEUE
129748. DPNI_DEST_DPCON
129749. DPNI_DEST_DPIO
129750. DPNI_DEST_NONE
129751. DPNI_DEST_TYPE_SHIFT
129752. DPNI_DEST_TYPE_SIZE
129753. DPNI_DIST_MODE_FS
129754. DPNI_DIST_MODE_HASH
129755. DPNI_DIST_MODE_NONE
129756. DPNI_DIST_MODE_SHIFT
129757. DPNI_DIST_MODE_SIZE
129758. DPNI_EFH_TYPE_SHIFT
129759. DPNI_EFH_TYPE_SIZE
129760. DPNI_ENABLE_SHIFT
129761. DPNI_ENABLE_SIZE
129762. DPNI_ENQUEUE_FQID_VER_MAJOR
129763. DPNI_ENQUEUE_FQID_VER_MINOR
129764. DPNI_ERROR_ACTION_CONTINUE
129765. DPNI_ERROR_ACTION_DISCARD
129766. DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE
129767. DPNI_ERROR_ACTION_SHIFT
129768. DPNI_ERROR_ACTION_SIZE
129769. DPNI_ERROR_EOFHE
129770. DPNI_ERROR_FLE
129771. DPNI_ERROR_FPE
129772. DPNI_ERROR_L3CE
129773. DPNI_ERROR_L4CE
129774. DPNI_ERROR_PHE
129775. DPNI_EXTRACT_TYPE_SHIFT
129776. DPNI_EXTRACT_TYPE_SIZE
129777. DPNI_FRAME_ANN_SHIFT
129778. DPNI_FRAME_ANN_SIZE
129779. DPNI_FS_MISS_DROP
129780. DPNI_FS_MISS_EXPLICIT_FLOWID
129781. DPNI_FS_MISS_HASH
129782. DPNI_FS_OPT_DISCARD
129783. DPNI_FS_OPT_SET_FLC
129784. DPNI_FS_OPT_SET_STASH_CONTROL
129785. DPNI_HOLD_ACTIVE_SHIFT
129786. DPNI_HOLD_ACTIVE_SIZE
129787. DPNI_IRQ_EVENT_ENDPOINT_CHANGED
129788. DPNI_IRQ_EVENT_LINK_CHANGED
129789. DPNI_IRQ_INDEX
129790. DPNI_LINK_OPT_ASYM_PAUSE
129791. DPNI_LINK_OPT_AUTONEG
129792. DPNI_LINK_OPT_HALF_DUPLEX
129793. DPNI_LINK_OPT_PAUSE
129794. DPNI_LINK_STATE_SHIFT
129795. DPNI_LINK_STATE_SIZE
129796. DPNI_MASK
129797. DPNI_MAX_DPBP
129798. DPNI_MAX_TC
129799. DPNI_MISS_ACTION_SHIFT
129800. DPNI_MISS_ACTION_SIZE
129801. DPNI_MULTICAST_FILTERS_SHIFT
129802. DPNI_MULTICAST_FILTERS_SIZE
129803. DPNI_NEW_FLOW_ID
129804. DPNI_OFF_RX_L3_CSUM
129805. DPNI_OFF_RX_L4_CSUM
129806. DPNI_OFF_TX_L3_CSUM
129807. DPNI_OFF_TX_L4_CSUM
129808. DPNI_OPT_HAS_KEY_MASKING
129809. DPNI_OPT_HAS_POLICING
129810. DPNI_OPT_NO_FS
129811. DPNI_OPT_NO_MAC_FILTER
129812. DPNI_OPT_SHARED_CONGESTION
129813. DPNI_OPT_TX_FRM_RELEASE
129814. DPNI_PASS_FS_SHIFT
129815. DPNI_PASS_FS_SIZE
129816. DPNI_PASS_PR_SHIFT
129817. DPNI_PASS_PR_SIZE
129818. DPNI_PASS_TS_SHIFT
129819. DPNI_PASS_TS_SIZE
129820. DPNI_PAUSE_VER_MAJOR
129821. DPNI_PAUSE_VER_MINOR
129822. DPNI_QUEUE_OPT_DEST
129823. DPNI_QUEUE_OPT_FLC
129824. DPNI_QUEUE_OPT_HOLD_ACTIVE
129825. DPNI_QUEUE_OPT_USER_CTX
129826. DPNI_QUEUE_RX
129827. DPNI_QUEUE_RX_ERR
129828. DPNI_QUEUE_TX
129829. DPNI_QUEUE_TX_CONFIRM
129830. DPNI_RX_DIST_KEY_VER_MAJOR
129831. DPNI_RX_DIST_KEY_VER_MINOR
129832. DPNI_RX_FS_DIST_ENABLE_SHIFT
129833. DPNI_RX_FS_DIST_ENABLE_SIZE
129834. DPNI_RX_HASH_DIST_ENABLE_SHIFT
129835. DPNI_RX_HASH_DIST_ENABLE_SIZE
129836. DPNI_STASH_CTRL_SHIFT
129837. DPNI_STASH_CTRL_SIZE
129838. DPNI_STATISTICS_CNT
129839. DPNI_TX_PENDING_VER_MAJOR
129840. DPNI_TX_PENDING_VER_MINOR
129841. DPNI_UNICAST_FILTERS_SHIFT
129842. DPNI_UNICAST_FILTERS_SIZE
129843. DPNI_VER_MAJOR
129844. DPNI_VER_MINOR
129845. DPOLICY_BG
129846. DPOLICY_FORCE
129847. DPOLICY_FSTRIM
129848. DPOLICY_UMOUNT
129849. DPOLL
129850. DPORT_ENABLE_LOOPCNT_DEFAULT
129851. DPORT_TEST_ELOOP
129852. DPORT_TEST_LINK
129853. DPORT_TEST_MAX
129854. DPORT_TEST_OLOOP
129855. DPORT_TEST_ROLOOP
129856. DPORT_TEST_ST_FAIL
129857. DPORT_TEST_ST_FINAL
129858. DPORT_TEST_ST_IDLE
129859. DPORT_TEST_ST_INPRG
129860. DPORT_TEST_ST_MAX
129861. DPORT_TEST_ST_RESPONDER
129862. DPORT_TEST_ST_SKIP
129863. DPORT_TEST_ST_STOPPED
129864. DPOT_AD5170_2FUSE
129865. DPOT_AD5170_2_3_FUSE
129866. DPOT_AD5170_2_3_OW
129867. DPOT_AD5172_3_A0
129868. DPOT_AD5270_1_2_4_CTRLREG
129869. DPOT_AD5270_1_2_4_RDAC
129870. DPOT_AD5270_1_2_4_READ_RDAC
129871. DPOT_AD5270_1_2_4_STORE_XTPM
129872. DPOT_AD5270_1_2_4_UNLOCK_CMD
129873. DPOT_AD5273_FUSE
129874. DPOT_AD5282_RDAC_AB
129875. DPOT_AD5291_CTRLREG
129876. DPOT_AD5291_RDAC
129877. DPOT_AD5291_READ_RDAC
129878. DPOT_AD5291_STORE_XTPM
129879. DPOT_AD5291_UNLOCK_CMD
129880. DPOT_ADDR_CMD
129881. DPOT_ADDR_EEPROM
129882. DPOT_ADDR_OTP
129883. DPOT_ADDR_OTP_EN
129884. DPOT_ADDR_RDAC
129885. DPOT_CONF
129886. DPOT_DEC_ALL
129887. DPOT_DEC_ALL_6DB
129888. DPOT_DEVICE_DO_CMD
129889. DPOT_DEVICE_SET
129890. DPOT_DEVICE_SHOW
129891. DPOT_DEVICE_SHOW_ONLY
129892. DPOT_DEVICE_SHOW_SET
129893. DPOT_FEAT
129894. DPOT_INC_ALL
129895. DPOT_INC_ALL_6DB
129896. DPOT_MAX_POS
129897. DPOT_RDAC0
129898. DPOT_RDAC1
129899. DPOT_RDAC2
129900. DPOT_RDAC3
129901. DPOT_RDAC4
129902. DPOT_RDAC5
129903. DPOT_RDAC_MASK
129904. DPOT_REG_TOL
129905. DPOT_SPI_DEC_ALL
129906. DPOT_SPI_DEC_ALL_6DB
129907. DPOT_SPI_EEPROM
129908. DPOT_SPI_INC_ALL
129909. DPOT_SPI_INC_ALL_6DB
129910. DPOT_SPI_RDAC
129911. DPOT_SPI_READ_EEPROM
129912. DPOT_SPI_READ_RDAC
129913. DPOT_TOL_RDAC0
129914. DPOT_TOL_RDAC1
129915. DPOT_TOL_RDAC2
129916. DPOT_TOL_RDAC3
129917. DPOT_TOL_RDAC4
129918. DPOT_TOL_RDAC5
129919. DPOT_UID
129920. DPOT_WIPERS
129921. DPOUNIT_CLOCK_GATE_DISABLE
129922. DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK
129923. DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT
129924. DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK
129925. DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT
129926. DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK
129927. DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT
129928. DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK
129929. DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT
129930. DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK
129931. DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT
129932. DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK
129933. DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT
129934. DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK
129935. DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT
129936. DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK
129937. DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT
129938. DPPCLK4_DTO_PARAM__DPPCLK4_DTO_MODULO_MASK
129939. DPPCLK4_DTO_PARAM__DPPCLK4_DTO_MODULO__SHIFT
129940. DPPCLK4_DTO_PARAM__DPPCLK4_DTO_PHASE_MASK
129941. DPPCLK4_DTO_PARAM__DPPCLK4_DTO_PHASE__SHIFT
129942. DPPCLK5_DTO_PARAM__DPPCLK5_DTO_MODULO_MASK
129943. DPPCLK5_DTO_PARAM__DPPCLK5_DTO_MODULO__SHIFT
129944. DPPCLK5_DTO_PARAM__DPPCLK5_DTO_PHASE_MASK
129945. DPPCLK5_DTO_PARAM__DPPCLK5_DTO_PHASE__SHIFT
129946. DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK
129947. DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT
129948. DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK
129949. DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT
129950. DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK
129951. DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT
129952. DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK
129953. DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT
129954. DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK
129955. DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT
129956. DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK
129957. DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT
129958. DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK
129959. DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT
129960. DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK
129961. DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT
129962. DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK
129963. DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT
129964. DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK
129965. DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT
129966. DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK
129967. DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT
129968. DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK
129969. DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT
129970. DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK
129971. DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT
129972. DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK
129973. DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT
129974. DPPD
129975. DPPD_MASK
129976. DPPD_SHIFT
129977. DPPLL_CLK_SRC_DSICLK
129978. DPPLL_SRC_DP_PLL_LOCK
129979. DPPR
129980. DPPR_BPP16
129981. DPPR_BPP32
129982. DPPR_BPP32_P1
129983. DPPR_BPP32_P2
129984. DPPR_DPE
129985. DPPR_DPS
129986. DPPR_DPS_SHIFT
129987. DPPU
129988. DPPU_MASK
129989. DPPU_SHIFT
129990. DPP_COMMON_REG_VARIABLE_LIST
129991. DPP_DCN2_REG_VARIABLE_LIST
129992. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
129993. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
129994. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
129995. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
129996. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
129997. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
129998. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
129999. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130000. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
130001. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
130002. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
130003. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130004. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
130005. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
130006. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
130007. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130008. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
130009. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
130010. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
130011. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130012. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
130013. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
130014. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
130015. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130016. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
130017. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
130018. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
130019. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130020. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
130021. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
130022. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
130023. DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
130024. DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK
130025. DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT
130026. DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK
130027. DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT
130028. DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK
130029. DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT
130030. DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK
130031. DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT
130032. DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK
130033. DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT
130034. DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK
130035. DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT
130036. DPP_TOP0_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK
130037. DPP_TOP0_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT
130038. DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK
130039. DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT
130040. DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK
130041. DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT
130042. DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK
130043. DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT
130044. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK
130045. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT
130046. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK
130047. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT
130048. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK
130049. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT
130050. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK
130051. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT
130052. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK
130053. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT
130054. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK
130055. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT
130056. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK
130057. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT
130058. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK
130059. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT
130060. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK
130061. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT
130062. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK
130063. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT
130064. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK
130065. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT
130066. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK
130067. DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT
130068. DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK
130069. DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT
130070. DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK
130071. DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT
130072. DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK
130073. DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT
130074. DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK
130075. DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT
130076. DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK
130077. DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT
130078. DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK
130079. DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT
130080. DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK
130081. DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT
130082. DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK
130083. DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT
130084. DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK
130085. DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT
130086. DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK
130087. DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT
130088. DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK
130089. DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT
130090. DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK
130091. DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT
130092. DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK
130093. DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT
130094. DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK
130095. DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT
130096. DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK
130097. DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT
130098. DPP_TOP1_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK
130099. DPP_TOP1_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT
130100. DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK
130101. DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT
130102. DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK
130103. DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT
130104. DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK
130105. DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT
130106. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK
130107. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT
130108. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK
130109. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT
130110. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK
130111. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT
130112. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK
130113. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT
130114. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK
130115. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT
130116. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK
130117. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT
130118. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK
130119. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT
130120. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK
130121. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT
130122. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK
130123. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT
130124. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK
130125. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT
130126. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK
130127. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT
130128. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK
130129. DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT
130130. DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK
130131. DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT
130132. DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK
130133. DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT
130134. DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK
130135. DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT
130136. DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK
130137. DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT
130138. DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK
130139. DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT
130140. DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK
130141. DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT
130142. DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK
130143. DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT
130144. DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK
130145. DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT
130146. DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK
130147. DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT
130148. DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK
130149. DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT
130150. DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK
130151. DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT
130152. DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK
130153. DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT
130154. DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK
130155. DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT
130156. DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK
130157. DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT
130158. DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK
130159. DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT
130160. DPP_TOP2_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK
130161. DPP_TOP2_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT
130162. DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK
130163. DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT
130164. DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK
130165. DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT
130166. DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK
130167. DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT
130168. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK
130169. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT
130170. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK
130171. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT
130172. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK
130173. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT
130174. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK
130175. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT
130176. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK
130177. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT
130178. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK
130179. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT
130180. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK
130181. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT
130182. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK
130183. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT
130184. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK
130185. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT
130186. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK
130187. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT
130188. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK
130189. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT
130190. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK
130191. DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT
130192. DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK
130193. DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT
130194. DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK
130195. DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT
130196. DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK
130197. DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT
130198. DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK
130199. DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT
130200. DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK
130201. DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT
130202. DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK
130203. DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT
130204. DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK
130205. DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT
130206. DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK
130207. DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT
130208. DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK
130209. DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT
130210. DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK
130211. DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT
130212. DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK
130213. DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT
130214. DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK
130215. DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT
130216. DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK
130217. DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT
130218. DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK
130219. DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT
130220. DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK
130221. DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT
130222. DPP_TOP3_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK
130223. DPP_TOP3_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT
130224. DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK
130225. DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT
130226. DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK
130227. DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT
130228. DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK
130229. DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT
130230. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK
130231. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT
130232. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK
130233. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT
130234. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK
130235. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT
130236. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK
130237. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT
130238. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK
130239. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT
130240. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK
130241. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT
130242. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK
130243. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT
130244. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK
130245. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT
130246. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK
130247. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT
130248. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK
130249. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT
130250. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK
130251. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT
130252. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK
130253. DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT
130254. DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK
130255. DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT
130256. DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK
130257. DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT
130258. DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK
130259. DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT
130260. DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK
130261. DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT
130262. DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK
130263. DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT
130264. DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK
130265. DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT
130266. DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK
130267. DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT
130268. DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK
130269. DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT
130270. DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK
130271. DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT
130272. DPP_TOP4_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK
130273. DPP_TOP4_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT
130274. DPP_TOP4_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK
130275. DPP_TOP4_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT
130276. DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK
130277. DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT
130278. DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK
130279. DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT
130280. DPP_TOP4_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK
130281. DPP_TOP4_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT
130282. DPP_TOP4_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK
130283. DPP_TOP4_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT
130284. DPP_TOP4_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK
130285. DPP_TOP4_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT
130286. DPP_TOP4_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK
130287. DPP_TOP4_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT
130288. DPP_TOP4_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK
130289. DPP_TOP4_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT
130290. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK
130291. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT
130292. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK
130293. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT
130294. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK
130295. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT
130296. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK
130297. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT
130298. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_EN_MASK
130299. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT
130300. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK
130301. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT
130302. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_MASK_MASK
130303. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT
130304. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK
130305. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT
130306. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK
130307. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT
130308. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK
130309. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT
130310. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK
130311. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT
130312. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK
130313. DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT
130314. DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK
130315. DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT
130316. DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK
130317. DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT
130318. DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK
130319. DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT
130320. DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK
130321. DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT
130322. DPP_TOP4_DPP_SOFT_RESET__CM_SOFT_RESET_MASK
130323. DPP_TOP4_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT
130324. DPP_TOP4_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK
130325. DPP_TOP4_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT
130326. DPP_TOP4_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK
130327. DPP_TOP4_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT
130328. DPP_TOP4_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK
130329. DPP_TOP4_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT
130330. DPP_TOP4_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK
130331. DPP_TOP4_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT
130332. DPP_TOP5_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK
130333. DPP_TOP5_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT
130334. DPP_TOP5_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK
130335. DPP_TOP5_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT
130336. DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK
130337. DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT
130338. DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK
130339. DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT
130340. DPP_TOP5_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK
130341. DPP_TOP5_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT
130342. DPP_TOP5_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK
130343. DPP_TOP5_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT
130344. DPP_TOP5_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK
130345. DPP_TOP5_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT
130346. DPP_TOP5_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK
130347. DPP_TOP5_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT
130348. DPP_TOP5_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK
130349. DPP_TOP5_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT
130350. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK
130351. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT
130352. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK
130353. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT
130354. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK
130355. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT
130356. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK
130357. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT
130358. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_EN_MASK
130359. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT
130360. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK
130361. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT
130362. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_MASK_MASK
130363. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT
130364. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK
130365. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT
130366. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK
130367. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT
130368. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK
130369. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT
130370. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK
130371. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT
130372. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK
130373. DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT
130374. DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK
130375. DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT
130376. DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK
130377. DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT
130378. DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK
130379. DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT
130380. DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK
130381. DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT
130382. DPP_TOP5_DPP_SOFT_RESET__CM_SOFT_RESET_MASK
130383. DPP_TOP5_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT
130384. DPP_TOP5_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK
130385. DPP_TOP5_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT
130386. DPP_TOP5_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK
130387. DPP_TOP5_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT
130388. DPP_TOP5_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK
130389. DPP_TOP5_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT
130390. DPP_TOP5_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK
130391. DPP_TOP5_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT
130392. DPR
130393. DPRAM_BASE
130394. DPRAM_CLR_RECV_FIFO
130395. DPRAM_COMMAND
130396. DPRAM_FCT_HOST
130397. DPRAM_FCT_PARAM
130398. DPRAM_FCT_RESULT
130399. DPRAM_INFO_BUSSTATE
130400. DPRAM_INFO_BUSSTATE2
130401. DPRAM_INFO_ERRSTATE
130402. DPRAM_INFO_ERRSTATE2
130403. DPRAM_IRQ_TOCARD
130404. DPRAM_IRQ_TOHOST
130405. DPRAM_READ_FIFO_LEVEL
130406. DPRAM_RECEIPT
130407. DPRAM_RESET
130408. DPRAM_RESET_RX_FIFO
130409. DPRAM_RESET_TIME
130410. DPRAM_RESET_TX_FIFO
130411. DPRAM_RX
130412. DPRAM_RX_CNT
130413. DPRAM_RX_FIFO_LEVEL
130414. DPRAM_RX_LOST
130415. DPRAM_RX_RD
130416. DPRAM_RX_SIZE
130417. DPRAM_RX_WR
130418. DPRAM_SIZE
130419. DPRAM_SPOOLER_DATA_SIZE
130420. DPRAM_SPOOLER_DEF_SIZE
130421. DPRAM_SPOOLER_MIN_SIZE
130422. DPRAM_TIME
130423. DPRAM_TX
130424. DPRAM_TX_CNT
130425. DPRAM_TX_FIFO_LEVEL
130426. DPRAM_TX_RD
130427. DPRAM_TX_SIZE
130428. DPRAM_TX_WR
130429. DPRAM_V2_IRQ_TOHOST
130430. DPRAM_V2_RESET
130431. DPRAM_WR_END
130432. DPRAM_WR_START
130433. DPRC_CMD
130434. DPRC_CMDID_CLEAR_IRQ_STATUS
130435. DPRC_CMDID_CLOSE
130436. DPRC_CMDID_GET_API_VERSION
130437. DPRC_CMDID_GET_ATTR
130438. DPRC_CMDID_GET_CONT_ID
130439. DPRC_CMDID_GET_IRQ_STATUS
130440. DPRC_CMDID_GET_OBJ
130441. DPRC_CMDID_GET_OBJ_COUNT
130442. DPRC_CMDID_GET_OBJ_REG
130443. DPRC_CMDID_GET_OBJ_REG_V2
130444. DPRC_CMDID_OPEN
130445. DPRC_CMDID_SET_IRQ
130446. DPRC_CMDID_SET_IRQ_ENABLE
130447. DPRC_CMDID_SET_IRQ_MASK
130448. DPRC_CMDID_SET_OBJ_IRQ
130449. DPRC_CMD_2ND_VERSION
130450. DPRC_CMD_BASE_VERSION
130451. DPRC_CMD_ID_OFFSET
130452. DPRC_CMD_V2
130453. DPRC_ENABLE
130454. DPRC_IRQ_EVENT_CONTAINER_DESTROYED
130455. DPRC_IRQ_EVENT_OBJ_ADDED
130456. DPRC_IRQ_EVENT_OBJ_CREATED
130457. DPRC_IRQ_EVENT_OBJ_DESTROYED
130458. DPRC_IRQ_EVENT_OBJ_REMOVED
130459. DPRC_MIN_VER_MAJOR
130460. DPRC_MIN_VER_MINOR
130461. DPRC_REGION_CACHEABLE
130462. DPRC_REGION_SHAREABLE
130463. DPRC_REGION_TYPE_MC_PORTAL
130464. DPRC_REGION_TYPE_QBMAN_MEM_BACKED_PORTAL
130465. DPRC_REGION_TYPE_QBMAN_PORTAL
130466. DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK
130467. DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT
130468. DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK
130469. DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT
130470. DPREFCLK_CNTL__DPREFCLK_CLOCK_EN_MASK
130471. DPREFCLK_CNTL__DPREFCLK_CLOCK_EN__SHIFT
130472. DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK
130473. DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT
130474. DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK
130475. DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT
130476. DPREFCLK_SRC_SEL
130477. DPREFCLK_SRC_SEL_CK
130478. DPREFCLK_SRC_SEL_P0PLL
130479. DPREFCLK_SRC_SEL_P1PLL
130480. DPREFCLK_SRC_SEL_P2PLL
130481. DPREFCLK_SRC_SEL_P3PLL
130482. DPRINT
130483. DPRINTF
130484. DPRINTK
130485. DPRINT_ARRAY
130486. DPRINT_FIELD
130487. DPRINT_IN_SIGNAL_BUF_SIZE
130488. DPRINT_TLA
130489. DPRINT_ovfl
130490. DPRP
130491. DPRPU
130492. DPRSLPVREN
130493. DPRTC_CMD
130494. DPRTC_CMDID_CLEAR_IRQ_STATUS
130495. DPRTC_CMDID_CLOSE
130496. DPRTC_CMDID_GET_IRQ_ENABLE
130497. DPRTC_CMDID_GET_IRQ_MASK
130498. DPRTC_CMDID_GET_IRQ_STATUS
130499. DPRTC_CMDID_OPEN
130500. DPRTC_CMDID_SET_IRQ_ENABLE
130501. DPRTC_CMDID_SET_IRQ_MASK
130502. DPRTC_CMD_BASE_VERSION
130503. DPRTC_CMD_ID_OFFSET
130504. DPRTC_EVENT_PPS
130505. DPRTC_IRQ_INDEX
130506. DPRTC_MAX_IRQ_NUM
130507. DPRT_CMD
130508. DPRUNIT_CLOCK_GATE_DISABLE
130509. DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA_MASK
130510. DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA__SHIFT
130511. DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX_MASK
130512. DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX__SHIFT
130513. DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN_MASK
130514. DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN__SHIFT
130515. DPRX_AUX_CONTROL__DPRX_AUX_EN_MASK
130516. DPRX_AUX_CONTROL__DPRX_AUX_EN__SHIFT
130517. DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN_MASK
130518. DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN__SHIFT
130519. DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN_MASK
130520. DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN__SHIFT
130521. DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0_MASK
130522. DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0__SHIFT
130523. DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1_MASK
130524. DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1__SHIFT
130525. DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE_MASK
130526. DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE__SHIFT
130527. DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER_MASK
130528. DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER__SHIFT
130529. DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK_MASK
130530. DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK__SHIFT
130531. DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK_MASK
130532. DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK__SHIFT
130533. DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS_MASK
130534. DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS__SHIFT
130535. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK_MASK
130536. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK__SHIFT
130537. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK_MASK
130538. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK__SHIFT
130539. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK_MASK
130540. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK__SHIFT
130541. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK_MASK
130542. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK__SHIFT
130543. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK_MASK
130544. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK__SHIFT
130545. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK_MASK
130546. DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK__SHIFT
130547. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED_MASK
130548. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED__SHIFT
130549. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK_MASK
130550. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK__SHIFT
130551. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS_MASK
130552. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS__SHIFT
130553. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED_MASK
130554. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED__SHIFT
130555. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK_MASK
130556. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK__SHIFT
130557. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS_MASK
130558. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS__SHIFT
130559. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED_MASK
130560. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED__SHIFT
130561. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK_MASK
130562. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK__SHIFT
130563. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS_MASK
130564. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS__SHIFT
130565. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED_MASK
130566. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED__SHIFT
130567. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK_MASK
130568. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK__SHIFT
130569. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS_MASK
130570. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS__SHIFT
130571. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED_MASK
130572. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED__SHIFT
130573. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK_MASK
130574. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK__SHIFT
130575. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS_MASK
130576. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS__SHIFT
130577. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED_MASK
130578. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED__SHIFT
130579. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK_MASK
130580. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK__SHIFT
130581. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS_MASK
130582. DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS__SHIFT
130583. DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER_MASK
130584. DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER__SHIFT
130585. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK_MASK
130586. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK__SHIFT
130587. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK_MASK
130588. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK__SHIFT
130589. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED_MASK
130590. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED__SHIFT
130591. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE_MASK
130592. DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE__SHIFT
130593. DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1_MASK
130594. DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1__SHIFT
130595. DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2_MASK
130596. DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2__SHIFT
130597. DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1_MASK
130598. DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1__SHIFT
130599. DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1_MASK
130600. DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1__SHIFT
130601. DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2_MASK
130602. DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2__SHIFT
130603. DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2_MASK
130604. DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2__SHIFT
130605. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
130606. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
130607. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
130608. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
130609. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
130610. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
130611. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD_MASK
130612. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD__SHIFT
130613. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN_MASK
130614. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
130615. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN_MASK
130616. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN__SHIFT
130617. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW_MASK
130618. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW__SHIFT
130619. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW_MASK
130620. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW__SHIFT
130621. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN_MASK
130622. DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN__SHIFT
130623. DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP_MASK
130624. DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP__SHIFT
130625. DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START_MASK
130626. DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START__SHIFT
130627. DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN_MASK
130628. DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN__SHIFT
130629. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
130630. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
130631. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_MASK
130632. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD__SHIFT
130633. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE_MASK
130634. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE__SHIFT
130635. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT_MASK
130636. DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT__SHIFT
130637. DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN_MASK
130638. DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN__SHIFT
130639. DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS_MASK
130640. DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS__SHIFT
130641. DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE_MASK
130642. DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE__SHIFT
130643. DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV_MASK
130644. DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV__SHIFT
130645. DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL_MASK
130646. DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL__SHIFT
130647. DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE_MASK
130648. DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE__SHIFT
130649. DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD_MASK
130650. DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD__SHIFT
130651. DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE_MASK
130652. DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE__SHIFT
130653. DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA_MASK
130654. DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA__SHIFT
130655. DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX_MASK
130656. DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX__SHIFT
130657. DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE_MASK
130658. DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE__SHIFT
130659. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A_MASK
130660. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A__SHIFT
130661. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN_MASK
130662. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN__SHIFT
130663. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP_MASK
130664. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP__SHIFT
130665. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH_MASK
130666. DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH__SHIFT
130667. DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER_MASK
130668. DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER__SHIFT
130669. DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY_MASK
130670. DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY__SHIFT
130671. DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1_MASK
130672. DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1__SHIFT
130673. DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2_MASK
130674. DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2__SHIFT
130675. DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1_MASK
130676. DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1__SHIFT
130677. DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1_MASK
130678. DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1__SHIFT
130679. DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2_MASK
130680. DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2__SHIFT
130681. DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2_MASK
130682. DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2__SHIFT
130683. DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING_MASK
130684. DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING__SHIFT
130685. DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING_MASK
130686. DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING__SHIFT
130687. DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING_MASK
130688. DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING__SHIFT
130689. DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING_MASK
130690. DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING__SHIFT
130691. DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1_MASK
130692. DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1__SHIFT
130693. DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1_MASK
130694. DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1__SHIFT
130695. DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2_MASK
130696. DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2__SHIFT
130697. DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2_MASK
130698. DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2__SHIFT
130699. DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1_MASK
130700. DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1__SHIFT
130701. DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2_MASK
130702. DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2__SHIFT
130703. DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1_MASK
130704. DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1__SHIFT
130705. DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1_MASK
130706. DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1__SHIFT
130707. DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2_MASK
130708. DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2__SHIFT
130709. DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2_MASK
130710. DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2__SHIFT
130711. DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN_MASK
130712. DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN__SHIFT
130713. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV_MASK
130714. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV__SHIFT
130715. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV_MASK
130716. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV__SHIFT
130717. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL_MASK
130718. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL__SHIFT
130719. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV_MASK
130720. DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV__SHIFT
130721. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK_MASK
130722. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK__SHIFT
130723. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK_MASK
130724. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK__SHIFT
130725. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK_MASK
130726. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK__SHIFT
130727. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK_MASK
130728. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK__SHIFT
130729. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK_MASK
130730. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK__SHIFT
130731. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK_MASK
130732. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK__SHIFT
130733. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK_MASK
130734. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK__SHIFT
130735. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK_MASK
130736. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK__SHIFT
130737. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK_MASK
130738. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK__SHIFT
130739. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK_MASK
130740. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK__SHIFT
130741. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK_MASK
130742. DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK__SHIFT
130743. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT_MASK
130744. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT__SHIFT
130745. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE_MASK
130746. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE__SHIFT
130747. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START_MASK
130748. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START__SHIFT
130749. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP_MASK
130750. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP__SHIFT
130751. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK
130752. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL__SHIFT
130753. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW_MASK
130754. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW__SHIFT
130755. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE_MASK
130756. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE__SHIFT
130757. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H_MASK
130758. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H__SHIFT
130759. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L_MASK
130760. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L__SHIFT
130761. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET_MASK
130762. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET__SHIFT
130763. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR_MASK
130764. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR__SHIFT
130765. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H_MASK
130766. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H__SHIFT
130767. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L_MASK
130768. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L__SHIFT
130769. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT_MASK
130770. DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT__SHIFT
130771. DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1_MASK
130772. DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1__SHIFT
130773. DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2_MASK
130774. DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2__SHIFT
130775. DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR_MASK
130776. DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR__SHIFT
130777. DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_MASK
130778. DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT__SHIFT
130779. DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT_MASK
130780. DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT__SHIFT
130781. DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR_MASK
130782. DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR__SHIFT
130783. DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_MASK
130784. DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT__SHIFT
130785. DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT_MASK
130786. DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT__SHIFT
130787. DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR_MASK
130788. DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR__SHIFT
130789. DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_MASK
130790. DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR__SHIFT
130791. DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR_MASK
130792. DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR__SHIFT
130793. DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_MASK
130794. DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR__SHIFT
130795. DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR_MASK
130796. DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR__SHIFT
130797. DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_MASK
130798. DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR__SHIFT
130799. DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR_MASK
130800. DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR__SHIFT
130801. DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_MASK
130802. DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR__SHIFT
130803. DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH_MASK
130804. DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH__SHIFT
130805. DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH_MASK
130806. DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH__SHIFT
130807. DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK_MASK
130808. DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK__SHIFT
130809. DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG_MASK
130810. DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT
130811. DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK_MASK
130812. DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK__SHIFT
130813. DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS_MASK
130814. DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS__SHIFT
130815. DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS_MASK
130816. DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS__SHIFT
130817. DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS_MASK
130818. DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS__SHIFT
130819. DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS_MASK
130820. DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS__SHIFT
130821. DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED_MASK
130822. DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED__SHIFT
130823. DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED_MASK
130824. DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED__SHIFT
130825. DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED_MASK
130826. DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED__SHIFT
130827. DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED_MASK
130828. DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED__SHIFT
130829. DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED_MASK
130830. DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED__SHIFT
130831. DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED_MASK
130832. DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED__SHIFT
130833. DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED_MASK
130834. DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED__SHIFT
130835. DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED_MASK
130836. DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED__SHIFT
130837. DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK_MASK
130838. DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK__SHIFT
130839. DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG_MASK
130840. DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG__SHIFT
130841. DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK_MASK
130842. DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK__SHIFT
130843. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK_MASK
130844. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK__SHIFT
130845. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG_MASK
130846. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG__SHIFT
130847. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK_MASK
130848. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK__SHIFT
130849. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE_MASK
130850. DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE__SHIFT
130851. DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK_MASK
130852. DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK__SHIFT
130853. DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG_MASK
130854. DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG__SHIFT
130855. DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK_MASK
130856. DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK__SHIFT
130857. DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET_MASK
130858. DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET__SHIFT
130859. DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET_MASK
130860. DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET__SHIFT
130861. DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT_MASK
130862. DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT
130863. DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT_MASK
130864. DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT__SHIFT
130865. DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET_MASK
130866. DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET__SHIFT
130867. DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT_MASK
130868. DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT
130869. DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT_MASK
130870. DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT__SHIFT
130871. DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET_MASK
130872. DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET__SHIFT
130873. DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT_MASK
130874. DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT
130875. DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT_MASK
130876. DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT__SHIFT
130877. DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET_MASK
130878. DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET__SHIFT
130879. DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT_MASK
130880. DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT
130881. DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT_MASK
130882. DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT__SHIFT
130883. DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN_MASK
130884. DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN__SHIFT
130885. DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET_MASK
130886. DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET__SHIFT
130887. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT_MASK
130888. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT__SHIFT
130889. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST_MASK
130890. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST__SHIFT
130891. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT_MASK
130892. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT__SHIFT
130893. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE_MASK
130894. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE__SHIFT
130895. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE_MASK
130896. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE__SHIFT
130897. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_MASK
130898. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE__SHIFT
130899. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE_MASK
130900. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE__SHIFT
130901. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE_MASK
130902. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE__SHIFT
130903. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_MASK
130904. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE__SHIFT
130905. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE_MASK
130906. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE__SHIFT
130907. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE_MASK
130908. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE__SHIFT
130909. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_MASK
130910. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE__SHIFT
130911. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE_MASK
130912. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE__SHIFT
130913. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE_MASK
130914. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE__SHIFT
130915. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_MASK
130916. DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE__SHIFT
130917. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA_MASK
130918. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA__SHIFT
130919. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA_MASK
130920. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA__SHIFT
130921. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA_MASK
130922. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA__SHIFT
130923. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA_MASK
130924. DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA__SHIFT
130925. DPRX_DPHY_ECF_LSB__ECF_LSB_MASK
130926. DPRX_DPHY_ECF_LSB__ECF_LSB__SHIFT
130927. DPRX_DPHY_ECF_MSB__ECF_MSB_MASK
130928. DPRX_DPHY_ECF_MSB__ECF_MSB__SHIFT
130929. DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN_MASK
130930. DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN__SHIFT
130931. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_MASK
130932. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID_MASK
130933. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID__SHIFT
130934. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT__SHIFT
130935. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_MASK
130936. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID_MASK
130937. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID__SHIFT
130938. DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT__SHIFT
130939. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_MASK
130940. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID_MASK
130941. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID__SHIFT
130942. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT__SHIFT
130943. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_MASK
130944. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID_MASK
130945. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID__SHIFT
130946. DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT__SHIFT
130947. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_MASK
130948. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID_MASK
130949. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID__SHIFT
130950. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT__SHIFT
130951. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_MASK
130952. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID_MASK
130953. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID__SHIFT
130954. DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT__SHIFT
130955. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_MASK
130956. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID_MASK
130957. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID__SHIFT
130958. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT__SHIFT
130959. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_MASK
130960. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID_MASK
130961. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID__SHIFT
130962. DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT__SHIFT
130963. DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_MASK
130964. DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID_MASK
130965. DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT
130966. DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT__SHIFT
130967. DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_MASK
130968. DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID_MASK
130969. DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT
130970. DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT__SHIFT
130971. DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_MASK
130972. DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID_MASK
130973. DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT
130974. DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT__SHIFT
130975. DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_MASK
130976. DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID_MASK
130977. DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT
130978. DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT__SHIFT
130979. DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR_MASK
130980. DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR__SHIFT
130981. DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR_MASK
130982. DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR__SHIFT
130983. DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR_MASK
130984. DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT
130985. DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR_MASK
130986. DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR__SHIFT
130987. DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR_MASK
130988. DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR__SHIFT
130989. DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR_MASK
130990. DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT
130991. DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR_MASK
130992. DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR__SHIFT
130993. DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR_MASK
130994. DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR__SHIFT
130995. DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR_MASK
130996. DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT
130997. DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR_MASK
130998. DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR__SHIFT
130999. DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR_MASK
131000. DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR__SHIFT
131001. DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR_MASK
131002. DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT
131003. DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH_MASK
131004. DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH__SHIFT
131005. DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH_MASK
131006. DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH__SHIFT
131007. DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH_MASK
131008. DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH__SHIFT
131009. DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH_MASK
131010. DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH__SHIFT
131011. DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH_MASK
131012. DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH__SHIFT
131013. DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH_MASK
131014. DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH__SHIFT
131015. DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH_MASK
131016. DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH__SHIFT
131017. DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH_MASK
131018. DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH__SHIFT
131019. DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH_MASK
131020. DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH__SHIFT
131021. DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH_MASK
131022. DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH__SHIFT
131023. DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH_MASK
131024. DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH__SHIFT
131025. DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH_MASK
131026. DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH__SHIFT
131027. DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK_MASK
131028. DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK__SHIFT
131029. DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG_MASK
131030. DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG__SHIFT
131031. DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK_MASK
131032. DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK__SHIFT
131033. DPRX_DPHY_INT_RESET__CTL_DS_RESET_MASK
131034. DPRX_DPHY_INT_RESET__CTL_DS_RESET__SHIFT
131035. DPRX_DPHY_INT_RESET__CTL_RESET_MASK
131036. DPRX_DPHY_INT_RESET__CTL_RESET__SHIFT
131037. DPRX_DPHY_INT_RESET__CTL_TRN_RESET_MASK
131038. DPRX_DPHY_INT_RESET__CTL_TRN_RESET__SHIFT
131039. DPRX_DPHY_INT_RESET__ENABLE_RESET_MASK
131040. DPRX_DPHY_INT_RESET__ENABLE_RESET__SHIFT
131041. DPRX_DPHY_INT_RESET__HEADERPARSE_RESET_MASK
131042. DPRX_DPHY_INT_RESET__HEADERPARSE_RESET__SHIFT
131043. DPRX_DPHY_INT_RESET__INV_RESET_MASK
131044. DPRX_DPHY_INT_RESET__INV_RESET__SHIFT
131045. DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET_MASK
131046. DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET__SHIFT
131047. DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET_MASK
131048. DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET__SHIFT
131049. DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET_MASK
131050. DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET__SHIFT
131051. DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET_MASK
131052. DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET__SHIFT
131053. DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET_MASK
131054. DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET__SHIFT
131055. DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET_MASK
131056. DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET__SHIFT
131057. DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET_MASK
131058. DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET__SHIFT
131059. DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET_MASK
131060. DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET__SHIFT
131061. DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET_MASK
131062. DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET__SHIFT
131063. DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET_MASK
131064. DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET__SHIFT
131065. DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET_MASK
131066. DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET__SHIFT
131067. DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET_MASK
131068. DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET__SHIFT
131069. DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET_MASK
131070. DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET__SHIFT
131071. DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET_MASK
131072. DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET__SHIFT
131073. DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET_MASK
131074. DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET__SHIFT
131075. DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET_MASK
131076. DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET__SHIFT
131077. DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET_MASK
131078. DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET__SHIFT
131079. DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET_MASK
131080. DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET__SHIFT
131081. DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET_MASK
131082. DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET__SHIFT
131083. DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET_MASK
131084. DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET__SHIFT
131085. DPRX_DPHY_INT_RESET__LANEREV_RESET_MASK
131086. DPRX_DPHY_INT_RESET__LANEREV_RESET__SHIFT
131087. DPRX_DPHY_INT_RESET__SDOUT_RESET_MASK
131088. DPRX_DPHY_INT_RESET__SDOUT_RESET__SHIFT
131089. DPRX_DPHY_LANESETUP0__LANE_MAP_MASK
131090. DPRX_DPHY_LANESETUP0__LANE_MAP__SHIFT
131091. DPRX_DPHY_LANESETUP1__LANEINV_MASK
131092. DPRX_DPHY_LANESETUP1__LANEINV__SHIFT
131093. DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT_MASK
131094. DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT__SHIFT
131095. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE_MASK
131096. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE__SHIFT
131097. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE_MASK
131098. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE__SHIFT
131099. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL_MASK
131100. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL__SHIFT
131101. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE_MASK
131102. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE__SHIFT
131103. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT_MASK
131104. DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT__SHIFT
131105. DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL_MASK
131106. DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL__SHIFT
131107. DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE_MASK
131108. DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE__SHIFT
131109. DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN_MASK
131110. DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN__SHIFT
131111. DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE_MASK
131112. DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE__SHIFT
131113. DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE_MASK
131114. DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE__SHIFT
131115. DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK_MASK
131116. DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK__SHIFT
131117. DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG_MASK
131118. DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG__SHIFT
131119. DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK_MASK
131120. DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK__SHIFT
131121. DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK_MASK
131122. DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK__SHIFT
131123. DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG_MASK
131124. DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG__SHIFT
131125. DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK_MASK
131126. DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK__SHIFT
131127. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE_MASK
131128. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE__SHIFT
131129. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE_MASK
131130. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE__SHIFT
131131. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE_MASK
131132. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE__SHIFT
131133. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF_MASK
131134. DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF__SHIFT
131135. DPRX_DPHY_READY__ACT_READY_CLR_MASK
131136. DPRX_DPHY_READY__ACT_READY_CLR__SHIFT
131137. DPRX_DPHY_READY__ACT_READY_MASK
131138. DPRX_DPHY_READY__ACT_READY__SHIFT
131139. DPRX_DPHY_READY__CP_READY_MASK
131140. DPRX_DPHY_READY__CP_READY__SHIFT
131141. DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR_MASK
131142. DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR__SHIFT
131143. DPRX_DPHY_READY__MVOTE_DATA_ERROR_MASK
131144. DPRX_DPHY_READY__MVOTE_DATA_ERROR__SHIFT
131145. DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR_MASK
131146. DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR__SHIFT
131147. DPRX_DPHY_READY__MVOTE_KCODE_ERROR_MASK
131148. DPRX_DPHY_READY__MVOTE_KCODE_ERROR__SHIFT
131149. DPRX_DPHY_READY__SDOUT_READY_MASK
131150. DPRX_DPHY_READY__SDOUT_READY__SHIFT
131151. DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE_MASK
131152. DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE__SHIFT
131153. DPRX_DPHY_SET_ENABLE__CLOCK_ON_MASK
131154. DPRX_DPHY_SET_ENABLE__CLOCK_ON__SHIFT
131155. DPRX_DPHY_SET_ENABLE__SET_ENABLE_MASK
131156. DPRX_DPHY_SET_ENABLE__SET_ENABLE__SHIFT
131157. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR_MASK
131158. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR__SHIFT
131159. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0_MASK
131160. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0__SHIFT
131161. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1_MASK
131162. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1__SHIFT
131163. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2_MASK
131164. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2__SHIFT
131165. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3_MASK
131166. DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3__SHIFT
131167. DPRX_DPHY_SPARE__DPHY_SPARE_MASK
131168. DPRX_DPHY_SPARE__DPHY_SPARE__SHIFT
131169. DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR_MASK
131170. DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR__SHIFT
131171. DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_MASK
131172. DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT__SHIFT
131173. DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT_MASK
131174. DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT__SHIFT
131175. DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK_MASK
131176. DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK__SHIFT
131177. DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG_MASK
131178. DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT
131179. DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK_MASK
131180. DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK__SHIFT
131181. DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK_MASK
131182. DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK__SHIFT
131183. DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG_MASK
131184. DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG__SHIFT
131185. DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK_MASK
131186. DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK__SHIFT
131187. DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK
131188. DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT
131189. DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK
131190. DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT
131191. DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK
131192. DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT
131193. DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK
131194. DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT
131195. DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK
131196. DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT
131197. DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE_MASK
131198. DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE__SHIFT
131199. DPRX_SD0_DPRX_SD_CONTROL__SD_RESET_MASK
131200. DPRX_SD0_DPRX_SD_CONTROL__SD_RESET__SHIFT
131201. DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK
131202. DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT
131203. DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK
131204. DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT
131205. DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK
131206. DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT
131207. DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK
131208. DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT
131209. DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK
131210. DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT
131211. DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK
131212. DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT
131213. DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK
131214. DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT
131215. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK
131216. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT
131217. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK
131218. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT
131219. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK
131220. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT
131221. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK
131222. DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT
131223. DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK
131224. DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT
131225. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK
131226. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT
131227. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK
131228. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT
131229. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK
131230. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT
131231. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK
131232. DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT
131233. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK
131234. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT
131235. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK
131236. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT
131237. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK
131238. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT
131239. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK
131240. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT
131241. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK
131242. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT
131243. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK
131244. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT
131245. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK
131246. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT
131247. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK
131248. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT
131249. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK
131250. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT
131251. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK
131252. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT
131253. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK
131254. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT
131255. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK
131256. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT
131257. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK
131258. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT
131259. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK
131260. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT
131261. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK
131262. DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT
131263. DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK
131264. DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT
131265. DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK
131266. DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT
131267. DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK
131268. DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT
131269. DPRX_SD0_DPRX_SD_MSA0__MSA0_MASK
131270. DPRX_SD0_DPRX_SD_MSA0__MSA0__SHIFT
131271. DPRX_SD0_DPRX_SD_MSA1__MSA1_MASK
131272. DPRX_SD0_DPRX_SD_MSA1__MSA1__SHIFT
131273. DPRX_SD0_DPRX_SD_MSA2__MSA2_MASK
131274. DPRX_SD0_DPRX_SD_MSA2__MSA2__SHIFT
131275. DPRX_SD0_DPRX_SD_MSA3__MSA3_MASK
131276. DPRX_SD0_DPRX_SD_MSA3__MSA3__SHIFT
131277. DPRX_SD0_DPRX_SD_MSA4__MSA4_MASK
131278. DPRX_SD0_DPRX_SD_MSA4__MSA4__SHIFT
131279. DPRX_SD0_DPRX_SD_MSA5__MSA5_MASK
131280. DPRX_SD0_DPRX_SD_MSA5__MSA5__SHIFT
131281. DPRX_SD0_DPRX_SD_MSA6__MSA6_MASK
131282. DPRX_SD0_DPRX_SD_MSA6__MSA6__SHIFT
131283. DPRX_SD0_DPRX_SD_MSA7__MSA7_MASK
131284. DPRX_SD0_DPRX_SD_MSA7__MSA7__SHIFT
131285. DPRX_SD0_DPRX_SD_MSA8__MSA8_MASK
131286. DPRX_SD0_DPRX_SD_MSA8__MSA8__SHIFT
131287. DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK
131288. DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT
131289. DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK
131290. DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT
131291. DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK
131292. DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT
131293. DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK
131294. DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT
131295. DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK
131296. DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT
131297. DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK
131298. DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT
131299. DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK
131300. DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT
131301. DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK
131302. DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT
131303. DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK
131304. DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT
131305. DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK
131306. DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT
131307. DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK
131308. DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT
131309. DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK
131310. DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT
131311. DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK
131312. DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT
131313. DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK
131314. DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT
131315. DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA_MASK
131316. DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT
131317. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK
131318. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT
131319. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK
131320. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT
131321. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK
131322. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT
131323. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK
131324. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT
131325. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK
131326. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT
131327. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK
131328. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT
131329. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK
131330. DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT
131331. DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK
131332. DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT
131333. DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK
131334. DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT
131335. DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK
131336. DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT
131337. DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK
131338. DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT
131339. DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK
131340. DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT
131341. DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK
131342. DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT
131343. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK
131344. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT
131345. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK
131346. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT
131347. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK
131348. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT
131349. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK
131350. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT
131351. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK
131352. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT
131353. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK
131354. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT
131355. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK
131356. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT
131357. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK
131358. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT
131359. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK
131360. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT
131361. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK
131362. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT
131363. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK
131364. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT
131365. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK
131366. DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT
131367. DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK
131368. DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT
131369. DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK
131370. DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT
131371. DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK
131372. DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT
131373. DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK
131374. DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT
131375. DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK
131376. DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT
131377. DPRX_SD0_DPRX_SD_VBID__VBID_MASK
131378. DPRX_SD0_DPRX_SD_VBID__VBID__SHIFT
131379. DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK
131380. DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT
131381. DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK
131382. DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT
131383. DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK
131384. DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT
131385. DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK
131386. DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT
131387. DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK
131388. DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT
131389. DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK
131390. DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT
131391. DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK
131392. DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT
131393. DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK
131394. DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT
131395. DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK
131396. DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT
131397. DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK
131398. DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT
131399. DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK
131400. DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT
131401. DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK
131402. DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT
131403. DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK
131404. DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT
131405. DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK
131406. DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT
131407. DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK
131408. DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT
131409. DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE_MASK
131410. DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE__SHIFT
131411. DPRX_SD1_DPRX_SD_CONTROL__SD_RESET_MASK
131412. DPRX_SD1_DPRX_SD_CONTROL__SD_RESET__SHIFT
131413. DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK
131414. DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT
131415. DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK
131416. DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT
131417. DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK
131418. DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT
131419. DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK
131420. DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT
131421. DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK
131422. DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT
131423. DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK
131424. DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT
131425. DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK
131426. DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT
131427. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK
131428. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT
131429. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK
131430. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT
131431. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK
131432. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT
131433. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK
131434. DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT
131435. DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK
131436. DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT
131437. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK
131438. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT
131439. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK
131440. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT
131441. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK
131442. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT
131443. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK
131444. DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT
131445. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK
131446. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT
131447. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK
131448. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT
131449. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK
131450. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT
131451. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK
131452. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT
131453. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK
131454. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT
131455. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK
131456. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT
131457. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK
131458. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT
131459. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK
131460. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT
131461. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK
131462. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT
131463. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK
131464. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT
131465. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK
131466. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT
131467. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK
131468. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT
131469. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK
131470. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT
131471. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK
131472. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT
131473. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK
131474. DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT
131475. DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK
131476. DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT
131477. DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK
131478. DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT
131479. DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK
131480. DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT
131481. DPRX_SD1_DPRX_SD_MSA0__MSA0_MASK
131482. DPRX_SD1_DPRX_SD_MSA0__MSA0__SHIFT
131483. DPRX_SD1_DPRX_SD_MSA1__MSA1_MASK
131484. DPRX_SD1_DPRX_SD_MSA1__MSA1__SHIFT
131485. DPRX_SD1_DPRX_SD_MSA2__MSA2_MASK
131486. DPRX_SD1_DPRX_SD_MSA2__MSA2__SHIFT
131487. DPRX_SD1_DPRX_SD_MSA3__MSA3_MASK
131488. DPRX_SD1_DPRX_SD_MSA3__MSA3__SHIFT
131489. DPRX_SD1_DPRX_SD_MSA4__MSA4_MASK
131490. DPRX_SD1_DPRX_SD_MSA4__MSA4__SHIFT
131491. DPRX_SD1_DPRX_SD_MSA5__MSA5_MASK
131492. DPRX_SD1_DPRX_SD_MSA5__MSA5__SHIFT
131493. DPRX_SD1_DPRX_SD_MSA6__MSA6_MASK
131494. DPRX_SD1_DPRX_SD_MSA6__MSA6__SHIFT
131495. DPRX_SD1_DPRX_SD_MSA7__MSA7_MASK
131496. DPRX_SD1_DPRX_SD_MSA7__MSA7__SHIFT
131497. DPRX_SD1_DPRX_SD_MSA8__MSA8_MASK
131498. DPRX_SD1_DPRX_SD_MSA8__MSA8__SHIFT
131499. DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK
131500. DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT
131501. DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK
131502. DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT
131503. DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK
131504. DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT
131505. DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK
131506. DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT
131507. DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK
131508. DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT
131509. DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK
131510. DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT
131511. DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK
131512. DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT
131513. DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK
131514. DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT
131515. DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK
131516. DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT
131517. DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK
131518. DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT
131519. DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK
131520. DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT
131521. DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK
131522. DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT
131523. DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK
131524. DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT
131525. DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK
131526. DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT
131527. DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA_MASK
131528. DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT
131529. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK
131530. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT
131531. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK
131532. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT
131533. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK
131534. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT
131535. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK
131536. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT
131537. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK
131538. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT
131539. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK
131540. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT
131541. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK
131542. DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT
131543. DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK
131544. DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT
131545. DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK
131546. DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT
131547. DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK
131548. DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT
131549. DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK
131550. DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT
131551. DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK
131552. DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT
131553. DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK
131554. DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT
131555. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK
131556. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT
131557. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK
131558. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT
131559. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK
131560. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT
131561. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK
131562. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT
131563. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK
131564. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT
131565. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK
131566. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT
131567. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK
131568. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT
131569. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK
131570. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT
131571. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK
131572. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT
131573. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK
131574. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT
131575. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK
131576. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT
131577. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK
131578. DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT
131579. DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK
131580. DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT
131581. DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK
131582. DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT
131583. DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK
131584. DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT
131585. DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK
131586. DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT
131587. DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK
131588. DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT
131589. DPRX_SD1_DPRX_SD_VBID__VBID_MASK
131590. DPRX_SD1_DPRX_SD_VBID__VBID__SHIFT
131591. DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK
131592. DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT
131593. DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK
131594. DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT
131595. DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK
131596. DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT
131597. DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK
131598. DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT
131599. DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK
131600. DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT
131601. DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK
131602. DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT
131603. DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK
131604. DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT
131605. DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK
131606. DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT
131607. DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK
131608. DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT
131609. DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK
131610. DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT
131611. DPRX_SD_COMPONENT_DEPTH
131612. DPRX_SD_PIXEL_ENCODING
131613. DPR_ADC_BUFFER
131614. DPR_AD_BUF_FRONT
131615. DPR_AD_BUF_REAR
131616. DPR_AI_FIFO_DEPTH
131617. DPR_AO_FIFO_DEPTH
131618. DPR_CMD
131619. DPR_CMD_CALCCLOCK
131620. DPR_CMD_COMPLETION
131621. DPR_CMD_COMPLETION_MASK
131622. DPR_CMD_CONFIG
131623. DPR_CMD_ERROR
131624. DPR_CMD_EXECUTE
131625. DPR_CMD_GETBRDINFO
131626. DPR_CMD_GETCONFIG
131627. DPR_CMD_HALT
131628. DPR_CMD_MASK
131629. DPR_CMD_MBX
131630. DPR_CMD_NOERROR
131631. DPR_CMD_NOTPROCESSED
131632. DPR_CMD_NOTSUPPORTED
131633. DPR_CMD_READCODE
131634. DPR_CMD_READCT
131635. DPR_CMD_READCTCTRL
131636. DPR_CMD_READDATA
131637. DPR_CMD_READEVENTS
131638. DPR_CMD_READIO
131639. DPR_CMD_READSINGLE
131640. DPR_CMD_START
131641. DPR_CMD_STOP
131642. DPR_CMD_TIMEOUT
131643. DPR_CMD_WRITECODE
131644. DPR_CMD_WRITECT
131645. DPR_CMD_WRITECTCTRL
131646. DPR_CMD_WRITEDATA
131647. DPR_CMD_WRITEIO
131648. DPR_CMD_WRITESINGLE
131649. DPR_COMMAND
131650. DPR_DAC_BUFFER
131651. DPR_DA_BUF_FRONT
131652. DPR_DA_BUF_REAR
131653. DPR_ENCODE
131654. DPR_EXTERNAL_CLOCK
131655. DPR_INTR_ADFULL
131656. DPR_INTR_ADHWERR
131657. DPR_INTR_ADSWERR
131658. DPR_INTR_CMDONE
131659. DPR_INTR_CTDONE
131660. DPR_INTR_DAEMPTY
131661. DPR_INTR_DAHWERR
131662. DPR_INTR_DASWERR
131663. DPR_INTR_FLAG
131664. DPR_INT_MASK
131665. DPR_PARAM5_AD_TRIG
131666. DPR_PARAM5_AD_TRIG_EXT
131667. DPR_PARAM5_AD_TRIG_EXT_RETRIG
131668. DPR_PARAM5_AD_TRIG_INT
131669. DPR_PARAM5_AD_TRIG_INT_RETRIG
131670. DPR_PARAM5_AD_TRIG_INT_RETRIG2
131671. DPR_PARAM6_AD_DIFF
131672. DPR_PARAMS
131673. DPR_RESPONSE_MBX
131674. DPR_RISING_EDGE
131675. DPR_SUBSYS
131676. DPR_SUBSYS_AI
131677. DPR_SUBSYS_AO
131678. DPR_SUBSYS_CT
131679. DPR_SUBSYS_DIN
131680. DPR_SUBSYS_DOUT
131681. DPR_SUBSYS_MEM
131682. DPR_TICK_REG_HI
131683. DPR_TICK_REG_LO
131684. DPR_TMODE_MASK
131685. DPS
131686. DPS1
131687. DPS310_BACKGROUND
131688. DPS310_CFG_REG
131689. DPS310_COEF_BASE
131690. DPS310_COEF_RDY
131691. DPS310_DEV_NAME
131692. DPS310_FIFO_EN
131693. DPS310_INT_HL
131694. DPS310_MEAS_CFG
131695. DPS310_MEAS_CTRL_BITS
131696. DPS310_POLL_SLEEP_US
131697. DPS310_POLL_TIMEOUT_US
131698. DPS310_PRS_B0
131699. DPS310_PRS_B1
131700. DPS310_PRS_B2
131701. DPS310_PRS_BASE
131702. DPS310_PRS_CFG
131703. DPS310_PRS_EN
131704. DPS310_PRS_PRC_BITS
131705. DPS310_PRS_RATE_BITS
131706. DPS310_PRS_RDY
131707. DPS310_PRS_SHIFT_EN
131708. DPS310_RESET
131709. DPS310_RESET_MAGIC
131710. DPS310_SENSOR_RDY
131711. DPS310_SPI_EN
131712. DPS310_TEMP_EN
131713. DPS310_TMP_B0
131714. DPS310_TMP_B1
131715. DPS310_TMP_B2
131716. DPS310_TMP_BASE
131717. DPS310_TMP_CFG
131718. DPS310_TMP_EXT
131719. DPS310_TMP_PRC_BITS
131720. DPS310_TMP_RATE_BITS
131721. DPS310_TMP_RDY
131722. DPS310_TMP_SHIFT_EN
131723. DPSECI_ALL_QUEUES
131724. DPSECI_CGN_DEST_TYPE_SHIFT
131725. DPSECI_CGN_DEST_TYPE_SIZE
131726. DPSECI_CGN_MODE_COHERENT_WRITE
131727. DPSECI_CGN_MODE_INTR_COALESCING_DISABLED
131728. DPSECI_CGN_MODE_NOTIFY_DEST_ON_ENTER
131729. DPSECI_CGN_MODE_NOTIFY_DEST_ON_EXIT
131730. DPSECI_CGN_MODE_WRITE_MEM_ON_ENTER
131731. DPSECI_CGN_MODE_WRITE_MEM_ON_EXIT
131732. DPSECI_CGN_UNITS_SHIFT
131733. DPSECI_CGN_UNITS_SIZE
131734. DPSECI_CMDID_CLOSE
131735. DPSECI_CMDID_DISABLE
131736. DPSECI_CMDID_ENABLE
131737. DPSECI_CMDID_GET_API_VERSION
131738. DPSECI_CMDID_GET_ATTR
131739. DPSECI_CMDID_GET_CONGESTION_NOTIFICATION
131740. DPSECI_CMDID_GET_RX_QUEUE
131741. DPSECI_CMDID_GET_SEC_ATTR
131742. DPSECI_CMDID_GET_TX_QUEUE
131743. DPSECI_CMDID_IS_ENABLED
131744. DPSECI_CMDID_OPEN
131745. DPSECI_CMDID_SET_CONGESTION_NOTIFICATION
131746. DPSECI_CMDID_SET_RX_QUEUE
131747. DPSECI_CMD_BASE_VERSION
131748. DPSECI_CMD_BASE_VERSION_V2
131749. DPSECI_CMD_ID_OFFSET
131750. DPSECI_CMD_V1
131751. DPSECI_CMD_V2
131752. DPSECI_CONGESTION_UNIT_BYTES
131753. DPSECI_CONGESTION_UNIT_FRAMES
131754. DPSECI_DEBUGFS_H
131755. DPSECI_DEST_DPCON
131756. DPSECI_DEST_DPIO
131757. DPSECI_DEST_NONE
131758. DPSECI_DEST_TYPE_SHIFT
131759. DPSECI_DEST_TYPE_SIZE
131760. DPSECI_ENABLE_SHIFT
131761. DPSECI_ENABLE_SIZE
131762. DPSECI_MASK
131763. DPSECI_MAX_QUEUE_NUM
131764. DPSECI_OPT_HAS_CG
131765. DPSECI_ORDER_PRESERVATION_SHIFT
131766. DPSECI_ORDER_PRESERVATION_SIZE
131767. DPSECI_QUEUE_OPT_DEST
131768. DPSECI_QUEUE_OPT_ORDER_PRESERVATION
131769. DPSECI_QUEUE_OPT_USER_CTX
131770. DPSECI_VER
131771. DPSECI_VERSION
131772. DPSECI_VER_MAJOR
131773. DPSECI_VER_MINOR
131774. DPSE_INTR_EN
131775. DPSE_INTR_HIGH_SEL
131776. DPSIGN
131777. DPSIZC
131778. DPSIZC_MASK
131779. DPSIZC_SHIFT
131780. DPSIZR
131781. DPSIZR_MASK
131782. DPSIZR_SHIFT
131783. DPST_HISTOGRAM
131784. DPST_PHASE_IN
131785. DPST_YUV_LUMA_MODE
131786. DPSW_ACTION_DROP
131787. DPSW_ACTION_REDIRECT
131788. DPSW_ADMIT_ALL
131789. DPSW_ADMIT_ONLY_VLAN_TAGGED
131790. DPSW_CMDID_CLEAR_IRQ_STATUS
131791. DPSW_CMDID_CLOSE
131792. DPSW_CMDID_DISABLE
131793. DPSW_CMDID_ENABLE
131794. DPSW_CMDID_FDB_ADD_MULTICAST
131795. DPSW_CMDID_FDB_ADD_UNICAST
131796. DPSW_CMDID_FDB_DUMP
131797. DPSW_CMDID_FDB_REMOVE_MULTICAST
131798. DPSW_CMDID_FDB_REMOVE_UNICAST
131799. DPSW_CMDID_FDB_SET_LEARNING_MODE
131800. DPSW_CMDID_GET_API_VERSION
131801. DPSW_CMDID_GET_ATTR
131802. DPSW_CMDID_GET_IRQ_STATUS
131803. DPSW_CMDID_IF_DISABLE
131804. DPSW_CMDID_IF_ENABLE
131805. DPSW_CMDID_IF_GET_COUNTER
131806. DPSW_CMDID_IF_GET_LINK_STATE
131807. DPSW_CMDID_IF_GET_TCI
131808. DPSW_CMDID_IF_SET_BROADCAST
131809. DPSW_CMDID_IF_SET_FLOODING
131810. DPSW_CMDID_IF_SET_LINK_CFG
131811. DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH
131812. DPSW_CMDID_IF_SET_STP
131813. DPSW_CMDID_IF_SET_TCI
131814. DPSW_CMDID_OPEN
131815. DPSW_CMDID_RESET
131816. DPSW_CMDID_SET_IRQ_ENABLE
131817. DPSW_CMDID_SET_IRQ_MASK
131818. DPSW_CMDID_VLAN_ADD
131819. DPSW_CMDID_VLAN_ADD_IF
131820. DPSW_CMDID_VLAN_ADD_IF_UNTAGGED
131821. DPSW_CMDID_VLAN_REMOVE
131822. DPSW_CMDID_VLAN_REMOVE_IF
131823. DPSW_CMDID_VLAN_REMOVE_IF_FLOODING
131824. DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED
131825. DPSW_CMD_BASE_VERSION
131826. DPSW_CMD_ID
131827. DPSW_CMD_ID_OFFSET
131828. DPSW_CNT_EGR_BYTE
131829. DPSW_CNT_EGR_FRAME
131830. DPSW_CNT_EGR_FRAME_DISCARD
131831. DPSW_CNT_EGR_STP_FRAME_DISCARD
131832. DPSW_CNT_ING_BCAST_BYTES
131833. DPSW_CNT_ING_BCAST_FRAME
131834. DPSW_CNT_ING_BYTE
131835. DPSW_CNT_ING_FLTR_FRAME
131836. DPSW_CNT_ING_FRAME
131837. DPSW_CNT_ING_FRAME_DISCARD
131838. DPSW_CNT_ING_MCAST_BYTE
131839. DPSW_CNT_ING_MCAST_FRAME
131840. DPSW_COMPONENT_TYPE_C_VLAN
131841. DPSW_COMPONENT_TYPE_SHIFT
131842. DPSW_COMPONENT_TYPE_SIZE
131843. DPSW_COMPONENT_TYPE_S_VLAN
131844. DPSW_COUNTER_TYPE_SHIFT
131845. DPSW_COUNTER_TYPE_SIZE
131846. DPSW_DEI_SHIFT
131847. DPSW_DEI_SIZE
131848. DPSW_ENABLE_SHIFT
131849. DPSW_ENABLE_SIZE
131850. DPSW_ENTRY_TYPE_SHIFT
131851. DPSW_ENTRY_TYPE_SIZE
131852. DPSW_FDB_ENTRY_DINAMIC
131853. DPSW_FDB_ENTRY_STATIC
131854. DPSW_FDB_ENTRY_TYPE_DYNAMIC
131855. DPSW_FDB_ENTRY_TYPE_UNICAST
131856. DPSW_FDB_LEARNING_MODE_DIS
131857. DPSW_FDB_LEARNING_MODE_HW
131858. DPSW_FDB_LEARNING_MODE_NON_SECURE
131859. DPSW_FDB_LEARNING_MODE_SECURE
131860. DPSW_IRQ_EVENT_LINK_CHANGED
131861. DPSW_IRQ_INDEX_IF
131862. DPSW_IRQ_INDEX_L2SW
131863. DPSW_IRQ_NUM
131864. DPSW_LEARNING_MODE_SHIFT
131865. DPSW_LEARNING_MODE_SIZE
131866. DPSW_LINK_OPT_ASYM_PAUSE
131867. DPSW_LINK_OPT_AUTONEG
131868. DPSW_LINK_OPT_HALF_DUPLEX
131869. DPSW_LINK_OPT_PAUSE
131870. DPSW_MASK
131871. DPSW_MAX_IF
131872. DPSW_MAX_PRIORITIES
131873. DPSW_MIN_VER_MAJOR
131874. DPSW_MIN_VER_MINOR
131875. DPSW_OPT_CTRL_IF_DIS
131876. DPSW_OPT_FLOODING_DIS
131877. DPSW_OPT_FLOODING_METERING_DIS
131878. DPSW_OPT_METERING_EN
131879. DPSW_OPT_MULTICAST_DIS
131880. DPSW_PCP_SHIFT
131881. DPSW_PCP_SIZE
131882. DPSW_STATE_SHIFT
131883. DPSW_STATE_SIZE
131884. DPSW_STP_STATE_BLOCKING
131885. DPSW_STP_STATE_DISABLED
131886. DPSW_STP_STATE_FORWARDING
131887. DPSW_STP_STATE_LEARNING
131888. DPSW_STP_STATE_LISTENING
131889. DPSW_UP_SHIFT
131890. DPSW_UP_SIZE
131891. DPSW_VER_MAJOR
131892. DPSW_VER_MINOR
131893. DPSW_VLAN_ID_SHIFT
131894. DPSW_VLAN_ID_SIZE
131895. DPS_RSTCT2_PER_EN
131896. DPS_TIMER
131897. DPTE_GROUP_SIZE
131898. DPTE_GROUP_SIZE_1024B
131899. DPTE_GROUP_SIZE_128B
131900. DPTE_GROUP_SIZE_2048B
131901. DPTE_GROUP_SIZE_256B
131902. DPTE_GROUP_SIZE_4096B
131903. DPTE_GROUP_SIZE_512B
131904. DPTE_GROUP_SIZE_64B
131905. DPTE_GROUP_SIZE_8192B
131906. DPTF_POWER_SHOW
131907. DPTI_DEV_OFFLINE
131908. DPTI_DEV_ONLINE
131909. DPTI_DEV_RESET
131910. DPTI_DEV_UNSCANNED
131911. DPTI_I2O_MAJOR
131912. DPTI_MAX_HBA
131913. DPTI_STATE_RESET
131914. DPTOREG
131915. DPTR_ALIGN
131916. DPTSQC
131917. DPTSQO
131918. DPTSR
131919. DPTSR_PnDK
131920. DPTSR_PnTS
131921. DPTXFSIZN
131922. DPTX_ENABLE_EVENT
131923. DPTX_ENHNCD
131924. DPTX_EVENT_ENABLE_HPD
131925. DPTX_EVENT_ENABLE_TRAINING
131926. DPTX_FORCE_LANES
131927. DPTX_FRMR_DATA_CLK_EN
131928. DPTX_FRMR_DATA_CLK_RSTN_EN
131929. DPTX_GET_EDID
131930. DPTX_GET_LAST_AUX_STAUS
131931. DPTX_HPD_DEL
131932. DPTX_HPD_EVENT
131933. DPTX_HPD_SEL
131934. DPTX_HPD_SEL_MASK
131935. DPTX_HPD_STATE
131936. DPTX_INT_MASK
131937. DPTX_INT_STATUS
131938. DPTX_LANE_EN
131939. DPTX_PHY_CHAR_CLK_EN
131940. DPTX_PHY_CHAR_RSTN_EN
131941. DPTX_PHY_DATA_CLK_EN
131942. DPTX_PHY_DATA_RSTN_EN
131943. DPTX_READ_DPCD
131944. DPTX_READ_EVENT
131945. DPTX_READ_LINK_STAT
131946. DPTX_READ_REGISTER
131947. DPTX_SET_AUDIO
131948. DPTX_SET_HOST_CAPABILITIES
131949. DPTX_SET_LINK_BREAK_POINT
131950. DPTX_SET_POWER_MNG
131951. DPTX_SET_VIDEO
131952. DPTX_SYS_CLK_EN
131953. DPTX_SYS_CLK_RSTN_EN
131954. DPTX_TRAINING_CONTROL
131955. DPTX_TRAINING_EVENT
131956. DPTX_WRITE_DPCD
131957. DPTX_WRITE_FIELD
131958. DPTX_WRITE_REGISTER
131959. DPT_BETA
131960. DPT_BLINKLED
131961. DPT_CLRSTAT
131962. DPT_CONFIG
131963. DPT_CTRLINFO
131964. DPT_DAY
131965. DPT_DEBUG
131966. DPT_DRIVER
131967. DPT_DRIVER_NAME
131968. DPT_EXPORT
131969. DPT_I2O_VERSION
131970. DPT_IMPORT
131971. DPT_MONTH
131972. DPT_NUMCTRLS
131973. DPT_ORGANIZATION_ID
131974. DPT_PERF_INFO
131975. DPT_REVISION
131976. DPT_RUNTIME_IMPORT
131977. DPT_SIGNATURE
131978. DPT_SIGNATURE_PACKED
131979. DPT_START
131980. DPT_STATINFO
131981. DPT_STATS_CLEAR
131982. DPT_STATS_INFO
131983. DPT_STOP
131984. DPT_SUBREVISION
131985. DPT_SYSINFO
131986. DPT_TARGET_BUSY
131987. DPT_THREAD_PRIORITY_HIGHEST
131988. DPT_THREAD_PRIORITY_LOWEST
131989. DPT_THREAD_PRIORITY_NORMAL
131990. DPT_TIMEOUT
131991. DPT_UNALIGNED
131992. DPT_VERSION
131993. DPT_YEAR
131994. DPTranslatorControl
131995. DPUNIT_A_CLOCK_GATE_DISABLE
131996. DPUNIT_B_CLOCK_GATE_DISABLE
131997. DPUNIT_CLOCK_GATE_DISABLE
131998. DPUNIT_PIPEA_GATE_DISABLE
131999. DPUNIT_PIPEB_GATE_DISABLE
132000. DPU_ATRACE_BEGIN
132001. DPU_ATRACE_END
132002. DPU_ATRACE_FUNC
132003. DPU_ATRACE_INT
132004. DPU_BLEND_BG_ALPHA_BG_CONST
132005. DPU_BLEND_BG_ALPHA_BG_PIXEL
132006. DPU_BLEND_BG_ALPHA_FG_CONST
132007. DPU_BLEND_BG_ALPHA_FG_PIXEL
132008. DPU_BLEND_BG_INV_ALPHA
132009. DPU_BLEND_BG_INV_MOD_ALPHA
132010. DPU_BLEND_BG_MOD_ALPHA
132011. DPU_BLEND_BG_TRANSP_EN
132012. DPU_BLEND_FG_ALPHA_BG_CONST
132013. DPU_BLEND_FG_ALPHA_BG_PIXEL
132014. DPU_BLEND_FG_ALPHA_FG_CONST
132015. DPU_BLEND_FG_ALPHA_FG_PIXEL
132016. DPU_BLEND_FG_INV_ALPHA
132017. DPU_BLEND_FG_INV_MOD_ALPHA
132018. DPU_BLEND_FG_MOD_ALPHA
132019. DPU_BLEND_FG_TRANSP_EN
132020. DPU_CHROMA_420
132021. DPU_CHROMA_H1V2
132022. DPU_CHROMA_H2V1
132023. DPU_CHROMA_RGB
132024. DPU_CLK_CTRL_CURSOR0
132025. DPU_CLK_CTRL_CURSOR1
132026. DPU_CLK_CTRL_DMA0
132027. DPU_CLK_CTRL_DMA1
132028. DPU_CLK_CTRL_INLINE_ROT0_SSPP
132029. DPU_CLK_CTRL_MAX
132030. DPU_CLK_CTRL_NONE
132031. DPU_CLK_CTRL_RGB0
132032. DPU_CLK_CTRL_RGB1
132033. DPU_CLK_CTRL_RGB2
132034. DPU_CLK_CTRL_RGB3
132035. DPU_CLK_CTRL_VIG0
132036. DPU_CLK_CTRL_VIG1
132037. DPU_CLK_CTRL_VIG2
132038. DPU_CLK_CTRL_VIG3
132039. DPU_CLK_CTRL_VIG4
132040. DPU_CORE_PERF_DATA_BUS_ID_EBI
132041. DPU_CORE_PERF_DATA_BUS_ID_LLCC
132042. DPU_CORE_PERF_DATA_BUS_ID_MAX
132043. DPU_CORE_PERF_DATA_BUS_ID_MNOC
132044. DPU_CRTC_FRAME_DONE_TIMEOUT_MS
132045. DPU_CRTC_FRAME_EVENT_SIZE
132046. DPU_CRTC_MAX_EVENT_COUNT
132047. DPU_CRTC_NAME_SIZE
132048. DPU_CSC_BIAS_SIZE
132049. DPU_CSC_CLAMP_SIZE
132050. DPU_CSC_MATRIX_COEFF_SIZE
132051. DPU_CTL_MAX
132052. DPU_CTL_MODE_SEL_CMD
132053. DPU_CTL_MODE_SEL_VID
132054. DPU_CTL_SPLIT_DISPLAY
132055. DPU_DBG_MASK_CTL
132056. DPU_DBG_MASK_INTF
132057. DPU_DBG_MASK_LM
132058. DPU_DBG_MASK_NONE
132059. DPU_DBG_MASK_PINGPONG
132060. DPU_DBG_MASK_ROT
132061. DPU_DBG_MASK_SSPP
132062. DPU_DBG_MASK_TOP
132063. DPU_DBG_MASK_VBIF
132064. DPU_DBG_MASK_WB
132065. DPU_DBG_NAME
132066. DPU_DEBUG
132067. DPU_DEBUGFS_DIR
132068. DPU_DEBUGFS_HWMASKNAME
132069. DPU_DEBUG_CMDENC
132070. DPU_DEBUG_DRIVER
132071. DPU_DEBUG_ENC
132072. DPU_DEBUG_PHYS
132073. DPU_DEBUG_PLANE
132074. DPU_DEBUG_VIDENC
132075. DPU_DIM_LAYER
132076. DPU_DRM_BLEND_OP_COVERAGE
132077. DPU_DRM_BLEND_OP_MAX
132078. DPU_DRM_BLEND_OP_NOT_DEFINED
132079. DPU_DRM_BLEND_OP_OPAQUE
132080. DPU_DRM_BLEND_OP_PREMULTIPLIED
132081. DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES
132082. DPU_ENCODER_FRAME_EVENT_DONE
132083. DPU_ENCODER_FRAME_EVENT_ERROR
132084. DPU_ENCODER_FRAME_EVENT_IDLE
132085. DPU_ENCODER_FRAME_EVENT_PANEL_DEAD
132086. DPU_ENCODER_NAME_MAX
132087. DPU_ENC_DISABLED
132088. DPU_ENC_DISABLING
132089. DPU_ENC_ENABLED
132090. DPU_ENC_ENABLING
132091. DPU_ENC_ERR_NEEDS_HW_RESET
132092. DPU_ENC_RC_EVENT_ENTER_IDLE
132093. DPU_ENC_RC_EVENT_FRAME_DONE
132094. DPU_ENC_RC_EVENT_KICKOFF
132095. DPU_ENC_RC_EVENT_PRE_STOP
132096. DPU_ENC_RC_EVENT_STOP
132097. DPU_ENC_RC_STATE_IDLE
132098. DPU_ENC_RC_STATE_OFF
132099. DPU_ENC_RC_STATE_ON
132100. DPU_ENC_RC_STATE_PRE_OFF
132101. DPU_ENC_WR_PTR_START_TIMEOUT_US
132102. DPU_ERROR
132103. DPU_ERROR_CMDENC
132104. DPU_ERROR_ENC
132105. DPU_ERROR_PHYS
132106. DPU_ERROR_PLANE
132107. DPU_ERROR_VIDENC
132108. DPU_FETCH_CONFIG_RESET_VALUE
132109. DPU_FETCH_LINEAR
132110. DPU_FETCH_TILE
132111. DPU_FETCH_UBWC
132112. DPU_FORMAT_FLAG_BIT_MAX
132113. DPU_FORMAT_FLAG_COMPRESSED
132114. DPU_FORMAT_FLAG_COMPRESSED_BIT
132115. DPU_FORMAT_FLAG_DX
132116. DPU_FORMAT_FLAG_DX_BIT
132117. DPU_FORMAT_FLAG_YUV
132118. DPU_FORMAT_FLAG_YUV_BIT
132119. DPU_FORMAT_IS_DX
132120. DPU_FORMAT_IS_LINEAR
132121. DPU_FORMAT_IS_TILE
132122. DPU_FORMAT_IS_UBWC
132123. DPU_FORMAT_IS_YUV
132124. DPU_FRAME_LINEAR
132125. DPU_FRAME_TILE_A4X
132126. DPU_FRAME_TILE_A5X
132127. DPU_HW_BLK_CTL
132128. DPU_HW_BLK_INFO
132129. DPU_HW_BLK_INTF
132130. DPU_HW_BLK_LM
132131. DPU_HW_BLK_MAX
132132. DPU_HW_BLK_NAME_LEN
132133. DPU_HW_BLK_PINGPONG
132134. DPU_HW_BLK_SSPP
132135. DPU_HW_BLK_TOP
132136. DPU_HW_BLK_WB
132137. DPU_HW_MAJOR
132138. DPU_HW_MAJOR_MINOR
132139. DPU_HW_MINOR
132140. DPU_HW_STEP
132141. DPU_HW_SUBBLK_INFO
132142. DPU_HW_UBWC_VER_10
132143. DPU_HW_UBWC_VER_20
132144. DPU_HW_UBWC_VER_30
132145. DPU_HW_VER
132146. DPU_HW_VER_170
132147. DPU_HW_VER_171
132148. DPU_HW_VER_172
132149. DPU_HW_VER_300
132150. DPU_HW_VER_301
132151. DPU_HW_VER_400
132152. DPU_HW_VER_401
132153. DPU_HW_VER_410
132154. DPU_HW_VER_500
132155. DPU_INTR_BACKLIGHT_UPDATED
132156. DPU_INTR_CTL_0_START
132157. DPU_INTR_CTL_1_START
132158. DPU_INTR_CTL_2_START
132159. DPU_INTR_CTL_3_START
132160. DPU_INTR_CTL_4_START
132161. DPU_INTR_CWB_2_OVERFLOW
132162. DPU_INTR_CWB_3_OVERFLOW
132163. DPU_INTR_DSICMD_0_INTO_STATIC
132164. DPU_INTR_DSICMD_0_OUTOF_STATIC
132165. DPU_INTR_DSICMD_1_INTO_STATIC
132166. DPU_INTR_DSICMD_1_OUTOF_STATIC
132167. DPU_INTR_DSICMD_2_INTO_STATIC
132168. DPU_INTR_DSICMD_2_OUTOF_STATIC
132169. DPU_INTR_HIST_DSPP_0_DONE
132170. DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE
132171. DPU_INTR_HIST_DSPP_1_DONE
132172. DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE
132173. DPU_INTR_HIST_DSPP_2_DONE
132174. DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE
132175. DPU_INTR_HIST_DSPP_3_DONE
132176. DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE
132177. DPU_INTR_HIST_VIG_0_DONE
132178. DPU_INTR_HIST_VIG_0_RSTSEQ_DONE
132179. DPU_INTR_HIST_VIG_1_DONE
132180. DPU_INTR_HIST_VIG_1_RSTSEQ_DONE
132181. DPU_INTR_HIST_VIG_2_DONE
132182. DPU_INTR_HIST_VIG_2_RSTSEQ_DONE
132183. DPU_INTR_HIST_VIG_3_DONE
132184. DPU_INTR_HIST_VIG_3_RSTSEQ_DONE
132185. DPU_INTR_INTF_0_UNDERRUN
132186. DPU_INTR_INTF_0_VSYNC
132187. DPU_INTR_INTF_1_UNDERRUN
132188. DPU_INTR_INTF_1_VSYNC
132189. DPU_INTR_INTF_2_UNDERRUN
132190. DPU_INTR_INTF_2_VSYNC
132191. DPU_INTR_INTF_3_UNDERRUN
132192. DPU_INTR_INTF_3_VSYNC
132193. DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE
132194. DPU_INTR_PING_PONG_0_DONE
132195. DPU_INTR_PING_PONG_0_RD_PTR
132196. DPU_INTR_PING_PONG_0_TEAR_DETECTED
132197. DPU_INTR_PING_PONG_0_TE_DETECTED
132198. DPU_INTR_PING_PONG_0_WR_PTR
132199. DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE
132200. DPU_INTR_PING_PONG_1_DONE
132201. DPU_INTR_PING_PONG_1_RD_PTR
132202. DPU_INTR_PING_PONG_1_TEAR_DETECTED
132203. DPU_INTR_PING_PONG_1_TE_DETECTED
132204. DPU_INTR_PING_PONG_1_WR_PTR
132205. DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE
132206. DPU_INTR_PING_PONG_2_DONE
132207. DPU_INTR_PING_PONG_2_RD_PTR
132208. DPU_INTR_PING_PONG_2_TEAR_DETECTED
132209. DPU_INTR_PING_PONG_2_TE_DETECTED
132210. DPU_INTR_PING_PONG_2_WR_PTR
132211. DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE
132212. DPU_INTR_PING_PONG_3_DONE
132213. DPU_INTR_PING_PONG_3_RD_PTR
132214. DPU_INTR_PING_PONG_3_TEAR_DETECTED
132215. DPU_INTR_PING_PONG_3_TE_DETECTED
132216. DPU_INTR_PING_PONG_3_WR_PTR
132217. DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE
132218. DPU_INTR_PING_PONG_S0_RD_PTR
132219. DPU_INTR_PING_PONG_S0_TEAR_DETECTED
132220. DPU_INTR_PING_PONG_S0_TE_DETECTED
132221. DPU_INTR_PING_PONG_S0_WR_PTR
132222. DPU_INTR_PROG_LINE
132223. DPU_INTR_VIDEO_INTO_STATIC
132224. DPU_INTR_VIDEO_OUTOF_STATIC
132225. DPU_INTR_WB_0_DONE
132226. DPU_INTR_WB_1_DONE
132227. DPU_INTR_WB_2_DONE
132228. DPU_INTR_WD_TIMER_0_DONE
132229. DPU_INTR_WD_TIMER_1_DONE
132230. DPU_INTR_WD_TIMER_2_DONE
132231. DPU_INTR_WD_TIMER_3_DONE
132232. DPU_INTR_WD_TIMER_4_DONE
132233. DPU_IRQ_TYPE_AD4_BL_DONE
132234. DPU_IRQ_TYPE_CTL_START
132235. DPU_IRQ_TYPE_CWB_OVERFLOW
132236. DPU_IRQ_TYPE_HIST_DSPP_DONE
132237. DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ
132238. DPU_IRQ_TYPE_HIST_VIG_DONE
132239. DPU_IRQ_TYPE_HIST_VIG_RSTSEQ
132240. DPU_IRQ_TYPE_INTF_UNDER_RUN
132241. DPU_IRQ_TYPE_INTF_VSYNC
132242. DPU_IRQ_TYPE_PING_PONG_AUTO_REF
132243. DPU_IRQ_TYPE_PING_PONG_COMP
132244. DPU_IRQ_TYPE_PING_PONG_RD_PTR
132245. DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK
132246. DPU_IRQ_TYPE_PING_PONG_TE_CHECK
132247. DPU_IRQ_TYPE_PING_PONG_WR_PTR
132248. DPU_IRQ_TYPE_PROG_LINE
132249. DPU_IRQ_TYPE_RESERVED
132250. DPU_IRQ_TYPE_SFI_CMD_0_IN
132251. DPU_IRQ_TYPE_SFI_CMD_0_OUT
132252. DPU_IRQ_TYPE_SFI_CMD_1_IN
132253. DPU_IRQ_TYPE_SFI_CMD_1_OUT
132254. DPU_IRQ_TYPE_SFI_CMD_2_IN
132255. DPU_IRQ_TYPE_SFI_CMD_2_OUT
132256. DPU_IRQ_TYPE_SFI_VIDEO_IN
132257. DPU_IRQ_TYPE_SFI_VIDEO_OUT
132258. DPU_IRQ_TYPE_WB_ROT_COMP
132259. DPU_IRQ_TYPE_WB_WFD_COMP
132260. DPU_IRQ_TYPE_WD_TIMER
132261. DPU_KMS_INFO_MAX_SIZE
132262. DPU_MAX_DE_CURVES
132263. DPU_MAX_IMG_HEIGHT
132264. DPU_MAX_IMG_WIDTH
132265. DPU_MAX_PLANES
132266. DPU_MDP_10BIT_SUPPORT
132267. DPU_MDP_BWC
132268. DPU_MDP_MAX
132269. DPU_MDP_PANIC_PER_PIPE
132270. DPU_MDP_UBWC_1_0
132271. DPU_MDP_UBWC_1_5
132272. DPU_MIXER_GC
132273. DPU_MIXER_LAYER
132274. DPU_MIXER_MAX
132275. DPU_MIXER_SOURCESPLIT
132276. DPU_NAME_SIZE
132277. DPU_NONE
132278. DPU_PERF_CDP_USAGE_MAX
132279. DPU_PERF_CDP_USAGE_NRT
132280. DPU_PERF_CDP_USAGE_RT
132281. DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE
132282. DPU_PERF_MODE_FIXED
132283. DPU_PERF_MODE_MAX
132284. DPU_PERF_MODE_MINIMUM
132285. DPU_PERF_MODE_NORMAL
132286. DPU_PINGPONG_DITHER
132287. DPU_PINGPONG_MAX
132288. DPU_PINGPONG_SLAVE
132289. DPU_PINGPONG_SPLIT
132290. DPU_PINGPONG_TE
132291. DPU_PINGPONG_TE2
132292. DPU_PLANE_COLOR_FILL_FLAG
132293. DPU_PLANE_INTERLEAVED
132294. DPU_PLANE_PLANAR
132295. DPU_PLANE_PSEUDO_PLANAR
132296. DPU_PLANE_QOS_PANIC_CTRL
132297. DPU_PLANE_QOS_VBLANK_AMORTIZE
132298. DPU_PLANE_QOS_VBLANK_CTRL
132299. DPU_QOS_LUT_USAGE_LINEAR
132300. DPU_QOS_LUT_USAGE_MACROTILE
132301. DPU_QOS_LUT_USAGE_MAX
132302. DPU_QOS_LUT_USAGE_NRT
132303. DPU_QSEED3_DEFAULT_PRELOAD_H
132304. DPU_QSEED3_DEFAULT_PRELOAD_V
132305. DPU_REG_READ
132306. DPU_REG_RESET_TIMEOUT_US
132307. DPU_REG_WRITE
132308. DPU_SCALE_1D_SEP
132309. DPU_SCALE_2D_4X4
132310. DPU_SCALE_2D_CIR
132311. DPU_SCALE_ALPHA_BIL
132312. DPU_SCALE_ALPHA_PIXEL_REP
132313. DPU_SCALE_BIL
132314. DPU_SCALE_FILTER_BIL
132315. DPU_SCALE_FILTER_CA
132316. DPU_SCALE_FILTER_MAX
132317. DPU_SCALE_FILTER_NEAREST
132318. DPU_SCALE_FILTER_PCMN
132319. DPU_SSPP_CDP
132320. DPU_SSPP_CDP_PRELOAD_AHEAD_32
132321. DPU_SSPP_CDP_PRELOAD_AHEAD_64
132322. DPU_SSPP_COMP_0
132323. DPU_SSPP_COMP_1_2
132324. DPU_SSPP_COMP_2
132325. DPU_SSPP_COMP_3
132326. DPU_SSPP_COMP_MAX
132327. DPU_SSPP_CSC
132328. DPU_SSPP_CSC_10BIT
132329. DPU_SSPP_CURSOR
132330. DPU_SSPP_EXCL_RECT
132331. DPU_SSPP_FLIP_LR
132332. DPU_SSPP_FLIP_UD
132333. DPU_SSPP_MAX
132334. DPU_SSPP_MULTIRECT_NONE
132335. DPU_SSPP_MULTIRECT_PARALLEL
132336. DPU_SSPP_MULTIRECT_TIME_MX
132337. DPU_SSPP_QOS
132338. DPU_SSPP_QOS_8LVL
132339. DPU_SSPP_RECT_0
132340. DPU_SSPP_RECT_1
132341. DPU_SSPP_RECT_SOLO
132342. DPU_SSPP_ROT_90
132343. DPU_SSPP_SCALER
132344. DPU_SSPP_SCALER_QSEED2
132345. DPU_SSPP_SCALER_QSEED3
132346. DPU_SSPP_SCALER_RGB
132347. DPU_SSPP_SMART_DMA_V1
132348. DPU_SSPP_SMART_DMA_V2
132349. DPU_SSPP_SOLID_FILL
132350. DPU_SSPP_SOURCE_ROTATED_90
132351. DPU_SSPP_SRC
132352. DPU_SSPP_TS_PREFILL
132353. DPU_SSPP_TS_PREFILL_REC1
132354. DPU_STAGE_0
132355. DPU_STAGE_1
132356. DPU_STAGE_10
132357. DPU_STAGE_2
132358. DPU_STAGE_3
132359. DPU_STAGE_4
132360. DPU_STAGE_5
132361. DPU_STAGE_6
132362. DPU_STAGE_7
132363. DPU_STAGE_8
132364. DPU_STAGE_9
132365. DPU_STAGE_BASE
132366. DPU_STAGE_MAX
132367. DPU_TILE_HEIGHT_DEFAULT
132368. DPU_TILE_HEIGHT_NV12
132369. DPU_TILE_HEIGHT_TILED
132370. DPU_TILE_HEIGHT_UBWC
132371. DPU_UBWC_META_BLOCK_SIZE
132372. DPU_UBWC_META_MACRO_W_H
132373. DPU_UBWC_PLANE_SIZE_ALIGNMENT
132374. DPU_VBIF_MAX
132375. DPU_VBIF_QOS_OTLIM
132376. DPU_VBIF_QOS_REMAP
132377. DPU_VSYNC0_SOURCE_GPIO
132378. DPU_VSYNC1_SOURCE_GPIO
132379. DPU_VSYNC2_SOURCE_GPIO
132380. DPU_VSYNC_SOURCE_INTF_0
132381. DPU_VSYNC_SOURCE_INTF_1
132382. DPU_VSYNC_SOURCE_INTF_2
132383. DPU_VSYNC_SOURCE_INTF_3
132384. DPU_VSYNC_SOURCE_WD_TIMER_0
132385. DPU_VSYNC_SOURCE_WD_TIMER_1
132386. DPU_VSYNC_SOURCE_WD_TIMER_2
132387. DPU_VSYNC_SOURCE_WD_TIMER_3
132388. DPU_VSYNC_SOURCE_WD_TIMER_4
132389. DPU_ZPOS_MAX
132390. DPX
132391. DPX1
132392. DPXMULT
132393. DPY_H
132394. DPY_W
132395. DP_1_62_GHZ
132396. DP_2_7_GHZ
132397. DP_A
132398. DP_ADAPTER_CAP
132399. DP_ADAPTER_CTRL
132400. DP_ADAPTER_CTRL_FORCE_LOAD_SENSE
132401. DP_ADAPTOR_DVI_MAX_TMDS_CLK
132402. DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK
132403. DP_ADAPTOR_TYPE2_ID
132404. DP_ADAPTOR_TYPE2_MAX_TMDS_CLK
132405. DP_ADAPTOR_TYPE2_MIN_TMDS_CLK
132406. DP_ADAPTOR_TYPE2_REG_ID
132407. DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK
132408. DP_ADAPTOR_TYPE2_SIZE
132409. DP_ADDR
132410. DP_ADDR_MASK_
132411. DP_ADJUST_PRE_EMPHASIS_LANE0_MASK
132412. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
132413. DP_ADJUST_PRE_EMPHASIS_LANE1_MASK
132414. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
132415. DP_ADJUST_REQUEST_LANE0_1
132416. DP_ADJUST_REQUEST_LANE2_3
132417. DP_ADJUST_REQUEST_POST_CURSOR2
132418. DP_ADJUST_VOLTAGE_SWING_LANE0_MASK
132419. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
132420. DP_ADJUST_VOLTAGE_SWING_LANE1_MASK
132421. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
132422. DP_AG_FACTOR_100US
132423. DP_AG_FACTOR_10US
132424. DP_AG_FACTOR_1MS
132425. DP_AG_FACTOR_1US
132426. DP_AG_FACTOR_200US
132427. DP_AG_FACTOR_2MS
132428. DP_AG_FACTOR_3MS
132429. DP_AG_FACTOR_500US
132430. DP_AG_FACTOR_MASK
132431. DP_ALLOCATE_PAYLOAD
132432. DP_ALL_PD
132433. DP_ALPM_CAP
132434. DP_ALPM_ENABLE
132435. DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE
132436. DP_ALPM_LOCK_TIMEOUT_ERROR
132437. DP_ALTERNATE_I2C_PATTERN_CAP
132438. DP_ALTERNATE_SCRAMBLER_RESET_CAP
132439. DP_ALTERNATE_SCRAMBLER_RESET_ENABLE
132440. DP_AND
132441. DP_ASSOCIATED_TO_PRECEDING_PORT
132442. DP_ASYNC0
132443. DP_ASYNC1
132444. DP_AUDIO_DELAY0
132445. DP_AUDIO_DELAY1
132446. DP_AUDIO_DELAY2
132447. DP_AUDIO_OUTPUT_ENABLE
132448. DP_AUDIO_REF
132449. DP_AUD_DEC_LAT0
132450. DP_AUD_DEC_LAT1
132451. DP_AUD_DEL_INS0
132452. DP_AUD_DEL_INS1
132453. DP_AUD_DEL_INS2
132454. DP_AUD_PP_LAT0
132455. DP_AUD_PP_LAT1
132456. DP_AUTOMATED_TEST_REQUEST
132457. DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
132458. DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
132459. DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
132460. DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
132461. DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
132462. DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
132463. DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
132464. DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
132465. DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
132466. DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
132467. DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
132468. DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
132469. DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
132470. DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
132471. DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
132472. DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
132473. DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
132474. DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
132475. DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
132476. DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
132477. DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
132478. DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
132479. DP_AUX0_AUX_CONTROL__AUX_EN_MASK
132480. DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT
132481. DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK
132482. DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT
132483. DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
132484. DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
132485. DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
132486. DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
132487. DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK
132488. DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
132489. DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
132490. DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
132491. DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK
132492. DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
132493. DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK
132494. DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT
132495. DP_AUX0_AUX_CONTROL__AUX_RESET_MASK
132496. DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT
132497. DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK
132498. DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT
132499. DP_AUX0_AUX_CONTROL__SPARE_0_MASK
132500. DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT
132501. DP_AUX0_AUX_CONTROL__SPARE_1_MASK
132502. DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT
132503. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
132504. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
132505. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
132506. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
132507. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
132508. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
132509. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
132510. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
132511. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
132512. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
132513. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
132514. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
132515. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
132516. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
132517. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
132518. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
132519. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
132520. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
132521. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
132522. DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
132523. DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
132524. DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
132525. DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK
132526. DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK
132527. DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
132528. DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
132529. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
132530. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
132531. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
132532. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
132533. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
132534. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
132535. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
132536. DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
132537. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
132538. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
132539. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK
132540. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT
132541. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
132542. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK
132543. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT
132544. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
132545. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
132546. DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
132547. DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
132548. DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
132549. DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
132550. DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
132551. DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
132552. DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
132553. DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
132554. DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
132555. DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
132556. DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
132557. DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
132558. DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
132559. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
132560. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
132561. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
132562. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
132563. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
132564. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
132565. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
132566. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
132567. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
132568. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
132569. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
132570. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
132571. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
132572. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
132573. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
132574. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
132575. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
132576. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
132577. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
132578. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
132579. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
132580. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
132581. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
132582. DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
132583. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
132584. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
132585. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
132586. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
132587. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
132588. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
132589. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
132590. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
132591. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
132592. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
132593. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
132594. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
132595. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
132596. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
132597. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
132598. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
132599. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
132600. DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
132601. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
132602. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
132603. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
132604. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
132605. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
132606. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
132607. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
132608. DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
132609. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
132610. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
132611. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
132612. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
132613. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
132614. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
132615. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
132616. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
132617. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
132618. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
132619. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
132620. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
132621. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
132622. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
132623. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
132624. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
132625. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
132626. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
132627. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
132628. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
132629. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
132630. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
132631. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
132632. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
132633. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
132634. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
132635. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
132636. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
132637. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
132638. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
132639. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
132640. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
132641. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
132642. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
132643. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
132644. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
132645. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
132646. DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
132647. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
132648. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
132649. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
132650. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
132651. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
132652. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
132653. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
132654. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
132655. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
132656. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
132657. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
132658. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
132659. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
132660. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
132661. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
132662. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
132663. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
132664. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
132665. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
132666. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
132667. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
132668. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
132669. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
132670. DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
132671. DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK
132672. DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT
132673. DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK
132674. DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
132675. DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
132676. DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
132677. DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK
132678. DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
132679. DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
132680. DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
132681. DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
132682. DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
132683. DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
132684. DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
132685. DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK
132686. DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
132687. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
132688. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
132689. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
132690. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
132691. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
132692. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
132693. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
132694. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
132695. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
132696. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
132697. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
132698. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
132699. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
132700. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
132701. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
132702. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
132703. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
132704. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
132705. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
132706. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
132707. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
132708. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
132709. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
132710. DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
132711. DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
132712. DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
132713. DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
132714. DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
132715. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK
132716. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT
132717. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK
132718. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT
132719. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK
132720. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT
132721. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK
132722. DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT
132723. DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
132724. DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
132725. DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK
132726. DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
132727. DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
132728. DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
132729. DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
132730. DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
132731. DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
132732. DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
132733. DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK
132734. DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
132735. DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
132736. DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT
132737. DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK
132738. DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
132739. DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
132740. DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
132741. DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK
132742. DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
132743. DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
132744. DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
132745. DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
132746. DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
132747. DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
132748. DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
132749. DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK
132750. DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
132751. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
132752. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
132753. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
132754. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
132755. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
132756. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
132757. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
132758. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
132759. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
132760. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
132761. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
132762. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
132763. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
132764. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
132765. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
132766. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
132767. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
132768. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
132769. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
132770. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
132771. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
132772. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
132773. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
132774. DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
132775. DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
132776. DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
132777. DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
132778. DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
132779. DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
132780. DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
132781. DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
132782. DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
132783. DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
132784. DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
132785. DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
132786. DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
132787. DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
132788. DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
132789. DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
132790. DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
132791. DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
132792. DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
132793. DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
132794. DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
132795. DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
132796. DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
132797. DP_AUX1_AUX_CONTROL__AUX_EN_MASK
132798. DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT
132799. DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK
132800. DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT
132801. DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
132802. DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
132803. DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
132804. DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
132805. DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK
132806. DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
132807. DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
132808. DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
132809. DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK
132810. DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
132811. DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK
132812. DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT
132813. DP_AUX1_AUX_CONTROL__AUX_RESET_MASK
132814. DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT
132815. DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK
132816. DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT
132817. DP_AUX1_AUX_CONTROL__SPARE_0_MASK
132818. DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT
132819. DP_AUX1_AUX_CONTROL__SPARE_1_MASK
132820. DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT
132821. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
132822. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
132823. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
132824. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
132825. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
132826. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
132827. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
132828. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
132829. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
132830. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
132831. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
132832. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
132833. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
132834. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
132835. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
132836. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
132837. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
132838. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
132839. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
132840. DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
132841. DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
132842. DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
132843. DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK
132844. DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK
132845. DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
132846. DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
132847. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
132848. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
132849. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
132850. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
132851. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
132852. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
132853. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
132854. DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
132855. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
132856. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
132857. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK
132858. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT
132859. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
132860. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK
132861. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT
132862. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
132863. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
132864. DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
132865. DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
132866. DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
132867. DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
132868. DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
132869. DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
132870. DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
132871. DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
132872. DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
132873. DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
132874. DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
132875. DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
132876. DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
132877. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
132878. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
132879. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
132880. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
132881. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
132882. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
132883. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
132884. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
132885. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
132886. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
132887. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
132888. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
132889. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
132890. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
132891. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
132892. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
132893. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
132894. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
132895. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
132896. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
132897. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
132898. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
132899. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
132900. DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
132901. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
132902. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
132903. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
132904. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
132905. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
132906. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
132907. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
132908. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
132909. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
132910. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
132911. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
132912. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
132913. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
132914. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
132915. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
132916. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
132917. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
132918. DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
132919. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
132920. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
132921. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
132922. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
132923. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
132924. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
132925. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
132926. DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
132927. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
132928. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
132929. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
132930. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
132931. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
132932. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
132933. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
132934. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
132935. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
132936. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
132937. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
132938. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
132939. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
132940. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
132941. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
132942. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
132943. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
132944. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
132945. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
132946. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
132947. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
132948. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
132949. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
132950. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
132951. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
132952. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
132953. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
132954. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
132955. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
132956. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
132957. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
132958. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
132959. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
132960. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
132961. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
132962. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
132963. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
132964. DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
132965. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
132966. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
132967. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
132968. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
132969. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
132970. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
132971. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
132972. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
132973. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
132974. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
132975. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
132976. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
132977. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
132978. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
132979. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
132980. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
132981. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
132982. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
132983. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
132984. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
132985. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
132986. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
132987. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
132988. DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
132989. DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK
132990. DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT
132991. DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK
132992. DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
132993. DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
132994. DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
132995. DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK
132996. DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
132997. DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
132998. DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
132999. DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
133000. DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
133001. DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
133002. DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
133003. DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK
133004. DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
133005. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
133006. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
133007. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
133008. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
133009. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
133010. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
133011. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
133012. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
133013. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
133014. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
133015. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
133016. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
133017. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
133018. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
133019. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
133020. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
133021. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
133022. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
133023. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
133024. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
133025. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
133026. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
133027. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
133028. DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
133029. DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
133030. DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
133031. DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
133032. DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
133033. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK
133034. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT
133035. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK
133036. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT
133037. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK
133038. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT
133039. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK
133040. DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT
133041. DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
133042. DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
133043. DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK
133044. DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
133045. DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
133046. DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
133047. DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
133048. DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
133049. DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
133050. DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
133051. DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK
133052. DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
133053. DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
133054. DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT
133055. DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK
133056. DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
133057. DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
133058. DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
133059. DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK
133060. DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
133061. DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
133062. DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
133063. DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
133064. DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
133065. DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
133066. DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
133067. DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK
133068. DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
133069. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
133070. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
133071. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
133072. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
133073. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
133074. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
133075. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
133076. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
133077. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
133078. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
133079. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
133080. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
133081. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
133082. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
133083. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
133084. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
133085. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
133086. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
133087. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
133088. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
133089. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
133090. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
133091. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
133092. DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
133093. DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK
133094. DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT
133095. DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK
133096. DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT
133097. DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK
133098. DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT
133099. DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK
133100. DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT
133101. DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK
133102. DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT
133103. DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK
133104. DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT
133105. DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK
133106. DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT
133107. DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK
133108. DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT
133109. DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK
133110. DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT
133111. DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J_MASK
133112. DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J__SHIFT
133113. DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K_MASK
133114. DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K__SHIFT
133115. DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L_MASK
133116. DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L__SHIFT
133117. DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M_MASK
133118. DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M__SHIFT
133119. DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N_MASK
133120. DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N__SHIFT
133121. DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O_MASK
133122. DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O__SHIFT
133123. DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P_MASK
133124. DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P__SHIFT
133125. DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q_MASK
133126. DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q__SHIFT
133127. DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
133128. DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
133129. DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
133130. DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
133131. DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
133132. DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
133133. DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
133134. DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
133135. DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
133136. DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
133137. DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
133138. DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
133139. DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
133140. DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
133141. DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
133142. DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
133143. DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
133144. DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
133145. DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
133146. DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
133147. DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
133148. DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
133149. DP_AUX2_AUX_CONTROL__AUX_EN_MASK
133150. DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT
133151. DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK
133152. DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT
133153. DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
133154. DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
133155. DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
133156. DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
133157. DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK
133158. DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
133159. DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
133160. DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
133161. DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK
133162. DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
133163. DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK
133164. DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT
133165. DP_AUX2_AUX_CONTROL__AUX_RESET_MASK
133166. DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT
133167. DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK
133168. DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT
133169. DP_AUX2_AUX_CONTROL__SPARE_0_MASK
133170. DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT
133171. DP_AUX2_AUX_CONTROL__SPARE_1_MASK
133172. DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT
133173. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
133174. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
133175. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
133176. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
133177. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
133178. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
133179. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
133180. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
133181. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
133182. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
133183. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
133184. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
133185. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
133186. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
133187. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
133188. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
133189. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
133190. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
133191. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
133192. DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
133193. DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
133194. DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
133195. DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK
133196. DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK
133197. DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
133198. DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
133199. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
133200. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
133201. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
133202. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
133203. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
133204. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
133205. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
133206. DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
133207. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
133208. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
133209. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK
133210. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT
133211. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
133212. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK
133213. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT
133214. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
133215. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
133216. DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
133217. DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
133218. DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
133219. DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
133220. DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
133221. DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
133222. DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
133223. DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
133224. DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
133225. DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
133226. DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
133227. DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
133228. DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
133229. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
133230. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
133231. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
133232. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
133233. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
133234. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
133235. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
133236. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
133237. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
133238. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
133239. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
133240. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
133241. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
133242. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
133243. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
133244. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
133245. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
133246. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
133247. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
133248. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
133249. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
133250. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
133251. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
133252. DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
133253. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
133254. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
133255. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
133256. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
133257. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
133258. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
133259. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
133260. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
133261. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
133262. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
133263. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
133264. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
133265. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
133266. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
133267. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
133268. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
133269. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
133270. DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
133271. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
133272. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
133273. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
133274. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
133275. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
133276. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
133277. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
133278. DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
133279. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
133280. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
133281. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
133282. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
133283. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
133284. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
133285. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
133286. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
133287. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
133288. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
133289. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
133290. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
133291. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
133292. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
133293. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
133294. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
133295. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
133296. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
133297. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
133298. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
133299. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
133300. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
133301. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
133302. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
133303. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
133304. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
133305. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
133306. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
133307. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
133308. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
133309. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
133310. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
133311. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
133312. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
133313. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
133314. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
133315. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
133316. DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
133317. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
133318. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
133319. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
133320. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
133321. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
133322. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
133323. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
133324. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
133325. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
133326. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
133327. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
133328. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
133329. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
133330. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
133331. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
133332. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
133333. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
133334. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
133335. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
133336. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
133337. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
133338. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
133339. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
133340. DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
133341. DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK
133342. DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT
133343. DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK
133344. DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
133345. DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
133346. DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
133347. DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK
133348. DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
133349. DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
133350. DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
133351. DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
133352. DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
133353. DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
133354. DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
133355. DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK
133356. DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
133357. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
133358. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
133359. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
133360. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
133361. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
133362. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
133363. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
133364. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
133365. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
133366. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
133367. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
133368. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
133369. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
133370. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
133371. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
133372. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
133373. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
133374. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
133375. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
133376. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
133377. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
133378. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
133379. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
133380. DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
133381. DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
133382. DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
133383. DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
133384. DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
133385. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK
133386. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT
133387. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK
133388. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT
133389. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK
133390. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT
133391. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK
133392. DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT
133393. DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
133394. DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
133395. DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK
133396. DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
133397. DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
133398. DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
133399. DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
133400. DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
133401. DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
133402. DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
133403. DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK
133404. DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
133405. DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
133406. DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT
133407. DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK
133408. DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
133409. DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
133410. DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
133411. DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK
133412. DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
133413. DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
133414. DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
133415. DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
133416. DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
133417. DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
133418. DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
133419. DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK
133420. DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
133421. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
133422. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
133423. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
133424. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
133425. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
133426. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
133427. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
133428. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
133429. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
133430. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
133431. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
133432. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
133433. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
133434. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
133435. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
133436. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
133437. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
133438. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
133439. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
133440. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
133441. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
133442. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
133443. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
133444. DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
133445. DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK
133446. DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT
133447. DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK
133448. DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT
133449. DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK
133450. DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT
133451. DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK
133452. DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT
133453. DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK
133454. DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT
133455. DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK
133456. DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT
133457. DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK
133458. DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT
133459. DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK
133460. DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT
133461. DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK
133462. DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT
133463. DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J_MASK
133464. DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J__SHIFT
133465. DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K_MASK
133466. DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K__SHIFT
133467. DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L_MASK
133468. DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L__SHIFT
133469. DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M_MASK
133470. DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M__SHIFT
133471. DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N_MASK
133472. DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N__SHIFT
133473. DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O_MASK
133474. DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O__SHIFT
133475. DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P_MASK
133476. DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P__SHIFT
133477. DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q_MASK
133478. DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q__SHIFT
133479. DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
133480. DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
133481. DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
133482. DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
133483. DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
133484. DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
133485. DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
133486. DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
133487. DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
133488. DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
133489. DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
133490. DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
133491. DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
133492. DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
133493. DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
133494. DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
133495. DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
133496. DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
133497. DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
133498. DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
133499. DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
133500. DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
133501. DP_AUX3_AUX_CONTROL__AUX_EN_MASK
133502. DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT
133503. DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK
133504. DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT
133505. DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
133506. DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
133507. DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
133508. DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
133509. DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK
133510. DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
133511. DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
133512. DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
133513. DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK
133514. DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
133515. DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK
133516. DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT
133517. DP_AUX3_AUX_CONTROL__AUX_RESET_MASK
133518. DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT
133519. DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK
133520. DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT
133521. DP_AUX3_AUX_CONTROL__SPARE_0_MASK
133522. DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT
133523. DP_AUX3_AUX_CONTROL__SPARE_1_MASK
133524. DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT
133525. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
133526. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
133527. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
133528. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
133529. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
133530. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
133531. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
133532. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
133533. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
133534. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
133535. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
133536. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
133537. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
133538. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
133539. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
133540. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
133541. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
133542. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
133543. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
133544. DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
133545. DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
133546. DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
133547. DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK
133548. DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK
133549. DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
133550. DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
133551. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
133552. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
133553. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
133554. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
133555. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
133556. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
133557. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
133558. DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
133559. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
133560. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
133561. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK
133562. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT
133563. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
133564. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK
133565. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT
133566. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
133567. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
133568. DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
133569. DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
133570. DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
133571. DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
133572. DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
133573. DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
133574. DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
133575. DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
133576. DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
133577. DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
133578. DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
133579. DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
133580. DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
133581. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
133582. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
133583. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
133584. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
133585. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
133586. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
133587. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
133588. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
133589. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
133590. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
133591. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
133592. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
133593. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
133594. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
133595. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
133596. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
133597. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
133598. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
133599. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
133600. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
133601. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
133602. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
133603. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
133604. DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
133605. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
133606. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
133607. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
133608. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
133609. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
133610. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
133611. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
133612. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
133613. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
133614. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
133615. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
133616. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
133617. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
133618. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
133619. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
133620. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
133621. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
133622. DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
133623. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
133624. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
133625. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
133626. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
133627. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
133628. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
133629. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
133630. DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
133631. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
133632. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
133633. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
133634. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
133635. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
133636. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
133637. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
133638. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
133639. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
133640. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
133641. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
133642. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
133643. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
133644. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
133645. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
133646. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
133647. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
133648. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
133649. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
133650. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
133651. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
133652. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
133653. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
133654. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
133655. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
133656. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
133657. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
133658. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
133659. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
133660. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
133661. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
133662. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
133663. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
133664. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
133665. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
133666. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
133667. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
133668. DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
133669. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
133670. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
133671. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
133672. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
133673. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
133674. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
133675. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
133676. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
133677. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
133678. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
133679. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
133680. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
133681. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
133682. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
133683. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
133684. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
133685. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
133686. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
133687. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
133688. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
133689. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
133690. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
133691. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
133692. DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
133693. DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK
133694. DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT
133695. DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK
133696. DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
133697. DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
133698. DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
133699. DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK
133700. DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
133701. DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
133702. DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
133703. DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
133704. DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
133705. DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
133706. DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
133707. DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK
133708. DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
133709. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
133710. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
133711. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
133712. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
133713. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
133714. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
133715. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
133716. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
133717. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
133718. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
133719. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
133720. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
133721. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
133722. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
133723. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
133724. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
133725. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
133726. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
133727. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
133728. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
133729. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
133730. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
133731. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
133732. DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
133733. DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
133734. DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
133735. DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
133736. DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
133737. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK
133738. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT
133739. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK
133740. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT
133741. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK
133742. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT
133743. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK
133744. DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT
133745. DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
133746. DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
133747. DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK
133748. DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
133749. DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
133750. DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
133751. DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
133752. DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
133753. DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
133754. DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
133755. DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK
133756. DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
133757. DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
133758. DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT
133759. DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK
133760. DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
133761. DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
133762. DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
133763. DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK
133764. DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
133765. DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
133766. DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
133767. DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
133768. DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
133769. DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
133770. DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
133771. DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK
133772. DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
133773. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
133774. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
133775. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
133776. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
133777. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
133778. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
133779. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
133780. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
133781. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
133782. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
133783. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
133784. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
133785. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
133786. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
133787. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
133788. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
133789. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
133790. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
133791. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
133792. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
133793. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
133794. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
133795. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
133796. DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
133797. DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK
133798. DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT
133799. DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK
133800. DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT
133801. DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK
133802. DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT
133803. DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK
133804. DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT
133805. DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK
133806. DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT
133807. DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK
133808. DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT
133809. DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK
133810. DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT
133811. DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK
133812. DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT
133813. DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK
133814. DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT
133815. DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J_MASK
133816. DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J__SHIFT
133817. DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K_MASK
133818. DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K__SHIFT
133819. DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L_MASK
133820. DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L__SHIFT
133821. DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M_MASK
133822. DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M__SHIFT
133823. DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N_MASK
133824. DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N__SHIFT
133825. DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O_MASK
133826. DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O__SHIFT
133827. DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P_MASK
133828. DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P__SHIFT
133829. DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q_MASK
133830. DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q__SHIFT
133831. DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
133832. DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
133833. DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
133834. DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
133835. DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
133836. DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
133837. DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
133838. DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
133839. DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
133840. DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
133841. DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
133842. DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
133843. DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
133844. DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
133845. DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
133846. DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
133847. DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
133848. DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
133849. DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
133850. DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
133851. DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
133852. DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
133853. DP_AUX4_AUX_CONTROL__AUX_EN_MASK
133854. DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT
133855. DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK
133856. DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT
133857. DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
133858. DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
133859. DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
133860. DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
133861. DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK
133862. DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
133863. DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
133864. DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
133865. DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK
133866. DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
133867. DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK
133868. DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT
133869. DP_AUX4_AUX_CONTROL__AUX_RESET_MASK
133870. DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT
133871. DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK
133872. DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT
133873. DP_AUX4_AUX_CONTROL__SPARE_0_MASK
133874. DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT
133875. DP_AUX4_AUX_CONTROL__SPARE_1_MASK
133876. DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT
133877. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
133878. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
133879. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
133880. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
133881. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
133882. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
133883. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
133884. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
133885. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
133886. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
133887. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
133888. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
133889. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
133890. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
133891. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
133892. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
133893. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
133894. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
133895. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
133896. DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
133897. DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
133898. DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
133899. DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK
133900. DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK
133901. DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
133902. DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
133903. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
133904. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
133905. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
133906. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
133907. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
133908. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
133909. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
133910. DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
133911. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
133912. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
133913. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK
133914. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT
133915. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
133916. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK
133917. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT
133918. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
133919. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
133920. DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
133921. DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
133922. DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
133923. DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
133924. DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
133925. DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
133926. DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
133927. DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
133928. DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
133929. DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
133930. DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
133931. DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
133932. DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
133933. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
133934. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
133935. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
133936. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
133937. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
133938. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
133939. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
133940. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
133941. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
133942. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
133943. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
133944. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
133945. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
133946. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
133947. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
133948. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
133949. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
133950. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
133951. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
133952. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
133953. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
133954. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
133955. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
133956. DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
133957. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
133958. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
133959. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
133960. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
133961. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
133962. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
133963. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
133964. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
133965. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
133966. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
133967. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
133968. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
133969. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
133970. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
133971. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
133972. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
133973. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
133974. DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
133975. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
133976. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
133977. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
133978. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
133979. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
133980. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
133981. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
133982. DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
133983. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
133984. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
133985. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
133986. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
133987. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
133988. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
133989. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
133990. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
133991. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
133992. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
133993. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
133994. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
133995. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
133996. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
133997. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
133998. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
133999. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
134000. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
134001. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
134002. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
134003. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
134004. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
134005. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
134006. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
134007. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
134008. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
134009. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
134010. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
134011. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
134012. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
134013. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
134014. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
134015. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
134016. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
134017. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
134018. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
134019. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
134020. DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
134021. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
134022. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
134023. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
134024. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
134025. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
134026. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
134027. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
134028. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
134029. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
134030. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
134031. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
134032. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
134033. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
134034. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
134035. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
134036. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
134037. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
134038. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
134039. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
134040. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
134041. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
134042. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
134043. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
134044. DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
134045. DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK
134046. DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT
134047. DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK
134048. DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
134049. DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
134050. DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
134051. DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK
134052. DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
134053. DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
134054. DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
134055. DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
134056. DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
134057. DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
134058. DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
134059. DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK
134060. DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
134061. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
134062. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
134063. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
134064. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
134065. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
134066. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
134067. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
134068. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
134069. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
134070. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
134071. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
134072. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
134073. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
134074. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
134075. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
134076. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
134077. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
134078. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
134079. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
134080. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
134081. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
134082. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
134083. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
134084. DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
134085. DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
134086. DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
134087. DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
134088. DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
134089. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK
134090. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT
134091. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK
134092. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT
134093. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK
134094. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT
134095. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK
134096. DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT
134097. DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
134098. DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
134099. DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK
134100. DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
134101. DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
134102. DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
134103. DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
134104. DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
134105. DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
134106. DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
134107. DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK
134108. DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
134109. DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
134110. DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT
134111. DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK
134112. DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
134113. DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
134114. DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
134115. DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK
134116. DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
134117. DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
134118. DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
134119. DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
134120. DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
134121. DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
134122. DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
134123. DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK
134124. DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
134125. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
134126. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
134127. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
134128. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
134129. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
134130. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
134131. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
134132. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
134133. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
134134. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
134135. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
134136. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
134137. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
134138. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
134139. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
134140. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
134141. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
134142. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
134143. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
134144. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
134145. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
134146. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
134147. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
134148. DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
134149. DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK
134150. DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT
134151. DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK
134152. DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT
134153. DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK
134154. DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT
134155. DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK
134156. DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT
134157. DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK
134158. DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT
134159. DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK
134160. DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT
134161. DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK
134162. DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT
134163. DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK
134164. DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT
134165. DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK
134166. DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT
134167. DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J_MASK
134168. DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J__SHIFT
134169. DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K_MASK
134170. DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K__SHIFT
134171. DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L_MASK
134172. DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L__SHIFT
134173. DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M_MASK
134174. DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M__SHIFT
134175. DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N_MASK
134176. DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N__SHIFT
134177. DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O_MASK
134178. DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O__SHIFT
134179. DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P_MASK
134180. DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P__SHIFT
134181. DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q_MASK
134182. DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q__SHIFT
134183. DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
134184. DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
134185. DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
134186. DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
134187. DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
134188. DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
134189. DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
134190. DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
134191. DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
134192. DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
134193. DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
134194. DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
134195. DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
134196. DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
134197. DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
134198. DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
134199. DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
134200. DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
134201. DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
134202. DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
134203. DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
134204. DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
134205. DP_AUX5_AUX_CONTROL__AUX_EN_MASK
134206. DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT
134207. DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK
134208. DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT
134209. DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
134210. DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
134211. DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
134212. DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
134213. DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK
134214. DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
134215. DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
134216. DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
134217. DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK
134218. DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
134219. DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK
134220. DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT
134221. DP_AUX5_AUX_CONTROL__AUX_RESET_MASK
134222. DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT
134223. DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK
134224. DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT
134225. DP_AUX5_AUX_CONTROL__SPARE_0_MASK
134226. DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT
134227. DP_AUX5_AUX_CONTROL__SPARE_1_MASK
134228. DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT
134229. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
134230. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
134231. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
134232. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
134233. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
134234. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
134235. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
134236. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
134237. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
134238. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
134239. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
134240. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
134241. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
134242. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
134243. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
134244. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
134245. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
134246. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
134247. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
134248. DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
134249. DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
134250. DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
134251. DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK
134252. DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK
134253. DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
134254. DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
134255. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
134256. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
134257. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
134258. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
134259. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
134260. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
134261. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
134262. DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
134263. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
134264. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
134265. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK
134266. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT
134267. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
134268. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK
134269. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT
134270. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
134271. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
134272. DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
134273. DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
134274. DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
134275. DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
134276. DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
134277. DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
134278. DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
134279. DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
134280. DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
134281. DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
134282. DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
134283. DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
134284. DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
134285. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
134286. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
134287. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
134288. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
134289. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
134290. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
134291. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
134292. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
134293. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
134294. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
134295. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
134296. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
134297. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
134298. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
134299. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
134300. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
134301. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
134302. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
134303. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
134304. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
134305. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
134306. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
134307. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
134308. DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
134309. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
134310. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
134311. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
134312. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
134313. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
134314. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
134315. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
134316. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
134317. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
134318. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
134319. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
134320. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
134321. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
134322. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
134323. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
134324. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
134325. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
134326. DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
134327. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
134328. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
134329. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
134330. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
134331. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
134332. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
134333. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
134334. DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
134335. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
134336. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
134337. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
134338. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
134339. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
134340. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
134341. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
134342. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
134343. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
134344. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
134345. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
134346. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
134347. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
134348. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
134349. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
134350. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
134351. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
134352. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
134353. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
134354. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
134355. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
134356. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
134357. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
134358. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
134359. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
134360. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
134361. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
134362. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
134363. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
134364. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
134365. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
134366. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
134367. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
134368. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
134369. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
134370. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
134371. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
134372. DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
134373. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
134374. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
134375. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
134376. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
134377. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
134378. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
134379. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
134380. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
134381. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
134382. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
134383. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
134384. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
134385. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
134386. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
134387. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
134388. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
134389. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
134390. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
134391. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
134392. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
134393. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
134394. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
134395. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
134396. DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
134397. DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK
134398. DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT
134399. DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK
134400. DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
134401. DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
134402. DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
134403. DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK
134404. DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
134405. DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
134406. DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
134407. DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
134408. DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
134409. DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
134410. DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
134411. DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK
134412. DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
134413. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
134414. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
134415. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
134416. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
134417. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
134418. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
134419. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
134420. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
134421. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
134422. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
134423. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
134424. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
134425. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
134426. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
134427. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
134428. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
134429. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
134430. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
134431. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
134432. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
134433. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
134434. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
134435. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
134436. DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
134437. DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
134438. DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
134439. DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
134440. DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
134441. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK
134442. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT
134443. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK
134444. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT
134445. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK
134446. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT
134447. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK
134448. DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT
134449. DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
134450. DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
134451. DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK
134452. DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
134453. DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
134454. DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
134455. DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
134456. DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
134457. DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
134458. DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
134459. DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK
134460. DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
134461. DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
134462. DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT
134463. DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK
134464. DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
134465. DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
134466. DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
134467. DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK
134468. DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
134469. DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
134470. DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
134471. DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
134472. DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
134473. DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
134474. DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
134475. DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK
134476. DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
134477. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
134478. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
134479. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
134480. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
134481. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
134482. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
134483. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
134484. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
134485. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
134486. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
134487. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
134488. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
134489. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
134490. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
134491. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
134492. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
134493. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
134494. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
134495. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
134496. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
134497. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
134498. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
134499. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
134500. DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
134501. DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK
134502. DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT
134503. DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK
134504. DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT
134505. DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK
134506. DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT
134507. DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK
134508. DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT
134509. DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK
134510. DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT
134511. DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK
134512. DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT
134513. DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK
134514. DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT
134515. DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK
134516. DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT
134517. DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK
134518. DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT
134519. DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J_MASK
134520. DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J__SHIFT
134521. DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K_MASK
134522. DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K__SHIFT
134523. DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L_MASK
134524. DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L__SHIFT
134525. DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M_MASK
134526. DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M__SHIFT
134527. DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N_MASK
134528. DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N__SHIFT
134529. DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O_MASK
134530. DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O__SHIFT
134531. DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P_MASK
134532. DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P__SHIFT
134533. DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q_MASK
134534. DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q__SHIFT
134535. DP_AUX6_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
134536. DP_AUX6_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
134537. DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
134538. DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
134539. DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
134540. DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
134541. DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
134542. DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
134543. DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
134544. DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
134545. DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
134546. DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
134547. DP_AUX6_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
134548. DP_AUX6_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
134549. DP_AUX6_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
134550. DP_AUX6_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
134551. DP_AUX6_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
134552. DP_AUX6_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
134553. DP_AUX6_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
134554. DP_AUX6_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
134555. DP_AUX6_AUX_CONTROL__AUX_DEGLITCH_EN_MASK
134556. DP_AUX6_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
134557. DP_AUX6_AUX_CONTROL__AUX_EN_MASK
134558. DP_AUX6_AUX_CONTROL__AUX_EN__SHIFT
134559. DP_AUX6_AUX_CONTROL__AUX_HPD_SEL_MASK
134560. DP_AUX6_AUX_CONTROL__AUX_HPD_SEL__SHIFT
134561. DP_AUX6_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
134562. DP_AUX6_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
134563. DP_AUX6_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
134564. DP_AUX6_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
134565. DP_AUX6_AUX_CONTROL__AUX_LS_READ_EN_MASK
134566. DP_AUX6_AUX_CONTROL__AUX_LS_READ_EN__SHIFT
134567. DP_AUX6_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
134568. DP_AUX6_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
134569. DP_AUX6_AUX_CONTROL__AUX_MODE_DET_EN_MASK
134570. DP_AUX6_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
134571. DP_AUX6_AUX_CONTROL__AUX_RESET_DONE_MASK
134572. DP_AUX6_AUX_CONTROL__AUX_RESET_DONE__SHIFT
134573. DP_AUX6_AUX_CONTROL__AUX_RESET_MASK
134574. DP_AUX6_AUX_CONTROL__AUX_RESET__SHIFT
134575. DP_AUX6_AUX_CONTROL__AUX_TEST_MODE_MASK
134576. DP_AUX6_AUX_CONTROL__AUX_TEST_MODE__SHIFT
134577. DP_AUX6_AUX_CONTROL__SPARE_0_MASK
134578. DP_AUX6_AUX_CONTROL__SPARE_0__SHIFT
134579. DP_AUX6_AUX_CONTROL__SPARE_1_MASK
134580. DP_AUX6_AUX_CONTROL__SPARE_1__SHIFT
134581. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
134582. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
134583. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
134584. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
134585. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
134586. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
134587. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
134588. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
134589. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
134590. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
134591. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
134592. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
134593. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
134594. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
134595. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
134596. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
134597. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
134598. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
134599. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
134600. DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
134601. DP_AUX6_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
134602. DP_AUX6_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
134603. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
134604. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
134605. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
134606. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
134607. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
134608. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
134609. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
134610. DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
134611. DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
134612. DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
134613. DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
134614. DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
134615. DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
134616. DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
134617. DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
134618. DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
134619. DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
134620. DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
134621. DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
134622. DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
134623. DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
134624. DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
134625. DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
134626. DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
134627. DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
134628. DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
134629. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
134630. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
134631. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
134632. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
134633. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
134634. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
134635. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
134636. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
134637. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
134638. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
134639. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
134640. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
134641. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
134642. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
134643. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
134644. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
134645. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
134646. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
134647. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
134648. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
134649. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
134650. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
134651. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
134652. DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
134653. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
134654. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
134655. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
134656. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
134657. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
134658. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
134659. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
134660. DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
134661. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
134662. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
134663. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
134664. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
134665. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
134666. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
134667. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
134668. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
134669. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
134670. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
134671. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
134672. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
134673. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
134674. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
134675. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
134676. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
134677. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
134678. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
134679. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
134680. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
134681. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
134682. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
134683. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
134684. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
134685. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
134686. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
134687. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
134688. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
134689. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
134690. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
134691. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
134692. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
134693. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
134694. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
134695. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
134696. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
134697. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
134698. DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
134699. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
134700. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
134701. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
134702. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
134703. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
134704. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
134705. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
134706. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
134707. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
134708. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
134709. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
134710. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
134711. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
134712. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
134713. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
134714. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
134715. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
134716. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
134717. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
134718. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
134719. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
134720. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
134721. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
134722. DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
134723. DP_AUX6_AUX_LS_DATA__AUX_LS_DATA_MASK
134724. DP_AUX6_AUX_LS_DATA__AUX_LS_DATA__SHIFT
134725. DP_AUX6_AUX_LS_DATA__AUX_LS_INDEX_MASK
134726. DP_AUX6_AUX_LS_DATA__AUX_LS_INDEX__SHIFT
134727. DP_AUX6_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
134728. DP_AUX6_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
134729. DP_AUX6_AUX_LS_STATUS__AUX_LS_DONE_MASK
134730. DP_AUX6_AUX_LS_STATUS__AUX_LS_DONE__SHIFT
134731. DP_AUX6_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
134732. DP_AUX6_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
134733. DP_AUX6_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
134734. DP_AUX6_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
134735. DP_AUX6_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
134736. DP_AUX6_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
134737. DP_AUX6_AUX_LS_STATUS__AUX_LS_REQ_MASK
134738. DP_AUX6_AUX_LS_STATUS__AUX_LS_REQ__SHIFT
134739. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
134740. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
134741. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
134742. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
134743. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
134744. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
134745. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
134746. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
134747. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
134748. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
134749. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
134750. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
134751. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
134752. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
134753. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
134754. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
134755. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
134756. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
134757. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
134758. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
134759. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
134760. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
134761. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
134762. DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
134763. DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
134764. DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
134765. DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_MASK
134766. DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
134767. DP_AUX6_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
134768. DP_AUX6_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
134769. DP_AUX6_AUX_SW_CONTROL__AUX_SW_GO_MASK
134770. DP_AUX6_AUX_SW_CONTROL__AUX_SW_GO__SHIFT
134771. DP_AUX6_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
134772. DP_AUX6_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
134773. DP_AUX6_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
134774. DP_AUX6_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
134775. DP_AUX6_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
134776. DP_AUX6_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
134777. DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_MASK
134778. DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_RW_MASK
134779. DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
134780. DP_AUX6_AUX_SW_DATA__AUX_SW_DATA__SHIFT
134781. DP_AUX6_AUX_SW_DATA__AUX_SW_INDEX_MASK
134782. DP_AUX6_AUX_SW_DATA__AUX_SW_INDEX__SHIFT
134783. DP_AUX6_AUX_SW_STATUS__AUX_ARB_STATUS_MASK
134784. DP_AUX6_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
134785. DP_AUX6_AUX_SW_STATUS__AUX_SW_DONE_MASK
134786. DP_AUX6_AUX_SW_STATUS__AUX_SW_DONE__SHIFT
134787. DP_AUX6_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
134788. DP_AUX6_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
134789. DP_AUX6_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
134790. DP_AUX6_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
134791. DP_AUX6_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
134792. DP_AUX6_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
134793. DP_AUX6_AUX_SW_STATUS__AUX_SW_REQ_MASK
134794. DP_AUX6_AUX_SW_STATUS__AUX_SW_REQ__SHIFT
134795. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
134796. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
134797. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
134798. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
134799. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
134800. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
134801. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
134802. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
134803. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
134804. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
134805. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
134806. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
134807. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
134808. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
134809. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
134810. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
134811. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
134812. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
134813. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
134814. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
134815. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
134816. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
134817. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
134818. DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
134819. DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK
134820. DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT
134821. DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK
134822. DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT
134823. DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK
134824. DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT
134825. DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK
134826. DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT
134827. DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK
134828. DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT
134829. DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK
134830. DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT
134831. DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK
134832. DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT
134833. DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK
134834. DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT
134835. DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK
134836. DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT
134837. DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J_MASK
134838. DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J__SHIFT
134839. DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K_MASK
134840. DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K__SHIFT
134841. DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L_MASK
134842. DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L__SHIFT
134843. DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M_MASK
134844. DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M__SHIFT
134845. DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N_MASK
134846. DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N__SHIFT
134847. DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O_MASK
134848. DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O__SHIFT
134849. DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P_MASK
134850. DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P__SHIFT
134851. DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q_MASK
134852. DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q__SHIFT
134853. DP_AUX_A
134854. DP_AUX_AFE_OUT
134855. DP_AUX_ARB_CONTROL_ARB_PRIORITY
134856. DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW
134857. DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW
134858. DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS
134859. DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC
134860. DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG
134861. DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ
134862. DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG
134863. DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG
134864. DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ
134865. DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ
134866. DP_AUX_B
134867. DP_AUX_C
134868. DP_AUX_CHANNEL_B_INT_STATUS_G4X
134869. DP_AUX_CHANNEL_C_INT_STATUS_G4X
134870. DP_AUX_CHANNEL_D_INT_STATUS_G4X
134871. DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
134872. DP_AUX_CH_CTL
134873. DP_AUX_CH_CTL_AUX_AKSV_SELECT
134874. DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK
134875. DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
134876. DP_AUX_CH_CTL_DEGLITCH_TEST
134877. DP_AUX_CH_CTL_DONE
134878. DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL
134879. DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL
134880. DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK
134881. DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL
134882. DP_AUX_CH_CTL_INTERRUPT
134883. DP_AUX_CH_CTL_MANCHESTER_TEST
134884. DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
134885. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
134886. DP_AUX_CH_CTL_PRECHARGE_2US_MASK
134887. DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
134888. DP_AUX_CH_CTL_PRECHARGE_TEST
134889. DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL
134890. DP_AUX_CH_CTL_RECEIVE_ERROR
134891. DP_AUX_CH_CTL_SEND_BUSY
134892. DP_AUX_CH_CTL_SYNC_PULSE_SKL
134893. DP_AUX_CH_CTL_SYNC_TEST
134894. DP_AUX_CH_CTL_TBT_IO
134895. DP_AUX_CH_CTL_TIME_OUT_1600us
134896. DP_AUX_CH_CTL_TIME_OUT_400us
134897. DP_AUX_CH_CTL_TIME_OUT_600us
134898. DP_AUX_CH_CTL_TIME_OUT_800us
134899. DP_AUX_CH_CTL_TIME_OUT_ERROR
134900. DP_AUX_CH_CTL_TIME_OUT_MASK
134901. DP_AUX_CH_CTL_TIME_OUT_MAX
134902. DP_AUX_CH_DATA
134903. DP_AUX_CLEAR_RX
134904. DP_AUX_CLEAR_TX
134905. DP_AUX_CONTROL_HPD1_SELECTED
134906. DP_AUX_CONTROL_HPD2_SELECTED
134907. DP_AUX_CONTROL_HPD3_SELECTED
134908. DP_AUX_CONTROL_HPD4_SELECTED
134909. DP_AUX_CONTROL_HPD5_SELECTED
134910. DP_AUX_CONTROL_HPD6_SELECTED
134911. DP_AUX_CONTROL_HPD_SEL
134912. DP_AUX_CONTROL_NO_HPD_SELECTED
134913. DP_AUX_CONTROL_TEST_MODE
134914. DP_AUX_CONTROL_TEST_MODE_DISABLE
134915. DP_AUX_CONTROL_TEST_MODE_ENABLE
134916. DP_AUX_D
134917. DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK
134918. DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT
134919. DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK
134920. DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT
134921. DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK
134922. DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT
134923. DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK
134924. DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT
134925. DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK
134926. DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT
134927. DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK
134928. DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT
134929. DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK
134930. DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT
134931. DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK
134932. DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT
134933. DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK
134934. DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT
134935. DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK
134936. DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT
134937. DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK
134938. DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT
134939. DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK
134940. DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT
134941. DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK
134942. DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT
134943. DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK
134944. DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT
134945. DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK
134946. DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT
134947. DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK
134948. DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT
134949. DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK
134950. DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT
134951. DP_AUX_DEFINITE_ERR_REACHED_ACK
134952. DP_AUX_DIVIDE_2M
134953. DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT
134954. DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START
134955. DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP
134956. DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN
134957. DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES
134958. DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES
134959. DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES
134960. DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED
134961. DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN
134962. DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS
134963. DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS
134964. DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS
134965. DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS
134966. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW
134967. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD
134968. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD
134969. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD
134970. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD
134971. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD
134972. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD
134973. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD
134974. DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD
134975. DP_AUX_DPHY_RX_CONTROL_START_WINDOW
134976. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD
134977. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD
134978. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD
134979. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD
134980. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD
134981. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD
134982. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD
134983. DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD
134984. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN
134985. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US
134986. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US
134987. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US
134988. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US
134989. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US
134990. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US
134991. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US
134992. DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US
134993. DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT
134994. DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START
134995. DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP
134996. DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT
134997. DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START
134998. DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP
134999. DP_AUX_DPHY_RX_DETECTION_THRESHOLD
135000. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128
135001. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16
135002. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2
135003. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256
135004. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32
135005. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4
135006. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64
135007. DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8
135008. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY
135009. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0
135010. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US
135011. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US
135012. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US
135013. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US
135014. DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US
135015. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN
135016. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US
135017. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US
135018. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US
135019. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US
135020. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US
135021. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US
135022. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US
135023. DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US
135024. DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE
135025. DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ
135026. DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ
135027. DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ
135028. DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ
135029. DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL
135030. DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK
135031. DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF
135032. DP_AUX_E
135033. DP_AUX_ERR_OCCURRED_ACK
135034. DP_AUX_ERR_OCCURRED__ACK
135035. DP_AUX_ERR_OCCURRED__NOT_ACK
135036. DP_AUX_F
135037. DP_AUX_FRAME_SYNC_CAP
135038. DP_AUX_FRAME_SYNC_ENABLE
135039. DP_AUX_FRAME_SYNC_VALID
135040. DP_AUX_FRAME_SYNC_VALUE
135041. DP_AUX_FREQUENCY_1M_MAX
135042. DP_AUX_FREQUENCY_1M_MIN
135043. DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX
135044. DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ
135045. DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX
135046. DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW
135047. DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US
135048. DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US
135049. DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US
135050. DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US
135051. DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT
135052. DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS
135053. DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS
135054. DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS
135055. DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED
135056. DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN
135057. DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0
135058. DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128
135059. DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256
135060. DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64
135061. DP_AUX_HDCP_AINFO
135062. DP_AUX_HDCP_AKSV
135063. DP_AUX_HDCP_AN
135064. DP_AUX_HDCP_BCAPS
135065. DP_AUX_HDCP_BINFO
135066. DP_AUX_HDCP_BKSV
135067. DP_AUX_HDCP_BSTATUS
135068. DP_AUX_HDCP_KSV_FIFO
135069. DP_AUX_HDCP_RI_PRIME
135070. DP_AUX_HDCP_V_PRIME
135071. DP_AUX_HOST_CONTROL
135072. DP_AUX_I2C_MOT
135073. DP_AUX_I2C_READ
135074. DP_AUX_I2C_REPLY_ACK
135075. DP_AUX_I2C_REPLY_DEFER
135076. DP_AUX_I2C_REPLY_MASK
135077. DP_AUX_I2C_REPLY_NACK
135078. DP_AUX_I2C_WRITE
135079. DP_AUX_I2C_WRITE_STATUS_UPDATE
135080. DP_AUX_INTERRUPT_MASK
135081. DP_AUX_INTERRUPT_SOURCE
135082. DP_AUX_INT_ACK
135083. DP_AUX_INT_LS_UPDATE_ACK
135084. DP_AUX_INT_LS_UPDATE_NOT_ACK
135085. DP_AUX_INT__ACK
135086. DP_AUX_INT__NOT_ACK
135087. DP_AUX_LS_UPDATE_ACK
135088. DP_AUX_MAIN_STATES
135089. DP_AUX_MAIN_TIMER
135090. DP_AUX_MAX_PAYLOAD_BYTES
135091. DP_AUX_NACK_FORMAT
135092. DP_AUX_NATIVE_READ
135093. DP_AUX_NATIVE_REPLY_ACK
135094. DP_AUX_NATIVE_REPLY_DEFER
135095. DP_AUX_NATIVE_REPLY_MASK
135096. DP_AUX_NATIVE_REPLY_NACK
135097. DP_AUX_NATIVE_WRITE
135098. DP_AUX_PHY_WAKE_HIGH_PRIORITY
135099. DP_AUX_PHY_WAKE_LOW_PRIORITY
135100. DP_AUX_PHY_WAKE_PRIORITY
135101. DP_AUX_POTENTIAL_ERR_REACHED_ACK
135102. DP_AUX_POTENTIAL_ERR_REACHED__ACK
135103. DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK
135104. DP_AUX_RESET
135105. DP_AUX_RESET_ASSERTED
135106. DP_AUX_RESET_DEASSERTED
135107. DP_AUX_RESET_DONE
135108. DP_AUX_RESET_SEQUENCE_DONE
135109. DP_AUX_RESET_SEQUENCE_NOT_DONE
135110. DP_AUX_RESET_SW
135111. DP_AUX_RX_CYCLE_COUNTER
135112. DP_AUX_RX_DATA
135113. DP_AUX_RX_PRE_MAX
135114. DP_AUX_RX_PRE_MIN
135115. DP_AUX_RX_STATUS
135116. DP_AUX_RX_TIMEOUT_LEN_MUL
135117. DP_AUX_RX_TIMEOUT_LEN_MUL_2
135118. DP_AUX_RX_TIMEOUT_LEN_MUL_4
135119. DP_AUX_RX_TIMEOUT_LEN_MUL_8
135120. DP_AUX_RX_TIMEOUT_LEN_NO_MUL
135121. DP_AUX_SEND_NACK_TRANSACTION
135122. DP_AUX_SWAP_INVERSION_CONTROL
135123. DP_AUX_SW_CONTROL_LS_READ_TRIG
135124. DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG
135125. DP_AUX_SW_CONTROL_LS_READ__TRIG
135126. DP_AUX_SW_CONTROL_SW_GO
135127. DP_AUX_SW_CONTROL_SW__GO
135128. DP_AUX_SW_CONTROL_SW__NOT_GO
135129. DP_AUX_TIMER_CLEAR
135130. DP_AUX_TIMER_PRESET
135131. DP_AUX_TIMER_STOP
135132. DP_AUX_TX_DATA
135133. DP_AUX_TX_PREACHARGE_LENGTH
135134. DP_AUX_TX_PRECHARGE_LEN_MUL
135135. DP_AUX_TX_PRECHARGE_LEN_MUL_2
135136. DP_AUX_TX_PRECHARGE_LEN_MUL_4
135137. DP_AUX_TX_PRECHARGE_LEN_MUL_8
135138. DP_AUX_TX_PRECHARGE_LEN_NO_MUL
135139. DP_AUX_TX_STATUS
135140. DP_AV_GRANULARITY
135141. DP_AV_SYNC_CAP
135142. DP_A_HOTPLUG
135143. DP_Alt_mode__Connect
135144. DP_Alt_mode__NoConnect
135145. DP_Alt_mode__Unknown
135146. DP_B
135147. DP_BB_REG_NUM
135148. DP_BCAPS_HDCP_CAPABLE
135149. DP_BCAPS_REPEATER_PRESENT
135150. DP_BKGD_CLR
135151. DP_BLACK_AND_WHITE_VERTICAL_LINES
135152. DP_BLANK_MAX_RETRY
135153. DP_BLOCK_SDP
135154. DP_BRANCH_DEVICE_CTRL
135155. DP_BRANCH_DEVICE_ID_00001A
135156. DP_BRANCH_DEVICE_ID_0010FA
135157. DP_BRANCH_DEVICE_ID_0022B9
135158. DP_BRANCH_DEVICE_ID_0080E1
135159. DP_BRANCH_DEVICE_ID_00E04C
135160. DP_BRANCH_DEVICE_ID_90CC24
135161. DP_BRANCH_DEVICE_IRQ_HPD
135162. DP_BRANCH_HW_REV
135163. DP_BRANCH_ID
135164. DP_BRANCH_OUI
135165. DP_BRANCH_OUI_HEADER_SIZE
135166. DP_BRANCH_REVISION_START
135167. DP_BRANCH_SW_REV
135168. DP_BRUSH_BKGD_CLR
135169. DP_BRUSH_FRGD_CLR
135170. DP_BSTATUS_LINK_FAILURE
135171. DP_BSTATUS_R0_PRIME_READY
135172. DP_BSTATUS_READY
135173. DP_BSTATUS_REAUTH_REQ
135174. DP_BYTE_COUNT
135175. DP_B_HOTPLUG
135176. DP_C
135177. DP_CAP_CAPABILITY
135178. DP_CAP_DFP_D
135179. DP_CAP_DFP_D_AND_UFP_D
135180. DP_CAP_DFP_D_PIN_ASSIGN
135181. DP_CAP_DP_SIGNALING
135182. DP_CAP_GEN2
135183. DP_CAP_RECEPTACLE
135184. DP_CAP_UFP_D
135185. DP_CAP_UFP_D_PIN_ASSIGN
135186. DP_CAP_USB
135187. DP_CEC_IRQ
135188. DP_CEC_LOGICAL_ADDRESS_0
135189. DP_CEC_LOGICAL_ADDRESS_1
135190. DP_CEC_LOGICAL_ADDRESS_10
135191. DP_CEC_LOGICAL_ADDRESS_11
135192. DP_CEC_LOGICAL_ADDRESS_12
135193. DP_CEC_LOGICAL_ADDRESS_13
135194. DP_CEC_LOGICAL_ADDRESS_14
135195. DP_CEC_LOGICAL_ADDRESS_15
135196. DP_CEC_LOGICAL_ADDRESS_2
135197. DP_CEC_LOGICAL_ADDRESS_3
135198. DP_CEC_LOGICAL_ADDRESS_4
135199. DP_CEC_LOGICAL_ADDRESS_5
135200. DP_CEC_LOGICAL_ADDRESS_6
135201. DP_CEC_LOGICAL_ADDRESS_7
135202. DP_CEC_LOGICAL_ADDRESS_8
135203. DP_CEC_LOGICAL_ADDRESS_9
135204. DP_CEC_LOGICAL_ADDRESS_MASK
135205. DP_CEC_LOGICAL_ADDRESS_MASK_2
135206. DP_CEC_MESSAGE_BUFFER_LENGTH
135207. DP_CEC_MULTIPLE_LA_CAPABLE
135208. DP_CEC_RX_MESSAGE_ACKED
135209. DP_CEC_RX_MESSAGE_BUFFER
135210. DP_CEC_RX_MESSAGE_ENDED
135211. DP_CEC_RX_MESSAGE_HPD_LOST
135212. DP_CEC_RX_MESSAGE_HPD_STATE
135213. DP_CEC_RX_MESSAGE_INFO
135214. DP_CEC_RX_MESSAGE_INFO_VALID
135215. DP_CEC_RX_MESSAGE_LEN_MASK
135216. DP_CEC_RX_MESSAGE_LEN_SHIFT
135217. DP_CEC_RX_MESSAGE_OVERFLOW
135218. DP_CEC_SNOOPING_CAPABLE
135219. DP_CEC_SNOOPING_ENABLE
135220. DP_CEC_TUNNELING_CAPABILITY
135221. DP_CEC_TUNNELING_CAPABLE
135222. DP_CEC_TUNNELING_CONTROL
135223. DP_CEC_TUNNELING_ENABLE
135224. DP_CEC_TUNNELING_IRQ_FLAGS
135225. DP_CEC_TX_ADDRESS_NACK_ERROR
135226. DP_CEC_TX_DATA_NACK_ERROR
135227. DP_CEC_TX_LINE_ERROR
135228. DP_CEC_TX_MESSAGE_BUFFER
135229. DP_CEC_TX_MESSAGE_INFO
135230. DP_CEC_TX_MESSAGE_LEN_MASK
135231. DP_CEC_TX_MESSAGE_LEN_SHIFT
135232. DP_CEC_TX_MESSAGE_SEND
135233. DP_CEC_TX_MESSAGE_SENT
135234. DP_CEC_TX_RETRY_COUNT_MASK
135235. DP_CEC_TX_RETRY_COUNT_SHIFT
135236. DP_CHAIN_15BPP
135237. DP_CHAIN_16BPP
135238. DP_CHAIN_24BPP
135239. DP_CHAIN_32BPP
135240. DP_CHAIN_4BPP
135241. DP_CHAIN_7BPP
135242. DP_CHAIN_8BPP
135243. DP_CHAIN_8BPP_RGB
135244. DP_CHAIN_MASK
135245. DP_CHANNEL_EQ_BITS
135246. DP_CLEAR_PAYLOAD_ID_TABLE
135247. DP_CLK_CTL
135248. DP_CLK_FUDGE_DEN
135249. DP_CLK_FUDGE_NUM
135250. DP_CLOCK_OUTPUT_ENABLE
135251. DP_CMD
135252. DP_CMD_CONFIGURE
135253. DP_CMD_READ
135254. DP_CMD_READ_
135255. DP_CMD_STATUS_UPDATE
135256. DP_CMD_WRITE
135257. DP_CMD_WRITE_
135258. DP_CNTL
135259. DP_CNTL_XDIR_YDIR_YMAJOR
135260. DP_COLOR_FORMAT_RGB
135261. DP_COLOR_FORMAT_YCbCr422
135262. DP_COLOR_FORMAT_YCbCr444
135263. DP_COLOR_RAMP
135264. DP_COLOR_RANGE_16_235
135265. DP_COLOR_SQUARE
135266. DP_COMBINE_FOUR_PIXEL
135267. DP_COMBINE_ONE_PIXEL
135268. DP_COMBINE_PIXEL_NUM
135269. DP_COMBINE_TWO_PIXEL
135270. DP_COMPONENT_DEPTH
135271. DP_COMPONENT_DEPTH_10BPC
135272. DP_COMPONENT_DEPTH_12BPC
135273. DP_COMPONENT_DEPTH_16BPC
135274. DP_COMPONENT_DEPTH_16BPC_RESERVED
135275. DP_COMPONENT_DEPTH_6BPC
135276. DP_COMPONENT_DEPTH_8BPC
135277. DP_COMPONENT_DEPTH_RESERVED
135278. DP_COMPONENT_PIXEL_DEPTH_10BPC
135279. DP_COMPONENT_PIXEL_DEPTH_12BPC
135280. DP_COMPONENT_PIXEL_DEPTH_16BPC
135281. DP_COMPONENT_PIXEL_DEPTH_6BPC
135282. DP_COMPONENT_PIXEL_DEPTH_8BPC
135283. DP_COM_CONF
135284. DP_COM_CONF_CSC_DEF_BG
135285. DP_COM_CONF_CSC_DEF_BOTH
135286. DP_COM_CONF_CSC_DEF_FG
135287. DP_COM_CONF_CSC_DEF_MASK
135288. DP_COM_CONF_CSC_DEF_OFFSET
135289. DP_COM_CONF_FG_EN
135290. DP_COM_CONF_GWAM
135291. DP_COM_CONF_GWCKE
135292. DP_COM_CONF_GWSEL
135293. DP_CONFIG__DP_UDI_LANES_MASK
135294. DP_CONFIG__DP_UDI_LANES__SHIFT
135295. DP_CONF_CURRENTLY
135296. DP_CONF_DFP_D
135297. DP_CONF_DUAL_D
135298. DP_CONF_GET_PIN_ASSIGN
135299. DP_CONF_PIN_ASSIGNEMENT_MASK
135300. DP_CONF_PIN_ASSIGNEMENT_SHIFT
135301. DP_CONF_SET_PIN_ASSIGN
135302. DP_CONF_SIGNALING_DP
135303. DP_CONF_SIGNALING_GEN_2
135304. DP_CONF_UFP_D
135305. DP_CONF_UFP_U_AS_DFP_D
135306. DP_CONF_UFP_U_AS_UFP_D
135307. DP_CONF_USB
135308. DP_CONNECTION
135309. DP_CONNECTION_STATUS_NOTIFY
135310. DP_CONT
135311. DP_CONVERSION_TEMP
135312. DP_CP_IRQ
135313. DP_CRC_VALID_BIT
135314. DP_CSC_0
135315. DP_CSC_1
135316. DP_CSC_A_0
135317. DP_CSC_A_1
135318. DP_CSC_A_2
135319. DP_CSC_A_3
135320. DP_C_HOTPLUG
135321. DP_D
135322. DP_DATA
135323. DP_DATA0
135324. DP_DATA1
135325. DP_DATARATE
135326. DP_DATARATE_MASK
135327. DP_DATATYPE
135328. DP_DATA_0
135329. DP_DEBUG
135330. DP_DECOMPRESSION_EN
135331. DP_DETAILED_CAP_INFO_AVAILABLE
135332. DP_DETECTED
135333. DP_DEVICE_SERVICE_IRQ_VECTOR
135334. DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0
135335. DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1
135336. DP_DISCARD
135337. DP_DOWNSPREAD_CTRL
135338. DP_DOWNSTREAMPORT_PRESENT
135339. DP_DOWNSTREAM_PORT_0
135340. DP_DOWNSTREAM_PORT_STATUS_CHANGED
135341. DP_DOWN_REP_MSG_RDY
135342. DP_DOWN_STREAM_PORT_COUNT
135343. DP_DP13_DPCD_REV
135344. DP_DP13_MAX_LINK_RATE
135345. DP_DPCD_DISPLAY_CONTROL_CAPABLE
135346. DP_DPCD_QUIRK_CONSTANT_N
135347. DP_DPCD_QUIRK_NO_PSR
135348. DP_DPCD_QUIRK_NO_SINK_COUNT
135349. DP_DPCD_REV
135350. DP_DPCD_REV_10
135351. DP_DPCD_REV_11
135352. DP_DPCD_REV_12
135353. DP_DPCD_REV_13
135354. DP_DPCD_REV_14
135355. DP_DPCD_SIZE
135356. DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK
135357. DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT
135358. DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK
135359. DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT
135360. DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK
135361. DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT
135362. DP_DPHY_8B10B_EXT_DISP
135363. DP_DPHY_8B10B_EXT_DISP_ONE
135364. DP_DPHY_8B10B_EXT_DISP_ZERO
135365. DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK
135366. DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT
135367. DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK
135368. DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK
135369. DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT
135370. DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT
135371. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK
135372. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT
135373. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK
135374. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT
135375. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK
135376. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT
135377. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK
135378. DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT
135379. DP_DPHY_CNTL__DPHY_BYPASS_MASK
135380. DP_DPHY_CNTL__DPHY_BYPASS__SHIFT
135381. DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK
135382. DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT
135383. DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK
135384. DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT
135385. DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK
135386. DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT
135387. DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK
135388. DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT
135389. DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK
135390. DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT
135391. DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK
135392. DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT
135393. DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK
135394. DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT
135395. DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK
135396. DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT
135397. DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK
135398. DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT
135399. DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK
135400. DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT
135401. DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK
135402. DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT
135403. DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK
135404. DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT
135405. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK
135406. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT
135407. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK
135408. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT
135409. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK
135410. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT
135411. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK
135412. DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT
135413. DP_DPHY_FAST_TRAINING_COMPLETE_ACK
135414. DP_DPHY_FAST_TRAINING_COMPLETE_ACKED
135415. DP_DPHY_FAST_TRAINING_COMPLETE_MASK
135416. DP_DPHY_FAST_TRAINING_COMPLETE_MASKED
135417. DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED
135418. DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED
135419. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK
135420. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT
135421. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK
135422. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT
135423. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK
135424. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT
135425. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK
135426. DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT
135427. DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED
135428. DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN
135429. DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED
135430. DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK
135431. DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT
135432. DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK
135433. DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT
135434. DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK
135435. DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT
135436. DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK
135437. DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT
135438. DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK
135439. DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT
135440. DP_DPHY_HBR2_PASS_THROUGH
135441. DP_DPHY_HBR2_PATTERN_1
135442. DP_DPHY_HBR2_PATTERN_2_NEG
135443. DP_DPHY_HBR2_PATTERN_2_POS
135444. DP_DPHY_HBR2_PATTERN_3
135445. DP_DPHY_HBR2_PATTERN_CONTROL_MODE
135446. DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK
135447. DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT
135448. DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK
135449. DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT
135450. DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK
135451. DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT
135452. DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK
135453. DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT
135454. DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK
135455. DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT
135456. DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK
135457. DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT
135458. DP_DPHY_SYM0__DPHY_SYM1_MASK
135459. DP_DPHY_SYM0__DPHY_SYM1__SHIFT
135460. DP_DPHY_SYM0__DPHY_SYM2_MASK
135461. DP_DPHY_SYM0__DPHY_SYM2__SHIFT
135462. DP_DPHY_SYM0__DPHY_SYM3_MASK
135463. DP_DPHY_SYM0__DPHY_SYM3__SHIFT
135464. DP_DPHY_SYM1__DPHY_SYM4_MASK
135465. DP_DPHY_SYM1__DPHY_SYM4__SHIFT
135466. DP_DPHY_SYM1__DPHY_SYM5_MASK
135467. DP_DPHY_SYM1__DPHY_SYM5__SHIFT
135468. DP_DPHY_SYM1__DPHY_SYM6_MASK
135469. DP_DPHY_SYM1__DPHY_SYM6__SHIFT
135470. DP_DPHY_SYM2__DPHY_SYM7_MASK
135471. DP_DPHY_SYM2__DPHY_SYM7__SHIFT
135472. DP_DPHY_SYM2__DPHY_SYM8_MASK
135473. DP_DPHY_SYM2__DPHY_SYM8__SHIFT
135474. DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK
135475. DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT
135476. DP_DPK_NUM
135477. DP_DPK_VALUE_NUM
135478. DP_DPRX_ESI_LEN
135479. DP_DPRX_FEATURE_ENUMERATION_LIST
135480. DP_DROP_NET_CONF
135481. DP_DSC_10_BPC
135482. DP_DSC_10_PER_DP_DSC_SINK
135483. DP_DSC_12_BPC
135484. DP_DSC_12_PER_DP_DSC_SINK
135485. DP_DSC_16_PER_DP_DSC_SINK
135486. DP_DSC_1_PER_DP_DSC_SINK
135487. DP_DSC_20_PER_DP_DSC_SINK
135488. DP_DSC_24_PER_DP_DSC_SINK
135489. DP_DSC_2_PER_DP_DSC_SINK
135490. DP_DSC_444_SIMPLE_422
135491. DP_DSC_4_PER_DP_DSC_SINK
135492. DP_DSC_6_PER_DP_DSC_SINK
135493. DP_DSC_8_BPC
135494. DP_DSC_8_PER_DP_DSC_SINK
135495. DP_DSC_BITS_PER_PIXEL_1
135496. DP_DSC_BITS_PER_PIXEL_1_16
135497. DP_DSC_BITS_PER_PIXEL_1_2
135498. DP_DSC_BITS_PER_PIXEL_1_4
135499. DP_DSC_BITS_PER_PIXEL_1_8
135500. DP_DSC_BITS_PER_PIXEL_INC
135501. DP_DSC_BLK_PREDICTION_IS_SUPPORTED
135502. DP_DSC_BLK_PREDICTION_SUPPORT
135503. DP_DSC_BRANCH_MAX_LINE_WIDTH
135504. DP_DSC_BRANCH_OVERALL_THROUGHPUT_0
135505. DP_DSC_BRANCH_OVERALL_THROUGHPUT_1
135506. DP_DSC_DECOMPRESSION_IS_SUPPORTED
135507. DP_DSC_DEC_COLOR_DEPTH_CAP
135508. DP_DSC_DEC_COLOR_FORMAT_CAP
135509. DP_DSC_DISABLE
135510. DP_DSC_ENABLE
135511. DP_DSC_FEC_OVERHEAD_FACTOR
135512. DP_DSC_LINE_BUF_BIT_DEPTH
135513. DP_DSC_LINE_BUF_BIT_DEPTH_10
135514. DP_DSC_LINE_BUF_BIT_DEPTH_11
135515. DP_DSC_LINE_BUF_BIT_DEPTH_12
135516. DP_DSC_LINE_BUF_BIT_DEPTH_13
135517. DP_DSC_LINE_BUF_BIT_DEPTH_14
135518. DP_DSC_LINE_BUF_BIT_DEPTH_15
135519. DP_DSC_LINE_BUF_BIT_DEPTH_16
135520. DP_DSC_LINE_BUF_BIT_DEPTH_8
135521. DP_DSC_LINE_BUF_BIT_DEPTH_9
135522. DP_DSC_LINE_BUF_BIT_DEPTH_MASK
135523. DP_DSC_MAJOR_MASK
135524. DP_DSC_MAJOR_SHIFT
135525. DP_DSC_MAX_BITS_PER_PIXEL_HI
135526. DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK
135527. DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT
135528. DP_DSC_MAX_BITS_PER_PIXEL_LOW
135529. DP_DSC_MAX_ENC_THROUGHPUT_0
135530. DP_DSC_MAX_ENC_THROUGHPUT_1
135531. DP_DSC_MAX_SLICE_WIDTH
135532. DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER
135533. DP_DSC_MAX_SUPPORTED_BPC
135534. DP_DSC_MINOR_MASK
135535. DP_DSC_MINOR_SHIFT
135536. DP_DSC_MIN_SLICE_WIDTH_VALUE
135537. DP_DSC_MIN_SUPPORTED_BPC
135538. DP_DSC_MODE
135539. DP_DSC_NATIVE_422_420
135540. DP_DSC_PEAK_PIXEL_RATE
135541. DP_DSC_PEAK_THROUGHPUT
135542. DP_DSC_RC_BUF_BLK_SIZE
135543. DP_DSC_RC_BUF_BLK_SIZE_1
135544. DP_DSC_RC_BUF_BLK_SIZE_16
135545. DP_DSC_RC_BUF_BLK_SIZE_4
135546. DP_DSC_RC_BUF_BLK_SIZE_64
135547. DP_DSC_RC_BUF_SIZE
135548. DP_DSC_RECEIVER_CAP_SIZE
135549. DP_DSC_REV
135550. DP_DSC_RGB
135551. DP_DSC_SLICE_CAP_1
135552. DP_DSC_SLICE_CAP_2
135553. DP_DSC_SLICE_WIDTH_MULTIPLIER
135554. DP_DSC_SUPPORT
135555. DP_DSC_THROUGHPUT_MODE_0_1000
135556. DP_DSC_THROUGHPUT_MODE_0_170
135557. DP_DSC_THROUGHPUT_MODE_0_340
135558. DP_DSC_THROUGHPUT_MODE_0_400
135559. DP_DSC_THROUGHPUT_MODE_0_450
135560. DP_DSC_THROUGHPUT_MODE_0_500
135561. DP_DSC_THROUGHPUT_MODE_0_550
135562. DP_DSC_THROUGHPUT_MODE_0_600
135563. DP_DSC_THROUGHPUT_MODE_0_650
135564. DP_DSC_THROUGHPUT_MODE_0_700
135565. DP_DSC_THROUGHPUT_MODE_0_750
135566. DP_DSC_THROUGHPUT_MODE_0_800
135567. DP_DSC_THROUGHPUT_MODE_0_850
135568. DP_DSC_THROUGHPUT_MODE_0_900
135569. DP_DSC_THROUGHPUT_MODE_0_950
135570. DP_DSC_THROUGHPUT_MODE_0_MASK
135571. DP_DSC_THROUGHPUT_MODE_0_SHIFT
135572. DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED
135573. DP_DSC_THROUGHPUT_MODE_1_1000
135574. DP_DSC_THROUGHPUT_MODE_1_170
135575. DP_DSC_THROUGHPUT_MODE_1_340
135576. DP_DSC_THROUGHPUT_MODE_1_400
135577. DP_DSC_THROUGHPUT_MODE_1_450
135578. DP_DSC_THROUGHPUT_MODE_1_500
135579. DP_DSC_THROUGHPUT_MODE_1_550
135580. DP_DSC_THROUGHPUT_MODE_1_600
135581. DP_DSC_THROUGHPUT_MODE_1_650
135582. DP_DSC_THROUGHPUT_MODE_1_700
135583. DP_DSC_THROUGHPUT_MODE_1_750
135584. DP_DSC_THROUGHPUT_MODE_1_800
135585. DP_DSC_THROUGHPUT_MODE_1_850
135586. DP_DSC_THROUGHPUT_MODE_1_900
135587. DP_DSC_THROUGHPUT_MODE_1_950
135588. DP_DSC_THROUGHPUT_MODE_1_MASK
135589. DP_DSC_THROUGHPUT_MODE_1_SHIFT
135590. DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED
135591. DP_DSC_YCbCr420_Native
135592. DP_DSC_YCbCr422_Native
135593. DP_DSC_YCbCr422_Simple
135594. DP_DSC_YCbCr444
135595. DP_DS_10BPC
135596. DP_DS_12BPC
135597. DP_DS_16BPC
135598. DP_DS_8BPC
135599. DP_DS_MAX_BPC_MASK
135600. DP_DS_PORT_HPD
135601. DP_DS_PORT_TYPE_DP
135602. DP_DS_PORT_TYPE_DP_DUALMODE
135603. DP_DS_PORT_TYPE_DVI
135604. DP_DS_PORT_TYPE_HDMI
135605. DP_DS_PORT_TYPE_MASK
135606. DP_DS_PORT_TYPE_NON_EDID
135607. DP_DS_PORT_TYPE_VGA
135608. DP_DS_PORT_TYPE_WIRELESS
135609. DP_DTO0_MODULO__DP_DTO0_MODULO_MASK
135610. DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT
135611. DP_DTO0_PHASE__DP_DTO0_PHASE_MASK
135612. DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT
135613. DP_DTO1_MODULO__DP_DTO1_MODULO_MASK
135614. DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT
135615. DP_DTO1_PHASE__DP_DTO1_PHASE_MASK
135616. DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT
135617. DP_DTO2_MODULO__DP_DTO2_MODULO_MASK
135618. DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT
135619. DP_DTO2_PHASE__DP_DTO2_PHASE_MASK
135620. DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT
135621. DP_DTO3_MODULO__DP_DTO3_MODULO_MASK
135622. DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT
135623. DP_DTO3_PHASE__DP_DTO3_PHASE_MASK
135624. DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT
135625. DP_DTO4_MODULO__DP_DTO4_MODULO_MASK
135626. DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT
135627. DP_DTO4_PHASE__DP_DTO4_PHASE_MASK
135628. DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT
135629. DP_DTO5_MODULO__DP_DTO5_MODULO_MASK
135630. DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT
135631. DP_DTO5_PHASE__DP_DTO5_PHASE_MASK
135632. DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT
135633. DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK
135634. DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT
135635. DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK
135636. DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT
135637. DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK
135638. DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT
135639. DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK
135640. DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT
135641. DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK
135642. DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT
135643. DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK
135644. DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT
135645. DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK
135646. DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT
135647. DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK
135648. DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT
135649. DP_DTO_DESPREAD_DISABLE
135650. DP_DTO_DESPREAD_ENABLE
135651. DP_DTO_DS_DISABLE
135652. DP_DUAL_DEVICE_ID
135653. DP_DUAL_DEVICE_ID_LEN
135654. DP_DUAL_IEEE_OUI_LEN
135655. DP_DUAL_MODE_ADAPTOR_ID
135656. DP_DUAL_MODE_CEC_ENABLE
135657. DP_DUAL_MODE_FIRMWARE_MAJOR_REV
135658. DP_DUAL_MODE_FIRMWARE_MINOR_REV
135659. DP_DUAL_MODE_HARDWARE_REV
135660. DP_DUAL_MODE_HDMI_ID
135661. DP_DUAL_MODE_HDMI_ID_LEN
135662. DP_DUAL_MODE_HDMI_PIN_CTRL
135663. DP_DUAL_MODE_I2C_SPEED_CAP
135664. DP_DUAL_MODE_I2C_SPEED_CTRL
135665. DP_DUAL_MODE_IEEE_OUI
135666. DP_DUAL_MODE_LSPCON_CURRENT_MODE
135667. DP_DUAL_MODE_LSPCON_MODE_CHANGE
135668. DP_DUAL_MODE_LSPCON_MODE_PCON
135669. DP_DUAL_MODE_MAX_TMDS_CLOCK
135670. DP_DUAL_MODE_REV_MASK
135671. DP_DUAL_MODE_REV_TYPE2
135672. DP_DUAL_MODE_SLAVE_ADDRESS
135673. DP_DUAL_MODE_TMDS_DISABLE
135674. DP_DUAL_MODE_TMDS_OEN
135675. DP_DUAL_MODE_TYPE_HAS_DPCD
135676. DP_DUAL_MODE_TYPE_MASK
135677. DP_DUAL_MODE_TYPE_TYPE2
135678. DP_DWN_STRM_PORT_PRESENT
135679. DP_DWN_STRM_PORT_TYPE_ANALOG
135680. DP_DWN_STRM_PORT_TYPE_DP
135681. DP_DWN_STRM_PORT_TYPE_MASK
135682. DP_DWN_STRM_PORT_TYPE_OTHER
135683. DP_DWN_STRM_PORT_TYPE_TMDS
135684. DP_DYN_CEA_RANGE
135685. DP_DYN_RANGE
135686. DP_DYN_VESA_RANGE
135687. DP_D_HOTPLUG
135688. DP_EBIAS
135689. DP_EDP_11
135690. DP_EDP_12
135691. DP_EDP_13
135692. DP_EDP_14
135693. DP_EDP_14a
135694. DP_EDP_14b
135695. DP_EDP_BACKLIGHT_ADJUSTMENT_CAP
135696. DP_EDP_BACKLIGHT_AUX_ENABLE_CAP
135697. DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP
135698. DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP
135699. DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT
135700. DP_EDP_BACKLIGHT_BRIGHTNESS_LSB
135701. DP_EDP_BACKLIGHT_BRIGHTNESS_MSB
135702. DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP
135703. DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD
135704. DP_EDP_BACKLIGHT_CONTROL_MODE_MASK
135705. DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET
135706. DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT
135707. DP_EDP_BACKLIGHT_CONTROL_MODE_PWM
135708. DP_EDP_BACKLIGHT_CONTROL_STATUS
135709. DP_EDP_BACKLIGHT_ENABLE
135710. DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP
135711. DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE
135712. DP_EDP_BACKLIGHT_FREQ_BASE_KHZ
135713. DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
135714. DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID
135715. DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB
135716. DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB
135717. DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID
135718. DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB
135719. DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP
135720. DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE
135721. DP_EDP_BACKLIGHT_FREQ_SET
135722. DP_EDP_BACKLIGHT_MODE_SET_REGISTER
135723. DP_EDP_BACKLIGHT_PIN_ENABLE_CAP
135724. DP_EDP_BLACK_VIDEO_ENABLE
135725. DP_EDP_COLOR_ENGINE_CAP
135726. DP_EDP_COLOR_ENGINE_ENABLE
135727. DP_EDP_CONFIGURATION_CAP
135728. DP_EDP_CONFIGURATION_SET
135729. DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
135730. DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
135731. DP_EDP_DISPLAY_CONTROL_REGISTER
135732. DP_EDP_DPCD_REV
135733. DP_EDP_DYNAMIC_BACKLIGHT_CAP
135734. DP_EDP_DYNAMIC_BACKLIGHT_ENABLE
135735. DP_EDP_FRC_ENABLE
135736. DP_EDP_FRC_ENABLE_CAP
135737. DP_EDP_GENERAL_CAP_1
135738. DP_EDP_GENERAL_CAP_2
135739. DP_EDP_GENERAL_CAP_3
135740. DP_EDP_OVERDRIVE_ENGINE_ENABLED
135741. DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP
135742. DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP
135743. DP_EDP_PWMGEN_BIT_COUNT
135744. DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX
135745. DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN
135746. DP_EDP_PWMGEN_BIT_COUNT_MASK
135747. DP_EDP_REGIONAL_BACKLIGHT_0
135748. DP_EDP_REGIONAL_BACKLIGHT_BASE
135749. DP_EDP_REGIONAL_BACKLIGHT_ENABLE
135750. DP_EDP_SET_POWER_CAP
135751. DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP
135752. DP_EDP_UPDATE_REGION_BRIGHTNESS
135753. DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP
135754. DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE
135755. DP_EDP_X_REGION_CAP_MASK
135756. DP_EDP_X_REGION_CAP_SHIFT
135757. DP_EDP_Y_REGION_CAP_MASK
135758. DP_EDP_Y_REGION_CAP_SHIFT
135759. DP_EMAX
135760. DP_EMBEDDED_PANEL
135761. DP_EMBEDDED_PANEL_MODE
135762. DP_EMIN
135763. DP_EN
135764. DP_ENCODER_SERVICE_PARAMETERS
135765. DP_ENCODER_SERVICE_PARAMETERS_V2
135766. DP_ENCODER_SERVICE_PS_ALLOCATION
135767. DP_ENCODER_SERVICE_PS_ALLOCATION_V2
135768. DP_ENHANCED_FRAME_CAP
135769. DP_ENHANCED_FRAMING
135770. DP_ENUM_PATH_RESOURCES
135771. DP_ERR
135772. DP_EXP_BG
135773. DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT
135774. DP_EXTERNAL_PANEL
135775. DP_FAUX_CAP
135776. DP_FAUX_CAP_1
135777. DP_FBITS
135778. DP_FEC_BIT_ERROR_COUNT
135779. DP_FEC_BIT_ERROR_COUNT_CAP
135780. DP_FEC_CAPABILITY
135781. DP_FEC_CAPABLE
135782. DP_FEC_CONFIGURATION
135783. DP_FEC_CORR_BLK_ERROR_COUNT
135784. DP_FEC_CORR_BLK_ERROR_COUNT_CAP
135785. DP_FEC_DECODE_DIS_DETECTED
135786. DP_FEC_DECODE_EN_DETECTED
135787. DP_FEC_ERROR_COUNT_LSB
135788. DP_FEC_ERROR_COUNT_MASK
135789. DP_FEC_ERROR_COUNT_MSB
135790. DP_FEC_ERR_COUNT_DIS
135791. DP_FEC_ERR_COUNT_SEL_MASK
135792. DP_FEC_ERR_COUNT_VALID
135793. DP_FEC_LANE_0_SELECT
135794. DP_FEC_LANE_1_SELECT
135795. DP_FEC_LANE_2_SELECT
135796. DP_FEC_LANE_3_SELECT
135797. DP_FEC_LANE_SELECT_MASK
135798. DP_FEC_READY
135799. DP_FEC_STATUS
135800. DP_FEC_UNCORR_BLK_ERROR_COUNT
135801. DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP
135802. DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK
135803. DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT
135804. DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK
135805. DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT
135806. DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK
135807. DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT
135808. DP_FG_POS
135809. DP_FIRST_SCAN_LINE_SU_REGION
135810. DP_FLUSH
135811. DP_FOG_CLR
135812. DP_FORCE_LOAD_SENSE_CAP
135813. DP_FORMAT_CONVERSION
135814. DP_FRAMER_GLOBAL_CONFIG
135815. DP_FRAMER_PXL_REPR
135816. DP_FRAMER_SP
135817. DP_FRAMER_SP_HSP
135818. DP_FRAMER_SP_INTERLACE_EN
135819. DP_FRAMER_SP_VSP
135820. DP_FRAMER_TU
135821. DP_FRAMING_CHANGE_CAP
135822. DP_FRAMING_CHANGE_ENABLE
135823. DP_FREEZE_IO
135824. DP_FRGD_BKGD_CLR
135825. DP_FRGD_CLR
135826. DP_FRGD_CLR_MIX
135827. DP_FRONT_BACK_PORCH
135828. DP_FUA
135829. DP_GET_MSG_TRANSACTION_VERSION
135830. DP_GET_SINK_COUNT
135831. DP_GRAPH_WIND_CTRL
135832. DP_GTC_CAP
135833. DP_GUID
135834. DP_GUI_MASTER_CNTL
135835. DP_GUI_MASTER_CNTL_C
135836. DP_HARDBARRIER
135837. DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK
135838. DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT
135839. DP_HDCP_2_2_AKE_INIT_OFFSET
135840. DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
135841. DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
135842. DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
135843. DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET
135844. DP_HDCP_2_2_AKE_STORED_KM_OFFSET
135845. DP_HDCP_2_2_LC_INIT_OFFSET
135846. DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
135847. DP_HDCP_2_2_REG_CERT_RX_OFFSET
135848. DP_HDCP_2_2_REG_DBG_OFFSET
135849. DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
135850. DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
135851. DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
135852. DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
135853. DP_HDCP_2_2_REG_HPRIME_OFFSET
135854. DP_HDCP_2_2_REG_K_OFFSET
135855. DP_HDCP_2_2_REG_LPRIME_OFFSET
135856. DP_HDCP_2_2_REG_MPRIME_OFFSET
135857. DP_HDCP_2_2_REG_M_OFFSET
135858. DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET
135859. DP_HDCP_2_2_REG_RIV_OFFSET
135860. DP_HDCP_2_2_REG_RN_OFFSET
135861. DP_HDCP_2_2_REG_RRX_OFFSET
135862. DP_HDCP_2_2_REG_RTX_OFFSET
135863. DP_HDCP_2_2_REG_RXINFO_OFFSET
135864. DP_HDCP_2_2_REG_RXSTATUS_OFFSET
135865. DP_HDCP_2_2_REG_RX_CAPS_OFFSET
135866. DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
135867. DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET
135868. DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET
135869. DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET
135870. DP_HDCP_2_2_REG_TXCAPS_OFFSET
135871. DP_HDCP_2_2_REG_VPRIME_OFFSET
135872. DP_HDCP_2_2_REG_V_OFFSET
135873. DP_HDCP_2_2_REP_SEND_ACK_OFFSET
135874. DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
135875. DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
135876. DP_HDCP_2_2_REP_STREAM_READY_OFFSET
135877. DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
135878. DP_HDMI_DONGLE_ADDRESS
135879. DP_HDMI_DONGLE_SIGNATURE_EOT
135880. DP_HEADER
135881. DP_HIDDEN_BIT
135882. DP_HORIZONTAL
135883. DP_HOST_TRIPLE_EN
135884. DP_I2C_AUX_DDC_READ_END_TBL_ADDR
135885. DP_I2C_AUX_DDC_READ_START_TBL_ADDR
135886. DP_I2C_AUX_DDC_READ_TBL_ADDR
135887. DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR
135888. DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR
135889. DP_I2C_AUX_DDC_WRITE_TBL_ADDR
135890. DP_I2C_SPEED_100K
135891. DP_I2C_SPEED_10K
135892. DP_I2C_SPEED_1K
135893. DP_I2C_SPEED_1M
135894. DP_I2C_SPEED_400K
135895. DP_I2C_SPEED_5K
135896. DP_I2C_SPEED_CAP
135897. DP_I2C_SPEED_CONTROL_STATUS
135898. DP_INC_BG
135899. DP_INFO
135900. DP_INFO_FRAME_WORD1
135901. DP_INNER
135902. DP_INTERLANE_ALIGN_DONE
135903. DP_INTERRUPT_MASK
135904. DP_INTERRUPT_SOURCE
135905. DP_IRQ_HPD_ENABLE
135906. DP_IRQ_TYPE_HP_CABLE_IN
135907. DP_IRQ_TYPE_HP_CABLE_OUT
135908. DP_IRQ_TYPE_HP_CHANGE
135909. DP_IRQ_TYPE_UNKNOWN
135910. DP_LANE02_MAX_POST_CURSOR2_REACHED
135911. DP_LANE02_POST_CURSOR2_SET_MASK
135912. DP_LANE0_1_STATUS
135913. DP_LANE0_1_STATUS_ESI
135914. DP_LANE13_MAX_POST_CURSOR2_REACHED
135915. DP_LANE13_POST_CURSOR2_SET_MASK
135916. DP_LANE2_3_STATUS
135917. DP_LANE2_3_STATUS_ESI
135918. DP_LANE_ALIGN_STATUS_UPDATED
135919. DP_LANE_ALIGN_STATUS_UPDATED_ESI
135920. DP_LANE_ASSIGNMENT
135921. DP_LANE_ASSIGNMENT_MASK
135922. DP_LANE_ASSIGNMENT_SHIFT
135923. DP_LANE_CHANNEL_EQ_DONE
135924. DP_LANE_COUNT_ENHANCED_FRAME_EN
135925. DP_LANE_COUNT_MASK
135926. DP_LANE_COUNT_SET
135927. DP_LANE_CR_DONE
135928. DP_LANE_SET__0DB_0_4V
135929. DP_LANE_SET__0DB_0_6V
135930. DP_LANE_SET__0DB_0_8V
135931. DP_LANE_SET__0DB_1_2V
135932. DP_LANE_SET__3_5DB_0_4V
135933. DP_LANE_SET__3_5DB_0_6V
135934. DP_LANE_SET__3_5DB_0_8V
135935. DP_LANE_SET__6DB_0_4V
135936. DP_LANE_SET__6DB_0_6V
135937. DP_LANE_SET__9_5DB_0_4V
135938. DP_LANE_SYMBOL_LOCKED
135939. DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK
135940. DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT
135941. DP_LAST_RECEIVED_PSR_SDP
135942. DP_LAST_SCAN_LINE_SU_REGION
135943. DP_LEVEL
135944. DP_LINK_ADDRESS
135945. DP_LINK_BW_1_62
135946. DP_LINK_BW_2_7
135947. DP_LINK_BW_5_4
135948. DP_LINK_BW_8_1
135949. DP_LINK_BW_SET
135950. DP_LINK_CAP_ENHANCED_FRAMING
135951. DP_LINK_CHECK_TIMEOUT
135952. DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK
135953. DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT
135954. DP_LINK_CNTL__DP_LINK_STATUS_MASK
135955. DP_LINK_CNTL__DP_LINK_STATUS__SHIFT
135956. DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK
135957. DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT
135958. DP_LINK_CONFIGURATION_SIZE
135959. DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK
135960. DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT
135961. DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK
135962. DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT
135963. DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK
135964. DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT
135965. DP_LINK_QUAL_LANE0_SET
135966. DP_LINK_QUAL_LANE1_SET
135967. DP_LINK_QUAL_LANE2_SET
135968. DP_LINK_QUAL_LANE3_SET
135969. DP_LINK_QUAL_PATTERN_11_D10_2
135970. DP_LINK_QUAL_PATTERN_11_DISABLE
135971. DP_LINK_QUAL_PATTERN_11_ERROR_RATE
135972. DP_LINK_QUAL_PATTERN_11_MASK
135973. DP_LINK_QUAL_PATTERN_11_PRBS7
135974. DP_LINK_QUAL_PATTERN_80BIT_CUSTOM
135975. DP_LINK_QUAL_PATTERN_D10_2
135976. DP_LINK_QUAL_PATTERN_DISABLE
135977. DP_LINK_QUAL_PATTERN_ERROR_RATE
135978. DP_LINK_QUAL_PATTERN_HBR2_EYE
135979. DP_LINK_QUAL_PATTERN_MASK
135980. DP_LINK_QUAL_PATTERN_PRBS7
135981. DP_LINK_RATE_162
135982. DP_LINK_RATE_27
135983. DP_LINK_RATE_SET
135984. DP_LINK_RATE_SET_MASK
135985. DP_LINK_RATE_SET_SHIFT
135986. DP_LINK_RATE_TABLE
135987. DP_LINK_SCRAMBLING_DISABLE
135988. DP_LINK_SERVICE_IRQ_VECTOR_ESI0
135989. DP_LINK_STATUS_SIZE
135990. DP_LINK_STATUS_UPDATED
135991. DP_LINK_TRAINING_ALREADY_COMPLETE
135992. DP_LINK_TRAINING_COMPLETE
135993. DP_LINK_TRAINING_NOT_COMPLETE
135994. DP_LINK_TRAINING_SWITCH_MODE
135995. DP_LINK_TRAINING_SWITCH_TO_IDLE
135996. DP_LINK_TRAINING_SWITCH_TO_VIDEO
135997. DP_LINK_TRAIN_MASK
135998. DP_LINK_TRAIN_MASK_CPT
135999. DP_LINK_TRAIN_OFF
136000. DP_LINK_TRAIN_OFF_CPT
136001. DP_LINK_TRAIN_PAT_1
136002. DP_LINK_TRAIN_PAT_1_CPT
136003. DP_LINK_TRAIN_PAT_2
136004. DP_LINK_TRAIN_PAT_2_CPT
136005. DP_LINK_TRAIN_PAT_IDLE
136006. DP_LINK_TRAIN_PAT_IDLE_CPT
136007. DP_LINK_TRAIN_SHIFT
136008. DP_LINK_TRAIN_SHIFT_CPT
136009. DP_LOCAL_EDID_PRESENT
136010. DP_LOCK_ACQUISITION_REQUEST
136011. DP_MAIN_LINK_CHANNEL_CODING
136012. DP_MAIN_LINK_CHANNEL_CODING_SET
136013. DP_MASK
136014. DP_MAX_BANDS
136015. DP_MAX_DOWNSPREAD
136016. DP_MAX_DOWNSPREAD_0_5
136017. DP_MAX_DOWNSTREAM_PORTS
136018. DP_MAX_LANE_COUNT
136019. DP_MAX_LANE_COUNT_MASK
136020. DP_MAX_LINK_RATE
136021. DP_MAX_PAYLOAD
136022. DP_MAX_PORTS
136023. DP_MAX_RESYNC_FRAME_COUNT_MASK
136024. DP_MAX_RESYNC_FRAME_COUNT_SHIFT
136025. DP_MAX_SUPPORTED_RATES
136026. DP_MAY_SET_IN_SYNC
136027. DP_MBIT
136028. DP_MBITS
136029. DP_MCCS_IRQ
136030. DP_MIE_CLKCON
136031. DP_MIE_CLK_DISABLE
136032. DP_MIE_CLK_DP_ENABLE
136033. DP_MIE_CLK_MIE_ENABLE
136034. DP_MIX
136035. DP_ML_PHY_SEQ_IMMEDIATE
136036. DP_ML_PHY_SEQ_LINE_NUM
136037. DP_ML_PHY_SEQ_MODE
136038. DP_MODE
136039. DP_MODE_A0
136040. DP_MODE_A2
136041. DP_MODE_CTL
136042. DP_MODE_ENTER_A0
136043. DP_MODE_ENTER_A2
136044. DP_MODULE
136045. DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK
136046. DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT
136047. DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK
136048. DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT
136049. DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK
136050. DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT
136051. DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK
136052. DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT
136053. DP_MSA_MISC0_OVERRIDE_ENABLE
136054. DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE
136055. DP_MSA_MISC__DP_MSA_MISC1_MASK
136056. DP_MSA_MISC__DP_MSA_MISC1__SHIFT
136057. DP_MSA_MISC__DP_MSA_MISC2_MASK
136058. DP_MSA_MISC__DP_MSA_MISC2__SHIFT
136059. DP_MSA_MISC__DP_MSA_MISC3_MASK
136060. DP_MSA_MISC__DP_MSA_MISC3__SHIFT
136061. DP_MSA_MISC__DP_MSA_MISC4_MASK
136062. DP_MSA_MISC__DP_MSA_MISC4__SHIFT
136063. DP_MSA_TIMING_PAR_IGNORED
136064. DP_MSA_TIMING_PAR_IGNORE_EN
136065. DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK
136066. DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT
136067. DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK
136068. DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT
136069. DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK
136070. DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT
136071. DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK
136072. DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT
136073. DP_MSA_V_TIMING_OVERRIDE_EN
136074. DP_MSE_BLANK_CODE
136075. DP_MSE_BLANK_CODE_SF_FILLED
136076. DP_MSE_BLANK_CODE_ZERO_FILLED
136077. DP_MSE_LINK_LINE
136078. DP_MSE_LINK_LINE_128_MTP_LONG
136079. DP_MSE_LINK_LINE_256_MTP_LONG
136080. DP_MSE_LINK_LINE_32_MTP_LONG
136081. DP_MSE_LINK_LINE_64_MTP_LONG
136082. DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK
136083. DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT
136084. DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK
136085. DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT
136086. DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK
136087. DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT
136088. DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK
136089. DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT
136090. DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK
136091. DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT
136092. DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK
136093. DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT
136094. DP_MSE_NOT_ZERO_FE_ENCODER
136095. DP_MSE_OUTPUT_DPDBG_DATA
136096. DP_MSE_OUTPUT_DPDBG_DATA_DIS
136097. DP_MSE_OUTPUT_DPDBG_DATA_EN
136098. DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK
136099. DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT
136100. DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK
136101. DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT
136102. DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK
136103. DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT
136104. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK
136105. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT
136106. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK
136107. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT
136108. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK
136109. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT
136110. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK
136111. DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT
136112. DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK
136113. DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT
136114. DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK
136115. DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT
136116. DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK
136117. DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT
136118. DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK
136119. DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT
136120. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK
136121. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT
136122. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK
136123. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT
136124. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK
136125. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT
136126. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK
136127. DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT
136128. DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK
136129. DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT
136130. DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK
136131. DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT
136132. DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK
136133. DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT
136134. DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK
136135. DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT
136136. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK
136137. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT
136138. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK
136139. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT
136140. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK
136141. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT
136142. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK
136143. DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT
136144. DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK
136145. DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT
136146. DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK
136147. DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT
136148. DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK
136149. DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT
136150. DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK
136151. DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT
136152. DP_MSE_SAT_UPDATE_ACT
136153. DP_MSE_SAT_UPDATE_NO_ACTION
136154. DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER
136155. DP_MSE_SAT_UPDATE_WITH_TRIGGER
136156. DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK
136157. DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT
136158. DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK
136159. DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT
136160. DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE
136161. DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE
136162. DP_MSE_TIMESTAMP_MODE
136163. DP_MSE_ZERO_ENCODER
136164. DP_MSE_ZERO_FE_ENCODER
136165. DP_MSO_FOUR_SSTLINK
136166. DP_MSO_NUM_OF_SST_LINKS
136167. DP_MSO_ONE_SSTLINK
136168. DP_MSO_TWO_SSTLINK
136169. DP_MSTM_CAP
136170. DP_MSTM_CTRL
136171. DP_MST_CAP
136172. DP_MST_EN
136173. DP_MST_LOGICAL_PORT_0
136174. DP_MST_PHYSICAL_PORT_0
136175. DP_MST_UPDATE_MAX_RETRY
136176. DP_MTPH_ACT_CONTROL
136177. DP_MTPH_ECF_CONTROL
136178. DP_MTPH_LVP_CONTROL
136179. DP_MTPH_STATUS
136180. DP_MTPH_SYMBOL_VALUES
136181. DP_NAK_ALLOCATE_FAIL
136182. DP_NAK_BAD_PARAM
136183. DP_NAK_CRC_FAILURE
136184. DP_NAK_DEFER
136185. DP_NAK_DPCD_FAIL
136186. DP_NAK_I2C_NAK
136187. DP_NAK_INVALID_READ
136188. DP_NAK_LINK_FAILURE
136189. DP_NAK_NO_RESOURCES
136190. DP_NAK_WRITE_FAILURE
136191. DP_NAME
136192. DP_NAUD_VAL
136193. DP_NONE
136194. DP_NORP
136195. DP_NOTICE
136196. DP_NO_AUX_HANDSHAKE_LINK_TRAINING
136197. DP_NO_TEST_PATTERN
136198. DP_NUMBER_OF_AUDIO_ENDPOINTS
136199. DP_NUM_LANES
136200. DP_NUM_LANES_MASK
136201. DP_OCTL
136202. DP_OP_ROP
136203. DP_OUI_SUPPORT
136204. DP_PANEL_MODE_DEFAULT
136205. DP_PANEL_MODE_DISABLE
136206. DP_PANEL_MODE_EDP
136207. DP_PANEL_MODE_ENABLE_LVLINK_MODE
136208. DP_PANEL_MODE_ENABLE_eDP_MODE
136209. DP_PANEL_MODE_EXTERNAL_DP_MODE
136210. DP_PANEL_MODE_INTERNAL_DP1_MODE
136211. DP_PANEL_MODE_INTERNAL_DP2_MODE
136212. DP_PANEL_MODE_SETUP_PARAMETERS_V5
136213. DP_PANEL_MODE_SPECIAL
136214. DP_PANEL_SELF_TEST_ENABLE
136215. DP_PATH_NUM
136216. DP_PAYLOAD_ACT_HANDLED
136217. DP_PAYLOAD_ALLOCATE_SET
136218. DP_PAYLOAD_ALLOCATE_START_TIME_SLOT
136219. DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT
136220. DP_PAYLOAD_DELETE_LOCAL
136221. DP_PAYLOAD_LOCAL
136222. DP_PAYLOAD_REMOTE
136223. DP_PAYLOAD_TABLE_SIZE
136224. DP_PAYLOAD_TABLE_UPDATED
136225. DP_PAYLOAD_TABLE_UPDATE_STATUS
136226. DP_PEER_DEVICE_DP_LEGACY_CONV
136227. DP_PEER_DEVICE_MST_BRANCHING
136228. DP_PEER_DEVICE_NONE
136229. DP_PEER_DEVICE_SOURCE_OR_SST
136230. DP_PEER_DEVICE_SST_SINK
136231. DP_PHY_CTRL
136232. DP_PHY_MODE_STATUS_COMPLETED
136233. DP_PHY_MODE_STATUS_NOT_SAFE
136234. DP_PHY_PD
136235. DP_PHY_RST
136236. DP_PIN_ASSIGN_A
136237. DP_PIN_ASSIGN_B
136238. DP_PIN_ASSIGN_C
136239. DP_PIN_ASSIGN_D
136240. DP_PIN_ASSIGN_DP_BR_MASK
136241. DP_PIN_ASSIGN_DP_ONLY_MASK
136242. DP_PIN_ASSIGN_E
136243. DP_PIN_ASSIGN_F
136244. DP_PIN_ASSIGN_GEN2_BR_MASK
136245. DP_PIN_ASSIGN_MULTI_FUNC_MASK
136246. DP_PIPEB_SELECT
136247. DP_PIPE_MASK
136248. DP_PIPE_SEL
136249. DP_PIPE_SEL_CHV
136250. DP_PIPE_SEL_IVB
136251. DP_PIPE_SEL_MASK
136252. DP_PIPE_SEL_MASK_CHV
136253. DP_PIPE_SEL_MASK_IVB
136254. DP_PIPE_SEL_SHIFT
136255. DP_PIPE_SEL_SHIFT_CHV
136256. DP_PIPE_SEL_SHIFT_IVB
136257. DP_PIXEL_ENCODING
136258. DP_PIXEL_ENCODING_RESERVED
136259. DP_PIXEL_ENCODING_RGB444
136260. DP_PIXEL_ENCODING_RGB_WIDE_GAMUT
136261. DP_PIXEL_ENCODING_TYPE_RGB444
136262. DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT
136263. DP_PIXEL_ENCODING_TYPE_YCBCR420
136264. DP_PIXEL_ENCODING_TYPE_YCBCR422
136265. DP_PIXEL_ENCODING_TYPE_YCBCR444
136266. DP_PIXEL_ENCODING_TYPE_Y_ONLY
136267. DP_PIXEL_ENCODING_YCBCR420
136268. DP_PIXEL_ENCODING_YCBCR422
136269. DP_PIXEL_ENCODING_YCBCR444
136270. DP_PIXEL_ENCODING_Y_ONLY
136271. DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK
136272. DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT
136273. DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK
136274. DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT
136275. DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK
136276. DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT
136277. DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK
136278. DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT
136279. DP_PIX_WIDTH
136280. DP_PLL_CLOCK_ENABLE
136281. DP_PLL_DATA_RATE_HBR
136282. DP_PLL_DATA_RATE_HBR2
136283. DP_PLL_DATA_RATE_RBR
136284. DP_PLL_ENABLE
136285. DP_PLL_FREQ_162MHZ
136286. DP_PLL_FREQ_270MHZ
136287. DP_PLL_FREQ_MASK
136288. DP_PLL_LOOP_BIT_DEFAULT
136289. DP_PLL_PD
136290. DP_PLL_REF_BIT_1_1250V
136291. DP_PLL_REF_BIT_1_2500V
136292. DP_PLL_RESET
136293. DP_PORT_COUNT_MASK
136294. DP_PORT_EN
136295. DP_PORT_REVERSAL
136296. DP_PORT_WIDTH
136297. DP_PORT_WIDTH_1
136298. DP_PORT_WIDTH_2
136299. DP_PORT_WIDTH_4
136300. DP_PORT_WIDTH_MASK
136301. DP_PORT_WIDTH_SHIFT
136302. DP_POWER_DOWN_PHY
136303. DP_POWER_STATE_D0
136304. DP_POWER_STATE_D3
136305. DP_POWER_UP_PHY
136306. DP_PRE_EMPHASIS_0
136307. DP_PRE_EMPHASIS_3_5
136308. DP_PRE_EMPHASIS_6
136309. DP_PRE_EMPHASIS_9_5
136310. DP_PRE_EMPHASIS_MASK
136311. DP_PRE_EMPHASIS_MAX
136312. DP_PRE_EMPHASIS_SHIFT
136313. DP_PSR2_IS_SUPPORTED
136314. DP_PSR2_SU_GRANULARITY_REQUIRED
136315. DP_PSR2_SU_X_GRANULARITY
136316. DP_PSR2_SU_Y_COORDINATE_REQUIRED
136317. DP_PSR2_SU_Y_GRANULARITY
136318. DP_PSR2_WITH_Y_COORD_IS_SUPPORTED
136319. DP_PSR_CAPS
136320. DP_PSR_CAPS_CHANGE
136321. DP_PSR_CRC_VERIFICATION
136322. DP_PSR_ENABLE
136323. DP_PSR_ENABLE_PSR2
136324. DP_PSR_EN_CFG
136325. DP_PSR_ERROR_STATUS
136326. DP_PSR_ESI
136327. DP_PSR_FRAME_CAPTURE
136328. DP_PSR_IRQ_HPD_WITH_CRC_ERRORS
136329. DP_PSR_IS_SUPPORTED
136330. DP_PSR_LINK_CRC_ERROR
136331. DP_PSR_MAIN_LINK_ACTIVE
136332. DP_PSR_NO_TRAIN_ON_EXIT
136333. DP_PSR_RFB_STORAGE_ERROR
136334. DP_PSR_SELECTIVE_UPDATE
136335. DP_PSR_SETUP_TIME_0
136336. DP_PSR_SETUP_TIME_110
136337. DP_PSR_SETUP_TIME_165
136338. DP_PSR_SETUP_TIME_220
136339. DP_PSR_SETUP_TIME_275
136340. DP_PSR_SETUP_TIME_330
136341. DP_PSR_SETUP_TIME_55
136342. DP_PSR_SETUP_TIME_MASK
136343. DP_PSR_SETUP_TIME_SHIFT
136344. DP_PSR_SINK_ACTIVE_RESYNC
136345. DP_PSR_SINK_ACTIVE_RFB
136346. DP_PSR_SINK_ACTIVE_SINK_SYNCED
136347. DP_PSR_SINK_ACTIVE_SRC_SYNCED
136348. DP_PSR_SINK_INACTIVE
136349. DP_PSR_SINK_INTERNAL_ERROR
136350. DP_PSR_SINK_STATE_MASK
136351. DP_PSR_STATE_BIT
136352. DP_PSR_STATUS
136353. DP_PSR_SUPPORT
136354. DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR
136355. DP_PWR_NOT_NEEDED
136356. DP_QUERY_PAYLOAD
136357. DP_QUERY_STREAM_ENC_STATUS
136358. DP_RECEIVER_ALPM_CAP
136359. DP_RECEIVER_ALPM_CONFIG
136360. DP_RECEIVER_ALPM_STATUS
136361. DP_RECEIVER_CAP_SIZE
136362. DP_RECEIVE_PORT_0_BUFFER_SIZE
136363. DP_RECEIVE_PORT_0_CAP_0
136364. DP_RECEIVE_PORT_0_STATUS
136365. DP_RECEIVE_PORT_1_BUFFER_SIZE
136366. DP_RECEIVE_PORT_1_CAP_0
136367. DP_RECEIVE_PORT_1_STATUS
136368. DP_RECONNECT
136369. DP_RECOVERED_CLOCK_OUT_EN
136370. DP_REG
136371. DP_REMOTE_CONTROL_COMMAND_PENDING
136372. DP_REMOTE_DPCD_READ
136373. DP_REMOTE_DPCD_WRITE
136374. DP_REMOTE_I2C_READ
136375. DP_REMOTE_I2C_READ_MAX_TRANSACTIONS
136376. DP_REMOTE_I2C_WRITE
136377. DP_REP_LAT
136378. DP_RESOURCE_STATUS_NOTIFY
136379. DP_RETRY_LIMIT
136380. DP_RF_REG_NUM
136381. DP_RW_SYNC
136382. DP_RX_GTC_MSTR_REQ_STATUS_CHANGE
136383. DP_RX_PACKET_RING_CHUNK_NUM
136384. DP_RX_PACKET_RING_CHUNK_SIZE
136385. DP_SCRAMBLING_DISABLE
136386. DP_SCRAMBLING_DISABLE_IRONLAKE
136387. DP_SDP_AUDIO_COPYMANAGEMENT
136388. DP_SDP_AUDIO_STREAM
136389. DP_SDP_AUDIO_TIMESTAMP
136390. DP_SDP_CAMERA_GENERIC
136391. DP_SDP_EXTENSION
136392. DP_SDP_ISRC
136393. DP_SDP_PPS
136394. DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1
136395. DP_SDP_VSC
136396. DP_SDP_VSC_EXT_CEA
136397. DP_SDP_VSC_EXT_VESA
136398. DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ
136399. DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE
136400. DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED
136401. DP_SEC_ASP_HIGH_PRIORITY
136402. DP_SEC_ASP_LOW_PRIORITY
136403. DP_SEC_ASP_PRIORITY
136404. DP_SEC_AUDIO_MUTE
136405. DP_SEC_AUDIO_MUTE_HW_CTRL
136406. DP_SEC_AUDIO_MUTE_SW_CTRL
136407. DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK
136408. DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT
136409. DP_SEC_AUD_M__DP_SEC_AUD_M_MASK
136410. DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT
136411. DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK
136412. DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT
136413. DP_SEC_AUD_N__DP_SEC_AUD_N_MASK
136414. DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT
136415. DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT
136416. DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK
136417. DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT
136418. DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK
136419. DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT
136420. DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK
136421. DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT
136422. DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK
136423. DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK
136424. DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT
136425. DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT
136426. DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK
136427. DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT
136428. DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK
136429. DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT
136430. DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK
136431. DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT
136432. DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK
136433. DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT
136434. DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK
136435. DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT
136436. DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK
136437. DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT
136438. DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK
136439. DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT
136440. DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK
136441. DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT
136442. DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK
136443. DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT
136444. DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK
136445. DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT
136446. DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK
136447. DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT
136448. DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK
136449. DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT
136450. DP_SEC_COLLISION_ACK
136451. DP_SEC_COLLISION_ACK_CLR_FLAG
136452. DP_SEC_COLLISION_ACK_NO_EFFECT
136453. DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK
136454. DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT
136455. DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK
136456. DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT
136457. DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK
136458. DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT
136459. DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK
136460. DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT
136461. DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK
136462. DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT
136463. DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK
136464. DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT
136465. DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK
136466. DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK
136467. DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT
136468. DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT
136469. DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK
136470. DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT
136471. DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK
136472. DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT
136473. DP_SEC_GSP0_PRIORITY
136474. DP_SEC_GSP0_SEND
136475. DP_SEC_GSP_SEND
136476. DP_SEC_GSP_SEND_ANY_LINE
136477. DP_SEC_GSP_SEND_PPS
136478. DP_SEC_LINE_REFERENCE
136479. DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK
136480. DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT
136481. DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK
136482. DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT
136483. DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK
136484. DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT
136485. DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK
136486. DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT
136487. DP_SEC_TIMESTAMP_AUTO_CALC_MODE
136488. DP_SEC_TIMESTAMP_MODE
136489. DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE
136490. DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK
136491. DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC
136492. DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT
136493. DP_SEL
136494. DP_SELECT
136495. DP_SEL_DESCRIPTOR
136496. DP_SEL_DPRDY
136497. DP_SEL_DPRDY_
136498. DP_SEL_FCT_RX
136499. DP_SEL_FCT_TX
136500. DP_SEL_LSO_HEAD
136501. DP_SEL_MASK_
136502. DP_SEL_RFE_RAM
136503. DP_SEL_RSEL
136504. DP_SEL_RSEL_DESC_RAM_
136505. DP_SEL_RSEL_LSO_
136506. DP_SEL_RSEL_MASK_
136507. DP_SEL_RSEL_OTP_64BIT_
136508. DP_SEL_RSEL_OTP_8BIT_
136509. DP_SEL_RSEL_RXFIFO_
136510. DP_SEL_RSEL_TXFIFO_
136511. DP_SEL_RSEL_URXBUF_
136512. DP_SEL_RSEL_USB_PHY_CSRS_
136513. DP_SEL_RSEL_UTX_BUF_RAM_
136514. DP_SEL_RSEL_VLAN_DA_
136515. DP_SEL_URX
136516. DP_SEL_VHF
136517. DP_SEL_VHF_HASH_LEN
136518. DP_SEL_VHF_VLAN_LEN
136519. DP_SEL_VOP_LIT
136520. DP_SEL_WOL
136521. DP_SEND_RECEIVE_ACK
136522. DP_SEND_WRITE_ACK
136523. DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION
136524. DP_SERVICE_V2_ACTION_GET_SINK_TYPE
136525. DP_SET_ANSI_8B10B
136526. DP_SET_GUI_ENGINE
136527. DP_SET_GUI_ENGINE2
136528. DP_SET_POWER
136529. DP_SET_POWER_D0
136530. DP_SET_POWER_D3
136531. DP_SET_POWER_D3_AUX_ON
136532. DP_SET_POWER_MASK
136533. DP_SHIFT_COUNT
136534. DP_SHMEM_LINE
136535. DP_SIDEBAND_MSG_DOWN_REP_BASE
136536. DP_SIDEBAND_MSG_DOWN_REQ_BASE
136537. DP_SIDEBAND_MSG_UP_REP_BASE
136538. DP_SIDEBAND_MSG_UP_REQ_BASE
136539. DP_SIDEBAND_REPLY_ACK
136540. DP_SIDEBAND_REPLY_NAK
136541. DP_SIGN_BIT
136542. DP_SINK_CAP_SIZE
136543. DP_SINK_COUNT
136544. DP_SINK_COUNT_CP_READY
136545. DP_SINK_COUNT_ESI
136546. DP_SINK_CP_READY
136547. DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
136548. DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF
136549. DP_SINK_EVENT_NOTIFY
136550. DP_SINK_HW_REVISION_START
136551. DP_SINK_OUI
136552. DP_SINK_SPECIFIC_IRQ
136553. DP_SINK_STATUS
136554. DP_SINK_STATUS_ESI
136555. DP_SOURCE_OUI
136556. DP_SPREAD_AMP_0_5
136557. DP_SRC
136558. DP_SRC_BKGD_CLR
136559. DP_SRC_ENDIAN
136560. DP_SRC_FRGD_CLR
136561. DP_SRC_HOST
136562. DP_SRC_HOST_BYTEALIGN
136563. DP_SRC_MEM_RECTANGULAR
136564. DP_SRC_RECT
136565. DP_SRC_SOURCE_MASK
136566. DP_SRC_SOURCE_MEMORY
136567. DP_SSC_CLK_GATE
136568. DP_SSC_MASK
136569. DP_SSC_PWR_GATE
136570. DP_SSC_PWR_ON
136571. DP_SSC_RESET
136572. DP_SSS_CLK_GATE
136573. DP_SSS_MASK
136574. DP_SSS_PWR_GATE
136575. DP_SSS_PWR_ON
136576. DP_SSS_RESET
136577. DP_SST_SPLIT_SDP_CAP
136578. DP_STATE_CONFIGURE
136579. DP_STATE_ENTER
136580. DP_STATE_EXIT
136581. DP_STATE_IDLE
136582. DP_STATE_UPDATE
136583. DP_STATUS_CONNECTION
136584. DP_STATUS_CON_BOTH
136585. DP_STATUS_CON_DFP_D
136586. DP_STATUS_CON_DISABLED
136587. DP_STATUS_CON_UFP_D
136588. DP_STATUS_ENABLED
136589. DP_STATUS_EXIT_DP_MODE
136590. DP_STATUS_HPD_STATE
136591. DP_STATUS_IRQ_HPD
136592. DP_STATUS_POWER_LOW
136593. DP_STATUS_PREFER_MULTI_FUNC
136594. DP_STATUS_SWITCH_TO_USB
136595. DP_STC_REF
136596. DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK
136597. DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT
136598. DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK
136599. DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT
136600. DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK
136601. DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT
136602. DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK
136603. DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT
136604. DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK
136605. DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT
136606. DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK
136607. DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT
136608. DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK
136609. DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT
136610. DP_STEER_OVERFLOW_ACK
136611. DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT
136612. DP_STEER_OVERFLOW_ACK_NO_EFFECT
136613. DP_STEER_OVERFLOW_MASK
136614. DP_STEER_OVERFLOW_MASKED
136615. DP_STEER_OVERFLOW_UNMASK
136616. DP_STR
136617. DP_SUPPORTED_LINK_RATES
136618. DP_SU_VALID
136619. DP_SW_RESET
136620. DP_SYMBOL_ERROR_COUNT_BOTH
136621. DP_SYMBOL_ERROR_COUNT_DISPARITY
136622. DP_SYMBOL_ERROR_COUNT_MASK
136623. DP_SYMBOL_ERROR_COUNT_SYMBOL
136624. DP_SYNC
136625. DP_SYNCHRONIZATION_LATENCY_IN_SINK
136626. DP_SYNC_HS_HIGH
136627. DP_SYNC_POLARITY
136628. DP_SYNC_POLARITY_ACTIVE_HIGH
136629. DP_SYNC_POLARITY_ACTIVE_LOW
136630. DP_SYNC_VS_HIGH
136631. DP_S_SRM_MODE_MASK
136632. DP_S_SRM_MODE_NEXT_FRAME
136633. DP_S_SRM_MODE_NOW
136634. DP_T12_CNTL
136635. DP_TEST_80BIT_CUSTOM_PATTERN_15_8
136636. DP_TEST_80BIT_CUSTOM_PATTERN_23_16
136637. DP_TEST_80BIT_CUSTOM_PATTERN_31_24
136638. DP_TEST_80BIT_CUSTOM_PATTERN_39_32
136639. DP_TEST_80BIT_CUSTOM_PATTERN_47_40
136640. DP_TEST_80BIT_CUSTOM_PATTERN_55_48
136641. DP_TEST_80BIT_CUSTOM_PATTERN_63_56
136642. DP_TEST_80BIT_CUSTOM_PATTERN_71_64
136643. DP_TEST_80BIT_CUSTOM_PATTERN_79_72
136644. DP_TEST_80BIT_CUSTOM_PATTERN_7_0
136645. DP_TEST_ACK
136646. DP_TEST_AUDIO_MODE
136647. DP_TEST_AUDIO_PATTERN_TYPE
136648. DP_TEST_AUDIO_PERIOD_CH1
136649. DP_TEST_AUDIO_PERIOD_CH2
136650. DP_TEST_AUDIO_PERIOD_CH3
136651. DP_TEST_AUDIO_PERIOD_CH4
136652. DP_TEST_AUDIO_PERIOD_CH5
136653. DP_TEST_AUDIO_PERIOD_CH6
136654. DP_TEST_AUDIO_PERIOD_CH7
136655. DP_TEST_AUDIO_PERIOD_CH8
136656. DP_TEST_BIT_DEPTH_10
136657. DP_TEST_BIT_DEPTH_12
136658. DP_TEST_BIT_DEPTH_16
136659. DP_TEST_BIT_DEPTH_6
136660. DP_TEST_BIT_DEPTH_8
136661. DP_TEST_BIT_DEPTH_MASK
136662. DP_TEST_BIT_DEPTH_SHIFT
136663. DP_TEST_COLOR_FORMAT_MASK
136664. DP_TEST_COLOR_FORMAT_SHIFT
136665. DP_TEST_COUNT_MASK
136666. DP_TEST_CRC_B_CB
136667. DP_TEST_CRC_G_Y
136668. DP_TEST_CRC_R_CR
136669. DP_TEST_CRC_SUPPORTED
136670. DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK
136671. DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT
136672. DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK
136673. DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT
136674. DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK
136675. DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT
136676. DP_TEST_DYNAMIC_RANGE_CEA
136677. DP_TEST_DYNAMIC_RANGE_VESA
136678. DP_TEST_EDID_CHECKSUM
136679. DP_TEST_EDID_CHECKSUM_WRITE
136680. DP_TEST_HSYNC_HI
136681. DP_TEST_HSYNC_POLARITY
136682. DP_TEST_HSYNC_WIDTH_HI_MASK
136683. DP_TEST_HSYNC_WIDTH_LO
136684. DP_TEST_H_START_HI
136685. DP_TEST_H_START_LO
136686. DP_TEST_H_TOTAL_HI
136687. DP_TEST_H_TOTAL_LO
136688. DP_TEST_H_WIDTH_HI
136689. DP_TEST_H_WIDTH_LO
136690. DP_TEST_INTERLACED
136691. DP_TEST_LANE_COUNT
136692. DP_TEST_LINK_AUDIO_DISABLED_VIDEO
136693. DP_TEST_LINK_AUDIO_PATTERN
136694. DP_TEST_LINK_EDID_READ
136695. DP_TEST_LINK_FAUX_PATTERN
136696. DP_TEST_LINK_PHY_TEST_PATTERN
136697. DP_TEST_LINK_RATE
136698. DP_TEST_LINK_TRAINING
136699. DP_TEST_LINK_VIDEO_PATTERN
136700. DP_TEST_MISC0
136701. DP_TEST_MISC1
136702. DP_TEST_NAK
136703. DP_TEST_PATTERN
136704. DP_TEST_PATTERN_80BIT_CUSTOM
136705. DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED
136706. DP_TEST_PATTERN_AUDIO_SAWTOOTH
136707. DP_TEST_PATTERN_COLOR_RAMP
136708. DP_TEST_PATTERN_COLOR_SQUARES
136709. DP_TEST_PATTERN_COLOR_SQUARES_CEA
136710. DP_TEST_PATTERN_CP2520_1
136711. DP_TEST_PATTERN_CP2520_2
136712. DP_TEST_PATTERN_CP2520_3
136713. DP_TEST_PATTERN_D102
136714. DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
136715. DP_TEST_PATTERN_HORIZONTAL_BARS
136716. DP_TEST_PATTERN_PHY_PATTERN_BEGIN
136717. DP_TEST_PATTERN_PHY_PATTERN_END
136718. DP_TEST_PATTERN_PRBS7
136719. DP_TEST_PATTERN_SYMBOL_ERROR
136720. DP_TEST_PATTERN_TRAINING_PATTERN1
136721. DP_TEST_PATTERN_TRAINING_PATTERN2
136722. DP_TEST_PATTERN_TRAINING_PATTERN3
136723. DP_TEST_PATTERN_TRAINING_PATTERN4
136724. DP_TEST_PATTERN_UNSUPPORTED
136725. DP_TEST_PATTERN_VERTICAL_BARS
136726. DP_TEST_PATTERN_VIDEO_MODE
136727. DP_TEST_PHY_PATTERN
136728. DP_TEST_REFRESH_DENOMINATOR
136729. DP_TEST_REFRESH_RATE_NUMERATOR
136730. DP_TEST_REQUEST
136731. DP_TEST_RESPONSE
136732. DP_TEST_SINK
136733. DP_TEST_SINK_MISC
136734. DP_TEST_SINK_START
136735. DP_TEST_SYNC_CLOCK
136736. DP_TEST_VSYNC_HI
136737. DP_TEST_VSYNC_POLARITY
136738. DP_TEST_VSYNC_WIDTH_HI_MASK
136739. DP_TEST_VSYNC_WIDTH_LO
136740. DP_TEST_V_HEIGHT_HI
136741. DP_TEST_V_HEIGHT_LO
136742. DP_TEST_V_START_HI
136743. DP_TEST_V_START_LO
136744. DP_TEST_V_TOTAL_HI
136745. DP_TEST_V_TOTAL_LO
136746. DP_TEST_YCBCR_COEFFICIENTS
136747. DP_TIMEOUT_LOOP_COUNT
136748. DP_TIMEOUT_PSR_LOOP_MS
136749. DP_TIMEOUT_TRAINING_US
136750. DP_TOP_FIELD_ONLY
136751. DP_TOP_PLUS_BOTTOM_FIELD
136752. DP_TPS3_SUPPORTED
136753. DP_TPS4_SUPPORTED
136754. DP_TP_CTL
136755. DP_TP_CTL_ENABLE
136756. DP_TP_CTL_ENHANCED_FRAME_ENABLE
136757. DP_TP_CTL_FDI_AUTOTRAIN
136758. DP_TP_CTL_FEC_ENABLE
136759. DP_TP_CTL_FORCE_ACT
136760. DP_TP_CTL_LINK_TRAIN_IDLE
136761. DP_TP_CTL_LINK_TRAIN_MASK
136762. DP_TP_CTL_LINK_TRAIN_NORMAL
136763. DP_TP_CTL_LINK_TRAIN_PAT1
136764. DP_TP_CTL_LINK_TRAIN_PAT2
136765. DP_TP_CTL_LINK_TRAIN_PAT3
136766. DP_TP_CTL_LINK_TRAIN_PAT4
136767. DP_TP_CTL_MODE_MST
136768. DP_TP_CTL_MODE_SST
136769. DP_TP_CTL_SCRAMBLE_DISABLE
136770. DP_TP_CTL_TO_PORT
136771. DP_TP_STATUS
136772. DP_TP_STATUS_ACT_SENT
136773. DP_TP_STATUS_AUTOTRAIN_DONE
136774. DP_TP_STATUS_FEC_ENABLE_LIVE
136775. DP_TP_STATUS_IDLE_DONE
136776. DP_TP_STATUS_MODE_STATUS_MST
136777. DP_TP_STATUS_PAYLOAD_MAPPING_VC0
136778. DP_TP_STATUS_PAYLOAD_MAPPING_VC1
136779. DP_TP_STATUS_PAYLOAD_MAPPING_VC2
136780. DP_TRAINING_AUX_RD_INTERVAL
136781. DP_TRAINING_AUX_RD_MASK
136782. DP_TRAINING_LANE0_1_SET2
136783. DP_TRAINING_LANE0_SET
136784. DP_TRAINING_LANE1_SET
136785. DP_TRAINING_LANE2_3_SET2
136786. DP_TRAINING_LANE2_SET
136787. DP_TRAINING_LANE3_SET
136788. DP_TRAINING_PATTERN_1
136789. DP_TRAINING_PATTERN_2
136790. DP_TRAINING_PATTERN_3
136791. DP_TRAINING_PATTERN_4
136792. DP_TRAINING_PATTERN_DISABLE
136793. DP_TRAINING_PATTERN_MASK
136794. DP_TRAINING_PATTERN_MASK_1_4
136795. DP_TRAINING_PATTERN_SEQUENCE_1
136796. DP_TRAINING_PATTERN_SEQUENCE_2
136797. DP_TRAINING_PATTERN_SEQUENCE_3
136798. DP_TRAINING_PATTERN_SEQUENCE_4
136799. DP_TRAINING_PATTERN_SET
136800. DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
136801. DP_TRAIN_MAX_SWING_REACHED
136802. DP_TRAIN_PRE_EMPHASIS_MASK
136803. DP_TRAIN_PRE_EMPHASIS_SHIFT
136804. DP_TRAIN_PRE_EMPH_LEVEL_0
136805. DP_TRAIN_PRE_EMPH_LEVEL_1
136806. DP_TRAIN_PRE_EMPH_LEVEL_2
136807. DP_TRAIN_PRE_EMPH_LEVEL_3
136808. DP_TRAIN_VOLTAGE_SWING_LEVEL_0
136809. DP_TRAIN_VOLTAGE_SWING_LEVEL_1
136810. DP_TRAIN_VOLTAGE_SWING_LEVEL_2
136811. DP_TRAIN_VOLTAGE_SWING_LEVEL_3
136812. DP_TRAIN_VOLTAGE_SWING_MASK
136813. DP_TRAIN_VOLTAGE_SWING_SHIFT
136814. DP_TRANSLATOR_DELAY
136815. DP_TU_OVERFLOW_ACK
136816. DP_TU_OVERFLOW_ACK_CLR_INTERRUPT
136817. DP_TU_OVERFLOW_ACK_NO_EFFECT
136818. DP_TX_COMPLETE_TIME_OUT
136819. DP_TX_PACKET_RING_CHUNK_NUM
136820. DP_TX_PACKET_RING_CHUNK_SIZE
136821. DP_TX_PHY_CONFIG_REG
136822. DP_TX_PHY_SCRAMBLER_SEED
136823. DP_TX_PHY_SW_RESET
136824. DP_TX_PHY_TRAINING_01_04
136825. DP_TX_PHY_TRAINING_05_08
136826. DP_TX_PHY_TRAINING_09_10
136827. DP_UDI_1_LANE
136828. DP_UDI_2_LANES
136829. DP_UDI_4_LANES
136830. DP_UDI_LANES
136831. DP_UDI_LANES_RESERVED
136832. DP_UNPLUG
136833. DP_UPDATE_RFB_BIT
136834. DP_UPSTREAM_DEVICE_DP_PWR_NEED
136835. DP_UPSTREAM_IS_SRC
136836. DP_UP_REQ_EN
136837. DP_UP_REQ_MSG_RDY
136838. DP_VB_ID
136839. DP_VC_PAYLOAD_ID_SLOT_1
136840. DP_VC_TABLE
136841. DP_VERBOSE
136842. DP_VERTICAL_0
136843. DP_VERTICAL_1
136844. DP_VG_FACTOR_100US
136845. DP_VG_FACTOR_1MS
136846. DP_VG_FACTOR_200US
136847. DP_VG_FACTOR_2MS
136848. DP_VG_FACTOR_3MS
136849. DP_VG_FACTOR_500US
136850. DP_VG_FACTOR_MASK
136851. DP_VIDEO_REF
136852. DP_VID_ENHANCED_FRAME_MODE
136853. DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK
136854. DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT
136855. DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK
136856. DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT
136857. DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK
136858. DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT
136859. DP_VID_INTER_LAT
136860. DP_VID_MSA_TOP_FIELD_MODE
136861. DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK
136862. DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT
136863. DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK
136864. DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT
136865. DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK
136866. DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT
136867. DP_VID_M_1X_INPUT_PIXEL_RATE
136868. DP_VID_M_2X_INPUT_PIXEL_RATE
136869. DP_VID_M_4X_INPUT_PIXEL_RATE
136870. DP_VID_M_8X_INPUT_PIXEL_RATE
136871. DP_VID_M_DOUBLE_INPUT_PIXEL_RATE
136872. DP_VID_M_DOUBLE_VALUE_EN
136873. DP_VID_M_INPUT_PIXEL_RATE
136874. DP_VID_M_N_CALC_AUTO
136875. DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE
136876. DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START
136877. DP_VID_M_N_DOUBLE_BUFFER_MODE
136878. DP_VID_M_N_GEN_EN
136879. DP_VID_M_N_PROGRAMMED_VIA_REG
136880. DP_VID_M__DP_VID_M_MASK
136881. DP_VID_M__DP_VID_M__SHIFT
136882. DP_VID_N_MUL
136883. DP_VID_N__DP_VID_N_MASK
136884. DP_VID_N__DP_VID_N__SHIFT
136885. DP_VID_PROG_LAT
136886. DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK
136887. DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT
136888. DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK
136889. DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT
136890. DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK
136891. DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT
136892. DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK
136893. DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT
136894. DP_VID_STREAM_DISABLE_ACK
136895. DP_VID_STREAM_DISABLE_MASK
136896. DP_VID_STREAM_DIS_DEFER
136897. DP_VID_STREAM_DIS_DEFER_TO_HBLANK
136898. DP_VID_STREAM_DIS_DEFER_TO_VBLANK
136899. DP_VID_STREAM_DIS_NO_DEFER
136900. DP_VID_TIMING_MODE
136901. DP_VID_TIMING_MODE_ASYNC
136902. DP_VID_TIMING_MODE_SYNC
136903. DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK
136904. DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT
136905. DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK
136906. DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT
136907. DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK
136908. DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT
136909. DP_VID_TIMING__DP_VID_N_DIV_MASK
136910. DP_VID_TIMING__DP_VID_N_DIV__SHIFT
136911. DP_VID_TIMING__DP_VID_TIMING_MODE_MASK
136912. DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT
136913. DP_VID_VBID_FIELD_POL
136914. DP_VID_VBID_FIELD_POL_INV
136915. DP_VID_VBID_FIELD_POL_NORMAL
136916. DP_VOLTAGE_0_4
136917. DP_VOLTAGE_0_6
136918. DP_VOLTAGE_0_8
136919. DP_VOLTAGE_1_2
136920. DP_VOLTAGE_MASK
136921. DP_VOLTAGE_MAX
136922. DP_VOLTAGE_SHIFT
136923. DP_VPORT_HASH_BUCKETS
136924. DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED
136925. DP_VSC_EXT_CEA_SDP_SUPPORTED
136926. DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED
136927. DP_VSC_EXT_VESA_SDP_SUPPORTED
136928. DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
136929. DP_VS_LEVEL0_PREEMPH_LEVEL0
136930. DP_VS_LEVEL0_PREEMPH_LEVEL1
136931. DP_VS_LEVEL0_PREEMPH_LEVEL2
136932. DP_VS_LEVEL0_PREEMPH_LEVEL3
136933. DP_VS_LEVEL1_PREEMPH_LEVEL0
136934. DP_VS_LEVEL1_PREEMPH_LEVEL1
136935. DP_VS_LEVEL1_PREEMPH_LEVEL2
136936. DP_VS_LEVEL2_PREEMPH_LEVEL0
136937. DP_VS_LEVEL2_PREEMPH_LEVEL1
136938. DP_VS_LEVEL3_PREEMPH_LEVEL0
136939. DP_WINDOW_SIZE
136940. DP_WRITE_MASK
136941. DP_WRITE_MSK
136942. DP_WSAME
136943. DP_XOP
136944. DP_YCBCR_COEFFICIENTS_ITU601
136945. DP_YCBCR_COEFFICIENTS_ITU709
136946. DP_YCBCR_RANGE
136947. DP_YCBCR_RANGE_BT601_5
136948. DP_YCBCR_RANGE_BT709_5
136949. DP_Y_COORDINATE_VALID
136950. DP_ZEROES
136951. DP__MEM_PG
136952. DP__MEM_PG__0
136953. DQ
136954. DQA_ENABLE_CMD
136955. DQCOUNT_INVALID
136956. DQF_GETINFO_MASK
136957. DQF_INFO_DIRTY
136958. DQF_INFO_DIRTY_B
136959. DQF_PRIVATE
136960. DQF_ROOT_SQUASH
136961. DQF_ROOT_SQUASH_B
136962. DQF_SETINFO_MASK
136963. DQF_SYS_FILE
136964. DQF_SYS_FILE_B
136965. DQH_ALIGNMENT
136966. DQL_MAX_LIMIT
136967. DQL_MAX_OBJECT
136968. DQPSK
136969. DQRR_CARRY
136970. DQRR_MAXFILL
136971. DQRR_SHIFT
136972. DQS0_GATE
136973. DQS1_GATE
136974. DQSI0
136975. DQSI0_TAP
136976. DQSI0_TAP_MASK
136977. DQSI1
136978. DQSI1_TAP
136979. DQSI1_TAP_MASK
136980. DQST_ALLOC_DQUOTS
136981. DQST_CACHE_HITS
136982. DQST_DROPS
136983. DQST_FREE_DQUOTS
136984. DQST_LOOKUPS
136985. DQST_READS
136986. DQST_SYNCS
136987. DQST_WRITES
136988. DQS_CTRL_GET_RD_DELAY
136989. DQS_CTRL_RD_DELAY
136990. DQT
136991. DQT_LEN
136992. DQT_START
136993. DQUOT_DEL_ALLOC
136994. DQUOT_DEL_REWRITE
136995. DQUOT_INIT_ALLOC
136996. DQUOT_INIT_REWRITE
136997. DQUOT_ITEM
136998. DQUOT_LIMITS_ENABLED
136999. DQUOT_NEGATIVE_USAGE
137000. DQUOT_NOLIST_DIRTY
137001. DQUOT_QUOTA_SYS_FILE
137002. DQUOT_SPACE_NOFAIL
137003. DQUOT_SPACE_RESERVE
137004. DQUOT_SPACE_WARN
137005. DQUOT_STATE_FLAGS
137006. DQUOT_STATE_LAST
137007. DQUOT_SUSPENDED
137008. DQUOT_USAGE_ENABLED
137009. DQX
137010. DQX_MASK
137011. DQ_ACTIVE_B
137012. DQ_BLKS_B
137013. DQ_CONN_TYPE_RANGE_SHIFT
137014. DQ_DEMS_LEGACY
137015. DQ_DEMS_ROCE_CQ_CONS
137016. DQ_DEMS_TOE_LOCAL_ADV_WND
137017. DQ_DEMS_TOE_MORE_TO_SEND
137018. DQ_DPM_WQE_BUFF_SIZE
137019. DQ_FAKE_B
137020. DQ_FQID_MASK
137021. DQ_FRAME_COUNT_MASK
137022. DQ_INODES_B
137023. DQ_LASTSET_B
137024. DQ_MOD_B
137025. DQ_PWM_OFFSET_DPM_BASE
137026. DQ_PWM_OFFSET_DPM_END
137027. DQ_PWM_OFFSET_TCM16_BASE
137028. DQ_PWM_OFFSET_TCM32_BASE
137029. DQ_PWM_OFFSET_TCM_FLAGS
137030. DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD
137031. DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD
137032. DQ_PWM_OFFSET_UCM16_4
137033. DQ_PWM_OFFSET_UCM16_BASE
137034. DQ_PWM_OFFSET_UCM32_BASE
137035. DQ_PWM_OFFSET_UCM_FLAGS
137036. DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS
137037. DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT
137038. DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT
137039. DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT
137040. DQ_PWM_OFFSET_XCM16_BASE
137041. DQ_PWM_OFFSET_XCM32_BASE
137042. DQ_PWM_OFFSET_XCM_FLAGS
137043. DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD
137044. DQ_RANGE_ALIGN
137045. DQ_RANGE_SHIFT
137046. DQ_READ_B
137047. DQ_REGION_SHIFT
137048. DQ_TCM_AGG_FLG_SHIFT_CF0
137049. DQ_TCM_AGG_FLG_SHIFT_CF1
137050. DQ_TCM_AGG_FLG_SHIFT_CF2
137051. DQ_TCM_AGG_FLG_SHIFT_CF3
137052. DQ_TCM_AGG_FLG_SHIFT_CF4
137053. DQ_TCM_AGG_FLG_SHIFT_CF5
137054. DQ_TCM_AGG_FLG_SHIFT_CF6
137055. DQ_TCM_AGG_FLG_SHIFT_CF7
137056. DQ_TCM_AGG_VAL_SEL_REG1
137057. DQ_TCM_AGG_VAL_SEL_REG2
137058. DQ_TCM_AGG_VAL_SEL_REG6
137059. DQ_TCM_AGG_VAL_SEL_REG9
137060. DQ_TCM_AGG_VAL_SEL_WORD0
137061. DQ_TCM_AGG_VAL_SEL_WORD1
137062. DQ_TCM_AGG_VAL_SEL_WORD2
137063. DQ_TCM_AGG_VAL_SEL_WORD3
137064. DQ_TCM_FCOE_DUMMY_TIMER_CMD
137065. DQ_TCM_FCOE_FLUSH_Q0_CMD
137066. DQ_TCM_FCOE_TIMER_STOP_ALL_CMD
137067. DQ_TCM_ISCSI_FLUSH_Q0_CMD
137068. DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD
137069. DQ_TCM_IWARP_POST_RQ_CF_CMD
137070. DQ_TCM_L2B_BD_PROD_CMD
137071. DQ_TCM_ROCE_RQ_PROD_CMD
137072. DQ_TCM_TOE_FLUSH_Q0_CMD
137073. DQ_TCM_TOE_TIMER_STOP_ALL_CMD
137074. DQ_UCM_AGG_FLG_SHIFT_CF0
137075. DQ_UCM_AGG_FLG_SHIFT_CF1
137076. DQ_UCM_AGG_FLG_SHIFT_CF3
137077. DQ_UCM_AGG_FLG_SHIFT_CF4
137078. DQ_UCM_AGG_FLG_SHIFT_CF5
137079. DQ_UCM_AGG_FLG_SHIFT_CF6
137080. DQ_UCM_AGG_FLG_SHIFT_RULE0EN
137081. DQ_UCM_AGG_FLG_SHIFT_RULE1EN
137082. DQ_UCM_AGG_VAL_SEL_REG0
137083. DQ_UCM_AGG_VAL_SEL_REG1
137084. DQ_UCM_AGG_VAL_SEL_REG2
137085. DQ_UCM_AGG_VAL_SEL_REG3
137086. DQ_UCM_AGG_VAL_SEL_WORD0
137087. DQ_UCM_AGG_VAL_SEL_WORD1
137088. DQ_UCM_AGG_VAL_SEL_WORD2
137089. DQ_UCM_AGG_VAL_SEL_WORD3
137090. DQ_UCM_ETH_PMD_RX_ARM_CMD
137091. DQ_UCM_ETH_PMD_RX_CONS_CMD
137092. DQ_UCM_ETH_PMD_TX_ARM_CMD
137093. DQ_UCM_ETH_PMD_TX_CONS_CMD
137094. DQ_UCM_ROCE_CQ_ARM_CF_CMD
137095. DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD
137096. DQ_UCM_ROCE_CQ_CONS_CMD
137097. DQ_UCM_ROCE_CQ_PROD_CMD
137098. DQ_UCM_TOE_DQ_CF_CMD
137099. DQ_UCM_TOE_SLOW_PATH_CF_CMD
137100. DQ_UCM_TOE_TIMER_STOP_ALL_CMD
137101. DQ_XCM_AGG_FLG_SHIFT_BIT14
137102. DQ_XCM_AGG_FLG_SHIFT_BIT15
137103. DQ_XCM_AGG_FLG_SHIFT_CF12
137104. DQ_XCM_AGG_FLG_SHIFT_CF13
137105. DQ_XCM_AGG_FLG_SHIFT_CF18
137106. DQ_XCM_AGG_FLG_SHIFT_CF19
137107. DQ_XCM_AGG_FLG_SHIFT_CF22
137108. DQ_XCM_AGG_FLG_SHIFT_CF23
137109. DQ_XCM_AGG_VAL_SEL_REG3
137110. DQ_XCM_AGG_VAL_SEL_REG4
137111. DQ_XCM_AGG_VAL_SEL_REG5
137112. DQ_XCM_AGG_VAL_SEL_REG6
137113. DQ_XCM_AGG_VAL_SEL_WORD2
137114. DQ_XCM_AGG_VAL_SEL_WORD3
137115. DQ_XCM_AGG_VAL_SEL_WORD4
137116. DQ_XCM_AGG_VAL_SEL_WORD5
137117. DQ_XCM_CORE_DQ_CF_CMD
137118. DQ_XCM_CORE_SLOW_PATH_CMD
137119. DQ_XCM_CORE_SPQ_PROD_CMD
137120. DQ_XCM_CORE_TERMINATE_CMD
137121. DQ_XCM_CORE_TX_BD_CONS_CMD
137122. DQ_XCM_CORE_TX_BD_PROD_CMD
137123. DQ_XCM_ETH_DQ_CF_CMD
137124. DQ_XCM_ETH_EDPM_NUM_BDS_CMD
137125. DQ_XCM_ETH_GO_TO_BD_CONS_CMD
137126. DQ_XCM_ETH_SLOW_PATH_CMD
137127. DQ_XCM_ETH_TERMINATE_CMD
137128. DQ_XCM_ETH_TPH_EN_CMD
137129. DQ_XCM_ETH_TX_BD_CONS_CMD
137130. DQ_XCM_ETH_TX_BD_PROD_CMD
137131. DQ_XCM_FCOE_SLOW_PATH_CMD
137132. DQ_XCM_FCOE_SQ_CONS_CMD
137133. DQ_XCM_FCOE_SQ_PROD_CMD
137134. DQ_XCM_FCOE_X_FERQ_PROD_CMD
137135. DQ_XCM_ISCSI_DQ_FLUSH_CMD
137136. DQ_XCM_ISCSI_EXP_STAT_SN_CMD
137137. DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD
137138. DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD
137139. DQ_XCM_ISCSI_SLOW_PATH_CMD
137140. DQ_XCM_ISCSI_SQ_CONS_CMD
137141. DQ_XCM_ISCSI_SQ_PROD_CMD
137142. DQ_XCM_ROCE_SQ_PROD_CMD
137143. DQ_XCM_TOE_DQ_FLUSH_CMD
137144. DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD
137145. DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD
137146. DQ_XCM_TOE_SLOW_PATH_CMD
137147. DQ_XCM_TOE_TX_BD_PROD_CMD
137148. DR
137149. DR0
137150. DR0_MARK
137151. DR1
137152. DR1_MARK
137153. DR2
137154. DR2_MARK
137155. DR2_SLOW_RET
137156. DR3
137157. DR3_MARK
137158. DR4_MARK
137159. DR5_MARK
137160. DR6_BD
137161. DR6_BS
137162. DR6_BT
137163. DR6_FIXED_1
137164. DR6_INIT
137165. DR6_RESERVED
137166. DR6_RTM
137167. DR6_VOLATILE
137168. DR7_BP_EN_MASK
137169. DR7_FIXED_1
137170. DR7_GD
137171. DR7_GE
137172. DR7_VOLATILE
137173. DRA722_REV_ES1_0
137174. DRA722_REV_ES2_0
137175. DRA722_REV_ES2_1
137176. DRA752_ADC_END_VALUE
137177. DRA752_ADC_START_VALUE
137178. DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK
137179. DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK
137180. DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK
137181. DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK
137182. DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK
137183. DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK
137184. DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK
137185. DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK
137186. DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK
137187. DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK
137188. DRA752_BANDGAP_CTRL_1_OFFSET
137189. DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK
137190. DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK
137191. DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK
137192. DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK
137193. DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK
137194. DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK
137195. DRA752_BANDGAP_CTRL_2_OFFSET
137196. DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK
137197. DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK
137198. DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK
137199. DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK
137200. DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK
137201. DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK
137202. DRA752_BANDGAP_STATUS_1_OFFSET
137203. DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK
137204. DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK
137205. DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK
137206. DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK
137207. DRA752_BANDGAP_STATUS_2_OFFSET
137208. DRA752_BANDGAP_THRESHOLD_COLD_MASK
137209. DRA752_BANDGAP_THRESHOLD_CORE_OFFSET
137210. DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET
137211. DRA752_BANDGAP_THRESHOLD_GPU_OFFSET
137212. DRA752_BANDGAP_THRESHOLD_HOT_MASK
137213. DRA752_BANDGAP_THRESHOLD_IVA_OFFSET
137214. DRA752_BANDGAP_THRESHOLD_MPU_OFFSET
137215. DRA752_CORE_MAX_FREQ
137216. DRA752_CORE_MIN_FREQ
137217. DRA752_CORE_T_COLD
137218. DRA752_CORE_T_HOT
137219. DRA752_DSPEVE_MAX_FREQ
137220. DRA752_DSPEVE_MIN_FREQ
137221. DRA752_DSPEVE_T_COLD
137222. DRA752_DSPEVE_T_HOT
137223. DRA752_DTEMP_CORE_1_OFFSET
137224. DRA752_DTEMP_CORE_2_OFFSET
137225. DRA752_DTEMP_DSPEVE_1_OFFSET
137226. DRA752_DTEMP_DSPEVE_2_OFFSET
137227. DRA752_DTEMP_GPU_1_OFFSET
137228. DRA752_DTEMP_GPU_2_OFFSET
137229. DRA752_DTEMP_IVA_1_OFFSET
137230. DRA752_DTEMP_IVA_2_OFFSET
137231. DRA752_DTEMP_MPU_1_OFFSET
137232. DRA752_DTEMP_MPU_2_OFFSET
137233. DRA752_GPU_MAX_FREQ
137234. DRA752_GPU_MIN_FREQ
137235. DRA752_GPU_T_COLD
137236. DRA752_GPU_T_HOT
137237. DRA752_GRADIENT_CONST_W_PCB
137238. DRA752_GRADIENT_SLOPE_W_PCB
137239. DRA752_IVA_MAX_FREQ
137240. DRA752_IVA_MIN_FREQ
137241. DRA752_IVA_T_COLD
137242. DRA752_IVA_T_HOT
137243. DRA752_MPU_MAX_FREQ
137244. DRA752_MPU_MIN_FREQ
137245. DRA752_MPU_T_COLD
137246. DRA752_MPU_T_HOT
137247. DRA752_REV_ES1_0
137248. DRA752_REV_ES1_1
137249. DRA752_REV_ES2_0
137250. DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET
137251. DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET
137252. DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET
137253. DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET
137254. DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET
137255. DRA752_TEMP_SENSOR_CORE_OFFSET
137256. DRA752_TEMP_SENSOR_DSPEVE_OFFSET
137257. DRA752_TEMP_SENSOR_DTEMP_MASK
137258. DRA752_TEMP_SENSOR_EOCZ_MASK
137259. DRA752_TEMP_SENSOR_GPU_OFFSET
137260. DRA752_TEMP_SENSOR_IVA_OFFSET
137261. DRA752_TEMP_SENSOR_MPU_OFFSET
137262. DRA752_TEMP_SENSOR_TMPSOFF_MASK
137263. DRA762_ABZ_REV_ES1_0
137264. DRA762_ACD_REV_ES1_0
137265. DRA762_REV_ES1_0
137266. DRA7XX_ATL_STATDEP_SHIFT
137267. DRA7XX_CAM_STATDEP_SHIFT
137268. DRA7XX_CLASS
137269. DRA7XX_CM_ATL_ATL_CLKCTRL
137270. DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET
137271. DRA7XX_CM_ATL_CLKSTCTRL_OFFSET
137272. DRA7XX_CM_AUTOIDLE_DPLL_ABE
137273. DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET
137274. DRA7XX_CM_AUTOIDLE_DPLL_CORE
137275. DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET
137276. DRA7XX_CM_AUTOIDLE_DPLL_DDR
137277. DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET
137278. DRA7XX_CM_AUTOIDLE_DPLL_DSP
137279. DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET
137280. DRA7XX_CM_AUTOIDLE_DPLL_EVE
137281. DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET
137282. DRA7XX_CM_AUTOIDLE_DPLL_GMAC
137283. DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET
137284. DRA7XX_CM_AUTOIDLE_DPLL_GPU
137285. DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET
137286. DRA7XX_CM_AUTOIDLE_DPLL_IVA
137287. DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET
137288. DRA7XX_CM_AUTOIDLE_DPLL_MPU
137289. DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET
137290. DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF
137291. DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET
137292. DRA7XX_CM_AUTOIDLE_DPLL_PER
137293. DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET
137294. DRA7XX_CM_AUTOIDLE_DPLL_USB
137295. DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET
137296. DRA7XX_CM_BYPCLK_DPLL_DSP
137297. DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET
137298. DRA7XX_CM_BYPCLK_DPLL_EVE
137299. DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET
137300. DRA7XX_CM_BYPCLK_DPLL_IVA
137301. DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET
137302. DRA7XX_CM_BYPCLK_DPLL_MPU
137303. DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET
137304. DRA7XX_CM_CAM_CLKSTCTRL_OFFSET
137305. DRA7XX_CM_CAM_CSI1_CLKCTRL
137306. DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET
137307. DRA7XX_CM_CAM_CSI2_CLKCTRL
137308. DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET
137309. DRA7XX_CM_CAM_LVDSRX_CLKCTRL
137310. DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET
137311. DRA7XX_CM_CAM_STATICDEP_OFFSET
137312. DRA7XX_CM_CAM_VIP1_CLKCTRL
137313. DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET
137314. DRA7XX_CM_CAM_VIP2_CLKCTRL
137315. DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET
137316. DRA7XX_CM_CAM_VIP3_CLKCTRL
137317. DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET
137318. DRA7XX_CM_CLKDCOLDO_DPLL_USB
137319. DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET
137320. DRA7XX_CM_CLKMODE_APLL_PCIE
137321. DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET
137322. DRA7XX_CM_CLKMODE_DPLL_ABE
137323. DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET
137324. DRA7XX_CM_CLKMODE_DPLL_CORE
137325. DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET
137326. DRA7XX_CM_CLKMODE_DPLL_DDR
137327. DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET
137328. DRA7XX_CM_CLKMODE_DPLL_DSP
137329. DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET
137330. DRA7XX_CM_CLKMODE_DPLL_EVE
137331. DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET
137332. DRA7XX_CM_CLKMODE_DPLL_GMAC
137333. DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET
137334. DRA7XX_CM_CLKMODE_DPLL_GPU
137335. DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET
137336. DRA7XX_CM_CLKMODE_DPLL_IVA
137337. DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET
137338. DRA7XX_CM_CLKMODE_DPLL_MPU
137339. DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET
137340. DRA7XX_CM_CLKMODE_DPLL_PCIE_REF
137341. DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET
137342. DRA7XX_CM_CLKMODE_DPLL_PER
137343. DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET
137344. DRA7XX_CM_CLKMODE_DPLL_USB
137345. DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET
137346. DRA7XX_CM_CLKSEL_ABE
137347. DRA7XX_CM_CLKSEL_ABE_24M
137348. DRA7XX_CM_CLKSEL_ABE_24M_OFFSET
137349. DRA7XX_CM_CLKSEL_ABE_CLK_DIV
137350. DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET
137351. DRA7XX_CM_CLKSEL_ABE_GICLK_DIV
137352. DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET
137353. DRA7XX_CM_CLKSEL_ABE_LP_CLK
137354. DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET
137355. DRA7XX_CM_CLKSEL_ABE_OFFSET
137356. DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS
137357. DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET
137358. DRA7XX_CM_CLKSEL_ABE_PLL_REF
137359. DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET
137360. DRA7XX_CM_CLKSEL_ABE_PLL_SYS
137361. DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET
137362. DRA7XX_CM_CLKSEL_ABE_SYS
137363. DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET
137364. DRA7XX_CM_CLKSEL_ADC_GFCLK
137365. DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET
137366. DRA7XX_CM_CLKSEL_AESS_FCLK_DIV
137367. DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET
137368. DRA7XX_CM_CLKSEL_CLKOUTMUX0
137369. DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET
137370. DRA7XX_CM_CLKSEL_CLKOUTMUX1
137371. DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET
137372. DRA7XX_CM_CLKSEL_CLKOUTMUX2
137373. DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET
137374. DRA7XX_CM_CLKSEL_CORE
137375. DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX
137376. DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET
137377. DRA7XX_CM_CLKSEL_CORE_OFFSET
137378. DRA7XX_CM_CLKSEL_DPLL_ABE
137379. DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET
137380. DRA7XX_CM_CLKSEL_DPLL_CORE
137381. DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET
137382. DRA7XX_CM_CLKSEL_DPLL_DDR
137383. DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET
137384. DRA7XX_CM_CLKSEL_DPLL_DSP
137385. DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET
137386. DRA7XX_CM_CLKSEL_DPLL_EVE
137387. DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET
137388. DRA7XX_CM_CLKSEL_DPLL_GMAC
137389. DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET
137390. DRA7XX_CM_CLKSEL_DPLL_GPU
137391. DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET
137392. DRA7XX_CM_CLKSEL_DPLL_IVA
137393. DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET
137394. DRA7XX_CM_CLKSEL_DPLL_MPU
137395. DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET
137396. DRA7XX_CM_CLKSEL_DPLL_PCIE_REF
137397. DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET
137398. DRA7XX_CM_CLKSEL_DPLL_PER
137399. DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET
137400. DRA7XX_CM_CLKSEL_DPLL_USB
137401. DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET
137402. DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX
137403. DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET
137404. DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX
137405. DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET
137406. DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX
137407. DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET
137408. DRA7XX_CM_CLKSEL_EVE_CLK
137409. DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET
137410. DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX
137411. DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET
137412. DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX
137413. DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET
137414. DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX
137415. DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET
137416. DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX
137417. DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET
137418. DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX
137419. DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET
137420. DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX
137421. DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET
137422. DRA7XX_CM_CLKSEL_HDMI_PLL_SYS
137423. DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET
137424. DRA7XX_CM_CLKSEL_HDMI_TIMER
137425. DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET
137426. DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX
137427. DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET
137428. DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX
137429. DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET
137430. DRA7XX_CM_CLKSEL_MCASP_SYS
137431. DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET
137432. DRA7XX_CM_CLKSEL_MLBP_MCASP
137433. DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET
137434. DRA7XX_CM_CLKSEL_MLB_MCASP
137435. DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET
137436. DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX
137437. DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET
137438. DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX
137439. DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET
137440. DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX
137441. DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET
137442. DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX
137443. DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET
137444. DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX
137445. DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET
137446. DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX
137447. DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET
137448. DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX
137449. DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET
137450. DRA7XX_CM_CLKSEL_SYS
137451. DRA7XX_CM_CLKSEL_SYSCLK1
137452. DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET
137453. DRA7XX_CM_CLKSEL_SYS_CLK1_32K
137454. DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET
137455. DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX
137456. DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET
137457. DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX
137458. DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET
137459. DRA7XX_CM_CLKSEL_SYS_OFFSET
137460. DRA7XX_CM_CLKSEL_TIMER_SYS
137461. DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET
137462. DRA7XX_CM_CLKSEL_USB_60MHZ
137463. DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET
137464. DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX
137465. DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET
137466. DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX
137467. DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET
137468. DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX
137469. DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET
137470. DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS
137471. DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET
137472. DRA7XX_CM_CLKSEL_VIDEO1_TIMER
137473. DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET
137474. DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX
137475. DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET
137476. DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX
137477. DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET
137478. DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS
137479. DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET
137480. DRA7XX_CM_CLKSEL_VIDEO2_TIMER
137481. DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET
137482. DRA7XX_CM_CLKSEL_WKUPAON
137483. DRA7XX_CM_CLKSEL_WKUPAON_OFFSET
137484. DRA7XX_CM_CLKVCOLDO_APLL_PCIE
137485. DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET
137486. DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL
137487. DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET
137488. DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL
137489. DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET
137490. DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET
137491. DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL
137492. DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET
137493. DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL
137494. DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET
137495. DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL
137496. DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET
137497. DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL
137498. DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET
137499. DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL
137500. DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET
137501. DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL
137502. DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET
137503. DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL
137504. DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET
137505. DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL
137506. DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET
137507. DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL
137508. DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET
137509. DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL
137510. DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET
137511. DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL
137512. DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET
137513. DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL
137514. DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET
137515. DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL
137516. DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET
137517. DRA7XX_CM_CORE_AON_BASE
137518. DRA7XX_CM_CORE_AON_CKGEN_INST
137519. DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET
137520. DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET
137521. DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET
137522. DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET
137523. DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET
137524. DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS
137525. DRA7XX_CM_CORE_AON_DSP1_INST
137526. DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS
137527. DRA7XX_CM_CORE_AON_DSP2_INST
137528. DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS
137529. DRA7XX_CM_CORE_AON_EVE1_INST
137530. DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS
137531. DRA7XX_CM_CORE_AON_EVE2_INST
137532. DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS
137533. DRA7XX_CM_CORE_AON_EVE3_INST
137534. DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS
137535. DRA7XX_CM_CORE_AON_EVE4_INST
137536. DRA7XX_CM_CORE_AON_INSTR_INST
137537. DRA7XX_CM_CORE_AON_IPU_INST
137538. DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS
137539. DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS
137540. DRA7XX_CM_CORE_AON_MPU_INST
137541. DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS
137542. DRA7XX_CM_CORE_AON_OCP_SOCKET_INST
137543. DRA7XX_CM_CORE_AON_PARTITION
137544. DRA7XX_CM_CORE_AON_REGADDR
137545. DRA7XX_CM_CORE_AON_RESTORE_INST
137546. DRA7XX_CM_CORE_AON_RTC_INST
137547. DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS
137548. DRA7XX_CM_CORE_AON_VPE_INST
137549. DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS
137550. DRA7XX_CM_CORE_BASE
137551. DRA7XX_CM_CORE_CAM_CAM_CDOFFS
137552. DRA7XX_CM_CORE_CAM_INST
137553. DRA7XX_CM_CORE_CKGEN_INST
137554. DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS
137555. DRA7XX_CM_CORE_COREAON_INST
137556. DRA7XX_CM_CORE_CORE_ATL_CDOFFS
137557. DRA7XX_CM_CORE_CORE_DMA_CDOFFS
137558. DRA7XX_CM_CORE_CORE_EMIF_CDOFFS
137559. DRA7XX_CM_CORE_CORE_INST
137560. DRA7XX_CM_CORE_CORE_IPU2_CDOFFS
137561. DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS
137562. DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS
137563. DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS
137564. DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS
137565. DRA7XX_CM_CORE_CUSTEFUSE_INST
137566. DRA7XX_CM_CORE_DEBUG_CFG_OFFSET
137567. DRA7XX_CM_CORE_DSS_DSS_CDOFFS
137568. DRA7XX_CM_CORE_DSS_INST
137569. DRA7XX_CM_CORE_GPU_GPU_CDOFFS
137570. DRA7XX_CM_CORE_GPU_INST
137571. DRA7XX_CM_CORE_IVA_INST
137572. DRA7XX_CM_CORE_IVA_IVA_CDOFFS
137573. DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS
137574. DRA7XX_CM_CORE_L3INIT_INST
137575. DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS
137576. DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS
137577. DRA7XX_CM_CORE_L4PER_INST
137578. DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS
137579. DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS
137580. DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS
137581. DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS
137582. DRA7XX_CM_CORE_OCP_SOCKET_INST
137583. DRA7XX_CM_CORE_PARTITION
137584. DRA7XX_CM_CORE_REGADDR
137585. DRA7XX_CM_CORE_RESTORE_INST
137586. DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET
137587. DRA7XX_CM_CPU0_CPU0_CLKCTRL
137588. DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET
137589. DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET
137590. DRA7XX_CM_CPU1_CPU1_CLKCTRL
137591. DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET
137592. DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET
137593. DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL
137594. DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET
137595. DRA7XX_CM_DIV_H11_DPLL_CORE
137596. DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET
137597. DRA7XX_CM_DIV_H11_DPLL_DDR
137598. DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET
137599. DRA7XX_CM_DIV_H11_DPLL_GMAC
137600. DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET
137601. DRA7XX_CM_DIV_H11_DPLL_PER
137602. DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET
137603. DRA7XX_CM_DIV_H12_DPLL_CORE
137604. DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET
137605. DRA7XX_CM_DIV_H12_DPLL_GMAC
137606. DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET
137607. DRA7XX_CM_DIV_H12_DPLL_PER
137608. DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET
137609. DRA7XX_CM_DIV_H13_DPLL_CORE
137610. DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET
137611. DRA7XX_CM_DIV_H13_DPLL_GMAC
137612. DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET
137613. DRA7XX_CM_DIV_H13_DPLL_PER
137614. DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET
137615. DRA7XX_CM_DIV_H14_DPLL_CORE
137616. DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET
137617. DRA7XX_CM_DIV_H14_DPLL_GMAC
137618. DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET
137619. DRA7XX_CM_DIV_H14_DPLL_PER
137620. DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET
137621. DRA7XX_CM_DIV_H21_DPLL_CORE
137622. DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET
137623. DRA7XX_CM_DIV_H22_DPLL_CORE
137624. DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET
137625. DRA7XX_CM_DIV_H23_DPLL_CORE
137626. DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET
137627. DRA7XX_CM_DIV_H24_DPLL_CORE
137628. DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET
137629. DRA7XX_CM_DIV_M2_APLL_PCIE
137630. DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET
137631. DRA7XX_CM_DIV_M2_DPLL_ABE
137632. DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET
137633. DRA7XX_CM_DIV_M2_DPLL_CORE
137634. DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET
137635. DRA7XX_CM_DIV_M2_DPLL_DDR
137636. DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET
137637. DRA7XX_CM_DIV_M2_DPLL_DSP
137638. DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET
137639. DRA7XX_CM_DIV_M2_DPLL_EVE
137640. DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET
137641. DRA7XX_CM_DIV_M2_DPLL_GMAC
137642. DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET
137643. DRA7XX_CM_DIV_M2_DPLL_GPU
137644. DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET
137645. DRA7XX_CM_DIV_M2_DPLL_IVA
137646. DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET
137647. DRA7XX_CM_DIV_M2_DPLL_MPU
137648. DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET
137649. DRA7XX_CM_DIV_M2_DPLL_PCIE_REF
137650. DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET
137651. DRA7XX_CM_DIV_M2_DPLL_PER
137652. DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET
137653. DRA7XX_CM_DIV_M2_DPLL_USB
137654. DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET
137655. DRA7XX_CM_DIV_M3_DPLL_ABE
137656. DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET
137657. DRA7XX_CM_DIV_M3_DPLL_CORE
137658. DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET
137659. DRA7XX_CM_DIV_M3_DPLL_DDR
137660. DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET
137661. DRA7XX_CM_DIV_M3_DPLL_DSP
137662. DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET
137663. DRA7XX_CM_DIV_M3_DPLL_EVE
137664. DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET
137665. DRA7XX_CM_DIV_M3_DPLL_GMAC
137666. DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET
137667. DRA7XX_CM_DIV_M3_DPLL_GPU
137668. DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET
137669. DRA7XX_CM_DIV_M3_DPLL_IVA
137670. DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET
137671. DRA7XX_CM_DIV_M3_DPLL_PER
137672. DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET
137673. DRA7XX_CM_DLL_CTRL_OFFSET
137674. DRA7XX_CM_DMA_CLKSTCTRL_OFFSET
137675. DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL
137676. DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
137677. DRA7XX_CM_DMA_DYNAMICDEP_OFFSET
137678. DRA7XX_CM_DMA_STATICDEP_OFFSET
137679. DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET
137680. DRA7XX_CM_DSP1_DSP1_CLKCTRL
137681. DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET
137682. DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET
137683. DRA7XX_CM_DSP1_STATICDEP_OFFSET
137684. DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET
137685. DRA7XX_CM_DSP2_DSP2_CLKCTRL
137686. DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET
137687. DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET
137688. DRA7XX_CM_DSP2_STATICDEP_OFFSET
137689. DRA7XX_CM_DSS_BB2D_CLKCTRL
137690. DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET
137691. DRA7XX_CM_DSS_CLKSTCTRL_OFFSET
137692. DRA7XX_CM_DSS_DSS_CLKCTRL
137693. DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
137694. DRA7XX_CM_DSS_DYNAMICDEP_OFFSET
137695. DRA7XX_CM_DSS_SDVENC_CLKCTRL
137696. DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET
137697. DRA7XX_CM_DSS_STATICDEP_OFFSET
137698. DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET
137699. DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET
137700. DRA7XX_CM_EMIF_DMM_CLKCTRL
137701. DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET
137702. DRA7XX_CM_EMIF_EMIF1_CLKCTRL
137703. DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET
137704. DRA7XX_CM_EMIF_EMIF2_CLKCTRL
137705. DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET
137706. DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL
137707. DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET
137708. DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL
137709. DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET
137710. DRA7XX_CM_EMU_CLKSTCTRL_OFFSET
137711. DRA7XX_CM_EMU_DEBUGSS_CLKCTRL
137712. DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
137713. DRA7XX_CM_EMU_DYNAMICDEP_OFFSET
137714. DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL
137715. DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET
137716. DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET
137717. DRA7XX_CM_EVE1_EVE1_CLKCTRL
137718. DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET
137719. DRA7XX_CM_EVE1_STATICDEP_OFFSET
137720. DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET
137721. DRA7XX_CM_EVE2_EVE2_CLKCTRL
137722. DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET
137723. DRA7XX_CM_EVE2_STATICDEP_OFFSET
137724. DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET
137725. DRA7XX_CM_EVE3_EVE3_CLKCTRL
137726. DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET
137727. DRA7XX_CM_EVE3_STATICDEP_OFFSET
137728. DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET
137729. DRA7XX_CM_EVE4_EVE4_CLKCTRL
137730. DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET
137731. DRA7XX_CM_EVE4_STATICDEP_OFFSET
137732. DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET
137733. DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET
137734. DRA7XX_CM_GMAC_GMAC_CLKCTRL
137735. DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET
137736. DRA7XX_CM_GMAC_STATICDEP_OFFSET
137737. DRA7XX_CM_GPU_CLKSTCTRL_OFFSET
137738. DRA7XX_CM_GPU_DYNAMICDEP_OFFSET
137739. DRA7XX_CM_GPU_GPU_CLKCTRL
137740. DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET
137741. DRA7XX_CM_GPU_STATICDEP_OFFSET
137742. DRA7XX_CM_IDLEST_APLL_PCIE
137743. DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET
137744. DRA7XX_CM_IDLEST_DPLL_ABE
137745. DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET
137746. DRA7XX_CM_IDLEST_DPLL_CORE
137747. DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET
137748. DRA7XX_CM_IDLEST_DPLL_DDR
137749. DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET
137750. DRA7XX_CM_IDLEST_DPLL_DSP
137751. DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET
137752. DRA7XX_CM_IDLEST_DPLL_EVE
137753. DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET
137754. DRA7XX_CM_IDLEST_DPLL_GMAC
137755. DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET
137756. DRA7XX_CM_IDLEST_DPLL_GPU
137757. DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET
137758. DRA7XX_CM_IDLEST_DPLL_IVA
137759. DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET
137760. DRA7XX_CM_IDLEST_DPLL_MPU
137761. DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET
137762. DRA7XX_CM_IDLEST_DPLL_PCIE_REF
137763. DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET
137764. DRA7XX_CM_IDLEST_DPLL_PER
137765. DRA7XX_CM_IDLEST_DPLL_PER_OFFSET
137766. DRA7XX_CM_IDLEST_DPLL_USB
137767. DRA7XX_CM_IDLEST_DPLL_USB_OFFSET
137768. DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET
137769. DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET
137770. DRA7XX_CM_IPU1_IPU1_CLKCTRL
137771. DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET
137772. DRA7XX_CM_IPU1_STATICDEP_OFFSET
137773. DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET
137774. DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET
137775. DRA7XX_CM_IPU2_IPU2_CLKCTRL
137776. DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET
137777. DRA7XX_CM_IPU2_STATICDEP_OFFSET
137778. DRA7XX_CM_IPU_CLKSTCTRL_OFFSET
137779. DRA7XX_CM_IPU_I2C5_CLKCTRL
137780. DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET
137781. DRA7XX_CM_IPU_MCASP1_CLKCTRL
137782. DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET
137783. DRA7XX_CM_IPU_TIMER5_CLKCTRL
137784. DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET
137785. DRA7XX_CM_IPU_TIMER6_CLKCTRL
137786. DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET
137787. DRA7XX_CM_IPU_TIMER7_CLKCTRL
137788. DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET
137789. DRA7XX_CM_IPU_TIMER8_CLKCTRL
137790. DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET
137791. DRA7XX_CM_IPU_UART6_CLKCTRL
137792. DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET
137793. DRA7XX_CM_IVA_CLKSTCTRL_OFFSET
137794. DRA7XX_CM_IVA_DYNAMICDEP_OFFSET
137795. DRA7XX_CM_IVA_IVA_CLKCTRL
137796. DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET
137797. DRA7XX_CM_IVA_SL2_CLKCTRL
137798. DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET
137799. DRA7XX_CM_IVA_STATICDEP_OFFSET
137800. DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET
137801. DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET
137802. DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL
137803. DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET
137804. DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL
137805. DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET
137806. DRA7XX_CM_L3INIT_MMC1_CLKCTRL
137807. DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
137808. DRA7XX_CM_L3INIT_MMC2_CLKCTRL
137809. DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
137810. DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL
137811. DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
137812. DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL
137813. DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET
137814. DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL
137815. DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET
137816. DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL
137817. DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET
137818. DRA7XX_CM_L3INIT_SATA_CLKCTRL
137819. DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET
137820. DRA7XX_CM_L3INIT_STATICDEP_OFFSET
137821. DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL
137822. DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET
137823. DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL
137824. DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET
137825. DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL
137826. DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET
137827. DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL
137828. DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET
137829. DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET
137830. DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL
137831. DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET
137832. DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL
137833. DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET
137834. DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL
137835. DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
137836. DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL
137837. DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET
137838. DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL
137839. DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET
137840. DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET
137841. DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET
137842. DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL
137843. DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET
137844. DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL
137845. DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
137846. DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL
137847. DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET
137848. DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL
137849. DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET
137850. DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL
137851. DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET
137852. DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL
137853. DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET
137854. DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL
137855. DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET
137856. DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL
137857. DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET
137858. DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL
137859. DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET
137860. DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL
137861. DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET
137862. DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL
137863. DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET
137864. DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL
137865. DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET
137866. DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL
137867. DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET
137868. DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL
137869. DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET
137870. DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL
137871. DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET
137872. DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL
137873. DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET
137874. DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL
137875. DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET
137876. DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL
137877. DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET
137878. DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL
137879. DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET
137880. DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL
137881. DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET
137882. DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL
137883. DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET
137884. DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL
137885. DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET
137886. DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL
137887. DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET
137888. DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET
137889. DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET
137890. DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL
137891. DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET
137892. DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL
137893. DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
137894. DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL
137895. DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET
137896. DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL
137897. DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET
137898. DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL
137899. DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET
137900. DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL
137901. DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET
137902. DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL
137903. DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET
137904. DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL
137905. DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET
137906. DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL
137907. DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET
137908. DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL
137909. DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET
137910. DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL
137911. DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET
137912. DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL
137913. DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET
137914. DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL
137915. DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET
137916. DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL
137917. DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET
137918. DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL
137919. DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET
137920. DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL
137921. DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET
137922. DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL
137923. DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET
137924. DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL
137925. DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET
137926. DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL
137927. DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET
137928. DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL
137929. DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET
137930. DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL
137931. DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
137932. DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET
137933. DRA7XX_CM_L4PER2_DCAN2_CLKCTRL
137934. DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET
137935. DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET
137936. DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL
137937. DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET
137938. DRA7XX_CM_L4PER2_MCASP2_CLKCTRL
137939. DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET
137940. DRA7XX_CM_L4PER2_MCASP3_CLKCTRL
137941. DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET
137942. DRA7XX_CM_L4PER2_MCASP4_CLKCTRL
137943. DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET
137944. DRA7XX_CM_L4PER2_MCASP5_CLKCTRL
137945. DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET
137946. DRA7XX_CM_L4PER2_MCASP6_CLKCTRL
137947. DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET
137948. DRA7XX_CM_L4PER2_MCASP7_CLKCTRL
137949. DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET
137950. DRA7XX_CM_L4PER2_MCASP8_CLKCTRL
137951. DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET
137952. DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL
137953. DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET
137954. DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL
137955. DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET
137956. DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL
137957. DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET
137958. DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL
137959. DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET
137960. DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL
137961. DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET
137962. DRA7XX_CM_L4PER2_QSPI_CLKCTRL
137963. DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET
137964. DRA7XX_CM_L4PER2_STATICDEP_OFFSET
137965. DRA7XX_CM_L4PER2_UART7_CLKCTRL
137966. DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET
137967. DRA7XX_CM_L4PER2_UART8_CLKCTRL
137968. DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET
137969. DRA7XX_CM_L4PER2_UART9_CLKCTRL
137970. DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET
137971. DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET
137972. DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET
137973. DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL
137974. DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET
137975. DRA7XX_CM_L4PER3_TIMER13_CLKCTRL
137976. DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET
137977. DRA7XX_CM_L4PER3_TIMER14_CLKCTRL
137978. DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET
137979. DRA7XX_CM_L4PER3_TIMER15_CLKCTRL
137980. DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET
137981. DRA7XX_CM_L4PER3_TIMER16_CLKCTRL
137982. DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET
137983. DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET
137984. DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET
137985. DRA7XX_CM_L4PER_ELM_CLKCTRL
137986. DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET
137987. DRA7XX_CM_L4PER_GPIO2_CLKCTRL
137988. DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
137989. DRA7XX_CM_L4PER_GPIO3_CLKCTRL
137990. DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
137991. DRA7XX_CM_L4PER_GPIO4_CLKCTRL
137992. DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
137993. DRA7XX_CM_L4PER_GPIO5_CLKCTRL
137994. DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
137995. DRA7XX_CM_L4PER_GPIO6_CLKCTRL
137996. DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
137997. DRA7XX_CM_L4PER_GPIO7_CLKCTRL
137998. DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
137999. DRA7XX_CM_L4PER_GPIO8_CLKCTRL
138000. DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
138001. DRA7XX_CM_L4PER_HDQ1W_CLKCTRL
138002. DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
138003. DRA7XX_CM_L4PER_I2C1_CLKCTRL
138004. DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
138005. DRA7XX_CM_L4PER_I2C2_CLKCTRL
138006. DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
138007. DRA7XX_CM_L4PER_I2C3_CLKCTRL
138008. DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
138009. DRA7XX_CM_L4PER_I2C4_CLKCTRL
138010. DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
138011. DRA7XX_CM_L4PER_L4_PER1_CLKCTRL
138012. DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET
138013. DRA7XX_CM_L4PER_MCSPI1_CLKCTRL
138014. DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
138015. DRA7XX_CM_L4PER_MCSPI2_CLKCTRL
138016. DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
138017. DRA7XX_CM_L4PER_MCSPI3_CLKCTRL
138018. DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
138019. DRA7XX_CM_L4PER_MCSPI4_CLKCTRL
138020. DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
138021. DRA7XX_CM_L4PER_MMC3_CLKCTRL
138022. DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
138023. DRA7XX_CM_L4PER_MMC4_CLKCTRL
138024. DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
138025. DRA7XX_CM_L4PER_TIMER10_CLKCTRL
138026. DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
138027. DRA7XX_CM_L4PER_TIMER11_CLKCTRL
138028. DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
138029. DRA7XX_CM_L4PER_TIMER2_CLKCTRL
138030. DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
138031. DRA7XX_CM_L4PER_TIMER3_CLKCTRL
138032. DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
138033. DRA7XX_CM_L4PER_TIMER4_CLKCTRL
138034. DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
138035. DRA7XX_CM_L4PER_TIMER9_CLKCTRL
138036. DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
138037. DRA7XX_CM_L4PER_UART1_CLKCTRL
138038. DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET
138039. DRA7XX_CM_L4PER_UART2_CLKCTRL
138040. DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET
138041. DRA7XX_CM_L4PER_UART3_CLKCTRL
138042. DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET
138043. DRA7XX_CM_L4PER_UART4_CLKCTRL
138044. DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET
138045. DRA7XX_CM_L4PER_UART5_CLKCTRL
138046. DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET
138047. DRA7XX_CM_L4SEC_AES1_CLKCTRL
138048. DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET
138049. DRA7XX_CM_L4SEC_AES2_CLKCTRL
138050. DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET
138051. DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET
138052. DRA7XX_CM_L4SEC_DES3DES_CLKCTRL
138053. DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET
138054. DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL
138055. DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET
138056. DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET
138057. DRA7XX_CM_L4SEC_FPKA_CLKCTRL
138058. DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET
138059. DRA7XX_CM_L4SEC_RNG_CLKCTRL
138060. DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET
138061. DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL
138062. DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET
138063. DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL
138064. DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET
138065. DRA7XX_CM_L4SEC_STATICDEP_OFFSET
138066. DRA7XX_CM_MPU_CLKSTCTRL_OFFSET
138067. DRA7XX_CM_MPU_DYNAMICDEP_OFFSET
138068. DRA7XX_CM_MPU_MPU_CLKCTRL
138069. DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET
138070. DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL
138071. DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET
138072. DRA7XX_CM_MPU_STATICDEP_OFFSET
138073. DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
138074. DRA7XX_CM_PCIE_STATICDEP_OFFSET
138075. DRA7XX_CM_PRM_PROFILING_CLKCTRL
138076. DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET
138077. DRA7XX_CM_RESTORE_ST_OFFSET
138078. DRA7XX_CM_RTC_CLKSTCTRL_OFFSET
138079. DRA7XX_CM_RTC_RTCSS_CLKCTRL
138080. DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET
138081. DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET
138082. DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET
138083. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET
138084. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET
138085. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET
138086. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET
138087. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET
138088. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET
138089. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET
138090. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET
138091. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET
138092. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET
138093. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET
138094. DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET
138095. DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET
138096. DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET
138097. DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET
138098. DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET
138099. DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET
138100. DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET
138101. DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET
138102. DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET
138103. DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET
138104. DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET
138105. DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET
138106. DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET
138107. DRA7XX_CM_VPE_CLKSTCTRL_OFFSET
138108. DRA7XX_CM_VPE_STATICDEP_OFFSET
138109. DRA7XX_CM_VPE_VPE_CLKCTRL
138110. DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET
138111. DRA7XX_CM_WKUPAON_ADC_CLKCTRL
138112. DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET
138113. DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET
138114. DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL
138115. DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
138116. DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL
138117. DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET
138118. DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL
138119. DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
138120. DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL
138121. DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET
138122. DRA7XX_CM_WKUPAON_KBD_CLKCTRL
138123. DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET
138124. DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL
138125. DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
138126. DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL
138127. DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET
138128. DRA7XX_CM_WKUPAON_SCRM_CLKCTRL
138129. DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET
138130. DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL
138131. DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET
138132. DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL
138133. DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET
138134. DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL
138135. DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET
138136. DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL
138137. DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET
138138. DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL
138139. DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET
138140. DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL
138141. DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET
138142. DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL
138143. DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET
138144. DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL
138145. DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
138146. DRA7XX_CM_WKUPAON_UART10_CLKCTRL
138147. DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET
138148. DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL
138149. DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET
138150. DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL
138151. DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
138152. DRA7XX_CORE_IOPAD
138153. DRA7XX_CPU_TO_BUS_ADDR
138154. DRA7XX_CTRL_BASE
138155. DRA7XX_DMA_REQ_START
138156. DRA7XX_DSP1_STATDEP_SHIFT
138157. DRA7XX_DSP2_STATDEP_SHIFT
138158. DRA7XX_DSS_STATDEP_SHIFT
138159. DRA7XX_EMIF_STATDEP_SHIFT
138160. DRA7XX_EVE1_STATDEP_SHIFT
138161. DRA7XX_EVE2_STATDEP_SHIFT
138162. DRA7XX_EVE3_STATDEP_SHIFT
138163. DRA7XX_EVE4_STATDEP_SHIFT
138164. DRA7XX_GMAC_STATDEP_SHIFT
138165. DRA7XX_GPU_STATDEP_SHIFT
138166. DRA7XX_IPU1_STATDEP_SHIFT
138167. DRA7XX_IPU2_STATDEP_SHIFT
138168. DRA7XX_IPU_STATDEP_SHIFT
138169. DRA7XX_IRQ_GIC_START
138170. DRA7XX_IVA_STATDEP_SHIFT
138171. DRA7XX_L3INIT_STATDEP_SHIFT
138172. DRA7XX_L3MAIN1_STATDEP_SHIFT
138173. DRA7XX_L4CFG_STATDEP_SHIFT
138174. DRA7XX_L4PER2_STATDEP_SHIFT
138175. DRA7XX_L4PER3_STATDEP_SHIFT
138176. DRA7XX_L4PER_STATDEP_SHIFT
138177. DRA7XX_L4SEC_STATDEP_SHIFT
138178. DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS
138179. DRA7XX_MPU_PRCM_CM_C0_INST
138180. DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS
138181. DRA7XX_MPU_PRCM_CM_C1_INST
138182. DRA7XX_MPU_PRCM_DEVICE_INST
138183. DRA7XX_MPU_PRCM_OCP_SOCKET_INST
138184. DRA7XX_MPU_PRCM_PARTITION
138185. DRA7XX_MPU_PRCM_PRM_C0_INST
138186. DRA7XX_MPU_PRCM_PRM_C1_INST
138187. DRA7XX_PCIE_STATDEP_SHIFT
138188. DRA7XX_PM_CAM_PWRSTCTRL_OFFSET
138189. DRA7XX_PM_CAM_PWRSTST_OFFSET
138190. DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET
138191. DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET
138192. DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET
138193. DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET
138194. DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET
138195. DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET
138196. DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET
138197. DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET
138198. DRA7XX_PM_CORE_PWRSTCTRL_OFFSET
138199. DRA7XX_PM_CORE_PWRSTST_OFFSET
138200. DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET
138201. DRA7XX_PM_CPU0_PWRSTST_OFFSET
138202. DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET
138203. DRA7XX_PM_CPU1_PWRSTST_OFFSET
138204. DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET
138205. DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET
138206. DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET
138207. DRA7XX_PM_DSP1_PWRSTST_OFFSET
138208. DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET
138209. DRA7XX_PM_DSP2_PWRSTST_OFFSET
138210. DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET
138211. DRA7XX_PM_DSS_DSS_WKDEP_OFFSET
138212. DRA7XX_PM_DSS_PWRSTCTRL_OFFSET
138213. DRA7XX_PM_DSS_PWRSTST_OFFSET
138214. DRA7XX_PM_EMU_PWRSTCTRL_OFFSET
138215. DRA7XX_PM_EMU_PWRSTST_OFFSET
138216. DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET
138217. DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET
138218. DRA7XX_PM_EVE1_PWRSTST_OFFSET
138219. DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET
138220. DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET
138221. DRA7XX_PM_EVE2_PWRSTST_OFFSET
138222. DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET
138223. DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET
138224. DRA7XX_PM_EVE3_PWRSTST_OFFSET
138225. DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET
138226. DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET
138227. DRA7XX_PM_EVE4_PWRSTST_OFFSET
138228. DRA7XX_PM_GPU_PWRSTCTRL_OFFSET
138229. DRA7XX_PM_GPU_PWRSTST_OFFSET
138230. DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET
138231. DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET
138232. DRA7XX_PM_IPU_PWRSTCTRL_OFFSET
138233. DRA7XX_PM_IPU_PWRSTST_OFFSET
138234. DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET
138235. DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET
138236. DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET
138237. DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET
138238. DRA7XX_PM_IPU_UART6_WKDEP_OFFSET
138239. DRA7XX_PM_IVA_PWRSTCTRL_OFFSET
138240. DRA7XX_PM_IVA_PWRSTST_OFFSET
138241. DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET
138242. DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET
138243. DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET
138244. DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET
138245. DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET
138246. DRA7XX_PM_L3INIT_PWRSTST_OFFSET
138247. DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET
138248. DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET
138249. DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET
138250. DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET
138251. DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET
138252. DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET
138253. DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET
138254. DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET
138255. DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET
138256. DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET
138257. DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET
138258. DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET
138259. DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET
138260. DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET
138261. DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET
138262. DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET
138263. DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET
138264. DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET
138265. DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET
138266. DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET
138267. DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET
138268. DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET
138269. DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET
138270. DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET
138271. DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET
138272. DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET
138273. DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET
138274. DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET
138275. DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET
138276. DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET
138277. DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET
138278. DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET
138279. DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET
138280. DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET
138281. DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET
138282. DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET
138283. DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET
138284. DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET
138285. DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET
138286. DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET
138287. DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET
138288. DRA7XX_PM_L4PER_PWRSTST_OFFSET
138289. DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET
138290. DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET
138291. DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET
138292. DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET
138293. DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET
138294. DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET
138295. DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET
138296. DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET
138297. DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET
138298. DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET
138299. DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET
138300. DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET
138301. DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET
138302. DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET
138303. DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET
138304. DRA7XX_PM_MPU_PWRSTCTRL_OFFSET
138305. DRA7XX_PM_MPU_PWRSTST_OFFSET
138306. DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET
138307. DRA7XX_PM_VPE_PWRSTCTRL_OFFSET
138308. DRA7XX_PM_VPE_PWRSTST_OFFSET
138309. DRA7XX_PM_VPE_VPE_WKDEP_OFFSET
138310. DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET
138311. DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET
138312. DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET
138313. DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET
138314. DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET
138315. DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET
138316. DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET
138317. DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET
138318. DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET
138319. DRA7XX_PRCM_MPU_BASE
138320. DRA7XX_PRCM_MPU_REGADDR
138321. DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET
138322. DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET
138323. DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET
138324. DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET
138325. DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET
138326. DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET
138327. DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET
138328. DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET
138329. DRA7XX_PRM_BANDGAP_SETUP_OFFSET
138330. DRA7XX_PRM_BASE
138331. DRA7XX_PRM_CAM_INST
138332. DRA7XX_PRM_CKGEN_INST
138333. DRA7XX_PRM_CLKREQCTRL_OFFSET
138334. DRA7XX_PRM_COREAON_INST
138335. DRA7XX_PRM_CORE_INST
138336. DRA7XX_PRM_CUSTEFUSE_INST
138337. DRA7XX_PRM_DEBUG_CFG1_OFFSET
138338. DRA7XX_PRM_DEBUG_CFG2_OFFSET
138339. DRA7XX_PRM_DEBUG_CFG3_OFFSET
138340. DRA7XX_PRM_DEBUG_OUT_OFFSET
138341. DRA7XX_PRM_DEVICE_INST
138342. DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET
138343. DRA7XX_PRM_DSP1_INST
138344. DRA7XX_PRM_DSP2_INST
138345. DRA7XX_PRM_DSS_INST
138346. DRA7XX_PRM_EMU_CM_EMU_CDOFFS
138347. DRA7XX_PRM_EMU_CM_INST
138348. DRA7XX_PRM_EMU_INST
138349. DRA7XX_PRM_EVE1_INST
138350. DRA7XX_PRM_EVE2_INST
138351. DRA7XX_PRM_EVE3_INST
138352. DRA7XX_PRM_EVE4_INST
138353. DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET
138354. DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET
138355. DRA7XX_PRM_GPU_INST
138356. DRA7XX_PRM_INSTR_INST
138357. DRA7XX_PRM_IO_COUNT_OFFSET
138358. DRA7XX_PRM_IO_PMCTRL_OFFSET
138359. DRA7XX_PRM_IPU_INST
138360. DRA7XX_PRM_IRQENABLE_DSP1_OFFSET
138361. DRA7XX_PRM_IRQENABLE_DSP2_OFFSET
138362. DRA7XX_PRM_IRQENABLE_EVE1_OFFSET
138363. DRA7XX_PRM_IRQENABLE_EVE2_OFFSET
138364. DRA7XX_PRM_IRQENABLE_EVE3_OFFSET
138365. DRA7XX_PRM_IRQENABLE_EVE4_OFFSET
138366. DRA7XX_PRM_IRQENABLE_IPU1_OFFSET
138367. DRA7XX_PRM_IRQENABLE_IPU2_OFFSET
138368. DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET
138369. DRA7XX_PRM_IRQENABLE_MPU_OFFSET
138370. DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET
138371. DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET
138372. DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET
138373. DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET
138374. DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET
138375. DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET
138376. DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET
138377. DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET
138378. DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET
138379. DRA7XX_PRM_IRQSTATUS_MPU_OFFSET
138380. DRA7XX_PRM_IVA_INST
138381. DRA7XX_PRM_L3INIT_INST
138382. DRA7XX_PRM_L4PER_INST
138383. DRA7XX_PRM_MODEM_IF_CTRL_OFFSET
138384. DRA7XX_PRM_MPU_INST
138385. DRA7XX_PRM_OCP_SOCKET_INST
138386. DRA7XX_PRM_PARTITION
138387. DRA7XX_PRM_PHASE1_CNDP_OFFSET
138388. DRA7XX_PRM_PHASE2A_CNDP_OFFSET
138389. DRA7XX_PRM_PHASE2B_CNDP_OFFSET
138390. DRA7XX_PRM_PSCON_COUNT_OFFSET
138391. DRA7XX_PRM_PWRREQCTRL_OFFSET
138392. DRA7XX_PRM_REGADDR
138393. DRA7XX_PRM_RSTCTRL_OFFSET
138394. DRA7XX_PRM_RSTST_OFFSET
138395. DRA7XX_PRM_RSTTIME_OFFSET
138396. DRA7XX_PRM_RTC_INST
138397. DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET
138398. DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET
138399. DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET
138400. DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET
138401. DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET
138402. DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET
138403. DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET
138404. DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET
138405. DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET
138406. DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET
138407. DRA7XX_PRM_SRAM_COUNT_OFFSET
138408. DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET
138409. DRA7XX_PRM_VOLTCTRL_OFFSET
138410. DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET
138411. DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET
138412. DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET
138413. DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET
138414. DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET
138415. DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET
138416. DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET
138417. DRA7XX_PRM_VOLTST_MM_OFFSET
138418. DRA7XX_PRM_VOLTST_MPU_OFFSET
138419. DRA7XX_PRM_VPE_INST
138420. DRA7XX_PRM_WKUPAON_CM_INST
138421. DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS
138422. DRA7XX_PRM_WKUPAON_INST
138423. DRA7XX_REVISION_CM_CORE_AON_OFFSET
138424. DRA7XX_REVISION_CM_CORE_OFFSET
138425. DRA7XX_REVISION_PRCM_MPU_OFFSET
138426. DRA7XX_REVISION_PRM_OFFSET
138427. DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET
138428. DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET
138429. DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET
138430. DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET
138431. DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET
138432. DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET
138433. DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET
138434. DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET
138435. DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET
138436. DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET
138437. DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET
138438. DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET
138439. DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET
138440. DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET
138441. DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET
138442. DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET
138443. DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET
138444. DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET
138445. DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET
138446. DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET
138447. DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET
138448. DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET
138449. DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET
138450. DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
138451. DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET
138452. DRA7XX_RM_DSP1_RSTCTRL_OFFSET
138453. DRA7XX_RM_DSP1_RSTST_OFFSET
138454. DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET
138455. DRA7XX_RM_DSP2_RSTCTRL_OFFSET
138456. DRA7XX_RM_DSP2_RSTST_OFFSET
138457. DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET
138458. DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET
138459. DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET
138460. DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET
138461. DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET
138462. DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET
138463. DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET
138464. DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET
138465. DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET
138466. DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET
138467. DRA7XX_RM_EVE1_RSTCTRL_OFFSET
138468. DRA7XX_RM_EVE1_RSTST_OFFSET
138469. DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET
138470. DRA7XX_RM_EVE2_RSTCTRL_OFFSET
138471. DRA7XX_RM_EVE2_RSTST_OFFSET
138472. DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET
138473. DRA7XX_RM_EVE3_RSTCTRL_OFFSET
138474. DRA7XX_RM_EVE3_RSTST_OFFSET
138475. DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET
138476. DRA7XX_RM_EVE4_RSTCTRL_OFFSET
138477. DRA7XX_RM_EVE4_RSTST_OFFSET
138478. DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET
138479. DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET
138480. DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET
138481. DRA7XX_RM_IPU1_RSTCTRL_OFFSET
138482. DRA7XX_RM_IPU1_RSTST_OFFSET
138483. DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET
138484. DRA7XX_RM_IPU2_RSTCTRL_OFFSET
138485. DRA7XX_RM_IPU2_RSTST_OFFSET
138486. DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET
138487. DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET
138488. DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET
138489. DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET
138490. DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET
138491. DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET
138492. DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET
138493. DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET
138494. DRA7XX_RM_IVA_RSTCTRL_OFFSET
138495. DRA7XX_RM_IVA_RSTST_OFFSET
138496. DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET
138497. DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET
138498. DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET
138499. DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
138500. DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
138501. DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
138502. DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET
138503. DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET
138504. DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET
138505. DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET
138506. DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET
138507. DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET
138508. DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET
138509. DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET
138510. DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET
138511. DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
138512. DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET
138513. DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET
138514. DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET
138515. DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
138516. DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET
138517. DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET
138518. DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET
138519. DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET
138520. DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET
138521. DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET
138522. DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET
138523. DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET
138524. DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET
138525. DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET
138526. DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET
138527. DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET
138528. DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET
138529. DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET
138530. DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET
138531. DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET
138532. DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET
138533. DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET
138534. DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET
138535. DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET
138536. DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET
138537. DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET
138538. DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
138539. DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET
138540. DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET
138541. DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET
138542. DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET
138543. DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET
138544. DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET
138545. DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET
138546. DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET
138547. DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET
138548. DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET
138549. DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET
138550. DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET
138551. DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET
138552. DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET
138553. DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET
138554. DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET
138555. DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET
138556. DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET
138557. DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
138558. DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET
138559. DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET
138560. DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET
138561. DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET
138562. DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET
138563. DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET
138564. DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET
138565. DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET
138566. DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET
138567. DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET
138568. DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET
138569. DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET
138570. DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET
138571. DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET
138572. DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET
138573. DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET
138574. DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET
138575. DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET
138576. DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET
138577. DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET
138578. DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET
138579. DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET
138580. DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET
138581. DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET
138582. DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
138583. DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
138584. DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
138585. DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
138586. DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
138587. DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
138588. DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
138589. DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET
138590. DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET
138591. DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET
138592. DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET
138593. DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET
138594. DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET
138595. DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
138596. DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
138597. DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
138598. DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
138599. DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET
138600. DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET
138601. DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
138602. DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
138603. DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
138604. DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
138605. DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
138606. DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
138607. DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET
138608. DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET
138609. DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET
138610. DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET
138611. DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET
138612. DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET
138613. DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET
138614. DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET
138615. DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET
138616. DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET
138617. DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET
138618. DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET
138619. DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET
138620. DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET
138621. DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET
138622. DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET
138623. DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET
138624. DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
138625. DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET
138626. DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
138627. DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET
138628. DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
138629. DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET
138630. DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET
138631. DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET
138632. DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET
138633. DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET
138634. DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET
138635. DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET
138636. DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET
138637. DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
138638. DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET
138639. DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET
138640. DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
138641. DRA7XX_TAP_BASE
138642. DRA7XX_VPE_STATDEP_SHIFT
138643. DRA7XX_WKUPAON_STATDEP_SHIFT
138644. DRA7_ADC_CLKCTRL
138645. DRA7_AES1_CLKCTRL
138646. DRA7_AES2_CLKCTRL
138647. DRA7_ATL_ATLCR_REG
138648. DRA7_ATL_ATL_CLKCTRL
138649. DRA7_ATL_AWSMUX_REG
138650. DRA7_ATL_BBSR_REG
138651. DRA7_ATL_BWSMUX_REG
138652. DRA7_ATL_CLKCTRL
138653. DRA7_ATL_CLKCTRL_INDEX
138654. DRA7_ATL_CLKCTRL_OFFSET
138655. DRA7_ATL_DIVIDER_MASK
138656. DRA7_ATL_INSTANCES
138657. DRA7_ATL_PCLKMUX
138658. DRA7_ATL_PCLKMUX_REG
138659. DRA7_ATL_PPMR_REG
138660. DRA7_ATL_SWEN
138661. DRA7_ATL_SWEN_REG
138662. DRA7_ATL_WS_MCASP1_FSR
138663. DRA7_ATL_WS_MCASP1_FSX
138664. DRA7_ATL_WS_MCASP2_FSR
138665. DRA7_ATL_WS_MCASP2_FSX
138666. DRA7_ATL_WS_MCASP3_FSX
138667. DRA7_ATL_WS_MCASP4_FSX
138668. DRA7_ATL_WS_MCASP5_FSX
138669. DRA7_ATL_WS_MCASP6_FSX
138670. DRA7_ATL_WS_MCASP7_FSX
138671. DRA7_ATL_WS_MCASP8_AHCLKX
138672. DRA7_ATL_WS_MCASP8_FSX
138673. DRA7_ATL_WS_OSC1_X1
138674. DRA7_ATL_WS_XREF_CLK0
138675. DRA7_ATL_WS_XREF_CLK1
138676. DRA7_ATL_WS_XREF_CLK2
138677. DRA7_ATL_WS_XREF_CLK3
138678. DRA7_BB2D_CLKCTRL
138679. DRA7_CLKCTRL_INDEX
138680. DRA7_CLKCTRL_OFFSET
138681. DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL
138682. DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL
138683. DRA7_COUNTER_32K_CLKCTRL
138684. DRA7_CTRL_CORE_BOOTSTRAP
138685. DRA7_DCAN1_CLKCTRL
138686. DRA7_DCAN2_CLKCTRL
138687. DRA7_DES_CLKCTRL
138688. DRA7_DMA_DMA_SYSTEM_CLKCTRL
138689. DRA7_DMA_SYSTEM_CLKCTRL
138690. DRA7_DMM_CLKCTRL
138691. DRA7_DPLL_GMAC_DEFFREQ
138692. DRA7_DPLL_USB_DEFFREQ
138693. DRA7_DSP1_MMU0_DSP1_CLKCTRL
138694. DRA7_DSP2_MMU0_DSP2_CLKCTRL
138695. DRA7_DSS_BB2D_CLKCTRL
138696. DRA7_DSS_CORE_CLKCTRL
138697. DRA7_DSS_DSS_CORE_CLKCTRL
138698. DRA7_EFUSE_HAS_ALL_MPU_OPP
138699. DRA7_EFUSE_HAS_HIGH_MPU_OPP
138700. DRA7_EFUSE_HAS_OD_MPU_OPP
138701. DRA7_EFUSE_HIGH_MPU_OPP
138702. DRA7_EFUSE_NOM_MPU_OPP
138703. DRA7_EFUSE_OD_MPU_OPP
138704. DRA7_ELM_CLKCTRL
138705. DRA7_EMIF_DMM_CLKCTRL
138706. DRA7_EPWMSS0_CLKCTRL
138707. DRA7_EPWMSS1_CLKCTRL
138708. DRA7_EPWMSS2_CLKCTRL
138709. DRA7_GMAC_CLKCTRL
138710. DRA7_GMAC_CLKCTRL_INDEX
138711. DRA7_GMAC_CLKCTRL_OFFSET
138712. DRA7_GMAC_GMAC_CLKCTRL
138713. DRA7_GPIO1_CLKCTRL
138714. DRA7_GPIO2_CLKCTRL
138715. DRA7_GPIO3_CLKCTRL
138716. DRA7_GPIO4_CLKCTRL
138717. DRA7_GPIO5_CLKCTRL
138718. DRA7_GPIO6_CLKCTRL
138719. DRA7_GPIO7_CLKCTRL
138720. DRA7_GPIO8_CLKCTRL
138721. DRA7_GPMC_CLKCTRL
138722. DRA7_HDQ1W_CLKCTRL
138723. DRA7_I2C1_CLKCTRL
138724. DRA7_I2C2_CLKCTRL
138725. DRA7_I2C3_CLKCTRL
138726. DRA7_I2C4_CLKCTRL
138727. DRA7_I2C5_CLKCTRL
138728. DRA7_IPU1_MMU_IPU1_CLKCTRL
138729. DRA7_IPU2_MMU_IPU2_CLKCTRL
138730. DRA7_IPU_CLKCTRL_INDEX
138731. DRA7_IPU_CLKCTRL_OFFSET
138732. DRA7_IPU_I2C5_CLKCTRL
138733. DRA7_IPU_MCASP1_CLKCTRL
138734. DRA7_IPU_TIMER5_CLKCTRL
138735. DRA7_IPU_TIMER6_CLKCTRL
138736. DRA7_IPU_TIMER7_CLKCTRL
138737. DRA7_IPU_TIMER8_CLKCTRL
138738. DRA7_IPU_UART6_CLKCTRL
138739. DRA7_L3INIT_MMC1_CLKCTRL
138740. DRA7_L3INIT_MMC2_CLKCTRL
138741. DRA7_L3INIT_OCP2SCP1_CLKCTRL
138742. DRA7_L3INIT_OCP2SCP3_CLKCTRL
138743. DRA7_L3INIT_SATA_CLKCTRL
138744. DRA7_L3INIT_USB_OTG_SS1_CLKCTRL
138745. DRA7_L3INIT_USB_OTG_SS2_CLKCTRL
138746. DRA7_L3INIT_USB_OTG_SS3_CLKCTRL
138747. DRA7_L3INIT_USB_OTG_SS4_CLKCTRL
138748. DRA7_L3INSTR_L3_INSTR_CLKCTRL
138749. DRA7_L3INSTR_L3_MAIN_2_CLKCTRL
138750. DRA7_L3MAIN1_GPMC_CLKCTRL
138751. DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL
138752. DRA7_L3MAIN1_TPCC_CLKCTRL
138753. DRA7_L3MAIN1_TPTC0_CLKCTRL
138754. DRA7_L3MAIN1_TPTC1_CLKCTRL
138755. DRA7_L3MAIN1_VCP1_CLKCTRL
138756. DRA7_L3MAIN1_VCP2_CLKCTRL
138757. DRA7_L3_INSTR_CLKCTRL
138758. DRA7_L3_MAIN_1_CLKCTRL
138759. DRA7_L3_MAIN_2_CLKCTRL
138760. DRA7_L4CFG_L4_CFG_CLKCTRL
138761. DRA7_L4CFG_MAILBOX10_CLKCTRL
138762. DRA7_L4CFG_MAILBOX11_CLKCTRL
138763. DRA7_L4CFG_MAILBOX12_CLKCTRL
138764. DRA7_L4CFG_MAILBOX13_CLKCTRL
138765. DRA7_L4CFG_MAILBOX1_CLKCTRL
138766. DRA7_L4CFG_MAILBOX2_CLKCTRL
138767. DRA7_L4CFG_MAILBOX3_CLKCTRL
138768. DRA7_L4CFG_MAILBOX4_CLKCTRL
138769. DRA7_L4CFG_MAILBOX5_CLKCTRL
138770. DRA7_L4CFG_MAILBOX6_CLKCTRL
138771. DRA7_L4CFG_MAILBOX7_CLKCTRL
138772. DRA7_L4CFG_MAILBOX8_CLKCTRL
138773. DRA7_L4CFG_MAILBOX9_CLKCTRL
138774. DRA7_L4CFG_SPINLOCK_CLKCTRL
138775. DRA7_L4PER2_CLKCTRL_INDEX
138776. DRA7_L4PER2_CLKCTRL_OFFSET
138777. DRA7_L4PER2_DCAN2_CLKCTRL
138778. DRA7_L4PER2_EPWMSS0_CLKCTRL
138779. DRA7_L4PER2_EPWMSS1_CLKCTRL
138780. DRA7_L4PER2_EPWMSS2_CLKCTRL
138781. DRA7_L4PER2_L4_PER2_CLKCTRL
138782. DRA7_L4PER2_MCASP2_CLKCTRL
138783. DRA7_L4PER2_MCASP3_CLKCTRL
138784. DRA7_L4PER2_MCASP4_CLKCTRL
138785. DRA7_L4PER2_MCASP5_CLKCTRL
138786. DRA7_L4PER2_MCASP6_CLKCTRL
138787. DRA7_L4PER2_MCASP7_CLKCTRL
138788. DRA7_L4PER2_MCASP8_CLKCTRL
138789. DRA7_L4PER2_PRUSS1_CLKCTRL
138790. DRA7_L4PER2_PRUSS2_CLKCTRL
138791. DRA7_L4PER2_QSPI_CLKCTRL
138792. DRA7_L4PER2_UART7_CLKCTRL
138793. DRA7_L4PER2_UART8_CLKCTRL
138794. DRA7_L4PER2_UART9_CLKCTRL
138795. DRA7_L4PER3_CLKCTRL_INDEX
138796. DRA7_L4PER3_CLKCTRL_OFFSET
138797. DRA7_L4PER3_L4_PER3_CLKCTRL
138798. DRA7_L4PER3_TIMER13_CLKCTRL
138799. DRA7_L4PER3_TIMER14_CLKCTRL
138800. DRA7_L4PER3_TIMER15_CLKCTRL
138801. DRA7_L4PER3_TIMER16_CLKCTRL
138802. DRA7_L4PER_CLKCTRL_INDEX
138803. DRA7_L4PER_CLKCTRL_OFFSET
138804. DRA7_L4PER_ELM_CLKCTRL
138805. DRA7_L4PER_GPIO2_CLKCTRL
138806. DRA7_L4PER_GPIO3_CLKCTRL
138807. DRA7_L4PER_GPIO4_CLKCTRL
138808. DRA7_L4PER_GPIO5_CLKCTRL
138809. DRA7_L4PER_GPIO6_CLKCTRL
138810. DRA7_L4PER_GPIO7_CLKCTRL
138811. DRA7_L4PER_GPIO8_CLKCTRL
138812. DRA7_L4PER_HDQ1W_CLKCTRL
138813. DRA7_L4PER_I2C1_CLKCTRL
138814. DRA7_L4PER_I2C2_CLKCTRL
138815. DRA7_L4PER_I2C3_CLKCTRL
138816. DRA7_L4PER_I2C4_CLKCTRL
138817. DRA7_L4PER_L4_PER1_CLKCTRL
138818. DRA7_L4PER_MCSPI1_CLKCTRL
138819. DRA7_L4PER_MCSPI2_CLKCTRL
138820. DRA7_L4PER_MCSPI3_CLKCTRL
138821. DRA7_L4PER_MCSPI4_CLKCTRL
138822. DRA7_L4PER_MMC3_CLKCTRL
138823. DRA7_L4PER_MMC4_CLKCTRL
138824. DRA7_L4PER_TIMER10_CLKCTRL
138825. DRA7_L4PER_TIMER11_CLKCTRL
138826. DRA7_L4PER_TIMER2_CLKCTRL
138827. DRA7_L4PER_TIMER3_CLKCTRL
138828. DRA7_L4PER_TIMER4_CLKCTRL
138829. DRA7_L4PER_TIMER9_CLKCTRL
138830. DRA7_L4PER_UART1_CLKCTRL
138831. DRA7_L4PER_UART2_CLKCTRL
138832. DRA7_L4PER_UART3_CLKCTRL
138833. DRA7_L4PER_UART4_CLKCTRL
138834. DRA7_L4PER_UART5_CLKCTRL
138835. DRA7_L4SEC_AES1_CLKCTRL
138836. DRA7_L4SEC_AES2_CLKCTRL
138837. DRA7_L4SEC_CLKCTRL_INDEX
138838. DRA7_L4SEC_CLKCTRL_OFFSET
138839. DRA7_L4SEC_DES_CLKCTRL
138840. DRA7_L4SEC_RNG_CLKCTRL
138841. DRA7_L4SEC_SHAM_CLKCTRL
138842. DRA7_L4_CFG_CLKCTRL
138843. DRA7_L4_PER1_CLKCTRL
138844. DRA7_L4_PER2_CLKCTRL
138845. DRA7_L4_PER3_CLKCTRL
138846. DRA7_L4_WKUP_CLKCTRL
138847. DRA7_MAILBOX10_CLKCTRL
138848. DRA7_MAILBOX11_CLKCTRL
138849. DRA7_MAILBOX12_CLKCTRL
138850. DRA7_MAILBOX13_CLKCTRL
138851. DRA7_MAILBOX1_CLKCTRL
138852. DRA7_MAILBOX2_CLKCTRL
138853. DRA7_MAILBOX3_CLKCTRL
138854. DRA7_MAILBOX4_CLKCTRL
138855. DRA7_MAILBOX5_CLKCTRL
138856. DRA7_MAILBOX6_CLKCTRL
138857. DRA7_MAILBOX7_CLKCTRL
138858. DRA7_MAILBOX8_CLKCTRL
138859. DRA7_MAILBOX9_CLKCTRL
138860. DRA7_MCASP1_CLKCTRL
138861. DRA7_MCASP2_CLKCTRL
138862. DRA7_MCASP3_CLKCTRL
138863. DRA7_MCASP4_CLKCTRL
138864. DRA7_MCASP5_CLKCTRL
138865. DRA7_MCASP6_CLKCTRL
138866. DRA7_MCASP7_CLKCTRL
138867. DRA7_MCASP8_CLKCTRL
138868. DRA7_MCSPI1_CLKCTRL
138869. DRA7_MCSPI2_CLKCTRL
138870. DRA7_MCSPI3_CLKCTRL
138871. DRA7_MCSPI4_CLKCTRL
138872. DRA7_MMC1_CLKCTRL
138873. DRA7_MMC2_CLKCTRL
138874. DRA7_MMC3_CLKCTRL
138875. DRA7_MMC4_CLKCTRL
138876. DRA7_MPU_CLKCTRL
138877. DRA7_MPU_MPU_CLKCTRL
138878. DRA7_OCP2SCP1_CLKCTRL
138879. DRA7_OCP2SCP3_CLKCTRL
138880. DRA7_PCIE1_CLKCTRL
138881. DRA7_PCIE2_CLKCTRL
138882. DRA7_PCIE_CLKCTRL_INDEX
138883. DRA7_PCIE_CLKCTRL_OFFSET
138884. DRA7_PCIE_PCIE1_CLKCTRL
138885. DRA7_PCIE_PCIE2_CLKCTRL
138886. DRA7_QSPI_CLKCTRL
138887. DRA7_RNG_CLKCTRL
138888. DRA7_RTCSS_CLKCTRL
138889. DRA7_RTC_CLKCTRL_INDEX
138890. DRA7_RTC_CLKCTRL_OFFSET
138891. DRA7_RTC_RTCSS_CLKCTRL
138892. DRA7_SATA_CLKCTRL
138893. DRA7_SHAM_CLKCTRL
138894. DRA7_SMARTREFLEX_CORE_CLKCTRL
138895. DRA7_SMARTREFLEX_MPU_CLKCTRL
138896. DRA7_SPEEDSELECT_MASK
138897. DRA7_SPINLOCK_CLKCTRL
138898. DRA7_TIMER10_CLKCTRL
138899. DRA7_TIMER11_CLKCTRL
138900. DRA7_TIMER12_CLKCTRL
138901. DRA7_TIMER13_CLKCTRL
138902. DRA7_TIMER14_CLKCTRL
138903. DRA7_TIMER15_CLKCTRL
138904. DRA7_TIMER16_CLKCTRL
138905. DRA7_TIMER1_CLKCTRL
138906. DRA7_TIMER2_CLKCTRL
138907. DRA7_TIMER3_CLKCTRL
138908. DRA7_TIMER4_CLKCTRL
138909. DRA7_TIMER5_CLKCTRL
138910. DRA7_TIMER6_CLKCTRL
138911. DRA7_TIMER7_CLKCTRL
138912. DRA7_TIMER8_CLKCTRL
138913. DRA7_TIMER9_CLKCTRL
138914. DRA7_TPCC_CLKCTRL
138915. DRA7_TPTC0_CLKCTRL
138916. DRA7_TPTC1_CLKCTRL
138917. DRA7_UART10_CLKCTRL
138918. DRA7_UART1_CLKCTRL
138919. DRA7_UART2_CLKCTRL
138920. DRA7_UART3_CLKCTRL
138921. DRA7_UART4_CLKCTRL
138922. DRA7_UART5_CLKCTRL
138923. DRA7_UART6_CLKCTRL
138924. DRA7_UART7_CLKCTRL
138925. DRA7_UART8_CLKCTRL
138926. DRA7_UART9_CLKCTRL
138927. DRA7_USB_OTG_SS1_CLKCTRL
138928. DRA7_USB_OTG_SS2_CLKCTRL
138929. DRA7_USB_OTG_SS3_CLKCTRL
138930. DRA7_USB_OTG_SS4_CLKCTRL
138931. DRA7_VCP1_CLKCTRL
138932. DRA7_VCP2_CLKCTRL
138933. DRA7_WD_TIMER2_CLKCTRL
138934. DRA7_WKUPAON_ADC_CLKCTRL
138935. DRA7_WKUPAON_COUNTER_32K_CLKCTRL
138936. DRA7_WKUPAON_DCAN1_CLKCTRL
138937. DRA7_WKUPAON_GPIO1_CLKCTRL
138938. DRA7_WKUPAON_L4_WKUP_CLKCTRL
138939. DRA7_WKUPAON_TIMER12_CLKCTRL
138940. DRA7_WKUPAON_TIMER1_CLKCTRL
138941. DRA7_WKUPAON_UART10_CLKCTRL
138942. DRA7_WKUPAON_WD_TIMER2_CLKCTRL
138943. DRACK0_B_MARK
138944. DRACK0_C_MARK
138945. DRACK0_MARK
138946. DRACR
138947. DRAGONFLY_JEDEC_ID
138948. DRAGONFLY_V2_JEDEC_ID
138949. DRAINED
138950. DRAIN_CQE
138951. DRAIN_LATENCY_MASK
138952. DRAIN_PIPE
138953. DRAIN_THRESHOLD
138954. DRAK0_MARK
138955. DRAK0_PK1_MARK
138956. DRAK0_PK3_MARK
138957. DRAK1_MARK
138958. DRAK1_PK0_MARK
138959. DRAK1_PK2_MARK
138960. DRAK2_MARK
138961. DRAK3_MARK
138962. DRAM
138963. DRAM0_OFFSET
138964. DRAM0_SIZE
138965. DRAM1_OFFSET
138966. DRAM1_SIZE
138967. DRAMADDRW_COLBIT_MASK
138968. DRAMADDRW_COLBIT_SHIFT
138969. DRAMADDRW_ROWBIT_MASK
138970. DRAMADDRW_ROWBIT_SHIFT
138971. DRAMC
138972. DRAMCH
138973. DRAMCL
138974. DRAMCOMMAND
138975. DRAMC_ADDR
138976. DRAMC_BC_MASK
138977. DRAMC_BC_SHIFT
138978. DRAMC_CLK
138979. DRAMC_DWE
138980. DRAMC_EDO
138981. DRAMC_EN
138982. DRAMC_LPR
138983. DRAMC_LSP
138984. DRAMC_MSW
138985. DRAMC_PGSZ_1024K
138986. DRAMC_PGSZ_2048K
138987. DRAMC_PGSZ_256K
138988. DRAMC_PGSZ_512K
138989. DRAMC_PGSZ_MASK
138990. DRAMC_PGSZ_SHIFT
138991. DRAMC_RM
138992. DRAMC_RST
138993. DRAMC_SLW
138994. DRAMC_WS_MASK
138995. DRAMC_WS_SHIFT
138996. DRAMControl
138997. DRAMDATA
138998. DRAMINIT0
138999. DRAMINIT0_SGRAM_NUM
139000. DRAMINIT0_SGRAM_TYPE
139001. DRAMINIT0_SGRAM_TYPE_MASK
139002. DRAMINIT0_SGRAM_TYPE_SHIFT
139003. DRAMINIT1
139004. DRAMINIT1_MEM_SDRAM
139005. DRAMMC
139006. DRAMMC_ADDR
139007. DRAMMC_COL10
139008. DRAMMC_COL8
139009. DRAMMC_COL9
139010. DRAMMC_REF_MASK
139011. DRAMMC_REF_SHIFT
139012. DRAMMC_ROW0_MASK
139013. DRAMMC_ROW0_PA11
139014. DRAMMC_ROW0_PA22
139015. DRAMMC_ROW0_PA23
139016. DRAMMC_ROW10
139017. DRAMMC_ROW11
139018. DRAMMC_ROW12_MASK
139019. DRAMMC_ROW12_PA10
139020. DRAMMC_ROW12_PA21
139021. DRAMMC_ROW12_PA23
139022. DRAMMC_ROW8
139023. DRAMMC_ROW9
139024. DRAMTiming
139025. DRAM_ADDR_SIZE_0
139026. DRAM_ADDR_SIZE_1
139027. DRAM_ADDR_SIZE_2
139028. DRAM_ADDR_SIZE_3
139029. DRAM_AD_SZ_DEF0
139030. DRAM_AD_SZ_NULL
139031. DRAM_BASE_ADDRESS
139032. DRAM_BASE_ADDR_USER
139033. DRAM_BASE_HI
139034. DRAM_BASE_LO
139035. DRAM_BIT_WIDTH_COUNT
139036. DRAM_BIT_WIDTH_DISABLED
139037. DRAM_BIT_WIDTH_TYPE_e
139038. DRAM_BIT_WIDTH_X_128
139039. DRAM_BIT_WIDTH_X_16
139040. DRAM_BIT_WIDTH_X_32
139041. DRAM_BIT_WIDTH_X_64
139042. DRAM_BIT_WIDTH_X_8
139043. DRAM_CAS_LATENCY
139044. DRAM_CONTROL
139045. DRAM_CONT_BASE
139046. DRAM_CONT_HIGH_OFF
139047. DRAM_CONT_LIMIT
139048. DRAM_DDR_INFO_ERROR
139049. DRAM_DDR_INFO_MASK
139050. DRAM_DDR_INFO_MR4
139051. DRAM_DDR_INFO_MR5
139052. DRAM_DDR_INFO_MR6
139053. DRAM_DDR_INFO_MR7
139054. DRAM_DDR_INFO_MR8
139055. DRAM_DEV_SEL_0
139056. DRAM_DEV_SEL_1
139057. DRAM_DEV_SEL_ALL
139058. DRAM_DRIVER_END_ADDR
139059. DRAM_ENTRY
139060. DRAM_EXT_CNTL
139061. DRAM_INC
139062. DRAM_INFO_ERROR
139063. DRAM_INFO_INTERVAL
139064. DRAM_INFO_MR4
139065. DRAM_INFO_MR4_MASK
139066. DRAM_INFO_MR4_SHIFT
139067. DRAM_LIMIT_HI
139068. DRAM_LIMIT_LO
139069. DRAM_LOCAL_NODE_BASE
139070. DRAM_LOCAL_NODE_LIM
139071. DRAM_LOG_ADDR_H
139072. DRAM_LOG_ADDR_L
139073. DRAM_LOG_BUFF_SIZE
139074. DRAM_LOG_PHY_ADDR_H
139075. DRAM_LOG_PHY_ADDR_L
139076. DRAM_MAX_CODE_SIZE
139077. DRAM_MODE_2
139078. DRAM_MR4_PPRE
139079. DRAM_MR4_PPRE_MASK
139080. DRAM_MR4_REFRESH
139081. DRAM_MR4_REFRESH_MASK
139082. DRAM_MR4_SR_ABORT
139083. DRAM_MR4_SR_ABORT_MASK
139084. DRAM_MR4_TH_OFFS
139085. DRAM_MR4_TH_OFFS_MASK
139086. DRAM_MR4_TUF
139087. DRAM_MR4_TUF_MASK
139088. DRAM_MSG_ADDR_MASK
139089. DRAM_MSG_ADDR_OFFSET
139090. DRAM_MSG_TYPE_MASK
139091. DRAM_MSG_TYPE_OFFSET
139092. DRAM_OFF
139093. DRAM_OFFSET
139094. DRAM_ON
139095. DRAM_PADS_POWERDOWN
139096. DRAM_PHYS_BASE
139097. DRAM_PHYS_DEFAULT_SIZE
139098. DRAM_PLL
139099. DRAM_RANGES
139100. DRAM_RAS_PRECHARGE
139101. DRAM_RAS_TIMING
139102. DRAM_REFRESH_16
139103. DRAM_REFRESH_60HZ
139104. DRAM_REFRESH_DISABLE
139105. DRAM_REFRESH_FAST_TEST
139106. DRAM_REFRESH_RATE
139107. DRAM_REFRESH_RESERVED
139108. DRAM_ROW_0
139109. DRAM_ROW_0_EMPTY
139110. DRAM_ROW_0_SDRAM
139111. DRAM_ROW_1
139112. DRAM_ROW_1_EMPTY
139113. DRAM_ROW_1_SDRAM
139114. DRAM_ROW_BNDRY_0
139115. DRAM_ROW_BNDRY_1
139116. DRAM_ROW_CNTL_HI
139117. DRAM_ROW_CNTL_LO
139118. DRAM_ROW_TYPE
139119. DRAM_RULE_ENABLE
139120. DRAM_SELF_REFRESH_GPIO_PINID
139121. DRAM_SIZE
139122. DRAM_SIZE_WORDS
139123. DRAM_START_CODE
139124. DRAM_TIMING
139125. DRAM_TIMING_DEF
139126. DRAM_TYPE_DDR1
139127. DRAM_TYPE_DDR2
139128. DRAM_TYPE_DDR3
139129. DRAM_TYPE_LPDDR3
139130. DRAM_TYPE_MT7628_MASK
139131. DRAM_TYPE_STR
139132. DRAM_VENDOR_ERROR
139133. DRAM_VENDOR_MASK
139134. DRAM_VENDOR_MR5
139135. DRAM_VENDOR_MR6
139136. DRAM_VENDOR_MR7
139137. DRAM_VENDOR_MR8
139138. DRAM_VENDOR_SHIFT
139139. DRAM_WRITE_CONTROL
139140. DRAM_global
139141. DRAMx16
139142. DRAMx4
139143. DRAWER
139144. DRAWFL
139145. DRAW_DONE
139146. DRAW_LINE_POINT
139147. DRA_MASK
139148. DRBAR
139149. DRBD_ADM_NEED_CONNECTION
139150. DRBD_ADM_NEED_MINOR
139151. DRBD_ADM_NEED_RESOURCE
139152. DRBD_AFTER_SB_0P_DEF
139153. DRBD_AFTER_SB_1P_DEF
139154. DRBD_AFTER_SB_2P_DEF
139155. DRBD_ALLOW_TWO_PRIMARIES_DEF
139156. DRBD_ALWAYS_ASBP_DEF
139157. DRBD_AL_EXTENTS_DEF
139158. DRBD_AL_EXTENTS_MAX
139159. DRBD_AL_EXTENTS_MIN
139160. DRBD_AL_EXTENTS_SCALE
139161. DRBD_AL_MAGIC
139162. DRBD_AL_STRIPES_DEF
139163. DRBD_AL_STRIPES_MAX
139164. DRBD_AL_STRIPES_MIN
139165. DRBD_AL_STRIPES_SCALE
139166. DRBD_AL_STRIPE_SIZE_DEF
139167. DRBD_AL_STRIPE_SIZE_MAX
139168. DRBD_AL_STRIPE_SIZE_MIN
139169. DRBD_AL_STRIPE_SIZE_SCALE
139170. DRBD_AL_UPDATES_DEF
139171. DRBD_CONG_EXTENTS_DEF
139172. DRBD_CONG_EXTENTS_MAX
139173. DRBD_CONG_EXTENTS_MIN
139174. DRBD_CONG_EXTENTS_SCALE
139175. DRBD_CONG_FILL_DEF
139176. DRBD_CONG_FILL_MAX
139177. DRBD_CONG_FILL_MIN
139178. DRBD_CONG_FILL_SCALE
139179. DRBD_CONNECT_INT_DEF
139180. DRBD_CONNECT_INT_MAX
139181. DRBD_CONNECT_INT_MIN
139182. DRBD_CONNECT_INT_SCALE
139183. DRBD_CPU_MASK_SIZE
139184. DRBD_CSUMS_AFTER_CRASH_ONLY_DEF
139185. DRBD_C_DELAY_TARGET_DEF
139186. DRBD_C_DELAY_TARGET_MAX
139187. DRBD_C_DELAY_TARGET_MIN
139188. DRBD_C_DELAY_TARGET_SCALE
139189. DRBD_C_FILL_TARGET_DEF
139190. DRBD_C_FILL_TARGET_MAX
139191. DRBD_C_FILL_TARGET_MIN
139192. DRBD_C_FILL_TARGET_SCALE
139193. DRBD_C_MAX_RATE_DEF
139194. DRBD_C_MAX_RATE_MAX
139195. DRBD_C_MAX_RATE_MIN
139196. DRBD_C_MAX_RATE_SCALE
139197. DRBD_C_MIN_RATE_DEF
139198. DRBD_C_MIN_RATE_MAX
139199. DRBD_C_MIN_RATE_MIN
139200. DRBD_C_MIN_RATE_SCALE
139201. DRBD_C_PLAN_AHEAD_DEF
139202. DRBD_C_PLAN_AHEAD_MAX
139203. DRBD_C_PLAN_AHEAD_MIN
139204. DRBD_C_PLAN_AHEAD_SCALE
139205. DRBD_DEGR_WFC_TIMEOUT_DEF
139206. DRBD_DEGR_WFC_TIMEOUT_MAX
139207. DRBD_DEGR_WFC_TIMEOUT_MIN
139208. DRBD_DEGR_WFC_TIMEOUT_SCALE
139209. DRBD_DEVICE_WORK_MASK
139210. DRBD_DIALOG_REFRESH_MAX
139211. DRBD_DIALOG_REFRESH_MIN
139212. DRBD_DIALOG_REFRESH_SCALE
139213. DRBD_DISABLE_WRITE_SAME_DEF
139214. DRBD_DISCARD_ZEROES_IF_ALIGNED_DEF
139215. DRBD_DISK_BARRIER_DEF
139216. DRBD_DISK_DRAIN_DEF
139217. DRBD_DISK_FLUSHES_DEF
139218. DRBD_DISK_SIZE_DEF
139219. DRBD_DISK_SIZE_MAX
139220. DRBD_DISK_SIZE_MIN
139221. DRBD_DISK_SIZE_SCALE
139222. DRBD_DISK_TIMEOUT_DEF
139223. DRBD_DISK_TIMEOUT_MAX
139224. DRBD_DISK_TIMEOUT_MIN
139225. DRBD_DISK_TIMEOUT_SCALE
139226. DRBD_END_OF_BITMAP
139227. DRBD_FAULT_AL_EE
139228. DRBD_FAULT_BM_ALLOC
139229. DRBD_FAULT_DT_RA
139230. DRBD_FAULT_DT_RD
139231. DRBD_FAULT_DT_WR
139232. DRBD_FAULT_MAX
139233. DRBD_FAULT_MD_RD
139234. DRBD_FAULT_MD_WR
139235. DRBD_FAULT_RECEIVE
139236. DRBD_FAULT_RS_RD
139237. DRBD_FAULT_RS_WR
139238. DRBD_FENCING_DEF
139239. DRBD_FF_THIN_RESYNC
139240. DRBD_FF_TRIM
139241. DRBD_FF_WSAME
139242. DRBD_FF_WZEROES
139243. DRBD_FORCE_DETACH
139244. DRBD_F_INVARIANT
139245. DRBD_F_REQUIRED
139246. DRBD_F_SENSITIVE
139247. DRBD_GENLA_F_MANDATORY
139248. DRBD_GENL_F_SET_DEFAULTS
139249. DRBD_GENL_STRUCT_H
139250. DRBD_H
139251. DRBD_KO_COUNT_DEF
139252. DRBD_KO_COUNT_MAX
139253. DRBD_KO_COUNT_MIN
139254. DRBD_KO_COUNT_SCALE
139255. DRBD_LIMITS_H
139256. DRBD_MAGIC
139257. DRBD_MAGIC_100
139258. DRBD_MAGIC_BIG
139259. DRBD_MAJOR
139260. DRBD_MAX_BATCH_BIO_SIZE
139261. DRBD_MAX_BBIO_SECTORS
139262. DRBD_MAX_BIO_BVECS_DEF
139263. DRBD_MAX_BIO_BVECS_MAX
139264. DRBD_MAX_BIO_BVECS_MIN
139265. DRBD_MAX_BIO_BVECS_SCALE
139266. DRBD_MAX_BIO_SIZE
139267. DRBD_MAX_BIO_SIZE_P95
139268. DRBD_MAX_BIO_SIZE_SAFE
139269. DRBD_MAX_BUFFERS_DEF
139270. DRBD_MAX_BUFFERS_MAX
139271. DRBD_MAX_BUFFERS_MIN
139272. DRBD_MAX_BUFFERS_SCALE
139273. DRBD_MAX_EPOCH_SIZE_DEF
139274. DRBD_MAX_EPOCH_SIZE_MAX
139275. DRBD_MAX_EPOCH_SIZE_MIN
139276. DRBD_MAX_EPOCH_SIZE_SCALE
139277. DRBD_MAX_SECTORS
139278. DRBD_MAX_SECTORS_32
139279. DRBD_MAX_SECTORS_FIXED_BM
139280. DRBD_MAX_SECTORS_FLEX
139281. DRBD_MAX_SIZE_H80_PACKET
139282. DRBD_MD_FLUSHES_DEF
139283. DRBD_MD_INDEX_FLEX_EXT
139284. DRBD_MD_INDEX_FLEX_INT
139285. DRBD_MD_INDEX_INTERNAL
139286. DRBD_MD_MAGIC_07
139287. DRBD_MD_MAGIC_08
139288. DRBD_MD_MAGIC_84_UNCLEAN
139289. DRBD_META_IO_ERROR
139290. DRBD_MINOR_COUNT_DEF
139291. DRBD_MINOR_COUNT_MAX
139292. DRBD_MINOR_COUNT_MIN
139293. DRBD_MINOR_COUNT_SCALE
139294. DRBD_MINOR_NUMBER_DEF
139295. DRBD_MINOR_NUMBER_MAX
139296. DRBD_MINOR_NUMBER_MIN
139297. DRBD_MINOR_NUMBER_SCALE
139298. DRBD_MIN_POOL_PAGES
139299. DRBD_ON_CONGESTION_DEF
139300. DRBD_ON_IO_ERROR_DEF
139301. DRBD_ON_NO_DATA_DEF
139302. DRBD_OUTDATED_WFC_TIMEOUT_DEF
139303. DRBD_OUTDATED_WFC_TIMEOUT_MAX
139304. DRBD_OUTDATED_WFC_TIMEOUT_MIN
139305. DRBD_OUTDATED_WFC_TIMEOUT_SCALE
139306. DRBD_PING_INT_DEF
139307. DRBD_PING_INT_MAX
139308. DRBD_PING_INT_MIN
139309. DRBD_PING_INT_SCALE
139310. DRBD_PING_TIMEO_DEF
139311. DRBD_PING_TIMEO_MAX
139312. DRBD_PING_TIMEO_MIN
139313. DRBD_PING_TIMEO_SCALE
139314. DRBD_PORT_MAX
139315. DRBD_PORT_MIN
139316. DRBD_PORT_SCALE
139317. DRBD_PROTOCOL_DEF
139318. DRBD_PROT_A
139319. DRBD_PROT_B
139320. DRBD_PROT_C
139321. DRBD_RCVBUF_SIZE_DEF
139322. DRBD_RCVBUF_SIZE_MAX
139323. DRBD_RCVBUF_SIZE_MIN
139324. DRBD_RCVBUF_SIZE_SCALE
139325. DRBD_READ_BALANCING_DEF
139326. DRBD_READ_ERROR
139327. DRBD_RESYNC_RATE_DEF
139328. DRBD_RESYNC_RATE_MAX
139329. DRBD_RESYNC_RATE_MIN
139330. DRBD_RESYNC_RATE_SCALE
139331. DRBD_RR_CONFLICT_DEF
139332. DRBD_RS_DISCARD_GRANULARITY_DEF
139333. DRBD_RS_DISCARD_GRANULARITY_MAX
139334. DRBD_RS_DISCARD_GRANULARITY_MIN
139335. DRBD_RS_DISCARD_GRANULARITY_SCALE
139336. DRBD_SIGKILL
139337. DRBD_SNDBUF_SIZE_DEF
139338. DRBD_SNDBUF_SIZE_MAX
139339. DRBD_SNDBUF_SIZE_MIN
139340. DRBD_SNDBUF_SIZE_SCALE
139341. DRBD_SOCKET_BUFFER_SIZE
139342. DRBD_SOCKET_CHECK_TIMEO_DEF
139343. DRBD_SOCKET_CHECK_TIMEO_MAX
139344. DRBD_SOCKET_CHECK_TIMEO_MIN
139345. DRBD_SOCKET_CHECK_TIMEO_SCALE
139346. DRBD_STATE_CHANGE_H
139347. DRBD_STATE_H
139348. DRBD_SYNC_MARKS
139349. DRBD_SYNC_MARK_STEP
139350. DRBD_TCP_CORK_DEF
139351. DRBD_THREAD_DETAILS_HIST
139352. DRBD_TIMEOUT_DEF
139353. DRBD_TIMEOUT_MAX
139354. DRBD_TIMEOUT_MIN
139355. DRBD_TIMEOUT_SCALE
139356. DRBD_UNPLUG_WATERMARK_DEF
139357. DRBD_UNPLUG_WATERMARK_MAX
139358. DRBD_UNPLUG_WATERMARK_MIN
139359. DRBD_UNPLUG_WATERMARK_SCALE
139360. DRBD_USE_RLE_DEF
139361. DRBD_VOLUME_MAX
139362. DRBD_WFC_TIMEOUT_DEF
139363. DRBD_WFC_TIMEOUT_MAX
139364. DRBD_WFC_TIMEOUT_MIN
139365. DRBD_WFC_TIMEOUT_SCALE
139366. DRBD_WRITE_ERROR
139367. DRBG_CTR
139368. DRBG_HASH
139369. DRBG_HMAC
139370. DRBG_OUTSCRATCHLEN
139371. DRBG_PREFIX0
139372. DRBG_PREFIX1
139373. DRBG_PREFIX2
139374. DRBG_PREFIX3
139375. DRBG_STRENGTH128
139376. DRBG_STRENGTH192
139377. DRBG_STRENGTH256
139378. DRBG_STRENGTH_MASK
139379. DRBG_TYPE_MASK
139380. DRBL_BUS_CHANGE
139381. DRBL_DATA_ABORT
139382. DRBL_DRV_VER
139383. DRBL_DRV_VER_1
139384. DRBL_ENB_MASK
139385. DRBL_EVENT_NOTIFY
139386. DRBL_FLASH_DONE
139387. DRBL_FLASH_REQ
139388. DRBL_FORCE_INT
139389. DRBL_FW_RESET
139390. DRBL_FW_VER
139391. DRBL_FW_VER_0
139392. DRBL_FW_VER_1
139393. DRBL_FW_VER_MSK
139394. DRBL_HANDSHAKE
139395. DRBL_HANDSHAKE_ISR
139396. DRBL_JUMP_TO_ZERO
139397. DRBL_MSG_IFC_DOWN
139398. DRBL_MSG_IFC_INIT
139399. DRBL_MU_RESET
139400. DRBL_PANIC_REASON_MASK
139401. DRBL_PAUSE_AE
139402. DRBL_POWER_DOWN
139403. DRBL_PREFETCH_ABORT
139404. DRBL_RESET_BUS
139405. DRBL_RESUME_AE
139406. DRBL_SOFT_RESET
139407. DRBL_UNDEF_INSTR
139408. DRBL_UNUSED_HANDLER
139409. DRCAPTURE
139410. DRCI_COMMAND
139411. DRCI_READ_REQ
139412. DRCI_REG_BASE
139413. DRCI_REG_HASH_TBL0
139414. DRCI_REG_HASH_TBL1
139415. DRCI_REG_HASH_TBL2
139416. DRCI_REG_HASH_TBL3
139417. DRCI_REG_HW_ADDR_HI
139418. DRCI_REG_HW_ADDR_LO
139419. DRCI_REG_HW_ADDR_MI
139420. DRCI_REG_MEP_FILTER
139421. DRCI_REG_NI_STATE
139422. DRCI_REG_NODE_ADDR
139423. DRCI_REG_NODE_POS
139424. DRCI_REG_PACKET_BW
139425. DRCI_WRITE_REQ
139426. DRCMR
139427. DRCMR_CHLNUM
139428. DRCMR_MAPVLD
139429. DRCONF_MEM_AI_INVALID
139430. DRCONF_MEM_ASSIGNED
139431. DRCONF_MEM_RESERVED
139432. DRCT_ACCESS_DEV
139433. DRCVBC
139434. DRCVPA
139435. DRDELAY
139436. DRDYE
139437. DRDY_DRV
139438. DRDY_OTHER
139439. DRDY_OWN
139440. DRD_CONFIG_DYNAMIC
139441. DRD_CONFIG_MASK
139442. DRD_CONFIG_STATIC_DEVICE
139443. DRD_CONFIG_STATIC_HOST
139444. DRD_CON_PERI_CON
139445. DRD_CON_VBOUT
139446. DRD_DEVICE_MODE
139447. DRD_DEV_MODE
139448. DRD_DEV_VAL
139449. DRD_DUAL_IO_MODE
139450. DRD_HOST_MODE
139451. DRD_HOST_VAL
139452. DRD_QUAD_IO_MODE
139453. DRD_SINGLE_WIRE_MODE
139454. DRD_SPI_X_MODE
139455. DREAM_CHEEKY
139456. DREF_CONTROL_MASK
139457. DREF_CPU_SOURCE_OUTPUT_DISABLE
139458. DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
139459. DREF_CPU_SOURCE_OUTPUT_MASK
139460. DREF_CPU_SOURCE_OUTPUT_NONSPREAD
139461. DREF_NONSPREAD_CK505_ENABLE
139462. DREF_NONSPREAD_SOURCE_DISABLE
139463. DREF_NONSPREAD_SOURCE_ENABLE
139464. DREF_NONSPREAD_SOURCE_MASK
139465. DREF_SSC1_DISABLE
139466. DREF_SSC1_ENABLE
139467. DREF_SSC4_CENTERSPREAD
139468. DREF_SSC4_DISABLE
139469. DREF_SSC4_DOWNSPREAD
139470. DREF_SSC4_ENABLE
139471. DREF_SSC_SOURCE_DISABLE
139472. DREF_SSC_SOURCE_ENABLE
139473. DREF_SSC_SOURCE_MASK
139474. DREF_SUPERSPREAD_SOURCE_DISABLE
139475. DREF_SUPERSPREAD_SOURCE_ENABLE
139476. DREF_SUPERSPREAD_SOURCE_MASK
139477. DREG
139478. DREG32
139479. DREG32_SYS
139480. DREG_DEBUG
139481. DREG_REGID_CPU_STATUS
139482. DREG_REGID_CURRENT_DMA_STREAM
139483. DREG_REGID_DMA_STATE
139484. DREG_REGID_DMA_STATE_0_3
139485. DREG_REGID_DMA_STATE_12_15
139486. DREG_REGID_DMA_STATE_16_19
139487. DREG_REGID_DMA_STATE_20_23
139488. DREG_REGID_DMA_STATE_24_27
139489. DREG_REGID_DMA_STATE_28_31
139490. DREG_REGID_DMA_STATE_32_35
139491. DREG_REGID_DMA_STATE_36_39
139492. DREG_REGID_DMA_STATE_40_43
139493. DREG_REGID_DMA_STATE_44_47
139494. DREG_REGID_DMA_STATE_48_51
139495. DREG_REGID_DMA_STATE_4_7
139496. DREG_REGID_DMA_STATE_52_55
139497. DREG_REGID_DMA_STATE_56_59
139498. DREG_REGID_DMA_STATE_60_63
139499. DREG_REGID_DMA_STATE_64_67
139500. DREG_REGID_DMA_STATE_68_71
139501. DREG_REGID_DMA_STATE_72_75
139502. DREG_REGID_DMA_STATE_76_79
139503. DREG_REGID_DMA_STATE_80_83
139504. DREG_REGID_DMA_STATE_84_87
139505. DREG_REGID_DMA_STATE_88_91
139506. DREG_REGID_DMA_STATE_8_11
139507. DREG_REGID_DMA_STATE_92_95
139508. DREG_REGID_INDEX0
139509. DREG_REGID_INDEX1
139510. DREG_REGID_INDIRECT_ADDRESS
139511. DREG_REGID_MAC0_ACC0_HIGH
139512. DREG_REGID_MAC0_ACC0_LOW
139513. DREG_REGID_MAC0_ACC0_MID
139514. DREG_REGID_MAC0_ACC1_HIGH
139515. DREG_REGID_MAC0_ACC1_LOW
139516. DREG_REGID_MAC0_ACC1_MID
139517. DREG_REGID_MAC0_ACC2_HIGH
139518. DREG_REGID_MAC0_ACC2_LOW
139519. DREG_REGID_MAC0_ACC2_MID
139520. DREG_REGID_MAC0_ACC3_HIGH
139521. DREG_REGID_MAC0_ACC3_LOW
139522. DREG_REGID_MAC0_ACC3_MID
139523. DREG_REGID_MAC1_ACC0_HIGH
139524. DREG_REGID_MAC1_ACC0_LOW
139525. DREG_REGID_MAC1_ACC0_MID
139526. DREG_REGID_MAC1_ACC1_HIGH
139527. DREG_REGID_MAC1_ACC1_LOW
139528. DREG_REGID_MAC1_ACC1_MID
139529. DREG_REGID_MAC1_ACC2_HIGH
139530. DREG_REGID_MAC1_ACC2_LOW
139531. DREG_REGID_MAC1_ACC2_MID
139532. DREG_REGID_MAC1_ACC3_HIGH
139533. DREG_REGID_MAC1_ACC3_LOW
139534. DREG_REGID_MAC1_ACC3_MID
139535. DREG_REGID_MAC_MODE
139536. DREG_REGID_MASK
139537. DREG_REGID_NEXT_DMA_STREAM
139538. DREG_REGID_R0
139539. DREG_REGID_R1
139540. DREG_REGID_R2
139541. DREG_REGID_R3
139542. DREG_REGID_R4
139543. DREG_REGID_R5
139544. DREG_REGID_R6
139545. DREG_REGID_R7
139546. DREG_REGID_R8
139547. DREG_REGID_R9
139548. DREG_REGID_RA
139549. DREG_REGID_RA_BUS_HIGH
139550. DREG_REGID_RA_BUS_LOW
139551. DREG_REGID_RB
139552. DREG_REGID_RC
139553. DREG_REGID_RD
139554. DREG_REGID_RE
139555. DREG_REGID_RF
139556. DREG_REGID_RSA0_HIGH
139557. DREG_REGID_RSA0_LOW
139558. DREG_REGID_RSA1_HIGH
139559. DREG_REGID_RSA1_LOW
139560. DREG_REGID_RSA2
139561. DREG_REGID_RSA3
139562. DREG_REGID_RSCONFIG01_HIGH
139563. DREG_REGID_RSCONFIG01_LOW
139564. DREG_REGID_RSCONFIG23_HIGH
139565. DREG_REGID_RSCONFIG23_LOW
139566. DREG_REGID_RSD0_HIGH
139567. DREG_REGID_RSD0_LOW
139568. DREG_REGID_RSD1_HIGH
139569. DREG_REGID_RSD1_LOW
139570. DREG_REGID_RSD2_HIGH
139571. DREG_REGID_RSD2_LOW
139572. DREG_REGID_RSD3_HIGH
139573. DREG_REGID_RSD3_LOW
139574. DREG_REGID_RSDMA01E
139575. DREG_REGID_RSDMA23E
139576. DREG_REGID_RSHOUT_HIGH
139577. DREG_REGID_RSHOUT_LOW
139578. DREG_REGID_RSHOUT_MID
139579. DREG_REGID_RSI0_HIGH
139580. DREG_REGID_RSI0_LOW
139581. DREG_REGID_RSI1
139582. DREG_REGID_RSI2
139583. DREG_REGID_SAGUSTATUS
139584. DREG_REGID_SHIFT
139585. DREG_REGID_SRAR_HIGH
139586. DREG_REGID_SRAR_LOW
139587. DREG_REGID_STACK_AND_REPEAT
139588. DREG_REGID_TOP_OF_STACK
139589. DREG_REGID_TRAP_0
139590. DREG_REGID_TRAP_1
139591. DREG_REGID_TRAP_10
139592. DREG_REGID_TRAP_11
139593. DREG_REGID_TRAP_12
139594. DREG_REGID_TRAP_13
139595. DREG_REGID_TRAP_14
139596. DREG_REGID_TRAP_15
139597. DREG_REGID_TRAP_16
139598. DREG_REGID_TRAP_17
139599. DREG_REGID_TRAP_18
139600. DREG_REGID_TRAP_19
139601. DREG_REGID_TRAP_2
139602. DREG_REGID_TRAP_20
139603. DREG_REGID_TRAP_21
139604. DREG_REGID_TRAP_22
139605. DREG_REGID_TRAP_23
139606. DREG_REGID_TRAP_3
139607. DREG_REGID_TRAP_4
139608. DREG_REGID_TRAP_5
139609. DREG_REGID_TRAP_6
139610. DREG_REGID_TRAP_7
139611. DREG_REGID_TRAP_8
139612. DREG_REGID_TRAP_9
139613. DREG_REGID_TRAP_SELECT
139614. DREG_REGID_TRAP_WRITE_0
139615. DREG_REGID_TRAP_WRITE_1
139616. DREG_REGID_TRAP_WRITE_10
139617. DREG_REGID_TRAP_WRITE_11
139618. DREG_REGID_TRAP_WRITE_12
139619. DREG_REGID_TRAP_WRITE_13
139620. DREG_REGID_TRAP_WRITE_14
139621. DREG_REGID_TRAP_WRITE_15
139622. DREG_REGID_TRAP_WRITE_16
139623. DREG_REGID_TRAP_WRITE_17
139624. DREG_REGID_TRAP_WRITE_18
139625. DREG_REGID_TRAP_WRITE_19
139626. DREG_REGID_TRAP_WRITE_2
139627. DREG_REGID_TRAP_WRITE_20
139628. DREG_REGID_TRAP_WRITE_21
139629. DREG_REGID_TRAP_WRITE_22
139630. DREG_REGID_TRAP_WRITE_23
139631. DREG_REGID_TRAP_WRITE_3
139632. DREG_REGID_TRAP_WRITE_4
139633. DREG_REGID_TRAP_WRITE_5
139634. DREG_REGID_TRAP_WRITE_6
139635. DREG_REGID_TRAP_WRITE_7
139636. DREG_REGID_TRAP_WRITE_8
139637. DREG_REGID_TRAP_WRITE_9
139638. DREG_REGID_YBUS_HIGH
139639. DREG_REGID_YBUS_LOW
139640. DREG_RGBK_MASK
139641. DREG_RGBK_REGID_MASK
139642. DREG_RGBK_SHIFT
139643. DREG_TRAP
139644. DREG_TRAPX
139645. DREQ0
139646. DREQ0EN
139647. DREQ0_A_MARK
139648. DREQ0_B_MARK
139649. DREQ0_C_MARK
139650. DREQ0_MARK
139651. DREQ0_N_MARK
139652. DREQ0_PD_MARK
139653. DREQ0_PE_MARK
139654. DREQ1_A_MARK
139655. DREQ1_B_MARK
139656. DREQ1_C_MARK
139657. DREQ1_D_MARK
139658. DREQ1_MARK
139659. DREQ1_N_B_MARK
139660. DREQ1_N_MARK
139661. DREQ1_PD_MARK
139662. DREQ1_PE_MARK
139663. DREQ2_A_MARK
139664. DREQ2_B_MARK
139665. DREQ2_C_MARK
139666. DREQ2_MARK
139667. DREQ2_N_MARK
139668. DREQ3_MARK
139669. DREQA
139670. DREQE
139671. DREQPERR_F
139672. DREQPERR_S
139673. DREQPERR_V
139674. DREQWRPERR_F
139675. DREQWRPERR_S
139676. DREQWRPERR_V
139677. DREQ_POLARITY
139678. DRERR
139679. DREXIT1
139680. DREXIT2
139681. DREX_FREQ_CTRL
139682. DREX_FREQ_CTRL0
139683. DREX_FREQ_CTRL1
139684. DRF_SPC2_RESERVATIONS
139685. DRF_SPC2_RESERVATIONS_WITH_ISID
139686. DRF_THRESH
139687. DRI
139688. DRIVE
139689. DRIVE1_02MA
139690. DRIVE1_04MA
139691. DRIVE1_08MA
139692. DRIVE1_10MA
139693. DRIVE2_02MA
139694. DRIVE2_04MA
139695. DRIVE2_08MA
139696. DRIVE2_10MA
139697. DRIVE2_ENABLE
139698. DRIVE3_04MA
139699. DRIVE3_08MA
139700. DRIVE3_12MA
139701. DRIVE3_16MA
139702. DRIVE3_20MA
139703. DRIVE3_24MA
139704. DRIVE3_32MA
139705. DRIVE3_40MA
139706. DRIVE4_02MA
139707. DRIVE4_04MA
139708. DRIVE4_08MA
139709. DRIVE4_10MA
139710. DRIVE6_04MA
139711. DRIVE6_12MA
139712. DRIVE6_19MA
139713. DRIVE6_27MA
139714. DRIVE6_32MA
139715. DRIVE6_MASK
139716. DRIVE7_02MA
139717. DRIVE7_04MA
139718. DRIVE7_06MA
139719. DRIVE7_08MA
139720. DRIVE7_10MA
139721. DRIVE7_12MA
139722. DRIVE7_14MA
139723. DRIVE7_16MA
139724. DRIVER
139725. DRIVERMODE_CODEC_ONLY
139726. DRIVERMODE_NORMAL
139727. DRIVERMSG_NOTIFY
139728. DRIVERNAME
139729. DRIVERNAPI
139730. DRIVERS_ATM_MIDWAY_H
139731. DRIVERS_ATM_uPD98401_H
139732. DRIVERS_ATM_uPD98402_H
139733. DRIVERS_CLK_INGENIC_PM_H
139734. DRIVERS_FSI_MASTER_H
139735. DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
139736. DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_
139737. DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GPIO_REGS_H_
139738. DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_
139739. DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
139740. DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
139741. DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
139742. DRIVERS_PCI_ECAM_H
139743. DRIVERS_PCI_H
139744. DRIVERVERSION
139745. DRIVER_4400
139746. DRIVER_ALIAS
139747. DRIVER_ATM_ENI_H
139748. DRIVER_ATM_HORIZON_H
139749. DRIVER_ATM_IDT77105_H
139750. DRIVER_ATM_SUNI_H
139751. DRIVER_ATM_TONGA_H
139752. DRIVER_ATM_ZATM_H
139753. DRIVER_ATM_ZEPROM_H
139754. DRIVER_ATOMIC
139755. DRIVER_ATTR_IGNORE_LOCKDEP
139756. DRIVER_ATTR_RO
139757. DRIVER_ATTR_RW
139758. DRIVER_ATTR_WO
139759. DRIVER_AUTHOR
139760. DRIVER_AUTHOR2
139761. DRIVER_BUSY
139762. DRIVER_BYTE
139763. DRIVER_CAPS
139764. DRIVER_CARD
139765. DRIVER_CFG80211
139766. DRIVER_DATE
139767. DRIVER_DEBUG
139768. DRIVER_DESC
139769. DRIVER_DESCRIPTION
139770. DRIVER_DESC_DEBUG
139771. DRIVER_DEV_DESC
139772. DRIVER_DISAPPEAR
139773. DRIVER_EARLY_INT_TIME
139774. DRIVER_EARLY_INT_TIME_8723B
139775. DRIVER_EMAIL
139776. DRIVER_ERROR
139777. DRIVER_ERROR_NONE
139778. DRIVER_ERROR_REQ_EINTR
139779. DRIVER_ERROR_REQ_EINVAL
139780. DRIVER_ERROR_REQ_ENOMEM
139781. DRIVER_ERROR_REQ_ENXIO
139782. DRIVER_ERROR_REQ_FAILED
139783. DRIVER_ERROR_REQ_PENDING
139784. DRIVER_ERROR_REQ_TIMEOUT
139785. DRIVER_FLAG
139786. DRIVER_FLAGS_BUSY
139787. DRIVER_FLAGS_CPU
139788. DRIVER_FLAGS_DMA_ACTIVE
139789. DRIVER_FLAGS_DMA_READY
139790. DRIVER_FLAGS_ERROR
139791. DRIVER_FLAGS_FINAL
139792. DRIVER_FLAGS_INIT
139793. DRIVER_FLAGS_MD5
139794. DRIVER_FLAGS_OUTPUT_READY
139795. DRIVER_FLAGS_SG
139796. DRIVER_FLAGS_SHA1
139797. DRIVER_FLAGS_SHA224
139798. DRIVER_FLAGS_SHA256
139799. DRIVER_FLAG_SKIP_ENTRY
139800. DRIVER_FULL_NAME
139801. DRIVER_GEM
139802. DRIVER_H
139803. DRIVER_HARD
139804. DRIVER_HAVE_DMA
139805. DRIVER_HAVE_IRQ
139806. DRIVER_INFO
139807. DRIVER_INVALID
139808. DRIVER_KMS_LEGACY_CONTEXT
139809. DRIVER_LEGACY
139810. DRIVER_LOAD_MSG
139811. DRIVER_LONG
139812. DRIVER_MAJOR
139813. DRIVER_MAJOR_ERROR_CODE
139814. DRIVER_MAJOR_VERSION
139815. DRIVER_MEDIA
139816. DRIVER_MINOR
139817. DRIVER_MINOR_VERSION
139818. DRIVER_MISC_MASK
139819. DRIVER_MODESET
139820. DRIVER_NAME
139821. DRIVER_NAME_SHORT
139822. DRIVER_NORMAL
139823. DRIVER_OK
139824. DRIVER_OUTPUT_CTRL_1
139825. DRIVER_OUTPUT_CTRL_2
139826. DRIVER_PATCHLEVEL
139827. DRIVER_PCI_DMA
139828. DRIVER_PREFIX
139829. DRIVER_PRODUCT_ID
139830. DRIVER_PRODUCT_NUM
139831. DRIVER_RELDATE
139832. DRIVER_RELEASE
139833. DRIVER_RELEASE_VERSION
139834. DRIVER_RENDER
139835. DRIVER_REPLACE_DONGLE
139836. DRIVER_REVISION
139837. DRIVER_RSSI
139838. DRIVER_RX_READY
139839. DRIVER_SENSE
139840. DRIVER_SG
139841. DRIVER_SHORT
139842. DRIVER_SOFT
139843. DRIVER_SPECIFIC_TYPE
139844. DRIVER_STATE
139845. DRIVER_STATE_BUF_LEN
139846. DRIVER_STATE_PRINT
139847. DRIVER_STATE_PRINT_GENERIC
139848. DRIVER_STATE_PRINT_HEX
139849. DRIVER_STATE_PRINT_INT
139850. DRIVER_STATE_PRINT_LHEX
139851. DRIVER_STATE_PRINT_LONG
139852. DRIVER_STATE_PRINT_STR
139853. DRIVER_STAT_LEN
139854. DRIVER_STOP_REQUEST
139855. DRIVER_STRENGTH_100_OHM
139856. DRIVER_STRENGTH_33_OHM
139857. DRIVER_STRENGTH_40_OHM
139858. DRIVER_STRENGTH_50_OHM
139859. DRIVER_STRENGTH_66_OHM
139860. DRIVER_SUB_VERSION
139861. DRIVER_SUPPORT_UA_ENABLE
139862. DRIVER_SWITCH
139863. DRIVER_SYNCOBJ
139864. DRIVER_SYNCOBJ_TIMELINE
139865. DRIVER_TIMEOUT
139866. DRIVER_TIMESTAMP
139867. DRIVER_TP
139868. DRIVER_TXMAP_MASK
139869. DRIVER_TXMAP_SHIFT
139870. DRIVER_TX_READY
139871. DRIVER_TYPE_A
139872. DRIVER_TYPE_B
139873. DRIVER_TYPE_C
139874. DRIVER_TYPE_D
139875. DRIVER_TYPE_DVT
139876. DRIVER_TYPE_MAX
139877. DRIVER_TYPE_MFG
139878. DRIVER_TYPE_PRODUCTION
139879. DRIVER_USE_AGP
139880. DRIVER_VENDOR_ID
139881. DRIVER_VENDOR_NUM
139882. DRIVER_VER
139883. DRIVER_VERSION
139884. DRIVER_VERSION_NUM
139885. DRIVER_WAVEFORM_CTRL
139886. DRIVER_WEXT
139887. DRIVE_CMDS_RESERVED_FOR_FW
139888. DRIVE_CURRENT_0_000_mA_T114
139889. DRIVE_CURRENT_0_400_mA_T114
139890. DRIVE_CURRENT_0_800_mA_T114
139891. DRIVE_CURRENT_10_000_mA_T114
139892. DRIVE_CURRENT_10_125_mA
139893. DRIVE_CURRENT_10_400_mA_T114
139894. DRIVE_CURRENT_10_500_mA
139895. DRIVE_CURRENT_10_800_mA_T114
139896. DRIVE_CURRENT_10_875_mA
139897. DRIVE_CURRENT_11_200_mA_T114
139898. DRIVE_CURRENT_11_250_mA
139899. DRIVE_CURRENT_11_600_mA_T114
139900. DRIVE_CURRENT_11_625_mA
139901. DRIVE_CURRENT_12_000_mA
139902. DRIVE_CURRENT_12_000_mA_T114
139903. DRIVE_CURRENT_12_375_mA
139904. DRIVE_CURRENT_12_400_mA_T114
139905. DRIVE_CURRENT_12_750_mA
139906. DRIVE_CURRENT_12_800_mA_T114
139907. DRIVE_CURRENT_13_125_mA
139908. DRIVE_CURRENT_13_200_mA_T114
139909. DRIVE_CURRENT_13_500_mA
139910. DRIVE_CURRENT_13_600_mA_T114
139911. DRIVE_CURRENT_13_875_mA
139912. DRIVE_CURRENT_14_000_mA_T114
139913. DRIVE_CURRENT_14_250_mA
139914. DRIVE_CURRENT_14_400_mA_T114
139915. DRIVE_CURRENT_14_625_mA
139916. DRIVE_CURRENT_14_800_mA_T114
139917. DRIVE_CURRENT_15_000_mA
139918. DRIVE_CURRENT_15_200_mA_T114
139919. DRIVE_CURRENT_15_375_mA
139920. DRIVE_CURRENT_15_600_mA_T114
139921. DRIVE_CURRENT_15_750_mA
139922. DRIVE_CURRENT_16_000_mA_T114
139923. DRIVE_CURRENT_16_125_mA
139924. DRIVE_CURRENT_16_400_mA_T114
139925. DRIVE_CURRENT_16_500_mA
139926. DRIVE_CURRENT_16_800_mA_T114
139927. DRIVE_CURRENT_16_875_mA
139928. DRIVE_CURRENT_17_200_mA_T114
139929. DRIVE_CURRENT_17_250_mA
139930. DRIVE_CURRENT_17_600_mA_T114
139931. DRIVE_CURRENT_17_625_mA
139932. DRIVE_CURRENT_18_000_mA
139933. DRIVE_CURRENT_18_000_mA_T114
139934. DRIVE_CURRENT_18_375_mA
139935. DRIVE_CURRENT_18_400_mA_T114
139936. DRIVE_CURRENT_18_750_mA
139937. DRIVE_CURRENT_18_800_mA_T114
139938. DRIVE_CURRENT_19_125_mA
139939. DRIVE_CURRENT_19_200_mA_T114
139940. DRIVE_CURRENT_19_500_mA
139941. DRIVE_CURRENT_19_600_mA_T114
139942. DRIVE_CURRENT_19_875_mA
139943. DRIVE_CURRENT_1_200_mA_T114
139944. DRIVE_CURRENT_1_500_mA
139945. DRIVE_CURRENT_1_600_mA_T114
139946. DRIVE_CURRENT_1_875_mA
139947. DRIVE_CURRENT_20_000_mA_T114
139948. DRIVE_CURRENT_20_250_mA
139949. DRIVE_CURRENT_20_400_mA_T114
139950. DRIVE_CURRENT_20_625_mA
139951. DRIVE_CURRENT_20_800_mA_T114
139952. DRIVE_CURRENT_21_000_mA
139953. DRIVE_CURRENT_21_200_mA_T114
139954. DRIVE_CURRENT_21_375_mA
139955. DRIVE_CURRENT_21_600_mA_T114
139956. DRIVE_CURRENT_21_750_mA
139957. DRIVE_CURRENT_22_000_mA_T114
139958. DRIVE_CURRENT_22_125_mA
139959. DRIVE_CURRENT_22_400_mA_T114
139960. DRIVE_CURRENT_22_500_mA
139961. DRIVE_CURRENT_22_800_mA_T114
139962. DRIVE_CURRENT_22_875_mA
139963. DRIVE_CURRENT_23_200_mA_T114
139964. DRIVE_CURRENT_23_250_mA
139965. DRIVE_CURRENT_23_600_mA_T114
139966. DRIVE_CURRENT_23_625_mA
139967. DRIVE_CURRENT_24_000_mA
139968. DRIVE_CURRENT_24_000_mA_T114
139969. DRIVE_CURRENT_24_375_mA
139970. DRIVE_CURRENT_24_400_mA_T114
139971. DRIVE_CURRENT_24_750_mA
139972. DRIVE_CURRENT_24_800_mA_T114
139973. DRIVE_CURRENT_25_200_mA_T114
139974. DRIVE_CURRENT_25_400_mA_T114
139975. DRIVE_CURRENT_25_800_mA_T114
139976. DRIVE_CURRENT_26_200_mA_T114
139977. DRIVE_CURRENT_26_600_mA_T114
139978. DRIVE_CURRENT_27_000_mA_T114
139979. DRIVE_CURRENT_27_400_mA_T114
139980. DRIVE_CURRENT_27_800_mA_T114
139981. DRIVE_CURRENT_28_200_mA_T114
139982. DRIVE_CURRENT_2_000_mA_T114
139983. DRIVE_CURRENT_2_250_mA
139984. DRIVE_CURRENT_2_400_mA_T114
139985. DRIVE_CURRENT_2_625_mA
139986. DRIVE_CURRENT_2_800_mA_T114
139987. DRIVE_CURRENT_3_000_mA
139988. DRIVE_CURRENT_3_200_mA_T114
139989. DRIVE_CURRENT_3_375_mA
139990. DRIVE_CURRENT_3_600_mA_T114
139991. DRIVE_CURRENT_3_750_mA
139992. DRIVE_CURRENT_4_000_mA_T114
139993. DRIVE_CURRENT_4_125_mA
139994. DRIVE_CURRENT_4_400_mA_T114
139995. DRIVE_CURRENT_4_500_mA
139996. DRIVE_CURRENT_4_800_mA_T114
139997. DRIVE_CURRENT_4_875_mA
139998. DRIVE_CURRENT_5_200_mA_T114
139999. DRIVE_CURRENT_5_250_mA
140000. DRIVE_CURRENT_5_600_mA_T114
140001. DRIVE_CURRENT_5_625_mA
140002. DRIVE_CURRENT_6_000_mA
140003. DRIVE_CURRENT_6_000_mA_T114
140004. DRIVE_CURRENT_6_375_mA
140005. DRIVE_CURRENT_6_400_mA_T114
140006. DRIVE_CURRENT_6_750_mA
140007. DRIVE_CURRENT_6_800_mA_T114
140008. DRIVE_CURRENT_7_125_mA
140009. DRIVE_CURRENT_7_200_mA_T114
140010. DRIVE_CURRENT_7_500_mA
140011. DRIVE_CURRENT_7_600_mA_T114
140012. DRIVE_CURRENT_7_875_mA
140013. DRIVE_CURRENT_8_000_mA_T114
140014. DRIVE_CURRENT_8_250_mA
140015. DRIVE_CURRENT_8_400_mA_T114
140016. DRIVE_CURRENT_8_625_mA
140017. DRIVE_CURRENT_8_800_mA_T114
140018. DRIVE_CURRENT_9_000_mA
140019. DRIVE_CURRENT_9_200_mA_T114
140020. DRIVE_CURRENT_9_375_mA
140021. DRIVE_CURRENT_9_600_mA_T114
140022. DRIVE_CURRENT_9_750_mA
140023. DRIVE_CURRENT_LANE0
140024. DRIVE_CURRENT_LANE0_T114
140025. DRIVE_CURRENT_LANE1
140026. DRIVE_CURRENT_LANE1_T114
140027. DRIVE_CURRENT_LANE2
140028. DRIVE_CURRENT_LANE2_T114
140029. DRIVE_CURRENT_LANE3
140030. DRIVE_CURRENT_LANE3_T114
140031. DRIVE_DVDD_BIT_1_0625V
140032. DRIVE_ENABLE
140033. DRIVE_MASK
140034. DRIVE_PRESENT
140035. DRIVE_QUEUE_DEPTH
140036. DRIVE_READY
140037. DRIVE_STRENGTH
140038. DRIVE_STRENGTH_BIT_DEF
140039. DRIVE_STRENGTH_BIT_HI
140040. DRIVE_STRENGTH_BIT_LOW
140041. DRIVE_STRENGTH_BIT_MED
140042. DRIVE_STRENGTH_BIT_MSK
140043. DRIVE_STRENGTH_HI_SHIFT
140044. DRIVE_STRENGTH_LO_SHIFT
140045. DRIVE_STRENGTH_MASK
140046. DRIVE_STRENGTH_SHIFT
140047. DRIVE_TX
140048. DRIVING_TYPE_A
140049. DRIVING_TYPE_A_MASK
140050. DRIVING_TYPE_B
140051. DRIVING_TYPE_B_MASK
140052. DRIVING_TYPE_C
140053. DRIVING_TYPE_C_MASK
140054. DRIVING_TYPE_D
140055. DRIVING_TYPE_D_MASK
140056. DRM
140057. DRMEM_LMB_RESERVED
140058. DRMID
140059. DRM_ADD_COMMAND
140060. DRM_AMDGPU_BO_LIST
140061. DRM_AMDGPU_CS
140062. DRM_AMDGPU_CTX
140063. DRM_AMDGPU_FENCE_TO_HANDLE
140064. DRM_AMDGPU_GEM_CREATE
140065. DRM_AMDGPU_GEM_METADATA
140066. DRM_AMDGPU_GEM_MMAP
140067. DRM_AMDGPU_GEM_OP
140068. DRM_AMDGPU_GEM_USERPTR
140069. DRM_AMDGPU_GEM_VA
140070. DRM_AMDGPU_GEM_WAIT_IDLE
140071. DRM_AMDGPU_INFO
140072. DRM_AMDGPU_SCHED
140073. DRM_AMDGPU_VM
140074. DRM_AMDGPU_WAIT_CS
140075. DRM_AMDGPU_WAIT_FENCES
140076. DRM_ARMADA_GEM_CREATE
140077. DRM_ARMADA_GEM_MMAP
140078. DRM_ARMADA_GEM_PWRITE
140079. DRM_ARMADA_IOCTL_H
140080. DRM_ATI_GART_FB
140081. DRM_ATI_GART_IGP
140082. DRM_ATI_GART_MAIN
140083. DRM_ATI_GART_PCI
140084. DRM_ATI_GART_PCIE
140085. DRM_ATI_PCIGART_H
140086. DRM_ATMEL_HLCDC_H
140087. DRM_ATOMIC_HELPER_H_
140088. DRM_ATOMIC_H_
140089. DRM_ATOMIC_UAPI_H_
140090. DRM_AUTH
140091. DRM_AUX_MINORS
140092. DRM_BLEND_ALPHA_OPAQUE
140093. DRM_BUS_FLAG_DATA_LSB_TO_MSB
140094. DRM_BUS_FLAG_DATA_MSB_TO_LSB
140095. DRM_BUS_FLAG_DE_HIGH
140096. DRM_BUS_FLAG_DE_LOW
140097. DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE
140098. DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
140099. DRM_BUS_FLAG_PIXDATA_NEGEDGE
140100. DRM_BUS_FLAG_PIXDATA_POSEDGE
140101. DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
140102. DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
140103. DRM_BUS_FLAG_SHARP_SIGNALS
140104. DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE
140105. DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
140106. DRM_BUS_FLAG_SYNC_NEGEDGE
140107. DRM_BUS_FLAG_SYNC_POSEDGE
140108. DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
140109. DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE
140110. DRM_CAP_ADDFB2_MODIFIERS
140111. DRM_CAP_ASYNC_PAGE_FLIP
140112. DRM_CAP_CRTC_IN_VBLANK_EVENT
140113. DRM_CAP_CURSOR_HEIGHT
140114. DRM_CAP_CURSOR_WIDTH
140115. DRM_CAP_DUMB_BUFFER
140116. DRM_CAP_DUMB_PREFERRED_DEPTH
140117. DRM_CAP_DUMB_PREFER_SHADOW
140118. DRM_CAP_PAGE_FLIP_TARGET
140119. DRM_CAP_PRIME
140120. DRM_CAP_SYNCOBJ
140121. DRM_CAP_SYNCOBJ_TIMELINE
140122. DRM_CAP_TIMESTAMP_MONOTONIC
140123. DRM_CAP_VBLANK_HIGH_CRTC
140124. DRM_CLIENT_CAP_ASPECT_RATIO
140125. DRM_CLIENT_CAP_ATOMIC
140126. DRM_CLIENT_CAP_STEREO_3D
140127. DRM_CLIENT_CAP_UNIVERSAL_PLANES
140128. DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
140129. DRM_CLIENT_MAX_CLONED_CONNECTORS
140130. DRM_CLOEXEC
140131. DRM_COLOR_ENCODING_MAX
140132. DRM_COLOR_FORMAT_RGB444
140133. DRM_COLOR_FORMAT_YCRCB420
140134. DRM_COLOR_FORMAT_YCRCB422
140135. DRM_COLOR_FORMAT_YCRCB444
140136. DRM_COLOR_LUT_EQUAL_CHANNELS
140137. DRM_COLOR_LUT_NON_DECREASING
140138. DRM_COLOR_RANGE_MAX
140139. DRM_COLOR_YCBCR_BT2020
140140. DRM_COLOR_YCBCR_BT601
140141. DRM_COLOR_YCBCR_BT709
140142. DRM_COLOR_YCBCR_FULL_RANGE
140143. DRM_COLOR_YCBCR_LIMITED_RANGE
140144. DRM_COMMAND_BASE
140145. DRM_COMMAND_END
140146. DRM_COMPONENT_DRIVER
140147. DRM_CONNECTOR_INITIALIZING
140148. DRM_CONNECTOR_MAX_ENCODER
140149. DRM_CONNECTOR_NAME_LEN
140150. DRM_CONNECTOR_POLL_CONNECT
140151. DRM_CONNECTOR_POLL_DISCONNECT
140152. DRM_CONNECTOR_POLL_HPD
140153. DRM_CONNECTOR_REGISTERED
140154. DRM_CONNECTOR_UNREGISTERED
140155. DRM_CORE_IOCTL_COUNT
140156. DRM_CRC_ENTRIES_NR
140157. DRM_CRTC_SEQUENCE_NEXT_ON_MISS
140158. DRM_CRTC_SEQUENCE_RELATIVE
140159. DRM_CURRENTPID
140160. DRM_DAMAGE_HELPER_H_
140161. DRM_DEBUG
140162. DRM_DEBUGFS_ENTRIES
140163. DRM_DEBUG_ATOMIC
140164. DRM_DEBUG_DP
140165. DRM_DEBUG_DRIVER
140166. DRM_DEBUG_DRIVER_RATELIMITED
140167. DRM_DEBUG_KMS
140168. DRM_DEBUG_KMS_RATELIMITED
140169. DRM_DEBUG_LEASE
140170. DRM_DEBUG_PRIME
140171. DRM_DEBUG_PRIME_RATELIMITED
140172. DRM_DEBUG_RATELIMITED
140173. DRM_DEBUG_VBL
140174. DRM_DEV_DEBUG
140175. DRM_DEV_DEBUG_ATOMIC
140176. DRM_DEV_DEBUG_DP
140177. DRM_DEV_DEBUG_DRIVER
140178. DRM_DEV_DEBUG_DRIVER_RATELIMITED
140179. DRM_DEV_DEBUG_KMS
140180. DRM_DEV_DEBUG_KMS_RATELIMITED
140181. DRM_DEV_DEBUG_PRIME
140182. DRM_DEV_DEBUG_PRIME_RATELIMITED
140183. DRM_DEV_DEBUG_RATELIMITED
140184. DRM_DEV_DEBUG_VBL
140185. DRM_DEV_ERROR
140186. DRM_DEV_ERROR_RATELIMITED
140187. DRM_DEV_INFO
140188. DRM_DEV_INFO_ONCE
140189. DRM_DISPLAYID_H
140190. DRM_DISPLAY_MODE_LEN
140191. DRM_DP_DUAL_MODE_HELPER_H
140192. DRM_DP_DUAL_MODE_LSPCON
140193. DRM_DP_DUAL_MODE_NONE
140194. DRM_DP_DUAL_MODE_TYPE1_DVI
140195. DRM_DP_DUAL_MODE_TYPE1_HDMI
140196. DRM_DP_DUAL_MODE_TYPE2_DVI
140197. DRM_DP_DUAL_MODE_TYPE2_HDMI
140198. DRM_DP_DUAL_MODE_UNKNOWN
140199. DRM_DP_MAX_SDP_STREAMS
140200. DRM_DP_SIDEBAND_TX_QUEUED
140201. DRM_DP_SIDEBAND_TX_RX
140202. DRM_DP_SIDEBAND_TX_SENT
140203. DRM_DP_SIDEBAND_TX_START_SEND
140204. DRM_DP_SIDEBAND_TX_TIMEOUT
140205. DRM_DRAWABLE_CLIPRECTS
140206. DRM_DSC_H_
140207. DRM_EDID_DIGITAL_DEPTH_10
140208. DRM_EDID_DIGITAL_DEPTH_12
140209. DRM_EDID_DIGITAL_DEPTH_14
140210. DRM_EDID_DIGITAL_DEPTH_16
140211. DRM_EDID_DIGITAL_DEPTH_6
140212. DRM_EDID_DIGITAL_DEPTH_8
140213. DRM_EDID_DIGITAL_DEPTH_MASK
140214. DRM_EDID_DIGITAL_DEPTH_RSVD
140215. DRM_EDID_DIGITAL_DEPTH_UNDEF
140216. DRM_EDID_DIGITAL_DFP_1_X
140217. DRM_EDID_DIGITAL_TYPE_DP
140218. DRM_EDID_DIGITAL_TYPE_DVI
140219. DRM_EDID_DIGITAL_TYPE_HDMI_A
140220. DRM_EDID_DIGITAL_TYPE_HDMI_B
140221. DRM_EDID_DIGITAL_TYPE_MASK
140222. DRM_EDID_DIGITAL_TYPE_MDDI
140223. DRM_EDID_DIGITAL_TYPE_UNDEF
140224. DRM_EDID_FEATURE_COLOR_MASK
140225. DRM_EDID_FEATURE_DEFAULT_GTF
140226. DRM_EDID_FEATURE_DISPLAY_TYPE
140227. DRM_EDID_FEATURE_PM_ACTIVE_OFF
140228. DRM_EDID_FEATURE_PM_STANDBY
140229. DRM_EDID_FEATURE_PM_SUSPEND
140230. DRM_EDID_FEATURE_PREFERRED_TIMING
140231. DRM_EDID_FEATURE_RGB
140232. DRM_EDID_FEATURE_RGB_YCRCB
140233. DRM_EDID_FEATURE_RGB_YCRCB422
140234. DRM_EDID_FEATURE_RGB_YCRCB444
140235. DRM_EDID_FEATURE_STANDARD_COLOR
140236. DRM_EDID_HDMI_DC_30
140237. DRM_EDID_HDMI_DC_36
140238. DRM_EDID_HDMI_DC_48
140239. DRM_EDID_HDMI_DC_Y444
140240. DRM_EDID_INPUT_BLANK_TO_BLACK
140241. DRM_EDID_INPUT_COMPOSITE_SYNC
140242. DRM_EDID_INPUT_DIGITAL
140243. DRM_EDID_INPUT_SEPARATE_SYNCS
140244. DRM_EDID_INPUT_SERRATION_VSYNC
140245. DRM_EDID_INPUT_SYNC_ON_GREEN
140246. DRM_EDID_INPUT_VIDEO_LEVEL
140247. DRM_EDID_PT_HSYNC_POSITIVE
140248. DRM_EDID_PT_INTERLACED
140249. DRM_EDID_PT_SEPARATE_SYNC
140250. DRM_EDID_PT_STEREO
140251. DRM_EDID_PT_VSYNC_POSITIVE
140252. DRM_EDID_YCBCR420_DC_30
140253. DRM_EDID_YCBCR420_DC_36
140254. DRM_EDID_YCBCR420_DC_48
140255. DRM_EDID_YCBCR420_DC_MASK
140256. DRM_ELD_AUD_SYNCH_DELAY
140257. DRM_ELD_AUD_SYNCH_DELAY_MAX
140258. DRM_ELD_BASELINE_ELD_LEN
140259. DRM_ELD_CEA_EDID_VER_CEA861
140260. DRM_ELD_CEA_EDID_VER_CEA861A
140261. DRM_ELD_CEA_EDID_VER_CEA861BCD
140262. DRM_ELD_CEA_EDID_VER_MASK
140263. DRM_ELD_CEA_EDID_VER_MNL
140264. DRM_ELD_CEA_EDID_VER_NONE
140265. DRM_ELD_CEA_EDID_VER_SHIFT
140266. DRM_ELD_CEA_SAD
140267. DRM_ELD_CONN_TYPE_DP
140268. DRM_ELD_CONN_TYPE_HDMI
140269. DRM_ELD_CONN_TYPE_MASK
140270. DRM_ELD_CONN_TYPE_SHIFT
140271. DRM_ELD_HEADER_BLOCK_SIZE
140272. DRM_ELD_MANUFACTURER_NAME0
140273. DRM_ELD_MANUFACTURER_NAME1
140274. DRM_ELD_MNL_MASK
140275. DRM_ELD_MNL_SHIFT
140276. DRM_ELD_MONITOR_NAME_STRING
140277. DRM_ELD_PORT_ID
140278. DRM_ELD_PORT_ID_LEN
140279. DRM_ELD_PRODUCT_CODE0
140280. DRM_ELD_PRODUCT_CODE1
140281. DRM_ELD_SAD_COUNT_CONN_TYPE
140282. DRM_ELD_SAD_COUNT_MASK
140283. DRM_ELD_SAD_COUNT_SHIFT
140284. DRM_ELD_SPEAKER
140285. DRM_ELD_SPEAKER_FC
140286. DRM_ELD_SPEAKER_FLR
140287. DRM_ELD_SPEAKER_FLRC
140288. DRM_ELD_SPEAKER_LFE
140289. DRM_ELD_SPEAKER_MASK
140290. DRM_ELD_SPEAKER_RC
140291. DRM_ELD_SPEAKER_RLR
140292. DRM_ELD_SPEAKER_RLRC
140293. DRM_ELD_SUPPORTS_AI
140294. DRM_ELD_SUPPORTS_HDCP
140295. DRM_ELD_VER
140296. DRM_ELD_VER_CANNED
140297. DRM_ELD_VER_CEA861D
140298. DRM_ELD_VER_MASK
140299. DRM_ELD_VER_SHIFT
140300. DRM_ENUM_NAME_FN
140301. DRM_ERROR
140302. DRM_ERROR_RATELIMITED
140303. DRM_ETNAVIV_GEM_CPU_FINI
140304. DRM_ETNAVIV_GEM_CPU_PREP
140305. DRM_ETNAVIV_GEM_INFO
140306. DRM_ETNAVIV_GEM_NEW
140307. DRM_ETNAVIV_GEM_SUBMIT
140308. DRM_ETNAVIV_GEM_USERPTR
140309. DRM_ETNAVIV_GEM_WAIT
140310. DRM_ETNAVIV_GET_PARAM
140311. DRM_ETNAVIV_NUM_IOCTLS
140312. DRM_ETNAVIV_PM_QUERY_DOM
140313. DRM_ETNAVIV_PM_QUERY_SIG
140314. DRM_ETNAVIV_WAIT_FENCE
140315. DRM_EVENT_CRTC_SEQUENCE
140316. DRM_EVENT_FLIP_COMPLETE
140317. DRM_EVENT_VBLANK
140318. DRM_EXYNOS_G2D_EVENT
140319. DRM_EXYNOS_G2D_EXEC
140320. DRM_EXYNOS_G2D_GET_VER
140321. DRM_EXYNOS_G2D_SET_CMDLIST
140322. DRM_EXYNOS_GEM_CREATE
140323. DRM_EXYNOS_GEM_GET
140324. DRM_EXYNOS_GEM_MAP
140325. DRM_EXYNOS_IPP_CAP_CONVERT
140326. DRM_EXYNOS_IPP_CAP_CROP
140327. DRM_EXYNOS_IPP_CAP_ROTATE
140328. DRM_EXYNOS_IPP_CAP_SCALE
140329. DRM_EXYNOS_IPP_COMMIT
140330. DRM_EXYNOS_IPP_EVENT
140331. DRM_EXYNOS_IPP_FLAGS
140332. DRM_EXYNOS_IPP_FLAG_EVENT
140333. DRM_EXYNOS_IPP_FLAG_NONBLOCK
140334. DRM_EXYNOS_IPP_FLAG_TEST_ONLY
140335. DRM_EXYNOS_IPP_FORMAT_DESTINATION
140336. DRM_EXYNOS_IPP_FORMAT_SOURCE
140337. DRM_EXYNOS_IPP_GET_CAPS
140338. DRM_EXYNOS_IPP_GET_LIMITS
140339. DRM_EXYNOS_IPP_GET_RESOURCES
140340. DRM_EXYNOS_IPP_LIMIT_SIZE_AREA
140341. DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER
140342. DRM_EXYNOS_IPP_LIMIT_SIZE_MASK
140343. DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED
140344. DRM_EXYNOS_IPP_LIMIT_TYPE_MASK
140345. DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE
140346. DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE
140347. DRM_EXYNOS_IPP_TASK_ALPHA
140348. DRM_EXYNOS_IPP_TASK_ASYNC
140349. DRM_EXYNOS_IPP_TASK_BUFFER
140350. DRM_EXYNOS_IPP_TASK_DONE
140351. DRM_EXYNOS_IPP_TASK_RECTANGLE
140352. DRM_EXYNOS_IPP_TASK_TRANSFORM
140353. DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION
140354. DRM_EXYNOS_IPP_TASK_TYPE_SOURCE
140355. DRM_EXYNOS_VIDI_CONNECTION
140356. DRM_FB_HELPER_DEFAULT_OPS
140357. DRM_FB_HELPER_H
140358. DRM_FILE_PAGE_OFFSET_SIZE
140359. DRM_FILE_PAGE_OFFSET_START
140360. DRM_FIMC_DEVICE
140361. DRM_FIXED_ALMOST_ONE
140362. DRM_FIXED_DECIMAL_MASK
140363. DRM_FIXED_DIGITS_MASK
140364. DRM_FIXED_EPSILON
140365. DRM_FIXED_H
140366. DRM_FIXED_ONE
140367. DRM_FIXED_POINT
140368. DRM_FLIP_WORK_H
140369. DRM_FORCE_OFF
140370. DRM_FORCE_ON
140371. DRM_FORCE_ON_DIGITAL
140372. DRM_FORCE_UNSPECIFIED
140373. DRM_FORMAT_ABGR1555
140374. DRM_FORMAT_ABGR16161616F
140375. DRM_FORMAT_ABGR2101010
140376. DRM_FORMAT_ABGR4444
140377. DRM_FORMAT_ABGR8888
140378. DRM_FORMAT_ARGB1555
140379. DRM_FORMAT_ARGB16161616F
140380. DRM_FORMAT_ARGB2101010
140381. DRM_FORMAT_ARGB4444
140382. DRM_FORMAT_ARGB8888
140383. DRM_FORMAT_AYUV
140384. DRM_FORMAT_BGR233
140385. DRM_FORMAT_BGR565
140386. DRM_FORMAT_BGR565_A8
140387. DRM_FORMAT_BGR888
140388. DRM_FORMAT_BGR888_A8
140389. DRM_FORMAT_BGRA1010102
140390. DRM_FORMAT_BGRA4444
140391. DRM_FORMAT_BGRA5551
140392. DRM_FORMAT_BGRA8888
140393. DRM_FORMAT_BGRX1010102
140394. DRM_FORMAT_BGRX4444
140395. DRM_FORMAT_BGRX5551
140396. DRM_FORMAT_BGRX8888
140397. DRM_FORMAT_BGRX8888_A8
140398. DRM_FORMAT_BIG_ENDIAN
140399. DRM_FORMAT_C8
140400. DRM_FORMAT_GR1616
140401. DRM_FORMAT_GR88
140402. DRM_FORMAT_HOST_ARGB8888
140403. DRM_FORMAT_HOST_RGB565
140404. DRM_FORMAT_HOST_XRGB1555
140405. DRM_FORMAT_HOST_XRGB8888
140406. DRM_FORMAT_INVALID
140407. DRM_FORMAT_MOD_ALLWINNER_TILED
140408. DRM_FORMAT_MOD_ARM_AFBC
140409. DRM_FORMAT_MOD_BROADCOM_SAND128
140410. DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT
140411. DRM_FORMAT_MOD_BROADCOM_SAND256
140412. DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT
140413. DRM_FORMAT_MOD_BROADCOM_SAND32
140414. DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT
140415. DRM_FORMAT_MOD_BROADCOM_SAND64
140416. DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT
140417. DRM_FORMAT_MOD_BROADCOM_UIF
140418. DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED
140419. DRM_FORMAT_MOD_INVALID
140420. DRM_FORMAT_MOD_LINEAR
140421. DRM_FORMAT_MOD_NONE
140422. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK
140423. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB
140424. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB
140425. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB
140426. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB
140427. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB
140428. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB
140429. DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED
140430. DRM_FORMAT_MOD_QCOM_COMPRESSED
140431. DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
140432. DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
140433. DRM_FORMAT_MOD_VENDOR_ALLWINNER
140434. DRM_FORMAT_MOD_VENDOR_AMD
140435. DRM_FORMAT_MOD_VENDOR_ARM
140436. DRM_FORMAT_MOD_VENDOR_BROADCOM
140437. DRM_FORMAT_MOD_VENDOR_INTEL
140438. DRM_FORMAT_MOD_VENDOR_NONE
140439. DRM_FORMAT_MOD_VENDOR_NVIDIA
140440. DRM_FORMAT_MOD_VENDOR_QCOM
140441. DRM_FORMAT_MOD_VENDOR_SAMSUNG
140442. DRM_FORMAT_MOD_VENDOR_VIVANTE
140443. DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED
140444. DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED
140445. DRM_FORMAT_MOD_VIVANTE_SUPER_TILED
140446. DRM_FORMAT_MOD_VIVANTE_TILED
140447. DRM_FORMAT_NV12
140448. DRM_FORMAT_NV16
140449. DRM_FORMAT_NV21
140450. DRM_FORMAT_NV24
140451. DRM_FORMAT_NV42
140452. DRM_FORMAT_NV61
140453. DRM_FORMAT_P010
140454. DRM_FORMAT_P012
140455. DRM_FORMAT_P016
140456. DRM_FORMAT_P210
140457. DRM_FORMAT_R16
140458. DRM_FORMAT_R8
140459. DRM_FORMAT_RESERVED
140460. DRM_FORMAT_RG1616
140461. DRM_FORMAT_RG88
140462. DRM_FORMAT_RGB332
140463. DRM_FORMAT_RGB565
140464. DRM_FORMAT_RGB565_A8
140465. DRM_FORMAT_RGB888
140466. DRM_FORMAT_RGB888_A8
140467. DRM_FORMAT_RGBA1010102
140468. DRM_FORMAT_RGBA4444
140469. DRM_FORMAT_RGBA5551
140470. DRM_FORMAT_RGBA8888
140471. DRM_FORMAT_RGBX1010102
140472. DRM_FORMAT_RGBX4444
140473. DRM_FORMAT_RGBX5551
140474. DRM_FORMAT_RGBX8888
140475. DRM_FORMAT_RGBX8888_A8
140476. DRM_FORMAT_UYVY
140477. DRM_FORMAT_VUY101010
140478. DRM_FORMAT_VUY888
140479. DRM_FORMAT_VYUY
140480. DRM_FORMAT_X0L0
140481. DRM_FORMAT_X0L2
140482. DRM_FORMAT_XBGR1555
140483. DRM_FORMAT_XBGR16161616F
140484. DRM_FORMAT_XBGR2101010
140485. DRM_FORMAT_XBGR4444
140486. DRM_FORMAT_XBGR8888
140487. DRM_FORMAT_XBGR8888_A8
140488. DRM_FORMAT_XRGB1555
140489. DRM_FORMAT_XRGB16161616F
140490. DRM_FORMAT_XRGB2101010
140491. DRM_FORMAT_XRGB4444
140492. DRM_FORMAT_XRGB8888
140493. DRM_FORMAT_XRGB8888_A8
140494. DRM_FORMAT_XVYU12_16161616
140495. DRM_FORMAT_XVYU16161616
140496. DRM_FORMAT_XVYU2101010
140497. DRM_FORMAT_XYUV8888
140498. DRM_FORMAT_Y0L0
140499. DRM_FORMAT_Y0L2
140500. DRM_FORMAT_Y210
140501. DRM_FORMAT_Y212
140502. DRM_FORMAT_Y216
140503. DRM_FORMAT_Y410
140504. DRM_FORMAT_Y412
140505. DRM_FORMAT_Y416
140506. DRM_FORMAT_YUV410
140507. DRM_FORMAT_YUV411
140508. DRM_FORMAT_YUV420
140509. DRM_FORMAT_YUV420_10BIT
140510. DRM_FORMAT_YUV420_8BIT
140511. DRM_FORMAT_YUV422
140512. DRM_FORMAT_YUV444
140513. DRM_FORMAT_YUYV
140514. DRM_FORMAT_YVU410
140515. DRM_FORMAT_YVU411
140516. DRM_FORMAT_YVU420
140517. DRM_FORMAT_YVU422
140518. DRM_FORMAT_YVU444
140519. DRM_FORMAT_YVYU
140520. DRM_FOURCC_H
140521. DRM_GEM_CMA_UNMAPPED_AREA_FOPS
140522. DRM_GEM_CMA_VMAP_DRIVER_OPS
140523. DRM_GEM_SHMEM_DRIVER_OPS
140524. DRM_GEM_VRAM_DRIVER
140525. DRM_GEM_VRAM_HELPER_H
140526. DRM_GEM_VRAM_PL_FLAG_SYSTEM
140527. DRM_GEM_VRAM_PL_FLAG_VRAM
140528. DRM_HASHTAB_H
140529. DRM_HDCP2_CHECK_PERIOD_MS
140530. DRM_HDCP_1_4_DCP_SIG_SIZE
140531. DRM_HDCP_1_4_SRM_ID
140532. DRM_HDCP_1_4_VRL_LENGTH_SIZE
140533. DRM_HDCP_2_DCP_SIG_SIZE
140534. DRM_HDCP_2_INDICATOR
140535. DRM_HDCP_2_INDICATOR_MASK
140536. DRM_HDCP_2_KSV_COUNT_2_LSBITS
140537. DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ
140538. DRM_HDCP_2_SRM_ID
140539. DRM_HDCP_2_VRL_LENGTH_SIZE
140540. DRM_HDCP_AN_LEN
140541. DRM_HDCP_BSTATUS_LEN
140542. DRM_HDCP_CHECK_PERIOD_MS
140543. DRM_HDCP_DDC_ADDR
140544. DRM_HDCP_DDC_AKSV
140545. DRM_HDCP_DDC_AN
140546. DRM_HDCP_DDC_BCAPS
140547. DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY
140548. DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT
140549. DRM_HDCP_DDC_BKSV
140550. DRM_HDCP_DDC_BSTATUS
140551. DRM_HDCP_DDC_KSV_FIFO
140552. DRM_HDCP_DDC_RI_PRIME
140553. DRM_HDCP_DDC_V_PRIME
140554. DRM_HDCP_KSV_LEN
140555. DRM_HDCP_MAX_CASCADE_EXCEEDED
140556. DRM_HDCP_MAX_DEVICE_EXCEEDED
140557. DRM_HDCP_NUM_DOWNSTREAM
140558. DRM_HDCP_RI_LEN
140559. DRM_HDCP_SRM_GEN1_MAX_BYTES
140560. DRM_HDCP_SRM_ID_MASK
140561. DRM_HDCP_V_PRIME_NUM_PARTS
140562. DRM_HDCP_V_PRIME_PART_LEN
140563. DRM_I810_CLEAR
140564. DRM_I810_COPY
140565. DRM_I810_DOCOPY
140566. DRM_I810_FLIP
140567. DRM_I810_FLUSH
140568. DRM_I810_FSTATUS
140569. DRM_I810_GETAGE
140570. DRM_I810_GETBUF
140571. DRM_I810_INIT
140572. DRM_I810_MC
140573. DRM_I810_OV0FLIP
140574. DRM_I810_OV0INFO
140575. DRM_I810_RSTATUS
140576. DRM_I810_SWAP
140577. DRM_I810_VERTEX
140578. DRM_I915_ALLOC
140579. DRM_I915_BATCHBUFFER
140580. DRM_I915_CMDBUFFER
140581. DRM_I915_DESTROY_HEAP
140582. DRM_I915_FLIP
140583. DRM_I915_FLUSH
140584. DRM_I915_FREE
140585. DRM_I915_GEM_BUSY
140586. DRM_I915_GEM_CONTEXT_CREATE
140587. DRM_I915_GEM_CONTEXT_DESTROY
140588. DRM_I915_GEM_CONTEXT_GETPARAM
140589. DRM_I915_GEM_CONTEXT_SETPARAM
140590. DRM_I915_GEM_CREATE
140591. DRM_I915_GEM_ENTERVT
140592. DRM_I915_GEM_EXECBUFFER
140593. DRM_I915_GEM_EXECBUFFER2
140594. DRM_I915_GEM_EXECBUFFER2_WR
140595. DRM_I915_GEM_GET_APERTURE
140596. DRM_I915_GEM_GET_CACHING
140597. DRM_I915_GEM_GET_TILING
140598. DRM_I915_GEM_INIT
140599. DRM_I915_GEM_LEAVEVT
140600. DRM_I915_GEM_MADVISE
140601. DRM_I915_GEM_MMAP
140602. DRM_I915_GEM_MMAP_GTT
140603. DRM_I915_GEM_PIN
140604. DRM_I915_GEM_PREAD
140605. DRM_I915_GEM_PWRITE
140606. DRM_I915_GEM_SET_CACHING
140607. DRM_I915_GEM_SET_DOMAIN
140608. DRM_I915_GEM_SET_TILING
140609. DRM_I915_GEM_SW_FINISH
140610. DRM_I915_GEM_THROTTLE
140611. DRM_I915_GEM_UNPIN
140612. DRM_I915_GEM_USERPTR
140613. DRM_I915_GEM_VM_CREATE
140614. DRM_I915_GEM_VM_DESTROY
140615. DRM_I915_GEM_WAIT
140616. DRM_I915_GETPARAM
140617. DRM_I915_GET_PIPE_FROM_CRTC_ID
140618. DRM_I915_GET_RESET_STATS
140619. DRM_I915_GET_SPRITE_COLORKEY
140620. DRM_I915_GET_VBLANK_PIPE
140621. DRM_I915_HANGCHECK_JIFFIES
140622. DRM_I915_HANGCHECK_PERIOD
140623. DRM_I915_HWS_ADDR
140624. DRM_I915_INIT
140625. DRM_I915_INIT_HEAP
140626. DRM_I915_IRQ_EMIT
140627. DRM_I915_IRQ_WAIT
140628. DRM_I915_OVERLAY_ATTRS
140629. DRM_I915_OVERLAY_PUT_IMAGE
140630. DRM_I915_PERF_ADD_CONFIG
140631. DRM_I915_PERF_OPEN
140632. DRM_I915_PERF_PROP_CTX_HANDLE
140633. DRM_I915_PERF_PROP_MAX
140634. DRM_I915_PERF_PROP_OA_EXPONENT
140635. DRM_I915_PERF_PROP_OA_FORMAT
140636. DRM_I915_PERF_PROP_OA_METRICS_SET
140637. DRM_I915_PERF_PROP_SAMPLE_OA
140638. DRM_I915_PERF_RECORD_MAX
140639. DRM_I915_PERF_RECORD_OA_BUFFER_LOST
140640. DRM_I915_PERF_RECORD_OA_REPORT_LOST
140641. DRM_I915_PERF_RECORD_SAMPLE
140642. DRM_I915_PERF_REMOVE_CONFIG
140643. DRM_I915_QUERY
140644. DRM_I915_QUERY_ENGINE_INFO
140645. DRM_I915_QUERY_TOPOLOGY_INFO
140646. DRM_I915_REG_READ
140647. DRM_I915_SETPARAM
140648. DRM_I915_SET_SPRITE_COLORKEY
140649. DRM_I915_SET_VBLANK_PIPE
140650. DRM_I915_THROTTLE_JIFFIES
140651. DRM_I915_VBLANK_PIPE_A
140652. DRM_I915_VBLANK_PIPE_B
140653. DRM_I915_VBLANK_SWAP
140654. DRM_IF_MAJOR
140655. DRM_IF_MINOR
140656. DRM_IF_VERSION
140657. DRM_INFO
140658. DRM_INFO_ONCE
140659. DRM_INST_HANDLER
140660. DRM_IO
140661. DRM_IOCTL32_DEF
140662. DRM_IOCTL_ADD_BUFS
140663. DRM_IOCTL_ADD_BUFS32
140664. DRM_IOCTL_ADD_CTX
140665. DRM_IOCTL_ADD_DRAW
140666. DRM_IOCTL_ADD_MAP
140667. DRM_IOCTL_ADD_MAP32
140668. DRM_IOCTL_AGP_ACQUIRE
140669. DRM_IOCTL_AGP_ALLOC
140670. DRM_IOCTL_AGP_ALLOC32
140671. DRM_IOCTL_AGP_BIND
140672. DRM_IOCTL_AGP_BIND32
140673. DRM_IOCTL_AGP_ENABLE
140674. DRM_IOCTL_AGP_ENABLE32
140675. DRM_IOCTL_AGP_FREE
140676. DRM_IOCTL_AGP_FREE32
140677. DRM_IOCTL_AGP_INFO
140678. DRM_IOCTL_AGP_INFO32
140679. DRM_IOCTL_AGP_RELEASE
140680. DRM_IOCTL_AGP_UNBIND
140681. DRM_IOCTL_AGP_UNBIND32
140682. DRM_IOCTL_AMDGPU_BO_LIST
140683. DRM_IOCTL_AMDGPU_CS
140684. DRM_IOCTL_AMDGPU_CTX
140685. DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE
140686. DRM_IOCTL_AMDGPU_GEM_CREATE
140687. DRM_IOCTL_AMDGPU_GEM_METADATA
140688. DRM_IOCTL_AMDGPU_GEM_MMAP
140689. DRM_IOCTL_AMDGPU_GEM_OP
140690. DRM_IOCTL_AMDGPU_GEM_USERPTR
140691. DRM_IOCTL_AMDGPU_GEM_VA
140692. DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE
140693. DRM_IOCTL_AMDGPU_INFO
140694. DRM_IOCTL_AMDGPU_SCHED
140695. DRM_IOCTL_AMDGPU_VM
140696. DRM_IOCTL_AMDGPU_WAIT_CS
140697. DRM_IOCTL_AMDGPU_WAIT_FENCES
140698. DRM_IOCTL_ARMADA_GEM_CREATE
140699. DRM_IOCTL_ARMADA_GEM_MMAP
140700. DRM_IOCTL_ARMADA_GEM_PWRITE
140701. DRM_IOCTL_AUTH_MAGIC
140702. DRM_IOCTL_BASE
140703. DRM_IOCTL_BLOCK
140704. DRM_IOCTL_CONTROL
140705. DRM_IOCTL_CRTC_GET_SEQUENCE
140706. DRM_IOCTL_CRTC_QUEUE_SEQUENCE
140707. DRM_IOCTL_DEF
140708. DRM_IOCTL_DEF_DRV
140709. DRM_IOCTL_DMA
140710. DRM_IOCTL_DMA32
140711. DRM_IOCTL_DROP_MASTER
140712. DRM_IOCTL_ETNAVIV_GEM_CPU_FINI
140713. DRM_IOCTL_ETNAVIV_GEM_CPU_PREP
140714. DRM_IOCTL_ETNAVIV_GEM_INFO
140715. DRM_IOCTL_ETNAVIV_GEM_NEW
140716. DRM_IOCTL_ETNAVIV_GEM_SUBMIT
140717. DRM_IOCTL_ETNAVIV_GEM_USERPTR
140718. DRM_IOCTL_ETNAVIV_GEM_WAIT
140719. DRM_IOCTL_ETNAVIV_GET_PARAM
140720. DRM_IOCTL_ETNAVIV_PM_QUERY_DOM
140721. DRM_IOCTL_ETNAVIV_PM_QUERY_SIG
140722. DRM_IOCTL_ETNAVIV_WAIT_FENCE
140723. DRM_IOCTL_EXYNOS_G2D_EXEC
140724. DRM_IOCTL_EXYNOS_G2D_GET_VER
140725. DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST
140726. DRM_IOCTL_EXYNOS_GEM_CREATE
140727. DRM_IOCTL_EXYNOS_GEM_GET
140728. DRM_IOCTL_EXYNOS_GEM_MAP
140729. DRM_IOCTL_EXYNOS_IPP_COMMIT
140730. DRM_IOCTL_EXYNOS_IPP_GET_CAPS
140731. DRM_IOCTL_EXYNOS_IPP_GET_LIMITS
140732. DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES
140733. DRM_IOCTL_EXYNOS_VIDI_CONNECTION
140734. DRM_IOCTL_FINISH
140735. DRM_IOCTL_FREE_BUFS
140736. DRM_IOCTL_FREE_BUFS32
140737. DRM_IOCTL_GEM_CLOSE
140738. DRM_IOCTL_GEM_FLINK
140739. DRM_IOCTL_GEM_OPEN
140740. DRM_IOCTL_GET_CAP
140741. DRM_IOCTL_GET_CLIENT
140742. DRM_IOCTL_GET_CLIENT32
140743. DRM_IOCTL_GET_CTX
140744. DRM_IOCTL_GET_MAGIC
140745. DRM_IOCTL_GET_MAP
140746. DRM_IOCTL_GET_MAP32
140747. DRM_IOCTL_GET_SAREA_CTX
140748. DRM_IOCTL_GET_SAREA_CTX32
140749. DRM_IOCTL_GET_STATS
140750. DRM_IOCTL_GET_STATS32
140751. DRM_IOCTL_GET_UNIQUE
140752. DRM_IOCTL_GET_UNIQUE32
140753. DRM_IOCTL_I810_CLEAR
140754. DRM_IOCTL_I810_COPY
140755. DRM_IOCTL_I810_DOCOPY
140756. DRM_IOCTL_I810_FLIP
140757. DRM_IOCTL_I810_FLUSH
140758. DRM_IOCTL_I810_FSTATUS
140759. DRM_IOCTL_I810_GETAGE
140760. DRM_IOCTL_I810_GETBUF
140761. DRM_IOCTL_I810_INIT
140762. DRM_IOCTL_I810_MC
140763. DRM_IOCTL_I810_OV0FLIP
140764. DRM_IOCTL_I810_OV0INFO
140765. DRM_IOCTL_I810_RSTATUS
140766. DRM_IOCTL_I810_SWAP
140767. DRM_IOCTL_I810_VERTEX
140768. DRM_IOCTL_I915_ALLOC
140769. DRM_IOCTL_I915_BATCHBUFFER
140770. DRM_IOCTL_I915_CMDBUFFER
140771. DRM_IOCTL_I915_DESTROY_HEAP
140772. DRM_IOCTL_I915_FLIP
140773. DRM_IOCTL_I915_FLUSH
140774. DRM_IOCTL_I915_FREE
140775. DRM_IOCTL_I915_GEM_BUSY
140776. DRM_IOCTL_I915_GEM_CONTEXT_CREATE
140777. DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT
140778. DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
140779. DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
140780. DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
140781. DRM_IOCTL_I915_GEM_CREATE
140782. DRM_IOCTL_I915_GEM_ENTERVT
140783. DRM_IOCTL_I915_GEM_EXECBUFFER
140784. DRM_IOCTL_I915_GEM_EXECBUFFER2
140785. DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
140786. DRM_IOCTL_I915_GEM_GET_APERTURE
140787. DRM_IOCTL_I915_GEM_GET_CACHING
140788. DRM_IOCTL_I915_GEM_GET_TILING
140789. DRM_IOCTL_I915_GEM_INIT
140790. DRM_IOCTL_I915_GEM_LEAVEVT
140791. DRM_IOCTL_I915_GEM_MADVISE
140792. DRM_IOCTL_I915_GEM_MMAP
140793. DRM_IOCTL_I915_GEM_MMAP_GTT
140794. DRM_IOCTL_I915_GEM_PIN
140795. DRM_IOCTL_I915_GEM_PREAD
140796. DRM_IOCTL_I915_GEM_PWRITE
140797. DRM_IOCTL_I915_GEM_SET_CACHING
140798. DRM_IOCTL_I915_GEM_SET_DOMAIN
140799. DRM_IOCTL_I915_GEM_SET_TILING
140800. DRM_IOCTL_I915_GEM_SW_FINISH
140801. DRM_IOCTL_I915_GEM_THROTTLE
140802. DRM_IOCTL_I915_GEM_UNPIN
140803. DRM_IOCTL_I915_GEM_USERPTR
140804. DRM_IOCTL_I915_GEM_VM_CREATE
140805. DRM_IOCTL_I915_GEM_VM_DESTROY
140806. DRM_IOCTL_I915_GEM_WAIT
140807. DRM_IOCTL_I915_GETPARAM
140808. DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID
140809. DRM_IOCTL_I915_GET_RESET_STATS
140810. DRM_IOCTL_I915_GET_SPRITE_COLORKEY
140811. DRM_IOCTL_I915_GET_VBLANK_PIPE
140812. DRM_IOCTL_I915_HWS_ADDR
140813. DRM_IOCTL_I915_INIT
140814. DRM_IOCTL_I915_INIT_HEAP
140815. DRM_IOCTL_I915_IRQ_EMIT
140816. DRM_IOCTL_I915_IRQ_WAIT
140817. DRM_IOCTL_I915_OVERLAY_ATTRS
140818. DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
140819. DRM_IOCTL_I915_PERF_ADD_CONFIG
140820. DRM_IOCTL_I915_PERF_OPEN
140821. DRM_IOCTL_I915_PERF_REMOVE_CONFIG
140822. DRM_IOCTL_I915_QUERY
140823. DRM_IOCTL_I915_REG_READ
140824. DRM_IOCTL_I915_SETPARAM
140825. DRM_IOCTL_I915_SET_SPRITE_COLORKEY
140826. DRM_IOCTL_I915_SET_VBLANK_PIPE
140827. DRM_IOCTL_I915_VBLANK_SWAP
140828. DRM_IOCTL_INFO_BUFS
140829. DRM_IOCTL_INFO_BUFS32
140830. DRM_IOCTL_IRQ_BUSID
140831. DRM_IOCTL_LIMA_CTX_CREATE
140832. DRM_IOCTL_LIMA_CTX_FREE
140833. DRM_IOCTL_LIMA_GEM_CREATE
140834. DRM_IOCTL_LIMA_GEM_INFO
140835. DRM_IOCTL_LIMA_GEM_SUBMIT
140836. DRM_IOCTL_LIMA_GEM_WAIT
140837. DRM_IOCTL_LIMA_GET_PARAM
140838. DRM_IOCTL_LOCK
140839. DRM_IOCTL_MAP_BUFS
140840. DRM_IOCTL_MAP_BUFS32
140841. DRM_IOCTL_MARK_BUFS
140842. DRM_IOCTL_MARK_BUFS32
140843. DRM_IOCTL_MGA_BLIT
140844. DRM_IOCTL_MGA_CLEAR
140845. DRM_IOCTL_MGA_DMA_BOOTSTRAP
140846. DRM_IOCTL_MGA_FLUSH
140847. DRM_IOCTL_MGA_GETPARAM
140848. DRM_IOCTL_MGA_ILOAD
140849. DRM_IOCTL_MGA_INDICES
140850. DRM_IOCTL_MGA_INIT
140851. DRM_IOCTL_MGA_RESET
140852. DRM_IOCTL_MGA_SET_FENCE
140853. DRM_IOCTL_MGA_SWAP
140854. DRM_IOCTL_MGA_VERTEX
140855. DRM_IOCTL_MGA_WAIT_FENCE
140856. DRM_IOCTL_MODESET_CTL
140857. DRM_IOCTL_MODE_ADDFB
140858. DRM_IOCTL_MODE_ADDFB2
140859. DRM_IOCTL_MODE_ADDFB232
140860. DRM_IOCTL_MODE_ATOMIC
140861. DRM_IOCTL_MODE_ATTACHMODE
140862. DRM_IOCTL_MODE_CREATEPROPBLOB
140863. DRM_IOCTL_MODE_CREATE_DUMB
140864. DRM_IOCTL_MODE_CREATE_LEASE
140865. DRM_IOCTL_MODE_CURSOR
140866. DRM_IOCTL_MODE_CURSOR2
140867. DRM_IOCTL_MODE_DESTROYPROPBLOB
140868. DRM_IOCTL_MODE_DESTROY_DUMB
140869. DRM_IOCTL_MODE_DETACHMODE
140870. DRM_IOCTL_MODE_DIRTYFB
140871. DRM_IOCTL_MODE_GETCONNECTOR
140872. DRM_IOCTL_MODE_GETCRTC
140873. DRM_IOCTL_MODE_GETENCODER
140874. DRM_IOCTL_MODE_GETFB
140875. DRM_IOCTL_MODE_GETGAMMA
140876. DRM_IOCTL_MODE_GETPLANE
140877. DRM_IOCTL_MODE_GETPLANERESOURCES
140878. DRM_IOCTL_MODE_GETPROPBLOB
140879. DRM_IOCTL_MODE_GETPROPERTY
140880. DRM_IOCTL_MODE_GETRESOURCES
140881. DRM_IOCTL_MODE_GET_LEASE
140882. DRM_IOCTL_MODE_LIST_LESSEES
140883. DRM_IOCTL_MODE_MAP_DUMB
140884. DRM_IOCTL_MODE_OBJ_GETPROPERTIES
140885. DRM_IOCTL_MODE_OBJ_SETPROPERTY
140886. DRM_IOCTL_MODE_PAGE_FLIP
140887. DRM_IOCTL_MODE_REVOKE_LEASE
140888. DRM_IOCTL_MODE_RMFB
140889. DRM_IOCTL_MODE_SETCRTC
140890. DRM_IOCTL_MODE_SETGAMMA
140891. DRM_IOCTL_MODE_SETPLANE
140892. DRM_IOCTL_MODE_SETPROPERTY
140893. DRM_IOCTL_MOD_CTX
140894. DRM_IOCTL_MSM_GEM_CPU_FINI
140895. DRM_IOCTL_MSM_GEM_CPU_PREP
140896. DRM_IOCTL_MSM_GEM_INFO
140897. DRM_IOCTL_MSM_GEM_MADVISE
140898. DRM_IOCTL_MSM_GEM_NEW
140899. DRM_IOCTL_MSM_GEM_SUBMIT
140900. DRM_IOCTL_MSM_GET_PARAM
140901. DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE
140902. DRM_IOCTL_MSM_SUBMITQUEUE_NEW
140903. DRM_IOCTL_MSM_SUBMITQUEUE_QUERY
140904. DRM_IOCTL_MSM_WAIT_FENCE
140905. DRM_IOCTL_NEW_CTX
140906. DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC
140907. DRM_IOCTL_NOUVEAU_CHANNEL_FREE
140908. DRM_IOCTL_NOUVEAU_GEM_CPU_FINI
140909. DRM_IOCTL_NOUVEAU_GEM_CPU_PREP
140910. DRM_IOCTL_NOUVEAU_GEM_INFO
140911. DRM_IOCTL_NOUVEAU_GEM_NEW
140912. DRM_IOCTL_NOUVEAU_GEM_PUSHBUF
140913. DRM_IOCTL_NOUVEAU_GETPARAM
140914. DRM_IOCTL_NOUVEAU_GPUOBJ_FREE
140915. DRM_IOCTL_NOUVEAU_GROBJ_ALLOC
140916. DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC
140917. DRM_IOCTL_NOUVEAU_SETPARAM
140918. DRM_IOCTL_NOUVEAU_SVM_BIND
140919. DRM_IOCTL_NOUVEAU_SVM_INIT
140920. DRM_IOCTL_NR
140921. DRM_IOCTL_OMAP_GEM_CPU_FINI
140922. DRM_IOCTL_OMAP_GEM_CPU_PREP
140923. DRM_IOCTL_OMAP_GEM_INFO
140924. DRM_IOCTL_OMAP_GEM_NEW
140925. DRM_IOCTL_OMAP_GET_PARAM
140926. DRM_IOCTL_OMAP_SET_PARAM
140927. DRM_IOCTL_PANFROST_CREATE_BO
140928. DRM_IOCTL_PANFROST_GET_BO_OFFSET
140929. DRM_IOCTL_PANFROST_GET_PARAM
140930. DRM_IOCTL_PANFROST_MADVISE
140931. DRM_IOCTL_PANFROST_MMAP_BO
140932. DRM_IOCTL_PANFROST_PERFCNT_DUMP
140933. DRM_IOCTL_PANFROST_PERFCNT_ENABLE
140934. DRM_IOCTL_PANFROST_SUBMIT
140935. DRM_IOCTL_PANFROST_WAIT_BO
140936. DRM_IOCTL_PRIME_FD_TO_HANDLE
140937. DRM_IOCTL_PRIME_HANDLE_TO_FD
140938. DRM_IOCTL_QXL_ALLOC
140939. DRM_IOCTL_QXL_ALLOC_SURF
140940. DRM_IOCTL_QXL_CLIENTCAP
140941. DRM_IOCTL_QXL_EXECBUFFER
140942. DRM_IOCTL_QXL_GETPARAM
140943. DRM_IOCTL_QXL_MAP
140944. DRM_IOCTL_QXL_UPDATE_AREA
140945. DRM_IOCTL_R128_BLIT
140946. DRM_IOCTL_R128_CCE_IDLE
140947. DRM_IOCTL_R128_CCE_RESET
140948. DRM_IOCTL_R128_CCE_START
140949. DRM_IOCTL_R128_CCE_STOP
140950. DRM_IOCTL_R128_CLEAR
140951. DRM_IOCTL_R128_CLEAR2
140952. DRM_IOCTL_R128_DEPTH
140953. DRM_IOCTL_R128_FLIP
140954. DRM_IOCTL_R128_FULLSCREEN
140955. DRM_IOCTL_R128_GETPARAM
140956. DRM_IOCTL_R128_INDICES
140957. DRM_IOCTL_R128_INDIRECT
140958. DRM_IOCTL_R128_INIT
140959. DRM_IOCTL_R128_RESET
140960. DRM_IOCTL_R128_STIPPLE
140961. DRM_IOCTL_R128_SWAP
140962. DRM_IOCTL_R128_VERTEX
140963. DRM_IOCTL_RADEON_ALLOC
140964. DRM_IOCTL_RADEON_CLEAR
140965. DRM_IOCTL_RADEON_CMDBUF
140966. DRM_IOCTL_RADEON_CP_IDLE
140967. DRM_IOCTL_RADEON_CP_INIT
140968. DRM_IOCTL_RADEON_CP_RESET
140969. DRM_IOCTL_RADEON_CP_RESUME
140970. DRM_IOCTL_RADEON_CP_START
140971. DRM_IOCTL_RADEON_CP_STOP
140972. DRM_IOCTL_RADEON_CS
140973. DRM_IOCTL_RADEON_FLIP
140974. DRM_IOCTL_RADEON_FREE
140975. DRM_IOCTL_RADEON_FULLSCREEN
140976. DRM_IOCTL_RADEON_GEM_BUSY
140977. DRM_IOCTL_RADEON_GEM_CREATE
140978. DRM_IOCTL_RADEON_GEM_GET_TILING
140979. DRM_IOCTL_RADEON_GEM_INFO
140980. DRM_IOCTL_RADEON_GEM_MMAP
140981. DRM_IOCTL_RADEON_GEM_OP
140982. DRM_IOCTL_RADEON_GEM_PREAD
140983. DRM_IOCTL_RADEON_GEM_PWRITE
140984. DRM_IOCTL_RADEON_GEM_SET_DOMAIN
140985. DRM_IOCTL_RADEON_GEM_SET_TILING
140986. DRM_IOCTL_RADEON_GEM_USERPTR
140987. DRM_IOCTL_RADEON_GEM_VA
140988. DRM_IOCTL_RADEON_GEM_WAIT_IDLE
140989. DRM_IOCTL_RADEON_GETPARAM
140990. DRM_IOCTL_RADEON_INDICES
140991. DRM_IOCTL_RADEON_INDIRECT
140992. DRM_IOCTL_RADEON_INFO
140993. DRM_IOCTL_RADEON_INIT_HEAP
140994. DRM_IOCTL_RADEON_IRQ_EMIT
140995. DRM_IOCTL_RADEON_IRQ_WAIT
140996. DRM_IOCTL_RADEON_RESET
140997. DRM_IOCTL_RADEON_SETPARAM
140998. DRM_IOCTL_RADEON_STIPPLE
140999. DRM_IOCTL_RADEON_SURF_ALLOC
141000. DRM_IOCTL_RADEON_SURF_FREE
141001. DRM_IOCTL_RADEON_SWAP
141002. DRM_IOCTL_RADEON_TEXTURE
141003. DRM_IOCTL_RADEON_VERTEX
141004. DRM_IOCTL_RADEON_VERTEX2
141005. DRM_IOCTL_RES_CTX
141006. DRM_IOCTL_RES_CTX32
141007. DRM_IOCTL_RM_CTX
141008. DRM_IOCTL_RM_DRAW
141009. DRM_IOCTL_RM_MAP
141010. DRM_IOCTL_RM_MAP32
141011. DRM_IOCTL_SAVAGE_BCI_CMDBUF
141012. DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT
141013. DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT
141014. DRM_IOCTL_SAVAGE_BCI_INIT
141015. DRM_IOCTL_SET_CLIENT_CAP
141016. DRM_IOCTL_SET_MASTER
141017. DRM_IOCTL_SET_SAREA_CTX
141018. DRM_IOCTL_SET_SAREA_CTX32
141019. DRM_IOCTL_SET_UNIQUE
141020. DRM_IOCTL_SET_UNIQUE32
141021. DRM_IOCTL_SET_VERSION
141022. DRM_IOCTL_SG_ALLOC
141023. DRM_IOCTL_SG_ALLOC32
141024. DRM_IOCTL_SG_FREE
141025. DRM_IOCTL_SG_FREE32
141026. DRM_IOCTL_SIS_AGP_ALLOC
141027. DRM_IOCTL_SIS_AGP_FREE
141028. DRM_IOCTL_SIS_AGP_INIT
141029. DRM_IOCTL_SIS_FB_ALLOC
141030. DRM_IOCTL_SIS_FB_FREE
141031. DRM_IOCTL_SIS_FB_INIT
141032. DRM_IOCTL_SWITCH_CTX
141033. DRM_IOCTL_SYNCOBJ_CREATE
141034. DRM_IOCTL_SYNCOBJ_DESTROY
141035. DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE
141036. DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD
141037. DRM_IOCTL_SYNCOBJ_QUERY
141038. DRM_IOCTL_SYNCOBJ_RESET
141039. DRM_IOCTL_SYNCOBJ_SIGNAL
141040. DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL
141041. DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT
141042. DRM_IOCTL_SYNCOBJ_TRANSFER
141043. DRM_IOCTL_SYNCOBJ_WAIT
141044. DRM_IOCTL_TEGRA_CLOSE_CHANNEL
141045. DRM_IOCTL_TEGRA_GEM_CREATE
141046. DRM_IOCTL_TEGRA_GEM_GET_FLAGS
141047. DRM_IOCTL_TEGRA_GEM_GET_TILING
141048. DRM_IOCTL_TEGRA_GEM_MMAP
141049. DRM_IOCTL_TEGRA_GEM_SET_FLAGS
141050. DRM_IOCTL_TEGRA_GEM_SET_TILING
141051. DRM_IOCTL_TEGRA_GET_SYNCPT
141052. DRM_IOCTL_TEGRA_GET_SYNCPT_BASE
141053. DRM_IOCTL_TEGRA_OPEN_CHANNEL
141054. DRM_IOCTL_TEGRA_SUBMIT
141055. DRM_IOCTL_TEGRA_SYNCPT_INCR
141056. DRM_IOCTL_TEGRA_SYNCPT_READ
141057. DRM_IOCTL_TEGRA_SYNCPT_WAIT
141058. DRM_IOCTL_UNBLOCK
141059. DRM_IOCTL_UNLOCK
141060. DRM_IOCTL_UPDATE_DRAW
141061. DRM_IOCTL_UPDATE_DRAW32
141062. DRM_IOCTL_V3D_CREATE_BO
141063. DRM_IOCTL_V3D_GET_BO_OFFSET
141064. DRM_IOCTL_V3D_GET_PARAM
141065. DRM_IOCTL_V3D_MMAP_BO
141066. DRM_IOCTL_V3D_SUBMIT_CL
141067. DRM_IOCTL_V3D_SUBMIT_CSD
141068. DRM_IOCTL_V3D_SUBMIT_TFU
141069. DRM_IOCTL_V3D_WAIT_BO
141070. DRM_IOCTL_VC4_CREATE_BO
141071. DRM_IOCTL_VC4_CREATE_SHADER_BO
141072. DRM_IOCTL_VC4_GEM_MADVISE
141073. DRM_IOCTL_VC4_GET_HANG_STATE
141074. DRM_IOCTL_VC4_GET_PARAM
141075. DRM_IOCTL_VC4_GET_TILING
141076. DRM_IOCTL_VC4_LABEL_BO
141077. DRM_IOCTL_VC4_MMAP_BO
141078. DRM_IOCTL_VC4_PERFMON_CREATE
141079. DRM_IOCTL_VC4_PERFMON_DESTROY
141080. DRM_IOCTL_VC4_PERFMON_GET_VALUES
141081. DRM_IOCTL_VC4_SET_TILING
141082. DRM_IOCTL_VC4_SUBMIT_CL
141083. DRM_IOCTL_VC4_WAIT_BO
141084. DRM_IOCTL_VC4_WAIT_SEQNO
141085. DRM_IOCTL_VERSION
141086. DRM_IOCTL_VERSION32
141087. DRM_IOCTL_VGEM_FENCE_ATTACH
141088. DRM_IOCTL_VGEM_FENCE_SIGNAL
141089. DRM_IOCTL_VIA_AGP_INIT
141090. DRM_IOCTL_VIA_ALLOCMEM
141091. DRM_IOCTL_VIA_BLIT_SYNC
141092. DRM_IOCTL_VIA_CMDBUFFER
141093. DRM_IOCTL_VIA_CMDBUF_SIZE
141094. DRM_IOCTL_VIA_DEC_FUTEX
141095. DRM_IOCTL_VIA_DMA_BLIT
141096. DRM_IOCTL_VIA_DMA_INIT
141097. DRM_IOCTL_VIA_FB_INIT
141098. DRM_IOCTL_VIA_FLUSH
141099. DRM_IOCTL_VIA_FREEMEM
141100. DRM_IOCTL_VIA_MAP_INIT
141101. DRM_IOCTL_VIA_PCICMD
141102. DRM_IOCTL_VIA_WAIT_IRQ
141103. DRM_IOCTL_VIRTGPU_EXECBUFFER
141104. DRM_IOCTL_VIRTGPU_GETPARAM
141105. DRM_IOCTL_VIRTGPU_GET_CAPS
141106. DRM_IOCTL_VIRTGPU_MAP
141107. DRM_IOCTL_VIRTGPU_RESOURCE_CREATE
141108. DRM_IOCTL_VIRTGPU_RESOURCE_INFO
141109. DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST
141110. DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST
141111. DRM_IOCTL_VIRTGPU_WAIT
141112. DRM_IOCTL_VMW_ALLOC_DMABUF
141113. DRM_IOCTL_VMW_CLAIM_STREAM
141114. DRM_IOCTL_VMW_CONTROL_STREAM
141115. DRM_IOCTL_VMW_CREATE_CONTEXT
141116. DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT
141117. DRM_IOCTL_VMW_CREATE_SHADER
141118. DRM_IOCTL_VMW_CREATE_SURFACE
141119. DRM_IOCTL_VMW_CURSOR_BYPASS
141120. DRM_IOCTL_VMW_EXECBUF
141121. DRM_IOCTL_VMW_FENCE_EVENT
141122. DRM_IOCTL_VMW_FENCE_SIGNALED
141123. DRM_IOCTL_VMW_FENCE_UNREF
141124. DRM_IOCTL_VMW_FENCE_WAIT
141125. DRM_IOCTL_VMW_GB_SURFACE_CREATE
141126. DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT
141127. DRM_IOCTL_VMW_GB_SURFACE_REF
141128. DRM_IOCTL_VMW_GB_SURFACE_REF_EXT
141129. DRM_IOCTL_VMW_GET_3D_CAP
141130. DRM_IOCTL_VMW_GET_PARAM
141131. DRM_IOCTL_VMW_PRESENT
141132. DRM_IOCTL_VMW_PRESENT_READBACK
141133. DRM_IOCTL_VMW_REF_SURFACE
141134. DRM_IOCTL_VMW_SYNCCPU
141135. DRM_IOCTL_VMW_UNREF_CONTEXT
141136. DRM_IOCTL_VMW_UNREF_DMABUF
141137. DRM_IOCTL_VMW_UNREF_SHADER
141138. DRM_IOCTL_VMW_UNREF_STREAM
141139. DRM_IOCTL_VMW_UNREF_SURFACE
141140. DRM_IOCTL_VMW_UPDATE_LAYOUT
141141. DRM_IOCTL_WAIT_VBLANK
141142. DRM_IOCTL_WAIT_VBLANK32
141143. DRM_IOR
141144. DRM_IOW
141145. DRM_IOWR
141146. DRM_KERNEL_CONTEXT
141147. DRM_LEGACY_IOCTL_DEF
141148. DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK
141149. DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT
141150. DRM_LIMA_CTX_CREATE
141151. DRM_LIMA_CTX_FREE
141152. DRM_LIMA_GEM_CREATE
141153. DRM_LIMA_GEM_INFO
141154. DRM_LIMA_GEM_SUBMIT
141155. DRM_LIMA_GEM_WAIT
141156. DRM_LIMA_GET_PARAM
141157. DRM_LIMA_PARAM_GPU_ID
141158. DRM_LIMA_PARAM_GPU_ID_MALI400
141159. DRM_LIMA_PARAM_GPU_ID_MALI450
141160. DRM_LIMA_PARAM_GPU_ID_UNKNOWN
141161. DRM_LIMA_PARAM_GP_VERSION
141162. DRM_LIMA_PARAM_NUM_PP
141163. DRM_LIMA_PARAM_PP_VERSION
141164. DRM_LINK_STATUS_BAD
141165. DRM_LINK_STATUS_GOOD
141166. DRM_LIST_FREE
141167. DRM_LIST_NONE
141168. DRM_LIST_PEND
141169. DRM_LIST_PRIO
141170. DRM_LIST_RECLAIM
141171. DRM_LIST_WAIT
141172. DRM_LSPCON_MODE_INVALID
141173. DRM_LSPCON_MODE_LS
141174. DRM_LSPCON_MODE_PCON
141175. DRM_MAJOR
141176. DRM_MAP_HASH_OFFSET
141177. DRM_MASTER
141178. DRM_MAX_CRC_NR
141179. DRM_MAX_ORDER
141180. DRM_MGA_BLIT
141181. DRM_MGA_CLEAR
141182. DRM_MGA_DMA_BOOTSTRAP
141183. DRM_MGA_FLUSH
141184. DRM_MGA_GETPARAM
141185. DRM_MGA_IDLE_RETRY
141186. DRM_MGA_ILOAD
141187. DRM_MGA_INDICES
141188. DRM_MGA_INIT
141189. DRM_MGA_RESET
141190. DRM_MGA_SET_FENCE
141191. DRM_MGA_SWAP
141192. DRM_MGA_VERTEX
141193. DRM_MGA_WAIT_FENCE
141194. DRM_MINOR_CONTROL
141195. DRM_MINOR_PRIMARY
141196. DRM_MINOR_RENDER
141197. DRM_MIN_ORDER
141198. DRM_MM_BUG_ON
141199. DRM_MM_INSERT_BEST
141200. DRM_MM_INSERT_EVICT
141201. DRM_MM_INSERT_HIGH
141202. DRM_MM_INSERT_HIGHEST
141203. DRM_MM_INSERT_LOW
141204. DRM_MM_INSERT_LOWEST
141205. DRM_MM_INSERT_ONCE
141206. DRM_MODE
141207. DRM_MODESET_ACQUIRE_INTERRUPTIBLE
141208. DRM_MODESET_LOCK_ALL_BEGIN
141209. DRM_MODESET_LOCK_ALL_END
141210. DRM_MODESET_LOCK_H_
141211. DRM_MODE_ARG
141212. DRM_MODE_ATOMIC_ALLOW_MODESET
141213. DRM_MODE_ATOMIC_FLAGS
141214. DRM_MODE_ATOMIC_NONBLOCK
141215. DRM_MODE_ATOMIC_TEST_ONLY
141216. DRM_MODE_BLEND_COVERAGE
141217. DRM_MODE_BLEND_PIXEL_NONE
141218. DRM_MODE_BLEND_PREMULTI
141219. DRM_MODE_COLORIMETRY_BT2020_CYCC
141220. DRM_MODE_COLORIMETRY_BT2020_RGB
141221. DRM_MODE_COLORIMETRY_BT2020_YCC
141222. DRM_MODE_COLORIMETRY_BT709_YCC
141223. DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65
141224. DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER
141225. DRM_MODE_COLORIMETRY_DEFAULT
141226. DRM_MODE_COLORIMETRY_NO_DATA
141227. DRM_MODE_COLORIMETRY_OPRGB
141228. DRM_MODE_COLORIMETRY_OPYCC_601
141229. DRM_MODE_COLORIMETRY_SMPTE_170M_YCC
141230. DRM_MODE_COLORIMETRY_SYCC_601
141231. DRM_MODE_COLORIMETRY_XVYCC_601
141232. DRM_MODE_COLORIMETRY_XVYCC_709
141233. DRM_MODE_CONNECTOR_9PinDIN
141234. DRM_MODE_CONNECTOR_Component
141235. DRM_MODE_CONNECTOR_Composite
141236. DRM_MODE_CONNECTOR_DPI
141237. DRM_MODE_CONNECTOR_DSI
141238. DRM_MODE_CONNECTOR_DVIA
141239. DRM_MODE_CONNECTOR_DVID
141240. DRM_MODE_CONNECTOR_DVII
141241. DRM_MODE_CONNECTOR_DisplayPort
141242. DRM_MODE_CONNECTOR_HDMIA
141243. DRM_MODE_CONNECTOR_HDMIB
141244. DRM_MODE_CONNECTOR_LVDS
141245. DRM_MODE_CONNECTOR_SPI
141246. DRM_MODE_CONNECTOR_SVIDEO
141247. DRM_MODE_CONNECTOR_TV
141248. DRM_MODE_CONNECTOR_Unknown
141249. DRM_MODE_CONNECTOR_VGA
141250. DRM_MODE_CONNECTOR_VIRTUAL
141251. DRM_MODE_CONNECTOR_WRITEBACK
141252. DRM_MODE_CONNECTOR_eDP
141253. DRM_MODE_CONTENT_PROTECTION_DESIRED
141254. DRM_MODE_CONTENT_PROTECTION_ENABLED
141255. DRM_MODE_CONTENT_PROTECTION_UNDESIRED
141256. DRM_MODE_CONTENT_TYPE_CINEMA
141257. DRM_MODE_CONTENT_TYPE_GAME
141258. DRM_MODE_CONTENT_TYPE_GRAPHICS
141259. DRM_MODE_CONTENT_TYPE_NO_DATA
141260. DRM_MODE_CONTENT_TYPE_PHOTO
141261. DRM_MODE_CURSOR_BO
141262. DRM_MODE_CURSOR_FLAGS
141263. DRM_MODE_CURSOR_MOVE
141264. DRM_MODE_DIRTY_ANNOTATE
141265. DRM_MODE_DIRTY_OFF
141266. DRM_MODE_DIRTY_ON
141267. DRM_MODE_DITHERING_AUTO
141268. DRM_MODE_DITHERING_OFF
141269. DRM_MODE_DITHERING_ON
141270. DRM_MODE_DPMS_OFF
141271. DRM_MODE_DPMS_ON
141272. DRM_MODE_DPMS_STANDBY
141273. DRM_MODE_DPMS_SUSPEND
141274. DRM_MODE_ENCODER_DAC
141275. DRM_MODE_ENCODER_DPI
141276. DRM_MODE_ENCODER_DPMST
141277. DRM_MODE_ENCODER_DSI
141278. DRM_MODE_ENCODER_LVDS
141279. DRM_MODE_ENCODER_NONE
141280. DRM_MODE_ENCODER_TMDS
141281. DRM_MODE_ENCODER_TVDAC
141282. DRM_MODE_ENCODER_VIRTUAL
141283. DRM_MODE_FB_DIRTY_ANNOTATE_COPY
141284. DRM_MODE_FB_DIRTY_ANNOTATE_FILL
141285. DRM_MODE_FB_DIRTY_FLAGS
141286. DRM_MODE_FB_DIRTY_MAX_CLIPS
141287. DRM_MODE_FB_INTERLACED
141288. DRM_MODE_FB_MODIFIERS
141289. DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE
141290. DRM_MODE_FLAG_3D_FRAME_PACKING
141291. DRM_MODE_FLAG_3D_LINE_ALTERNATIVE
141292. DRM_MODE_FLAG_3D_L_DEPTH
141293. DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH
141294. DRM_MODE_FLAG_3D_MASK
141295. DRM_MODE_FLAG_3D_MAX
141296. DRM_MODE_FLAG_3D_NONE
141297. DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL
141298. DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
141299. DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
141300. DRM_MODE_FLAG_ALL
141301. DRM_MODE_FLAG_BCAST
141302. DRM_MODE_FLAG_CLKDIV2
141303. DRM_MODE_FLAG_CSYNC
141304. DRM_MODE_FLAG_DBLCLK
141305. DRM_MODE_FLAG_DBLSCAN
141306. DRM_MODE_FLAG_HSKEW
141307. DRM_MODE_FLAG_INTERLACE
141308. DRM_MODE_FLAG_NCSYNC
141309. DRM_MODE_FLAG_NHSYNC
141310. DRM_MODE_FLAG_NVSYNC
141311. DRM_MODE_FLAG_PCSYNC
141312. DRM_MODE_FLAG_PHSYNC
141313. DRM_MODE_FLAG_PIC_AR_16_9
141314. DRM_MODE_FLAG_PIC_AR_256_135
141315. DRM_MODE_FLAG_PIC_AR_4_3
141316. DRM_MODE_FLAG_PIC_AR_64_27
141317. DRM_MODE_FLAG_PIC_AR_MASK
141318. DRM_MODE_FLAG_PIC_AR_NONE
141319. DRM_MODE_FLAG_PIXMUX
141320. DRM_MODE_FLAG_PVSYNC
141321. DRM_MODE_FMT
141322. DRM_MODE_HDCP_CONTENT_TYPE0
141323. DRM_MODE_HDCP_CONTENT_TYPE1
141324. DRM_MODE_LINK_STATUS_BAD
141325. DRM_MODE_LINK_STATUS_GOOD
141326. DRM_MODE_MATCH_3D_FLAGS
141327. DRM_MODE_MATCH_ASPECT_RATIO
141328. DRM_MODE_MATCH_CLOCK
141329. DRM_MODE_MATCH_FLAGS
141330. DRM_MODE_MATCH_TIMINGS
141331. DRM_MODE_OBJECT_ANY
141332. DRM_MODE_OBJECT_BLOB
141333. DRM_MODE_OBJECT_CONNECTOR
141334. DRM_MODE_OBJECT_CRTC
141335. DRM_MODE_OBJECT_ENCODER
141336. DRM_MODE_OBJECT_FB
141337. DRM_MODE_OBJECT_MODE
141338. DRM_MODE_OBJECT_PLANE
141339. DRM_MODE_OBJECT_PROPERTY
141340. DRM_MODE_PAGE_FLIP_ASYNC
141341. DRM_MODE_PAGE_FLIP_EVENT
141342. DRM_MODE_PAGE_FLIP_FLAGS
141343. DRM_MODE_PAGE_FLIP_TARGET
141344. DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE
141345. DRM_MODE_PAGE_FLIP_TARGET_RELATIVE
141346. DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP
141347. DRM_MODE_PANEL_ORIENTATION_LEFT_UP
141348. DRM_MODE_PANEL_ORIENTATION_NORMAL
141349. DRM_MODE_PANEL_ORIENTATION_RIGHT_UP
141350. DRM_MODE_PANEL_ORIENTATION_UNKNOWN
141351. DRM_MODE_PICTURE_ASPECT_16_9
141352. DRM_MODE_PICTURE_ASPECT_256_135
141353. DRM_MODE_PICTURE_ASPECT_4_3
141354. DRM_MODE_PICTURE_ASPECT_64_27
141355. DRM_MODE_PICTURE_ASPECT_NONE
141356. DRM_MODE_PRESENT_BOTTOM_FIELD
141357. DRM_MODE_PRESENT_TOP_FIELD
141358. DRM_MODE_PROP_ATOMIC
141359. DRM_MODE_PROP_BITMASK
141360. DRM_MODE_PROP_BLOB
141361. DRM_MODE_PROP_ENUM
141362. DRM_MODE_PROP_EXTENDED_TYPE
141363. DRM_MODE_PROP_IMMUTABLE
141364. DRM_MODE_PROP_LEGACY_TYPE
141365. DRM_MODE_PROP_OBJECT
141366. DRM_MODE_PROP_PENDING
141367. DRM_MODE_PROP_RANGE
141368. DRM_MODE_PROP_SIGNED_RANGE
141369. DRM_MODE_PROP_TYPE
141370. DRM_MODE_REFLECT_MASK
141371. DRM_MODE_REFLECT_X
141372. DRM_MODE_REFLECT_Y
141373. DRM_MODE_ROTATE_0
141374. DRM_MODE_ROTATE_180
141375. DRM_MODE_ROTATE_270
141376. DRM_MODE_ROTATE_90
141377. DRM_MODE_ROTATE_MASK
141378. DRM_MODE_SCALE_ASPECT
141379. DRM_MODE_SCALE_CENTER
141380. DRM_MODE_SCALE_FULLSCREEN
141381. DRM_MODE_SCALE_NONE
141382. DRM_MODE_SCALE_NO_SCALE
141383. DRM_MODE_SUBCONNECTOR_Automatic
141384. DRM_MODE_SUBCONNECTOR_Component
141385. DRM_MODE_SUBCONNECTOR_Composite
141386. DRM_MODE_SUBCONNECTOR_DVIA
141387. DRM_MODE_SUBCONNECTOR_DVID
141388. DRM_MODE_SUBCONNECTOR_SCART
141389. DRM_MODE_SUBCONNECTOR_SVIDEO
141390. DRM_MODE_SUBCONNECTOR_Unknown
141391. DRM_MODE_TYPE_ALL
141392. DRM_MODE_TYPE_BUILTIN
141393. DRM_MODE_TYPE_CLOCK_C
141394. DRM_MODE_TYPE_CRTC_C
141395. DRM_MODE_TYPE_DEFAULT
141396. DRM_MODE_TYPE_DRIVER
141397. DRM_MODE_TYPE_PREFERRED
141398. DRM_MODE_TYPE_USERDEF
141399. DRM_MSM_GEM_CPU_FINI
141400. DRM_MSM_GEM_CPU_PREP
141401. DRM_MSM_GEM_INFO
141402. DRM_MSM_GEM_MADVISE
141403. DRM_MSM_GEM_NEW
141404. DRM_MSM_GEM_SUBMIT
141405. DRM_MSM_GET_PARAM
141406. DRM_MSM_HANGCHECK_JIFFIES
141407. DRM_MSM_HANGCHECK_PERIOD
141408. DRM_MSM_INACTIVE_PERIOD
141409. DRM_MSM_SUBMITQUEUE_CLOSE
141410. DRM_MSM_SUBMITQUEUE_NEW
141411. DRM_MSM_SUBMITQUEUE_QUERY
141412. DRM_MSM_WAIT_FENCE
141413. DRM_NAME
141414. DRM_NOTE
141415. DRM_NOTE_ONCE
141416. DRM_NOUVEAU_CHANNEL_ALLOC
141417. DRM_NOUVEAU_CHANNEL_FREE
141418. DRM_NOUVEAU_EVENT_NVIF
141419. DRM_NOUVEAU_GEM_CPU_FINI
141420. DRM_NOUVEAU_GEM_CPU_PREP
141421. DRM_NOUVEAU_GEM_INFO
141422. DRM_NOUVEAU_GEM_NEW
141423. DRM_NOUVEAU_GEM_PUSHBUF
141424. DRM_NOUVEAU_GETPARAM
141425. DRM_NOUVEAU_GPUOBJ_FREE
141426. DRM_NOUVEAU_GROBJ_ALLOC
141427. DRM_NOUVEAU_NOTIFIEROBJ_ALLOC
141428. DRM_NOUVEAU_NVIF
141429. DRM_NOUVEAU_SETPARAM
141430. DRM_NOUVEAU_SVM_BIND
141431. DRM_NOUVEAU_SVM_INIT
141432. DRM_OBJECT_MAX_PROPERTY
141433. DRM_OMAP_GEM_CPU_FINI
141434. DRM_OMAP_GEM_CPU_PREP
141435. DRM_OMAP_GEM_INFO
141436. DRM_OMAP_GEM_NEW
141437. DRM_OMAP_GET_PARAM
141438. DRM_OMAP_NUM_IOCTLS
141439. DRM_OMAP_SET_PARAM
141440. DRM_OUTPUT_POLL_PERIOD
141441. DRM_PANFROST_CREATE_BO
141442. DRM_PANFROST_GET_BO_OFFSET
141443. DRM_PANFROST_GET_PARAM
141444. DRM_PANFROST_MADVISE
141445. DRM_PANFROST_MMAP_BO
141446. DRM_PANFROST_PARAM_AS_PRESENT
141447. DRM_PANFROST_PARAM_COHERENCY_FEATURES
141448. DRM_PANFROST_PARAM_CORE_FEATURES
141449. DRM_PANFROST_PARAM_GPU_PROD_ID
141450. DRM_PANFROST_PARAM_GPU_REVISION
141451. DRM_PANFROST_PARAM_JS_FEATURES0
141452. DRM_PANFROST_PARAM_JS_FEATURES1
141453. DRM_PANFROST_PARAM_JS_FEATURES10
141454. DRM_PANFROST_PARAM_JS_FEATURES11
141455. DRM_PANFROST_PARAM_JS_FEATURES12
141456. DRM_PANFROST_PARAM_JS_FEATURES13
141457. DRM_PANFROST_PARAM_JS_FEATURES14
141458. DRM_PANFROST_PARAM_JS_FEATURES15
141459. DRM_PANFROST_PARAM_JS_FEATURES2
141460. DRM_PANFROST_PARAM_JS_FEATURES3
141461. DRM_PANFROST_PARAM_JS_FEATURES4
141462. DRM_PANFROST_PARAM_JS_FEATURES5
141463. DRM_PANFROST_PARAM_JS_FEATURES6
141464. DRM_PANFROST_PARAM_JS_FEATURES7
141465. DRM_PANFROST_PARAM_JS_FEATURES8
141466. DRM_PANFROST_PARAM_JS_FEATURES9
141467. DRM_PANFROST_PARAM_JS_PRESENT
141468. DRM_PANFROST_PARAM_L2_FEATURES
141469. DRM_PANFROST_PARAM_L2_PRESENT
141470. DRM_PANFROST_PARAM_MAX_THREADS
141471. DRM_PANFROST_PARAM_MEM_FEATURES
141472. DRM_PANFROST_PARAM_MMU_FEATURES
141473. DRM_PANFROST_PARAM_NR_CORE_GROUPS
141474. DRM_PANFROST_PARAM_SHADER_PRESENT
141475. DRM_PANFROST_PARAM_STACK_PRESENT
141476. DRM_PANFROST_PARAM_TEXTURE_FEATURES0
141477. DRM_PANFROST_PARAM_TEXTURE_FEATURES1
141478. DRM_PANFROST_PARAM_TEXTURE_FEATURES2
141479. DRM_PANFROST_PARAM_TEXTURE_FEATURES3
141480. DRM_PANFROST_PARAM_THREAD_FEATURES
141481. DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ
141482. DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ
141483. DRM_PANFROST_PARAM_THREAD_TLS_ALLOC
141484. DRM_PANFROST_PARAM_TILER_FEATURES
141485. DRM_PANFROST_PARAM_TILER_PRESENT
141486. DRM_PANFROST_PERFCNT_DUMP
141487. DRM_PANFROST_PERFCNT_ENABLE
141488. DRM_PANFROST_SUBMIT
141489. DRM_PANFROST_WAIT_BO
141490. DRM_PLANE_COMMIT_ACTIVE_ONLY
141491. DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET
141492. DRM_PLANE_HELPER_H
141493. DRM_PLANE_HELPER_NO_SCALING
141494. DRM_PLANE_TYPE_CURSOR
141495. DRM_PLANE_TYPE_OVERLAY
141496. DRM_PLANE_TYPE_PRIMARY
141497. DRM_PRIME_CAP_EXPORT
141498. DRM_PRIME_CAP_IMPORT
141499. DRM_PRINT_H_
141500. DRM_PROP_NAME_LEN
141501. DRM_QXL_ALLOC
141502. DRM_QXL_ALLOC_SURF
141503. DRM_QXL_CLIENTCAP
141504. DRM_QXL_EXECBUFFER
141505. DRM_QXL_GETPARAM
141506. DRM_QXL_MAP
141507. DRM_QXL_UPDATE_AREA
141508. DRM_R128_BLIT
141509. DRM_R128_CCE_IDLE
141510. DRM_R128_CCE_RESET
141511. DRM_R128_CCE_START
141512. DRM_R128_CCE_STOP
141513. DRM_R128_CLEAR
141514. DRM_R128_CLEAR2
141515. DRM_R128_DEPTH
141516. DRM_R128_FLIP
141517. DRM_R128_FULLSCREEN
141518. DRM_R128_GETPARAM
141519. DRM_R128_INDICES
141520. DRM_R128_INDIRECT
141521. DRM_R128_INIT
141522. DRM_R128_RESET
141523. DRM_R128_STIPPLE
141524. DRM_R128_SWAP
141525. DRM_R128_VERTEX
141526. DRM_RADEON_ALLOC
141527. DRM_RADEON_CLEAR
141528. DRM_RADEON_CMDBUF
141529. DRM_RADEON_CP_IDLE
141530. DRM_RADEON_CP_INIT
141531. DRM_RADEON_CP_RESET
141532. DRM_RADEON_CP_RESUME
141533. DRM_RADEON_CP_START
141534. DRM_RADEON_CP_STOP
141535. DRM_RADEON_CS
141536. DRM_RADEON_FLIP
141537. DRM_RADEON_FREE
141538. DRM_RADEON_FULLSCREEN
141539. DRM_RADEON_GEM_BUSY
141540. DRM_RADEON_GEM_CREATE
141541. DRM_RADEON_GEM_GET_TILING
141542. DRM_RADEON_GEM_INFO
141543. DRM_RADEON_GEM_MMAP
141544. DRM_RADEON_GEM_OP
141545. DRM_RADEON_GEM_PREAD
141546. DRM_RADEON_GEM_PWRITE
141547. DRM_RADEON_GEM_SET_DOMAIN
141548. DRM_RADEON_GEM_SET_TILING
141549. DRM_RADEON_GEM_USERPTR
141550. DRM_RADEON_GEM_VA
141551. DRM_RADEON_GEM_WAIT_IDLE
141552. DRM_RADEON_GETPARAM
141553. DRM_RADEON_INDICES
141554. DRM_RADEON_INDIRECT
141555. DRM_RADEON_INFO
141556. DRM_RADEON_INIT_HEAP
141557. DRM_RADEON_IRQ_EMIT
141558. DRM_RADEON_IRQ_WAIT
141559. DRM_RADEON_NOT_USED
141560. DRM_RADEON_RESET
141561. DRM_RADEON_SETPARAM
141562. DRM_RADEON_STIPPLE
141563. DRM_RADEON_SURF_ALLOC
141564. DRM_RADEON_SURF_FREE
141565. DRM_RADEON_SWAP
141566. DRM_RADEON_TEXTURE
141567. DRM_RADEON_VBLANK_CRTC1
141568. DRM_RADEON_VBLANK_CRTC2
141569. DRM_RADEON_VERTEX
141570. DRM_RADEON_VERTEX2
141571. DRM_RAM_PERCENT
141572. DRM_RDWR
141573. DRM_READ16
141574. DRM_READ32
141575. DRM_READ64
141576. DRM_READ8
141577. DRM_RECT_ARG
141578. DRM_RECT_FMT
141579. DRM_RECT_FP_ARG
141580. DRM_RECT_FP_FMT
141581. DRM_RECT_H
141582. DRM_REDUNDANT_VBLIRQ_THRESH_NS
141583. DRM_RENDER_ALLOW
141584. DRM_RESERVED_CONTEXTS
141585. DRM_RM_COMMAND
141586. DRM_RND_STATE
141587. DRM_RND_STATE_INITIALIZER
141588. DRM_ROOT_ONLY
141589. DRM_SAVAGE_BCI_CMDBUF
141590. DRM_SAVAGE_BCI_EVENT_EMIT
141591. DRM_SAVAGE_BCI_EVENT_WAIT
141592. DRM_SAVAGE_BCI_INIT
141593. DRM_SCANOUTPOS_ACCURATE
141594. DRM_SCANOUTPOS_IN_VBLANK
141595. DRM_SCANOUTPOS_VALID
141596. DRM_SCDC_HELPER_H
141597. DRM_SCHEDULER_SPSC_QUEUE_H_
141598. DRM_SCHED_PRIORITY_HIGH_HW
141599. DRM_SCHED_PRIORITY_HIGH_SW
141600. DRM_SCHED_PRIORITY_INVALID
141601. DRM_SCHED_PRIORITY_KERNEL
141602. DRM_SCHED_PRIORITY_LOW
141603. DRM_SCHED_PRIORITY_MAX
141604. DRM_SCHED_PRIORITY_MIN
141605. DRM_SCHED_PRIORITY_NORMAL
141606. DRM_SCHED_PRIORITY_UNSET
141607. DRM_SELF_REFRESH_HELPER_H_
141608. DRM_SIMPLE_MODE
141609. DRM_SIS_AGP_ALLOC
141610. DRM_SIS_AGP_FREE
141611. DRM_SIS_AGP_INIT
141612. DRM_SIS_FB_ALLOC
141613. DRM_SIS_FB_FREE
141614. DRM_SIS_FB_INIT
141615. DRM_SWITCH_POWER_CHANGING
141616. DRM_SWITCH_POWER_DYNAMIC_OFF
141617. DRM_SWITCH_POWER_OFF
141618. DRM_SWITCH_POWER_ON
141619. DRM_SYNCOBJ_CREATE_SIGNALED
141620. DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE
141621. DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE
141622. DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
141623. DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE
141624. DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT
141625. DRM_SYNCOBJ_WAIT_FOR_SUBMIT_TIMEOUT
141626. DRM_TEGRA_CLOSE_CHANNEL
141627. DRM_TEGRA_DPAUX_H
141628. DRM_TEGRA_DSI_H
141629. DRM_TEGRA_GEM_BOTTOM_UP
141630. DRM_TEGRA_GEM_CREATE
141631. DRM_TEGRA_GEM_CREATE_BOTTOM_UP
141632. DRM_TEGRA_GEM_CREATE_TILED
141633. DRM_TEGRA_GEM_FLAGS
141634. DRM_TEGRA_GEM_GET_FLAGS
141635. DRM_TEGRA_GEM_GET_TILING
141636. DRM_TEGRA_GEM_MMAP
141637. DRM_TEGRA_GEM_SET_FLAGS
141638. DRM_TEGRA_GEM_SET_TILING
141639. DRM_TEGRA_GEM_TILING_MODE_BLOCK
141640. DRM_TEGRA_GEM_TILING_MODE_PITCH
141641. DRM_TEGRA_GEM_TILING_MODE_TILED
141642. DRM_TEGRA_GET_SYNCPT
141643. DRM_TEGRA_GET_SYNCPT_BASE
141644. DRM_TEGRA_HDA_H
141645. DRM_TEGRA_MIPI_PHY_H
141646. DRM_TEGRA_NO_TIMEOUT
141647. DRM_TEGRA_OPEN_CHANNEL
141648. DRM_TEGRA_SOR_H
141649. DRM_TEGRA_SUBMIT
141650. DRM_TEGRA_SYNCPT_INCR
141651. DRM_TEGRA_SYNCPT_READ
141652. DRM_TEGRA_SYNCPT_WAIT
141653. DRM_TEGRA_TRACE_H
141654. DRM_TIMESTAMP_MAXRETRIES
141655. DRM_UDELAY
141656. DRM_UNINST_HANDLER
141657. DRM_UNIT
141658. DRM_UNLOCKED
141659. DRM_UT_ATOMIC
141660. DRM_UT_CORE
141661. DRM_UT_DP
141662. DRM_UT_DRIVER
141663. DRM_UT_KMS
141664. DRM_UT_LEASE
141665. DRM_UT_NONE
141666. DRM_UT_PRIME
141667. DRM_UT_STATE
141668. DRM_UT_VBL
141669. DRM_V3D_CREATE_BO
141670. DRM_V3D_GET_BO_OFFSET
141671. DRM_V3D_GET_PARAM
141672. DRM_V3D_MMAP_BO
141673. DRM_V3D_PARAM_SUPPORTS_CSD
141674. DRM_V3D_PARAM_SUPPORTS_TFU
141675. DRM_V3D_PARAM_V3D_CORE0_IDENT0
141676. DRM_V3D_PARAM_V3D_CORE0_IDENT1
141677. DRM_V3D_PARAM_V3D_CORE0_IDENT2
141678. DRM_V3D_PARAM_V3D_HUB_IDENT1
141679. DRM_V3D_PARAM_V3D_HUB_IDENT2
141680. DRM_V3D_PARAM_V3D_HUB_IDENT3
141681. DRM_V3D_PARAM_V3D_UIFCFG
141682. DRM_V3D_SUBMIT_CL
141683. DRM_V3D_SUBMIT_CSD
141684. DRM_V3D_SUBMIT_TFU
141685. DRM_V3D_WAIT_BO
141686. DRM_VC4_CREATE_BO
141687. DRM_VC4_CREATE_SHADER_BO
141688. DRM_VC4_GEM_MADVISE
141689. DRM_VC4_GET_HANG_STATE
141690. DRM_VC4_GET_PARAM
141691. DRM_VC4_GET_TILING
141692. DRM_VC4_LABEL_BO
141693. DRM_VC4_MAX_PERF_COUNTERS
141694. DRM_VC4_MMAP_BO
141695. DRM_VC4_PARAM_SUPPORTS_BRANCHES
141696. DRM_VC4_PARAM_SUPPORTS_ETC1
141697. DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER
141698. DRM_VC4_PARAM_SUPPORTS_MADVISE
141699. DRM_VC4_PARAM_SUPPORTS_PERFMON
141700. DRM_VC4_PARAM_SUPPORTS_THREADED_FS
141701. DRM_VC4_PARAM_V3D_IDENT0
141702. DRM_VC4_PARAM_V3D_IDENT1
141703. DRM_VC4_PARAM_V3D_IDENT2
141704. DRM_VC4_PERFMON_CREATE
141705. DRM_VC4_PERFMON_DESTROY
141706. DRM_VC4_PERFMON_GET_VALUES
141707. DRM_VC4_SET_TILING
141708. DRM_VC4_SUBMIT_CL
141709. DRM_VC4_WAIT_BO
141710. DRM_VC4_WAIT_SEQNO
141711. DRM_VGEM_FENCE_ATTACH
141712. DRM_VGEM_FENCE_SIGNAL
141713. DRM_VIA_AGP_INIT
141714. DRM_VIA_ALLOCMEM
141715. DRM_VIA_BLIT_SYNC
141716. DRM_VIA_CMDBUFFER
141717. DRM_VIA_CMDBUF_SIZE
141718. DRM_VIA_DEC_FUTEX
141719. DRM_VIA_DMA_BLIT
141720. DRM_VIA_DMA_INIT
141721. DRM_VIA_FB_INIT
141722. DRM_VIA_FLUSH
141723. DRM_VIA_FREEMEM
141724. DRM_VIA_MAP_INIT
141725. DRM_VIA_PCICMD
141726. DRM_VIA_WAIT_IRQ
141727. DRM_VIRTGPU_EXECBUFFER
141728. DRM_VIRTGPU_GETPARAM
141729. DRM_VIRTGPU_GET_CAPS
141730. DRM_VIRTGPU_MAP
141731. DRM_VIRTGPU_RESOURCE_CREATE
141732. DRM_VIRTGPU_RESOURCE_INFO
141733. DRM_VIRTGPU_TRANSFER_FROM_HOST
141734. DRM_VIRTGPU_TRANSFER_TO_HOST
141735. DRM_VIRTGPU_WAIT
141736. DRM_VIRTIO_NUM_IOCTLS
141737. DRM_VIRTUAL_DEVICE
141738. DRM_VMW_ALLOC_BO
141739. DRM_VMW_ALLOC_DMABUF
141740. DRM_VMW_CLAIM_STREAM
141741. DRM_VMW_CONTROL_STREAM
141742. DRM_VMW_CREATE_CONTEXT
141743. DRM_VMW_CREATE_EXTENDED_CONTEXT
141744. DRM_VMW_CREATE_SHADER
141745. DRM_VMW_CREATE_SURFACE
141746. DRM_VMW_CURSOR_BYPASS
141747. DRM_VMW_CURSOR_BYPASS_ALL
141748. DRM_VMW_CURSOR_BYPASS_FLAGS
141749. DRM_VMW_EVENT_FENCE_SIGNALED
141750. DRM_VMW_EXECBUF
141751. DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD
141752. DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD
141753. DRM_VMW_EXECBUF_VERSION
141754. DRM_VMW_FENCE_EVENT
141755. DRM_VMW_FENCE_FLAG_EXEC
141756. DRM_VMW_FENCE_FLAG_QUERY
141757. DRM_VMW_FENCE_SIGNALED
141758. DRM_VMW_FENCE_UNREF
141759. DRM_VMW_FENCE_WAIT
141760. DRM_VMW_FE_FLAG_REQ_TIME
141761. DRM_VMW_GB_SURFACE_CREATE
141762. DRM_VMW_GB_SURFACE_CREATE_EXT
141763. DRM_VMW_GB_SURFACE_REF
141764. DRM_VMW_GB_SURFACE_REF_EXT
141765. DRM_VMW_GET_3D_CAP
141766. DRM_VMW_GET_PARAM
141767. DRM_VMW_HANDLE_CLOSE
141768. DRM_VMW_HANDLE_LEGACY
141769. DRM_VMW_HANDLE_PRIME
141770. DRM_VMW_MAX_MIP_LEVELS
141771. DRM_VMW_MAX_SURFACE_FACES
141772. DRM_VMW_PARAM_3D
141773. DRM_VMW_PARAM_3D_CAPS_SIZE
141774. DRM_VMW_PARAM_DX
141775. DRM_VMW_PARAM_FIFO_CAPS
141776. DRM_VMW_PARAM_FIFO_HW_VERSION
141777. DRM_VMW_PARAM_HW_CAPS
141778. DRM_VMW_PARAM_HW_CAPS2
141779. DRM_VMW_PARAM_MAX_FB_SIZE
141780. DRM_VMW_PARAM_MAX_MOB_MEMORY
141781. DRM_VMW_PARAM_MAX_MOB_SIZE
141782. DRM_VMW_PARAM_MAX_SURF_MEMORY
141783. DRM_VMW_PARAM_NUM_FREE_STREAMS
141784. DRM_VMW_PARAM_NUM_STREAMS
141785. DRM_VMW_PARAM_SCREEN_TARGET
141786. DRM_VMW_PARAM_SM4_1
141787. DRM_VMW_PRESENT
141788. DRM_VMW_PRESENT_READBACK
141789. DRM_VMW_REF_SURFACE
141790. DRM_VMW_SYNCCPU
141791. DRM_VMW_UNREF_CONTEXT
141792. DRM_VMW_UNREF_DMABUF
141793. DRM_VMW_UNREF_SHADER
141794. DRM_VMW_UNREF_STREAM
141795. DRM_VMW_UNREF_SURFACE
141796. DRM_VMW_UPDATE_LAYOUT
141797. DRM_VMW_WAIT_OPTION_UNREF
141798. DRM_VRAM_MM_FILE_OPERATIONS
141799. DRM_VRAM_MM_HELPER_H
141800. DRM_WAIT_ON
141801. DRM_WARN
141802. DRM_WARN_ONCE
141803. DRM_WRITE16
141804. DRM_WRITE32
141805. DRM_WRITE64
141806. DRM_WRITE8
141807. DROP
141808. DROPBITS
141809. DROPLESS_FC_HEADROOM
141810. DROPPED_DB_F
141811. DROPPED_DB_S
141812. DROPPED_DB_V
141813. DROP_ACTIVE
141814. DROP_ALL
141815. DROP_BOUND
141816. DROP_BUFFER_SIZE
141817. DROP_COUNT_RESET
141818. DROP_DATA_EN
141819. DROP_EP
141820. DROP_ERR_INNER_MAP
141821. DROP_ERR_SKB_DATA
141822. DROP_ERR_SK_SELECT_REUSEPORT
141823. DROP_FREED
141824. DROP_HREF
141825. DROP_IDLE
141826. DROP_IO
141827. DROP_MISC
141828. DROP_MSEC
141829. DROP_PACKET
141830. DROP_PACKET_OFF
141831. DROP_PACKET_ON
141832. DROP_PAGECACHE
141833. DROP_PKT
141834. DROP_PKTS_CNT
141835. DROP_REFERENCE
141836. DROP_RESET_ACTIVE
141837. DROP_RESET_SEQNO
141838. DROP_RETIRE
141839. DROP_SHRINK_ALL
141840. DROP_SLAB
141841. DROP_THRESH
141842. DROP_THRESH_NS
141843. DROP_UNBOUND
141844. DROP_VSYNC
141845. DROP_WRITES
141846. DROUND
141847. DRP0_INTERRUPT_ENABLE
141848. DRPAUSE
141849. DRPD
141850. DRPW_BASE
141851. DRP_DONE
141852. DRP_ECC_DB_ERR_SYN0
141853. DRP_ECC_ERROR_CFG
141854. DRP_ECC_ERROR_CNTR_CLEAR
141855. DRP_ECC_ERROR_STATUS0
141856. DRP_ECC_ERROR_STATUS1
141857. DRP_ECC_SB_ERR_SYN0
141858. DRP_EN
141859. DRP_INTERRUPT_CLEAR
141860. DRP_INTERRUPT_ENABLE
141861. DRP_INTERRUPT_STATUS
141862. DRP_PKT_CNTR
141863. DRP_PKT_CNTR_NC
141864. DRP_READ
141865. DRP_START
141866. DRP_SYN_REG_CNT
141867. DRP_TRP_CNT_CLEAR
141868. DRP_TRP_INT_CLEAR
141869. DRP_WRITE
141870. DRQ_BLOCK_SIZE_1024
141871. DRQ_BLOCK_SIZE_2048
141872. DRQ_BLOCK_SIZE_4096
141873. DRQ_BLOCK_SIZE_512
141874. DRQ_BLOCK_SIZE_MASK
141875. DRQ_SDRAM
141876. DRQ_STAT
141877. DRR
141878. DRRS_HIGH_RR
141879. DRRS_LOW_RR
141880. DRRS_MAX_RR
141881. DRRS_NOT_SUPPORTED
141882. DRR_UPDATE_LOCK_SEL
141883. DRR_UPDATE_LOCK_SEL_0
141884. DRR_UPDATE_LOCK_SEL_1
141885. DRR_UPDATE_LOCK_SEL_2
141886. DRR_UPDATE_LOCK_SEL_3
141887. DRR_UPDATE_LOCK_SEL_4
141888. DRR_UPDATE_LOCK_SEL_5
141889. DRS
141890. DRSELECT
141891. DRSHIFT
141892. DRSI
141893. DRSPPERR_F
141894. DRSPPERR_S
141895. DRSPPERR_V
141896. DRSR
141897. DRST_VOP
141898. DRT
141899. DRTRY
141900. DRTY
141901. DRUPDATE
141902. DRV260X_AC_CPLE_EN
141903. DRV260X_ANANLOG_IN
141904. DRV260X_AUDIOHAPTIC
141905. DRV260X_AUDIO_HAPTICS_FILTER_100HZ
141906. DRV260X_AUDIO_HAPTICS_FILTER_125HZ
141907. DRV260X_AUDIO_HAPTICS_FILTER_150HZ
141908. DRV260X_AUDIO_HAPTICS_FILTER_200HZ
141909. DRV260X_AUDIO_HAPTICS_MAX_IN_VOLT
141910. DRV260X_AUDIO_HAPTICS_MAX_OUT_VOLT
141911. DRV260X_AUDIO_HAPTICS_MIN_IN_VOLT
141912. DRV260X_AUDIO_HAPTICS_MIN_OUT_VOLT
141913. DRV260X_AUDIO_HAPTICS_PEAK_10MS
141914. DRV260X_AUDIO_HAPTICS_PEAK_20MS
141915. DRV260X_AUDIO_HAPTICS_PEAK_30MS
141916. DRV260X_AUDIO_HAPTICS_PEAK_40MS
141917. DRV260X_AUTOCAL_TIME_1000MS
141918. DRV260X_AUTOCAL_TIME_150MS
141919. DRV260X_AUTOCAL_TIME_250MS
141920. DRV260X_AUTOCAL_TIME_500MS
141921. DRV260X_AUTO_CAL
141922. DRV260X_A_TO_V_CTRL
141923. DRV260X_A_TO_V_MAX_INPUT
141924. DRV260X_A_TO_V_MAX_OUT
141925. DRV260X_A_TO_V_MIN_INPUT
141926. DRV260X_A_TO_V_MIN_OUT
141927. DRV260X_BEMF_GAIN_0
141928. DRV260X_BEMF_GAIN_1
141929. DRV260X_BEMF_GAIN_2
141930. DRV260X_BEMF_GAIN_3
141931. DRV260X_BIDIR_IN
141932. DRV260X_BLANK_TIME_150
141933. DRV260X_BLANK_TIME_225
141934. DRV260X_BLANK_TIME_45
141935. DRV260X_BLANK_TIME_75
141936. DRV260X_BRAKE_FACTOR_16
141937. DRV260X_BRAKE_FACTOR_2X
141938. DRV260X_BRAKE_FACTOR_3X
141939. DRV260X_BRAKE_FACTOR_4X
141940. DRV260X_BRAKE_FACTOR_6X
141941. DRV260X_BRAKE_FACTOR_8X
141942. DRV260X_BRAKE_FACTOR_DIS
141943. DRV260X_BRAKE_FACTOR_MASK
141944. DRV260X_BRAKE_OFF
141945. DRV260X_BRAKE_STABILIZER
141946. DRV260X_CAL_BACK_EMF
141947. DRV260X_CAL_COMP
141948. DRV260X_CTRL1
141949. DRV260X_CTRL2
141950. DRV260X_CTRL3
141951. DRV260X_CTRL4
141952. DRV260X_CTRL5
141953. DRV260X_DEF_OD_CLAMP_VOLT
141954. DRV260X_DEF_RATED_VOLT
141955. DRV260X_DIAGNOSTICS
141956. DRV260X_ERM_LIB_A
141957. DRV260X_ERM_LIB_B
141958. DRV260X_ERM_LIB_C
141959. DRV260X_ERM_LIB_D
141960. DRV260X_ERM_LIB_E
141961. DRV260X_ERM_LIB_F
141962. DRV260X_ERM_MODE
141963. DRV260X_ERM_OPEN_LOOP
141964. DRV260X_EXT_TRIGGER_EDGE
141965. DRV260X_EXT_TRIGGER_LEVEL
141966. DRV260X_FB_REG_ERM_MODE
141967. DRV260X_FB_REG_LRA_MODE
141968. DRV260X_FEEDBACK_CTRL
141969. DRV260X_GO
141970. DRV260X_GO_BIT
141971. DRV260X_IDISS_TIME_150
141972. DRV260X_IDISS_TIME_225
141973. DRV260X_IDISS_TIME_45
141974. DRV260X_IDISS_TIME_75
141975. DRV260X_INTERNAL_TRIGGER
141976. DRV260X_LIB_EMPTY
141977. DRV260X_LIB_LRA
141978. DRV260X_LIB_SEL
141979. DRV260X_LIB_SEL_100_140
141980. DRV260X_LIB_SEL_140_PLUS
141981. DRV260X_LIB_SEL_40_60
141982. DRV260X_LIB_SEL_60_80
141983. DRV260X_LIB_SEL_HIZ_DIS
141984. DRV260X_LIB_SEL_HIZ_EN
141985. DRV260X_LIB_SEL_HIZ_MASK
141986. DRV260X_LIB_SEL_MASK
141987. DRV260X_LIB_SEL_OD
141988. DRV260X_LIB_SEL_RAM
141989. DRV260X_LOOP_GAIN_HIGH
141990. DRV260X_LOOP_GAIN_LOW
141991. DRV260X_LOOP_GAIN_MED
141992. DRV260X_LOOP_GAIN_VERY_HIGH
141993. DRV260X_LRA_DRV_MODE
141994. DRV260X_LRA_LOOP_PERIOD
141995. DRV260X_LRA_MODE
141996. DRV260X_LRA_NO_CAL_MODE
141997. DRV260X_LRA_OPEN_LOOP
141998. DRV260X_LRA_RES_PERIOD
141999. DRV260X_MAX_REG
142000. DRV260X_MODE
142001. DRV260X_NG_THRESH_0
142002. DRV260X_NG_THRESH_2
142003. DRV260X_NG_THRESH_4
142004. DRV260X_NG_THRESH_8
142005. DRV260X_OD_CLAMP_VOLT
142006. DRV260X_OVERDRIVE_OFF
142007. DRV260X_PWM_ANALOG_IN
142008. DRV260X_RATED_VOLT
142009. DRV260X_RTP_UNSIGNED_DATA
142010. DRV260X_RT_PB_IN
142011. DRV260X_RT_PLAYBACK
142012. DRV260X_SAMP_TIME_150
142013. DRV260X_SAMP_TIME_200
142014. DRV260X_SAMP_TIME_250
142015. DRV260X_SAMP_TIME_300
142016. DRV260X_STANDBY
142017. DRV260X_STANDBY_MASK
142018. DRV260X_STARTUP_BOOST
142019. DRV260X_STATUS
142020. DRV260X_SUPPLY_COMP_DIS
142021. DRV260X_SUSTAIN_N_OFF
142022. DRV260X_SUSTAIN_P_OFF
142023. DRV260X_UNIDIR_IN
142024. DRV260X_VBAT_MON
142025. DRV260X_WV_SEQ_1
142026. DRV260X_WV_SEQ_2
142027. DRV260X_WV_SEQ_3
142028. DRV260X_WV_SEQ_4
142029. DRV260X_WV_SEQ_5
142030. DRV260X_WV_SEQ_6
142031. DRV260X_WV_SEQ_7
142032. DRV260X_WV_SEQ_8
142033. DRV2665_100_VPP_GAIN
142034. DRV2665_10_MS_IDLE_TOUT
142035. DRV2665_15_MS_IDLE_TOUT
142036. DRV2665_20_MS_IDLE_TOUT
142037. DRV2665_25_VPP_GAIN
142038. DRV2665_50_VPP_GAIN
142039. DRV2665_5_MS_IDLE_TOUT
142040. DRV2665_75_VPP_GAIN
142041. DRV2665_ANALOG_IN
142042. DRV2665_BOOST_EN
142043. DRV2665_CTRL_1
142044. DRV2665_CTRL_2
142045. DRV2665_DEV_RST
142046. DRV2665_DIGITAL_IN
142047. DRV2665_FIFO
142048. DRV2665_FIFO_EMPTY
142049. DRV2665_FIFO_FULL
142050. DRV2665_STANDBY
142051. DRV2665_STATUS
142052. DRV2667_100_VPP_GAIN
142053. DRV2667_1024_MS_ENV
142054. DRV2667_1280_MS_ENV
142055. DRV2667_128_MS_ENV
142056. DRV2667_1536_MS_ENV
142057. DRV2667_160_MS_ENV
142058. DRV2667_1792_MS_ENV
142059. DRV2667_192_MS_ENV
142060. DRV2667_2048_MS_ENV
142061. DRV2667_224_MS_ENV
142062. DRV2667_256_MS_ENV
142063. DRV2667_25_VPP_GAIN
142064. DRV2667_32_MS_ENV
142065. DRV2667_50_VPP_GAIN
142066. DRV2667_512_MS_ENV
142067. DRV2667_64_MS_ENV
142068. DRV2667_75_VPP_GAIN
142069. DRV2667_768_MS_ENV
142070. DRV2667_96_MS_ENV
142071. DRV2667_ANALOG_IN
142072. DRV2667_CTRL_1
142073. DRV2667_CTRL_2
142074. DRV2667_DEV_RST
142075. DRV2667_DIGITAL_IN
142076. DRV2667_FIFO
142077. DRV2667_GO
142078. DRV2667_MAX_REG
142079. DRV2667_NO_ENV
142080. DRV2667_PAGE
142081. DRV2667_PAGE_0
142082. DRV2667_PAGE_1
142083. DRV2667_PAGE_2
142084. DRV2667_PAGE_3
142085. DRV2667_PAGE_4
142086. DRV2667_PAGE_5
142087. DRV2667_PAGE_6
142088. DRV2667_PAGE_7
142089. DRV2667_PAGE_8
142090. DRV2667_RAM_AMP
142091. DRV2667_RAM_DURATION
142092. DRV2667_RAM_ENVELOPE
142093. DRV2667_RAM_FREQ
142094. DRV2667_RAM_HDR_SZ
142095. DRV2667_RAM_REPEAT_CT
142096. DRV2667_RAM_START_HI
142097. DRV2667_RAM_START_LO
142098. DRV2667_RAM_STOP_HI
142099. DRV2667_RAM_STOP_LO
142100. DRV2667_STANDBY
142101. DRV2667_STATUS
142102. DRV2667_WV_SEQ_0
142103. DRV2667_WV_SEQ_1
142104. DRV2667_WV_SEQ_2
142105. DRV2667_WV_SEQ_3
142106. DRV2667_WV_SEQ_4
142107. DRV2667_WV_SEQ_5
142108. DRV2667_WV_SEQ_6
142109. DRV2667_WV_SEQ_7
142110. DRVCRA
142111. DRVCRB
142112. DRVDESC
142113. DRVERLYINT
142114. DRVERLY_TU
142115. DRVERLY_US
142116. DRVINFO_SZ
142117. DRVNAME
142118. DRVPFX
142119. DRVRTYPE_HPE
142120. DRVRTYPE_MBOX
142121. DRVR_DRVRBAR_ENABLE
142122. DRVR_LOGIC_CLK_DIV
142123. DRVR_LOGIC_CLK_EN
142124. DRVR_RST
142125. DRVSTAT
142126. DRVSTAT_INFO
142127. DRVSTAT_RX
142128. DRVSTAT_RX_INFO
142129. DRVSTAT_TX
142130. DRVSTAT_TX_INFO
142131. DRVVBUS_FORCE
142132. DRVVBUS_OVERRIDE
142133. DRV_ACTIVE
142134. DRV_ATTR
142135. DRV_AUTHOR
142136. DRV_BASE
142137. DRV_BASE1
142138. DRV_BASE2
142139. DRV_BUF_FLUSH
142140. DRV_BYP
142141. DRV_CIPHER_BITLOCKER
142142. DRV_CIPHER_CBC
142143. DRV_CIPHER_CBC_CTS
142144. DRV_CIPHER_CBC_MAC
142145. DRV_CIPHER_CCM
142146. DRV_CIPHER_CMAC
142147. DRV_CIPHER_CTR
142148. DRV_CIPHER_ECB
142149. DRV_CIPHER_ESSIV
142150. DRV_CIPHER_GCTR
142151. DRV_CIPHER_NULL_MODE
142152. DRV_CIPHER_OFB
142153. DRV_CIPHER_RESERVE32B
142154. DRV_CIPHER_XCBC_MAC
142155. DRV_CIPHER_XTS
142156. DRV_COPYRIGHT
142157. DRV_CRYPTO_ALG_AEAD
142158. DRV_CRYPTO_ALG_AES
142159. DRV_CRYPTO_ALG_BYPASS
142160. DRV_CRYPTO_ALG_C2
142161. DRV_CRYPTO_ALG_DES
142162. DRV_CRYPTO_ALG_HASH
142163. DRV_CRYPTO_ALG_HMAC
142164. DRV_CRYPTO_ALG_NULL
142165. DRV_CRYPTO_ALG_NUM
142166. DRV_CRYPTO_ALG_RESERVE32B
142167. DRV_CRYPTO_DIRECTION_DECRYPT
142168. DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT
142169. DRV_CRYPTO_DIRECTION_ENCRYPT
142170. DRV_CRYPTO_DIRECTION_NULL
142171. DRV_CRYPTO_DIRECTION_RESERVE32B
142172. DRV_CTL_CTXTBL_WR_CMD
142173. DRV_CTL_CTX_WR_CMD
142174. DRV_CTL_IO_RD_CMD
142175. DRV_CTL_IO_WR_CMD
142176. DRV_CTL_ISCSI_STOPPED_CMD
142177. DRV_CTL_RET_L2_SPQ_CREDIT_CMD
142178. DRV_CTL_RET_L5_SPQ_CREDIT_CMD
142179. DRV_CTL_START_L2_CMD
142180. DRV_CTL_STOP_L2_CMD
142181. DRV_CTL_ULP_REGISTER_CMD
142182. DRV_CTL_ULP_UNREGISTER_CMD
142183. DRV_DCMD_POLLED_MODE
142184. DRV_DCMD_SKIP_REFIRE
142185. DRV_DESC
142186. DRV_DESCRIPTION
142187. DRV_DUMP_CSTORM_WAITP_ADDRESS
142188. DRV_DUMP_TSTORM_WAITP_ADDRESS
142189. DRV_DUMP_USTORM_WAITP_ADDRESS
142190. DRV_DUMP_XSTORM_WAITP_ADDRESS
142191. DRV_ENGINE_AES
142192. DRV_ENGINE_DES
142193. DRV_ENGINE_DOUT
142194. DRV_ENGINE_HASH
142195. DRV_ENGINE_NULL
142196. DRV_ENGINE_RC4
142197. DRV_ENGINE_RESERVE32B
142198. DRV_EXT
142199. DRV_EXTRAVERSION
142200. DRV_FIXED
142201. DRV_FLAGS_CAPABILITIES_LOADED_FCOE
142202. DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
142203. DRV_FLAGS_CAPABILITIES_LOADED_L2
142204. DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED
142205. DRV_FLAGS_DCB_CONFIGURATION_ABORTED
142206. DRV_FLAGS_DCB_CONFIGURED
142207. DRV_FLAGS_DCB_MFW_CONFIGURED
142208. DRV_FLAGS_MTU_MASK
142209. DRV_FLAGS_MTU_SHIFT
142210. DRV_FLAGS_PORT_MASK
142211. DRV_GRP0
142212. DRV_GRP1
142213. DRV_GRP2
142214. DRV_GRP3
142215. DRV_GRP4
142216. DRV_GRP_MAX
142217. DRV_HASH_CBC_MAC
142218. DRV_HASH_CMAC
142219. DRV_HASH_HW_GHASH
142220. DRV_HASH_HW_MD5
142221. DRV_HASH_HW_RESERVE32B
142222. DRV_HASH_HW_SHA1
142223. DRV_HASH_HW_SHA224
142224. DRV_HASH_HW_SHA256
142225. DRV_HASH_HW_SHA384
142226. DRV_HASH_HW_SHA512
142227. DRV_HASH_HW_SM3
142228. DRV_HASH_MD5
142229. DRV_HASH_MODE_NUM
142230. DRV_HASH_NULL
142231. DRV_HASH_RESERVE32B
142232. DRV_HASH_SHA1
142233. DRV_HASH_SHA224
142234. DRV_HASH_SHA256
142235. DRV_HASH_SHA384
142236. DRV_HASH_SHA512
142237. DRV_HASH_SM3
142238. DRV_HASH_XCBC_MAC
142239. DRV_IBIAS_CLK_SHIFT
142240. DRV_IBIAS_D0_SHIFT
142241. DRV_IBIAS_D1_SHIFT
142242. DRV_IBIAS_D2_SHIFT
142243. DRV_ID_DRV_INIT_HW_FLAG
142244. DRV_ID_DRV_INIT_HW_MASK
142245. DRV_ID_DRV_INIT_HW_SHIFT
142246. DRV_ID_DRV_TYPE_LINUX
142247. DRV_ID_DRV_TYPE_MASK
142248. DRV_ID_DRV_TYPE_SHIFT
142249. DRV_ID_DRV_TYPE_UNKNOWN
142250. DRV_ID_MCP_HSI_VER_CURRENT
142251. DRV_ID_MCP_HSI_VER_MASK
142252. DRV_ID_MCP_HSI_VER_SHIFT
142253. DRV_ID_PDA_COMP_VER_MASK
142254. DRV_ID_PDA_COMP_VER_SHIFT
142255. DRV_IMP_CLK_SHIFT
142256. DRV_IMP_D0_SHIFT
142257. DRV_IMP_D1_SHIFT
142258. DRV_IMP_D2_SHIFT
142259. DRV_IMP_EN_SHIFT
142260. DRV_INACTIVE
142261. DRV_INFO
142262. DRV_INFO_CONTROL_OP_CODE_MASK
142263. DRV_INFO_CONTROL_OP_CODE_SHIFT
142264. DRV_INFO_CONTROL_VER_MASK
142265. DRV_INFO_CONTROL_VER_SHIFT
142266. DRV_INFO_CUR_VER
142267. DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
142268. DRV_INNER_RD
142269. DRV_INNER_WR
142270. DRV_IOCTL
142271. DRV_KERN
142272. DRV_MAC_LEARN
142273. DRV_MB_PARAM_BIST_CLOCK_TEST
142274. DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX
142275. DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES
142276. DRV_MB_PARAM_BIST_RC_FAILED
142277. DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER
142278. DRV_MB_PARAM_BIST_RC_PASSED
142279. DRV_MB_PARAM_BIST_RC_UNKNOWN
142280. DRV_MB_PARAM_BIST_REGISTER_TEST
142281. DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK
142282. DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT
142283. DRV_MB_PARAM_BIST_TEST_INDEX_MASK
142284. DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT
142285. DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK
142286. DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT
142287. DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK
142288. DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT
142289. DRV_MB_PARAM_DCBX_NOTIFY_MASK
142290. DRV_MB_PARAM_DCBX_NOTIFY_SHIFT
142291. DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK
142292. DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET
142293. DRV_MB_PARAM_ESWITCH_MODE_MASK
142294. DRV_MB_PARAM_ESWITCH_MODE_NONE
142295. DRV_MB_PARAM_ESWITCH_MODE_VEB
142296. DRV_MB_PARAM_ESWITCH_MODE_VEPA
142297. DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK
142298. DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE
142299. DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK
142300. DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET
142301. DRV_MB_PARAM_LLDP_SEND_MASK
142302. DRV_MB_PARAM_LLDP_SEND_SHIFT
142303. DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK
142304. DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT
142305. DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK
142306. DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT
142307. DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK
142308. DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT
142309. DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK
142310. DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT
142311. DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK
142312. DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT
142313. DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK
142314. DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT
142315. DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK
142316. DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT
142317. DRV_MB_PARAM_NVM_LEN_OFFSET
142318. DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI
142319. DRV_MB_PARAM_OV_CURR_CFG_MASK
142320. DRV_MB_PARAM_OV_CURR_CFG_NONE
142321. DRV_MB_PARAM_OV_CURR_CFG_OS
142322. DRV_MB_PARAM_OV_CURR_CFG_OTHER
142323. DRV_MB_PARAM_OV_CURR_CFG_SHIFT
142324. DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC
142325. DRV_MB_PARAM_OV_MTU_SIZE_MASK
142326. DRV_MB_PARAM_OV_MTU_SIZE_SHIFT
142327. DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK
142328. DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK
142329. DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK
142330. DRV_MB_PARAM_OV_STORM_FW_VER_MASK
142331. DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK
142332. DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT
142333. DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK
142334. DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT
142335. DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK
142336. DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT
142337. DRV_MB_PARAM_SET_LED_MODE_OFF
142338. DRV_MB_PARAM_SET_LED_MODE_ON
142339. DRV_MB_PARAM_SET_LED_MODE_OPER
142340. DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK
142341. DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET
142342. DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK
142343. DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET
142344. DRV_MB_PARAM_TRANSCEIVER_PORT_MASK
142345. DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET
142346. DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK
142347. DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET
142348. DRV_MB_PARAM_UNLOAD_WOL_DISABLED
142349. DRV_MB_PARAM_UNLOAD_WOL_ENABLED
142350. DRV_MB_PARAM_UNLOAD_WOL_MCP
142351. DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN
142352. DRV_MB_PARAM_WOL_DEFAULT
142353. DRV_MB_PARAM_WOL_DISABLED
142354. DRV_MB_PARAM_WOL_ENABLED
142355. DRV_MB_PARAM_WOL_MASK
142356. DRV_MB_RD
142357. DRV_MB_WR
142358. DRV_MDIONAME
142359. DRV_MODULE_DESC
142360. DRV_MODULE_NAME
142361. DRV_MODULE_RELDATE
142362. DRV_MODULE_SYM
142363. DRV_MODULE_VERSION
142364. DRV_MODULE_VER_MAJOR
142365. DRV_MODULE_VER_MINOR
142366. DRV_MODULE_VER_SUBMINOR
142367. DRV_MSG_CODE_AFEX_DRIVER_SETMAC
142368. DRV_MSG_CODE_AFEX_LISTGET_ACK
142369. DRV_MSG_CODE_AFEX_LISTSET_ACK
142370. DRV_MSG_CODE_AFEX_STATSGET_ACK
142371. DRV_MSG_CODE_AFEX_VIFSET_ACK
142372. DRV_MSG_CODE_BIST_TEST
142373. DRV_MSG_CODE_BW_UPDATE_ACK
142374. DRV_MSG_CODE_CANCEL_LOAD_REQ
142375. DRV_MSG_CODE_CFG_PF_VFS_MSIX
142376. DRV_MSG_CODE_CFG_VF_MSIX
142377. DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG
142378. DRV_MSG_CODE_DCBX_PMF_DRV_OK
142379. DRV_MSG_CODE_DCC_FAILURE
142380. DRV_MSG_CODE_DCC_OK
142381. DRV_MSG_CODE_DIAG_ENTER_REQ
142382. DRV_MSG_CODE_DIAG_EXIT_REQ
142383. DRV_MSG_CODE_DRV_INFO_ACK
142384. DRV_MSG_CODE_DRV_INFO_NACK
142385. DRV_MSG_CODE_EEE_RESULTS_ACK
142386. DRV_MSG_CODE_FEATURE_SUPPORT
142387. DRV_MSG_CODE_GET_CURR_KEY
142388. DRV_MSG_CODE_GET_ENGINE_CONFIG
142389. DRV_MSG_CODE_GET_MANUF_KEY
142390. DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT
142391. DRV_MSG_CODE_GET_NVM_CFG_OPTION
142392. DRV_MSG_CODE_GET_OEM_UPDATES
142393. DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL
142394. DRV_MSG_CODE_GET_PPFID_BITMAP
142395. DRV_MSG_CODE_GET_STATS
142396. DRV_MSG_CODE_GET_TLV_DONE
142397. DRV_MSG_CODE_GET_UPGRADE_KEY
142398. DRV_MSG_CODE_GET_VMAC
142399. DRV_MSG_CODE_INITIATE_FLR
142400. DRV_MSG_CODE_INITIATE_PF_FLR
142401. DRV_MSG_CODE_INIT_HW
142402. DRV_MSG_CODE_INIT_PHY
142403. DRV_MSG_CODE_LINK_RESET
142404. DRV_MSG_CODE_LINK_STATUS_CHANGED
142405. DRV_MSG_CODE_LOAD_DONE
142406. DRV_MSG_CODE_LOAD_L2B_PRAM
142407. DRV_MSG_CODE_LOAD_REQ
142408. DRV_MSG_CODE_LOAD_REQ_FORCE_LFA
142409. DRV_MSG_CODE_LOAD_REQ_WITH_LFA
142410. DRV_MSG_CODE_MASK
142411. DRV_MSG_CODE_MASK_PARITIES
142412. DRV_MSG_CODE_MCP_HALT
142413. DRV_MSG_CODE_MCP_RESET
142414. DRV_MSG_CODE_NIG_DRAIN
142415. DRV_MSG_CODE_NVM_GET_FILE_ATT
142416. DRV_MSG_CODE_NVM_PUT_FILE_BEGIN
142417. DRV_MSG_CODE_NVM_PUT_FILE_DATA
142418. DRV_MSG_CODE_NVM_READ_NVRAM
142419. DRV_MSG_CODE_NVM_WRITE_NVRAM
142420. DRV_MSG_CODE_OEM_FAILURE
142421. DRV_MSG_CODE_OEM_OK
142422. DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE
142423. DRV_MSG_CODE_OEM_UPDATE_SVID_OK
142424. DRV_MSG_CODE_OS_WOL
142425. DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS
142426. DRV_MSG_CODE_OV_UPDATE_BUS_NUM
142427. DRV_MSG_CODE_OV_UPDATE_CURR_CFG
142428. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE
142429. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE
142430. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED
142431. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING
142432. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK
142433. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED
142434. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT
142435. DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN
142436. DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE
142437. DRV_MSG_CODE_OV_UPDATE_MTU
142438. DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER
142439. DRV_MSG_CODE_OV_UPDATE_WOL
142440. DRV_MSG_CODE_RESOURCE_CMD
142441. DRV_MSG_CODE_RMMOD
142442. DRV_MSG_CODE_SET_DCBX
142443. DRV_MSG_CODE_SET_LED_MODE
142444. DRV_MSG_CODE_SET_MF_BW
142445. DRV_MSG_CODE_SET_MF_BW_ACK
142446. DRV_MSG_CODE_SET_MF_BW_MAX_MASK
142447. DRV_MSG_CODE_SET_MF_BW_MIN_MASK
142448. DRV_MSG_CODE_SET_NVM_CFG_OPTION
142449. DRV_MSG_CODE_SET_VERSION
142450. DRV_MSG_CODE_SET_VMAC
142451. DRV_MSG_CODE_STATS_TYPE_FCOE
142452. DRV_MSG_CODE_STATS_TYPE_ISCSI
142453. DRV_MSG_CODE_STATS_TYPE_LAN
142454. DRV_MSG_CODE_STATS_TYPE_RDMA
142455. DRV_MSG_CODE_S_TAG_UPDATE_ACK
142456. DRV_MSG_CODE_TRANSCEIVER_READ
142457. DRV_MSG_CODE_UNLOAD_DONE
142458. DRV_MSG_CODE_UNLOAD_REQ
142459. DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
142460. DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
142461. DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
142462. DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
142463. DRV_MSG_CODE_VALIDATE_KEY
142464. DRV_MSG_CODE_VF_DISABLED_DONE
142465. DRV_MSG_CODE_VMAC_TYPE_MAC
142466. DRV_MSG_CODE_VMAC_TYPE_MASK
142467. DRV_MSG_CODE_VMAC_TYPE_SHIFT
142468. DRV_MSG_CODE_VMAC_TYPE_WWNN
142469. DRV_MSG_CODE_VMAC_TYPE_WWPN
142470. DRV_MSG_CODE_VRFY_AFEX_SUPPORTED
142471. DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL
142472. DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL
142473. DRV_MSG_GET_RESOURCE_ALLOC_MSG
142474. DRV_MSG_SEQ_NUMBER_MASK
142475. DRV_MSG_SET_RESOURCE_VALUE_MSG
142476. DRV_NAME
142477. DRV_NAME_ALCOR_PCI
142478. DRV_NAME_ALCOR_PCI_MS
142479. DRV_NAME_ALCOR_PCI_SDMMC
142480. DRV_NAME_FOR_FW
142481. DRV_NAME_RTSX_PCI
142482. DRV_NAME_RTSX_PCI_MS
142483. DRV_NAME_RTSX_PCI_SDMMC
142484. DRV_NCPT_MASK
142485. DRV_NCPT_SHIFT
142486. DRV_NOP
142487. DRV_NUM_TCS_MASK
142488. DRV_NUM_TCS_SHIFT
142489. DRV_PCM_STATE_CHANGE
142490. DRV_PERS_ETHERNET
142491. DRV_PERS_FCOE
142492. DRV_PERS_ISCSI
142493. DRV_PG
142494. DRV_PG_EXT
142495. DRV_PINGROUP
142496. DRV_PINGROUP_ENTRY_Y
142497. DRV_PINGROUP_REG
142498. DRV_PINGROUP_REG_A
142499. DRV_PKT_DELAY_TO_FW_MAX
142500. DRV_PREFIX
142501. DRV_PRNT_CHLD_CONFIG
142502. DRV_PROCNAME
142503. DRV_PROJECT
142504. DRV_PTR
142505. DRV_PULSE_ALWAYS_ALIVE
142506. DRV_PULSE_PERIOD_MS
142507. DRV_PULSE_SEQ_MASK
142508. DRV_PULSE_SYSTEM_TIME_MASK
142509. DRV_RELDATE
142510. DRV_RES_SEL
142511. DRV_RMT_INDICATION
142512. DRV_ROLE_KDUMP
142513. DRV_ROLE_NONE
142514. DRV_ROLE_OS
142515. DRV_ROLE_PREBOOT
142516. DRV_S3C2410
142517. DRV_S3C2412
142518. DRV_SLEWRATE
142519. DRV_STATE_START
142520. DRV_STATE_START_DONE
142521. DRV_STATE_SUSPEND
142522. DRV_STATE_UNLOAD
142523. DRV_STATE_UNLOAD_DONE
142524. DRV_STATE_WOL
142525. DRV_STATUS_AFEX_EVENT_MASK
142526. DRV_STATUS_AFEX_LISTGET_REQ
142527. DRV_STATUS_AFEX_LISTSET_REQ
142528. DRV_STATUS_AFEX_STATSGET_REQ
142529. DRV_STATUS_AFEX_VIFSET_REQ
142530. DRV_STATUS_DCBX_EVENT_MASK
142531. DRV_STATUS_DCBX_NEGOTIATION_RESULTS
142532. DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
142533. DRV_STATUS_DCC_CHANGE_MAC_ADDRESS
142534. DRV_STATUS_DCC_DISABLE_ENABLE_PF
142535. DRV_STATUS_DCC_EVENT_MASK
142536. DRV_STATUS_DCC_RESERVED1
142537. DRV_STATUS_DCC_SET_PRIORITY
142538. DRV_STATUS_DCC_SET_PROTOCOL
142539. DRV_STATUS_DRV_INFO_REQ
142540. DRV_STATUS_EEE_NEGOTIATION_RESULTS
142541. DRV_STATUS_LINK_EVENT
142542. DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
142543. DRV_STATUS_OEM_DISABLE_ENABLE_PF
142544. DRV_STATUS_OEM_EVENT_MASK
142545. DRV_STATUS_OEM_UPDATE_SVID
142546. DRV_STATUS_PMF
142547. DRV_STATUS_SET_MF_BW
142548. DRV_STATUS_VF_DISABLED
142549. DRV_STRENGTH_OFFSET
142550. DRV_STRENGTH_SEL_MASK
142551. DRV_STRENGTH_SEL_OFF
142552. DRV_STRING
142553. DRV_SUMMARY
142554. DRV_TLV_ABORT_TASK_SETS_ISSUED
142555. DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID
142556. DRV_TLV_ABTS_1_TIMESTAMP
142557. DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID
142558. DRV_TLV_ABTS_2_TIMESTAMP
142559. DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID
142560. DRV_TLV_ABTS_3_TIMESTAMP
142561. DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID
142562. DRV_TLV_ABTS_4_TIMESTAMP
142563. DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID
142564. DRV_TLV_ABTS_5_TIMESTAMP
142565. DRV_TLV_ABTS_ACCS_RECEIVED
142566. DRV_TLV_ABTS_RJTS_RECEIVED
142567. DRV_TLV_ABTS_SENT_COUNT
142568. DRV_TLV_ACCS_ISSUED
142569. DRV_TLV_ACCS_RECEIVED
142570. DRV_TLV_ADDITIONAL_MAC_ADDR_1
142571. DRV_TLV_ADDITIONAL_MAC_ADDR_2
142572. DRV_TLV_AUTHENTICATION_METHOD
142573. DRV_TLV_BOOT_TYPE
142574. DRV_TLV_CLP_STR
142575. DRV_TLV_CLP_STR_CTD
142576. DRV_TLV_CODE_VIOLATION_ERROR_COUNT
142577. DRV_TLV_CORRECTABLE_ERROR_MASK
142578. DRV_TLV_CORRECTABLE_ERROR_STATUS
142579. DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID
142580. DRV_TLV_CRC_ERROR_1_TIMESTAMP
142581. DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID
142582. DRV_TLV_CRC_ERROR_2_TIMESTAMP
142583. DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID
142584. DRV_TLV_CRC_ERROR_3_TIMESTAMP
142585. DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID
142586. DRV_TLV_CRC_ERROR_4_TIMESTAMP
142587. DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID
142588. DRV_TLV_CRC_ERROR_5_TIMESTAMP
142589. DRV_TLV_CRC_ERROR_COUNT
142590. DRV_TLV_CR_TOV
142591. DRV_TLV_DATA_DIGEST_FLAG_ENABLED
142592. DRV_TLV_DEVICE_CPU_CORES_UTILIZATION
142593. DRV_TLV_DISPARITY_ERROR_COUNT
142594. DRV_TLV_EOFA_COUNT
142595. DRV_TLV_EOFNI_COUNT
142596. DRV_TLV_E_D_TOV
142597. DRV_TLV_FCOE_BOOT_PROGRESS
142598. DRV_TLV_FCOE_RX_BYTES_RECEIVED
142599. DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH
142600. DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE
142601. DRV_TLV_FCOE_RX_FRAMES_RECEIVED
142602. DRV_TLV_FCOE_TX_BYTES_SENT
142603. DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH
142604. DRV_TLV_FCOE_TX_FRAMES_SENT
142605. DRV_TLV_FDISCS_SENT_COUNT
142606. DRV_TLV_FDISC_ACCS_RECEIVED
142607. DRV_TLV_FDISC_RJTS_RECEIVED
142608. DRV_TLV_FEATURE_FLAGS
142609. DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE
142610. DRV_TLV_FLEX_NIC_OUTER_VLAN_ID
142611. DRV_TLV_HEADER_DIGEST_FLAG_ENABLED
142612. DRV_TLV_IOV_OFFLOAD
142613. DRV_TLV_ISCSI_BOOT_PROGRESS
142614. DRV_TLV_ISCSI_BOOT_TARGET_PORTAL
142615. DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED
142616. DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED
142617. DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
142618. DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT
142619. DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1
142620. DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2
142621. DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3
142622. DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4
142623. DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP
142624. DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1
142625. DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2
142626. DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3
142627. DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4
142628. DRV_TLV_LAST_FLOGI_RJT
142629. DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP
142630. DRV_TLV_LAST_FLOGI_TIMESTAMP
142631. DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1
142632. DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2
142633. DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3
142634. DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4
142635. DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED
142636. DRV_TLV_LINK_FAILURE_COUNT
142637. DRV_TLV_LIP_RECEIVED_COUNT
142638. DRV_TLV_LIP_SENT_COUNT
142639. DRV_TLV_LOCAL_ADMIN_ADDR
142640. DRV_TLV_LOGOS_ISSUED
142641. DRV_TLV_LOGOS_RECEIVED
142642. DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID
142643. DRV_TLV_LOGO_1_TIMESTAMP
142644. DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID
142645. DRV_TLV_LOGO_2_TIMESTAMP
142646. DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID
142647. DRV_TLV_LOGO_3_TIMESTAMP
142648. DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID
142649. DRV_TLV_LOGO_4_TIMESTAMP
142650. DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID
142651. DRV_TLV_LOGO_5_TIMESTAMP
142652. DRV_TLV_LOGO_ACCS_RECEIVED
142653. DRV_TLV_LOGO_RJTS_RECEIVED
142654. DRV_TLV_LOSS_OF_SIGNAL_ERRORS
142655. DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT
142656. DRV_TLV_LRR_COUNT
142657. DRV_TLV_LR_COUNT
142658. DRV_TLV_LSO_MAX_OFFLOAD_SIZE
142659. DRV_TLV_LSO_MIN_SEGMENT_COUNT
142660. DRV_TLV_LUN_RESETS_ISSUED
142661. DRV_TLV_MAX_FRAME_SIZE
142662. DRV_TLV_NCSI_RX_BYTES_RECEIVED
142663. DRV_TLV_NCSI_TX_BYTES_SENT
142664. DRV_TLV_NOS_RECEIVED_COUNT
142665. DRV_TLV_NOS_SENT_COUNT
142666. DRV_TLV_NPIV_ENABLED
142667. DRV_TLV_NPIV_STATE
142668. DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4
142669. DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6
142670. DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG
142671. DRV_TLV_NUM_OF_NPIV_IDS
142672. DRV_TLV_OLS_COUNT
142673. DRV_TLV_OS_DRIVER_STATES
142674. DRV_TLV_PCIE_BUS_RX_UTILIZATION
142675. DRV_TLV_PCIE_BUS_TX_UTILIZATION
142676. DRV_TLV_PCI_ERRORS_AECC_REGISTER
142677. DRV_TLV_PCI_ERRORS_CAP_ID
142678. DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH
142679. DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE
142680. DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE
142681. DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH
142682. DRV_TLV_PF_RX_FRAMES_RECEIVED
142683. DRV_TLV_PF_TX_FRAMES_SENT
142684. DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID
142685. DRV_TLV_PLOGI_1_ACC_TIMESTAMP
142686. DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID
142687. DRV_TLV_PLOGI_1_TIMESTAMP
142688. DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID
142689. DRV_TLV_PLOGI_2_ACC_TIMESTAMP
142690. DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID
142691. DRV_TLV_PLOGI_2_TIMESTAMP
142692. DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID
142693. DRV_TLV_PLOGI_3_ACC_TIMESTAMP
142694. DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID
142695. DRV_TLV_PLOGI_3_TIMESTAMP
142696. DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID
142697. DRV_TLV_PLOGI_4_ACC_TIMESTAMP
142698. DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID
142699. DRV_TLV_PLOGI_4_TIMESTAMP
142700. DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID
142701. DRV_TLV_PLOGI_5_ACC_TIMESTAMP
142702. DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID
142703. DRV_TLV_PLOGI_5_TIMESTAMP
142704. DRV_TLV_PLOGI_ACCS_RECEIVED
142705. DRV_TLV_PLOGI_RJTS_RECEIVED
142706. DRV_TLV_PLOGI_SENT_COUNT
142707. DRV_TLV_PORT_ALIAS
142708. DRV_TLV_PORT_STATE
142709. DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT
142710. DRV_TLV_PRLIS_ISSUED
142711. DRV_TLV_PROMISCUOUS_MODE
142712. DRV_TLV_PXE_BOOT_PROGRESS
142713. DRV_TLV_QOS_PRIORITY_PER_802_1P
142714. DRV_TLV_RSCNS_RECEIVED
142715. DRV_TLV_RX_BROADCAST_PACKETS
142716. DRV_TLV_RX_BYTES_RECEIVED
142717. DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH
142718. DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE
142719. DRV_TLV_RX_DISCARDS
142720. DRV_TLV_RX_ERRORS
142721. DRV_TLV_RX_FRAMES_RECEIVED
142722. DRV_TLV_RX_QUEUES_EMPTY
142723. DRV_TLV_RX_QUEUES_FULL
142724. DRV_TLV_R_A_TOV
142725. DRV_TLV_R_T_TOV
142726. DRV_TLV_SCSI_CHECK_1_TIMESTAMP
142727. DRV_TLV_SCSI_CHECK_2_TIMESTAMP
142728. DRV_TLV_SCSI_CHECK_3_TIMESTAMP
142729. DRV_TLV_SCSI_CHECK_4_TIMESTAMP
142730. DRV_TLV_SCSI_CHECK_5_TIMESTAMP
142731. DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ
142732. DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ
142733. DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ
142734. DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ
142735. DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ
142736. DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT
142737. DRV_TLV_SCSI_STATUS_BUSY_COUNT
142738. DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT
142739. DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT
142740. DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT
142741. DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT
142742. DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT
142743. DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT
142744. DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT
142745. DRV_TLV_SCSI_TO
142746. DRV_TLV_SWITCH_FW_VER
142747. DRV_TLV_SWITCH_MODEL
142748. DRV_TLV_SWITCH_NAME
142749. DRV_TLV_SWITCH_PORT_ID
142750. DRV_TLV_SWITCH_PORT_NUM
142751. DRV_TLV_TARGET_LLMNR_ENABLED
142752. DRV_TLV_TPRLOS_SENT
142753. DRV_TLV_TX_BROADCAST_PACKETS
142754. DRV_TLV_TX_BYTES_SENT
142755. DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE
142756. DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH
142757. DRV_TLV_TX_DISCARDS
142758. DRV_TLV_TX_ERRORS
142759. DRV_TLV_TX_FRAMES_SENT
142760. DRV_TLV_TX_QUEUES_EMPTY
142761. DRV_TLV_TX_QUEUES_FULL
142762. DRV_TLV_UNCORRECTABLE_ERROR_MASK
142763. DRV_TLV_UNCORRECTABLE_ERROR_STATUS
142764. DRV_TLV_VENDOR_NAME
142765. DRV_TYPE_IO_1V8_3V0_AUTO
142766. DRV_TYPE_IO_1V8_ONLY
142767. DRV_TYPE_IO_1V8_OR_3V0
142768. DRV_TYPE_IO_3V3_ONLY
142769. DRV_TYPE_IO_DEFAULT
142770. DRV_TYPE_MAX
142771. DRV_UNLOADED
142772. DRV_VER
142773. DRV_VERSION
142774. DRV_VERSION_BUILD
142775. DRV_VERSION_MAJOR
142776. DRV_VERSION_MINOR
142777. DRV_VER_MAJ
142778. DRV_VER_MIN
142779. DRV_VER_NOT_LOADED
142780. DRV_VER_UPD
142781. DRWE
142782. DRWTIM0
142783. DRWTIM1
142784. DRWTIM2
142785. DRWTIM23
142786. DRWTIM3
142787. DRX
142788. DRX39XXJ_H
142789. DRX39XX_MAIN_FIRMWARE
142790. DRXDAPFASI_LONG_ADDR_ALLOWED
142791. DRXDAPFASI_SHORT_ADDR_ALLOWED
142792. DRXDAP_FASI_ADDR2BANK
142793. DRXDAP_FASI_ADDR2BLOCK
142794. DRXDAP_FASI_ADDR2OFFSET
142795. DRXDAP_FASI_BROADCAST
142796. DRXDAP_FASI_CLEARCRC
142797. DRXDAP_FASI_FLAGS
142798. DRXDAP_FASI_LONG_FORMAT
142799. DRXDAP_FASI_MODEFLAGS
142800. DRXDAP_FASI_MULTI_MASTER
142801. DRXDAP_FASI_OFFSET_TOO_LARGE
142802. DRXDAP_FASI_RMW
142803. DRXDAP_FASI_SHORT_FORMAT
142804. DRXDAP_FASI_SINGLE_MASTER
142805. DRXDAP_FASI_SMM_SWITCH
142806. DRXDAP_MAX_RCHUNKSIZE
142807. DRXDAP_MAX_WCHUNKSIZE
142808. DRXDAP_MAX_WCHUNKSIZE_MIN
142809. DRXDAP_SINGLE_MASTER
142810. DRXD_BANDWIDTH_6MHZ_IN_HZ
142811. DRXD_BANDWIDTH_7MHZ_IN_HZ
142812. DRXD_BANDWIDTH_8MHZ_IN_HZ
142813. DRXD_DEF_AG_AGC_SIO
142814. DRXD_DEF_AG_PWD_CONSUMER
142815. DRXD_DEF_AG_PWD_PRO
142816. DRXD_FE_CTRL_MAX
142817. DRXD_MAX_RETRIES
142818. DRXD_OSCDEV_DONT_SCAN
142819. DRXD_OSCDEV_DO_SCAN
142820. DRXD_OSCDEV_STEP
142821. DRXD_PLL_DTT7520X
142822. DRXD_PLL_MT3X0823
142823. DRXD_PLL_NONE
142824. DRXD_SCAN_TIMEOUT
142825. DRXD_STARTED
142826. DRXD_STOPPED
142827. DRXD_UNINITIALIZED
142828. DRXD_init
142829. DRXD_status
142830. DRXJ_16TO8
142831. DRXJ_8TO16
142832. DRXJ_AGC_SNS
142833. DRXJ_AGC_TOP
142834. DRXJ_ATTR_BTSC_DETECT
142835. DRXJ_ATV_CHANGED_COEF
142836. DRXJ_ATV_CHANGED_NOISE_FLT
142837. DRXJ_ATV_CHANGED_OUTPUT
142838. DRXJ_ATV_CHANGED_PEAK_FLT
142839. DRXJ_ATV_CHANGED_SIF_ATT
142840. DRXJ_AUD_MAX_FM_DEVIATION
142841. DRXJ_AUD_MAX_NICAM_PRESCALE
142842. DRXJ_AUD_MAX_WAITTIME
142843. DRXJ_CFG_ACCUM_CR_RS_CW_ERR
142844. DRXJ_CFG_AFE_GAIN
142845. DRXJ_CFG_AGC_IF
142846. DRXJ_CFG_AGC_INTERNAL
142847. DRXJ_CFG_AGC_RF
142848. DRXJ_CFG_ATV_AGC_STATUS
142849. DRXJ_CFG_ATV_EQU_COEF
142850. DRXJ_CFG_ATV_MISC
142851. DRXJ_CFG_ATV_OUTPUT
142852. DRXJ_CFG_FEC_MERS_SEQ_COUNT
142853. DRXJ_CFG_HW_CFG
142854. DRXJ_CFG_MAX
142855. DRXJ_CFG_MPEG_OUTPUT_MISC
142856. DRXJ_CFG_OOB_LO_POW
142857. DRXJ_CFG_OOB_MISC
142858. DRXJ_CFG_OOB_PRE_SAW
142859. DRXJ_CFG_PRE_SAW
142860. DRXJ_CFG_RESET_PACKET_ERR
142861. DRXJ_CFG_SMART_ANT
142862. DRXJ_CFG_SYMBOL_CLK_OFFSET
142863. DRXJ_CFG_VSB_MISC
142864. DRXJ_COEF_IDX_BG
142865. DRXJ_COEF_IDX_DK
142866. DRXJ_COEF_IDX_FM
142867. DRXJ_COEF_IDX_I
142868. DRXJ_COEF_IDX_L
142869. DRXJ_COEF_IDX_LP
142870. DRXJ_COEF_IDX_MAX
142871. DRXJ_COEF_IDX_MN
142872. DRXJ_CTRL_CFG_BASE
142873. DRXJ_DAP_AUDTRIF_TIMEOUT
142874. DRXJ_DEF_DEMOD_DEV_ID
142875. DRXJ_DEF_I2C_ADDR
142876. DRXJ_DEMOD_LOCK
142877. DRXJ_FM_CARRIER_FREQ_OFFSET
142878. DRXJ_HI_ATOMIC_BUF_END
142879. DRXJ_HI_ATOMIC_BUF_START
142880. DRXJ_HI_ATOMIC_READ
142881. DRXJ_HI_ATOMIC_WRITE
142882. DRXJ_I2C_SPEED_100KBPS
142883. DRXJ_I2C_SPEED_400KBPS
142884. DRXJ_ISATVSTD
142885. DRXJ_ISAUDWRITE
142886. DRXJ_ISQAMSTD
142887. DRXJ_MAX_RETRIES
142888. DRXJ_MAX_RETRIES_POWERUP
142889. DRXJ_MAX_WAITTIME
142890. DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
142891. DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K
142892. DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K
142893. DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K
142894. DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K
142895. DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K
142896. DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO
142897. DRXJ_MPEG_START_WIDTH_1CLKCYC
142898. DRXJ_MPEG_START_WIDTH_8CLKCYC
142899. DRXJ_NTSC_CARRIER_FREQ_OFFSET
142900. DRXJ_OOB_AGC_LOCK
142901. DRXJ_OOB_LO_POW_MAX
142902. DRXJ_OOB_LO_POW_MINUS0DB
142903. DRXJ_OOB_LO_POW_MINUS10DB
142904. DRXJ_OOB_LO_POW_MINUS15DB
142905. DRXJ_OOB_LO_POW_MINUS5DB
142906. DRXJ_OOB_STATE_AGC_HUNT
142907. DRXJ_OOB_STATE_AGN_HUNT
142908. DRXJ_OOB_STATE_DGN_HUNT
142909. DRXJ_OOB_STATE_EQT_HUNT
142910. DRXJ_OOB_STATE_EQU_HUNT
142911. DRXJ_OOB_STATE_FRQ_HUNT
142912. DRXJ_OOB_STATE_PHA_HUNT
142913. DRXJ_OOB_STATE_RESET
142914. DRXJ_OOB_STATE_SYNC
142915. DRXJ_OOB_STATE_TIM_HUNT
142916. DRXJ_OOB_SYNC_LOCK
142917. DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
142918. DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
142919. DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
142920. DRXJ_PIN_SAFE_MODE
142921. DRXJ_POWER_DOWN_CORE
142922. DRXJ_POWER_DOWN_MAIN_PATH
142923. DRXJ_POWER_DOWN_PLL
142924. DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
142925. DRXJ_QAM_FEC_LOCK_WAITTIME
142926. DRXJ_QAM_MAX_WAITTIME
142927. DRXJ_QAM_SL_SIG_POWER_QAM128
142928. DRXJ_QAM_SL_SIG_POWER_QAM16
142929. DRXJ_QAM_SL_SIG_POWER_QAM256
142930. DRXJ_QAM_SL_SIG_POWER_QAM32
142931. DRXJ_QAM_SL_SIG_POWER_QAM64
142932. DRXJ_QAM_SL_SIG_POWER_QAM8
142933. DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN
142934. DRXJ_QAM_SL_SIG_POWER_QPSK
142935. DRXJ_QAM_SYMBOLRATE_MAX
142936. DRXJ_QAM_SYMBOLRATE_MIN
142937. DRXJ_RFAGC_MAX
142938. DRXJ_RFAGC_MIN
142939. DRXJ_SCAN_TIMEOUT
142940. DRXJ_SIF_ATTENUATION_0DB
142941. DRXJ_SIF_ATTENUATION_3DB
142942. DRXJ_SIF_ATTENUATION_6DB
142943. DRXJ_SIF_ATTENUATION_9DB
142944. DRXJ_SMT_ANT_INPUT
142945. DRXJ_SMT_ANT_OUTPUT
142946. DRXJ_STR_OOB_LOCKSTATUS
142947. DRXJ_TYPE_ID
142948. DRXJ_WAKE_UP_KEY
142949. DRXJ_XTAL_FREQ_20P25MHZ
142950. DRXJ_XTAL_FREQ_27MHZ
142951. DRXJ_XTAL_FREQ_4MHZ
142952. DRXJ_XTAL_FREQ_RSVD
142953. DRXK_8VSB_MPEG_BIT_RATE
142954. DRXK_AGC_CTRL_AUTO
142955. DRXK_AGC_CTRL_OFF
142956. DRXK_AGC_CTRL_USER
142957. DRXK_AGC_DAC_OFFSET
142958. DRXK_ATV_STARTED
142959. DRXK_BANDWIDTH_6MHZ_IN_HZ
142960. DRXK_BANDWIDTH_7MHZ_IN_HZ
142961. DRXK_BANDWIDTH_8MHZ_IN_HZ
142962. DRXK_BLCC_NR_ELEMENTS_TAPS
142963. DRXK_BLCC_NR_ELEMENTS_UCODE
142964. DRXK_BLC_TIMEOUT
142965. DRXK_BLDC_NR_ELEMENTS_TAPS
142966. DRXK_BL_ROM_OFFSET_TAPS_BG
142967. DRXK_BL_ROM_OFFSET_TAPS_DKILLP
142968. DRXK_BL_ROM_OFFSET_TAPS_DVBT
142969. DRXK_BL_ROM_OFFSET_TAPS_FM
142970. DRXK_BL_ROM_OFFSET_TAPS_ITU_A
142971. DRXK_BL_ROM_OFFSET_TAPS_ITU_C
142972. DRXK_BL_ROM_OFFSET_TAPS_NTSC
142973. DRXK_BL_ROM_OFFSET_UCODE
142974. DRXK_COEF_IDX_BG
142975. DRXK_COEF_IDX_DK
142976. DRXK_COEF_IDX_FM
142977. DRXK_COEF_IDX_I
142978. DRXK_COEF_IDX_L
142979. DRXK_COEF_IDX_LP
142980. DRXK_COEF_IDX_MAX
142981. DRXK_COEF_IDX_MN
142982. DRXK_DTV_STARTED
142983. DRXK_DVBT_MPEG_BIT_RATE
142984. DRXK_DVBT_SQI_SPEED_FAST
142985. DRXK_DVBT_SQI_SPEED_MEDIUM
142986. DRXK_DVBT_SQI_SPEED_SLOW
142987. DRXK_DVBT_SQI_SPEED_UNKNOWN
142988. DRXK_HI_ATOMIC_BUF_END
142989. DRXK_HI_ATOMIC_BUF_START
142990. DRXK_HI_ATOMIC_READ
142991. DRXK_HI_ATOMIC_WRITE
142992. DRXK_KI_DAGC_ATV
142993. DRXK_KI_DAGC_DVBT
142994. DRXK_KI_DAGC_QAM
142995. DRXK_KI_IAGC_ATV
142996. DRXK_KI_IAGC_DVBT
142997. DRXK_KI_IAGC_QAM
142998. DRXK_KI_RAGC_ATV
142999. DRXK_KI_RAGC_DVBT
143000. DRXK_KI_RAGC_QAM
143001. DRXK_MAX_MPEG_BIT_RATE
143002. DRXK_MAX_RETRIES
143003. DRXK_MAX_RETRIES_POWERUP
143004. DRXK_MAX_WAITTIME
143005. DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
143006. DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
143007. DRXK_NO_DEV
143008. DRXK_OFDM_NE_NOTCH_WIDTH
143009. DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
143010. DRXK_POWERED_DOWN
143011. DRXK_POWER_DOWN_CORE
143012. DRXK_POWER_DOWN_OFDM
143013. DRXK_POWER_DOWN_PLL
143014. DRXK_QAM128_MPEG_BIT_RATE
143015. DRXK_QAM16_MPEG_BIT_RATE
143016. DRXK_QAM256_MPEG_BIT_RATE
143017. DRXK_QAM32_MPEG_BIT_RATE
143018. DRXK_QAM64_MPEG_BIT_RATE
143019. DRXK_QAMA_TAPS_SELECT
143020. DRXK_QAM_I12_J17
143021. DRXK_QAM_I_UNKNOWN
143022. DRXK_QAM_SL_SIG_POWER_QAM128
143023. DRXK_QAM_SL_SIG_POWER_QAM16
143024. DRXK_QAM_SL_SIG_POWER_QAM256
143025. DRXK_QAM_SL_SIG_POWER_QAM32
143026. DRXK_QAM_SL_SIG_POWER_QAM64
143027. DRXK_QAM_SYMBOLRATE_MAX
143028. DRXK_SIF_ATTENUATION_0DB
143029. DRXK_SIF_ATTENUATION_3DB
143030. DRXK_SIF_ATTENUATION_6DB
143031. DRXK_SIF_ATTENUATION_9DB
143032. DRXK_SPIN_A1
143033. DRXK_SPIN_A2
143034. DRXK_SPIN_A3
143035. DRXK_SPIN_UNKNOWN
143036. DRXK_STOPPED
143037. DRXK_UNINITIALIZED
143038. DRXK_VERSION_MAJOR
143039. DRXK_VERSION_MINOR
143040. DRXK_VERSION_PATCH
143041. DRXX_JTAGID
143042. DRXX_J_JTAGID
143043. DRXX_K_JTAGID
143044. DRX_16TO8
143045. DRX_ACCESSMACRO_GET
143046. DRX_ACCESSMACRO_SET
143047. DRX_AGC_CTRL_AUTO
143048. DRX_AGC_CTRL_OFF
143049. DRX_AGC_CTRL_USER
143050. DRX_ATTR_CACHESTANDARD
143051. DRX_ATTR_CAPABILITIES
143052. DRX_ATTR_CURRENTCHANNEL
143053. DRX_ATTR_CURRENTPOWERMODE
143054. DRX_ATTR_CURRENTSTANDARD
143055. DRX_ATTR_I2CADDR
143056. DRX_ATTR_I2CDEVID
143057. DRX_ATTR_INTERMEDIATEFREQ
143058. DRX_ATTR_ISOPENED
143059. DRX_ATTR_MCRECORD
143060. DRX_ATTR_MICROCODE
143061. DRX_ATTR_MIRRORFREQSPECT
143062. DRX_ATTR_PREVSTANDARD
143063. DRX_ATTR_PRODUCTID
143064. DRX_ATTR_SYSCLOCKFREQ
143065. DRX_ATTR_TUNERIFAGCPOL
143066. DRX_ATTR_TUNERRFAGCPOL
143067. DRX_ATTR_TUNERSLOWMODE
143068. DRX_ATTR_TUNERSPORTNR
143069. DRX_ATTR_USEBOOTLOADER
143070. DRX_ATTR_VERIFYMICROCODE
143071. DRX_AUD_AUTO_SOUND_OFF
143072. DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
143073. DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON
143074. DRX_AUD_AVC_DECAYTIME_20MS
143075. DRX_AUD_AVC_DECAYTIME_2S
143076. DRX_AUD_AVC_DECAYTIME_4S
143077. DRX_AUD_AVC_DECAYTIME_8S
143078. DRX_AUD_AVC_MAX_ATTEN_12DB
143079. DRX_AUD_AVC_MAX_ATTEN_18DB
143080. DRX_AUD_AVC_MAX_ATTEN_24DB
143081. DRX_AUD_AVC_MAX_GAIN_0DB
143082. DRX_AUD_AVC_MAX_GAIN_12DB
143083. DRX_AUD_AVC_MAX_GAIN_6DB
143084. DRX_AUD_AVC_OFF
143085. DRX_AUD_AVSYNC_MONOCHROME
143086. DRX_AUD_AVSYNC_NTSC
143087. DRX_AUD_AVSYNC_OFF
143088. DRX_AUD_AVSYNC_PAL_SECAM
143089. DRX_AUD_DEVIATION_HIGH
143090. DRX_AUD_DEVIATION_NORMAL
143091. DRX_AUD_FM_DEEMPH_50US
143092. DRX_AUD_FM_DEEMPH_75US
143093. DRX_AUD_FM_DEEMPH_OFF
143094. DRX_AUD_FM_MATRIX_GERMAN
143095. DRX_AUD_FM_MATRIX_KOREAN
143096. DRX_AUD_FM_MATRIX_NO_MATRIX
143097. DRX_AUD_FM_MATRIX_SOUND_A
143098. DRX_AUD_FM_MATRIX_SOUND_B
143099. DRX_AUD_I2S_MATRIX_A_MONO
143100. DRX_AUD_I2S_MATRIX_B_MONO
143101. DRX_AUD_I2S_MATRIX_MONO
143102. DRX_AUD_I2S_MATRIX_STEREO
143103. DRX_AUD_MAX_FM_DEVIATION
143104. DRX_AUD_MAX_NICAM_PRESCALE
143105. DRX_AUD_NICAM_BAD
143106. DRX_AUD_NICAM_DETECTED
143107. DRX_AUD_NICAM_NOT_DETECTED
143108. DRX_AUD_SRC_MONO
143109. DRX_AUD_SRC_STEREO_OR_A
143110. DRX_AUD_SRC_STEREO_OR_AB
143111. DRX_AUD_SRC_STEREO_OR_B
143112. DRX_AUD_STANDARD_A2
143113. DRX_AUD_STANDARD_AUTO
143114. DRX_AUD_STANDARD_BG_FM
143115. DRX_AUD_STANDARD_BG_NICAM_FM
143116. DRX_AUD_STANDARD_BTSC
143117. DRX_AUD_STANDARD_D_K1
143118. DRX_AUD_STANDARD_D_K2
143119. DRX_AUD_STANDARD_D_K3
143120. DRX_AUD_STANDARD_D_K_MONO
143121. DRX_AUD_STANDARD_D_K_NICAM_FM
143122. DRX_AUD_STANDARD_EIAJ
143123. DRX_AUD_STANDARD_FM_STEREO
143124. DRX_AUD_STANDARD_I_NICAM_FM
143125. DRX_AUD_STANDARD_L_NICAM_AM
143126. DRX_AUD_STANDARD_M_MONO
143127. DRX_AUD_STANDARD_NOT_READY
143128. DRX_AUD_STANDARD_UNKNOWN
143129. DRX_AUTO
143130. DRX_BANDWIDTH_6MHZ
143131. DRX_BANDWIDTH_7MHZ
143132. DRX_BANDWIDTH_8MHZ
143133. DRX_BANDWIDTH_AUTO
143134. DRX_BANDWIDTH_UNKNOWN
143135. DRX_BTSC_MONO_AND_SAP
143136. DRX_BTSC_STEREO
143137. DRX_CAPABILITY_HAS_8VSB
143138. DRX_CAPABILITY_HAS_ATV
143139. DRX_CAPABILITY_HAS_AUD
143140. DRX_CAPABILITY_HAS_DVBT
143141. DRX_CAPABILITY_HAS_GPIO1
143142. DRX_CAPABILITY_HAS_GPIO2
143143. DRX_CAPABILITY_HAS_IRQN
143144. DRX_CAPABILITY_HAS_ITUAC
143145. DRX_CAPABILITY_HAS_ITUB
143146. DRX_CAPABILITY_HAS_LNA
143147. DRX_CAPABILITY_HAS_OOBRX
143148. DRX_CAPABILITY_HAS_SAWSW
143149. DRX_CAPABILITY_HAS_SMARX
143150. DRX_CAPABILITY_HAS_SMATX
143151. DRX_CARRIER_AUTO
143152. DRX_CARRIER_MULTI
143153. DRX_CARRIER_SINGLE
143154. DRX_CARRIER_UNKNOWN
143155. DRX_CFG_ATV_STANDARD
143156. DRX_CFG_AUD_ASS_THRES
143157. DRX_CFG_AUD_AUTOSOUND
143158. DRX_CFG_AUD_AVSYNC
143159. DRX_CFG_AUD_CARRIER
143160. DRX_CFG_AUD_DEVIATION
143161. DRX_CFG_AUD_MIXER
143162. DRX_CFG_AUD_PRESCALE
143163. DRX_CFG_AUD_RDS
143164. DRX_CFG_AUD_VOLUME
143165. DRX_CFG_BASE
143166. DRX_CFG_I2S_OUTPUT
143167. DRX_CFG_MPEG_OUTPUT
143168. DRX_CFG_PINSAFE
143169. DRX_CFG_PINS_SAFE_MODE
143170. DRX_CFG_PKTERR
143171. DRX_CFG_SMA
143172. DRX_CFG_SQI_SPEED
143173. DRX_CFG_SUBSTANDARD
143174. DRX_CFG_SYMCLK_OFFS
143175. DRX_CHANNEL_AUTO
143176. DRX_CHANNEL_HIGH
143177. DRX_CHANNEL_LOW
143178. DRX_CLASSIFICATION_AUTO
143179. DRX_CLASSIFICATION_COCHANNEL
143180. DRX_CLASSIFICATION_GAUSS
143181. DRX_CLASSIFICATION_HVY_GAUSS
143182. DRX_CLASSIFICATION_MOVING
143183. DRX_CLASSIFICATION_STATIC
143184. DRX_CLASSIFICATION_UNKNOWN
143185. DRX_CLASSIFICATION_ZERODB
143186. DRX_CODERATE_1DIV2
143187. DRX_CODERATE_2DIV3
143188. DRX_CODERATE_3DIV4
143189. DRX_CODERATE_5DIV6
143190. DRX_CODERATE_7DIV8
143191. DRX_CODERATE_AUTO
143192. DRX_CODERATE_UNKNOWN
143193. DRX_CONSTELLATION_AUTO
143194. DRX_CONSTELLATION_BPSK
143195. DRX_CONSTELLATION_PSK8
143196. DRX_CONSTELLATION_QAM1024
143197. DRX_CONSTELLATION_QAM128
143198. DRX_CONSTELLATION_QAM16
143199. DRX_CONSTELLATION_QAM256
143200. DRX_CONSTELLATION_QAM32
143201. DRX_CONSTELLATION_QAM512
143202. DRX_CONSTELLATION_QAM64
143203. DRX_CONSTELLATION_QPSK
143204. DRX_CONSTELLATION_QPSK_NR
143205. DRX_CONSTELLATION_UNKNOWN
143206. DRX_CTRL_CFG_MAX
143207. DRX_ConfigureI2CBridge
143208. DRX_FFTMODE_2K
143209. DRX_FFTMODE_4K
143210. DRX_FFTMODE_8K
143211. DRX_FFTMODE_AUTO
143212. DRX_FFTMODE_UNKNOWN
143213. DRX_FRAMEMODE_420
143214. DRX_FRAMEMODE_420_FIXED_PN
143215. DRX_FRAMEMODE_595
143216. DRX_FRAMEMODE_945
143217. DRX_FRAMEMODE_945_FIXED_PN
143218. DRX_FRAMEMODE_AUTO
143219. DRX_FRAMEMODE_UNKNOWN
143220. DRX_FW_FILENAME_A2
143221. DRX_FW_FILENAME_B1
143222. DRX_GET_AUD_BTSC_DETECT
143223. DRX_GET_PRESET
143224. DRX_GET_QAM_LOCKRANGE
143225. DRX_GUARD_1DIV16
143226. DRX_GUARD_1DIV32
143227. DRX_GUARD_1DIV4
143228. DRX_GUARD_1DIV8
143229. DRX_GUARD_AUTO
143230. DRX_GUARD_UNKNOWN
143231. DRX_GetLockStatus
143232. DRX_HIERARCHY_ALPHA1
143233. DRX_HIERARCHY_ALPHA2
143234. DRX_HIERARCHY_ALPHA4
143235. DRX_HIERARCHY_AUTO
143236. DRX_HIERARCHY_NONE
143237. DRX_HIERARCHY_UNKNOWN
143238. DRX_I2C_BROADCAST
143239. DRX_I2C_CLEARCRC
143240. DRX_I2C_FLAGS
143241. DRX_I2C_MODEFLAGS
143242. DRX_I2C_RMW
143243. DRX_I2C_SINGLE_MASTER
143244. DRX_I2S_FORMAT_WS_ADVANCED
143245. DRX_I2S_FORMAT_WS_WITH_DATA
143246. DRX_I2S_MODE_MASTER
143247. DRX_I2S_MODE_SLAVE
143248. DRX_I2S_POLARITY_LEFT
143249. DRX_I2S_POLARITY_RIGHT
143250. DRX_I2S_WORDLENGTH_16
143251. DRX_I2S_WORDLENGTH_32
143252. DRX_INTERLEAVEMODE_AUTO
143253. DRX_INTERLEAVEMODE_B52_M0
143254. DRX_INTERLEAVEMODE_B52_M240
143255. DRX_INTERLEAVEMODE_B52_M48
143256. DRX_INTERLEAVEMODE_B52_M720
143257. DRX_INTERLEAVEMODE_I128_J1
143258. DRX_INTERLEAVEMODE_I128_J1_V2
143259. DRX_INTERLEAVEMODE_I128_J2
143260. DRX_INTERLEAVEMODE_I128_J3
143261. DRX_INTERLEAVEMODE_I128_J4
143262. DRX_INTERLEAVEMODE_I128_J5
143263. DRX_INTERLEAVEMODE_I128_J6
143264. DRX_INTERLEAVEMODE_I128_J7
143265. DRX_INTERLEAVEMODE_I128_J8
143266. DRX_INTERLEAVEMODE_I12_J17
143267. DRX_INTERLEAVEMODE_I16_J8
143268. DRX_INTERLEAVEMODE_I32_J4
143269. DRX_INTERLEAVEMODE_I5_J4
143270. DRX_INTERLEAVEMODE_I64_J2
143271. DRX_INTERLEAVEMODE_I8_J16
143272. DRX_INTERLEAVEMODE_RESERVED_11
143273. DRX_INTERLEAVEMODE_RESERVED_13
143274. DRX_INTERLEAVEMODE_RESERVED_15
143275. DRX_INTERLEAVEMODE_UNKNOWN
143276. DRX_ISATVSTD
143277. DRX_ISDVBTSTD
143278. DRX_ISMCVERTYPE
143279. DRX_ISPOWERDOWNMODE
143280. DRX_ISQAMSTD
143281. DRX_ISVSBSTD
143282. DRX_LDPC_0_4
143283. DRX_LDPC_0_6
143284. DRX_LDPC_0_8
143285. DRX_LDPC_AUTO
143286. DRX_LDPC_UNKNOWN
143287. DRX_LOCKED
143288. DRX_LOCK_DEMOD
143289. DRX_LOCK_FEC
143290. DRX_LOCK_MPEG
143291. DRX_LOCK_STATE_1
143292. DRX_LOCK_STATE_2
143293. DRX_LOCK_STATE_3
143294. DRX_LOCK_STATE_4
143295. DRX_LOCK_STATE_5
143296. DRX_LOCK_STATE_6
143297. DRX_LOCK_STATE_7
143298. DRX_LOCK_STATE_8
143299. DRX_LOCK_STATE_9
143300. DRX_MIRROR_AUTO
143301. DRX_MIRROR_NO
143302. DRX_MIRROR_UNKNOWN
143303. DRX_MIRROR_YES
143304. DRX_MODULE_BSP_HOST
143305. DRX_MODULE_BSP_I2C
143306. DRX_MODULE_BSP_TUNER
143307. DRX_MODULE_DAP
143308. DRX_MODULE_DEVICE
143309. DRX_MODULE_DEVICEDRIVER
143310. DRX_MODULE_DRIVERCORE
143311. DRX_MODULE_MICROCODE
143312. DRX_MODULE_UNKNOWN
143313. DRX_MPEG_STR_WIDTH_1
143314. DRX_MPEG_STR_WIDTH_8
143315. DRX_NEVER_LOCK
143316. DRX_NOT_LOCKED
143317. DRX_NO_CARRIER_MUTE
143318. DRX_NO_CARRIER_NOISE
143319. DRX_OOB_MODE_A
143320. DRX_OOB_MODE_B_GRADE_A
143321. DRX_OOB_MODE_B_GRADE_B
143322. DRX_PILOT_AUTO
143323. DRX_PILOT_OFF
143324. DRX_PILOT_ON
143325. DRX_PILOT_UNKNOWN
143326. DRX_POWER_DOWN
143327. DRX_POWER_MODE_1
143328. DRX_POWER_MODE_10
143329. DRX_POWER_MODE_11
143330. DRX_POWER_MODE_12
143331. DRX_POWER_MODE_13
143332. DRX_POWER_MODE_14
143333. DRX_POWER_MODE_15
143334. DRX_POWER_MODE_16
143335. DRX_POWER_MODE_2
143336. DRX_POWER_MODE_3
143337. DRX_POWER_MODE_4
143338. DRX_POWER_MODE_5
143339. DRX_POWER_MODE_6
143340. DRX_POWER_MODE_7
143341. DRX_POWER_MODE_8
143342. DRX_POWER_MODE_9
143343. DRX_POWER_UP
143344. DRX_PRIORITY_HIGH
143345. DRX_PRIORITY_LOW
143346. DRX_PRIORITY_UNKNOWN
143347. DRX_QAM_LOCKRANGE_EXTENDED
143348. DRX_QAM_LOCKRANGE_NORMAL
143349. DRX_REG
143350. DRX_SCAN_COMMAND_INIT
143351. DRX_SCAN_COMMAND_NEXT
143352. DRX_SCAN_COMMAND_STOP
143353. DRX_SCU_READY
143354. DRX_SET_AUD_BTSC_DETECT
143355. DRX_SET_PRESET
143356. DRX_SET_QAM_LOCKRANGE
143357. DRX_SQI_SPEED_FAST
143358. DRX_SQI_SPEED_MEDIUM
143359. DRX_SQI_SPEED_SLOW
143360. DRX_SQI_SPEED_UNKNOWN
143361. DRX_STANDARD_8VSB
143362. DRX_STANDARD_AUTO
143363. DRX_STANDARD_DTMB
143364. DRX_STANDARD_DVBT
143365. DRX_STANDARD_FM
143366. DRX_STANDARD_ITU_A
143367. DRX_STANDARD_ITU_B
143368. DRX_STANDARD_ITU_C
143369. DRX_STANDARD_ITU_D
143370. DRX_STANDARD_NTSC
143371. DRX_STANDARD_PAL_SECAM_BG
143372. DRX_STANDARD_PAL_SECAM_DK
143373. DRX_STANDARD_PAL_SECAM_I
143374. DRX_STANDARD_PAL_SECAM_L
143375. DRX_STANDARD_PAL_SECAM_LP
143376. DRX_STANDARD_UNKNOWN
143377. DRX_STR_AUD_CARRIER
143378. DRX_STR_AUD_NICAM_STATUS
143379. DRX_STR_AUD_RDS
143380. DRX_STR_AUD_SAP
143381. DRX_STR_AUD_STANDARD
143382. DRX_STR_AUD_STEREO
143383. DRX_STR_BANDWIDTH
143384. DRX_STR_CARRIER
143385. DRX_STR_CLASSIFICATION
143386. DRX_STR_CODERATE
143387. DRX_STR_CONSTELLATION
143388. DRX_STR_FFTMODE
143389. DRX_STR_FRAMEMODE
143390. DRX_STR_GUARD
143391. DRX_STR_HIERARCHY
143392. DRX_STR_INTERLEAVEMODE
143393. DRX_STR_LDPC
143394. DRX_STR_LOCKSTATUS
143395. DRX_STR_MIRROR
143396. DRX_STR_MODULE
143397. DRX_STR_OOB_STANDARD
143398. DRX_STR_PILOT
143399. DRX_STR_POWER_MODE
143400. DRX_STR_PRIORITY
143401. DRX_STR_RDS_VALID
143402. DRX_STR_STANDARD
143403. DRX_STR_TPS_FRAME
143404. DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA
143405. DRX_SUBSTANDARD_ATV_DK_CHINA
143406. DRX_SUBSTANDARD_ATV_DK_POLAND
143407. DRX_SUBSTANDARD_AUTO
143408. DRX_SUBSTANDARD_MAIN
143409. DRX_SUBSTANDARD_UNKNOWN
143410. DRX_Start
143411. DRX_Stop
143412. DRX_TPS_FRAME1
143413. DRX_TPS_FRAME2
143414. DRX_TPS_FRAME3
143415. DRX_TPS_FRAME4
143416. DRX_TPS_FRAME_UNKNOWN
143417. DRX_U16TODRXFREQ
143418. DRX_UCODE_CRC_FLAG
143419. DRX_UCODE_MAGIC_WORD
143420. DRX_UCODE_MAX_BUF_SIZE
143421. DRX_UIO1
143422. DRX_UIO10
143423. DRX_UIO11
143424. DRX_UIO12
143425. DRX_UIO13
143426. DRX_UIO14
143427. DRX_UIO15
143428. DRX_UIO16
143429. DRX_UIO17
143430. DRX_UIO18
143431. DRX_UIO19
143432. DRX_UIO2
143433. DRX_UIO20
143434. DRX_UIO21
143435. DRX_UIO22
143436. DRX_UIO23
143437. DRX_UIO24
143438. DRX_UIO25
143439. DRX_UIO26
143440. DRX_UIO27
143441. DRX_UIO28
143442. DRX_UIO29
143443. DRX_UIO3
143444. DRX_UIO30
143445. DRX_UIO31
143446. DRX_UIO32
143447. DRX_UIO4
143448. DRX_UIO5
143449. DRX_UIO6
143450. DRX_UIO7
143451. DRX_UIO8
143452. DRX_UIO9
143453. DRX_UIO_MAX
143454. DRX_UIO_MODE_DISABLE
143455. DRX_UIO_MODE_FIRMWARE
143456. DRX_UIO_MODE_FIRMWARE0
143457. DRX_UIO_MODE_FIRMWARE1
143458. DRX_UIO_MODE_FIRMWARE2
143459. DRX_UIO_MODE_FIRMWARE3
143460. DRX_UIO_MODE_FIRMWARE4
143461. DRX_UIO_MODE_FIRMWARE5
143462. DRX_UIO_MODE_FIRMWARE_SAW
143463. DRX_UIO_MODE_FIRMWARE_SMA
143464. DRX_UIO_MODE_READWRITE
143465. DRX_UNKNOWN
143466. DRX_VERSIONSTRING
143467. DRX_VERSIONSTRING_HELP
143468. DRX_XS_CFG_AUD_BTSC_DETECT
143469. DRX_XS_CFG_BASE
143470. DRX_XS_CFG_PRESET
143471. DRX_XS_CFG_QAM_LOCKRANGE
143472. DR_ACTION
143473. DR_ACTION_DOMAIN_FDB_EGRESS
143474. DR_ACTION_DOMAIN_FDB_INGRESS
143475. DR_ACTION_DOMAIN_MAX
143476. DR_ACTION_DOMAIN_NIC_EGRESS
143477. DR_ACTION_DOMAIN_NIC_INGRESS
143478. DR_ACTION_MAX_STES
143479. DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2
143480. DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3
143481. DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2
143482. DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2
143483. DR_ACTION_STATE_ERR
143484. DR_ACTION_STATE_MAX
143485. DR_ACTION_STATE_MODIFY_HDR
143486. DR_ACTION_STATE_MODIFY_VLAN
143487. DR_ACTION_STATE_NON_TERM
143488. DR_ACTION_STATE_NO_ACTION
143489. DR_ACTION_STATE_REFORMAT
143490. DR_ACTION_STATE_TERM
143491. DR_ACTION_TYP_CTR
143492. DR_ACTION_TYP_DROP
143493. DR_ACTION_TYP_FT
143494. DR_ACTION_TYP_L2_TO_TNL_L2
143495. DR_ACTION_TYP_L2_TO_TNL_L3
143496. DR_ACTION_TYP_MAX
143497. DR_ACTION_TYP_MODIFY_HDR
143498. DR_ACTION_TYP_POP_VLAN
143499. DR_ACTION_TYP_PUSH_VLAN
143500. DR_ACTION_TYP_QP
143501. DR_ACTION_TYP_TAG
143502. DR_ACTION_TYP_TNL_L2_TO_L2
143503. DR_ACTION_TYP_TNL_L3_TO_L2
143504. DR_ACTION_TYP_VPORT
143505. DR_CHUNK_SIZE_1
143506. DR_CHUNK_SIZE_1024K
143507. DR_CHUNK_SIZE_128
143508. DR_CHUNK_SIZE_128K
143509. DR_CHUNK_SIZE_16
143510. DR_CHUNK_SIZE_16K
143511. DR_CHUNK_SIZE_1K
143512. DR_CHUNK_SIZE_2
143513. DR_CHUNK_SIZE_2048K
143514. DR_CHUNK_SIZE_256
143515. DR_CHUNK_SIZE_256K
143516. DR_CHUNK_SIZE_2K
143517. DR_CHUNK_SIZE_32
143518. DR_CHUNK_SIZE_32K
143519. DR_CHUNK_SIZE_4
143520. DR_CHUNK_SIZE_4K
143521. DR_CHUNK_SIZE_512
143522. DR_CHUNK_SIZE_512K
143523. DR_CHUNK_SIZE_64
143524. DR_CHUNK_SIZE_64K
143525. DR_CHUNK_SIZE_8
143526. DR_CHUNK_SIZE_8K
143527. DR_CHUNK_SIZE_MAX
143528. DR_CHUNK_SIZE_MIN
143529. DR_CONTROL
143530. DR_CONTROL_RESERVED
143531. DR_CONTROL_SHIFT
143532. DR_CONTROL_SIZE
143533. DR_CPU_CONFIGURE
143534. DR_CPU_ERROR
143535. DR_CPU_FORCE_UNCONFIGURE
143536. DR_CPU_OK
143537. DR_CPU_RES_BLOCKED
143538. DR_CPU_RES_CPU_NOT_RESPONDING
143539. DR_CPU_RES_FAILURE
143540. DR_CPU_RES_NOT_IN_MD
143541. DR_CPU_RES_OK
143542. DR_CPU_STATUS
143543. DR_CPU_STAT_CONFIGURED
143544. DR_CPU_STAT_NOT_PRESENT
143545. DR_CPU_STAT_UNCONFIGURED
143546. DR_CPU_UNCONFIGURE
143547. DR_DEVICE
143548. DR_ENABLE_SIZE
143549. DR_ENTITY_PRESENT
143550. DR_ENTITY_SENSE
143551. DR_ENTITY_UNUSABLE
143552. DR_FIRSTADDR
143553. DR_GLOBAL_ENABLE
143554. DR_GLOBAL_ENABLE_MASK
143555. DR_GLOBAL_ENABLE_SHIFT
143556. DR_GLOBAL_SLOWDOWN
143557. DR_HOST
143558. DR_ICM_MODIFY_HDR_ALIGN_BASE
143559. DR_ICM_SYNC_THRESHOLD
143560. DR_ICM_TYPE_MODIFY_ACTION
143561. DR_ICM_TYPE_STE
143562. DR_INDICATOR
143563. DR_INSERT
143564. DR_LASTADDR
143565. DR_LEN_1
143566. DR_LEN_2
143567. DR_LEN_4
143568. DR_LEN_8
143569. DR_LOCAL_ENABLE
143570. DR_LOCAL_ENABLE_MASK
143571. DR_LOCAL_ENABLE_SHIFT
143572. DR_LOCAL_SLOWDOWN
143573. DR_MASK_IS_ETH_L4_MISC_SET
143574. DR_MASK_IS_ETH_L4_SET
143575. DR_MASK_IS_FIRST_MPLS_SET
143576. DR_MASK_IS_FLEX_PARSER_0_SET
143577. DR_MASK_IS_FLEX_PARSER_ICMPV4_SET
143578. DR_MASK_IS_L2_DST
143579. DR_MASK_IS_OUTER_MPLS_OVER_GRE_UDP_SET
143580. DR_MATCHER_CRITERIA_EMPTY
143581. DR_MATCHER_CRITERIA_INNER
143582. DR_MATCHER_CRITERIA_MAX
143583. DR_MATCHER_CRITERIA_MISC
143584. DR_MATCHER_CRITERIA_MISC2
143585. DR_MATCHER_CRITERIA_MISC3
143586. DR_MATCHER_CRITERIA_OUTER
143587. DR_MODIFY_ACTION_SIZE
143588. DR_NONE
143589. DR_RULE_MAX_STES
143590. DR_RULE_MAX_STE_CHAIN
143591. DR_RW_EXECUTE
143592. DR_RW_READ
143593. DR_RW_WRITE
143594. DR_SELECT
143595. DR_STAT
143596. DR_STATUS
143597. DR_STEP
143598. DR_STE_ACTION_TYPE_ENCAP
143599. DR_STE_ACTION_TYPE_ENCAP_L3
143600. DR_STE_ACTION_TYPE_PUSH_VLAN
143601. DR_STE_CALC_LU_TYPE
143602. DR_STE_CRC_POLY
143603. DR_STE_CVLAN
143604. DR_STE_ENABLE_FLOW_TAG
143605. DR_STE_IS_OUTER_MPLS_OVER_GRE_SET
143606. DR_STE_IS_OUTER_MPLS_OVER_UDP_SET
143607. DR_STE_SET_MASK
143608. DR_STE_SET_MASK_V
143609. DR_STE_SET_MPLS_MASK
143610. DR_STE_SET_MPLS_TAG
143611. DR_STE_SET_TAG
143612. DR_STE_SET_TCP_FLAGS
143613. DR_STE_SET_VAL
143614. DR_STE_SIZE
143615. DR_STE_SIZE_CTRL
143616. DR_STE_SIZE_MASK
143617. DR_STE_SIZE_REDUCED
143618. DR_STE_SIZE_TAG
143619. DR_STE_SVLAN
143620. DR_STE_TUNL_ACTION_DECAP
143621. DR_STE_TUNL_ACTION_ENABLE
143622. DR_STE_TUNL_ACTION_L3_DECAP
143623. DR_STE_TUNL_ACTION_NONE
143624. DR_STE_TUNL_ACTION_POP_VLAN
143625. DR_SWITCH
143626. DR_TRAP0
143627. DR_TRAP1
143628. DR_TRAP2
143629. DR_TRAP3
143630. DR_TRAP_BITS
143631. DR_TY_MASK
143632. DR_TY_SHIFT
143633. DR_VARIABLE_STRUCT
143634. DRm
143635. DRn
143636. DS
143637. DS0
143638. DS0_FORCE_OFF_MODE
143639. DS0_FORCE_OUT_HIGH
143640. DS0_INPUT
143641. DS0_PIN_INPUT
143642. DS0_PIN_INPUT_PULLDOWN
143643. DS0_PIN_INPUT_PULLUP
143644. DS0_PIN_OUTPUT
143645. DS0_PIN_OUTPUT_HIGH
143646. DS0_PIN_OUTPUT_PULLDOWN
143647. DS0_PIN_OUTPUT_PULLUP
143648. DS0_PULL_UP_DOWN_DIS
143649. DS0_PULL_UP_DOWN_EN
143650. DS0_PULL_UP_SEL
143651. DS1
143652. DS1216_HOUR_1224
143653. DS1216_HOUR_AMPM
143654. DS1305_AEI0
143655. DS1305_AEI1
143656. DS1305_ALM0
143657. DS1305_ALM1
143658. DS1305_ALM_DISABLE
143659. DS1305_ALM_LEN
143660. DS1305_CONTROL
143661. DS1305_CONTROL_LEN
143662. DS1305_HOUR
143663. DS1305_HR_12
143664. DS1305_HR_PM
143665. DS1305_INTCN
143666. DS1305_MDAY
143667. DS1305_MIN
143668. DS1305_MON
143669. DS1305_NVRAM
143670. DS1305_NVRAM_LEN
143671. DS1305_RTC_LEN
143672. DS1305_SEC
143673. DS1305_STATUS
143674. DS1305_TRICKLE
143675. DS1305_TRICKLE_2K
143676. DS1305_TRICKLE_4K
143677. DS1305_TRICKLE_8K
143678. DS1305_TRICKLE_DS1
143679. DS1305_TRICKLE_DS2
143680. DS1305_TRICKLE_MAGIC
143681. DS1305_WDAY
143682. DS1305_WP
143683. DS1305_WRITE
143684. DS1305_YEAR
143685. DS1305_nEOSC
143686. DS1306_1HZ
143687. DS1307_BIT_12HR
143688. DS1307_BIT_CH
143689. DS1307_BIT_OUT
143690. DS1307_BIT_PM
143691. DS1307_BIT_RS0
143692. DS1307_BIT_RS1
143693. DS1307_BIT_SQWE
143694. DS1307_REG_CONTROL
143695. DS1307_REG_HOUR
143696. DS1307_REG_MDAY
143697. DS1307_REG_MIN
143698. DS1307_REG_MONTH
143699. DS1307_REG_SECS
143700. DS1307_REG_WDAY
143701. DS1307_REG_YEAR
143702. DS1307_TRICKLE_CHARGER_250_OHM
143703. DS1307_TRICKLE_CHARGER_2K_OHM
143704. DS1307_TRICKLE_CHARGER_4K_OHM
143705. DS1307_TRICKLE_CHARGER_DIODE
143706. DS1307_TRICKLE_CHARGER_NO_DIODE
143707. DS1337_BIT_A1I
143708. DS1337_BIT_A1IE
143709. DS1337_BIT_A2I
143710. DS1337_BIT_A2IE
143711. DS1337_BIT_CENTURY
143712. DS1337_BIT_INTCN
143713. DS1337_BIT_OSF
143714. DS1337_BIT_RS1
143715. DS1337_BIT_RS2
143716. DS1337_BIT_nEOSC
143717. DS1337_REG_CONTROL
143718. DS1337_REG_STATUS
143719. DS1338_BIT_OSF
143720. DS1339_BIT_BBSQI
143721. DS1339_REG_ALARM1_SECS
143722. DS1340_BIT_CALIB_SIGN
143723. DS1340_BIT_CENTURY
143724. DS1340_BIT_CENTURY_EN
143725. DS1340_BIT_FT
143726. DS1340_BIT_OSF
143727. DS1340_BIT_OUT
143728. DS1340_BIT_nEOSC
143729. DS1340_M_CALIBRATION
143730. DS1340_REG_CONTROL
143731. DS1340_REG_FLAG
143732. DS1343_A0IE
143733. DS1343_A1IE
143734. DS1343_ALM0_DAY_REG
143735. DS1343_ALM0_HOUR_REG
143736. DS1343_ALM0_MIN_REG
143737. DS1343_ALM0_SEC_REG
143738. DS1343_ALM1_DAY_REG
143739. DS1343_ALM1_HOUR_REG
143740. DS1343_ALM1_MIN_REG
143741. DS1343_ALM1_SEC_REG
143742. DS1343_CONTROL_REG
143743. DS1343_DATE_REG
143744. DS1343_DAY_REG
143745. DS1343_DOSF
143746. DS1343_EGFIL
143747. DS1343_EOSC
143748. DS1343_HOURS_REG
143749. DS1343_INTCN
143750. DS1343_IRQF0
143751. DS1343_IRQF1
143752. DS1343_MINUTES_REG
143753. DS1343_MONTH_REG
143754. DS1343_NVRAM
143755. DS1343_NVRAM_LEN
143756. DS1343_OSF
143757. DS1343_SECONDS_REG
143758. DS1343_SQW
143759. DS1343_STATUS_REG
143760. DS1343_TRICKLE_1K
143761. DS1343_TRICKLE_2K
143762. DS1343_TRICKLE_4K
143763. DS1343_TRICKLE_DS1
143764. DS1343_TRICKLE_MAGIC
143765. DS1343_TRICKLE_REG
143766. DS1343_YEAR_REG
143767. DS1347_CLOCK_BURST
143768. DS1347_CONTROL_REG
143769. DS1347_DATE_REG
143770. DS1347_DAY_REG
143771. DS1347_HOURS_REG
143772. DS1347_MINUTES_REG
143773. DS1347_MONTH_REG
143774. DS1347_SECONDS_REG
143775. DS1347_STATUS_REG
143776. DS1347_YEAR_REG
143777. DS1374_REG_CR
143778. DS1374_REG_CR_AIE
143779. DS1374_REG_CR_WACE
143780. DS1374_REG_CR_WDALM
143781. DS1374_REG_SR
143782. DS1374_REG_SR_AF
143783. DS1374_REG_SR_OSF
143784. DS1374_REG_TCR
143785. DS1374_REG_TOD0
143786. DS1374_REG_TOD1
143787. DS1374_REG_TOD2
143788. DS1374_REG_TOD3
143789. DS1374_REG_WDALM0
143790. DS1374_REG_WDALM1
143791. DS1374_REG_WDALM2
143792. DS1390_REG_100THS
143793. DS1390_REG_ALARM_100THS
143794. DS1390_REG_ALARM_DAY_DATE
143795. DS1390_REG_ALARM_HOURS
143796. DS1390_REG_ALARM_MINUTES
143797. DS1390_REG_ALARM_SECONDS
143798. DS1390_REG_CONTROL
143799. DS1390_REG_DATE
143800. DS1390_REG_DAY
143801. DS1390_REG_HOURS
143802. DS1390_REG_MINUTES
143803. DS1390_REG_MONTH_CENT
143804. DS1390_REG_SECONDS
143805. DS1390_REG_STATUS
143806. DS1390_REG_TRICKLE
143807. DS1390_REG_YEAR
143808. DS1390_TRICKLE_CHARGER_250_OHM
143809. DS1390_TRICKLE_CHARGER_2K_OHM
143810. DS1390_TRICKLE_CHARGER_4K_OHM
143811. DS1390_TRICKLE_CHARGER_DIODE
143812. DS1390_TRICKLE_CHARGER_ENABLE
143813. DS1390_TRICKLE_CHARGER_NO_DIODE
143814. DS13XX_TRICKLE_CHARGER_MAGIC
143815. DS1511_AM1_SEC
143816. DS1511_AM2_MIN
143817. DS1511_AM3_HOUR
143818. DS1511_AM4_DATE
143819. DS1511_BLF1
143820. DS1511_BLF2
143821. DS1511_BME
143822. DS1511_CENTURY
143823. DS1511_CONTROL_A
143824. DS1511_CONTROL_B
143825. DS1511_CS
143826. DS1511_DOM
143827. DS1511_DOW
143828. DS1511_HOUR
143829. DS1511_IRQF
143830. DS1511_KIE
143831. DS1511_KSF
143832. DS1511_MIN
143833. DS1511_MONTH
143834. DS1511_PAB
143835. DS1511_PRS
143836. DS1511_RAMADDR_LSB
143837. DS1511_RAMDATA
143838. DS1511_RAM_MAX
143839. DS1511_SEC
143840. DS1511_TDF
143841. DS1511_TE
143842. DS1511_TIE
143843. DS1511_TPE
143844. DS1511_WDE
143845. DS1511_WDF
143846. DS1511_WDS
143847. DS1511_WD_MSEC
143848. DS1511_WD_SEC
143849. DS1511_YEAR
143850. DS1603_CLK_100
143851. DS1603_CLK_200
143852. DS1603_DATA_100
143853. DS1603_DATA_200
143854. DS1603_DATA_READ_200
143855. DS1603_DATA_READ_SHIFT_200
143856. DS1603_DATA_REG_200
143857. DS1603_DATA_SHIFT_100
143858. DS1603_REG_100
143859. DS1603_REG_200
143860. DS1603_RST_100
143861. DS1603_RST_200
143862. DS1621_ALARM_TEMP_HIGH
143863. DS1621_ALARM_TEMP_LOW
143864. DS1621_COM_START
143865. DS1621_COM_STOP
143866. DS1621_CONVERSION_MAX
143867. DS1621_REG_CONF
143868. DS1621_REG_CONFIG_1SHOT
143869. DS1621_REG_CONFIG_DONE
143870. DS1621_REG_CONFIG_NVB
143871. DS1621_REG_CONFIG_POLARITY
143872. DS1621_REG_CONFIG_RESOL
143873. DS1621_REG_CONFIG_RESOL_SHIFT
143874. DS1621_TEMP_FROM_REG
143875. DS1621_TEMP_MAX
143876. DS1621_TEMP_MIN
143877. DS1621_TEMP_TO_REG
143878. DS1625_CONVERSION_MAX
143879. DS1672_REG_CNT_BASE
143880. DS1672_REG_CONTROL
143881. DS1672_REG_CONTROL_EOSC
143882. DS1672_REG_TRICKLE
143883. DS1682_EEPROM_SIZE
143884. DS1682_REG_ALARM
143885. DS1682_REG_CONFIG
143886. DS1682_REG_EEPROM
143887. DS1682_REG_ELAPSED
143888. DS1682_REG_EVT_CNTR
143889. DS1682_REG_RESET
143890. DS1682_REG_WRITE_DISABLE
143891. DS1682_REG_WRITE_MEM_DISABLE
143892. DS1721_COM_START
143893. DS1781_CONTROL_UVTH
143894. DS1803_010
143895. DS1803_050
143896. DS1803_100
143897. DS1803_CHANNEL
143898. DS1803_MAX_POS
143899. DS1803_WRITE
143900. DS1PR
143901. DS1WM_CLKDIV
143902. DS1WM_CMD
143903. DS1WM_CMD_1W_RESET
143904. DS1WM_CMD_DQ_INPUT
143905. DS1WM_CMD_DQ_OUTPUT
143906. DS1WM_CMD_OD
143907. DS1WM_CMD_RST
143908. DS1WM_CMD_SRA
143909. DS1WM_CNTRL
143910. DS1WM_DATA
143911. DS1WM_INT
143912. DS1WM_INTEN_DQO
143913. DS1WM_INTEN_EPD
143914. DS1WM_INTEN_ERBF
143915. DS1WM_INTEN_ERSRF
143916. DS1WM_INTEN_ETBE
143917. DS1WM_INTEN_ETMT
143918. DS1WM_INTEN_IAS
143919. DS1WM_INTEN_NOT_IAS
143920. DS1WM_INT_EN
143921. DS1WM_INT_PD
143922. DS1WM_INT_PDR
143923. DS1WM_INT_RBF
143924. DS1WM_INT_RSRF
143925. DS1WM_INT_TBE
143926. DS1WM_INT_TSRE
143927. DS1WM_TIMEOUT
143928. DS2
143929. DS2100_3100
143930. DS2404_CLK
143931. DS2404_CONTROL_REG
143932. DS2404_COPY_SCRATCHPAD_CMD
143933. DS2404_DQ
143934. DS2404_READ_MEMORY_CMD
143935. DS2404_READ_SCRATCHPAD_CMD
143936. DS2404_RST
143937. DS2404_RTC_REG
143938. DS2404_STATUS_REG
143939. DS2404_WRITE_SCRATCHPAD_CMD
143940. DS2438_ADC_INPUT_VAD
143941. DS2438_ADC_INPUT_VDD
143942. DS2438_CURRENT_LSB
143943. DS2438_CURRENT_MSB
143944. DS2438_MAX_CONVERSION_TIME
143945. DS2438_PAGE_SIZE
143946. DS2438_STATUS_AD
143947. DS2438_STATUS_ADB
143948. DS2438_STATUS_CA
143949. DS2438_STATUS_EE
143950. DS2438_STATUS_IAD
143951. DS2438_STATUS_NVB
143952. DS2438_STATUS_REG
143953. DS2438_STATUS_TB
143954. DS2438_TEMP_LSB
143955. DS2438_TEMP_MSB
143956. DS2438_THRESHOLD
143957. DS2438_VOLTAGE_LSB
143958. DS2438_VOLTAGE_MSB
143959. DS2482_CMD_1WIRE_READ_BYTE
143960. DS2482_CMD_1WIRE_RESET
143961. DS2482_CMD_1WIRE_SINGLE_BIT
143962. DS2482_CMD_1WIRE_TRIPLET
143963. DS2482_CMD_1WIRE_WRITE_BYTE
143964. DS2482_CMD_CHANNEL_SELECT
143965. DS2482_CMD_RESET
143966. DS2482_CMD_SET_READ_PTR
143967. DS2482_CMD_WRITE_CONFIG
143968. DS2482_PTR_CODE_CHANNEL
143969. DS2482_PTR_CODE_CONFIG
143970. DS2482_PTR_CODE_DATA
143971. DS2482_PTR_CODE_STATUS
143972. DS2482_REG_CFG_1WS
143973. DS2482_REG_CFG_APU
143974. DS2482_REG_CFG_PPM
143975. DS2482_REG_CFG_SPU
143976. DS2482_REG_STS_1WB
143977. DS2482_REG_STS_DIR
143978. DS2482_REG_STS_LL
143979. DS2482_REG_STS_PPD
143980. DS2482_REG_STS_RST
143981. DS2482_REG_STS_SBR
143982. DS2482_REG_STS_SD
143983. DS2482_REG_STS_TSB
143984. DS2482_WAIT_IDLE_TIMEOUT
143985. DS26522_BERT_ADDR_END
143986. DS26522_BERT_ADDR_START
143987. DS26522_CARD
143988. DS26522_E1TAF_ADDR
143989. DS26522_E1TAF_DEFAULT
143990. DS26522_E1TNAF_ADDR
143991. DS26522_E1TNAF_DEFAULT
143992. DS26522_GFCR_ADDR
143993. DS26522_GFCR_BPCLK_2048KHZ
143994. DS26522_GFSRR_ADDR
143995. DS26522_GFSRR_NORMAL
143996. DS26522_GFSRR_RESET
143997. DS26522_GLB_ADDR_END
143998. DS26522_GLB_ADDR_START
143999. DS26522_GLSRR_ADDR
144000. DS26522_GLSRR_NORMAL
144001. DS26522_GLSRR_RESET
144002. DS26522_GTCCR_ADDR
144003. DS26522_GTCCR_BFREQSEL_1544KHZ
144004. DS26522_GTCCR_BFREQSEL_2048KHZ
144005. DS26522_GTCCR_BPREFSEL_REFCLKIN
144006. DS26522_GTCCR_FREQSEL_1544KHZ
144007. DS26522_GTCCR_FREQSEL_2048KHZ
144008. DS26522_GTCR1
144009. DS26522_GTCR1_ADDR
144010. DS26522_GTCR2_ADDR
144011. DS26522_GTCR2_TSSYNCOUT
144012. DS26522_IDR_ADDR
144013. DS26522_LIU_ADDR_END
144014. DS26522_LIU_ADDR_START
144015. DS26522_LMCR_ADDR
144016. DS26522_LMCR_TE
144017. DS26522_LRISMR_100OHM
144018. DS26522_LRISMR_75OHM
144019. DS26522_LRISMR_ADDR
144020. DS26522_LRISMR_MAX
144021. DS26522_LTITSR_ADDR
144022. DS26522_LTITSR_LBOS_75OHM
144023. DS26522_LTITSR_TLIS_0DB_CSU
144024. DS26522_LTITSR_TLIS_100OHM
144025. DS26522_LTITSR_TLIS_75OHM
144026. DS26522_LTRCR_ADDR
144027. DS26522_LTRCR_E1
144028. DS26522_LTRCR_T1
144029. DS26522_RCR1_ADDR
144030. DS26522_RCR1_E1_CCS
144031. DS26522_RCR1_E1_HDB3
144032. DS26522_RCR1_T1_RB8ZS
144033. DS26522_RCR1_T1_SYNCC
144034. DS26522_RCR1_T1_SYNCT
144035. DS26522_RCR3_ADDR
144036. DS26522_RCR3_FLB
144037. DS26522_RF_ADDR_END
144038. DS26522_RF_ADDR_START
144039. DS26522_RIOCR_1544KHZ
144040. DS26522_RIOCR_2048KHZ
144041. DS26522_RIOCR_ADDR
144042. DS26522_RIOCR_RSIO_OUT
144043. DS26522_RMMR_ADDR
144044. DS26522_RMMR_E1
144045. DS26522_RMMR_FRM_EN
144046. DS26522_RMMR_INIT_DONE
144047. DS26522_RMMR_SFTRST
144048. DS26522_RMMR_T1
144049. DS26522_TCR1_ADDR
144050. DS26522_TCR1_TB8ZS
144051. DS26522_TEST_ADDR_END
144052. DS26522_TEST_ADDR_START
144053. DS26522_TF_ADDR_END
144054. DS26522_TF_ADDR_START
144055. DS26522_TIOCR_1544KHZ
144056. DS26522_TIOCR_2048KHZ
144057. DS26522_TIOCR_ADDR
144058. DS26522_TIOCR_TSIO_OUT
144059. DS26522_TMMR_ADDR
144060. DS26522_TMMR_E1
144061. DS26522_TMMR_FRM_EN
144062. DS26522_TMMR_INIT_DONE
144063. DS26522_TMMR_SFTRST
144064. DS26522_TMMR_T1
144065. DS2760_ACTIVE_EMPTY
144066. DS2760_ACTIVE_FULL
144067. DS2760_CURRENT_ACCUM_LSB
144068. DS2760_CURRENT_ACCUM_MSB
144069. DS2760_CURRENT_LSB
144070. DS2760_CURRENT_MSB
144071. DS2760_CURRENT_OFFSET_BIAS
144072. DS2760_DATA_SIZE
144073. DS2760_EEPROM_BLOCK0
144074. DS2760_EEPROM_BLOCK1
144075. DS2760_EEPROM_REG
144076. DS2760_PROTECTION_REG
144077. DS2760_RATED_CAPACITY
144078. DS2760_SPECIAL_FEATURE_REG
144079. DS2760_STATUS_IE
144080. DS2760_STATUS_PMOD
144081. DS2760_STATUS_REG
144082. DS2760_STATUS_RNAOP
144083. DS2760_STATUS_SWEN
144084. DS2760_STATUS_WRITE_REG
144085. DS2760_TEMP_LSB
144086. DS2760_TEMP_MSB
144087. DS2760_VOLTAGE_LSB
144088. DS2760_VOLTAGE_MSB
144089. DS2780_AB_REG
144090. DS2780_ACRL_LSB_REG
144091. DS2780_ACRL_MSB_REG
144092. DS2780_ACR_LSB_REG
144093. DS2780_ACR_MSB_REG
144094. DS2780_AC_LSB_REG
144095. DS2780_AC_MSB_REG
144096. DS2780_AE_0010_SLOPE_REG
144097. DS2780_AE_1020_SLOPE_REG
144098. DS2780_AE_2030_SLOPE_REG
144099. DS2780_AE_3040_SLOPE_REG
144100. DS2780_AE_40_REG
144101. DS2780_AE_LSB_REG
144102. DS2780_AE_MSB_REG
144103. DS2780_AS_REG
144104. DS2780_CHARGE_UNITS
144105. DS2780_CONTROL_REG
144106. DS2780_CONTROL_REG_PMOD
144107. DS2780_CONTROL_REG_RNAOP
144108. DS2780_CONTROL_REG_UVEN
144109. DS2780_CURRENT_LSB_REG
144110. DS2780_CURRENT_MSB_REG
144111. DS2780_CURRENT_UNITS
144112. DS2780_DATA_SIZE
144113. DS2780_EEPROM_BLOCK0_END
144114. DS2780_EEPROM_BLOCK0_START
144115. DS2780_EEPROM_BLOCK1_END
144116. DS2780_EEPROM_BLOCK1_START
144117. DS2780_EEPROM_REG
144118. DS2780_EEPROM_REG_BL0
144119. DS2780_EEPROM_REG_BL1
144120. DS2780_EEPROM_REG_EEC
144121. DS2780_EEPROM_REG_LOCK
144122. DS2780_FRSGAIN_LSB_REG
144123. DS2780_FRSGAIN_MSB_REG
144124. DS2780_FULL_0010_SLOPE_REG
144125. DS2780_FULL_1020_SLOPE_REG
144126. DS2780_FULL_2030_SLOPE_REG
144127. DS2780_FULL_3040_SLOPE_REG
144128. DS2780_FULL_40_LSB_REG
144129. DS2780_FULL_40_MSB_REG
144130. DS2780_FULL_LSB_REG
144131. DS2780_FULL_MSB_REG
144132. DS2780_IAE_REG
144133. DS2780_IAVG_LSB_REG
144134. DS2780_IAVG_MSB_REG
144135. DS2780_IMIN_REG
144136. DS2780_PARAM_EEPROM_SIZE
144137. DS2780_RAAC_LSB_REG
144138. DS2780_RAAC_MSB_REG
144139. DS2780_RARC_REG
144140. DS2780_RSAC_LSB_REG
144141. DS2780_RSAC_MSB_REG
144142. DS2780_RSGAIN_LSB_REG
144143. DS2780_RSGAIN_MSB_REG
144144. DS2780_RSNSP_REG
144145. DS2780_RSRC_REG
144146. DS2780_RSTC_REG
144147. DS2780_SE_0010_SLOPE_REG
144148. DS2780_SE_1020_SLOPE_REG
144149. DS2780_SE_2030_SLOPE_REG
144150. DS2780_SE_3040_SLOPE_REG
144151. DS2780_SE_LSB_REG
144152. DS2780_SE_MSB_REG
144153. DS2780_SFR_REG
144154. DS2780_SFR_REG_PIOSC
144155. DS2780_STATUS_REG
144156. DS2780_STATUS_REG_AEF
144157. DS2780_STATUS_REG_CHGTF
144158. DS2780_STATUS_REG_LEARNF
144159. DS2780_STATUS_REG_PORF
144160. DS2780_STATUS_REG_SEF
144161. DS2780_STATUS_REG_UVF
144162. DS2780_TEMP_LSB_REG
144163. DS2780_TEMP_MSB_REG
144164. DS2780_USER_EEPROM_SIZE
144165. DS2780_VAE_REG
144166. DS2780_VCHG_REG
144167. DS2780_VOLT_LSB_REG
144168. DS2780_VOLT_MSB_REG
144169. DS2781_AB
144170. DS2781_ACRL_LSB
144171. DS2781_ACRL_MSB
144172. DS2781_ACR_LSB
144173. DS2781_ACR_MSB
144174. DS2781_AC_LSB
144175. DS2781_AC_MSB
144176. DS2781_AE_1_SLOPE
144177. DS2781_AE_2_SLOPE
144178. DS2781_AE_3_SLOPE
144179. DS2781_AE_40
144180. DS2781_AE_4_SLOPE
144181. DS2781_AE_LSB
144182. DS2781_AE_MSB
144183. DS2781_AS
144184. DS2781_CHARGE_UNITS
144185. DS2781_COB
144186. DS2781_CONTROL
144187. DS2781_CONTROL_NBEN
144188. DS2781_CONTROL_PMOD
144189. DS2781_CONTROL_RNAOP
144190. DS2781_CONTROL_UVEN
144191. DS2781_CURRENT_LSB
144192. DS2781_CURRENT_MSB
144193. DS2781_CURRENT_UNITS
144194. DS2781_DATA_SIZE
144195. DS2781_EEPROM
144196. DS2781_EEPROM_BL0
144197. DS2781_EEPROM_BL1
144198. DS2781_EEPROM_BLOCK0_END
144199. DS2781_EEPROM_BLOCK0_START
144200. DS2781_EEPROM_BLOCK1_END
144201. DS2781_EEPROM_BLOCK1_START
144202. DS2781_EEPROM_EEC
144203. DS2781_EEPROM_LOCK
144204. DS2781_FSGAIN_LSB
144205. DS2781_FSGAIN_MSB
144206. DS2781_FULL_1_SLOPE
144207. DS2781_FULL_2_SLOPE
144208. DS2781_FULL_3_SLOPE
144209. DS2781_FULL_40_LSB
144210. DS2781_FULL_40_MSB
144211. DS2781_FULL_4_SLOPE
144212. DS2781_FULL_LSB
144213. DS2781_FULL_MSB
144214. DS2781_IAE
144215. DS2781_IAVG_LSB
144216. DS2781_IAVG_MSB
144217. DS2781_IMIN
144218. DS2781_PARAM_EEPROM_SIZE
144219. DS2781_RAAC_LSB
144220. DS2781_RAAC_MSB
144221. DS2781_RARC
144222. DS2781_RSAC_LSB
144223. DS2781_RSAC_MSB
144224. DS2781_RSGAIN_LSB
144225. DS2781_RSGAIN_MSB
144226. DS2781_RSNSP
144227. DS2781_RSRC
144228. DS2781_RSTC
144229. DS2781_SE_1_SLOPE
144230. DS2781_SE_2_SLOPE
144231. DS2781_SE_3_SLOPE
144232. DS2781_SE_4_SLOPE
144233. DS2781_SE_LSB
144234. DS2781_SE_MSB
144235. DS2781_SFR
144236. DS2781_SFR_PIOSC
144237. DS2781_STATUS
144238. DS2781_STATUS_AEF
144239. DS2781_STATUS_CHGTF
144240. DS2781_STATUS_LEARNF
144241. DS2781_STATUS_PORF
144242. DS2781_STATUS_SEF
144243. DS2781_STATUS_UVF
144244. DS2781_TBP12
144245. DS2781_TBP23
144246. DS2781_TBP34
144247. DS2781_TEMP_LSB
144248. DS2781_TEMP_MSB
144249. DS2781_USER_EEPROM_SIZE
144250. DS2781_VAE
144251. DS2781_VCHG
144252. DS2781_VOLT_LSB
144253. DS2781_VOLT_MSB
144254. DS2782
144255. DS2782_CURRENT_UNITS
144256. DS2782_REG_RARC
144257. DS2782_REG_RSNSP
144258. DS2786
144259. DS2786_CURRENT_UNITS
144260. DS2786_REG_RARC
144261. DS278x_DELAY
144262. DS278x_REG_CURRENT_MSB
144263. DS278x_REG_TEMP_MSB
144264. DS278x_REG_VOLT_MSB
144265. DS2PHYS
144266. DS2PR
144267. DS3
144268. DS3000_DEFAULT_FIRMWARE
144269. DS3000_H
144270. DS3000_SAMPLE_RATE
144271. DS3231_BIT_BBSQW
144272. DS3231_BIT_EN32KHZ
144273. DS3231_CLK_32KHZ
144274. DS3231_CLK_SQW
144275. DS3231_REG_TEMPERATURE
144276. DS3232_REG_ALARM1
144277. DS3232_REG_ALARM2
144278. DS3232_REG_AMPM
144279. DS3232_REG_CENTURY
144280. DS3232_REG_CR
144281. DS3232_REG_CR_A1IE
144282. DS3232_REG_CR_A2IE
144283. DS3232_REG_CR_INTCN
144284. DS3232_REG_CR_nEOSC
144285. DS3232_REG_DATE
144286. DS3232_REG_DAY
144287. DS3232_REG_HOURS
144288. DS3232_REG_MINUTES
144289. DS3232_REG_MONTH
144290. DS3232_REG_SECONDS
144291. DS3232_REG_SR
144292. DS3232_REG_SRAM_END
144293. DS3232_REG_SRAM_SIZE
144294. DS3232_REG_SRAM_START
144295. DS3232_REG_SR_A1F
144296. DS3232_REG_SR_A2F
144297. DS3232_REG_SR_BSY
144298. DS3232_REG_SR_OSF
144299. DS3232_REG_TEMPERATURE
144300. DS3232_REG_YEAR
144301. DS3303u
144302. DS4422_MAX_DAC_CHANNELS
144303. DS4424_CHANNEL
144304. DS4424_DAC_ADDR
144305. DS4424_MAX_DAC_CHANNELS
144306. DS4424_SINK_I
144307. DS4424_SOURCE_I
144308. DS4_ACC_RES_PER_G
144309. DS4_BT_DEFAULT_POLL_INTERVAL_MS
144310. DS4_BT_MAX_POLL_INTERVAL_MS
144311. DS4_FEATURE_REPORT_0x02_SIZE
144312. DS4_FEATURE_REPORT_0x05_SIZE
144313. DS4_FEATURE_REPORT_0x81_SIZE
144314. DS4_FEATURE_REPORT_0xA3_SIZE
144315. DS4_GYRO_RES_PER_DEG_S
144316. DS4_INPUT_REPORT_0x11_SIZE
144317. DS4_INPUT_REPORT_AXIS_OFFSET
144318. DS4_INPUT_REPORT_BATTERY_OFFSET
144319. DS4_INPUT_REPORT_BUTTON_OFFSET
144320. DS4_INPUT_REPORT_GYRO_X_OFFSET
144321. DS4_INPUT_REPORT_TIMESTAMP_OFFSET
144322. DS4_INPUT_REPORT_TOUCHPAD_OFFSET
144323. DS4_OUTPUT_REPORT_0x05_SIZE
144324. DS4_OUTPUT_REPORT_0x11_SIZE
144325. DS4_TOUCHPAD_SUFFIX
144326. DS5000_1XX
144327. DS5000_200
144328. DS5000_2X0
144329. DS5000_XX
144330. DS5000_xx_ONBOARD_FBMEM_START
144331. DS5100
144332. DS5400
144333. DS5500
144334. DS5800
144335. DS620_COM_START
144336. DS620_COM_STOP
144337. DS620_REG_CONF
144338. DS620_REG_CONFIG_1SHOT
144339. DS620_REG_CONFIG_A0
144340. DS620_REG_CONFIG_A1
144341. DS620_REG_CONFIG_A2
144342. DS620_REG_CONFIG_AUTOC
144343. DS620_REG_CONFIG_DONE
144344. DS620_REG_CONFIG_NVB
144345. DS620_REG_CONFIG_PO1
144346. DS620_REG_CONFIG_PO2
144347. DS620_REG_CONFIG_R0
144348. DS620_REG_CONFIG_R1
144349. DS620_REG_CONFIG_THF
144350. DS620_REG_CONFIG_TLF
144351. DSA
144352. DSADR
144353. DSAFV2_CFG_VLAN_TAG_MODE_S
144354. DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG
144355. DSAFV2_INODE_IN_PORT1_NUM_M
144356. DSAFV2_INODE_IN_PORT1_NUM_S
144357. DSAFV2_INODE_IN_PORT2_NUM_M
144358. DSAFV2_INODE_IN_PORT2_NUM_S
144359. DSAFV2_INODE_IN_PORT3_NUM_M
144360. DSAFV2_INODE_IN_PORT3_NUM_S
144361. DSAFV2_INODE_IN_PORT4_NUM_M
144362. DSAFV2_INODE_IN_PORT4_NUM_S
144363. DSAFV2_INODE_IN_PORT5_NUM_M
144364. DSAFV2_INODE_IN_PORT5_NUM_S
144365. DSAFV2_MAC_FUZZY_TCAM_NUM
144366. DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG
144367. DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M
144368. DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S
144369. DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M
144370. DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S
144371. DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M
144372. DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S
144373. DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M
144374. DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S
144375. DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M
144376. DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S
144377. DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M
144378. DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S
144379. DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M
144380. DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S
144381. DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M
144382. DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S
144383. DSAFV2_SBM_CFG2_RESET_BUF_NUM_M
144384. DSAFV2_SBM_CFG2_RESET_BUF_NUM_S
144385. DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M
144386. DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S
144387. DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M
144388. DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S
144389. DSAFV2_SBM_CFG2_SET_BUF_NUM_M
144390. DSAFV2_SBM_CFG2_SET_BUF_NUM_S
144391. DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M
144392. DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S
144393. DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M
144394. DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S
144395. DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M
144396. DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S
144397. DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M
144398. DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S
144399. DSAFV2_SBM_NUM
144400. DSAFV2_SBM_PPE_CHN
144401. DSAFV2_SBM_XGE_CHN
144402. DSAFV2_SERDES_LBK_0_REG
144403. DSAFV2_SERDES_LBK_EN_B
144404. DSAFV2_SERDES_LBK_QID_M
144405. DSAFV2_SERDES_LBK_QID_S
144406. DSAFV2_SRAM_INIT_OVER_M
144407. DSAF_ABNORMAL_TIMEOUT_0_REG
144408. DSAF_BASE_INNER_PORT_NUM
144409. DSAF_CFG_0_REG
144410. DSAF_CFG_CRC_EN_S
144411. DSAF_CFG_EN_S
144412. DSAF_CFG_LOCA_ADDR_EN_S
144413. DSAF_CFG_MIX_MODE_S
144414. DSAF_CFG_READ_CNT
144415. DSAF_CFG_SBM_INIT_S
144416. DSAF_CFG_STP_MODE_S
144417. DSAF_CFG_TC_MODE_S
144418. DSAF_CHNS_MASK
144419. DSAF_CNT_CLR_CE_S
144420. DSAF_COMM_CHN
144421. DSAF_COMM_DEV_NUM
144422. DSAF_DEBUG_NW_NUM
144423. DSAF_DEFAUTL_QUEUE_NUM_PER_PPE
144424. DSAF_DEST_PORT_NUM
144425. DSAF_DEVICE_NAME
144426. DSAF_DRV_NAME
144427. DSAF_DSA_REG_CNT_CLR_CE_REG
144428. DSAF_DSA_SBM_INF_FIFO_THRD_REG
144429. DSAF_DSA_SRAM_1BIT_ECC_CNT_REG
144430. DSAF_DSA_SRAM_1BIT_ECC_SEL_REG
144431. DSAF_DUMP_REGS_NUM
144432. DSAF_ECC_ERR_INVERT_0_REG
144433. DSAF_FC_XGE_TX_PAUSE_S
144434. DSAF_FSM_TIMEOUT_0_REG
144435. DSAF_GE_NUM
144436. DSAF_INODE_BD_ORDER_STATUS_0_REG
144437. DSAF_INODE_BD_SAVE_STATUS_0_REG
144438. DSAF_INODE_BP_DISCARD_NUM_0_REG
144439. DSAF_INODE_BP_STATUS_0_REG
144440. DSAF_INODE_CRC_FALSE_NUM_0_REG
144441. DSAF_INODE_CUT_THROUGH_CFG_0_REG
144442. DSAF_INODE_ECC_ERR_ADDR_0_REG
144443. DSAF_INODE_ECC_INVERT_EN_0_REG
144444. DSAF_INODE_FIFO_WL_0_REG
144445. DSAF_INODE_FINAL_IN_MAN_NUM_0_REG
144446. DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG
144447. DSAF_INODE_FINAL_IN_PKT_NUM_0_REG
144448. DSAF_INODE_GE_FC_EN_0_REG
144449. DSAF_INODE_IN_DATA_STP_DISC_0_REG
144450. DSAF_INODE_IN_PORT_NUM_0_REG
144451. DSAF_INODE_IN_PORT_NUM_M
144452. DSAF_INODE_IN_PORT_NUM_S
144453. DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET
144454. DSAF_INODE_IN_PRIO_PAUSE_BASE_REG
144455. DSAF_INODE_IN_PRIO_PAUSE_OFFSET
144456. DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG
144457. DSAF_INODE_NUM
144458. DSAF_INODE_PAD_DISCARD_NUM_0_REG
144459. DSAF_INODE_PRI_TC_CFG_0_REG
144460. DSAF_INODE_RSLT_DISCARD_NUM_0_REG
144461. DSAF_INODE_SBM_DROP_NUM_0_REG
144462. DSAF_INODE_SBM_PID_NUM_0_REG
144463. DSAF_INODE_SBM_RELS_NUM_0_REG
144464. DSAF_INODE_SW_VLAN_TAG_DISC_0_REG
144465. DSAF_INODE_VC0_IN_PKT_NUM_0_REG
144466. DSAF_INODE_VC1_IN_PKT_NUM_0_REG
144467. DSAF_INODE_VOQ_OVER_NUM_0_REG
144468. DSAF_INVALID_ENTRY_IDX
144469. DSAF_LED_ANCHOR_B
144470. DSAF_LED_DATA_B
144471. DSAF_LED_LINK_B
144472. DSAF_LED_SPEED_M
144473. DSAF_LED_SPEED_S
144474. DSAF_LINE_SUM
144475. DSAF_MAC_PAUSE_RX_EN_B
144476. DSAF_MAX_CHIP_NUM
144477. DSAF_MAX_PORT_NUM
144478. DSAF_MAX_VM_NUM
144479. DSAF_MIX_DEF_QID_0_REG
144480. DSAF_MODE_DISABLE_2PORT_16VM
144481. DSAF_MODE_DISABLE_2PORT_64VM
144482. DSAF_MODE_DISABLE_2PORT_8VM
144483. DSAF_MODE_DISABLE_6PORT_0VM
144484. DSAF_MODE_DISABLE_6PORT_16VM
144485. DSAF_MODE_DISABLE_6PORT_2VM
144486. DSAF_MODE_DISABLE_6PORT_4VM
144487. DSAF_MODE_DISABLE_FIX
144488. DSAF_MODE_DISABLE_SP
144489. DSAF_MODE_ENABLE
144490. DSAF_MODE_ENABLE_0VM
144491. DSAF_MODE_ENABLE_128VM
144492. DSAF_MODE_ENABLE_16VM
144493. DSAF_MODE_ENABLE_32VM
144494. DSAF_MODE_ENABLE_8VM
144495. DSAF_MODE_ENABLE_FIX
144496. DSAF_MODE_INVALID
144497. DSAF_MODE_MAX
144498. DSAF_MOD_VERSION
144499. DSAF_NETPORT_CTRL_SIG_0_REG
144500. DSAF_NODE_NUM
144501. DSAF_ONODE_FIFO_WL_0_REG
144502. DSAF_PAUSE_CFG_REG
144503. DSAF_PFC_EN_0_REG
144504. DSAF_PFC_PAUSE_RX_EN_B
144505. DSAF_PFC_PAUSE_TX_EN_B
144506. DSAF_PFC_UNINT_CNT_M
144507. DSAF_PFC_UNINT_CNT_S
144508. DSAF_PFC_UNIT_CNT_0_REG
144509. DSAF_PORT_DEF_VLAN_0_REG
144510. DSAF_PORT_MSK_NUM
144511. DSAF_PORT_RATE_1000
144512. DSAF_PORT_RATE_10000
144513. DSAF_PORT_RATE_2500
144514. DSAF_PORT_TYPE_NUM
144515. DSAF_PPE_INODE_BASE
144516. DSAF_PPE_INT_MSK_0_REG
144517. DSAF_PPE_INT_SRC_0_REG
144518. DSAF_PPE_INT_STS_0_REG
144519. DSAF_PPE_QID_CFG_0_REG
144520. DSAF_PPE_QID_CFG_M
144521. DSAF_PPE_QID_CFG_S
144522. DSAF_PRIO_NR
144523. DSAF_REGS_XGE_CNT_CAR_S
144524. DSAF_REG_PER_ZONE
144525. DSAF_ROCEE_INT_MSK_0_REG
144526. DSAF_ROCEE_INT_SRC_0_REG
144527. DSAF_ROCEE_INT_STS_0_REG
144528. DSAF_ROCE_2PORT_MODE
144529. DSAF_ROCE_4PORT_MODE
144530. DSAF_ROCE_6PORT_MODE
144531. DSAF_ROCE_CHAN_MODE
144532. DSAF_ROCE_CHAN_MODE_NUM
144533. DSAF_ROCE_CREDIT_CHN
144534. DSAF_ROCE_PORT_0
144535. DSAF_ROCE_PORT_1
144536. DSAF_ROCE_PORT_2
144537. DSAF_ROCE_PORT_3
144538. DSAF_ROCE_PORT_4
144539. DSAF_ROCE_PORT_5
144540. DSAF_ROCE_PORT_MAP_REG
144541. DSAF_ROCE_SL_0
144542. DSAF_ROCE_SL_1
144543. DSAF_ROCE_SL_2
144544. DSAF_ROCE_SL_3
144545. DSAF_ROCE_SL_MAP_REG
144546. DSAF_SBM_BP_CFG_0_PPE_REG_0_REG
144547. DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG
144548. DSAF_SBM_BP_CFG_0_XGE_REG_0_REG
144549. DSAF_SBM_BP_CFG_1_REG_0_REG
144550. DSAF_SBM_BP_CFG_2_PPE_REG_0_REG
144551. DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG
144552. DSAF_SBM_BP_CFG_2_XGE_REG_0_REG
144553. DSAF_SBM_BP_CFG_3_REG_0_REG
144554. DSAF_SBM_BP_CFG_4_REG_0_REG
144555. DSAF_SBM_BP_CNT_0_0_REG
144556. DSAF_SBM_BP_CNT_1_0_REG
144557. DSAF_SBM_BP_CNT_2_0_REG
144558. DSAF_SBM_BP_CNT_3_0_REG
144559. DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M
144560. DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S
144561. DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M
144562. DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S
144563. DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M
144564. DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S
144565. DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M
144566. DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S
144567. DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M
144568. DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S
144569. DSAF_SBM_CFG2_RESET_BUF_NUM_M
144570. DSAF_SBM_CFG2_RESET_BUF_NUM_S
144571. DSAF_SBM_CFG2_SET_BUF_NUM_M
144572. DSAF_SBM_CFG2_SET_BUF_NUM_S
144573. DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M
144574. DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S
144575. DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M
144576. DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S
144577. DSAF_SBM_CFG_ECC_INVERT_EN_S
144578. DSAF_SBM_CFG_EN_S
144579. DSAF_SBM_CFG_MIB_EN_S
144580. DSAF_SBM_CFG_REG_0_REG
144581. DSAF_SBM_CFG_SHCUT_EN_S
144582. DSAF_SBM_FREE_CNT_0_0_REG
144583. DSAF_SBM_FREE_CNT_1_0_REG
144584. DSAF_SBM_INER_ST_0_REG
144585. DSAF_SBM_INF_OUTPORT_CNT_0_REG
144586. DSAF_SBM_LNK_DROP_CNT_0_REG
144587. DSAF_SBM_LNK_INPORT_CNT_0_REG
144588. DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG
144589. DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG
144590. DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG
144591. DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG
144592. DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG
144593. DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG
144594. DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG
144595. DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG
144596. DSAF_SBM_LNK_RELS_CNT_0_REG
144597. DSAF_SBM_LNK_REQ_CNT_0_REG
144598. DSAF_SBM_MIB_REQ_FAILED_TC_0_REG
144599. DSAF_SBM_NUM
144600. DSAF_SBM_ROCEE_CFG_CRD_EN_B
144601. DSAF_SBM_ROCEE_CFG_REG_REG
144602. DSAF_SERVICE_NW_NUM
144603. DSAF_SNAP_EN_S
144604. DSAF_SRAM_INIT_OVER_0_REG
144605. DSAF_SRAM_INIT_OVER_M
144606. DSAF_SRAM_INIT_OVER_S
144607. DSAF_STATIC_NUM
144608. DSAF_STATS_READ
144609. DSAF_STP_PORT_TYPE_0_REG
144610. DSAF_STP_PORT_TYPE_BLOCK
144611. DSAF_STP_PORT_TYPE_DISCARD
144612. DSAF_STP_PORT_TYPE_FORWARD
144613. DSAF_STP_PORT_TYPE_LEARN
144614. DSAF_STP_PORT_TYPE_LISTEN
144615. DSAF_STP_PORT_TYPE_M
144616. DSAF_STP_PORT_TYPE_S
144617. DSAF_SUB_BASE_SIZE
144618. DSAF_SUB_SC_CPU_CLK_ST_REG
144619. DSAF_SUB_SC_DSAF_CLK_DIS_REG
144620. DSAF_SUB_SC_DSAF_CLK_EN_REG
144621. DSAF_SUB_SC_DSAF_CLK_ST_REG
144622. DSAF_SUB_SC_DSAF_RESET_DREQ_REG
144623. DSAF_SUB_SC_DSAF_RESET_REQ_REG
144624. DSAF_SUB_SC_GE_CLK_DIS_REG
144625. DSAF_SUB_SC_GE_CLK_EN_REG
144626. DSAF_SUB_SC_GE_CLK_ST_REG
144627. DSAF_SUB_SC_GE_RESET_DREQ0_REG
144628. DSAF_SUB_SC_GE_RESET_DREQ1_REG
144629. DSAF_SUB_SC_GE_RESET_REQ0_REG
144630. DSAF_SUB_SC_GE_RESET_REQ1_REG
144631. DSAF_SUB_SC_GE_RESET_ST0_REG
144632. DSAF_SUB_SC_GE_RESET_ST1_REG
144633. DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG
144634. DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG
144635. DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG
144636. DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG
144637. DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG
144638. DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG
144639. DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG
144640. DSAF_SUB_SC_NT_CLK_DIS_REG
144641. DSAF_SUB_SC_NT_CLK_EN_REG
144642. DSAF_SUB_SC_NT_CLK_ST_REG
144643. DSAF_SUB_SC_NT_RESET_DREQ_REG
144644. DSAF_SUB_SC_NT_RESET_REQ_REG
144645. DSAF_SUB_SC_NT_RESET_ST_REG
144646. DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG
144647. DSAF_SUB_SC_PPE_CLK_DIS_REG
144648. DSAF_SUB_SC_PPE_CLK_EN_REG
144649. DSAF_SUB_SC_PPE_CLK_ST_REG
144650. DSAF_SUB_SC_PPE_RESET_DREQ_REG
144651. DSAF_SUB_SC_PPE_RESET_REQ_REG
144652. DSAF_SUB_SC_PPE_RESET_ST_REG
144653. DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG
144654. DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG
144655. DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG
144656. DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG
144657. DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG
144658. DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG
144659. DSAF_SUB_SC_ROCEE_CLK_DIS_REG
144660. DSAF_SUB_SC_ROCEE_CLK_EN_REG
144661. DSAF_SUB_SC_ROCEE_CLK_ST_REG
144662. DSAF_SUB_SC_ROCEE_RESET_DREQ_REG
144663. DSAF_SUB_SC_ROCEE_RESET_REQ_REG
144664. DSAF_SUB_SC_TCAM_MBIST_EN_REG
144665. DSAF_SUB_SC_XBAR_RESET_DREQ_REG
144666. DSAF_SUB_SC_XBAR_RESET_REQ_REG
144667. DSAF_SUB_SC_XBAR_RESET_ST_REG
144668. DSAF_SUB_SC_XGE_CLK_DIS_REG
144669. DSAF_SUB_SC_XGE_CLK_EN_REG
144670. DSAF_SUB_SC_XGE_CLK_ST_REG
144671. DSAF_SUB_SC_XGE_RESET_DREQ_REG
144672. DSAF_SUB_SC_XGE_RESET_REQ_REG
144673. DSAF_SUB_SC_XGE_RESET_ST_REG
144674. DSAF_SW_PORT_NUM
144675. DSAF_SW_PORT_TYPE_0_REG
144676. DSAF_SW_PORT_TYPE_ACCESS
144677. DSAF_SW_PORT_TYPE_M
144678. DSAF_SW_PORT_TYPE_NON_VLAN
144679. DSAF_SW_PORT_TYPE_S
144680. DSAF_SW_PORT_TYPE_TRUNK
144681. DSAF_TBL_CTRL_0_REG
144682. DSAF_TBL_DA0_MIS_INFO0_0_REG
144683. DSAF_TBL_DA0_MIS_INFO1_0_REG
144684. DSAF_TBL_DFX_BC_LKUP_NUM_EN_S
144685. DSAF_TBL_DFX_CTRL_0_REG
144686. DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S
144687. DSAF_TBL_DFX_MC_LKUP_NUM_EN_S
144688. DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S
144689. DSAF_TBL_DFX_STAT_0_REG
144690. DSAF_TBL_DFX_STAT_2_0_REG
144691. DSAF_TBL_DFX_UC_LKUP_NUM_EN_S
144692. DSAF_TBL_INT_MSK_0_REG
144693. DSAF_TBL_INT_SRC_0_REG
144694. DSAF_TBL_INT_STS_0_REG
144695. DSAF_TBL_LINE_ADDR_0_REG
144696. DSAF_TBL_LINE_ADDR_M
144697. DSAF_TBL_LINE_ADDR_S
144698. DSAF_TBL_LINE_CFG_DVC_S
144699. DSAF_TBL_LINE_CFG_MAC_DISCARD_S
144700. DSAF_TBL_LINE_CFG_OUT_PORT_M
144701. DSAF_TBL_LINE_CFG_OUT_PORT_S
144702. DSAF_TBL_LIN_CFG_0_REG
144703. DSAF_TBL_LIN_RDATA_0_REG
144704. DSAF_TBL_LKUP_NUM_I_0_REG
144705. DSAF_TBL_LKUP_NUM_O_0_REG
144706. DSAF_TBL_MCAST_CFG0_VM25_0_M
144707. DSAF_TBL_MCAST_CFG0_VM25_0_S
144708. DSAF_TBL_MCAST_CFG0_XGE5_0_M
144709. DSAF_TBL_MCAST_CFG0_XGE5_0_S
144710. DSAF_TBL_MCAST_CFG4_ITEM_VLD_S
144711. DSAF_TBL_MCAST_CFG4_OLD_EN_S
144712. DSAF_TBL_MCAST_CFG4_VM128_112_M
144713. DSAF_TBL_MCAST_CFG4_VM128_112_S
144714. DSAF_TBL_NUM
144715. DSAF_TBL_OLD_RSLT_0_REG
144716. DSAF_TBL_OLD_SCAN_VAL_0_REG
144717. DSAF_TBL_PUL_0_REG
144718. DSAF_TBL_PUL_LINE_LOAD_S
144719. DSAF_TBL_PUL_LINE_VLD_S
144720. DSAF_TBL_PUL_MCAST_VLD_S
144721. DSAF_TBL_PUL_OLD_RSLT_RE_S
144722. DSAF_TBL_PUL_TCAM_DATA_VLD_S
144723. DSAF_TBL_PUL_TCAM_LOAD_S
144724. DSAF_TBL_PUL_UCAST_VLD_S
144725. DSAF_TBL_SA_MIS_INFO0_0_REG
144726. DSAF_TBL_SA_MIS_INFO1_0_REG
144727. DSAF_TBL_SA_MIS_INFO2_0_REG
144728. DSAF_TBL_TCAM_ADDR_0_REG
144729. DSAF_TBL_TCAM_ADDR_M
144730. DSAF_TBL_TCAM_ADDR_S
144731. DSAF_TBL_TCAM_HIGH_0_REG
144732. DSAF_TBL_TCAM_KEY_PORT_M
144733. DSAF_TBL_TCAM_KEY_PORT_S
144734. DSAF_TBL_TCAM_KEY_VLAN_M
144735. DSAF_TBL_TCAM_KEY_VLAN_S
144736. DSAF_TBL_TCAM_LOW_0_REG
144737. DSAF_TBL_TCAM_MATCH_CFG_H_REG
144738. DSAF_TBL_TCAM_MATCH_CFG_L_REG
144739. DSAF_TBL_TCAM_MCAST_CFG_0_0_REG
144740. DSAF_TBL_TCAM_MCAST_CFG_1_0_REG
144741. DSAF_TBL_TCAM_MCAST_CFG_2_0_REG
144742. DSAF_TBL_TCAM_MCAST_CFG_3_0_REG
144743. DSAF_TBL_TCAM_MCAST_CFG_4_0_REG
144744. DSAF_TBL_TCAM_RAM_RDATA0_0_REG
144745. DSAF_TBL_TCAM_RAM_RDATA1_0_REG
144746. DSAF_TBL_TCAM_RAM_RDATA2_0_REG
144747. DSAF_TBL_TCAM_RAM_RDATA3_0_REG
144748. DSAF_TBL_TCAM_RAM_RDATA4_0_REG
144749. DSAF_TBL_TCAM_RDATA_HIGH_0_REG
144750. DSAF_TBL_TCAM_RDATA_LOW_0_REG
144751. DSAF_TBL_TCAM_UCAST_CFG_0_REG
144752. DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG
144753. DSAF_TBL_UCAST_CFG1_DVC_S
144754. DSAF_TBL_UCAST_CFG1_ITEM_VLD_S
144755. DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S
144756. DSAF_TBL_UCAST_CFG1_OLD_EN_S
144757. DSAF_TBL_UCAST_CFG1_OUT_PORT_M
144758. DSAF_TBL_UCAST_CFG1_OUT_PORT_S
144759. DSAF_TCAM_SUM
144760. DSAF_TOTAL_QUEUE_NUM
144761. DSAF_V2_STATIC_NUM
144762. DSAF_VM_DEF_VLAN_0_REG
144763. DSAF_VOQ_BP_ALL_DOWNTHRD_M
144764. DSAF_VOQ_BP_ALL_DOWNTHRD_S
144765. DSAF_VOQ_BP_ALL_THRD_0_REG
144766. DSAF_VOQ_BP_ALL_UPTHRD_M
144767. DSAF_VOQ_BP_ALL_UPTHRD_S
144768. DSAF_VOQ_BP_STATUS_0_REG
144769. DSAF_VOQ_ECC_ERR_ADDR_0_REG
144770. DSAF_VOQ_ECC_INVERT_EN_0_REG
144771. DSAF_VOQ_IN_PKT_NUM_0_REG
144772. DSAF_VOQ_NUM
144773. DSAF_VOQ_OUT_PKT_NUM_0_REG
144774. DSAF_VOQ_PPE_XOD_REQ_0_REG
144775. DSAF_VOQ_ROCEE_XOD_REQ_0_REG
144776. DSAF_VOQ_SPUP_IDLE_0_REG
144777. DSAF_VOQ_SRAM_PKT_NUM_0_REG
144778. DSAF_VOQ_XGE_XOD_REQ_0_0_REG
144779. DSAF_VOQ_XGE_XOD_REQ_1_0_REG
144780. DSAF_WORD_BIT_CNT
144781. DSAF_XGE_APP_RX_LINK_UP_0_REG
144782. DSAF_XGE_CTRL_SIG_CFG_0_REG
144783. DSAF_XGE_GE_LOOPBACK_S
144784. DSAF_XGE_GE_WORK_MODE_0_REG
144785. DSAF_XGE_GE_WORK_MODE_S
144786. DSAF_XGE_INT_MSK_0_REG
144787. DSAF_XGE_INT_SRC_0_REG
144788. DSAF_XGE_INT_STS_0_REG
144789. DSAF_XGE_NUM
144790. DSAF_XOD_BIG_NUM
144791. DSAF_XOD_CONNECT_STATE_0_REG
144792. DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG
144793. DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG
144794. DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG
144795. DSAF_XOD_ETS_TOKEN_CFG_0_REG
144796. DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG
144797. DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG
144798. DSAF_XOD_FIFO_STATUS_0_REG
144799. DSAF_XOD_GNT_H_0_REG
144800. DSAF_XOD_GNT_L_0_REG
144801. DSAF_XOD_NUM
144802. DSAF_XOD_PFS_CFG_0_0_REG
144803. DSAF_XOD_PFS_CFG_1_0_REG
144804. DSAF_XOD_PFS_CFG_2_0_REG
144805. DSAF_XOD_PPE_RCVIN0_CNT_0_REG
144806. DSAF_XOD_PPE_RCVIN1_CNT_0_REG
144807. DSAF_XOD_RCVPKT_CNT_0_REG
144808. DSAF_XOD_RCVTC0_CNT_0_REG
144809. DSAF_XOD_RCVTC1_CNT_0_REG
144810. DSAF_XOD_RCVTC2_CNT_0_REG
144811. DSAF_XOD_RCVTC3_CNT_0_REG
144812. DSAF_XOD_RCVVC0_CNT_0_REG
144813. DSAF_XOD_RCVVC1_CNT_0_REG
144814. DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG
144815. DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG
144816. DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG
144817. DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET
144818. DSAF_XOD_XGE_RCVIN0_CNT_0_REG
144819. DSAF_XOD_XGE_RCVIN1_CNT_0_REG
144820. DSAF_XOD_XGE_RCVIN2_CNT_0_REG
144821. DSAF_XOD_XGE_RCVIN3_CNT_0_REG
144822. DSAF_XOD_XGE_RCVIN4_CNT_0_REG
144823. DSAF_XOD_XGE_RCVIN5_CNT_0_REG
144824. DSAF_XOD_XGE_RCVIN6_CNT_0_REG
144825. DSAF_XOD_XGE_RCVIN7_CNT_0_REG
144826. DSA_8021Q_DIR
144827. DSA_8021Q_DIR_MASK
144828. DSA_8021Q_DIR_RX
144829. DSA_8021Q_DIR_SHIFT
144830. DSA_8021Q_DIR_TX
144831. DSA_8021Q_PORT
144832. DSA_8021Q_PORT_MASK
144833. DSA_8021Q_PORT_SHIFT
144834. DSA_8021Q_SWITCH_ID
144835. DSA_8021Q_SWITCH_ID_MASK
144836. DSA_8021Q_SWITCH_ID_SHIFT
144837. DSA_BCR
144838. DSA_CORE_CLK
144839. DSA_CORE_CLK_SRC
144840. DSA_HLEN
144841. DSA_LOOP_CPU_PORT
144842. DSA_LOOP_NUM_PORTS
144843. DSA_LOOP_PHY_READ_ERR
144844. DSA_LOOP_PHY_READ_OK
144845. DSA_LOOP_PHY_WRITE_ERR
144846. DSA_LOOP_PHY_WRITE_OK
144847. DSA_LOOP_VLANS
144848. DSA_MAX_PORTS
144849. DSA_MAX_SWITCHES
144850. DSA_NOC_CFG_AHB_CLK
144851. DSA_NOTIFIER_AGEING_TIME
144852. DSA_NOTIFIER_BRIDGE_JOIN
144853. DSA_NOTIFIER_BRIDGE_LEAVE
144854. DSA_NOTIFIER_FDB_ADD
144855. DSA_NOTIFIER_FDB_DEL
144856. DSA_NOTIFIER_MDB_ADD
144857. DSA_NOTIFIER_MDB_DEL
144858. DSA_NOTIFIER_VLAN_ADD
144859. DSA_NOTIFIER_VLAN_DEL
144860. DSA_PDB_L_MASK
144861. DSA_PDB_L_SHIFT
144862. DSA_PDB_N_MASK
144863. DSA_PDB_SGF_AB_SIGN
144864. DSA_PDB_SGF_AB_VERIFY
144865. DSA_PDB_SGF_C
144866. DSA_PDB_SGF_D
144867. DSA_PDB_SGF_F
144868. DSA_PDB_SGF_G
144869. DSA_PDB_SGF_MASK
144870. DSA_PDB_SGF_Q
144871. DSA_PDB_SGF_R
144872. DSA_PDB_SGF_S
144873. DSA_PDB_SGF_SHIFT
144874. DSA_PDB_SGF_W
144875. DSA_PORT_MALL_MIRROR
144876. DSA_PORT_REGISTER
144877. DSA_PORT_TYPE_CPU
144878. DSA_PORT_TYPE_DSA
144879. DSA_PORT_TYPE_UNUSED
144880. DSA_PORT_TYPE_USER
144881. DSA_PORT_UNREGISTER
144882. DSA_RTABLE_NONE
144883. DSA_SKB_CB
144884. DSA_SKB_CB_PRIV
144885. DSA_TAG_DRIVER
144886. DSA_TAG_DRIVER_ALIAS
144887. DSA_TAG_DRIVER_NAME
144888. DSA_TAG_PROTO_8021Q
144889. DSA_TAG_PROTO_8021Q_VALUE
144890. DSA_TAG_PROTO_BRCM
144891. DSA_TAG_PROTO_BRCM_PREPEND
144892. DSA_TAG_PROTO_BRCM_PREPEND_VALUE
144893. DSA_TAG_PROTO_BRCM_VALUE
144894. DSA_TAG_PROTO_DSA
144895. DSA_TAG_PROTO_DSA_VALUE
144896. DSA_TAG_PROTO_EDSA
144897. DSA_TAG_PROTO_EDSA_VALUE
144898. DSA_TAG_PROTO_GSWIP
144899. DSA_TAG_PROTO_GSWIP_VALUE
144900. DSA_TAG_PROTO_KSZ8795
144901. DSA_TAG_PROTO_KSZ8795_VALUE
144902. DSA_TAG_PROTO_KSZ9477
144903. DSA_TAG_PROTO_KSZ9477_VALUE
144904. DSA_TAG_PROTO_KSZ9893
144905. DSA_TAG_PROTO_KSZ9893_VALUE
144906. DSA_TAG_PROTO_LAN9303
144907. DSA_TAG_PROTO_LAN9303_VALUE
144908. DSA_TAG_PROTO_MTK
144909. DSA_TAG_PROTO_MTK_VALUE
144910. DSA_TAG_PROTO_NONE
144911. DSA_TAG_PROTO_NONE_VALUE
144912. DSA_TAG_PROTO_QCA
144913. DSA_TAG_PROTO_QCA_VALUE
144914. DSA_TAG_PROTO_SJA1105
144915. DSA_TAG_PROTO_SJA1105_VALUE
144916. DSA_TAG_PROTO_TRAILER
144917. DSA_TAG_PROTO_TRAILER_VALUE
144918. DSB100_ONOFF
144919. DSB100_PRODUCT
144920. DSB100_TUNE
144921. DSB100_VENDOR
144922. DSBC_MASK
144923. DSC2_SF
144924. DSCA_PICTURE_PARAMETER_SET_0
144925. DSCA_PICTURE_PARAMETER_SET_1
144926. DSCA_PICTURE_PARAMETER_SET_10
144927. DSCA_PICTURE_PARAMETER_SET_11
144928. DSCA_PICTURE_PARAMETER_SET_12
144929. DSCA_PICTURE_PARAMETER_SET_13
144930. DSCA_PICTURE_PARAMETER_SET_14
144931. DSCA_PICTURE_PARAMETER_SET_15
144932. DSCA_PICTURE_PARAMETER_SET_16
144933. DSCA_PICTURE_PARAMETER_SET_2
144934. DSCA_PICTURE_PARAMETER_SET_3
144935. DSCA_PICTURE_PARAMETER_SET_4
144936. DSCA_PICTURE_PARAMETER_SET_5
144937. DSCA_PICTURE_PARAMETER_SET_6
144938. DSCA_PICTURE_PARAMETER_SET_7
144939. DSCA_PICTURE_PARAMETER_SET_8
144940. DSCA_PICTURE_PARAMETER_SET_9
144941. DSCA_RC_BUF_THRESH_0
144942. DSCA_RC_BUF_THRESH_0_UDW
144943. DSCA_RC_BUF_THRESH_1
144944. DSCA_RC_BUF_THRESH_1_UDW
144945. DSCA_RC_RANGE_PARAMETERS_0
144946. DSCA_RC_RANGE_PARAMETERS_0_UDW
144947. DSCA_RC_RANGE_PARAMETERS_1
144948. DSCA_RC_RANGE_PARAMETERS_1_UDW
144949. DSCA_RC_RANGE_PARAMETERS_2
144950. DSCA_RC_RANGE_PARAMETERS_2_UDW
144951. DSCA_RC_RANGE_PARAMETERS_3
144952. DSCA_RC_RANGE_PARAMETERS_3_UDW
144953. DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK
144954. DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT
144955. DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK
144956. DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT
144957. DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK
144958. DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT
144959. DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK
144960. DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT
144961. DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK
144962. DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT
144963. DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK
144964. DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT
144965. DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK
144966. DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT
144967. DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK
144968. DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT
144969. DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK
144970. DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT
144971. DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK
144972. DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT
144973. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK
144974. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT
144975. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK
144976. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT
144977. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK
144978. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT
144979. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK
144980. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT
144981. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK
144982. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT
144983. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK
144984. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT
144985. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK
144986. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT
144987. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK
144988. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT
144989. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK
144990. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT
144991. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK
144992. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT
144993. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK
144994. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT
144995. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK
144996. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT
144997. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK
144998. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT
144999. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK
145000. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT
145001. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK
145002. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145003. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK
145004. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT
145005. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK
145006. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145007. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK
145008. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT
145009. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK
145010. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145011. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK
145012. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT
145013. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK
145014. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145015. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK
145016. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT
145017. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK
145018. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145019. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK
145020. DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT
145021. DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK
145022. DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT
145023. DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK
145024. DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT
145025. DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK
145026. DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT
145027. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK
145028. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT
145029. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK
145030. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT
145031. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK
145032. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT
145033. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK
145034. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT
145035. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK
145036. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT
145037. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK
145038. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT
145039. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK
145040. DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT
145041. DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK
145042. DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT
145043. DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK
145044. DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT
145045. DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK
145046. DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT
145047. DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK
145048. DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT
145049. DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK
145050. DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT
145051. DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK
145052. DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT
145053. DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK
145054. DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT
145055. DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK
145056. DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT
145057. DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK
145058. DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT
145059. DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK
145060. DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT
145061. DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK
145062. DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT
145063. DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK
145064. DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT
145065. DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK
145066. DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT
145067. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK
145068. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT
145069. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK
145070. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT
145071. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK
145072. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT
145073. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK
145074. DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT
145075. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK
145076. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT
145077. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK
145078. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT
145079. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK
145080. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT
145081. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK
145082. DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT
145083. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK
145084. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT
145085. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK
145086. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT
145087. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK
145088. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT
145089. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK
145090. DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT
145091. DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK
145092. DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT
145093. DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK
145094. DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT
145095. DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK
145096. DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT
145097. DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK
145098. DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT
145099. DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK
145100. DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT
145101. DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK
145102. DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT
145103. DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK
145104. DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT
145105. DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK
145106. DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT
145107. DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK
145108. DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT
145109. DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK
145110. DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT
145111. DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK
145112. DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT
145113. DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK
145114. DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT
145115. DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK
145116. DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT
145117. DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK
145118. DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT
145119. DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK
145120. DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT
145121. DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK
145122. DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT
145123. DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK
145124. DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT
145125. DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK
145126. DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT
145127. DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK
145128. DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT
145129. DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK
145130. DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT
145131. DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK
145132. DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT
145133. DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK
145134. DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT
145135. DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK
145136. DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT
145137. DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK
145138. DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT
145139. DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK
145140. DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT
145141. DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK
145142. DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT
145143. DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK
145144. DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT
145145. DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK
145146. DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT
145147. DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK
145148. DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT
145149. DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK
145150. DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT
145151. DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK
145152. DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT
145153. DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK
145154. DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT
145155. DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK
145156. DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT
145157. DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK
145158. DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT
145159. DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK
145160. DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT
145161. DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK
145162. DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT
145163. DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK
145164. DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT
145165. DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK
145166. DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT
145167. DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK
145168. DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT
145169. DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK
145170. DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT
145171. DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK
145172. DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT
145173. DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK
145174. DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT
145175. DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK
145176. DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT
145177. DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK
145178. DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT
145179. DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK
145180. DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT
145181. DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK
145182. DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT
145183. DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK
145184. DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT
145185. DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK
145186. DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT
145187. DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK
145188. DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT
145189. DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK
145190. DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT
145191. DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK
145192. DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT
145193. DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK
145194. DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT
145195. DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK
145196. DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT
145197. DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK
145198. DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT
145199. DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK
145200. DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT
145201. DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK
145202. DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT
145203. DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK
145204. DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT
145205. DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK
145206. DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT
145207. DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK
145208. DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT
145209. DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK
145210. DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT
145211. DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK
145212. DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT
145213. DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK
145214. DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT
145215. DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK
145216. DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT
145217. DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK
145218. DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT
145219. DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK
145220. DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT
145221. DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK
145222. DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT
145223. DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK
145224. DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT
145225. DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK
145226. DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT
145227. DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK
145228. DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT
145229. DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK
145230. DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT
145231. DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK
145232. DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT
145233. DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK
145234. DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT
145235. DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK
145236. DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
145237. DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK
145238. DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
145239. DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK
145240. DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
145241. DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK
145242. DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
145243. DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK
145244. DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
145245. DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK
145246. DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
145247. DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK
145248. DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
145249. DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK
145250. DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
145251. DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK
145252. DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT
145253. DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK
145254. DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT
145255. DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
145256. DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
145257. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK
145258. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT
145259. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK
145260. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT
145261. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK
145262. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT
145263. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK
145264. DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT
145265. DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK
145266. DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT
145267. DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK
145268. DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT
145269. DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK
145270. DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT
145271. DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK
145272. DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT
145273. DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK
145274. DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT
145275. DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK
145276. DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT
145277. DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK
145278. DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT
145279. DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK
145280. DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT
145281. DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK
145282. DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT
145283. DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK
145284. DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT
145285. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK
145286. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145287. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK
145288. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT
145289. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK
145290. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145291. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK
145292. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT
145293. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK
145294. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145295. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK
145296. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT
145297. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK
145298. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145299. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK
145300. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT
145301. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK
145302. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145303. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK
145304. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT
145305. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK
145306. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145307. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK
145308. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT
145309. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK
145310. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145311. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK
145312. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT
145313. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK
145314. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145315. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK
145316. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT
145317. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK
145318. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145319. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK
145320. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT
145321. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK
145322. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145323. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK
145324. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT
145325. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK
145326. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145327. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK
145328. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT
145329. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK
145330. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145331. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK
145332. DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT
145333. DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK
145334. DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT
145335. DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK
145336. DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT
145337. DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK
145338. DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT
145339. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK
145340. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT
145341. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK
145342. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT
145343. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK
145344. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT
145345. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK
145346. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT
145347. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK
145348. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT
145349. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK
145350. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT
145351. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK
145352. DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT
145353. DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK
145354. DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT
145355. DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK
145356. DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT
145357. DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK
145358. DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT
145359. DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK
145360. DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT
145361. DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK
145362. DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT
145363. DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK
145364. DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT
145365. DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK
145366. DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT
145367. DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK
145368. DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT
145369. DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK
145370. DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT
145371. DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK
145372. DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT
145373. DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK
145374. DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT
145375. DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK
145376. DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT
145377. DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK
145378. DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT
145379. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK
145380. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT
145381. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK
145382. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT
145383. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK
145384. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT
145385. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK
145386. DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT
145387. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK
145388. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT
145389. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK
145390. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT
145391. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK
145392. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT
145393. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK
145394. DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT
145395. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK
145396. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT
145397. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK
145398. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT
145399. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK
145400. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT
145401. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK
145402. DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT
145403. DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK
145404. DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT
145405. DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK
145406. DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT
145407. DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK
145408. DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT
145409. DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK
145410. DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT
145411. DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK
145412. DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT
145413. DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK
145414. DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT
145415. DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK
145416. DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT
145417. DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK
145418. DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT
145419. DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK
145420. DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT
145421. DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK
145422. DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT
145423. DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK
145424. DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT
145425. DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK
145426. DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT
145427. DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK
145428. DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT
145429. DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK
145430. DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT
145431. DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK
145432. DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT
145433. DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK
145434. DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT
145435. DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK
145436. DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT
145437. DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK
145438. DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT
145439. DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK
145440. DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT
145441. DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK
145442. DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT
145443. DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK
145444. DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT
145445. DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK
145446. DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT
145447. DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK
145448. DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT
145449. DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK
145450. DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT
145451. DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK
145452. DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT
145453. DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK
145454. DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT
145455. DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK
145456. DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT
145457. DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK
145458. DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT
145459. DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK
145460. DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT
145461. DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK
145462. DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT
145463. DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK
145464. DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT
145465. DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK
145466. DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT
145467. DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK
145468. DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT
145469. DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK
145470. DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT
145471. DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK
145472. DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT
145473. DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK
145474. DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT
145475. DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK
145476. DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT
145477. DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK
145478. DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT
145479. DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK
145480. DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT
145481. DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK
145482. DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT
145483. DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK
145484. DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT
145485. DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK
145486. DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT
145487. DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK
145488. DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT
145489. DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK
145490. DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT
145491. DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK
145492. DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT
145493. DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK
145494. DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT
145495. DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK
145496. DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT
145497. DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK
145498. DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT
145499. DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK
145500. DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT
145501. DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK
145502. DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT
145503. DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK
145504. DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT
145505. DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK
145506. DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT
145507. DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK
145508. DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT
145509. DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK
145510. DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT
145511. DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK
145512. DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT
145513. DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK
145514. DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT
145515. DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK
145516. DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT
145517. DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK
145518. DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT
145519. DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK
145520. DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT
145521. DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK
145522. DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT
145523. DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK
145524. DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT
145525. DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK
145526. DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT
145527. DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK
145528. DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT
145529. DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK
145530. DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT
145531. DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK
145532. DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT
145533. DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK
145534. DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT
145535. DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK
145536. DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT
145537. DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK
145538. DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT
145539. DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK
145540. DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT
145541. DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK
145542. DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT
145543. DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK
145544. DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT
145545. DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK
145546. DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT
145547. DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK
145548. DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
145549. DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK
145550. DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
145551. DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK
145552. DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
145553. DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK
145554. DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
145555. DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK
145556. DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
145557. DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK
145558. DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
145559. DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK
145560. DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
145561. DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK
145562. DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
145563. DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK
145564. DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT
145565. DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK
145566. DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT
145567. DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
145568. DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
145569. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK
145570. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT
145571. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK
145572. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT
145573. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK
145574. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT
145575. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK
145576. DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT
145577. DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK
145578. DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT
145579. DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK
145580. DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT
145581. DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK
145582. DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT
145583. DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK
145584. DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT
145585. DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK
145586. DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT
145587. DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK
145588. DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT
145589. DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK
145590. DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT
145591. DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK
145592. DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT
145593. DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK
145594. DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT
145595. DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK
145596. DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT
145597. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK
145598. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145599. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK
145600. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT
145601. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK
145602. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145603. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK
145604. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT
145605. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK
145606. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145607. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK
145608. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT
145609. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK
145610. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145611. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK
145612. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT
145613. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK
145614. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145615. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK
145616. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT
145617. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK
145618. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145619. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK
145620. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT
145621. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK
145622. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145623. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK
145624. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT
145625. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK
145626. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145627. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK
145628. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT
145629. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK
145630. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145631. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK
145632. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT
145633. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK
145634. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145635. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK
145636. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT
145637. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK
145638. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145639. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK
145640. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT
145641. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK
145642. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145643. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK
145644. DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT
145645. DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK
145646. DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT
145647. DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK
145648. DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT
145649. DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK
145650. DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT
145651. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK
145652. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT
145653. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK
145654. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT
145655. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK
145656. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT
145657. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK
145658. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT
145659. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK
145660. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT
145661. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK
145662. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT
145663. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK
145664. DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT
145665. DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK
145666. DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT
145667. DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK
145668. DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT
145669. DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK
145670. DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT
145671. DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK
145672. DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT
145673. DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK
145674. DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT
145675. DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK
145676. DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT
145677. DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK
145678. DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT
145679. DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK
145680. DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT
145681. DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK
145682. DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT
145683. DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK
145684. DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT
145685. DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK
145686. DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT
145687. DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK
145688. DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT
145689. DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK
145690. DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT
145691. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK
145692. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT
145693. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK
145694. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT
145695. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK
145696. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT
145697. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK
145698. DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT
145699. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK
145700. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT
145701. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK
145702. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT
145703. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK
145704. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT
145705. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK
145706. DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT
145707. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK
145708. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT
145709. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK
145710. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT
145711. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK
145712. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT
145713. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK
145714. DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT
145715. DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK
145716. DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT
145717. DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK
145718. DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT
145719. DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK
145720. DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT
145721. DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK
145722. DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT
145723. DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK
145724. DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT
145725. DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK
145726. DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT
145727. DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK
145728. DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT
145729. DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK
145730. DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT
145731. DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK
145732. DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT
145733. DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK
145734. DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT
145735. DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK
145736. DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT
145737. DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK
145738. DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT
145739. DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK
145740. DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT
145741. DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK
145742. DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT
145743. DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK
145744. DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT
145745. DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK
145746. DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT
145747. DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK
145748. DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT
145749. DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK
145750. DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT
145751. DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK
145752. DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT
145753. DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK
145754. DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT
145755. DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK
145756. DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT
145757. DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK
145758. DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT
145759. DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK
145760. DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT
145761. DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK
145762. DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT
145763. DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK
145764. DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT
145765. DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK
145766. DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT
145767. DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK
145768. DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT
145769. DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK
145770. DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT
145771. DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK
145772. DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT
145773. DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK
145774. DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT
145775. DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK
145776. DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT
145777. DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK
145778. DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT
145779. DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK
145780. DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT
145781. DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK
145782. DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT
145783. DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK
145784. DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT
145785. DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK
145786. DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT
145787. DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK
145788. DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT
145789. DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK
145790. DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT
145791. DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK
145792. DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT
145793. DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK
145794. DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT
145795. DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK
145796. DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT
145797. DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK
145798. DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT
145799. DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK
145800. DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT
145801. DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK
145802. DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT
145803. DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK
145804. DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT
145805. DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK
145806. DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT
145807. DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK
145808. DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT
145809. DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK
145810. DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT
145811. DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK
145812. DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT
145813. DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK
145814. DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT
145815. DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK
145816. DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT
145817. DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK
145818. DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT
145819. DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK
145820. DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT
145821. DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK
145822. DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT
145823. DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK
145824. DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT
145825. DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK
145826. DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT
145827. DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK
145828. DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT
145829. DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK
145830. DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT
145831. DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK
145832. DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT
145833. DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK
145834. DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT
145835. DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK
145836. DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT
145837. DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK
145838. DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT
145839. DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK
145840. DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT
145841. DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK
145842. DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT
145843. DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK
145844. DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT
145845. DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK
145846. DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT
145847. DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK
145848. DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT
145849. DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK
145850. DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT
145851. DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK
145852. DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT
145853. DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK
145854. DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT
145855. DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK
145856. DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT
145857. DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK
145858. DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT
145859. DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK
145860. DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
145861. DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK
145862. DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
145863. DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK
145864. DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
145865. DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK
145866. DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
145867. DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK
145868. DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
145869. DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK
145870. DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
145871. DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK
145872. DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
145873. DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK
145874. DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
145875. DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK
145876. DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT
145877. DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK
145878. DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT
145879. DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
145880. DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
145881. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK
145882. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT
145883. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK
145884. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT
145885. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK
145886. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT
145887. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK
145888. DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT
145889. DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK
145890. DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT
145891. DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK
145892. DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT
145893. DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK
145894. DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT
145895. DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK
145896. DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT
145897. DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK
145898. DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT
145899. DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK
145900. DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT
145901. DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK
145902. DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT
145903. DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK
145904. DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT
145905. DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK
145906. DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT
145907. DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK
145908. DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT
145909. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK
145910. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145911. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK
145912. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT
145913. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK
145914. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145915. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK
145916. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT
145917. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK
145918. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145919. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK
145920. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT
145921. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK
145922. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145923. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK
145924. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT
145925. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK
145926. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145927. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK
145928. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT
145929. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK
145930. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145931. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK
145932. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT
145933. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK
145934. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145935. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK
145936. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT
145937. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK
145938. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT
145939. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK
145940. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT
145941. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK
145942. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT
145943. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK
145944. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT
145945. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK
145946. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT
145947. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK
145948. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT
145949. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK
145950. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT
145951. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK
145952. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT
145953. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK
145954. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT
145955. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK
145956. DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT
145957. DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK
145958. DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT
145959. DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK
145960. DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT
145961. DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK
145962. DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT
145963. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK
145964. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT
145965. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK
145966. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT
145967. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK
145968. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT
145969. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK
145970. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT
145971. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK
145972. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT
145973. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK
145974. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT
145975. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK
145976. DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT
145977. DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK
145978. DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT
145979. DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK
145980. DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT
145981. DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK
145982. DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT
145983. DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK
145984. DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT
145985. DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK
145986. DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT
145987. DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK
145988. DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT
145989. DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK
145990. DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT
145991. DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK
145992. DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT
145993. DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK
145994. DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT
145995. DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK
145996. DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT
145997. DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK
145998. DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT
145999. DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK
146000. DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT
146001. DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK
146002. DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT
146003. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK
146004. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT
146005. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK
146006. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT
146007. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK
146008. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT
146009. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK
146010. DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT
146011. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK
146012. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT
146013. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK
146014. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT
146015. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK
146016. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT
146017. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK
146018. DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT
146019. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK
146020. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT
146021. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK
146022. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT
146023. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK
146024. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT
146025. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK
146026. DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT
146027. DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK
146028. DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT
146029. DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK
146030. DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT
146031. DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK
146032. DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT
146033. DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK
146034. DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT
146035. DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK
146036. DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT
146037. DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK
146038. DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT
146039. DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK
146040. DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT
146041. DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK
146042. DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT
146043. DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK
146044. DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT
146045. DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK
146046. DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT
146047. DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK
146048. DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT
146049. DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK
146050. DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT
146051. DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK
146052. DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT
146053. DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK
146054. DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT
146055. DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK
146056. DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT
146057. DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK
146058. DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT
146059. DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK
146060. DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT
146061. DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK
146062. DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT
146063. DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK
146064. DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT
146065. DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK
146066. DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT
146067. DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK
146068. DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT
146069. DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK
146070. DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT
146071. DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK
146072. DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT
146073. DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK
146074. DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT
146075. DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK
146076. DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT
146077. DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK
146078. DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT
146079. DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK
146080. DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT
146081. DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK
146082. DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT
146083. DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK
146084. DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT
146085. DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK
146086. DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT
146087. DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK
146088. DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT
146089. DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK
146090. DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT
146091. DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK
146092. DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT
146093. DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK
146094. DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT
146095. DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK
146096. DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT
146097. DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK
146098. DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT
146099. DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK
146100. DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT
146101. DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK
146102. DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT
146103. DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK
146104. DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT
146105. DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK
146106. DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT
146107. DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK
146108. DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT
146109. DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK
146110. DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT
146111. DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK
146112. DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT
146113. DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK
146114. DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT
146115. DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK
146116. DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT
146117. DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK
146118. DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT
146119. DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK
146120. DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT
146121. DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK
146122. DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT
146123. DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK
146124. DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT
146125. DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK
146126. DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT
146127. DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK
146128. DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT
146129. DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK
146130. DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT
146131. DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK
146132. DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT
146133. DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK
146134. DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT
146135. DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK
146136. DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT
146137. DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK
146138. DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT
146139. DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK
146140. DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT
146141. DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK
146142. DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT
146143. DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK
146144. DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT
146145. DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK
146146. DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT
146147. DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK
146148. DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT
146149. DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK
146150. DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT
146151. DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK
146152. DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT
146153. DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK
146154. DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT
146155. DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK
146156. DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT
146157. DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK
146158. DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT
146159. DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK
146160. DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT
146161. DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK
146162. DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT
146163. DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK
146164. DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT
146165. DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK
146166. DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT
146167. DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK
146168. DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT
146169. DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK
146170. DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT
146171. DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK
146172. DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
146173. DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK
146174. DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
146175. DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK
146176. DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
146177. DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK
146178. DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
146179. DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK
146180. DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
146181. DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK
146182. DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
146183. DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK
146184. DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
146185. DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK
146186. DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
146187. DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK
146188. DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT
146189. DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK
146190. DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT
146191. DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146192. DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146193. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK
146194. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT
146195. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK
146196. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT
146197. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK
146198. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT
146199. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK
146200. DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT
146201. DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK
146202. DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT
146203. DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK
146204. DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT
146205. DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK
146206. DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT
146207. DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK
146208. DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT
146209. DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK
146210. DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT
146211. DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK
146212. DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT
146213. DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK
146214. DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT
146215. DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK
146216. DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT
146217. DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK
146218. DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT
146219. DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK
146220. DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT
146221. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK
146222. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT
146223. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK
146224. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT
146225. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK
146226. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146227. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK
146228. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT
146229. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK
146230. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT
146231. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK
146232. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT
146233. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK
146234. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146235. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK
146236. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT
146237. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK
146238. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT
146239. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK
146240. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT
146241. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK
146242. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146243. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK
146244. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT
146245. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK
146246. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT
146247. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK
146248. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT
146249. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK
146250. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146251. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK
146252. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT
146253. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK
146254. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT
146255. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK
146256. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT
146257. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK
146258. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT
146259. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK
146260. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT
146261. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK
146262. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT
146263. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK
146264. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT
146265. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK
146266. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT
146267. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK
146268. DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT
146269. DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK
146270. DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT
146271. DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK
146272. DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT
146273. DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK
146274. DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT
146275. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK
146276. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT
146277. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK
146278. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT
146279. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK
146280. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT
146281. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK
146282. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT
146283. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK
146284. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT
146285. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK
146286. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT
146287. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK
146288. DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT
146289. DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK
146290. DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT
146291. DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK
146292. DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT
146293. DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK
146294. DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT
146295. DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK
146296. DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT
146297. DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK
146298. DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT
146299. DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK
146300. DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT
146301. DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK
146302. DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT
146303. DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK
146304. DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT
146305. DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK
146306. DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT
146307. DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK
146308. DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT
146309. DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK
146310. DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT
146311. DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK
146312. DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT
146313. DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK
146314. DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT
146315. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK
146316. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT
146317. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK
146318. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT
146319. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK
146320. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT
146321. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK
146322. DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT
146323. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK
146324. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT
146325. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK
146326. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT
146327. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK
146328. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT
146329. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK
146330. DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT
146331. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK
146332. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT
146333. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK
146334. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT
146335. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK
146336. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT
146337. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK
146338. DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT
146339. DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK
146340. DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT
146341. DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK
146342. DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT
146343. DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK
146344. DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT
146345. DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK
146346. DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT
146347. DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK
146348. DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT
146349. DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK
146350. DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT
146351. DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK
146352. DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT
146353. DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK
146354. DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT
146355. DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK
146356. DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT
146357. DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK
146358. DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT
146359. DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK
146360. DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT
146361. DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK
146362. DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT
146363. DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK
146364. DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT
146365. DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK
146366. DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT
146367. DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK
146368. DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT
146369. DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK
146370. DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT
146371. DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK
146372. DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT
146373. DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK
146374. DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT
146375. DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK
146376. DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT
146377. DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK
146378. DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT
146379. DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK
146380. DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT
146381. DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK
146382. DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT
146383. DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK
146384. DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT
146385. DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK
146386. DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT
146387. DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK
146388. DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT
146389. DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK
146390. DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT
146391. DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK
146392. DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT
146393. DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK
146394. DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT
146395. DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK
146396. DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT
146397. DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK
146398. DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT
146399. DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK
146400. DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT
146401. DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK
146402. DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT
146403. DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK
146404. DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT
146405. DSCC4_DSCC_PPS_CONFIG1__NATIVE_420_MASK
146406. DSCC4_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT
146407. DSCC4_DSCC_PPS_CONFIG1__NATIVE_422_MASK
146408. DSCC4_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT
146409. DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422_MASK
146410. DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT
146411. DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK
146412. DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT
146413. DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK
146414. DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT
146415. DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK
146416. DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT
146417. DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK
146418. DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT
146419. DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK
146420. DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT
146421. DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK
146422. DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT
146423. DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK
146424. DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT
146425. DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK
146426. DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT
146427. DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK
146428. DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT
146429. DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK
146430. DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT
146431. DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK
146432. DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT
146433. DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK
146434. DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT
146435. DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK
146436. DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT
146437. DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK
146438. DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT
146439. DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK
146440. DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT
146441. DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK
146442. DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT
146443. DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK
146444. DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT
146445. DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK
146446. DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT
146447. DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK
146448. DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT
146449. DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK
146450. DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT
146451. DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK
146452. DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT
146453. DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK
146454. DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT
146455. DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK
146456. DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT
146457. DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK
146458. DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT
146459. DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK
146460. DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT
146461. DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK
146462. DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT
146463. DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK
146464. DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT
146465. DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK
146466. DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT
146467. DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK
146468. DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT
146469. DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK
146470. DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT
146471. DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK
146472. DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT
146473. DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK
146474. DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT
146475. DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK
146476. DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT
146477. DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK
146478. DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT
146479. DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK
146480. DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT
146481. DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK
146482. DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT
146483. DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK
146484. DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
146485. DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK
146486. DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
146487. DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK
146488. DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
146489. DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK
146490. DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
146491. DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK
146492. DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
146493. DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK
146494. DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
146495. DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK
146496. DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
146497. DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK
146498. DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
146499. DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK
146500. DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT
146501. DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK
146502. DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT
146503. DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146504. DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146505. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK
146506. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT
146507. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK
146508. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT
146509. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK
146510. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT
146511. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK
146512. DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT
146513. DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK
146514. DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT
146515. DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK
146516. DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT
146517. DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK
146518. DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT
146519. DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK
146520. DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT
146521. DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK
146522. DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT
146523. DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK
146524. DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT
146525. DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK
146526. DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT
146527. DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK
146528. DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT
146529. DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK
146530. DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT
146531. DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK
146532. DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT
146533. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK
146534. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT
146535. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK
146536. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT
146537. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK
146538. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146539. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK
146540. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT
146541. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK
146542. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT
146543. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK
146544. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT
146545. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK
146546. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146547. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK
146548. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT
146549. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK
146550. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT
146551. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK
146552. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT
146553. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK
146554. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146555. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK
146556. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT
146557. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK
146558. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT
146559. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK
146560. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT
146561. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK
146562. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146563. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK
146564. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT
146565. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK
146566. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT
146567. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK
146568. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT
146569. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK
146570. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT
146571. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK
146572. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT
146573. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK
146574. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT
146575. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK
146576. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT
146577. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK
146578. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT
146579. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK
146580. DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT
146581. DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK
146582. DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT
146583. DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK
146584. DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT
146585. DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK
146586. DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT
146587. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK
146588. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT
146589. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK
146590. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT
146591. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK
146592. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT
146593. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK
146594. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT
146595. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK
146596. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT
146597. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK
146598. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT
146599. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK
146600. DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT
146601. DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK
146602. DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT
146603. DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK
146604. DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT
146605. DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK
146606. DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT
146607. DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK
146608. DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT
146609. DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK
146610. DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT
146611. DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK
146612. DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT
146613. DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK
146614. DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT
146615. DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK
146616. DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT
146617. DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK
146618. DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT
146619. DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK
146620. DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT
146621. DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK
146622. DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT
146623. DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK
146624. DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT
146625. DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK
146626. DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT
146627. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK
146628. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT
146629. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK
146630. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT
146631. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK
146632. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT
146633. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK
146634. DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT
146635. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK
146636. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT
146637. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK
146638. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT
146639. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK
146640. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT
146641. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK
146642. DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT
146643. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK
146644. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT
146645. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK
146646. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT
146647. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK
146648. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT
146649. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK
146650. DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT
146651. DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK
146652. DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT
146653. DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK
146654. DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT
146655. DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK
146656. DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT
146657. DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK
146658. DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT
146659. DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK
146660. DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT
146661. DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK
146662. DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT
146663. DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK
146664. DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT
146665. DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK
146666. DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT
146667. DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK
146668. DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT
146669. DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK
146670. DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT
146671. DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK
146672. DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT
146673. DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK
146674. DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT
146675. DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK
146676. DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT
146677. DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK
146678. DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT
146679. DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK
146680. DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT
146681. DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK
146682. DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT
146683. DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK
146684. DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT
146685. DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK
146686. DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT
146687. DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK
146688. DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT
146689. DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK
146690. DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT
146691. DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK
146692. DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT
146693. DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK
146694. DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT
146695. DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK
146696. DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT
146697. DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK
146698. DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT
146699. DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK
146700. DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT
146701. DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK
146702. DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT
146703. DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK
146704. DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT
146705. DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK
146706. DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT
146707. DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK
146708. DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT
146709. DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK
146710. DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT
146711. DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK
146712. DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT
146713. DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK
146714. DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT
146715. DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK
146716. DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT
146717. DSCC5_DSCC_PPS_CONFIG1__NATIVE_420_MASK
146718. DSCC5_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT
146719. DSCC5_DSCC_PPS_CONFIG1__NATIVE_422_MASK
146720. DSCC5_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT
146721. DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422_MASK
146722. DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT
146723. DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK
146724. DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT
146725. DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK
146726. DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT
146727. DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK
146728. DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT
146729. DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK
146730. DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT
146731. DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK
146732. DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT
146733. DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK
146734. DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT
146735. DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK
146736. DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT
146737. DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK
146738. DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT
146739. DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK
146740. DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT
146741. DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK
146742. DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT
146743. DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK
146744. DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT
146745. DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK
146746. DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT
146747. DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK
146748. DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT
146749. DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK
146750. DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT
146751. DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK
146752. DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT
146753. DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK
146754. DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT
146755. DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK
146756. DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT
146757. DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK
146758. DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT
146759. DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK
146760. DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT
146761. DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK
146762. DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT
146763. DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK
146764. DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT
146765. DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK
146766. DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT
146767. DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK
146768. DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT
146769. DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK
146770. DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT
146771. DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK
146772. DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT
146773. DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK
146774. DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT
146775. DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK
146776. DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT
146777. DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK
146778. DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT
146779. DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK
146780. DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT
146781. DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK
146782. DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT
146783. DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK
146784. DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT
146785. DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK
146786. DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT
146787. DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK
146788. DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT
146789. DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK
146790. DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT
146791. DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK
146792. DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT
146793. DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK
146794. DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT
146795. DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK
146796. DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
146797. DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK
146798. DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
146799. DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK
146800. DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
146801. DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK
146802. DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
146803. DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK
146804. DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT
146805. DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK
146806. DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT
146807. DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK
146808. DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT
146809. DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK
146810. DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT
146811. DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK
146812. DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT
146813. DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK
146814. DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT
146815. DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146816. DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146817. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK
146818. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT
146819. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK
146820. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT
146821. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK
146822. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT
146823. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK
146824. DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT
146825. DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK
146826. DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT
146827. DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146828. DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146829. DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK
146830. DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146831. DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK
146832. DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT
146833. DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK
146834. DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT
146835. DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK
146836. DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT
146837. DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK
146838. DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT
146839. DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK
146840. DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT
146841. DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK
146842. DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT
146843. DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146844. DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146845. DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK
146846. DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146847. DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK
146848. DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT
146849. DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK
146850. DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT
146851. DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK
146852. DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT
146853. DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK
146854. DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT
146855. DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK
146856. DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT
146857. DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK
146858. DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT
146859. DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146860. DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146861. DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK
146862. DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146863. DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK
146864. DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT
146865. DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK
146866. DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT
146867. DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK
146868. DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT
146869. DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK
146870. DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT
146871. DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK
146872. DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT
146873. DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK
146874. DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT
146875. DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146876. DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146877. DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK
146878. DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146879. DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK
146880. DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT
146881. DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK
146882. DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT
146883. DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK
146884. DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT
146885. DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK
146886. DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT
146887. DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK
146888. DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT
146889. DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK
146890. DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT
146891. DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146892. DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146893. DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK
146894. DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146895. DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK
146896. DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT
146897. DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK
146898. DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT
146899. DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK
146900. DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT
146901. DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT_MASK
146902. DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT
146903. DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH_MASK
146904. DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT
146905. DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK
146906. DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT
146907. DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
146908. DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
146909. DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK
146910. DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT
146911. DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK
146912. DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT
146913. DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK
146914. DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT
146915. DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK
146916. DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT
146917. DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT_MASK
146918. DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT
146919. DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH_MASK
146920. DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT
146921. DSCCIF_BITS_PER_COMPONENT_ENUM
146922. DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT
146923. DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT
146924. DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT
146925. DSCCIF_ENABLE_ENUM
146926. DSCCIF_ENABLE_ENUM_DISABLED
146927. DSCCIF_ENABLE_ENUM_ENABLED
146928. DSCCIF_INPUT_PIXEL_FORMAT_ENUM
146929. DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420
146930. DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422
146931. DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB
146932. DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422
146933. DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444
146934. DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK
146935. DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT
146936. DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK
146937. DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT
146938. DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK
146939. DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT
146940. DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK
146941. DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT
146942. DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK
146943. DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT
146944. DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK
146945. DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT
146946. DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK
146947. DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT
146948. DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK
146949. DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT
146950. DSCCLK4_DTO_PARAM__DSCCLK4_DTO_MODULO_MASK
146951. DSCCLK4_DTO_PARAM__DSCCLK4_DTO_MODULO__SHIFT
146952. DSCCLK4_DTO_PARAM__DSCCLK4_DTO_PHASE_MASK
146953. DSCCLK4_DTO_PARAM__DSCCLK4_DTO_PHASE__SHIFT
146954. DSCCLK5_DTO_PARAM__DSCCLK5_DTO_MODULO_MASK
146955. DSCCLK5_DTO_PARAM__DSCCLK5_DTO_MODULO__SHIFT
146956. DSCCLK5_DTO_PARAM__DSCCLK5_DTO_PHASE_MASK
146957. DSCCLK5_DTO_PARAM__DSCCLK5_DTO_PHASE__SHIFT
146958. DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK
146959. DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT
146960. DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK
146961. DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT
146962. DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK
146963. DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT
146964. DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK
146965. DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT
146966. DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK
146967. DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT
146968. DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK
146969. DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT
146970. DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK
146971. DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT
146972. DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK
146973. DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT
146974. DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK
146975. DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT
146976. DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK
146977. DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT
146978. DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK
146979. DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT
146980. DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK
146981. DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT
146982. DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN_MASK
146983. DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN__SHIFT
146984. DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE_MASK
146985. DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE__SHIFT
146986. DSCC_BITS_PER_COMPONENT_ENUM
146987. DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT
146988. DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT
146989. DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT
146990. DSCC_DSC_VERSION_MAJOR_ENUM
146991. DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION
146992. DSCC_DSC_VERSION_MINOR_ENUM
146993. DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION
146994. DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION
146995. DSCC_ENABLE_ENUM
146996. DSCC_ENABLE_ENUM_DISABLED
146997. DSCC_ENABLE_ENUM_ENABLED
146998. DSCC_ICH_RESET_ENUM
146999. DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET
147000. DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET
147001. DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET
147002. DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET
147003. DSCC_LINEBUF_DEPTH_ENUM
147004. DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT
147005. DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT
147006. DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT
147007. DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT
147008. DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT
147009. DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT
147010. DSCC_MEM_PWR_DIS_ENUM
147011. DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS
147012. DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN
147013. DSCC_MEM_PWR_FORCE_ENUM
147014. DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST
147015. DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST
147016. DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST
147017. DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST
147018. DSCC_PICTURE_PARAMETER_SET_0
147019. DSCC_PICTURE_PARAMETER_SET_1
147020. DSCC_PICTURE_PARAMETER_SET_10
147021. DSCC_PICTURE_PARAMETER_SET_11
147022. DSCC_PICTURE_PARAMETER_SET_12
147023. DSCC_PICTURE_PARAMETER_SET_13
147024. DSCC_PICTURE_PARAMETER_SET_14
147025. DSCC_PICTURE_PARAMETER_SET_15
147026. DSCC_PICTURE_PARAMETER_SET_16
147027. DSCC_PICTURE_PARAMETER_SET_2
147028. DSCC_PICTURE_PARAMETER_SET_3
147029. DSCC_PICTURE_PARAMETER_SET_4
147030. DSCC_PICTURE_PARAMETER_SET_5
147031. DSCC_PICTURE_PARAMETER_SET_6
147032. DSCC_PICTURE_PARAMETER_SET_7
147033. DSCC_PICTURE_PARAMETER_SET_8
147034. DSCC_PICTURE_PARAMETER_SET_9
147035. DSCC_RC_BUF_THRESH_0
147036. DSCC_RC_BUF_THRESH_0_UDW
147037. DSCC_RC_BUF_THRESH_1
147038. DSCC_RC_BUF_THRESH_1_UDW
147039. DSCC_RC_RANGE_PARAMETERS_0
147040. DSCC_RC_RANGE_PARAMETERS_0_UDW
147041. DSCC_RC_RANGE_PARAMETERS_1
147042. DSCC_RC_RANGE_PARAMETERS_1_UDW
147043. DSCC_RC_RANGE_PARAMETERS_2
147044. DSCC_RC_RANGE_PARAMETERS_2_UDW
147045. DSCC_RC_RANGE_PARAMETERS_3
147046. DSCC_RC_RANGE_PARAMETERS_3_UDW
147047. DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK
147048. DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT
147049. DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK
147050. DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT
147051. DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK
147052. DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT
147053. DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK
147054. DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT
147055. DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK
147056. DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT
147057. DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK
147058. DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT
147059. DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK
147060. DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT
147061. DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK
147062. DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT
147063. DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK
147064. DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT
147065. DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK
147066. DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT
147067. DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK
147068. DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT
147069. DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK
147070. DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT
147071. DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK
147072. DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT
147073. DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK
147074. DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT
147075. DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK
147076. DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT
147077. DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK
147078. DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT
147079. DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK
147080. DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT
147081. DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK
147082. DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT
147083. DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK
147084. DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT
147085. DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK
147086. DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT
147087. DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK
147088. DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT
147089. DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK
147090. DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT
147091. DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK
147092. DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT
147093. DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK
147094. DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT
147095. DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK
147096. DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT
147097. DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK
147098. DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT
147099. DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK
147100. DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT
147101. DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK
147102. DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT
147103. DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK
147104. DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT
147105. DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK
147106. DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT
147107. DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK
147108. DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT
147109. DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK
147110. DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT
147111. DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK
147112. DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT
147113. DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK
147114. DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT
147115. DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK
147116. DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT
147117. DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK
147118. DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT
147119. DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK
147120. DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT
147121. DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK
147122. DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT
147123. DSCL0_LB_DATA_FORMAT__DITHER_EN_MASK
147124. DSCL0_LB_DATA_FORMAT__DITHER_EN__SHIFT
147125. DSCL0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK
147126. DSCL0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT
147127. DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK
147128. DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
147129. DSCL0_LB_DATA_FORMAT__PIXEL_DEPTH_MASK
147130. DSCL0_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT
147131. DSCL0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK
147132. DSCL0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT
147133. DSCL0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK
147134. DSCL0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT
147135. DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK
147136. DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT
147137. DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK
147138. DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT
147139. DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK
147140. DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT
147141. DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK
147142. DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT
147143. DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK
147144. DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT
147145. DSCL0_LB_V_COUNTER__V_COUNTER_MASK
147146. DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT
147147. DSCL0_MPC_SIZE__MPC_HEIGHT_MASK
147148. DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT
147149. DSCL0_MPC_SIZE__MPC_WIDTH_MASK
147150. DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT
147151. DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK
147152. DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT
147153. DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK
147154. DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT
147155. DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK
147156. DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT
147157. DSCL0_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK
147158. DSCL0_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT
147159. DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK
147160. DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT
147161. DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK
147162. DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT
147163. DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK
147164. DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT
147165. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK
147166. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT
147167. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK
147168. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT
147169. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK
147170. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT
147171. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK
147172. DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT
147173. DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK
147174. DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT
147175. DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK
147176. DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT
147177. DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK
147178. DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT
147179. DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK
147180. DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT
147181. DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK
147182. DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT
147183. DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK
147184. DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT
147185. DSCL0_RECOUT_START__RECOUT_START_X_MASK
147186. DSCL0_RECOUT_START__RECOUT_START_X__SHIFT
147187. DSCL0_RECOUT_START__RECOUT_START_Y_MASK
147188. DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT
147189. DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK
147190. DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT
147191. DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK
147192. DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT
147193. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK
147194. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT
147195. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK
147196. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT
147197. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK
147198. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT
147199. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK
147200. DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT
147201. DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK
147202. DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT
147203. DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK
147204. DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT
147205. DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK
147206. DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT
147207. DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK
147208. DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT
147209. DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK
147210. DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT
147211. DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK
147212. DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT
147213. DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK
147214. DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT
147215. DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK
147216. DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT
147217. DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK
147218. DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT
147219. DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK
147220. DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT
147221. DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK
147222. DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT
147223. DSCL0_SCL_MODE__DSCL_MODE_MASK
147224. DSCL0_SCL_MODE__DSCL_MODE__SHIFT
147225. DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK
147226. DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT
147227. DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK
147228. DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT
147229. DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK
147230. DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT
147231. DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK
147232. DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK
147233. DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT
147234. DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT
147235. DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK
147236. DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT
147237. DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK
147238. DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT
147239. DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK
147240. DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT
147241. DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK
147242. DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT
147243. DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK
147244. DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT
147245. DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK
147246. DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT
147247. DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK
147248. DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT
147249. DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK
147250. DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT
147251. DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK
147252. DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT
147253. DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK
147254. DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT
147255. DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK
147256. DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT
147257. DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK
147258. DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT
147259. DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK
147260. DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT
147261. DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK
147262. DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT
147263. DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK
147264. DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT
147265. DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK
147266. DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT
147267. DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK
147268. DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT
147269. DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK
147270. DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT
147271. DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK
147272. DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT
147273. DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK
147274. DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT
147275. DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK
147276. DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT
147277. DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK
147278. DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT
147279. DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK
147280. DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT
147281. DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK
147282. DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT
147283. DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK
147284. DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT
147285. DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK
147286. DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT
147287. DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK
147288. DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT
147289. DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK
147290. DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT
147291. DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK
147292. DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT
147293. DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK
147294. DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT
147295. DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK
147296. DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT
147297. DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK
147298. DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT
147299. DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK
147300. DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT
147301. DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK
147302. DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT
147303. DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK
147304. DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT
147305. DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK
147306. DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT
147307. DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK
147308. DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT
147309. DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK
147310. DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT
147311. DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK
147312. DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT
147313. DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK
147314. DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT
147315. DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK
147316. DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT
147317. DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK
147318. DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT
147319. DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK
147320. DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT
147321. DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK
147322. DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT
147323. DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK
147324. DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT
147325. DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK
147326. DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT
147327. DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK
147328. DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT
147329. DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK
147330. DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT
147331. DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK
147332. DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT
147333. DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK
147334. DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT
147335. DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK
147336. DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT
147337. DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK
147338. DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT
147339. DSCL1_LB_DATA_FORMAT__DITHER_EN_MASK
147340. DSCL1_LB_DATA_FORMAT__DITHER_EN__SHIFT
147341. DSCL1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK
147342. DSCL1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT
147343. DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK
147344. DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
147345. DSCL1_LB_DATA_FORMAT__PIXEL_DEPTH_MASK
147346. DSCL1_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT
147347. DSCL1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK
147348. DSCL1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT
147349. DSCL1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK
147350. DSCL1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT
147351. DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK
147352. DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT
147353. DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK
147354. DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT
147355. DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK
147356. DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT
147357. DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK
147358. DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT
147359. DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK
147360. DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT
147361. DSCL1_LB_V_COUNTER__V_COUNTER_MASK
147362. DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT
147363. DSCL1_MPC_SIZE__MPC_HEIGHT_MASK
147364. DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT
147365. DSCL1_MPC_SIZE__MPC_WIDTH_MASK
147366. DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT
147367. DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK
147368. DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT
147369. DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK
147370. DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT
147371. DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK
147372. DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT
147373. DSCL1_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK
147374. DSCL1_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT
147375. DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK
147376. DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT
147377. DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK
147378. DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT
147379. DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK
147380. DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT
147381. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK
147382. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT
147383. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK
147384. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT
147385. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK
147386. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT
147387. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK
147388. DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT
147389. DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK
147390. DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT
147391. DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK
147392. DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT
147393. DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK
147394. DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT
147395. DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK
147396. DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT
147397. DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK
147398. DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT
147399. DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK
147400. DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT
147401. DSCL1_RECOUT_START__RECOUT_START_X_MASK
147402. DSCL1_RECOUT_START__RECOUT_START_X__SHIFT
147403. DSCL1_RECOUT_START__RECOUT_START_Y_MASK
147404. DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT
147405. DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK
147406. DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT
147407. DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK
147408. DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT
147409. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK
147410. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT
147411. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK
147412. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT
147413. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK
147414. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT
147415. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK
147416. DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT
147417. DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK
147418. DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT
147419. DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK
147420. DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT
147421. DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK
147422. DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT
147423. DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK
147424. DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT
147425. DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK
147426. DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT
147427. DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK
147428. DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT
147429. DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK
147430. DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT
147431. DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK
147432. DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT
147433. DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK
147434. DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT
147435. DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK
147436. DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT
147437. DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK
147438. DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT
147439. DSCL1_SCL_MODE__DSCL_MODE_MASK
147440. DSCL1_SCL_MODE__DSCL_MODE__SHIFT
147441. DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK
147442. DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT
147443. DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK
147444. DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT
147445. DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK
147446. DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT
147447. DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK
147448. DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK
147449. DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT
147450. DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT
147451. DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK
147452. DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT
147453. DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK
147454. DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT
147455. DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK
147456. DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT
147457. DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK
147458. DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT
147459. DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK
147460. DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT
147461. DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK
147462. DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT
147463. DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK
147464. DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT
147465. DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK
147466. DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT
147467. DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK
147468. DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT
147469. DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK
147470. DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT
147471. DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK
147472. DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT
147473. DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK
147474. DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT
147475. DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK
147476. DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT
147477. DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK
147478. DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT
147479. DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK
147480. DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT
147481. DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK
147482. DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT
147483. DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK
147484. DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT
147485. DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK
147486. DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT
147487. DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK
147488. DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT
147489. DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK
147490. DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT
147491. DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK
147492. DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT
147493. DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK
147494. DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT
147495. DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK
147496. DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT
147497. DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK
147498. DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT
147499. DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK
147500. DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT
147501. DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK
147502. DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT
147503. DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK
147504. DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT
147505. DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK
147506. DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT
147507. DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK
147508. DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT
147509. DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK
147510. DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT
147511. DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK
147512. DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT
147513. DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK
147514. DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT
147515. DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK
147516. DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT
147517. DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK
147518. DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT
147519. DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK
147520. DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT
147521. DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK
147522. DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT
147523. DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK
147524. DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT
147525. DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK
147526. DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT
147527. DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK
147528. DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT
147529. DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK
147530. DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT
147531. DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK
147532. DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT
147533. DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK
147534. DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT
147535. DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK
147536. DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT
147537. DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK
147538. DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT
147539. DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK
147540. DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT
147541. DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK
147542. DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT
147543. DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK
147544. DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT
147545. DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK
147546. DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT
147547. DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK
147548. DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT
147549. DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK
147550. DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT
147551. DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK
147552. DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT
147553. DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK
147554. DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT
147555. DSCL2_LB_DATA_FORMAT__DITHER_EN_MASK
147556. DSCL2_LB_DATA_FORMAT__DITHER_EN__SHIFT
147557. DSCL2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK
147558. DSCL2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT
147559. DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK
147560. DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
147561. DSCL2_LB_DATA_FORMAT__PIXEL_DEPTH_MASK
147562. DSCL2_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT
147563. DSCL2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK
147564. DSCL2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT
147565. DSCL2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK
147566. DSCL2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT
147567. DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK
147568. DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT
147569. DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK
147570. DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT
147571. DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK
147572. DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT
147573. DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK
147574. DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT
147575. DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK
147576. DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT
147577. DSCL2_LB_V_COUNTER__V_COUNTER_MASK
147578. DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT
147579. DSCL2_MPC_SIZE__MPC_HEIGHT_MASK
147580. DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT
147581. DSCL2_MPC_SIZE__MPC_WIDTH_MASK
147582. DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT
147583. DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK
147584. DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT
147585. DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK
147586. DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT
147587. DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK
147588. DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT
147589. DSCL2_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK
147590. DSCL2_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT
147591. DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK
147592. DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT
147593. DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK
147594. DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT
147595. DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK
147596. DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT
147597. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK
147598. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT
147599. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK
147600. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT
147601. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK
147602. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT
147603. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK
147604. DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT
147605. DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK
147606. DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT
147607. DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK
147608. DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT
147609. DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK
147610. DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT
147611. DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK
147612. DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT
147613. DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK
147614. DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT
147615. DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK
147616. DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT
147617. DSCL2_RECOUT_START__RECOUT_START_X_MASK
147618. DSCL2_RECOUT_START__RECOUT_START_X__SHIFT
147619. DSCL2_RECOUT_START__RECOUT_START_Y_MASK
147620. DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT
147621. DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK
147622. DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT
147623. DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK
147624. DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT
147625. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK
147626. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT
147627. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK
147628. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT
147629. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK
147630. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT
147631. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK
147632. DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT
147633. DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK
147634. DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT
147635. DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK
147636. DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT
147637. DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK
147638. DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT
147639. DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK
147640. DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT
147641. DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK
147642. DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT
147643. DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK
147644. DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT
147645. DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK
147646. DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT
147647. DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK
147648. DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT
147649. DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK
147650. DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT
147651. DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK
147652. DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT
147653. DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK
147654. DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT
147655. DSCL2_SCL_MODE__DSCL_MODE_MASK
147656. DSCL2_SCL_MODE__DSCL_MODE__SHIFT
147657. DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK
147658. DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT
147659. DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK
147660. DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT
147661. DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK
147662. DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT
147663. DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK
147664. DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK
147665. DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT
147666. DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT
147667. DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK
147668. DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT
147669. DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK
147670. DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT
147671. DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK
147672. DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT
147673. DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK
147674. DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT
147675. DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK
147676. DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT
147677. DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK
147678. DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT
147679. DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK
147680. DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT
147681. DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK
147682. DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT
147683. DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK
147684. DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT
147685. DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK
147686. DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT
147687. DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK
147688. DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT
147689. DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK
147690. DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT
147691. DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK
147692. DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT
147693. DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK
147694. DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT
147695. DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK
147696. DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT
147697. DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK
147698. DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT
147699. DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK
147700. DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT
147701. DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK
147702. DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT
147703. DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK
147704. DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT
147705. DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK
147706. DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT
147707. DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK
147708. DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT
147709. DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK
147710. DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT
147711. DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK
147712. DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT
147713. DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK
147714. DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT
147715. DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK
147716. DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT
147717. DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK
147718. DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT
147719. DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK
147720. DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT
147721. DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK
147722. DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT
147723. DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK
147724. DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT
147725. DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK
147726. DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT
147727. DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK
147728. DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT
147729. DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK
147730. DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT
147731. DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK
147732. DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT
147733. DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK
147734. DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT
147735. DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK
147736. DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT
147737. DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK
147738. DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT
147739. DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK
147740. DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT
147741. DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK
147742. DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT
147743. DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK
147744. DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT
147745. DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK
147746. DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT
147747. DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK
147748. DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT
147749. DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK
147750. DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT
147751. DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK
147752. DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT
147753. DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK
147754. DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT
147755. DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK
147756. DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT
147757. DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK
147758. DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT
147759. DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK
147760. DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT
147761. DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK
147762. DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT
147763. DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK
147764. DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT
147765. DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK
147766. DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT
147767. DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK
147768. DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT
147769. DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK
147770. DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT
147771. DSCL3_LB_DATA_FORMAT__DITHER_EN_MASK
147772. DSCL3_LB_DATA_FORMAT__DITHER_EN__SHIFT
147773. DSCL3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK
147774. DSCL3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT
147775. DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK
147776. DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
147777. DSCL3_LB_DATA_FORMAT__PIXEL_DEPTH_MASK
147778. DSCL3_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT
147779. DSCL3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK
147780. DSCL3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT
147781. DSCL3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK
147782. DSCL3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT
147783. DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK
147784. DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT
147785. DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK
147786. DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT
147787. DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK
147788. DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT
147789. DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK
147790. DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT
147791. DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK
147792. DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT
147793. DSCL3_LB_V_COUNTER__V_COUNTER_MASK
147794. DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT
147795. DSCL3_MPC_SIZE__MPC_HEIGHT_MASK
147796. DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT
147797. DSCL3_MPC_SIZE__MPC_WIDTH_MASK
147798. DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT
147799. DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK
147800. DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT
147801. DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK
147802. DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT
147803. DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK
147804. DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT
147805. DSCL3_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK
147806. DSCL3_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT
147807. DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK
147808. DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT
147809. DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK
147810. DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT
147811. DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK
147812. DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT
147813. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK
147814. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT
147815. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK
147816. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT
147817. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK
147818. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT
147819. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK
147820. DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT
147821. DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK
147822. DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT
147823. DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK
147824. DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT
147825. DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK
147826. DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT
147827. DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK
147828. DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT
147829. DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK
147830. DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT
147831. DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK
147832. DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT
147833. DSCL3_RECOUT_START__RECOUT_START_X_MASK
147834. DSCL3_RECOUT_START__RECOUT_START_X__SHIFT
147835. DSCL3_RECOUT_START__RECOUT_START_Y_MASK
147836. DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT
147837. DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK
147838. DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT
147839. DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK
147840. DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT
147841. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK
147842. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT
147843. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK
147844. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT
147845. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK
147846. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT
147847. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK
147848. DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT
147849. DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK
147850. DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT
147851. DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK
147852. DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT
147853. DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK
147854. DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT
147855. DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK
147856. DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT
147857. DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK
147858. DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT
147859. DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK
147860. DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT
147861. DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK
147862. DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT
147863. DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK
147864. DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT
147865. DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK
147866. DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT
147867. DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK
147868. DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT
147869. DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK
147870. DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT
147871. DSCL3_SCL_MODE__DSCL_MODE_MASK
147872. DSCL3_SCL_MODE__DSCL_MODE__SHIFT
147873. DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK
147874. DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT
147875. DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK
147876. DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT
147877. DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK
147878. DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT
147879. DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK
147880. DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK
147881. DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT
147882. DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT
147883. DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK
147884. DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT
147885. DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK
147886. DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT
147887. DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK
147888. DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT
147889. DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK
147890. DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT
147891. DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK
147892. DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT
147893. DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK
147894. DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT
147895. DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK
147896. DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT
147897. DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK
147898. DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT
147899. DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK
147900. DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT
147901. DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK
147902. DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT
147903. DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK
147904. DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT
147905. DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK
147906. DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT
147907. DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK
147908. DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT
147909. DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK
147910. DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT
147911. DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK
147912. DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT
147913. DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK
147914. DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT
147915. DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK
147916. DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT
147917. DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK
147918. DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT
147919. DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK
147920. DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT
147921. DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK
147922. DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT
147923. DSCL4_DSCL_AUTOCAL__AUTOCAL_MODE_MASK
147924. DSCL4_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT
147925. DSCL4_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK
147926. DSCL4_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT
147927. DSCL4_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK
147928. DSCL4_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT
147929. DSCL4_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK
147930. DSCL4_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT
147931. DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK
147932. DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT
147933. DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK
147934. DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT
147935. DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK
147936. DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT
147937. DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK
147938. DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT
147939. DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK
147940. DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT
147941. DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK
147942. DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT
147943. DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK
147944. DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT
147945. DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK
147946. DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT
147947. DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK
147948. DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT
147949. DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK
147950. DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT
147951. DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK
147952. DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT
147953. DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK
147954. DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT
147955. DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK
147956. DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT
147957. DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK
147958. DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT
147959. DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK
147960. DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT
147961. DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK
147962. DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT
147963. DSCL4_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK
147964. DSCL4_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT
147965. DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK
147966. DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT
147967. DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK
147968. DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT
147969. DSCL4_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK
147970. DSCL4_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT
147971. DSCL4_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK
147972. DSCL4_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT
147973. DSCL4_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK
147974. DSCL4_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT
147975. DSCL4_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK
147976. DSCL4_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT
147977. DSCL4_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK
147978. DSCL4_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT
147979. DSCL4_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK
147980. DSCL4_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT
147981. DSCL4_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK
147982. DSCL4_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT
147983. DSCL4_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK
147984. DSCL4_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT
147985. DSCL4_LB_DATA_FORMAT__ALPHA_EN_MASK
147986. DSCL4_LB_DATA_FORMAT__ALPHA_EN__SHIFT
147987. DSCL4_LB_DATA_FORMAT__INTERLEAVE_EN_MASK
147988. DSCL4_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
147989. DSCL4_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK
147990. DSCL4_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT
147991. DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK
147992. DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT
147993. DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK
147994. DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT
147995. DSCL4_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK
147996. DSCL4_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT
147997. DSCL4_LB_V_COUNTER__V_COUNTER_C_MASK
147998. DSCL4_LB_V_COUNTER__V_COUNTER_C__SHIFT
147999. DSCL4_LB_V_COUNTER__V_COUNTER_MASK
148000. DSCL4_LB_V_COUNTER__V_COUNTER__SHIFT
148001. DSCL4_MPC_SIZE__MPC_HEIGHT_MASK
148002. DSCL4_MPC_SIZE__MPC_HEIGHT__SHIFT
148003. DSCL4_MPC_SIZE__MPC_WIDTH_MASK
148004. DSCL4_MPC_SIZE__MPC_WIDTH__SHIFT
148005. DSCL4_OBUF_CONTROL__OBUF_BYPASS_MASK
148006. DSCL4_OBUF_CONTROL__OBUF_BYPASS__SHIFT
148007. DSCL4_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK
148008. DSCL4_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT
148009. DSCL4_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK
148010. DSCL4_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT
148011. DSCL4_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK
148012. DSCL4_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT
148013. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK
148014. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT
148015. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK
148016. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT
148017. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK
148018. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT
148019. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK
148020. DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT
148021. DSCL4_OTG_H_BLANK__OTG_H_BLANK_END_MASK
148022. DSCL4_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT
148023. DSCL4_OTG_H_BLANK__OTG_H_BLANK_START_MASK
148024. DSCL4_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT
148025. DSCL4_OTG_V_BLANK__OTG_V_BLANK_END_MASK
148026. DSCL4_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT
148027. DSCL4_OTG_V_BLANK__OTG_V_BLANK_START_MASK
148028. DSCL4_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT
148029. DSCL4_RECOUT_SIZE__RECOUT_HEIGHT_MASK
148030. DSCL4_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT
148031. DSCL4_RECOUT_SIZE__RECOUT_WIDTH_MASK
148032. DSCL4_RECOUT_SIZE__RECOUT_WIDTH__SHIFT
148033. DSCL4_RECOUT_START__RECOUT_START_X_MASK
148034. DSCL4_RECOUT_START__RECOUT_START_X__SHIFT
148035. DSCL4_RECOUT_START__RECOUT_START_Y_MASK
148036. DSCL4_RECOUT_START__RECOUT_START_Y__SHIFT
148037. DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK
148038. DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT
148039. DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK
148040. DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT
148041. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK
148042. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT
148043. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK
148044. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT
148045. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK
148046. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT
148047. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK
148048. DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT
148049. DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK
148050. DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT
148051. DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK
148052. DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT
148053. DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK
148054. DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT
148055. DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK
148056. DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT
148057. DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK
148058. DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT
148059. DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK
148060. DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT
148061. DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK
148062. DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT
148063. DSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK
148064. DSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT
148065. DSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK
148066. DSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT
148067. DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK
148068. DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT
148069. DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK
148070. DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT
148071. DSCL4_SCL_MODE__DSCL_MODE_MASK
148072. DSCL4_SCL_MODE__DSCL_MODE__SHIFT
148073. DSCL4_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK
148074. DSCL4_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT
148075. DSCL4_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK
148076. DSCL4_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT
148077. DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK
148078. DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT
148079. DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_MASK
148080. DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK
148081. DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT
148082. DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT
148083. DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK
148084. DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT
148085. DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK
148086. DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT
148087. DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK
148088. DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT
148089. DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK
148090. DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT
148091. DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK
148092. DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT
148093. DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK
148094. DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT
148095. DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK
148096. DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT
148097. DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK
148098. DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT
148099. DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK
148100. DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT
148101. DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK
148102. DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT
148103. DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK
148104. DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT
148105. DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK
148106. DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT
148107. DSCL4_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK
148108. DSCL4_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT
148109. DSCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK
148110. DSCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT
148111. DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK
148112. DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT
148113. DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK
148114. DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT
148115. DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK
148116. DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT
148117. DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK
148118. DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT
148119. DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK
148120. DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT
148121. DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK
148122. DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT
148123. DSCL5_DSCL_AUTOCAL__AUTOCAL_MODE_MASK
148124. DSCL5_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT
148125. DSCL5_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK
148126. DSCL5_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT
148127. DSCL5_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK
148128. DSCL5_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT
148129. DSCL5_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK
148130. DSCL5_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT
148131. DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK
148132. DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT
148133. DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK
148134. DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT
148135. DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK
148136. DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT
148137. DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK
148138. DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT
148139. DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK
148140. DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT
148141. DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK
148142. DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT
148143. DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK
148144. DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT
148145. DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK
148146. DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT
148147. DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK
148148. DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT
148149. DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK
148150. DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT
148151. DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK
148152. DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT
148153. DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK
148154. DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT
148155. DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK
148156. DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT
148157. DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK
148158. DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT
148159. DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK
148160. DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT
148161. DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK
148162. DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT
148163. DSCL5_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK
148164. DSCL5_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT
148165. DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK
148166. DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT
148167. DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK
148168. DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT
148169. DSCL5_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK
148170. DSCL5_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT
148171. DSCL5_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK
148172. DSCL5_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT
148173. DSCL5_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK
148174. DSCL5_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT
148175. DSCL5_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK
148176. DSCL5_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT
148177. DSCL5_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK
148178. DSCL5_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT
148179. DSCL5_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK
148180. DSCL5_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT
148181. DSCL5_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK
148182. DSCL5_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT
148183. DSCL5_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK
148184. DSCL5_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT
148185. DSCL5_LB_DATA_FORMAT__ALPHA_EN_MASK
148186. DSCL5_LB_DATA_FORMAT__ALPHA_EN__SHIFT
148187. DSCL5_LB_DATA_FORMAT__INTERLEAVE_EN_MASK
148188. DSCL5_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
148189. DSCL5_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK
148190. DSCL5_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT
148191. DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK
148192. DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT
148193. DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK
148194. DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT
148195. DSCL5_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK
148196. DSCL5_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT
148197. DSCL5_LB_V_COUNTER__V_COUNTER_C_MASK
148198. DSCL5_LB_V_COUNTER__V_COUNTER_C__SHIFT
148199. DSCL5_LB_V_COUNTER__V_COUNTER_MASK
148200. DSCL5_LB_V_COUNTER__V_COUNTER__SHIFT
148201. DSCL5_MPC_SIZE__MPC_HEIGHT_MASK
148202. DSCL5_MPC_SIZE__MPC_HEIGHT__SHIFT
148203. DSCL5_MPC_SIZE__MPC_WIDTH_MASK
148204. DSCL5_MPC_SIZE__MPC_WIDTH__SHIFT
148205. DSCL5_OBUF_CONTROL__OBUF_BYPASS_MASK
148206. DSCL5_OBUF_CONTROL__OBUF_BYPASS__SHIFT
148207. DSCL5_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK
148208. DSCL5_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT
148209. DSCL5_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK
148210. DSCL5_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT
148211. DSCL5_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK
148212. DSCL5_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT
148213. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK
148214. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT
148215. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK
148216. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT
148217. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK
148218. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT
148219. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK
148220. DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT
148221. DSCL5_OTG_H_BLANK__OTG_H_BLANK_END_MASK
148222. DSCL5_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT
148223. DSCL5_OTG_H_BLANK__OTG_H_BLANK_START_MASK
148224. DSCL5_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT
148225. DSCL5_OTG_V_BLANK__OTG_V_BLANK_END_MASK
148226. DSCL5_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT
148227. DSCL5_OTG_V_BLANK__OTG_V_BLANK_START_MASK
148228. DSCL5_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT
148229. DSCL5_RECOUT_SIZE__RECOUT_HEIGHT_MASK
148230. DSCL5_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT
148231. DSCL5_RECOUT_SIZE__RECOUT_WIDTH_MASK
148232. DSCL5_RECOUT_SIZE__RECOUT_WIDTH__SHIFT
148233. DSCL5_RECOUT_START__RECOUT_START_X_MASK
148234. DSCL5_RECOUT_START__RECOUT_START_X__SHIFT
148235. DSCL5_RECOUT_START__RECOUT_START_Y_MASK
148236. DSCL5_RECOUT_START__RECOUT_START_Y__SHIFT
148237. DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK
148238. DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT
148239. DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK
148240. DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT
148241. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK
148242. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT
148243. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK
148244. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT
148245. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK
148246. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT
148247. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK
148248. DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT
148249. DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK
148250. DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT
148251. DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK
148252. DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT
148253. DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK
148254. DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT
148255. DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK
148256. DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT
148257. DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK
148258. DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT
148259. DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK
148260. DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT
148261. DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK
148262. DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT
148263. DSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK
148264. DSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT
148265. DSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK
148266. DSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT
148267. DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK
148268. DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT
148269. DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK
148270. DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT
148271. DSCL5_SCL_MODE__DSCL_MODE_MASK
148272. DSCL5_SCL_MODE__DSCL_MODE__SHIFT
148273. DSCL5_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK
148274. DSCL5_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT
148275. DSCL5_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK
148276. DSCL5_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT
148277. DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK
148278. DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT
148279. DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_MASK
148280. DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK
148281. DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT
148282. DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT
148283. DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK
148284. DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT
148285. DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK
148286. DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT
148287. DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK
148288. DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT
148289. DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK
148290. DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT
148291. DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK
148292. DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT
148293. DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK
148294. DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT
148295. DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK
148296. DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT
148297. DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK
148298. DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT
148299. DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK
148300. DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT
148301. DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK
148302. DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT
148303. DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK
148304. DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT
148305. DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK
148306. DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT
148307. DSCL5_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK
148308. DSCL5_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT
148309. DSCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK
148310. DSCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT
148311. DSCL_DATA_PRCESSING_FIXED_FORMAT
148312. DSCL_DATA_PRCESSING_FLOAT_FORMAT
148313. DSCL_MODE_CHROMA_SCALING_BYPASS
148314. DSCL_MODE_DSCL_BYPASS
148315. DSCL_MODE_LUMA_SCALING_BYPASS
148316. DSCL_MODE_SCALING_420_CHROMA_BYPASS
148317. DSCL_MODE_SCALING_420_LUMA_BYPASS
148318. DSCL_MODE_SCALING_420_YCBCR_ENABLE
148319. DSCL_MODE_SCALING_444_BYPASS
148320. DSCL_MODE_SCALING_444_RGB_ENABLE
148321. DSCL_MODE_SCALING_444_YCBCR_ENABLE
148322. DSCL_MODE_SCALING_YCBCR_ENABLE
148323. DSCL_MODE_SEL
148324. DSCL__MEM_PG
148325. DSCL__MEM_PG__0
148326. DSCP_BITS
148327. DSCP_G
148328. DSCP_HASH_TYPE
148329. DSCP_M
148330. DSCP_PRI_EN
148331. DSCP_S
148332. DSCP_V
148333. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
148334. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
148335. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK
148336. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK
148337. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT
148338. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT
148339. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK
148340. DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT
148341. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
148342. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
148343. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK
148344. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK
148345. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT
148346. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT
148347. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK
148348. DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT
148349. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
148350. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
148351. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK
148352. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK
148353. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT
148354. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT
148355. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK
148356. DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT
148357. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
148358. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
148359. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK
148360. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK
148361. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT
148362. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT
148363. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK
148364. DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT
148365. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
148366. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
148367. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK
148368. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK
148369. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT
148370. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT
148371. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK
148372. DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT
148373. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK
148374. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT
148375. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK
148376. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK
148377. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT
148378. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT
148379. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK
148380. DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT
148381. DSCR_1
148382. DSCR_2
148383. DSCR_3
148384. DSCR_4
148385. DSCR_5
148386. DSCR_CMD0_ALWAYS
148387. DSCR_CMD0_ARB
148388. DSCR_CMD0_BYTE
148389. DSCR_CMD0_CMP_BRANCH
148390. DSCR_CMD0_CV
148391. DSCR_CMD0_DID
148392. DSCR_CMD0_DID_MASK
148393. DSCR_CMD0_DN
148394. DSCR_CMD0_DT
148395. DSCR_CMD0_DT_MASK
148396. DSCR_CMD0_DW
148397. DSCR_CMD0_DW_MASK
148398. DSCR_CMD0_HALFWORD
148399. DSCR_CMD0_IE
148400. DSCR_CMD0_LITERAL
148401. DSCR_CMD0_MEM
148402. DSCR_CMD0_SID
148403. DSCR_CMD0_SID_MASK
148404. DSCR_CMD0_SM
148405. DSCR_CMD0_SN
148406. DSCR_CMD0_SP
148407. DSCR_CMD0_ST
148408. DSCR_CMD0_STANDARD
148409. DSCR_CMD0_ST_BYTECNT
148410. DSCR_CMD0_ST_CMD0
148411. DSCR_CMD0_ST_CURRENT
148412. DSCR_CMD0_ST_MASK
148413. DSCR_CMD0_ST_NOCHANGE
148414. DSCR_CMD0_SW
148415. DSCR_CMD0_SW_MASK
148416. DSCR_CMD0_THROTTLE
148417. DSCR_CMD0_V
148418. DSCR_CMD0_WORD
148419. DSCR_CMD1_BC_MASK
148420. DSCR_CMD1_DUPTR_MASK
148421. DSCR_CMD1_FL
148422. DSCR_CMD1_FL_MASK
148423. DSCR_CMD1_FL_MEM_STRIDE0
148424. DSCR_CMD1_FL_MEM_STRIDE1
148425. DSCR_CMD1_FL_MEM_STRIDE2
148426. DSCR_CMD1_SUPTR_MASK
148427. DSCR_CUSTOM2DEV_ID
148428. DSCR_DEFAULT
148429. DSCR_DEST1_DAM
148430. DSCR_DEST1_DAM_MASK
148431. DSCR_DEST1_DB
148432. DSCR_DEST1_DB_MASK
148433. DSCR_DEST1_DS
148434. DSCR_DEST1_DS_MASK
148435. DSCR_DEST1_DTS
148436. DSCR_DEST1_DTS_MASK
148437. DSCR_DEV2CUSTOM_ID
148438. DSCR_DEVSTATE_DISABLED
148439. DSCR_DEVSTATE_ENABLED
148440. DSCR_GET_NXTPTR
148441. DSCR_MAX
148442. DSCR_NDEV_IDS
148443. DSCR_NXTPTR
148444. DSCR_NXTPTR_MASK
148445. DSCR_NXTPTR_MS
148446. DSCR_SRC1_SAM
148447. DSCR_SRC1_SAM_MASK
148448. DSCR_SRC1_SB
148449. DSCR_SRC1_SB_MASK
148450. DSCR_SRC1_SS
148451. DSCR_SRC1_SS_MASK
148452. DSCR_SRC1_STS
148453. DSCR_SRC1_STS_MASK
148454. DSCR_xAM_BURST
148455. DSCR_xAM_DECREMENT
148456. DSCR_xAM_INCREMENT
148457. DSCR_xAM_STATIC
148458. DSCR_xTS_SIZE1
148459. DSCR_xTS_SIZE2
148460. DSCR_xTS_SIZE4
148461. DSCR_xTS_SIZE8
148462. DSCTRL
148463. DSCTRL_BLNK_DIS
148464. DSCTRL_BLNK_POL
148465. DSCTRL_CLKPOL
148466. DSCTRL_CSYNC_EN
148467. DSCTRL_DPL_RST
148468. DSCTRL_HS_DIS
148469. DSCTRL_HS_POL
148470. DSCTRL_HS_SLAVE
148471. DSCTRL_PWRDN_M
148472. DSCTRL_SYNCGEN_EN
148473. DSCTRL_UPDCNT
148474. DSCTRL_UPDINTCNT
148475. DSCTRL_UPDSYNCCNT
148476. DSCTRL_UPDWAIT
148477. DSCTRL_VS_DIS
148478. DSCTRL_VS_POL
148479. DSCTRL_VS_SLAVE
148480. DSC_1_1_MAX_LINEBUF_DEPTH_BITS
148481. DSC_1_2_MAX_LINEBUF_DEPTH_BITS
148482. DSC_1_2_MAX_LINEBUF_DEPTH_VAL
148483. DSC_422_ENABLE
148484. DSC_ADISC
148485. DSC_BBUF_UF_INT
148486. DSC_BLOCK_PREDICTION
148487. DSC_BPC_10
148488. DSC_BPC_12
148489. DSC_BPC_8
148490. DSC_BPC_SHIFT
148491. DSC_BPC_UNKNOWN
148492. DSC_BPP
148493. DSC_CMD_SEND
148494. DSC_COLOR_SPACE_CONVERSION
148495. DSC_DBW_32
148496. DSC_DBW_64
148497. DSC_DBW_MASK
148498. DSC_DELETED
148499. DSC_DELETE_PEND
148500. DSC_ECC_EN
148501. DSC_EXECUTE_QUEUE
148502. DSC_EXEC_DONE
148503. DSC_FIELD_LIST_DCN20
148504. DSC_FINAL_OFFSET
148505. DSC_FIRST_LINE_BPG_OFFSET
148506. DSC_FLATNESS_MAX_QP
148507. DSC_FLATNESS_MIN_QP
148508. DSC_GNL
148509. DSC_GNN_ID
148510. DSC_GPDB
148511. DSC_INIT16
148512. DSC_INITIAL_DEC_DELAY
148513. DSC_INITIAL_OFFSET
148514. DSC_INITIAL_SCALE_VALUE
148515. DSC_INITIAL_XMIT_DELAY
148516. DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK
148517. DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT
148518. DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK
148519. DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT
148520. DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
148521. DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
148522. DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
148523. DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
148524. DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK
148525. DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT
148526. DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK
148527. DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT
148528. DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
148529. DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
148530. DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
148531. DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
148532. DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK
148533. DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT
148534. DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK
148535. DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT
148536. DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
148537. DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
148538. DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
148539. DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
148540. DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK
148541. DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT
148542. DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK
148543. DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT
148544. DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
148545. DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
148546. DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
148547. DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
148548. DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK
148549. DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT
148550. DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK
148551. DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT
148552. DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
148553. DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
148554. DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
148555. DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
148556. DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK
148557. DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT
148558. DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK
148559. DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT
148560. DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
148561. DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
148562. DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
148563. DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
148564. DSC_LINE_BUF_DEPTH_SHIFT
148565. DSC_LOGIN_COMPLETE
148566. DSC_LOGIN_FAILED
148567. DSC_LOGIN_PEND
148568. DSC_LS_LLIOCB_SENT
148569. DSC_LS_LOGO_PEND
148570. DSC_LS_PLOGI_COMP
148571. DSC_LS_PLOGI_PEND
148572. DSC_LS_PORT_UNAVAIL
148573. DSC_LS_PRLI_COMP
148574. DSC_LS_PRLI_PEND
148575. DSC_LS_PRLO_PEND
148576. DSC_MEM_EN
148577. DSC_MODE_CTL
148578. DSC_MODE_EN
148579. DSC_MODE_STS
148580. DSC_MUX_WORD_SIZE_12_BPC
148581. DSC_MUX_WORD_SIZE_8_10_BPC
148582. DSC_NFL_BPG_OFFSET
148583. DSC_NUM_BUF_RANGES
148584. DSC_OBUF_UF_INT
148585. DSC_OWNER_MAC
148586. DSC_PIC_HEIGHT
148587. DSC_PIC_WIDTH
148588. DSC_PIXFMT_NATIVE_YCBCR420
148589. DSC_PIXFMT_NATIVE_YCBCR422
148590. DSC_PIXFMT_RGB
148591. DSC_PIXFMT_SIMPLE_YCBCR422
148592. DSC_PIXFMT_UNKNOWN
148593. DSC_PIXFMT_YCBCR444
148594. DSC_PPS_BLOCK_PRED_EN_SHIFT
148595. DSC_PPS_BPC_SHIFT
148596. DSC_PPS_BPP_HIGH_MASK
148597. DSC_PPS_CONVERT_RGB_SHIFT
148598. DSC_PPS_DONE
148599. DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK
148600. DSC_PPS_LSB_MASK
148601. DSC_PPS_MSB_SHIFT
148602. DSC_PPS_NATIVE_420_SHIFT
148603. DSC_PPS_RC_RANGE_MAXQP_SHIFT
148604. DSC_PPS_RC_RANGE_MINQP_SHIFT
148605. DSC_PPS_RC_TGT_OFFSET_HI_SHIFT
148606. DSC_PPS_SCALE_DEC_INT_HIGH_MASK
148607. DSC_PPS_SIMPLE422_SHIFT
148608. DSC_PPS_VBR_EN_SHIFT
148609. DSC_PPS_VERSION_MAJOR_SHIFT
148610. DSC_PPS_WRDAT
148611. DSC_RANGE_BPG_OFFSET_MASK
148612. DSC_RBUF_UF_INT
148613. DSC_RC_EDGE_FACTOR
148614. DSC_RC_EDGE_FACTOR_CONST
148615. DSC_RC_MODEL_SIZE
148616. DSC_RC_MODEL_SIZE_CONST
148617. DSC_RC_PIXELS_PER_GROUP
148618. DSC_RC_QUANT_INC_LIMIT0
148619. DSC_RC_QUANT_INC_LIMIT1
148620. DSC_RC_TARGET_OFF_HIGH
148621. DSC_RC_TARGET_OFF_LOW
148622. DSC_RC_TGT_OFFSET_HI_CONST
148623. DSC_RC_TGT_OFFSET_LO_CONST
148624. DSC_RD_EN
148625. DSC_REG_LIST_DCN20
148626. DSC_REG_LIST_SH_MASK_DCN20
148627. DSC_REQ_MSG
148628. DSC_RESP_MSG
148629. DSC_RX_BCAST
148630. DSC_RX_ERR
148631. DSC_RX_ERR_BUF
148632. DSC_RX_ERR_CRC
148633. DSC_RX_ERR_DRI
148634. DSC_RX_ERR_LONG
148635. DSC_RX_ERR_RUNT
148636. DSC_RX_IDX_MID_MASK
148637. DSC_RX_MCAST
148638. DSC_RX_MCH_HIT
148639. DSC_RX_MIDH_HIT
148640. DSC_RX_OK
148641. DSC_SCALE_DECREMENT_INTERVAL_MAX
148642. DSC_SCALE_DEC_INT
148643. DSC_SCALE_INC_INT
148644. DSC_SDTYPE_MASK
148645. DSC_SEND_PPS
148646. DSC_SF
148647. DSC_SLICE_BPG_OFFSET
148648. DSC_SLICE_CHUNK_SIZE
148649. DSC_SLICE_HEIGHT
148650. DSC_SLICE_PER_LINE
148651. DSC_SLICE_ROW_PER_FRAME
148652. DSC_SLICE_WIDTH
148653. DSC_SUPPORTED_VERSION_MIN
148654. DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK
148655. DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT
148656. DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK
148657. DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT
148658. DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK
148659. DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT
148660. DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK
148661. DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT
148662. DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK
148663. DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT
148664. DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK
148665. DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT
148666. DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK
148667. DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT
148668. DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK
148669. DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT
148670. DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK
148671. DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT
148672. DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK
148673. DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT
148674. DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK
148675. DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT
148676. DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK
148677. DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT
148678. DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK
148679. DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT
148680. DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK
148681. DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT
148682. DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK
148683. DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT
148684. DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK
148685. DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT
148686. DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK
148687. DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT
148688. DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK
148689. DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT
148690. DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK
148691. DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT
148692. DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK
148693. DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT
148694. DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK
148695. DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT
148696. DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK
148697. DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT
148698. DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK
148699. DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT
148700. DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK
148701. DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT
148702. DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK
148703. DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT
148704. DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK
148705. DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT
148706. DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK
148707. DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT
148708. DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK
148709. DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT
148710. DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK
148711. DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT
148712. DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK
148713. DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT
148714. DSC_TO_UF_INT
148715. DSC_TRIAL_FAIL_MSG
148716. DSC_TRIAL_MSG
148717. DSC_UPD_FCPORT
148718. DSC_VBR_ENABLE
148719. DSC_VER_MAJ
148720. DSC_VER_MIN_SHIFT
148721. DSC_X32_EN
148722. DSD_CFG_MUX
148723. DSD_CFG_MUX_TE_UNMASK_GLOBAL
148724. DSD_INV
148725. DSD_LIST_DMA_POOL_SIZE
148726. DSD_SEL
148727. DSEL_TIME
148728. DSE_CFG
148729. DSE_FIRST
148730. DSE_PRIO_0
148731. DSE_PRIO_1
148732. DSE_PRIO_2
148733. DSE_PRIO_3
148734. DSE_RING_REGION_HI
148735. DSE_RING_REGION_LO
148736. DSE_THR_CTRL
148737. DSE_THR_DESC_CTRL
148738. DSE_THR_DESC_DPTR_HI
148739. DSE_THR_DESC_DPTR_LO
148740. DSE_THR_DESC_S_DPTR_HI
148741. DSE_THR_DESC_S_DPTR_LO
148742. DSE_THR_ERROR_STAT
148743. DSE_THR_STAT
148744. DSHI
148745. DSHPR
148746. DSHPR_CODE
148747. DSHPR_PRIH
148748. DSHPR_PRIL_BPP16
148749. DSHPR_PRIL_BPP32
148750. DSI
148751. DSI0_CTRL
148752. DSI0_CTRL_CLR_CDF
148753. DSI0_CTRL_CLR_CPBCF
148754. DSI0_CTRL_CLR_PBCF
148755. DSI0_CTRL_CLR_PDF
148756. DSI0_CTRL_CTRL0
148757. DSI0_CTRL_CTRL1
148758. DSI0_CTRL_CTRL2
148759. DSI0_CTRL_RESET_FIFOS
148760. DSI0_DISP0_CTRL
148761. DSI0_DISP1_CTRL
148762. DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK
148763. DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT
148764. DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK
148765. DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT
148766. DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK
148767. DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT
148768. DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK
148769. DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT
148770. DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK
148771. DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT
148772. DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK
148773. DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT
148774. DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK
148775. DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT
148776. DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK
148777. DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT
148778. DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK
148779. DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT
148780. DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK
148781. DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT
148782. DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK
148783. DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT
148784. DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK
148785. DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT
148786. DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK
148787. DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT
148788. DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK
148789. DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT
148790. DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK
148791. DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT
148792. DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK
148793. DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT
148794. DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK
148795. DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT
148796. DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK
148797. DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT
148798. DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK
148799. DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT
148800. DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK
148801. DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT
148802. DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK
148803. DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT
148804. DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK
148805. DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT
148806. DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK
148807. DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT
148808. DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK
148809. DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT
148810. DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK
148811. DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT
148812. DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK
148813. DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT
148814. DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK
148815. DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT
148816. DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK
148817. DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT
148818. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK
148819. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT
148820. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK
148821. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT
148822. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK
148823. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT
148824. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK
148825. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT
148826. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK
148827. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT
148828. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK
148829. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT
148830. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK
148831. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT
148832. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK
148833. DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT
148834. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK
148835. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT
148836. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK
148837. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT
148838. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK
148839. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT
148840. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK
148841. DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT
148842. DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK
148843. DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT
148844. DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK
148845. DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT
148846. DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK
148847. DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT
148848. DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK
148849. DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT
148850. DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK
148851. DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT
148852. DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK
148853. DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT
148854. DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK
148855. DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT
148856. DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK
148857. DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT
148858. DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK
148859. DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT
148860. DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK
148861. DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT
148862. DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK
148863. DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT
148864. DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK
148865. DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT
148866. DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK
148867. DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT
148868. DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK
148869. DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT
148870. DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK
148871. DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT
148872. DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK
148873. DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT
148874. DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK
148875. DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT
148876. DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK
148877. DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT
148878. DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK
148879. DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT
148880. DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK
148881. DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT
148882. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK
148883. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT
148884. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK
148885. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT
148886. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK
148887. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT
148888. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK
148889. DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT
148890. DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK
148891. DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT
148892. DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK
148893. DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT
148894. DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK
148895. DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT
148896. DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK
148897. DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT
148898. DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK
148899. DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT
148900. DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK
148901. DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT
148902. DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK
148903. DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT
148904. DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK
148905. DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT
148906. DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK
148907. DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT
148908. DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK
148909. DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT
148910. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK
148911. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT
148912. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK
148913. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT
148914. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK
148915. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT
148916. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK
148917. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT
148918. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK
148919. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT
148920. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK
148921. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT
148922. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK
148923. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT
148924. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK
148925. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT
148926. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK
148927. DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT
148928. DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK
148929. DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT
148930. DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK
148931. DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT
148932. DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK
148933. DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT
148934. DSI0_DISP_DSI_CTRL__CLKLN_EN_MASK
148935. DSI0_DISP_DSI_CTRL__CLKLN_EN__SHIFT
148936. DSI0_DISP_DSI_CTRL__CMD_MODE_EN_MASK
148937. DSI0_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT
148938. DSI0_DISP_DSI_CTRL__CRC_CHK_EN_MASK
148939. DSI0_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT
148940. DSI0_DISP_DSI_CTRL__CRTC_SEL_MASK
148941. DSI0_DISP_DSI_CTRL__CRTC_SEL__SHIFT
148942. DSI0_DISP_DSI_CTRL__DLN0_EN_MASK
148943. DSI0_DISP_DSI_CTRL__DLN0_EN__SHIFT
148944. DSI0_DISP_DSI_CTRL__DLN0_PHY_EN_MASK
148945. DSI0_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT
148946. DSI0_DISP_DSI_CTRL__DLN1_EN_MASK
148947. DSI0_DISP_DSI_CTRL__DLN1_EN__SHIFT
148948. DSI0_DISP_DSI_CTRL__DLN1_PHY_EN_MASK
148949. DSI0_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT
148950. DSI0_DISP_DSI_CTRL__DLN2_EN_MASK
148951. DSI0_DISP_DSI_CTRL__DLN2_EN__SHIFT
148952. DSI0_DISP_DSI_CTRL__DLN2_PHY_EN_MASK
148953. DSI0_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT
148954. DSI0_DISP_DSI_CTRL__DLN3_EN_MASK
148955. DSI0_DISP_DSI_CTRL__DLN3_EN__SHIFT
148956. DSI0_DISP_DSI_CTRL__DLN3_PHY_EN_MASK
148957. DSI0_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT
148958. DSI0_DISP_DSI_CTRL__DSI_EN_MASK
148959. DSI0_DISP_DSI_CTRL__DSI_EN__SHIFT
148960. DSI0_DISP_DSI_CTRL__ECC_CHK_EN_MASK
148961. DSI0_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT
148962. DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK
148963. DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT
148964. DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK
148965. DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT
148966. DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK
148967. DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT
148968. DSI0_DISP_DSI_CTRL__RESET_BYTECLK_MASK
148969. DSI0_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT
148970. DSI0_DISP_DSI_CTRL__RESET_DISPCLK_MASK
148971. DSI0_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT
148972. DSI0_DISP_DSI_CTRL__RESET_DSICLK_MASK
148973. DSI0_DISP_DSI_CTRL__RESET_DSICLK__SHIFT
148974. DSI0_DISP_DSI_CTRL__RESET_ESCCLK_MASK
148975. DSI0_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT
148976. DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK
148977. DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT
148978. DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK
148979. DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT
148980. DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK
148981. DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT
148982. DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK
148983. DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT
148984. DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK
148985. DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT
148986. DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK
148987. DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT
148988. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK
148989. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT
148990. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK
148991. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
148992. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK
148993. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT
148994. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK
148995. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
148996. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK
148997. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
148998. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK
148999. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT
149000. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK
149001. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT
149002. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK
149003. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT
149004. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK
149005. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT
149006. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK
149007. DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
149008. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK
149009. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT
149010. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK
149011. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK
149012. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT
149013. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT
149014. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK
149015. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT
149016. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK
149017. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK
149018. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT
149019. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT
149020. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK
149021. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT
149022. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK
149023. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK
149024. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT
149025. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT
149026. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK
149027. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT
149028. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK
149029. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK
149030. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT
149031. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT
149032. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK
149033. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT
149034. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK
149035. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK
149036. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT
149037. DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT
149038. DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK
149039. DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT
149040. DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK
149041. DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT
149042. DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK
149043. DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT
149044. DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK
149045. DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT
149046. DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK
149047. DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT
149048. DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK
149049. DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT
149050. DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK
149051. DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT
149052. DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK
149053. DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT
149054. DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK
149055. DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT
149056. DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK
149057. DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT
149058. DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK
149059. DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT
149060. DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK
149061. DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT
149062. DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK
149063. DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT
149064. DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK
149065. DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT
149066. DSI0_DISP_DSI_EOT_PACKET__DI_MASK
149067. DSI0_DISP_DSI_EOT_PACKET__DI__SHIFT
149068. DSI0_DISP_DSI_EOT_PACKET__ECC_MASK
149069. DSI0_DISP_DSI_EOT_PACKET__ECC__SHIFT
149070. DSI0_DISP_DSI_EOT_PACKET__WC_MASK
149071. DSI0_DISP_DSI_EOT_PACKET__WC__SHIFT
149072. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK
149073. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT
149074. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK
149075. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT
149076. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK
149077. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT
149078. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK
149079. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT
149080. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK
149081. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT
149082. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK
149083. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT
149084. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK
149085. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT
149086. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK
149087. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT
149088. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK
149089. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT
149090. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK
149091. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT
149092. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK
149093. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT
149094. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK
149095. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT
149096. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK
149097. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT
149098. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK
149099. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT
149100. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK
149101. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT
149102. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK
149103. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT
149104. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK
149105. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT
149106. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK
149107. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT
149108. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK
149109. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT
149110. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK
149111. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT
149112. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK
149113. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT
149114. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK
149115. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT
149116. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK
149117. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT
149118. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK
149119. DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT
149120. DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK
149121. DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT
149122. DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK
149123. DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT
149124. DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK
149125. DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT
149126. DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK
149127. DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT
149128. DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK
149129. DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT
149130. DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK
149131. DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT
149132. DSI0_DISP_DSI_EXT_RESET__RESET_PANEL_MASK
149133. DSI0_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT
149134. DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK
149135. DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT
149136. DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK
149137. DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT
149138. DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK
149139. DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT
149140. DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK
149141. DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT
149142. DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK
149143. DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT
149144. DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK
149145. DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT
149146. DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK
149147. DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT
149148. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK
149149. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT
149150. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK
149151. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT
149152. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK
149153. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT
149154. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK
149155. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT
149156. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK
149157. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT
149158. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK
149159. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT
149160. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK
149161. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT
149162. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK
149163. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT
149164. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK
149165. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT
149166. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK
149167. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT
149168. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK
149169. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT
149170. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK
149171. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT
149172. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK
149173. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT
149174. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK
149175. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT
149176. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK
149177. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT
149178. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK
149179. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT
149180. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK
149181. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT
149182. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK
149183. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT
149184. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK
149185. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT
149186. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK
149187. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT
149188. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK
149189. DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT
149190. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK
149191. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT
149192. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK
149193. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT
149194. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK
149195. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT
149196. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK
149197. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT
149198. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK
149199. DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT
149200. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK
149201. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT
149202. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK
149203. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT
149204. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK
149205. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT
149206. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK
149207. DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT
149208. DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK
149209. DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT
149210. DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK
149211. DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT
149212. DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK
149213. DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT
149214. DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK
149215. DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT
149216. DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK
149217. DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT
149218. DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK
149219. DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT
149220. DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK
149221. DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT
149222. DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK
149223. DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT
149224. DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK
149225. DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT
149226. DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK
149227. DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT
149228. DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK
149229. DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT
149230. DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK
149231. DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT
149232. DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK
149233. DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT
149234. DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK
149235. DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT
149236. DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK
149237. DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT
149238. DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK
149239. DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT
149240. DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK
149241. DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT
149242. DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK
149243. DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT
149244. DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK
149245. DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT
149246. DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK
149247. DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT
149248. DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK
149249. DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT
149250. DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK
149251. DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT
149252. DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK
149253. DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT
149254. DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK
149255. DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT
149256. DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK
149257. DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT
149258. DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK
149259. DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT
149260. DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK
149261. DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT
149262. DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK
149263. DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT
149264. DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK
149265. DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT
149266. DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK
149267. DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT
149268. DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK
149269. DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT
149270. DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK
149271. DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT
149272. DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK
149273. DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT
149274. DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK
149275. DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT
149276. DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK
149277. DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT
149278. DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK
149279. DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT
149280. DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK
149281. DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT
149282. DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK
149283. DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT
149284. DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK
149285. DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT
149286. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK
149287. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT
149288. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK
149289. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT
149290. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK
149291. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT
149292. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK
149293. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT
149294. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK
149295. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT
149296. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK
149297. DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT
149298. DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK
149299. DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT
149300. DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK
149301. DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT
149302. DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK
149303. DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT
149304. DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK
149305. DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT
149306. DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK
149307. DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT
149308. DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK
149309. DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT
149310. DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK
149311. DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT
149312. DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK
149313. DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT
149314. DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK
149315. DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT
149316. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK
149317. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT
149318. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK
149319. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT
149320. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK
149321. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT
149322. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK
149323. DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT
149324. DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK
149325. DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT
149326. DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK
149327. DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT
149328. DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK
149329. DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT
149330. DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK
149331. DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT
149332. DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK
149333. DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT
149334. DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK
149335. DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT
149336. DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK
149337. DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT
149338. DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK
149339. DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT
149340. DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK
149341. DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT
149342. DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK
149343. DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT
149344. DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK
149345. DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT
149346. DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK
149347. DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT
149348. DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK
149349. DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT
149350. DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK
149351. DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT
149352. DSI0_DISP_DSI_RDBK_NUM__ALL_NUM_MASK
149353. DSI0_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT
149354. DSI0_DISP_DSI_RDBK_NUM__RD_NUM_MASK
149355. DSI0_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT
149356. DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK
149357. DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT
149358. DSI0_DISP_DSI_STATUS__BTA_BUSY_MASK
149359. DSI0_DISP_DSI_STATUS__BTA_BUSY__SHIFT
149360. DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK
149361. DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT
149362. DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK
149363. DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT
149364. DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK
149365. DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT
149366. DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK
149367. DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT
149368. DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK
149369. DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT
149370. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK
149371. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT
149372. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK
149373. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT
149374. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK
149375. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT
149376. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK
149377. DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT
149378. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK
149379. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT
149380. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK
149381. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT
149382. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK
149383. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT
149384. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK
149385. DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT
149386. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK
149387. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT
149388. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK
149389. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT
149390. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK
149391. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT
149392. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK
149393. DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT
149394. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK
149395. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT
149396. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK
149397. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT
149398. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK
149399. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT
149400. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK
149401. DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT
149402. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK
149403. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT
149404. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK
149405. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT
149406. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK
149407. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT
149408. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK
149409. DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT
149410. DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK
149411. DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT
149412. DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK
149413. DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT
149414. DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK
149415. DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT
149416. DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK
149417. DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT
149418. DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK
149419. DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT
149420. DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK
149421. DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT
149422. DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK
149423. DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT
149424. DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK
149425. DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT
149426. DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK
149427. DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT
149428. DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK
149429. DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT
149430. DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK
149431. DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT
149432. DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK
149433. DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT
149434. DSI0_DISP_DSI_STATUS__TE_ABORT_CLR_MASK
149435. DSI0_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT
149436. DSI0_DISP_DSI_STATUS__TE_ABORT_MASK
149437. DSI0_DISP_DSI_STATUS__TE_ABORT__SHIFT
149438. DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK
149439. DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT
149440. DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK
149441. DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK
149442. DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT
149443. DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT
149444. DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK
149445. DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT
149446. DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK
149447. DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT
149448. DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK
149449. DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT
149450. DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK
149451. DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT
149452. DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK
149453. DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT
149454. DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK
149455. DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT
149456. DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK
149457. DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT
149458. DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK
149459. DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT
149460. DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK
149461. DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT
149462. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK
149463. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT
149464. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK
149465. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT
149466. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK
149467. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT
149468. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK
149469. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT
149470. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK
149471. DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT
149472. DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK
149473. DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT
149474. DSI0_DISP_DSI_TRIG_CTRL__TE_SEL_MASK
149475. DSI0_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT
149476. DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK
149477. DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT
149478. DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK
149479. DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT
149480. DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK
149481. DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT
149482. DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK
149483. DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT
149484. DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK
149485. DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT
149486. DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK
149487. DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT
149488. DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK
149489. DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT
149490. DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK
149491. DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT
149492. DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK
149493. DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT
149494. DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK
149495. DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT
149496. DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK
149497. DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT
149498. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK
149499. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT
149500. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK
149501. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT
149502. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK
149503. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT
149504. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK
149505. DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT
149506. DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK
149507. DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT
149508. DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK
149509. DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT
149510. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK
149511. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT
149512. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK
149513. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK
149514. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT
149515. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT
149516. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK
149517. DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT
149518. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK
149519. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT
149520. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK
149521. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT
149522. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK
149523. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT
149524. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK
149525. DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT
149526. DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK
149527. DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT
149528. DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK
149529. DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT
149530. DSI0_HSTX_TO_CNT
149531. DSI0_HS_CLT0
149532. DSI0_HS_CLT1
149533. DSI0_HS_CLT2
149534. DSI0_HS_DLT3
149535. DSI0_HS_DLT4
149536. DSI0_HS_DLT5
149537. DSI0_HS_DLT6
149538. DSI0_HS_DLT7
149539. DSI0_ID
149540. DSI0_INT_EN
149541. DSI0_INT_STAT
149542. DSI0_LPRX_TO_CNT
149543. DSI0_PHYC
149544. DSI0_PHYC_CLANE_ENABLE
149545. DSI0_PHYC_CLANE_ULPS
149546. DSI0_PHYC_ESC_CLK_LPDT_MASK
149547. DSI0_PHYC_ESC_CLK_LPDT_SHIFT
149548. DSI0_PHYC_HS_CLK_CONTINUOUS
149549. DSI0_PHY_AFEC0
149550. DSI0_PHY_AFEC0_ACTRL_CLANE_MASK
149551. DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT
149552. DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK
149553. DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT
149554. DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK
149555. DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT
149556. DSI0_PHY_AFEC0_DDR2CLK_EN
149557. DSI0_PHY_AFEC0_DDRCLK_EN
149558. DSI0_PHY_AFEC0_LATCH_ULPS
149559. DSI0_PHY_AFEC0_PD
149560. DSI0_PHY_AFEC0_PD_BG
149561. DSI0_PHY_AFEC0_PD_DLANE1
149562. DSI0_PHY_AFEC0_RESET
149563. DSI0_PHY_AFEC1
149564. DSI0_PHY_AFEC1_IDR_CLANE_MASK
149565. DSI0_PHY_AFEC1_IDR_CLANE_SHIFT
149566. DSI0_PHY_AFEC1_IDR_DLANE0_MASK
149567. DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT
149568. DSI0_PHY_AFEC1_IDR_DLANE1_MASK
149569. DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT
149570. DSI0_PR_TO_CNT
149571. DSI0_RXPKT1H
149572. DSI0_RXPKT2H
149573. DSI0_SEL_IN_RDMA1
149574. DSI0_SEL_IN_RDMA2
149575. DSI0_STAT
149576. DSI0_TA_TO_CNT
149577. DSI0_TST_MON
149578. DSI0_TST_SEL
149579. DSI0_TXPKT1C
149580. DSI0_TXPKT1H
149581. DSI0_TXPKT_CMD_FIFO
149582. DSI0_TXPKT_PIX_FIFO
149583. DSI1_BITCLK_DIV
149584. DSI1_BITCLK_DIV_MASK
149585. DSI1_BYTE_CLK
149586. DSI1_BYTE_SRC
149587. DSI1_CTRL
149588. DSI1_CTRL_CLR_CDF
149589. DSI1_CTRL_CLR_PDF
149590. DSI1_CTRL_CLR_RXF
149591. DSI1_CTRL_DISABLE_DISP_CRCC
149592. DSI1_CTRL_DISABLE_DISP_ECCC
149593. DSI1_CTRL_EN
149594. DSI1_CTRL_RESET_FIFOS
149595. DSI1_DISP0_CTRL
149596. DSI1_DISP1_CTRL
149597. DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK
149598. DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT
149599. DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK
149600. DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT
149601. DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK
149602. DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT
149603. DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK
149604. DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT
149605. DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK
149606. DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT
149607. DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK
149608. DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT
149609. DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK
149610. DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT
149611. DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK
149612. DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT
149613. DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK
149614. DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT
149615. DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK
149616. DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT
149617. DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK
149618. DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT
149619. DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK
149620. DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT
149621. DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK
149622. DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT
149623. DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK
149624. DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT
149625. DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK
149626. DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT
149627. DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK
149628. DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT
149629. DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK
149630. DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT
149631. DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK
149632. DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT
149633. DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK
149634. DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT
149635. DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK
149636. DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT
149637. DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK
149638. DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT
149639. DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK
149640. DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT
149641. DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK
149642. DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT
149643. DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK
149644. DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT
149645. DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK
149646. DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT
149647. DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK
149648. DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT
149649. DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK
149650. DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT
149651. DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK
149652. DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT
149653. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK
149654. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT
149655. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK
149656. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT
149657. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK
149658. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT
149659. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK
149660. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT
149661. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK
149662. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT
149663. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK
149664. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT
149665. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK
149666. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT
149667. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK
149668. DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT
149669. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK
149670. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT
149671. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK
149672. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT
149673. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK
149674. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT
149675. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK
149676. DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT
149677. DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK
149678. DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT
149679. DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK
149680. DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT
149681. DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK
149682. DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT
149683. DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK
149684. DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT
149685. DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK
149686. DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT
149687. DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK
149688. DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT
149689. DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK
149690. DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT
149691. DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK
149692. DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT
149693. DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK
149694. DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT
149695. DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK
149696. DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT
149697. DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK
149698. DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT
149699. DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK
149700. DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT
149701. DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK
149702. DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT
149703. DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK
149704. DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT
149705. DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK
149706. DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT
149707. DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK
149708. DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT
149709. DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK
149710. DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT
149711. DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK
149712. DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT
149713. DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK
149714. DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT
149715. DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK
149716. DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT
149717. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK
149718. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT
149719. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK
149720. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT
149721. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK
149722. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT
149723. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK
149724. DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT
149725. DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK
149726. DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT
149727. DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK
149728. DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT
149729. DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK
149730. DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT
149731. DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK
149732. DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT
149733. DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK
149734. DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT
149735. DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK
149736. DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT
149737. DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK
149738. DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT
149739. DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK
149740. DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT
149741. DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK
149742. DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT
149743. DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK
149744. DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT
149745. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK
149746. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT
149747. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK
149748. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT
149749. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK
149750. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT
149751. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK
149752. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT
149753. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK
149754. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT
149755. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK
149756. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT
149757. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK
149758. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT
149759. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK
149760. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT
149761. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK
149762. DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT
149763. DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK
149764. DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT
149765. DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK
149766. DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT
149767. DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK
149768. DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT
149769. DSI1_DISP_DSI_CTRL__CLKLN_EN_MASK
149770. DSI1_DISP_DSI_CTRL__CLKLN_EN__SHIFT
149771. DSI1_DISP_DSI_CTRL__CMD_MODE_EN_MASK
149772. DSI1_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT
149773. DSI1_DISP_DSI_CTRL__CRC_CHK_EN_MASK
149774. DSI1_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT
149775. DSI1_DISP_DSI_CTRL__CRTC_SEL_MASK
149776. DSI1_DISP_DSI_CTRL__CRTC_SEL__SHIFT
149777. DSI1_DISP_DSI_CTRL__DLN0_EN_MASK
149778. DSI1_DISP_DSI_CTRL__DLN0_EN__SHIFT
149779. DSI1_DISP_DSI_CTRL__DLN0_PHY_EN_MASK
149780. DSI1_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT
149781. DSI1_DISP_DSI_CTRL__DLN1_EN_MASK
149782. DSI1_DISP_DSI_CTRL__DLN1_EN__SHIFT
149783. DSI1_DISP_DSI_CTRL__DLN1_PHY_EN_MASK
149784. DSI1_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT
149785. DSI1_DISP_DSI_CTRL__DLN2_EN_MASK
149786. DSI1_DISP_DSI_CTRL__DLN2_EN__SHIFT
149787. DSI1_DISP_DSI_CTRL__DLN2_PHY_EN_MASK
149788. DSI1_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT
149789. DSI1_DISP_DSI_CTRL__DLN3_EN_MASK
149790. DSI1_DISP_DSI_CTRL__DLN3_EN__SHIFT
149791. DSI1_DISP_DSI_CTRL__DLN3_PHY_EN_MASK
149792. DSI1_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT
149793. DSI1_DISP_DSI_CTRL__DSI_EN_MASK
149794. DSI1_DISP_DSI_CTRL__DSI_EN__SHIFT
149795. DSI1_DISP_DSI_CTRL__ECC_CHK_EN_MASK
149796. DSI1_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT
149797. DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK
149798. DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT
149799. DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK
149800. DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT
149801. DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK
149802. DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT
149803. DSI1_DISP_DSI_CTRL__RESET_BYTECLK_MASK
149804. DSI1_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT
149805. DSI1_DISP_DSI_CTRL__RESET_DISPCLK_MASK
149806. DSI1_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT
149807. DSI1_DISP_DSI_CTRL__RESET_DSICLK_MASK
149808. DSI1_DISP_DSI_CTRL__RESET_DSICLK__SHIFT
149809. DSI1_DISP_DSI_CTRL__RESET_ESCCLK_MASK
149810. DSI1_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT
149811. DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK
149812. DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT
149813. DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK
149814. DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT
149815. DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK
149816. DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT
149817. DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK
149818. DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT
149819. DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK
149820. DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT
149821. DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK
149822. DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT
149823. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK
149824. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT
149825. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK
149826. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT
149827. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK
149828. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT
149829. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK
149830. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT
149831. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK
149832. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT
149833. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK
149834. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT
149835. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK
149836. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT
149837. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK
149838. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT
149839. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK
149840. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT
149841. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK
149842. DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT
149843. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK
149844. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT
149845. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK
149846. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK
149847. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT
149848. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT
149849. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK
149850. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT
149851. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK
149852. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK
149853. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT
149854. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT
149855. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK
149856. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT
149857. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK
149858. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK
149859. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT
149860. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT
149861. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK
149862. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT
149863. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK
149864. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK
149865. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT
149866. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT
149867. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK
149868. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT
149869. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK
149870. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK
149871. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT
149872. DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT
149873. DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK
149874. DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT
149875. DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK
149876. DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT
149877. DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK
149878. DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT
149879. DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK
149880. DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT
149881. DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK
149882. DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT
149883. DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK
149884. DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT
149885. DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK
149886. DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT
149887. DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK
149888. DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT
149889. DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK
149890. DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT
149891. DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK
149892. DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT
149893. DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK
149894. DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT
149895. DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK
149896. DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT
149897. DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK
149898. DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT
149899. DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK
149900. DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT
149901. DSI1_DISP_DSI_EOT_PACKET__DI_MASK
149902. DSI1_DISP_DSI_EOT_PACKET__DI__SHIFT
149903. DSI1_DISP_DSI_EOT_PACKET__ECC_MASK
149904. DSI1_DISP_DSI_EOT_PACKET__ECC__SHIFT
149905. DSI1_DISP_DSI_EOT_PACKET__WC_MASK
149906. DSI1_DISP_DSI_EOT_PACKET__WC__SHIFT
149907. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK
149908. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT
149909. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK
149910. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT
149911. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK
149912. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT
149913. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK
149914. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT
149915. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK
149916. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT
149917. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK
149918. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT
149919. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK
149920. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT
149921. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK
149922. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT
149923. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK
149924. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT
149925. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK
149926. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT
149927. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK
149928. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT
149929. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK
149930. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT
149931. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK
149932. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT
149933. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK
149934. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT
149935. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK
149936. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT
149937. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK
149938. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT
149939. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK
149940. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT
149941. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK
149942. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT
149943. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK
149944. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT
149945. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK
149946. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT
149947. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK
149948. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT
149949. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK
149950. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT
149951. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK
149952. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT
149953. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK
149954. DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT
149955. DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK
149956. DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT
149957. DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK
149958. DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT
149959. DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK
149960. DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT
149961. DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK
149962. DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT
149963. DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK
149964. DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT
149965. DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK
149966. DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT
149967. DSI1_DISP_DSI_EXT_RESET__RESET_PANEL_MASK
149968. DSI1_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT
149969. DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK
149970. DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT
149971. DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK
149972. DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT
149973. DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK
149974. DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT
149975. DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK
149976. DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT
149977. DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK
149978. DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT
149979. DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK
149980. DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT
149981. DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK
149982. DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT
149983. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK
149984. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT
149985. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK
149986. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT
149987. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK
149988. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT
149989. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK
149990. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT
149991. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK
149992. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT
149993. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK
149994. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT
149995. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK
149996. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT
149997. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK
149998. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT
149999. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK
150000. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT
150001. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK
150002. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT
150003. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK
150004. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT
150005. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK
150006. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT
150007. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK
150008. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT
150009. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK
150010. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT
150011. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK
150012. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT
150013. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK
150014. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT
150015. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK
150016. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT
150017. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK
150018. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT
150019. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK
150020. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT
150021. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK
150022. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT
150023. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK
150024. DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT
150025. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK
150026. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT
150027. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK
150028. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT
150029. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK
150030. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT
150031. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK
150032. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT
150033. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK
150034. DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT
150035. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK
150036. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT
150037. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK
150038. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT
150039. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK
150040. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT
150041. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK
150042. DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT
150043. DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK
150044. DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT
150045. DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK
150046. DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT
150047. DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK
150048. DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT
150049. DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK
150050. DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT
150051. DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK
150052. DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT
150053. DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK
150054. DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT
150055. DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK
150056. DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT
150057. DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK
150058. DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT
150059. DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK
150060. DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT
150061. DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK
150062. DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT
150063. DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK
150064. DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT
150065. DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK
150066. DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT
150067. DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK
150068. DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT
150069. DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK
150070. DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT
150071. DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK
150072. DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT
150073. DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK
150074. DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT
150075. DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK
150076. DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT
150077. DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK
150078. DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT
150079. DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK
150080. DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT
150081. DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK
150082. DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT
150083. DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK
150084. DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT
150085. DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK
150086. DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT
150087. DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK
150088. DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT
150089. DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK
150090. DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT
150091. DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK
150092. DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT
150093. DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK
150094. DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT
150095. DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK
150096. DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT
150097. DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK
150098. DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT
150099. DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK
150100. DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT
150101. DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK
150102. DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT
150103. DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK
150104. DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT
150105. DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK
150106. DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT
150107. DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK
150108. DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT
150109. DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK
150110. DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT
150111. DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK
150112. DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT
150113. DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK
150114. DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT
150115. DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK
150116. DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT
150117. DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK
150118. DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT
150119. DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK
150120. DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT
150121. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK
150122. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT
150123. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK
150124. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT
150125. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK
150126. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT
150127. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK
150128. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT
150129. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK
150130. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT
150131. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK
150132. DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT
150133. DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK
150134. DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT
150135. DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK
150136. DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT
150137. DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK
150138. DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT
150139. DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK
150140. DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT
150141. DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK
150142. DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT
150143. DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK
150144. DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT
150145. DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK
150146. DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT
150147. DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK
150148. DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT
150149. DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK
150150. DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT
150151. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK
150152. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT
150153. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK
150154. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT
150155. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK
150156. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT
150157. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK
150158. DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT
150159. DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK
150160. DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT
150161. DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK
150162. DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT
150163. DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK
150164. DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT
150165. DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK
150166. DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT
150167. DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK
150168. DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT
150169. DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK
150170. DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT
150171. DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK
150172. DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT
150173. DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK
150174. DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT
150175. DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK
150176. DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT
150177. DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK
150178. DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT
150179. DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK
150180. DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT
150181. DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK
150182. DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT
150183. DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK
150184. DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT
150185. DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK
150186. DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT
150187. DSI1_DISP_DSI_RDBK_NUM__ALL_NUM_MASK
150188. DSI1_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT
150189. DSI1_DISP_DSI_RDBK_NUM__RD_NUM_MASK
150190. DSI1_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT
150191. DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK
150192. DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT
150193. DSI1_DISP_DSI_STATUS__BTA_BUSY_MASK
150194. DSI1_DISP_DSI_STATUS__BTA_BUSY__SHIFT
150195. DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK
150196. DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT
150197. DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK
150198. DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT
150199. DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK
150200. DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT
150201. DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK
150202. DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT
150203. DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK
150204. DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT
150205. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK
150206. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT
150207. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK
150208. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT
150209. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK
150210. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT
150211. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK
150212. DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT
150213. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK
150214. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT
150215. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK
150216. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT
150217. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK
150218. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT
150219. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK
150220. DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT
150221. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK
150222. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT
150223. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK
150224. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT
150225. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK
150226. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT
150227. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK
150228. DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT
150229. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK
150230. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT
150231. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK
150232. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT
150233. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK
150234. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT
150235. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK
150236. DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT
150237. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK
150238. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT
150239. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK
150240. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT
150241. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK
150242. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT
150243. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK
150244. DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT
150245. DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK
150246. DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT
150247. DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK
150248. DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT
150249. DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK
150250. DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT
150251. DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK
150252. DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT
150253. DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK
150254. DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT
150255. DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK
150256. DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT
150257. DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK
150258. DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT
150259. DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK
150260. DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT
150261. DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK
150262. DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT
150263. DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK
150264. DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT
150265. DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK
150266. DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT
150267. DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK
150268. DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT
150269. DSI1_DISP_DSI_STATUS__TE_ABORT_CLR_MASK
150270. DSI1_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT
150271. DSI1_DISP_DSI_STATUS__TE_ABORT_MASK
150272. DSI1_DISP_DSI_STATUS__TE_ABORT__SHIFT
150273. DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK
150274. DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT
150275. DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK
150276. DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK
150277. DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT
150278. DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT
150279. DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK
150280. DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT
150281. DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK
150282. DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT
150283. DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK
150284. DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT
150285. DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK
150286. DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT
150287. DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK
150288. DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT
150289. DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK
150290. DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT
150291. DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK
150292. DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT
150293. DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK
150294. DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT
150295. DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK
150296. DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT
150297. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK
150298. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT
150299. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK
150300. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT
150301. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK
150302. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT
150303. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK
150304. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT
150305. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK
150306. DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT
150307. DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK
150308. DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT
150309. DSI1_DISP_DSI_TRIG_CTRL__TE_SEL_MASK
150310. DSI1_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT
150311. DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK
150312. DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT
150313. DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK
150314. DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT
150315. DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK
150316. DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT
150317. DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK
150318. DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT
150319. DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK
150320. DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT
150321. DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK
150322. DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT
150323. DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK
150324. DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT
150325. DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK
150326. DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT
150327. DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK
150328. DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT
150329. DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK
150330. DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT
150331. DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK
150332. DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT
150333. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK
150334. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT
150335. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK
150336. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT
150337. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK
150338. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT
150339. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK
150340. DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT
150341. DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK
150342. DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT
150343. DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK
150344. DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT
150345. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK
150346. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT
150347. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK
150348. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK
150349. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT
150350. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT
150351. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK
150352. DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT
150353. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK
150354. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT
150355. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK
150356. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT
150357. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK
150358. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT
150359. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK
150360. DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT
150361. DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK
150362. DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT
150363. DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK
150364. DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT
150365. DSI1_ESC_CLK
150366. DSI1_ESC_SRC
150367. DSI1_HSTX_TO_CNT
150368. DSI1_HS_CLT0
150369. DSI1_HS_CLT1
150370. DSI1_HS_CLT2
150371. DSI1_HS_DLT3
150372. DSI1_HS_DLT4
150373. DSI1_HS_DLT5
150374. DSI1_HS_DLT6
150375. DSI1_HS_DLT7
150376. DSI1_ID
150377. DSI1_INTERRUPTS_ALWAYS_ENABLED
150378. DSI1_INT_EN
150379. DSI1_INT_ERR_CONTROL
150380. DSI1_INT_ERR_CONT_LP0
150381. DSI1_INT_ERR_CONT_LP1
150382. DSI1_INT_ERR_SYNC_ESC
150383. DSI1_INT_FIFO_ERR
150384. DSI1_INT_HSTX_TO
150385. DSI1_INT_LPRX_TO
150386. DSI1_INT_PHY_CLOCK_HS
150387. DSI1_INT_PHY_CLOCK_STOP
150388. DSI1_INT_PHY_CLOCK_ULPS
150389. DSI1_INT_PHY_D0_LPDT
150390. DSI1_INT_PHY_D0_STOP
150391. DSI1_INT_PHY_D0_ULPS
150392. DSI1_INT_PHY_D1_STOP
150393. DSI1_INT_PHY_D1_ULPS
150394. DSI1_INT_PHY_D2_STOP
150395. DSI1_INT_PHY_D2_ULPS
150396. DSI1_INT_PHY_D3_STOP
150397. DSI1_INT_PHY_D3_ULPS
150398. DSI1_INT_PHY_DIR_FTR
150399. DSI1_INT_PHY_DIR_RTF
150400. DSI1_INT_PHY_RXLPDT
150401. DSI1_INT_PHY_RXTRIG
150402. DSI1_INT_PR_TO
150403. DSI1_INT_RXPKT1
150404. DSI1_INT_RXPKT2
150405. DSI1_INT_STAT
150406. DSI1_INT_TA_TO
150407. DSI1_INT_TXPKT1_DONE
150408. DSI1_INT_TXPKT1_END
150409. DSI1_INT_TXPKT2_DONE
150410. DSI1_INT_TXPKT2_END
150411. DSI1_LPRX_TO_CNT
150412. DSI1_PHYC
150413. DSI1_PHYC_CLANE_ENABLE
150414. DSI1_PHYC_CLANE_ULPS
150415. DSI1_PHYC_ESC_CLK_LPDT_MASK
150416. DSI1_PHYC_ESC_CLK_LPDT_SHIFT
150417. DSI1_PHYC_HS_CLK_CONTINUOUS
150418. DSI1_PHY_AFEC0
150419. DSI1_PHY_AFEC0_DDR2CLK_EN
150420. DSI1_PHY_AFEC0_DDRCLK_EN
150421. DSI1_PHY_AFEC0_IDR_CLANE_MASK
150422. DSI1_PHY_AFEC0_IDR_CLANE_SHIFT
150423. DSI1_PHY_AFEC0_IDR_DLANE0_MASK
150424. DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT
150425. DSI1_PHY_AFEC0_IDR_DLANE1_MASK
150426. DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT
150427. DSI1_PHY_AFEC0_IDR_DLANE2_MASK
150428. DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT
150429. DSI1_PHY_AFEC0_IDR_DLANE3_MASK
150430. DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT
150431. DSI1_PHY_AFEC0_LATCH_ULPS
150432. DSI1_PHY_AFEC0_PD
150433. DSI1_PHY_AFEC0_PD_BG
150434. DSI1_PHY_AFEC0_PD_DLANE1
150435. DSI1_PHY_AFEC0_PD_DLANE2
150436. DSI1_PHY_AFEC0_PD_DLANE3
150437. DSI1_PHY_AFEC0_RESET
150438. DSI1_PHY_AFEC1
150439. DSI1_PHY_AFEC1_ACTRL_CLANE_MASK
150440. DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT
150441. DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK
150442. DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT
150443. DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK
150444. DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT
150445. DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK
150446. DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT
150447. DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK
150448. DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT
150449. DSI1_PHY_FIFO_STAT
150450. DSI1_PHY_TST1
150451. DSI1_PHY_TST2
150452. DSI1_PR_TO_CNT
150453. DSI1_REGS_PHYSICAL_BASE
150454. DSI1_RXPKT1H
150455. DSI1_RXPKT2H
150456. DSI1_RXPKT_FIFO
150457. DSI1_SEL_IN_RDMA1
150458. DSI1_SEL_IN_RDMA2
150459. DSI1_STAT
150460. DSI1_STAT_ERR_CONTROL
150461. DSI1_STAT_ERR_CONT_LP0
150462. DSI1_STAT_ERR_CONT_LP1
150463. DSI1_STAT_ERR_SYNC_ESC
150464. DSI1_STAT_FIFO_ERR
150465. DSI1_STAT_HSTX_TO
150466. DSI1_STAT_LPRX_TO
150467. DSI1_STAT_PHY_CLOCK_HS
150468. DSI1_STAT_PHY_CLOCK_STOP
150469. DSI1_STAT_PHY_CLOCK_ULPS
150470. DSI1_STAT_PHY_D0_LPDT
150471. DSI1_STAT_PHY_D0_STOP
150472. DSI1_STAT_PHY_D0_ULPS
150473. DSI1_STAT_PHY_D1_STOP
150474. DSI1_STAT_PHY_D1_ULPS
150475. DSI1_STAT_PHY_D2_STOP
150476. DSI1_STAT_PHY_D2_ULPS
150477. DSI1_STAT_PHY_D3_STOP
150478. DSI1_STAT_PHY_D3_ULPS
150479. DSI1_STAT_PHY_DIR
150480. DSI1_STAT_PHY_RXLPDT
150481. DSI1_STAT_PHY_RXTRIG
150482. DSI1_STAT_PR_TO
150483. DSI1_STAT_RXPKT1
150484. DSI1_STAT_RXPKT2
150485. DSI1_STAT_TA_TO
150486. DSI1_STAT_TXPKT1_BUSY
150487. DSI1_STAT_TXPKT1_DONE
150488. DSI1_STAT_TXPKT1_END
150489. DSI1_STAT_TXPKT2_BUSY
150490. DSI1_STAT_TXPKT2_DONE
150491. DSI1_STAT_TXPKT2_END
150492. DSI1_TA_TO_CNT
150493. DSI1_TST_MON
150494. DSI1_TST_SEL
150495. DSI1_TXPKT1C
150496. DSI1_TXPKT1H
150497. DSI1_TXPKT2C
150498. DSI1_TXPKT2H
150499. DSI1_TXPKT_CMD_FIFO
150500. DSI1_TXPKT_PIX_FIFO
150501. DSI2_BYTE_CLK
150502. DSI2_BYTE_SRC
150503. DSI2_CLK
150504. DSI2_ESC_CLK
150505. DSI2_ESC_SRC
150506. DSI2_M_AHB_CLK
150507. DSI2_M_AHB_RESET
150508. DSI2_PIXEL_CLK
150509. DSI2_PIXEL_SRC
150510. DSI2_REGS_PHYSICAL_BASE
150511. DSI2_RESET
150512. DSI2_SEL_IN_RDMA1
150513. DSI2_SEL_IN_RDMA2
150514. DSI2_SRC
150515. DSI2_S_AHB_CLK
150516. DSI2_S_AHB_RESET
150517. DSI3_SEL_IN_RDMA1
150518. DSI3_SEL_IN_RDMA2
150519. DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY_MASK
150520. DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY__SHIFT
150521. DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY_MASK
150522. DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY__SHIFT
150523. DSIERRCNT
150524. DSIG
150525. DSIM_AFC_CTL
150526. DSIM_AFC_EN
150527. DSIM_AUTO_MODE
150528. DSIM_BTA_TIMEOUT
150529. DSIM_BURST_MODE
150530. DSIM_BYTE_CLKEN
150531. DSIM_BYTE_CLK_SRC
150532. DSIM_BYTE_CLK_SRC_MASK
150533. DSIM_CLKCTRL_REG
150534. DSIM_CLKLANE_STOP
150535. DSIM_CMD_ALLOW
150536. DSIM_CMD_ALLOW_MASK
150537. DSIM_CMD_LPDT_LP
150538. DSIM_CONFIG_REG
150539. DSIM_EOT_DISABLE
150540. DSIM_ESCMODE_REG
150541. DSIM_ESC_CLKEN
150542. DSIM_ESC_PRESCALER
150543. DSIM_ESC_PRESCALER_MASK
150544. DSIM_FIFOCTRL_REG
150545. DSIM_FORCE_BTA
150546. DSIM_FORCE_STOP_STATE
150547. DSIM_FREQ_BAND
150548. DSIM_FUNCRST
150549. DSIM_HBP_MODE
150550. DSIM_HFP_MODE
150551. DSIM_HSA_MODE
150552. DSIM_HSE_MODE
150553. DSIM_I80_FIFO
150554. DSIM_I80_HEADER_EMPTY
150555. DSIM_I80_HEADER_FULL
150556. DSIM_I80_PAYLOAD_EMPTY
150557. DSIM_I80_PAYLOAD_FULL
150558. DSIM_INTMSK_REG
150559. DSIM_INTSRC_REG
150560. DSIM_INT_BTA
150561. DSIM_INT_BTA_TIMEOUT
150562. DSIM_INT_FRAME_DONE
150563. DSIM_INT_PLL_STABLE
150564. DSIM_INT_RX_ACK
150565. DSIM_INT_RX_CRC_ERR
150566. DSIM_INT_RX_DONE
150567. DSIM_INT_RX_ECC_ERR
150568. DSIM_INT_RX_TE
150569. DSIM_INT_RX_TIMEOUT
150570. DSIM_INT_SFR_FIFO_EMPTY
150571. DSIM_INT_SFR_HDR_FIFO_EMPTY
150572. DSIM_INT_SW_RST_RELEASE
150573. DSIM_LANE_EN
150574. DSIM_LANE_EN_CLK
150575. DSIM_LANE_ESC_CLK_EN_CLK
150576. DSIM_LANE_ESC_CLK_EN_DATA
150577. DSIM_LANE_ESC_CLK_EN_DATA_MASK
150578. DSIM_LPDR_TIMEOUT
150579. DSIM_MAIN_HBP
150580. DSIM_MAIN_HBP_MASK
150581. DSIM_MAIN_HFP
150582. DSIM_MAIN_HFP_MASK
150583. DSIM_MAIN_HRESOL
150584. DSIM_MAIN_HSA
150585. DSIM_MAIN_HSA_MASK
150586. DSIM_MAIN_PIX_FORMAT_MASK
150587. DSIM_MAIN_PIX_FORMAT_RGB565
150588. DSIM_MAIN_PIX_FORMAT_RGB666
150589. DSIM_MAIN_PIX_FORMAT_RGB666_P
150590. DSIM_MAIN_PIX_FORMAT_RGB888
150591. DSIM_MAIN_STAND_BY
150592. DSIM_MAIN_VBP
150593. DSIM_MAIN_VBP_MASK
150594. DSIM_MAIN_VC
150595. DSIM_MAIN_VRESOL
150596. DSIM_MAIN_VSA
150597. DSIM_MAIN_VSA_MASK
150598. DSIM_MDRESOL_REG
150599. DSIM_MD_FIFO
150600. DSIM_MD_HEADER_EMPTY
150601. DSIM_MD_HEADER_FULL
150602. DSIM_MD_PAYLOAD_EMPTY
150603. DSIM_MD_PAYLOAD_FULL
150604. DSIM_MFLUSH_VS
150605. DSIM_MHPORCH_REG
150606. DSIM_MSYNC_REG
150607. DSIM_MVPORCH_REG
150608. DSIM_NUM_OF_DATA_LANE
150609. DSIM_PAYLOAD_REG
150610. DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP
150611. DSIM_PHYCTRL_B_DPHYCTL_VREG_LP
150612. DSIM_PHYCTRL_REG
150613. DSIM_PHYCTRL_ULPS_EXIT
150614. DSIM_PHYTIMING1_CLK_POST
150615. DSIM_PHYTIMING1_CLK_PREPARE
150616. DSIM_PHYTIMING1_CLK_TRAIL
150617. DSIM_PHYTIMING1_CLK_ZERO
150618. DSIM_PHYTIMING1_REG
150619. DSIM_PHYTIMING2_HS_PREPARE
150620. DSIM_PHYTIMING2_HS_TRAIL
150621. DSIM_PHYTIMING2_HS_ZERO
150622. DSIM_PHYTIMING2_REG
150623. DSIM_PHYTIMING_HS_EXIT
150624. DSIM_PHYTIMING_LPX
150625. DSIM_PHYTIMING_REG
150626. DSIM_PKTHDR_REG
150627. DSIM_PLLCTRL_REG
150628. DSIM_PLL_BYPASS
150629. DSIM_PLL_EN
150630. DSIM_PLL_M
150631. DSIM_PLL_P
150632. DSIM_PLL_S
150633. DSIM_PLL_STABLE
150634. DSIM_RXFIFO_REG
150635. DSIM_RX_DATA_EMPTY
150636. DSIM_RX_DATA_FULL
150637. DSIM_RX_FIFO
150638. DSIM_SD_FIFO
150639. DSIM_SD_HEADER_EMPTY
150640. DSIM_SD_HEADER_FULL
150641. DSIM_SD_PAYLOAD_EMPTY
150642. DSIM_SD_PAYLOAD_FULL
150643. DSIM_SFR_FIFO
150644. DSIM_SFR_HEADER_EMPTY
150645. DSIM_SFR_HEADER_FULL
150646. DSIM_SFR_PAYLOAD_EMPTY
150647. DSIM_SFR_PAYLOAD_FULL
150648. DSIM_STABLE_VFP
150649. DSIM_STABLE_VFP_MASK
150650. DSIM_STATE_CMD_LPM
150651. DSIM_STATE_ENABLED
150652. DSIM_STATE_INITIALIZED
150653. DSIM_STATE_VIDOUT_AVAILABLE
150654. DSIM_STATUS_REG
150655. DSIM_STOP_STATE_CLK
150656. DSIM_STOP_STATE_CNT
150657. DSIM_STOP_STATE_CNT_MASK
150658. DSIM_STOP_STATE_DAT
150659. DSIM_SUB_HRESOL
150660. DSIM_SUB_HRESOL_MASK
150661. DSIM_SUB_PIX_FORMAT
150662. DSIM_SUB_STANDY
150663. DSIM_SUB_STANDY_MASK
150664. DSIM_SUB_VC
150665. DSIM_SUB_VRESOL
150666. DSIM_SUB_VRESOL_MASK
150667. DSIM_SWRST
150668. DSIM_SWRST_REG
150669. DSIM_SYNC_INFORM
150670. DSIM_TIMEOUT_REG
150671. DSIM_TX_LPDT_LP
150672. DSIM_TX_READY_HS_CLK
150673. DSIM_TX_REQUEST_HSCLK
150674. DSIM_TX_TRIGGER_RST
150675. DSIM_VIDEO_MODE
150676. DSISIGMOD
150677. DSISR_ATTR_CONFLICT
150678. DSISR_BADACCESS
150679. DSISR_BAD_AMO
150680. DSISR_BAD_CI_LDST
150681. DSISR_BAD_COPYPASTE
150682. DSISR_BAD_DIRECT_ST
150683. DSISR_BAD_EXT_CTRL
150684. DSISR_BAD_FAULT_32S
150685. DSISR_BAD_FAULT_64S
150686. DSISR_DABRMATCH
150687. DSISR_FLAGS
150688. DSISR_ICSWX_NO_CT
150689. DSISR_ISSTORE
150690. DSISR_KEYFAULT
150691. DSISR_MC_DERAT_MULTI
150692. DSISR_MC_SLB_MULTI
150693. DSISR_MC_SLB_PARITY
150694. DSISR_MC_SLB_PARMULTI
150695. DSISR_MC_TLB_MULTI
150696. DSISR_NOEXEC_OR_G
150697. DSISR_NOHPTE
150698. DSISR_NOSEGMENT
150699. DSISR_PROTFAULT
150700. DSISR_PRTABLE_FAULT
150701. DSISR_SET_RC
150702. DSISR_SRR1_MATCH_32S
150703. DSISR_SRR1_MATCH_64S
150704. DSISR_UNSUPP_MMU
150705. DSIUINTREG
150706. DSIUINT_ALL
150707. DSIUINT_CTS
150708. DSIUINT_RX
150709. DSIUINT_RXERR
150710. DSIUINT_TX
150711. DSIU_CLOCK
150712. DSIU_IRQ
150713. DSIZE
150714. DSI_0
150715. DSI_1
150716. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0
150717. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK
150718. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT
150719. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4
150720. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK
150721. DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT
150722. DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL
150723. DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL
150724. DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL
150725. DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK
150726. DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT
150727. DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START
150728. DSI_14nm_PHY_LN_CFG0_PREPARE_DLY
150729. DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK
150730. DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT
150731. DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN
150732. DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET
150733. DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK
150734. DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT
150735. DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD
150736. DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK
150737. DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT
150738. DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT
150739. DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK
150740. DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT
150741. DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO
150742. DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK
150743. DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT
150744. DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE
150745. DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK
150746. DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT
150747. DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL
150748. DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK
150749. DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT
150750. DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST
150751. DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK
150752. DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT
150753. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO
150754. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK
150755. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT
150756. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE
150757. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK
150758. DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT
150759. DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL
150760. DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO
150761. DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK
150762. DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT
150763. DSI_20nm_PHY_TIMING_CTRL_10_TA_GET
150764. DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK
150765. DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT
150766. DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD
150767. DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK
150768. DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT
150769. DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL
150770. DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK
150771. DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT
150772. DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE
150773. DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK
150774. DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT
150775. DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8
150776. DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT
150777. DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK
150778. DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT
150779. DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO
150780. DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK
150781. DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT
150782. DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE
150783. DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK
150784. DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT
150785. DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL
150786. DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK
150787. DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT
150788. DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST
150789. DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK
150790. DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT
150791. DSI_20nm_PHY_TIMING_CTRL_9_TA_GO
150792. DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK
150793. DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT
150794. DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE
150795. DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK
150796. DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT
150797. DSI_24BITS_1
150798. DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY
150799. DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE
150800. DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY
150801. DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO
150802. DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK
150803. DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT
150804. DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET
150805. DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK
150806. DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT
150807. DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD
150808. DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK
150809. DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT
150810. DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL
150811. DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK
150812. DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT
150813. DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE
150814. DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK
150815. DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT
150816. DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT
150817. DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK
150818. DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT
150819. DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO
150820. DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK
150821. DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT
150822. DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE
150823. DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK
150824. DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT
150825. DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL
150826. DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK
150827. DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT
150828. DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST
150829. DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK
150830. DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT
150831. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO
150832. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK
150833. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT
150834. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE
150835. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK
150836. DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT
150837. DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL
150838. DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE
150839. DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B
150840. DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B
150841. DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B
150842. DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR
150843. DSI_28nm_PHY_PLL_SDM_CFG0_BYP
150844. DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV
150845. DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK
150846. DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT
150847. DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET
150848. DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK
150849. DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT
150850. DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN
150851. DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK
150852. DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT
150853. DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0
150854. DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK
150855. DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT
150856. DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8
150857. DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK
150858. DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT
150859. DSI_28nm_PHY_PLL_STATUS_PLL_RDY
150860. DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET
150861. DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B
150862. DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO
150863. DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK
150864. DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT
150865. DSI_28nm_PHY_TIMING_CTRL_10_TA_GET
150866. DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK
150867. DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT
150868. DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD
150869. DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK
150870. DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT
150871. DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL
150872. DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK
150873. DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT
150874. DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE
150875. DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK
150876. DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT
150877. DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8
150878. DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT
150879. DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK
150880. DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT
150881. DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO
150882. DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK
150883. DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT
150884. DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE
150885. DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK
150886. DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT
150887. DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL
150888. DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK
150889. DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT
150890. DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST
150891. DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK
150892. DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT
150893. DSI_28nm_PHY_TIMING_CTRL_9_TA_GO
150894. DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK
150895. DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT
150896. DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE
150897. DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK
150898. DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT
150899. DSI_6G_HW_VERSION_MAJOR
150900. DSI_6G_HW_VERSION_MAJOR__MASK
150901. DSI_6G_HW_VERSION_MAJOR__SHIFT
150902. DSI_6G_HW_VERSION_MINOR
150903. DSI_6G_HW_VERSION_MINOR__MASK
150904. DSI_6G_HW_VERSION_MINOR__SHIFT
150905. DSI_6G_HW_VERSION_STEP
150906. DSI_6G_HW_VERSION_STEP__MASK
150907. DSI_6G_HW_VERSION_STEP__SHIFT
150908. DSI_6G_REG_SHIFT
150909. DSI_8x60_PHY_CAL_STATUS_CAL_BUSY
150910. DSI_ACTIVE_HSYNC_END
150911. DSI_ACTIVE_HSYNC_END__MASK
150912. DSI_ACTIVE_HSYNC_END__SHIFT
150913. DSI_ACTIVE_HSYNC_START
150914. DSI_ACTIVE_HSYNC_START__MASK
150915. DSI_ACTIVE_HSYNC_START__SHIFT
150916. DSI_ACTIVE_H_END
150917. DSI_ACTIVE_H_END__MASK
150918. DSI_ACTIVE_H_END__SHIFT
150919. DSI_ACTIVE_H_START
150920. DSI_ACTIVE_H_START__MASK
150921. DSI_ACTIVE_H_START__SHIFT
150922. DSI_ACTIVE_VSYNC_HPOS_END
150923. DSI_ACTIVE_VSYNC_HPOS_END__MASK
150924. DSI_ACTIVE_VSYNC_HPOS_END__SHIFT
150925. DSI_ACTIVE_VSYNC_HPOS_START
150926. DSI_ACTIVE_VSYNC_HPOS_START__MASK
150927. DSI_ACTIVE_VSYNC_HPOS_START__SHIFT
150928. DSI_ACTIVE_VSYNC_VPOS_END
150929. DSI_ACTIVE_VSYNC_VPOS_END__MASK
150930. DSI_ACTIVE_VSYNC_VPOS_END__SHIFT
150931. DSI_ACTIVE_VSYNC_VPOS_START
150932. DSI_ACTIVE_VSYNC_VPOS_START__MASK
150933. DSI_ACTIVE_VSYNC_VPOS_START__SHIFT
150934. DSI_ACTIVE_V_END
150935. DSI_ACTIVE_V_END__MASK
150936. DSI_ACTIVE_V_END__SHIFT
150937. DSI_ACTIVE_V_START
150938. DSI_ACTIVE_V_START__MASK
150939. DSI_ACTIVE_V_START__SHIFT
150940. DSI_BIT_SWAP
150941. DSI_BIT_SWAP_DISABLE
150942. DSI_BIT_SWAP_ENABLE
150943. DSI_BLANKING_FRAME_OVERHEAD
150944. DSI_BTACLR
150945. DSI_BTASTA
150946. DSI_BTA_TIMING
150947. DSI_BTA_TO_CNT
150948. DSI_BURST_SYNC_PULSES_1
150949. DSI_BURST_SYNC_PULSES_2
150950. DSI_BUSY
150951. DSI_BUSYDSI
150952. DSI_BUS_CLK_MAX
150953. DSI_BYTE_PLL_CLK
150954. DSI_CATCH_MISSING_TE
150955. DSI_CIO_IRQ_ERRCONTENTIONLP0_1
150956. DSI_CIO_IRQ_ERRCONTENTIONLP0_2
150957. DSI_CIO_IRQ_ERRCONTENTIONLP0_3
150958. DSI_CIO_IRQ_ERRCONTENTIONLP0_4
150959. DSI_CIO_IRQ_ERRCONTENTIONLP0_5
150960. DSI_CIO_IRQ_ERRCONTENTIONLP1_1
150961. DSI_CIO_IRQ_ERRCONTENTIONLP1_2
150962. DSI_CIO_IRQ_ERRCONTENTIONLP1_3
150963. DSI_CIO_IRQ_ERRCONTENTIONLP1_4
150964. DSI_CIO_IRQ_ERRCONTENTIONLP1_5
150965. DSI_CIO_IRQ_ERRCONTROL1
150966. DSI_CIO_IRQ_ERRCONTROL2
150967. DSI_CIO_IRQ_ERRCONTROL3
150968. DSI_CIO_IRQ_ERRCONTROL4
150969. DSI_CIO_IRQ_ERRCONTROL5
150970. DSI_CIO_IRQ_ERRESC1
150971. DSI_CIO_IRQ_ERRESC2
150972. DSI_CIO_IRQ_ERRESC3
150973. DSI_CIO_IRQ_ERRESC4
150974. DSI_CIO_IRQ_ERRESC5
150975. DSI_CIO_IRQ_ERROR_MASK
150976. DSI_CIO_IRQ_ERRSYNCESC1
150977. DSI_CIO_IRQ_ERRSYNCESC2
150978. DSI_CIO_IRQ_ERRSYNCESC3
150979. DSI_CIO_IRQ_ERRSYNCESC4
150980. DSI_CIO_IRQ_ERRSYNCESC5
150981. DSI_CIO_IRQ_STATEULPS1
150982. DSI_CIO_IRQ_STATEULPS2
150983. DSI_CIO_IRQ_STATEULPS3
150984. DSI_CIO_IRQ_STATEULPS4
150985. DSI_CIO_IRQ_STATEULPS5
150986. DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
150987. DSI_CIO_IRQ_ULPSACTIVENOT_ALL1
150988. DSI_CK
150989. DSI_CLK
150990. DSI_CLKMGR_CFG
150991. DSI_CLKOUT_TIMING_CTRL_T_CLK_POST
150992. DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK
150993. DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT
150994. DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE
150995. DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK
150996. DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT
150997. DSI_CLK_CTRL
150998. DSI_CLK_CTRL_AHBM_SCLK_ON
150999. DSI_CLK_CTRL_AHBS_HCLK_ON
151000. DSI_CLK_CTRL_BYTECLK_ON
151001. DSI_CLK_CTRL_DSICLK_ON
151002. DSI_CLK_CTRL_ENABLE_CLKS
151003. DSI_CLK_CTRL_ESCCLK_ON
151004. DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK
151005. DSI_CLK_CTRL_PCLK_ON
151006. DSI_CLK_GATING
151007. DSI_CLK_GATING_DISABLE
151008. DSI_CLK_GATING_ENABLE
151009. DSI_CLK_STATUS_PLL_UNLOCKED
151010. DSI_CLK_TIMING
151011. DSI_CLK_TIMING_PARAM
151012. DSI_CLOCK_LANE_DISABLE
151013. DSI_CLOCK_LANE_EN
151014. DSI_CLOCK_LANE_ENABLE
151015. DSI_CLOCK_LANE_HS_FORCE_REQUEST
151016. DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT
151017. DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT
151018. DSI_CLOCK_MASTER
151019. DSI_CLOCK_SLAVE
151020. DSI_CMD2BK0_SEL
151021. DSI_CMD2BK1_SEL
151022. DSI_CMD2BKX_SEL
151023. DSI_CMD2BKX_SEL_NONE
151024. DSI_CMD2_BK0_INVSEL
151025. DSI_CMD2_BK0_INVSEL_B0
151026. DSI_CMD2_BK0_INVSEL_B1
151027. DSI_CMD2_BK0_LNESET
151028. DSI_CMD2_BK0_LNESET_B0
151029. DSI_CMD2_BK0_LNESET_B1
151030. DSI_CMD2_BK0_NVGAMCTRL
151031. DSI_CMD2_BK0_PORCTRL
151032. DSI_CMD2_BK0_PORCTRL_B0
151033. DSI_CMD2_BK0_PORCTRL_B1
151034. DSI_CMD2_BK0_PVGAMCTRL
151035. DSI_CMD2_BK1_MIPISET1
151036. DSI_CMD2_BK1_MIPISET1_SET
151037. DSI_CMD2_BK1_PWCTLR1
151038. DSI_CMD2_BK1_PWCTLR1_SET
151039. DSI_CMD2_BK1_PWCTLR2
151040. DSI_CMD2_BK1_PWCTLR2_SET
151041. DSI_CMD2_BK1_SPD1
151042. DSI_CMD2_BK1_SPD1_SET
151043. DSI_CMD2_BK1_SPD2
151044. DSI_CMD2_BK1_SPD2_SET
151045. DSI_CMD2_BK1_TESTCMD
151046. DSI_CMD2_BK1_TESTCMD_VAL
151047. DSI_CMD2_BK1_VCOM
151048. DSI_CMD2_BK1_VCOM_SET
151049. DSI_CMD2_BK1_VGHSS
151050. DSI_CMD2_BK1_VGHSS_SET
151051. DSI_CMD2_BK1_VGLS
151052. DSI_CMD2_BK1_VGLS_SET
151053. DSI_CMD2_BK1_VRHA_SET
151054. DSI_CMD2_BK1_VRHS
151055. DSI_CMDQ0
151056. DSI_CMDQ_SIZE
151057. DSI_CMD_CFG0_B_SEL
151058. DSI_CMD_CFG0_DST_FORMAT
151059. DSI_CMD_CFG0_DST_FORMAT__MASK
151060. DSI_CMD_CFG0_DST_FORMAT__SHIFT
151061. DSI_CMD_CFG0_G_SEL
151062. DSI_CMD_CFG0_INTERLEAVE_MAX
151063. DSI_CMD_CFG0_INTERLEAVE_MAX__MASK
151064. DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT
151065. DSI_CMD_CFG0_RGB_SWAP
151066. DSI_CMD_CFG0_RGB_SWAP__MASK
151067. DSI_CMD_CFG0_RGB_SWAP__SHIFT
151068. DSI_CMD_CFG0_R_SEL
151069. DSI_CMD_CFG1_INSERT_DCS_COMMAND
151070. DSI_CMD_CFG1_WR_MEM_CONTINUE
151071. DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK
151072. DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT
151073. DSI_CMD_CFG1_WR_MEM_START
151074. DSI_CMD_CFG1_WR_MEM_START__MASK
151075. DSI_CMD_CFG1_WR_MEM_START__SHIFT
151076. DSI_CMD_DMA_CTRL_BROADCAST_EN
151077. DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER
151078. DSI_CMD_DMA_CTRL_LOW_POWER
151079. DSI_CMD_EMBEDDED_MODE
151080. DSI_CMD_FIFO_DEPTH
151081. DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE
151082. DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK
151083. DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT
151084. DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL
151085. DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK
151086. DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT
151087. DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT
151088. DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK
151089. DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT
151090. DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL
151091. DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK
151092. DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT
151093. DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL
151094. DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK
151095. DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT
151096. DSI_CMD_MODE_CFG
151097. DSI_CMD_MODE_CTL
151098. DSI_CMD_MODE_CTL_ARB_MODE
151099. DSI_CMD_MODE_CTL_ARB_PRI
151100. DSI_CMD_MODE_CTL_FIL_VALUE_MASK
151101. DSI_CMD_MODE_CTL_FIL_VALUE_SHIFT
151102. DSI_CMD_MODE_CTL_IF1_ID_MASK
151103. DSI_CMD_MODE_CTL_IF1_ID_SHIFT
151104. DSI_CMD_MODE_CTL_IF1_LP_EN
151105. DSI_CMD_MODE_CTL_IF2_ID_MASK
151106. DSI_CMD_MODE_CTL_IF2_ID_SHIFT
151107. DSI_CMD_MODE_CTL_IF2_LP_EN
151108. DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK
151109. DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT
151110. DSI_CMD_MODE_DISABLE
151111. DSI_CMD_MODE_EN
151112. DSI_CMD_MODE_ENABLE
151113. DSI_CMD_MODE_STS
151114. DSI_CMD_MODE_STS_CLR
151115. DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR
151116. DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR
151117. DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR
151118. DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR
151119. DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR
151120. DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR
151121. DSI_CMD_MODE_STS_CSM_RUNNING
151122. DSI_CMD_MODE_STS_CTL
151123. DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE
151124. DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN
151125. DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE
151126. DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN
151127. DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE
151128. DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN
151129. DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE
151130. DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN
151131. DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE
151132. DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN
151133. DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE
151134. DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN
151135. DSI_CMD_MODE_STS_ERR_NO_TE
151136. DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN
151137. DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN
151138. DSI_CMD_MODE_STS_ERR_TE_MISS
151139. DSI_CMD_MODE_STS_ERR_UNWANTED_RD
151140. DSI_CMD_MODE_STS_FLAG
151141. DSI_CMD_ORDER
151142. DSI_CMD_ORDER_COMMAND_FIRST
151143. DSI_CMD_ORDER_DATA_FIRST
151144. DSI_CMD_PACKET_TYPE
151145. DSI_CMD_PACKET_TYPE_LONG
151146. DSI_CMD_PACKET_TYPE_SHORT
151147. DSI_CMD_PKT_STATUS
151148. DSI_CMD_PWR_MODE
151149. DSI_CMD_PWR_MODE_HS
151150. DSI_CMD_PWR_MODE_LP
151151. DSI_CMD_RXCTL
151152. DSI_CMD_TXCTL
151153. DSI_CMD_TXHDR
151154. DSI_CMD_TXPYLD
151155. DSI_CMD_USE_CMDFIFO
151156. DSI_CMD_USE_DMAFIFO
151157. DSI_CN
151158. DSI_COMMAND_DST_FORMAT_RGB111
151159. DSI_COMMAND_DST_FORMAT_RGB332
151160. DSI_COMMAND_DST_FORMAT_RGB444
151161. DSI_COMMAND_DST_FORMAT_RGB565
151162. DSI_COMMAND_DST_FORMAT_RGB666
151163. DSI_COMMAND_DST_FORMAT_RGB888
151164. DSI_COMMAND_MODE
151165. DSI_COMMAND_MODE_DST_FORMAT
151166. DSI_COMMAND_MODE_SRC_FORMAT
151167. DSI_COMMAND_SRC_FORMAT_RGB332
151168. DSI_COMMAND_SRC_FORMAT_RGB444
151169. DSI_COMMAND_SRC_FORMAT_RGB555
151170. DSI_COMMAND_SRC_FORMAT_RGB565
151171. DSI_COMMAND_SRC_FORMAT_RGB888
151172. DSI_COMMAND_SRC_FORMAT_RGB8BIT
151173. DSI_COMMAND_TRIGGER_MODE
151174. DSI_COMMAND_TRIGGER_MODE_AUTO
151175. DSI_COMMAND_TRIGGER_MODE_MANUAL
151176. DSI_COMMAND_TRIGGER_ORDER
151177. DSI_COMMAND_TRIGGER_ORDER_DENG
151178. DSI_COMMAND_TRIGGER_ORDER_DMA
151179. DSI_COMMAND_TRIGGER_SEL
151180. DSI_COMMAND_TRIGGER_SEL_CRTC
151181. DSI_COMMAND_TRIGGER_SEL_HW
151182. DSI_COMMAND_TRIGGER_SEL_NONE
151183. DSI_COMMAND_TRIGGER_SEL_TE
151184. DSI_COMPLEXIO_CFG1
151185. DSI_COMPLEXIO_CFG2
151186. DSI_COMPLEXIO_IRQ_ENABLE
151187. DSI_COMPLEXIO_IRQ_STATUS
151188. DSI_COMPLEXIO_POWER_OFF
151189. DSI_COMPLEXIO_POWER_ON
151190. DSI_COMPLEXIO_POWER_ULPS
151191. DSI_CONTROL
151192. DSI_CONTROLLER_DISABLE
151193. DSI_CONTROLLER_EN
151194. DSI_CONTROLLER_ENABLE
151195. DSI_CONTROL_CHANNEL
151196. DSI_CONTROL_DCS_ENABLE
151197. DSI_CONTROL_FORMAT
151198. DSI_CONTROL_HOST_ENABLE
151199. DSI_CONTROL_HS_CLK_CTRL
151200. DSI_CONTROL_LANES
151201. DSI_CONTROL_SOURCE
151202. DSI_CONTROL_TX_TRIG
151203. DSI_CONTROL_VIDEO_ENABLE
151204. DSI_CON_CTRL
151205. DSI_CP
151206. DSI_CPU_CMD_0
151207. DSI_CPU_CMD_1
151208. DSI_CPU_CMD_1_CFG_TXLP_LPDT_MASK
151209. DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT
151210. DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_MASK
151211. DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT
151212. DSI_CPU_CMD_1_CFG_TXLP_ULPS_MASK
151213. DSI_CPU_CMD_1_CFG_TXLP_ULPS_SHIFT
151214. DSI_CPU_CMD_3
151215. DSI_CPU_WDAT_0
151216. DSI_CRC_CAL_DISABLE
151217. DSI_CRC_CAL_ENABLE
151218. DSI_CRC_ENABLE
151219. DSI_CRTC_FREEZE_TRIG
151220. DSI_CRTC_FREEZE_TRIG_ASSERT
151221. DSI_CRTC_FREEZE_TRIG_DEASSERT
151222. DSI_CRTC_SEL
151223. DSI_CTRL
151224. DSI_CTRL_0
151225. DSI_CTRL_0_CFG_LCD1_EN
151226. DSI_CTRL_0_CFG_LCD1_SLV
151227. DSI_CTRL_0_CFG_LCD1_TX_EN
151228. DSI_CTRL_0_CFG_SOFT_RST
151229. DSI_CTRL_0_CFG_SOFT_RST_REG
151230. DSI_CTRL_1
151231. DSI_CTRL_1_CFG_EOTP
151232. DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK
151233. DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT
151234. DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK
151235. DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT
151236. DSI_CTRL_1_CFG_RSVD
151237. DSI_CTRL_CAL_BYTE
151238. DSI_CTRL_CLK_EN
151239. DSI_CTRL_CLR_LDF
151240. DSI_CTRL_CMD_MODE_EN
151241. DSI_CTRL_CRC_CHECK
151242. DSI_CTRL_ECC_CHECK
151243. DSI_CTRL_ENABLE
151244. DSI_CTRL_HSDT_EOT_DISABLE
151245. DSI_CTRL_HS_CLKC_BYTE
151246. DSI_CTRL_HS_CLKC_DDR
151247. DSI_CTRL_HS_CLKC_DDR2
151248. DSI_CTRL_HS_CLKC_MASK
151249. DSI_CTRL_HS_CLKC_SHIFT
151250. DSI_CTRL_INV_BYTE
151251. DSI_CTRL_LANE0
151252. DSI_CTRL_LANE1
151253. DSI_CTRL_LANE2
151254. DSI_CTRL_LANE3
151255. DSI_CTRL_LPDT_EOT_DISABLE
151256. DSI_CTRL_RX_LPDT_EOT_DISABLE
151257. DSI_CTRL_SOFT_RESET_CFG
151258. DSI_CTRL_VID_MODE_EN
151259. DSI_CTXSW
151260. DSI_DATA_BUFFER_ID
151261. DSI_DATA_BUFFER_OFFSET0
151262. DSI_DATA_BUFFER_OFFSET1
151263. DSI_DATA_LANE0_DISABLE
151264. DSI_DATA_LANE0_EN
151265. DSI_DATA_LANE0_ENABLE
151266. DSI_DATA_LANE1_DISABLE
151267. DSI_DATA_LANE1_EN
151268. DSI_DATA_LANE1_ENABLE
151269. DSI_DATA_LANE2_DISABLE
151270. DSI_DATA_LANE2_EN
151271. DSI_DATA_LANE2_ENABLE
151272. DSI_DATA_LANE3_DISABLE
151273. DSI_DATA_LANE3_EN
151274. DSI_DATA_LANE3_ENABLE
151275. DSI_DATA_TIMING_PARAM
151276. DSI_DBG_CLK_SEL
151277. DSI_DBI_CFG
151278. DSI_DBI_CMDSIZE
151279. DSI_DBI_COLOR_FORMAT_OPTION2
151280. DSI_DBI_FIFO_WM_HALF
151281. DSI_DBI_FIFO_WM_LOW
151282. DSI_DBI_FIFO_WM_QUARTER
151283. DSI_DBI_HS_LP_SWITCH_MASK
151284. DSI_DBI_PARTITIONING_EN
151285. DSI_DBI_RETURN_PACK_SIZE_MASK
151286. DSI_DBI_VCID
151287. DSI_DBI_VIRT_CHANNEL_OFFSET
151288. DSI_DCS_CMDS
151289. DSI_DEBUG_BYTECLK_SEL
151290. DSI_DEBUG_BYTECLK_SEL_AFIFO
151291. DSI_DEBUG_BYTECLK_SEL_EOT
151292. DSI_DEBUG_BYTECLK_SEL_LANEBUF0
151293. DSI_DEBUG_BYTECLK_SEL_LANEBUF1
151294. DSI_DEBUG_BYTECLK_SEL_LANEBUF2
151295. DSI_DEBUG_BYTECLK_SEL_LANEBUF3
151296. DSI_DEBUG_BYTECLK_SEL_LANECTRL
151297. DSI_DEBUG_BYTECLK_SEL_LANEFIFO0
151298. DSI_DEBUG_BYTECLK_SEL_LANEFIFO1
151299. DSI_DEBUG_BYTECLK_SEL_LANEFIFO2
151300. DSI_DEBUG_BYTECLK_SEL_LANEFIFO3
151301. DSI_DEBUG_BYTECLK_SEL_PINGPING2
151302. DSI_DEBUG_BYTECLK_SEL_PINGPING3
151303. DSI_DEBUG_BYTECLK_SEL_PINGPONG0
151304. DSI_DEBUG_BYTECLK_SEL_PINGPONG1
151305. DSI_DEBUG_DSICLK_SEL
151306. DSI_DEBUG_DSICLK_SEL_AFIFO
151307. DSI_DEBUG_DSICLK_SEL_CMDBUFFER
151308. DSI_DEBUG_DSICLK_SEL_CMDFIFO
151309. DSI_DEBUG_DSICLK_SEL_CMD_ENGINE
151310. DSI_DEBUG_DSICLK_SEL_LANECTRL
151311. DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO
151312. DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE
151313. DSI_DEFAULT_HS_FREQ_HZ
151314. DSI_DEFAULT_LP_FREQ_HZ
151315. DSI_DENG_FIFO_FORCE_RECAL_AVERAGE
151316. DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT
151317. DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT
151318. DSI_DENG_FIFO_FORCE_RECOMP_MINMAX
151319. DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT
151320. DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT
151321. DSI_DENG_FIFO_LEVEL_CAL_AVERAGE
151322. DSI_DENG_FIFO_LEVEL_OVERWRITE
151323. DSI_DENG_FIFO_START
151324. DSI_DENG_FIFO_START_ASSERT
151325. DSI_DENG_FIFO_START_DEASSERT
151326. DSI_DENG_FIFO_USE_OVERWRITE_LEVEL
151327. DSI_DEVICE_READY
151328. DSI_DEV_NAME_SIZE
151329. DSI_DEV_REGULATOR_MAX
151330. DSI_DIRECT_CMD_MAIN_SETTINGS
151331. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_LONG_WRITE
151332. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_READ
151333. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_0
151334. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_1
151335. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_GENERIC_LONG_WRITE
151336. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_GENERIC_SHORT_WRITE_0
151337. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_GENERIC_SHORT_WRITE_1
151338. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_GENERIC_SHORT_WRITE_2
151339. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK
151340. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SET_MAX_PKT_SIZE
151341. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT
151342. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHUT_DOWN_PERIPHERAL
151343. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_TURN_ON_PERIPHERAL
151344. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT
151345. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT
151346. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN
151347. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_BTA_REQ
151348. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK
151349. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ
151350. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT
151351. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ
151352. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TRIG_REQ
151353. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE
151354. DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT
151355. DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK
151356. DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_SHIFT
151357. DSI_DIRECT_CMD_RDDAT
151358. DSI_DIRECT_CMD_RD_INIT
151359. DSI_DIRECT_CMD_RD_INIT_RESET_MASK
151360. DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT
151361. DSI_DIRECT_CMD_RD_PROPERTY
151362. DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK
151363. DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_SHIFT
151364. DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK
151365. DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_SHIFT
151366. DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK
151367. DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT
151368. DSI_DIRECT_CMD_RD_STS
151369. DSI_DIRECT_CMD_RD_STS_CLR
151370. DSI_DIRECT_CMD_RD_STS_FLAG
151371. DSI_DIRECT_CMD_SEND
151372. DSI_DIRECT_CMD_STS
151373. DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT
151374. DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED
151375. DSI_DIRECT_CMD_STS_ACK_VAL_MASK
151376. DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT
151377. DSI_DIRECT_CMD_STS_BTA_COMPLETED
151378. DSI_DIRECT_CMD_STS_BTA_FINISHED
151379. DSI_DIRECT_CMD_STS_CLR
151380. DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR
151381. DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR
151382. DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR
151383. DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR
151384. DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR
151385. DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR
151386. DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR
151387. DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR
151388. DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR
151389. DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR
151390. DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR
151391. DSI_DIRECT_CMD_STS_CMD_TRANSMISSION
151392. DSI_DIRECT_CMD_STS_CTL
151393. DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE
151394. DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN
151395. DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE
151396. DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN
151397. DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE
151398. DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN
151399. DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE
151400. DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN
151401. DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE
151402. DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN
151403. DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE
151404. DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN
151405. DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE
151406. DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN
151407. DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE
151408. DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN
151409. DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE
151410. DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN
151411. DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE
151412. DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN
151413. DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE
151414. DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN
151415. DSI_DIRECT_CMD_STS_FLAG
151416. DSI_DIRECT_CMD_STS_READ_COMPLETED
151417. DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR
151418. DSI_DIRECT_CMD_STS_TE_RECEIVED
151419. DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED
151420. DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED
151421. DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK
151422. DSI_DIRECT_CMD_STS_TRIGGER_VAL_SHIFT
151423. DSI_DIRECT_CMD_STS_WRITE_COMPLETED
151424. DSI_DIRECT_CMD_WRDAT0
151425. DSI_DIRECT_CMD_WRDAT1
151426. DSI_DIRECT_CMD_WRDAT2
151427. DSI_DIRECT_CMD_WRDAT3
151428. DSI_DISP0_CHANNEL_MASK
151429. DSI_DISP0_CHANNEL_SHIFT
151430. DSI_DISP0_COMMAND_MODE
151431. DSI_DISP0_ENABLE
151432. DSI_DISP0_LP_STOP_CTRL_MASK
151433. DSI_DISP0_LP_STOP_CTRL_SHIFT
151434. DSI_DISP0_LP_STOP_DISABLE
151435. DSI_DISP0_LP_STOP_PERFRAME
151436. DSI_DISP0_LP_STOP_PERLINE
151437. DSI_DISP0_PFORMAT_MASK
151438. DSI_DISP0_PFORMAT_SHIFT
151439. DSI_DISP0_PIX_CLK_DIV_MASK
151440. DSI_DISP0_PIX_CLK_DIV_SHIFT
151441. DSI_DISP0_ST_END
151442. DSI_DISP1_ENABLE
151443. DSI_DISP1_PFORMAT_16BIT
151444. DSI_DISP1_PFORMAT_24BIT
151445. DSI_DISP1_PFORMAT_32BIT_BE
151446. DSI_DISP1_PFORMAT_32BIT_LE
151447. DSI_DISP1_PFORMAT_MASK
151448. DSI_DISP1_PFORMAT_SHIFT
151449. DSI_DISP_HACTIVE_NULL
151450. DSI_DISP_HBP_CTRL
151451. DSI_DISP_HFP_CTRL
151452. DSI_DISP_VBLP_CTRL
151453. DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0
151454. DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1
151455. DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL
151456. DSI_DLN0_PHY_ERR_DLN0_ERR_ESC
151457. DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC
151458. DSI_DMAFIFO_READ_WATERMARK
151459. DSI_DMAFIFO_READ_WATERMARK_EIGHTH
151460. DSI_DMAFIFO_READ_WATERMARK_FOURTH
151461. DSI_DMAFIFO_READ_WATERMARK_HALF
151462. DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH
151463. DSI_DMAFIFO_WRITE_WATERMARK
151464. DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH
151465. DSI_DMAFIFO_WRITE_WATERMARK_FOURTH
151466. DSI_DMAFIFO_WRITE_WATERMARK_HALF
151467. DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH
151468. DSI_DN0
151469. DSI_DN1
151470. DSI_DN2
151471. DSI_DN3
151472. DSI_DP0
151473. DSI_DP1
151474. DSI_DP2
151475. DSI_DP3
151476. DSI_DPHY_LANES_TRIM
151477. DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1
151478. DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK
151479. DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1
151480. DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2
151481. DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK
151482. DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1
151483. DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2
151484. DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK
151485. DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_SHIFT
151486. DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK
151487. DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_SHIFT
151488. DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK
151489. DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_SHIFT
151490. DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK
151491. DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT
151492. DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2
151493. DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81
151494. DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90
151495. DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK
151496. DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1
151497. DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2
151498. DSI_DPI_CFG_POL
151499. DSI_DPI_COLOR_CODING
151500. DSI_DPI_COLOR_FORMAT_RGB565
151501. DSI_DPI_COLOR_FORMAT_RGB666
151502. DSI_DPI_COLOR_FORMAT_RGB666_UNPACK
151503. DSI_DPI_COLOR_FORMAT_RGB888
151504. DSI_DPI_COMPLETE_LAST_LINE
151505. DSI_DPI_CTRL_HS_SHUTDOWN
151506. DSI_DPI_CTRL_HS_TURN_ON
151507. DSI_DPI_DISABLE_BTA
151508. DSI_DPI_LP_CMD_TIM
151509. DSI_DPI_TIMING_MASK
151510. DSI_DPI_VCID
151511. DSI_DPI_VIRT_CHANNEL_OFFSET
151512. DSI_DSIPHY_CFG0
151513. DSI_DSIPHY_CFG1
151514. DSI_DSIPHY_CFG10
151515. DSI_DSIPHY_CFG2
151516. DSI_DSIPHY_CFG5
151517. DSI_DUAL_LINK_FRONT_BACK
151518. DSI_DUAL_LINK_NONE
151519. DSI_DUAL_LINK_PIXEL_ALT
151520. DSI_DWORD_BYTE_SWAP
151521. DSI_EDPI_CMD_SIZE
151522. DSI_EN
151523. DSI_ENABLE
151524. DSI_ENCODER_MASTER
151525. DSI_ENCODER_SLAVE
151526. DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE
151527. DSI_EOT_PACKET_CTRL_TX_EOT_APPEND
151528. DSI_EOT_PKT_SIZE
151529. DSI_ERR_STATE_ACK
151530. DSI_ERR_STATE_DLN0_PHY
151531. DSI_ERR_STATE_FIFO
151532. DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION
151533. DSI_ERR_STATE_MDP_FIFO_UNDERFLOW
151534. DSI_ERR_STATE_PLL_UNLOCKED
151535. DSI_ERR_STATE_TIMEOUT
151536. DSI_ESC_CLK
151537. DSI_ESC_CLK_T
151538. DSI_EXITS
151539. DSI_EXT_RESET_POL
151540. DSI_EXT_RESET_POL_HIGH
151541. DSI_EXT_RESET_POL_LOW
151542. DSI_EXT_TE_MODE
151543. DSI_EXT_TE_MODE_HVSYNC_EDGE
151544. DSI_EXT_TE_MODE_HVSYNC_WIDTH
151545. DSI_EXT_TE_MODE_VSYNC_EDGE
151546. DSI_EXT_TE_MODE_VSYNC_WIDTH
151547. DSI_EXT_TE_MUX
151548. DSI_EXT_TE_POL
151549. DSI_EXT_TE_POL_FALLING
151550. DSI_EXT_TE_POL_RISING
151551. DSI_FIFO_DBI_EMPTY
151552. DSI_FIFO_DPI_EMPTY
151553. DSI_FIFO_GEN_HS_CTRL_EMPTY
151554. DSI_FIFO_GEN_HS_CTRL_FULL
151555. DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY
151556. DSI_FIFO_GEN_HS_DATA_EMPTY
151557. DSI_FIFO_GEN_HS_DATA_FULL
151558. DSI_FIFO_GEN_HS_DATA_HALF_EMPTY
151559. DSI_FIFO_GEN_LP_CTRL_EMPTY
151560. DSI_FIFO_GEN_LP_CTRL_FULL
151561. DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY
151562. DSI_FIFO_GEN_LP_DATA_EMPTY
151563. DSI_FIFO_GEN_LP_DATA_FULL
151564. DSI_FIFO_GEN_LP_DATA_HALF_EMPTY
151565. DSI_FIFO_SIZE_0
151566. DSI_FIFO_SIZE_128
151567. DSI_FIFO_SIZE_32
151568. DSI_FIFO_SIZE_64
151569. DSI_FIFO_SIZE_96
151570. DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW
151571. DSI_FLAG_CLEAR
151572. DSI_FLAG_CLR
151573. DSI_FLAG_NO_CLEAR
151574. DSI_FLD_GET
151575. DSI_FOUR_DATA_LANE
151576. DSI_FUNC_PRG_REG
151577. DSI_GANGED_MODE_CONTROL
151578. DSI_GANGED_MODE_CONTROL_ENABLE
151579. DSI_GANGED_MODE_SIZE
151580. DSI_GANGED_MODE_START
151581. DSI_GEN_HDR
151582. DSI_GEN_PLD_DATA
151583. DSI_GEN_VCID
151584. DSI_GET_PIXEL_STREAM_FROM_FMT0
151585. DSI_GET_PIXEL_STREAM_FROM_FMT1
151586. DSI_GET_PIXEL_STREAM_FROM_FMT2
151587. DSI_GET_PIXEL_STREAM_FROM_FMT3
151588. DSI_GET_PIXEL_STREAM_FROM_FMT4
151589. DSI_GET_PIXEL_STREAM_FROM_FMT5
151590. DSI_GNQ
151591. DSI_HBP_FRAME_OVERHEAD
151592. DSI_HBP_WC
151593. DSI_HFP_FRAME_OVERHEAD
151594. DSI_HFP_WC
151595. DSI_HOST_CONTROL
151596. DSI_HOST_CONTROL_CRC_RESET
151597. DSI_HOST_CONTROL_CS
151598. DSI_HOST_CONTROL_ECC
151599. DSI_HOST_CONTROL_FIFO_RESET
151600. DSI_HOST_CONTROL_FIFO_SEL
151601. DSI_HOST_CONTROL_HS
151602. DSI_HOST_CONTROL_IMM_BTA
151603. DSI_HOST_CONTROL_PKT_BTA
151604. DSI_HOST_CONTROL_RAW
151605. DSI_HOST_CONTROL_TX_TRIG_FIFO
151606. DSI_HOST_CONTROL_TX_TRIG_HOST
151607. DSI_HOST_CONTROL_TX_TRIG_SOL
151608. DSI_HSA_FRAME_OVERHEAD
151609. DSI_HSA_WC
151610. DSI_HSS_VSS_VSE_FRAME_OVERHEAD
151611. DSI_HSTX_CKL_WC
151612. DSI_HSTX_TO
151613. DSI_HS_CLT0_CPREP_MASK
151614. DSI_HS_CLT0_CPREP_SHIFT
151615. DSI_HS_CLT0_CPRE_MASK
151616. DSI_HS_CLT0_CPRE_SHIFT
151617. DSI_HS_CLT0_CZERO_MASK
151618. DSI_HS_CLT0_CZERO_SHIFT
151619. DSI_HS_CLT1_CPOST_MASK
151620. DSI_HS_CLT1_CPOST_SHIFT
151621. DSI_HS_CLT1_CTRAIL_MASK
151622. DSI_HS_CLT1_CTRAIL_SHIFT
151623. DSI_HS_CLT2_WUP_MASK
151624. DSI_HS_CLT2_WUP_SHIFT
151625. DSI_HS_CTRL_GEN_LONG_W
151626. DSI_HS_CTRL_GEN_R0
151627. DSI_HS_CTRL_GEN_R1
151628. DSI_HS_CTRL_GEN_R2
151629. DSI_HS_CTRL_GEN_SHORT_W0
151630. DSI_HS_CTRL_GEN_SHORT_W1
151631. DSI_HS_CTRL_GEN_SHORT_W2
151632. DSI_HS_CTRL_MCS_LONG_W
151633. DSI_HS_CTRL_MCS_R0
151634. DSI_HS_CTRL_MCS_SHORT_W0
151635. DSI_HS_CTRL_MCS_SHORT_W1
151636. DSI_HS_CTRL_VC_OFFSET
151637. DSI_HS_CTRL_WC_OFFSET
151638. DSI_HS_DLT3_EXIT_MASK
151639. DSI_HS_DLT3_EXIT_SHIFT
151640. DSI_HS_DLT3_PRE_MASK
151641. DSI_HS_DLT3_PRE_SHIFT
151642. DSI_HS_DLT3_ZERO_MASK
151643. DSI_HS_DLT3_ZERO_SHIFT
151644. DSI_HS_DLT4_ANLAT_MASK
151645. DSI_HS_DLT4_ANLAT_SHIFT
151646. DSI_HS_DLT4_LPX_MASK
151647. DSI_HS_DLT4_LPX_SHIFT
151648. DSI_HS_DLT4_TRAIL_MASK
151649. DSI_HS_DLT4_TRAIL_SHIFT
151650. DSI_HS_DLT5_INIT_MASK
151651. DSI_HS_DLT5_INIT_SHIFT
151652. DSI_HS_DLT6_LP_LPX_MASK
151653. DSI_HS_DLT6_LP_LPX_SHIFT
151654. DSI_HS_DLT6_TA_GET_MASK
151655. DSI_HS_DLT6_TA_GET_SHIFT
151656. DSI_HS_DLT6_TA_GO_MASK
151657. DSI_HS_DLT6_TA_GO_SHIFT
151658. DSI_HS_DLT6_TA_SURE_MASK
151659. DSI_HS_DLT6_TA_SURE_SHIFT
151660. DSI_HS_DLT7_LP_WUP_MASK
151661. DSI_HS_DLT7_LP_WUP_SHIFT
151662. DSI_HS_LP_SWITCH_COUNTER_OFFSET
151663. DSI_HS_RD_TO_CNT
151664. DSI_HS_TX_TIMEOUT_MASK
151665. DSI_HS_WR_TO_CNT
151666. DSI_HW_SOURCE_SEL
151667. DSI_ID_REG
151668. DSI_ID_VALUE
151669. DSI_INCR_SYNCPT
151670. DSI_INCR_SYNCPT_CONTROL
151671. DSI_INCR_SYNCPT_ERROR
151672. DSI_INIT_SEQ_CONTROL
151673. DSI_INIT_SEQ_DATA_0
151674. DSI_INIT_SEQ_DATA_1
151675. DSI_INIT_SEQ_DATA_10
151676. DSI_INIT_SEQ_DATA_11
151677. DSI_INIT_SEQ_DATA_12
151678. DSI_INIT_SEQ_DATA_13
151679. DSI_INIT_SEQ_DATA_14
151680. DSI_INIT_SEQ_DATA_15
151681. DSI_INIT_SEQ_DATA_2
151682. DSI_INIT_SEQ_DATA_3
151683. DSI_INIT_SEQ_DATA_4
151684. DSI_INIT_SEQ_DATA_5
151685. DSI_INIT_SEQ_DATA_6
151686. DSI_INIT_SEQ_DATA_7
151687. DSI_INIT_SEQ_DATA_8
151688. DSI_INIT_SEQ_DATA_9
151689. DSI_INIT_TIMER_MASK
151690. DSI_INPUT_PORT
151691. DSI_INSERT_DCS_COMMAND
151692. DSI_INSERT_DCS_COMMAND_DISABLE
151693. DSI_INSERT_DCS_COMMAND_ENABLE
151694. DSI_INST_ESCA_LPDT
151695. DSI_INST_ESCA_RESET
151696. DSI_INST_ESCA_ULPS
151697. DSI_INST_ESCA_UN1
151698. DSI_INST_ESCA_UN2
151699. DSI_INST_ESCA_UN3
151700. DSI_INST_ESCA_UN4
151701. DSI_INST_ESCA_UN5
151702. DSI_INST_ID_DLY
151703. DSI_INST_ID_END
151704. DSI_INST_ID_HSC
151705. DSI_INST_ID_HSCEXIT
151706. DSI_INST_ID_HSD
151707. DSI_INST_ID_LP11
151708. DSI_INST_ID_LPDT
151709. DSI_INST_ID_NOP
151710. DSI_INST_ID_TBA
151711. DSI_INST_MODE_ESCAPE
151712. DSI_INST_MODE_HS
151713. DSI_INST_MODE_HSCEXIT
151714. DSI_INST_MODE_NOP
151715. DSI_INST_MODE_STOP
151716. DSI_INST_MODE_TBA
151717. DSI_INST_PACK_COMMAND
151718. DSI_INST_PACK_PIXEL
151719. DSI_INTCLR
151720. DSI_INTEN
151721. DSI_INTMASK
151722. DSI_INTR_STATE_RXSOTERROR
151723. DSI_INTR_STATE_SPL_PKG_SENT
151724. DSI_INTR_STATE_TE
151725. DSI_INTSTA
151726. DSI_INTSTATUS
151727. DSI_INT_CMD_GNT
151728. DSI_INT_CMD_RDDATA
151729. DSI_INT_ENABLE
151730. DSI_INT_INTERRUPT_CTL
151731. DSI_INT_MASK
151732. DSI_INT_MSK0
151733. DSI_INT_MSK1
151734. DSI_INT_ST0
151735. DSI_INT_ST1
151736. DSI_INT_STATUS
151737. DSI_INT_VID_GNT
151738. DSI_INT_VID_RDDATA
151739. DSI_INVSEL_DEFAULT
151740. DSI_INVSEL_NLINV
151741. DSI_INVSEL_RTNI
151742. DSI_IRQENABLE
151743. DSI_IRQSTATUS
151744. DSI_IRQ_ACK_TRIGGER
151745. DSI_IRQ_BTA_DONE
151746. DSI_IRQ_CHANNEL_MASK
151747. DSI_IRQ_CMD_DMA_DONE
151748. DSI_IRQ_CMD_MDP_DONE
151749. DSI_IRQ_COMPLEXIO_ERR
151750. DSI_IRQ_ERROR
151751. DSI_IRQ_ERROR_MASK
151752. DSI_IRQ_HS_TX_TIMEOUT
151753. DSI_IRQ_LDO_POWER_GOOD
151754. DSI_IRQ_LP_RX_TIMEOUT
151755. DSI_IRQ_MASK_BTA_DONE
151756. DSI_IRQ_MASK_CMD_DMA_DONE
151757. DSI_IRQ_MASK_CMD_MDP_DONE
151758. DSI_IRQ_MASK_ERROR
151759. DSI_IRQ_MASK_VIDEO_DONE
151760. DSI_IRQ_PLL_LOCK
151761. DSI_IRQ_PLL_RECALL
151762. DSI_IRQ_PLL_UNLOCK
151763. DSI_IRQ_RESYNC
151764. DSI_IRQ_SYNC_LOST
151765. DSI_IRQ_TA_TIMEOUT
151766. DSI_IRQ_TE_TRIGGER
151767. DSI_IRQ_VC0
151768. DSI_IRQ_VC1
151769. DSI_IRQ_VC2
151770. DSI_IRQ_VC3
151771. DSI_IRQ_VIDEO_DONE
151772. DSI_IRQ_WAKEUP
151773. DSI_K
151774. DSI_LANEENABLE
151775. DSI_LANEENABLE_CLOCK
151776. DSI_LANEENABLE_D0
151777. DSI_LANEENABLE_D1
151778. DSI_LANESTATUS0
151779. DSI_LANESTATUS1
151780. DSI_LANE_CLK
151781. DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST
151782. DSI_LANE_DATA1
151783. DSI_LANE_DATA2
151784. DSI_LANE_DATA3
151785. DSI_LANE_DATA4
151786. DSI_LANE_FORCE_TX_STOP
151787. DSI_LANE_FORCE_TX_STOP_ASSERT
151788. DSI_LANE_FORCE_TX_STOP_DEASSERT
151789. DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL
151790. DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK
151791. DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT
151792. DSI_LANE_ULPS_EXIT
151793. DSI_LANE_ULPS_EXIT_ASSERT
151794. DSI_LANE_ULPS_EXIT_DEASSERT
151795. DSI_LANE_ULPS_REQUEST
151796. DSI_LANE_ULPS_REQUEST_ASSERT
151797. DSI_LANE_ULPS_REQUEST_DEASSERT
151798. DSI_LANE_UNUSED
151799. DSI_LCD1_CTRL_0
151800. DSI_LCD1_CTRL_1
151801. DSI_LCD1_CTRL_1_CFG_L1_ALL_SLOT_EN
151802. DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_MASK
151803. DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT
151804. DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN
151805. DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN
151806. DSI_LCD1_CTRL_1_CFG_L1_HEX_PKT_EN
151807. DSI_LCD1_CTRL_1_CFG_L1_HEX_SLOT_EN
151808. DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN
151809. DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN
151810. DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN
151811. DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN
151812. DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN
151813. DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN
151814. DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN
151815. DSI_LCD1_CTRL_1_CFG_L1_M2K_EN
151816. DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN
151817. DSI_LCD1_TIMING_0
151818. DSI_LCD1_TIMING_1
151819. DSI_LCD1_TIMING_2
151820. DSI_LCD1_TIMING_3
151821. DSI_LCD1_WC_0
151822. DSI_LCD1_WC_1
151823. DSI_LCD1_WC_2
151824. DSI_LCD2_CTRL_0
151825. DSI_LCD2_CTRL_1
151826. DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_MASK
151827. DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT
151828. DSI_LCD2_TIMING_0
151829. DSI_LCD2_TIMING_1
151830. DSI_LCD2_TIMING_2
151831. DSI_LCD2_TIMING_3
151832. DSI_LCD2_WC_0
151833. DSI_LCD2_WC_1
151834. DSI_LCD2_WC_2
151835. DSI_LEFT
151836. DSI_LINESET_LDE_EN
151837. DSI_LINESET_LINE
151838. DSI_LINESET_LINEDELTA
151839. DSI_LPCLK_CTRL
151840. DSI_LPRX_HOST_TO
151841. DSI_LPTXTO
151842. DSI_LP_BYTECLK_MASK
151843. DSI_LP_HS_SWITCH_COUNTER_OFFSET
151844. DSI_LP_MSG
151845. DSI_LP_RD_TO_CNT
151846. DSI_LP_RX_TIMEOUT_MASK
151847. DSI_LP_WR_TO_CNT
151848. DSI_MAX
151849. DSI_MAX_BUS_WIDTH
151850. DSI_MAX_ESC_CLK
151851. DSI_MAX_NR_ISRS
151852. DSI_MAX_NR_LANES
151853. DSI_MAX_THRESHOLD
151854. DSI_MCTL_DHPY_ERR_CTL
151855. DSI_MCTL_DPHY_ERR
151856. DSI_MCTL_DPHY_ERR_CLR
151857. DSI_MCTL_DPHY_STATIC
151858. DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK
151859. DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1
151860. DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2
151861. DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK
151862. DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1
151863. DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2
151864. DSI_MCTL_DPHY_STATIC_UI_X4_MASK
151865. DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT
151866. DSI_MCTL_DPHY_TIMEOUT
151867. DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK
151868. DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT
151869. DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK
151870. DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT
151871. DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK
151872. DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT
151873. DSI_MCTL_INTEGRATION_MODE
151874. DSI_MCTL_LANE_STS
151875. DSI_MCTL_MAIN_DATA_CTL
151876. DSI_MCTL_MAIN_DATA_CTL_BTA_EN
151877. DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN
151878. DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM
151879. DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC
151880. DSI_MCTL_MAIN_DATA_CTL_DLX_REMAP_EN
151881. DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN
151882. DSI_MCTL_MAIN_DATA_CTL_IF1_MODE
151883. DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN
151884. DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN
151885. DSI_MCTL_MAIN_DATA_CTL_LINK_EN
151886. DSI_MCTL_MAIN_DATA_CTL_READ_EN
151887. DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN
151888. DSI_MCTL_MAIN_DATA_CTL_TBG_SEL
151889. DSI_MCTL_MAIN_DATA_CTL_TE_POLLING_EN
151890. DSI_MCTL_MAIN_DATA_CTL_TVG_SEL
151891. DSI_MCTL_MAIN_DATA_CTL_VID_EN
151892. DSI_MCTL_MAIN_EN
151893. DSI_MCTL_MAIN_EN_CKLANE_EN
151894. DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ
151895. DSI_MCTL_MAIN_EN_DAT1_EN
151896. DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ
151897. DSI_MCTL_MAIN_EN_DAT2_EN
151898. DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ
151899. DSI_MCTL_MAIN_EN_IF1_EN
151900. DSI_MCTL_MAIN_EN_IF2_EN
151901. DSI_MCTL_MAIN_EN_PLL_START
151902. DSI_MCTL_MAIN_PHY_CTL
151903. DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS
151904. DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN
151905. DSI_MCTL_MAIN_PHY_CTL_CLOCK_FORCE_STOP_MODE
151906. DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN
151907. DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN
151908. DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE
151909. DSI_MCTL_MAIN_PHY_CTL_LANE2_EN
151910. DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK
151911. DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT
151912. DSI_MCTL_MAIN_STS
151913. DSI_MCTL_MAIN_STS_CLKLANE_READY
151914. DSI_MCTL_MAIN_STS_CLR
151915. DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK
151916. DSI_MCTL_MAIN_STS_DAT1_READY
151917. DSI_MCTL_MAIN_STS_DAT2_READY
151918. DSI_MCTL_MAIN_STS_FLAG
151919. DSI_MCTL_MAIN_STS_HSTX_TO_ERR
151920. DSI_MCTL_MAIN_STS_LPRX_TO_ERR
151921. DSI_MCTL_MAIN_STS_PLL_LOCK
151922. DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK
151923. DSI_MCTL_PLL_CTL
151924. DSI_MCTL_ULPOUT_TIME
151925. DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK
151926. DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT
151927. DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK
151928. DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT
151929. DSI_MIPISET1_EOT_EN
151930. DSI_MIPI_BIST_RESET
151931. DSI_MIPI_BIST_RESET_ASSERT
151932. DSI_MIPI_BIST_RESET_DEASSERT
151933. DSI_MIPI_BIST_START
151934. DSI_MIPI_BIST_START_ASSERT
151935. DSI_MIPI_BIST_START_DEASSERT
151936. DSI_MIPI_BIST_VIDEO_FRMT
151937. DSI_MIPI_BIST_VIDEO_FRMT_RAW8
151938. DSI_MIPI_BIST_VIDEO_FRMT_YUV422
151939. DSI_MODE
151940. DSI_MODEL_OMAP3
151941. DSI_MODEL_OMAP4
151942. DSI_MODEL_OMAP5
151943. DSI_MODE_CFG
151944. DSI_MODE_CTRL
151945. DSI_M_AHB_CLK
151946. DSI_M_AHB_RESET
151947. DSI_NON_BURST_SYNC_EVENTS
151948. DSI_NON_BURST_SYNC_PULSES
151949. DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC
151950. DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC
151951. DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC
151952. DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC
151953. DSI_NULL_FRAME_OVERHEAD
151954. DSI_NUM_VIRTUAL_CHANNELS
151955. DSI_ONE_DATA_LANE
151956. DSI_OUTPUT_PORT
151957. DSI_PACKET_BYTE_MSB_LSB_FLIP
151958. DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP
151959. DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP
151960. DSI_PAD_CD_STATUS
151961. DSI_PAD_CONTROL_0
151962. DSI_PAD_CONTROL_1
151963. DSI_PAD_CONTROL_2
151964. DSI_PAD_CONTROL_3
151965. DSI_PAD_CONTROL_4
151966. DSI_PAD_CONTROL_CD
151967. DSI_PAD_CONTROL_VS1_PDIO
151968. DSI_PAD_CONTROL_VS1_PDIO_CLK
151969. DSI_PAD_CONTROL_VS1_PULLDN
151970. DSI_PAD_CONTROL_VS1_PULLDN_CLK
151971. DSI_PAD_LP_DN
151972. DSI_PAD_LP_UP
151973. DSI_PAD_OUT_CLK
151974. DSI_PAD_PREEMP_PD
151975. DSI_PAD_PREEMP_PD_CLK
151976. DSI_PAD_PREEMP_PU
151977. DSI_PAD_PREEMP_PU_CLK
151978. DSI_PAD_SLEW_DN
151979. DSI_PAD_SLEW_UP
151980. DSI_PAYLOAD0
151981. DSI_PAYLOAD1
151982. DSI_PCKHDL_CFG
151983. DSI_PCLK_OFF
151984. DSI_PCLK_ON
151985. DSI_PERF_LATENCY_SEL
151986. DSI_PERF_LATENCY_SEL_DATA_LANE0
151987. DSI_PERF_LATENCY_SEL_DATA_LANE1
151988. DSI_PERF_LATENCY_SEL_DATA_LANE2
151989. DSI_PERF_LATENCY_SEL_DATA_LANE3
151990. DSI_PFORMAT_RGB565
151991. DSI_PFORMAT_RGB666
151992. DSI_PFORMAT_RGB666_PACKED
151993. DSI_PFORMAT_RGB888
151994. DSI_PG_CONFIG__DSI_POWER_FORCEON_MASK
151995. DSI_PG_CONFIG__DSI_POWER_FORCEON__SHIFT
151996. DSI_PG_ENABLE__DSI_POWER_GATE_MASK
151997. DSI_PG_ENABLE__DSI_POWER_GATE__SHIFT
151998. DSI_PG_STATUS__DSI_DESIRED_PWR_STATE_MASK
151999. DSI_PG_STATUS__DSI_DESIRED_PWR_STATE__SHIFT
152000. DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS_MASK
152001. DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS__SHIFT
152002. DSI_PHY
152003. DSI_PHYC_DLANE0_ENABLE
152004. DSI_PHYC_DLANE0_FORCE_STOP
152005. DSI_PHYC_DLANE0_ULPS
152006. DSI_PHYC_DLANE1_ENABLE
152007. DSI_PHYC_DLANE1_ULPS
152008. DSI_PHYC_DLANE2_ENABLE
152009. DSI_PHYC_DLANE2_ULPS
152010. DSI_PHYC_DLANE3_ENABLE
152011. DSI_PHYC_DLANE3_ULPS
152012. DSI_PHY_AFEC0_CTATADJ_MASK
152013. DSI_PHY_AFEC0_CTATADJ_SHIFT
152014. DSI_PHY_AFEC0_PTATADJ_MASK
152015. DSI_PHY_AFEC0_PTATADJ_SHIFT
152016. DSI_PHY_CTRL_2
152017. DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_MASK
152018. DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT
152019. DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_MASK
152020. DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_SHIFT
152021. DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_MASK
152022. DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_SHIFT
152023. DSI_PHY_CTRL_3
152024. DSI_PHY_DATA_LANE0_DISABLE
152025. DSI_PHY_DATA_LANE0_EN
152026. DSI_PHY_DATA_LANE0_ENABLE
152027. DSI_PHY_DATA_LANE1_DISABLE
152028. DSI_PHY_DATA_LANE1_EN
152029. DSI_PHY_DATA_LANE1_ENABLE
152030. DSI_PHY_DATA_LANE2_DISABLE
152031. DSI_PHY_DATA_LANE2_EN
152032. DSI_PHY_DATA_LANE2_ENABLE
152033. DSI_PHY_DATA_LANE3_DISABLE
152034. DSI_PHY_DATA_LANE3_EN
152035. DSI_PHY_DATA_LANE3_ENABLE
152036. DSI_PHY_IF_CFG
152037. DSI_PHY_LCCON
152038. DSI_PHY_LD0CON
152039. DSI_PHY_OFFSET
152040. DSI_PHY_PLL_CTRL_0_ENABLE
152041. DSI_PHY_PLL_STATUS_PLL_BUSY
152042. DSI_PHY_RCOMP_0
152043. DSI_PHY_RESET_RESET
152044. DSI_PHY_RSTZ
152045. DSI_PHY_STATUS
152046. DSI_PHY_SZ
152047. DSI_PHY_TIMECON0
152048. DSI_PHY_TIMECON1
152049. DSI_PHY_TIMECON2
152050. DSI_PHY_TIMECON3
152051. DSI_PHY_TIME_0
152052. DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_MASK
152053. DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT
152054. DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_MASK
152055. DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT
152056. DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_MASK
152057. DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_SHIFT
152058. DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_MASK
152059. DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT
152060. DSI_PHY_TIME_1
152061. DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_MASK
152062. DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT
152063. DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_MASK
152064. DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT
152065. DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_MASK
152066. DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_SHIFT
152067. DSI_PHY_TIME_2
152068. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_MASK
152069. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT
152070. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_MASK
152071. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_SHIFT
152072. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_MASK
152073. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT
152074. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_MASK
152075. DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT
152076. DSI_PHY_TIME_3
152077. DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_MASK
152078. DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT
152079. DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK
152080. DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT
152081. DSI_PHY_TIME_4
152082. DSI_PHY_TIME_5
152083. DSI_PHY_TIMING_0
152084. DSI_PHY_TIMING_1
152085. DSI_PHY_TIMING_2
152086. DSI_PHY_TMR_CFG
152087. DSI_PHY_TMR_LPCLK_CFG
152088. DSI_PHY_TMR_RD_CFG
152089. DSI_PHY_TST_CTRL0
152090. DSI_PHY_TST_CTRL1
152091. DSI_PHY_TX_TRIGGERS
152092. DSI_PHY_ULPS_CTRL
152093. DSI_PIXEL_CLK
152094. DSI_PIXEL_PLL_CLK
152095. DSI_PIXEL_SRC
152096. DSI_PIX_FIFO_DEPTH
152097. DSI_PIX_FIFO_WIDTH
152098. DSI_PKT_LEN_0_1
152099. DSI_PKT_LEN_2_3
152100. DSI_PKT_LEN_4_5
152101. DSI_PKT_LEN_6_7
152102. DSI_PKT_SEQ_0_HI
152103. DSI_PKT_SEQ_0_LO
152104. DSI_PKT_SEQ_1_HI
152105. DSI_PKT_SEQ_1_LO
152106. DSI_PKT_SEQ_2_HI
152107. DSI_PKT_SEQ_2_LO
152108. DSI_PKT_SEQ_3_HI
152109. DSI_PKT_SEQ_3_LO
152110. DSI_PKT_SEQ_4_HI
152111. DSI_PKT_SEQ_4_LO
152112. DSI_PKT_SEQ_5_HI
152113. DSI_PKT_SEQ_5_LO
152114. DSI_PLL
152115. DSI_PLL_CLK_GATE_DSI0_CCK
152116. DSI_PLL_CLK_GATE_DSI0_DSIPLL
152117. DSI_PLL_CLK_GATE_DSI1_CCK
152118. DSI_PLL_CLK_GATE_DSI1_DSIPLL
152119. DSI_PLL_CLK_GATE_MASK
152120. DSI_PLL_CONFIGURATION1
152121. DSI_PLL_CONFIGURATION2
152122. DSI_PLL_CONTROL
152123. DSI_PLL_DEFAULT_VCO_POSTDIV
152124. DSI_PLL_FRACTION_EN
152125. DSI_PLL_FRAC_COUNTER_MASK
152126. DSI_PLL_FRAC_COUNTER_SHIFT
152127. DSI_PLL_GO
152128. DSI_PLL_LDO_GATE
152129. DSI_PLL_LFSR
152130. DSI_PLL_LOCK
152131. DSI_PLL_M1_DIV_MASK
152132. DSI_PLL_M1_DIV_SHIFT
152133. DSI_PLL_MUX_DSI0_CCK
152134. DSI_PLL_MUX_DSI0_DSIPLL
152135. DSI_PLL_MUX_DSI1_CCK
152136. DSI_PLL_MUX_DSI1_DSIPLL
152137. DSI_PLL_MUX_MASK
152138. DSI_PLL_N1_DIV_MASK
152139. DSI_PLL_N1_DIV_SHIFT
152140. DSI_PLL_OFFSET
152141. DSI_PLL_P1_POST_DIV_MASK
152142. DSI_PLL_P1_POST_DIV_SHIFT
152143. DSI_PLL_P2_MUX_DSI0_DIV2
152144. DSI_PLL_P3_MUX_DSI1_DIV2
152145. DSI_PLL_POWER_OFF
152146. DSI_PLL_POWER_ON_ALL
152147. DSI_PLL_POWER_ON_DIV
152148. DSI_PLL_POWER_ON_HSCLK
152149. DSI_PLL_STATUS
152150. DSI_PLL_SZ
152151. DSI_PLL_USYNC_CNT_MASK
152152. DSI_PLL_USYNC_CNT_SHIFT
152153. DSI_PLL_VCO_EN
152154. DSI_PORT_BIT
152155. DSI_PORT_IN
152156. DSI_PORT_OUT
152157. DSI_PORT_READ
152158. DSI_PORT_WRITE
152159. DSI_POWER_CONTROL
152160. DSI_POWER_CONTROL_ENABLE
152161. DSI_POWER_MODE_DISPLAY_ON
152162. DSI_POWER_MODE_IDLE_ON
152163. DSI_POWER_MODE_NORMAL_ON
152164. DSI_POWER_MODE_PARTIAL_ON
152165. DSI_POWER_MODE_SLEEP_OUT
152166. DSI_POWER_STATE_ULPS_ENTER
152167. DSI_POWER_STATE_ULPS_EXIT
152168. DSI_POWER_STATE_ULPS_OFFSET
152169. DSI_PROTO
152170. DSI_PROTO_SZ
152171. DSI_PSCTRL
152172. DSI_PS_SEL
152173. DSI_PS_WC
152174. DSI_PWAIT_TO
152175. DSI_PWCTLR1_AP
152176. DSI_PWCTLR1_APIS
152177. DSI_PWCTLR1_APOS
152178. DSI_PWCTLR2_AVCL
152179. DSI_PWCTLR2_AVDD
152180. DSI_PWR_UP
152181. DSI_PX
152182. DSI_QUIRK_DCS_CMD_CONFIG_VC
152183. DSI_QUIRK_GNQ
152184. DSI_QUIRK_PHY_DCC
152185. DSI_QUIRK_PLL_PWR_BUG
152186. DSI_QUIRK_REVERSE_TXCLKESC
152187. DSI_QUIRK_VC_OCP_WIDTH
152188. DSI_R
152189. DSI_RACK
152190. DSI_RAW_DATA_BYTE_COUNT
152191. DSI_RDBK_DATA_CTRL_CLR
152192. DSI_RDBK_DATA_CTRL_COUNT
152193. DSI_RDBK_DATA_CTRL_COUNT__MASK
152194. DSI_RDBK_DATA_CTRL_COUNT__SHIFT
152195. DSI_RD_DATA
152196. DSI_READ
152197. DSI_REG
152198. DSI_RESET
152199. DSI_RESET_BYTECLK
152200. DSI_RESET_DISPCLK
152201. DSI_RESET_DSICLK
152202. DSI_RESET_ESCCLK
152203. DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC
152204. DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC
152205. DSI_RESET_ON_DSICLK_DOMAIN_LOGIC
152206. DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC
152207. DSI_RESET_PANEL
152208. DSI_RESET_PANEL_ASSERT
152209. DSI_RESET_PANEL_DEASSERT
152210. DSI_RESET_TIMER_MASK
152211. DSI_RESET_TOGGLE_DELAY_MS
152212. DSI_REVISION
152213. DSI_RGB565_CONF1
152214. DSI_RGB565_CONF2
152215. DSI_RGB565_CONF3
152216. DSI_RGB666_CONF1
152217. DSI_RGB666_CONF2
152218. DSI_RGB888
152219. DSI_RGB_SWAP
152220. DSI_RIGHT
152221. DSI_RXPKT1H_BC_PARAM_MASK
152222. DSI_RXPKT1H_BC_PARAM_SHIFT
152223. DSI_RXPKT1H_COR_ERR
152224. DSI_RXPKT1H_CRC_ERR
152225. DSI_RXPKT1H_DET_ERR
152226. DSI_RXPKT1H_DT_LP_CMD_MASK
152227. DSI_RXPKT1H_DT_LP_CMD_SHIFT
152228. DSI_RXPKT1H_DT_MASK
152229. DSI_RXPKT1H_DT_SHIFT
152230. DSI_RXPKT1H_ECC_ERR
152231. DSI_RXPKT1H_INCOMP_PKT
152232. DSI_RXPKT1H_PKT_TYPE_LONG
152233. DSI_RXPKT1H_SHORT_0_MASK
152234. DSI_RXPKT1H_SHORT_0_SHIFT
152235. DSI_RXPKT1H_SHORT_1_MASK
152236. DSI_RXPKT1H_SHORT_1_SHIFT
152237. DSI_RX_DATA0
152238. DSI_RX_DATA1
152239. DSI_RX_DATA2
152240. DSI_RX_DATA3
152241. DSI_RX_EOT_IGNORE
152242. DSI_RX_EOT_IGNORE_DISABLE
152243. DSI_RX_EOT_IGNORE_ENABLE
152244. DSI_RX_FIFO_EMPTY
152245. DSI_RX_FIFO_SIZE
152246. DSI_RX_FIFO_VC_FULLNESS
152247. DSI_RX_FIFO_VC_SIZE
152248. DSI_RX_PKT_HDR_0
152249. DSI_RX_START
152250. DSI_SEL_IN_BLS
152251. DSI_SEL_IN_RDMA
152252. DSI_SHORTPKTDAT
152253. DSI_SHORTPKTREQ
152254. DSI_SOL_DELAY
152255. DSI_SPD1_T2D
152256. DSI_SRC
152257. DSI_START
152258. DSI_STARTDSI
152259. DSI_START_HSC
152260. DSI_START_HSD
152261. DSI_START_LPRX
152262. DSI_START_LPTX
152263. DSI_START_SEL_SHIFT
152264. DSI_STATUS
152265. DSI_STATUS0_CMD_MODE_DMA_BUSY
152266. DSI_STATUS0_CMD_MODE_ENGINE_BUSY
152267. DSI_STATUS0_CMD_MODE_MDP_BUSY
152268. DSI_STATUS0_DSI_BUSY
152269. DSI_STATUS0_INTERLEAVE_OP_CONTENTION
152270. DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY
152271. DSI_STATUS_IDLE
152272. DSI_STATUS_OVERFLOW
152273. DSI_STATUS_UNDERFLOW
152274. DSI_STOPCLK_TIMING
152275. DSI_SWAP_BGR
152276. DSI_SWAP_BRG
152277. DSI_SWAP_GBR
152278. DSI_SWAP_GRB
152279. DSI_SWAP_RBG
152280. DSI_SWAP_RGB
152281. DSI_SYSCONFIG
152282. DSI_SYSSTATUS
152283. DSI_S_AHB_CLK
152284. DSI_S_AHB_RESET
152285. DSI_TALLY_HTX
152286. DSI_TALLY_LRX
152287. DSI_TALLY_TA
152288. DSI_TA_TIMING_PARAM
152289. DSI_TA_TO
152290. DSI_TEST_CLK_SEL_BYTECLK_G
152291. DSI_TEST_CLK_SEL_DISPCLK_G
152292. DSI_TEST_CLK_SEL_DISPCLK_P
152293. DSI_TEST_CLK_SEL_DISPCLK_R
152294. DSI_TEST_CLK_SEL_DSICLK_G
152295. DSI_TEST_CLK_SEL_DSICLK_P
152296. DSI_TEST_CLK_SEL_DSICLK_R
152297. DSI_TEST_CLK_SEL_DSICLK_TRN
152298. DSI_TEST_CLK_SEL_ESCCLK_G
152299. DSI_TE_SEL_LINK
152300. DSI_TE_SEL_PIN
152301. DSI_TE_SRC_SEL
152302. DSI_TG_STS_CLR
152303. DSI_TG_STS_CTL
152304. DSI_TG_STS_FLAG
152305. DSI_THREE_DATA_LANE
152306. DSI_TIMEOUT_0
152307. DSI_TIMEOUT_1
152308. DSI_TIMEOUT_HTX
152309. DSI_TIMEOUT_LRX
152310. DSI_TIMEOUT_PR
152311. DSI_TIMEOUT_TA
152312. DSI_TIMING1
152313. DSI_TIMING2
152314. DSI_TIMING_FIELD
152315. DSI_TOTAL_H_TOTAL
152316. DSI_TOTAL_H_TOTAL__MASK
152317. DSI_TOTAL_H_TOTAL__SHIFT
152318. DSI_TOTAL_V_TOTAL
152319. DSI_TOTAL_V_TOTAL__MASK
152320. DSI_TOTAL_V_TOTAL__SHIFT
152321. DSI_TO_CNT_CFG
152322. DSI_TO_TALLY
152323. DSI_TRAFFIC_MODE_BURST
152324. DSI_TRAFFIC_MODE_RESERVED
152325. DSI_TRAFFIC_MODE_SYNC_EVENTS
152326. DSI_TRAFFIC_MODE_SYNC_PULSES
152327. DSI_TRANS_FUNC_CONF
152328. DSI_TRIGGER
152329. DSI_TRIGGER_HOST
152330. DSI_TRIGGER_VIDEO
152331. DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME
152332. DSI_TRIG_CTRL_DMA_TRIGGER
152333. DSI_TRIG_CTRL_DMA_TRIGGER__MASK
152334. DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT
152335. DSI_TRIG_CTRL_MDP_TRIGGER
152336. DSI_TRIG_CTRL_MDP_TRIGGER__MASK
152337. DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT
152338. DSI_TRIG_CTRL_STREAM
152339. DSI_TRIG_CTRL_STREAM__MASK
152340. DSI_TRIG_CTRL_STREAM__SHIFT
152341. DSI_TRIG_CTRL_TE
152342. DSI_TURN_AROUND_TIMEOUT_MASK
152343. DSI_TWO_DATA_LANE
152344. DSI_TXPKT1C_CMD_CTRL_BTA
152345. DSI_TXPKT1C_CMD_CTRL_MASK
152346. DSI_TXPKT1C_CMD_CTRL_RX
152347. DSI_TXPKT1C_CMD_CTRL_SHIFT
152348. DSI_TXPKT1C_CMD_CTRL_TRIG
152349. DSI_TXPKT1C_CMD_CTRL_TX
152350. DSI_TXPKT1C_CMD_EN
152351. DSI_TXPKT1C_CMD_MODE_LP
152352. DSI_TXPKT1C_CMD_REPEAT_MASK
152353. DSI_TXPKT1C_CMD_REPEAT_SHIFT
152354. DSI_TXPKT1C_CMD_TE_EN
152355. DSI_TXPKT1C_CMD_TX_TIME_MASK
152356. DSI_TXPKT1C_CMD_TX_TIME_SHIFT
152357. DSI_TXPKT1C_CMD_TYPE_LONG
152358. DSI_TXPKT1C_DISPLAY_NO_MASK
152359. DSI_TXPKT1C_DISPLAY_NO_PRIMARY
152360. DSI_TXPKT1C_DISPLAY_NO_SECONDARY
152361. DSI_TXPKT1C_DISPLAY_NO_SHIFT
152362. DSI_TXPKT1C_DISPLAY_NO_SHORT
152363. DSI_TXPKT1C_TRIG_CMD_MASK
152364. DSI_TXPKT1C_TRIG_CMD_SHIFT
152365. DSI_TXPKT1H_BC_CMDFIFO_MASK
152366. DSI_TXPKT1H_BC_CMDFIFO_SHIFT
152367. DSI_TXPKT1H_BC_DT_MASK
152368. DSI_TXPKT1H_BC_DT_SHIFT
152369. DSI_TXPKT1H_BC_PARAM_MASK
152370. DSI_TXPKT1H_BC_PARAM_SHIFT
152371. DSI_TXRX_CTRL
152372. DSI_TX_CRC
152373. DSI_TX_EOT_APPEND
152374. DSI_TX_EOT_APPEND_DISABLE
152375. DSI_TX_EOT_APPEND_ENABLE
152376. DSI_TX_FIFO_SIZE
152377. DSI_TX_FIFO_VC_EMPTINESS
152378. DSI_TX_FIFO_VC_SIZE
152379. DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK
152380. DSI_ULTRA_LOW_POWER_CONTROL
152381. DSI_USE_CMDFIFO
152382. DSI_USE_DENG_LENGTH
152383. DSI_USE_DENG_LENGTH_DISABLE
152384. DSI_USE_DENG_LENGTH_ENABLE
152385. DSI_VACT_NL
152386. DSI_VBP_NL
152387. DSI_VC_CTRL
152388. DSI_VC_IRQENABLE
152389. DSI_VC_IRQSTATUS
152390. DSI_VC_IRQ_BTA
152391. DSI_VC_IRQ_CS
152392. DSI_VC_IRQ_ECC_CORR
152393. DSI_VC_IRQ_ECC_NO_CORR
152394. DSI_VC_IRQ_ERROR_MASK
152395. DSI_VC_IRQ_FIFO_RX_OVF
152396. DSI_VC_IRQ_FIFO_TX_OVF
152397. DSI_VC_IRQ_FIFO_TX_UDF
152398. DSI_VC_IRQ_PACKET_SENT
152399. DSI_VC_IRQ_PP_BUSY_CHANGE
152400. DSI_VC_LONG_PACKET_HEADER
152401. DSI_VC_LONG_PACKET_PAYLOAD
152402. DSI_VC_SHORT_PACKET_HEADER
152403. DSI_VC_SOURCE_L4
152404. DSI_VC_SOURCE_VP
152405. DSI_VC_TE
152406. DSI_VERSION
152407. DSI_VERSION_MAJOR
152408. DSI_VERSION_MAJOR__MASK
152409. DSI_VERSION_MAJOR__SHIFT
152410. DSI_VFP_NL
152411. DSI_VGLS_DEFAULT
152412. DSI_VGLS_SEL
152413. DSI_VIDEO_BLLP_PWR_MODE
152414. DSI_VIDEO_BLLP_PWR_MODE_HS
152415. DSI_VIDEO_BLLP_PWR_MODE_LP
152416. DSI_VIDEO_DST_FORMAT_RGB565
152417. DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED
152418. DSI_VIDEO_DST_FORMAT_RGB666_PACKED
152419. DSI_VIDEO_DST_FORMAT_RGB888
152420. DSI_VIDEO_EOF_BLLP_PWR_MODE
152421. DSI_VIDEO_EOF_BLLP_PWR_MODE_HS
152422. DSI_VIDEO_EOF_BLLP_PWR_MODE_LP
152423. DSI_VIDEO_MODE
152424. DSI_VIDEO_MODE_CONTROL
152425. DSI_VIDEO_MODE_DISABLE
152426. DSI_VIDEO_MODE_DST_FORMAT
152427. DSI_VIDEO_MODE_EN
152428. DSI_VIDEO_MODE_ENABLE
152429. DSI_VIDEO_PULSE_MODE_OPT
152430. DSI_VIDEO_PWR_MODE
152431. DSI_VIDEO_PWR_MODE_HS
152432. DSI_VIDEO_PWR_MODE_LP
152433. DSI_VIDEO_TRAFFIC_MODE
152434. DSI_VID_BLKSIZE1
152435. DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK
152436. DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT
152437. DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK
152438. DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT
152439. DSI_VID_BLKSIZE2
152440. DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK
152441. DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT
152442. DSI_VID_CFG0_BLLP_POWER_STOP
152443. DSI_VID_CFG0_DST_FORMAT
152444. DSI_VID_CFG0_DST_FORMAT__MASK
152445. DSI_VID_CFG0_DST_FORMAT__SHIFT
152446. DSI_VID_CFG0_EOF_BLLP_POWER_STOP
152447. DSI_VID_CFG0_HBP_POWER_STOP
152448. DSI_VID_CFG0_HFP_POWER_STOP
152449. DSI_VID_CFG0_HSA_POWER_STOP
152450. DSI_VID_CFG0_PULSE_MODE_HSA_HE
152451. DSI_VID_CFG0_TRAFFIC_MODE
152452. DSI_VID_CFG0_TRAFFIC_MODE__MASK
152453. DSI_VID_CFG0_TRAFFIC_MODE__SHIFT
152454. DSI_VID_CFG0_VIRT_CHANNEL
152455. DSI_VID_CFG0_VIRT_CHANNEL__MASK
152456. DSI_VID_CFG0_VIRT_CHANNEL__SHIFT
152457. DSI_VID_CFG1_B_SEL
152458. DSI_VID_CFG1_G_SEL
152459. DSI_VID_CFG1_RGB_SWAP
152460. DSI_VID_CFG1_RGB_SWAP__MASK
152461. DSI_VID_CFG1_RGB_SWAP__SHIFT
152462. DSI_VID_CFG1_R_SEL
152463. DSI_VID_DPHY_TIME
152464. DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK
152465. DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT
152466. DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK
152467. DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT
152468. DSI_VID_HBP_TIME
152469. DSI_VID_HLINE_TIME
152470. DSI_VID_HSA_TIME
152471. DSI_VID_HSIZE1
152472. DSI_VID_HSIZE1_HBP_LENGTH_MASK
152473. DSI_VID_HSIZE1_HBP_LENGTH_SHIFT
152474. DSI_VID_HSIZE1_HFP_LENGTH_MASK
152475. DSI_VID_HSIZE1_HFP_LENGTH_SHIFT
152476. DSI_VID_HSIZE1_HSA_LENGTH_MASK
152477. DSI_VID_HSIZE1_HSA_LENGTH_SHIFT
152478. DSI_VID_HSIZE2
152479. DSI_VID_HSIZE2_RGB_SIZE_MASK
152480. DSI_VID_HSIZE2_RGB_SIZE_SHIFT
152481. DSI_VID_MAIN_CTL
152482. DSI_VID_MAIN_CTL_BURST_MODE
152483. DSI_VID_MAIN_CTL_HEADER_MASK
152484. DSI_VID_MAIN_CTL_HEADER_SHIFT
152485. DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK
152486. DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT
152487. DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING
152488. DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0
152489. DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1
152490. DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL
152491. DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING
152492. DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0
152493. DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1
152494. DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL
152495. DSI_VID_MAIN_CTL_START_MODE_MASK
152496. DSI_VID_MAIN_CTL_START_MODE_SHIFT
152497. DSI_VID_MAIN_CTL_STOP_MODE_MASK
152498. DSI_VID_MAIN_CTL_STOP_MODE_SHIFT
152499. DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE
152500. DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL
152501. DSI_VID_MAIN_CTL_VID_ID_MASK
152502. DSI_VID_MAIN_CTL_VID_ID_SHIFT
152503. DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS
152504. DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS
152505. DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE
152506. DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS
152507. DSI_VID_MODE_CFG
152508. DSI_VID_MODE_STS
152509. DSI_VID_MODE_STS_CLR
152510. DSI_VID_MODE_STS_CTL
152511. DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE
152512. DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE
152513. DSI_VID_MODE_STS_CTL_ERR_LONGREAD
152514. DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE
152515. DSI_VID_MODE_STS_CTL_ERR_LONGWRITE
152516. DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE
152517. DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA
152518. DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE
152519. DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC
152520. DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE
152521. DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC
152522. DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE
152523. DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH
152524. DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE
152525. DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT
152526. DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE
152527. DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH
152528. DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE
152529. DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE
152530. DSI_VID_MODE_STS_CTL_VSG_RUNNING
152531. DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE
152532. DSI_VID_MODE_STS_FLAG
152533. DSI_VID_MODE_STS_VSG_RUNNING
152534. DSI_VID_NULL_SIZE
152535. DSI_VID_NUM_CHUNKS
152536. DSI_VID_PCK_TIME
152537. DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT
152538. DSI_VID_PKT_SIZE
152539. DSI_VID_VACTIVE_LINES
152540. DSI_VID_VBP_LINES
152541. DSI_VID_VCA_SETTING1
152542. DSI_VID_VCA_SETTING1_BURST_LP
152543. DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK
152544. DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT
152545. DSI_VID_VCA_SETTING2
152546. DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK
152547. DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT
152548. DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK
152549. DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT
152550. DSI_VID_VFP_LINES
152551. DSI_VID_VSA_LINES
152552. DSI_VID_VSIZE
152553. DSI_VID_VSIZE_VACT_LENGTH_MASK
152554. DSI_VID_VSIZE_VACT_LENGTH_SHIFT
152555. DSI_VID_VSIZE_VBP_LENGTH_MASK
152556. DSI_VID_VSIZE_VBP_LENGTH_SHIFT
152557. DSI_VID_VSIZE_VFP_LENGTH_MASK
152558. DSI_VID_VSIZE_VFP_LENGTH_SHIFT
152559. DSI_VID_VSIZE_VSA_LENGTH_MASK
152560. DSI_VID_VSIZE_VSA_LENGTH_SHIFT
152561. DSI_VM_CMD_CON
152562. DSI_VM_TIMING1
152563. DSI_VM_TIMING2
152564. DSI_VM_TIMING3
152565. DSI_VM_TIMING4
152566. DSI_VM_TIMING5
152567. DSI_VM_TIMING6
152568. DSI_VM_TIMING7
152569. DSI_VSA_NL
152570. DSI_WCFGR
152571. DSI_WCR
152572. DSI_WISR
152573. DSI_WPCR0
152574. DSI_WRITE
152575. DSI_WRPCR
152576. DSI_WR_DATA
152577. DSI_XFER_TIMEOUT_MS
152578. DSI_XML
152579. DSI_XT_TE_MUX_DCLK
152580. DSI_XT_TE_MUX_DINV
152581. DSI_XT_TE_MUX_FRAME
152582. DSI_XT_TE_MUX_GCLK
152583. DSI_XT_TE_MUX_GOE
152584. DSI_XT_TE_MUX_GPIO4
152585. DSI_XT_TE_MUX_GPIO5
152586. DSI_XT_TE_MUX_LCDD17
152587. DSI_XT_TE_MUX_SS
152588. DSI__MEM_PG
152589. DSI__MEM_PG__0
152590. DSKBYT
152591. DSKCHANGE
152592. DSKDIREC
152593. DSKDRV0
152594. DSKDRV1
152595. DSKDRVNONE
152596. DSKINDEX
152597. DSKLEN_DMAEN
152598. DSKLEN_WRITE
152599. DSKMOTOR
152600. DSKPROT
152601. DSKRDY
152602. DSKSEL0
152603. DSKSEL1
152604. DSKSEL2
152605. DSKSEL3
152606. DSKSIDE
152607. DSKSTEP
152608. DSKTRACK0
152609. DSK_STATISTICS
152610. DSL
152611. DSL3510_H_
152612. DSLH
152613. DSLO
152614. DSLRADD
152615. DSL_0
152616. DSL_1
152617. DSL_16
152618. DSL_2
152619. DSL_32
152620. DSL_4
152621. DSL_8
152622. DSL_FXSENDAMOUNT_D
152623. DSL_FXSENDAMOUNT_D_MASK
152624. DSL_LINEMASK_GEN2
152625. DSL_LINEMASK_GEN3
152626. DSL_LOOPENDADDR
152627. DSL_LOOPENDADDR_MASK
152628. DSMARK_EMBEDDED_SZ
152629. DSMC
152630. DSMG600_FREQ
152631. DSMG600_LED_PWR_GPIO
152632. DSMG600_LED_WLAN_GPIO
152633. DSMG600_PB_GPIO
152634. DSMG600_PO_GPIO
152635. DSMG600_RB_GPIO
152636. DSMG600_SCL_PIN
152637. DSMG600_SDA_PIN
152638. DSMR
152639. DSMR_CDED
152640. DSMR_CDEL
152641. DSMR_CDEM_CDE
152642. DSMR_CDEM_HIGH
152643. DSMR_CDEM_LOW
152644. DSMR_CDEM_MASK
152645. DSMR_CSPM
152646. DSMR_CSY_222
152647. DSMR_CSY_333
152648. DSMR_CSY_MASK
152649. DSMR_CSY_VH_OR
152650. DSMR_DDIS
152651. DSMR_DIL
152652. DSMR_DIPM_CSYNC
152653. DSMR_DIPM_DE
152654. DSMR_DIPM_DISP
152655. DSMR_DIPM_MASK
152656. DSMR_HSL
152657. DSMR_ODEV
152658. DSMR_ODPM
152659. DSMR_VSL
152660. DSMR_VSPM
152661. DSM_CC_STREAM
152662. DSM_CTRL1
152663. DSM_CTRL2
152664. DSM_DATA_SEL
152665. DSM_DATA_SEL_0
152666. DSM_DATA_SEL_1
152667. DSM_DATA_SEL_BOTH
152668. DSM_DATA_SEL_DISABLE
152669. DSM_ENABLE_ERROR_INJECT
152670. DSM_ENABLE_ERROR_INJECT_DOUBLE
152671. DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED
152672. DSM_ENABLE_ERROR_INJECT_FED_IN
152673. DSM_ENABLE_ERROR_INJECT_SINGLE
152674. DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE
152675. DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED
152676. DSM_FUNC_ERR_HANDLE_MSI
152677. DSM_SELECT_INJECT_DELAY
152678. DSM_SELECT_INJECT_DELAY_DELAY_ERROR
152679. DSM_SELECT_INJECT_DELAY_NO_DELAY
152680. DSM_SINGLE_WRITE
152681. DSM_SINGLE_WRITE_DIS
152682. DSM_SINGLE_WRITE_EN
152683. DSM_STATUS1
152684. DSM_STATUS2
152685. DSM_TRICK_FLAG
152686. DSNDTX0
152687. DSNDTX1
152688. DSNDTX2
152689. DSNDTX3
152690. DSNDTX4
152691. DSNDTX5
152692. DSNDTX6
152693. DSNDTX7
152694. DSNT_XFH
152695. DSO
152696. DSO_ACCEPTMODE
152697. DSO_BINARY_TYPE__BPF_PROG_INFO
152698. DSO_BINARY_TYPE__BUILDID_DEBUGINFO
152699. DSO_BINARY_TYPE__BUILD_ID_CACHE
152700. DSO_BINARY_TYPE__BUILD_ID_CACHE_DEBUGINFO
152701. DSO_BINARY_TYPE__DEBUGLINK
152702. DSO_BINARY_TYPE__FEDORA_DEBUGINFO
152703. DSO_BINARY_TYPE__GUEST_KALLSYMS
152704. DSO_BINARY_TYPE__GUEST_KCORE
152705. DSO_BINARY_TYPE__GUEST_KMODULE
152706. DSO_BINARY_TYPE__GUEST_KMODULE_COMP
152707. DSO_BINARY_TYPE__GUEST_VMLINUX
152708. DSO_BINARY_TYPE__JAVA_JIT
152709. DSO_BINARY_TYPE__KALLSYMS
152710. DSO_BINARY_TYPE__KCORE
152711. DSO_BINARY_TYPE__NOT_FOUND
152712. DSO_BINARY_TYPE__OPENEMBEDDED_DEBUGINFO
152713. DSO_BINARY_TYPE__SYMTAB_CNT
152714. DSO_BINARY_TYPE__SYSTEM_PATH_DSO
152715. DSO_BINARY_TYPE__SYSTEM_PATH_KMODULE
152716. DSO_BINARY_TYPE__SYSTEM_PATH_KMODULE_COMP
152717. DSO_BINARY_TYPE__UBUNTU_DEBUGINFO
152718. DSO_BINARY_TYPE__VMLINUX
152719. DSO_CONACCEPT
152720. DSO_CONACCESS
152721. DSO_CONDATA
152722. DSO_CONREJECT
152723. DSO_CORK
152724. DSO_DATA_STATUS_ERROR
152725. DSO_DATA_STATUS_OK
152726. DSO_DATA_STATUS_SEEN_ITRACE
152727. DSO_DATA_STATUS_UNKNOWN
152728. DSO_DISDATA
152729. DSO_INFO
152730. DSO_LINKINFO
152731. DSO_LOAD_ERRNO__CANNOT_READ_BUILDID
152732. DSO_LOAD_ERRNO__DECOMPRESSION_FAILURE
152733. DSO_LOAD_ERRNO__INTERNAL_ERROR
152734. DSO_LOAD_ERRNO__INVALID_ELF
152735. DSO_LOAD_ERRNO__MISMATCHING_BUILDID
152736. DSO_LOAD_ERRNO__SUCCESS
152737. DSO_MAX
152738. DSO_MAXWINDOW
152739. DSO_NODELAY
152740. DSO_ORDER_RAS
152741. DSO_SEQPACKET
152742. DSO_SERVICES
152743. DSO_STREAM
152744. DSO_SWAP__NO
152745. DSO_SWAP__UNSET
152746. DSO_SWAP__YES
152747. DSO_TYPE_GUEST_KERNEL
152748. DSO_TYPE_KERNEL
152749. DSO_TYPE_USER
152750. DSO__DATA_CACHE_MASK
152751. DSO__DATA_CACHE_SIZE
152752. DSO__DELETED
152753. DSO__NAME_KALLSYMS
152754. DSO__NAME_KCORE
152755. DSO__NAME_VDSO
152756. DSO__NAME_VDSO32
152757. DSO__NAME_VDSOX32
152758. DSO__SWAP
152759. DSO__TYPE_32BIT
152760. DSO__TYPE_64BIT
152761. DSO__TYPE_UNKNOWN
152762. DSO__TYPE_X32BIT
152763. DSP
152764. DSP0CONDCODE
152765. DSP0CURLOOPADDRREG
152766. DSP0CURLOOPCOUNT
152767. DSP0INTCONTLVEC_END
152768. DSP0INTCONTLVEC_START
152769. DSP0INTCONTMASKREG
152770. DSP0INTCONTPENDREG
152771. DSP0INTCONTSERVINT
152772. DSP0IO_END
152773. DSP0IO_START
152774. DSP0LOCALHWREG_END
152775. DSP0LOCALHWREG_START
152776. DSP0LOOPSTACKPTR
152777. DSP0PROGCOUNT
152778. DSP0PROGCOUNTSTACKDATAREG
152779. DSP0PROGCOUNTSTACKPTREG
152780. DSP0STACKFLAG
152781. DSP0STASSTACKDATAREG
152782. DSP0STASSTACKPTR
152783. DSP0TOPLOOPADDRSTACK
152784. DSP0TOPLOOPCOUNTSTACK
152785. DSP0XGPRAM_END
152786. DSP0XGPRAM_START
152787. DSP0XYRAMAGINDEX_END
152788. DSP0XYRAMAGINDEX_START
152789. DSP0XYRAMAGMDFR_END
152790. DSP0XYRAMAGMDFR_START
152791. DSP0XYRAMBASE_END
152792. DSP0XYRAMBASE_START
152793. DSP0XYRAMLENG_END
152794. DSP0XYRAMLENG_START
152795. DSP0YGPRAM_END
152796. DSP0YGPRAM_START
152797. DSP1CONDCODE
152798. DSP1CURLOOPADDRREG
152799. DSP1CURLOOPCOUNT
152800. DSP1INTCONTLVEC_END
152801. DSP1INTCONTLVEC_START
152802. DSP1INTCONTMASKREG
152803. DSP1INTCONTPENDREG
152804. DSP1INTCONTSERVINT
152805. DSP1LOCALHWREG_END
152806. DSP1LOCALHWREG_START
152807. DSP1LOOPSTACKPTR
152808. DSP1PROGCOUNT
152809. DSP1PROGCOUNTSTACKDATAREG
152810. DSP1PROGCOUNTSTACKPTREG
152811. DSP1STACKFLAG
152812. DSP1STASSTACKDATAREG
152813. DSP1STASSTACKPTR
152814. DSP1TOPLOOPADDRSTACK
152815. DSP1TOPLOOPCOUNTSTACK
152816. DSP1XGPRAM_END
152817. DSP1XGPRAM_START
152818. DSP1XYRAMAGINDEX_END
152819. DSP1XYRAMAGINDEX_START
152820. DSP1XYRAMAGMDFR_END
152821. DSP1XYRAMAGMDFR_START
152822. DSP1XYRAMBASE_END
152823. DSP1XYRAMBASE_START
152824. DSP1XYRAMLENG_END
152825. DSP1XYRAMLENG_START
152826. DSP1YGPRAM_END
152827. DSP1YGPRAM_START
152828. DSP2CONDCODE
152829. DSP2CURLOOPADDRREG
152830. DSP2CURLOOPCOUNT
152831. DSP2HOST_REQ_I2SRATE
152832. DSP2HOST_REQ_PIORECORD
152833. DSP2HOST_REQ_TIMER
152834. DSP2INTCONTLVEC_END
152835. DSP2INTCONTLVEC_START
152836. DSP2INTCONTMASKREG
152837. DSP2INTCONTPENDREG
152838. DSP2INTCONTSERVINT
152839. DSP2LOCALHWREG_END
152840. DSP2LOCALHWREG_START
152841. DSP2LOOPSTACKPTR
152842. DSP2PROGCOUNT
152843. DSP2PROGCOUNTSTACKDATAREG
152844. DSP2PROGCOUNTSTACKPTREG
152845. DSP2STACKFLAG
152846. DSP2STASSTACKDATAREG
152847. DSP2STASSTACKPTR
152848. DSP2TOPLOOPADDRSTACK
152849. DSP2TOPLOOPCOUNTSTACK
152850. DSP2XGPRAM_END
152851. DSP2XGPRAM_START
152852. DSP2XYRAMAGINDEX_END
152853. DSP2XYRAMAGINDEX_START
152854. DSP2XYRAMAGMDFR_END
152855. DSP2XYRAMAGMDFR_START
152856. DSP2XYRAMBASE_END
152857. DSP2XYRAMBASE_START
152858. DSP2XYRAMLENG_END
152859. DSP2XYRAMLENG_START
152860. DSP2YGPRAM_END
152861. DSP2YGPRAM_START
152862. DSP2_CONFIG
152863. DSP2_ON_OFF
152864. DSP3CONDCODE
152865. DSP3CURLOOPADDRREG
152866. DSP3CURLOOPCOUNT
152867. DSP3INTCONTLVEC_END
152868. DSP3INTCONTLVEC_START
152869. DSP3INTCONTMASKREG
152870. DSP3INTCONTPENDREG
152871. DSP3INTCONTSERVINT
152872. DSP3LOCALHWREG_END
152873. DSP3LOCALHWREG_START
152874. DSP3LOOPSTACKPTR
152875. DSP3PROGCOUNT
152876. DSP3PROGCOUNTSTACKDATAREG
152877. DSP3PROGCOUNTSTACKPTREG
152878. DSP3STACKFLAG
152879. DSP3STASSTACKDATAREG
152880. DSP3STASSTACKPTR
152881. DSP3TOPLOOPADDRSTACK
152882. DSP3TOPLOOPCOUNTSTACK
152883. DSP3XGPRAM_END
152884. DSP3XGPRAM_START
152885. DSP3XYRAMAGINDEX_END
152886. DSP3XYRAMAGINDEX_START
152887. DSP3XYRAMAGMDFR_END
152888. DSP3XYRAMAGMDFR_START
152889. DSP3XYRAMBASE_END
152890. DSP3XYRAMBASE_START
152891. DSP3XYRAMLENG_END
152892. DSP3XYRAMLENG_START
152893. DSP3YGPRAM_END
152894. DSP3YGPRAM_START
152895. DSP4I_FIRMWARE
152896. DSP4P_FIRMWARE
152897. DSP56K_CVR_HC
152898. DSP56K_CVR_HV_MASK
152899. DSP56K_DEV_56001
152900. DSP56K_HOST_CMD
152901. DSP56K_HOST_FLAGS
152902. DSP56K_HOST_INTERFACE
152903. DSP56K_HOST_INTERFACE_BASE
152904. DSP56K_ICR_HF0
152905. DSP56K_ICR_HF1
152906. DSP56K_ICR_HM0
152907. DSP56K_ICR_HM1
152908. DSP56K_ICR_INIT
152909. DSP56K_ICR_RREQ
152910. DSP56K_ICR_TREQ
152911. DSP56K_ISR_DMA
152912. DSP56K_ISR_HF2
152913. DSP56K_ISR_HF3
152914. DSP56K_ISR_HREQ
152915. DSP56K_ISR_RXDF
152916. DSP56K_ISR_TRDY
152917. DSP56K_ISR_TXDE
152918. DSP56K_MAJOR
152919. DSP56K_MAX_BINARY_LENGTH
152920. DSP56K_RECEIVE
152921. DSP56K_RX_INT_OFF
152922. DSP56K_RX_INT_ON
152923. DSP56K_SET_RX_WSIZE
152924. DSP56K_SET_TX_WSIZE
152925. DSP56K_TRANSMIT
152926. DSP56K_TX_INT_OFF
152927. DSP56K_TX_INT_ON
152928. DSP56K_UPLOAD
152929. DSP9I_FIRMWARE
152930. DSP9P_FIRMWARE
152931. DSPABASE
152932. DSPACNTR
152933. DSPADDR
152934. DSPAIMAP_END
152935. DSPAIMAP_START
152936. DSPAKEYMASK
152937. DSPAKEYVAL
152938. DSPALINOFF
152939. DSPAPOS
152940. DSPARB
152941. DSPARB2
152942. DSPARB3
152943. DSPARB_AEND_SHIFT
152944. DSPARB_BEND_SHIFT
152945. DSPARB_BSTART_MASK
152946. DSPARB_BSTART_SHIFT
152947. DSPARB_CSTART_MASK
152948. DSPARB_CSTART_SHIFT
152949. DSPARB_SPRITEA_HI_MASK_VLV
152950. DSPARB_SPRITEA_HI_SHIFT_VLV
152951. DSPARB_SPRITEA_MASK_VLV
152952. DSPARB_SPRITEA_SHIFT_VLV
152953. DSPARB_SPRITEB_HI_MASK_VLV
152954. DSPARB_SPRITEB_HI_SHIFT_VLV
152955. DSPARB_SPRITEB_MASK_VLV
152956. DSPARB_SPRITEB_SHIFT_VLV
152957. DSPARB_SPRITEC_HI_MASK_VLV
152958. DSPARB_SPRITEC_HI_SHIFT_VLV
152959. DSPARB_SPRITEC_MASK_VLV
152960. DSPARB_SPRITEC_SHIFT_VLV
152961. DSPARB_SPRITED_HI_MASK_VLV
152962. DSPARB_SPRITED_HI_SHIFT_VLV
152963. DSPARB_SPRITED_MASK_VLV
152964. DSPARB_SPRITED_SHIFT_VLV
152965. DSPARB_SPRITEE_HI_MASK_VLV
152966. DSPARB_SPRITEE_HI_SHIFT_VLV
152967. DSPARB_SPRITEE_MASK_VLV
152968. DSPARB_SPRITEE_SHIFT_VLV
152969. DSPARB_SPRITEF_HI_MASK_VLV
152970. DSPARB_SPRITEF_HI_SHIFT_VLV
152971. DSPARB_SPRITEF_MASK_VLV
152972. DSPARB_SPRITEF_SHIFT_VLV
152973. DSPASIZE
152974. DSPASTRIDE
152975. DSPASURF
152976. DSPATILEOFF
152977. DSPAUTO
152978. DSPAXRAM_END
152979. DSPAXRAM_START
152980. DSPAYRAM_END
152981. DSPAYRAM_START
152982. DSPBADDR
152983. DSPBBASE
152984. DSPBCNTR
152985. DSPBLINOFF
152986. DSPBPOS
152987. DSPBSIZE
152988. DSPBSTRIDE
152989. DSPBSURF
152990. DSPBTILEOFF
152991. DSPCBASE
152992. DSPCCNTR
152993. DSPCFG
152994. DSPCFG_COEF
152995. DSPCFG_LOCK
152996. DSPCFG_VAL
152997. DSPCHICKENBIT
152998. DSPCKEYMAXVAL
152999. DSPCKEYMINVAL
153000. DSPCKEYMSK
153001. DSPCLINOFF
153002. DSPCLKOFF_HWPCLKOFF
153003. DSPCLKOFF_HWPOFF
153004. DSPCLK_COUNT
153005. DSPCLK_DCEFCLK
153006. DSPCLK_DCFCLK
153007. DSPCLK_DISPCLK
153008. DSPCLK_GATE_D
153009. DSPCLK_PHYCLK
153010. DSPCLK_PIXCLK
153011. DSPCLK_e
153012. DSPCNTR
153013. DSPCPOS
153014. DSPCR_INIT_PARAM
153015. DSPCSIZE
153016. DSPCSTRIDE
153017. DSPCSURF
153018. DSPCTILEOFF
153019. DSPDMAC_ACTIVE_AAR_HIBIT
153020. DSPDMAC_ACTIVE_AAR_LOBIT
153021. DSPDMAC_ACTIVE_AAR_MASK
153022. DSPDMAC_ACTIVE_INST_OFFSET
153023. DSPDMAC_ACTIVE_MODULE_OFFSET
153024. DSPDMAC_ACTIVE_WFR_HIBIT
153025. DSPDMAC_ACTIVE_WFR_LOBIT
153026. DSPDMAC_ACTIVE_WFR_MASK
153027. DSPDMAC_AUDCHSEL_ACS_HIBIT
153028. DSPDMAC_AUDCHSEL_ACS_LOBIT
153029. DSPDMAC_AUDCHSEL_ACS_MASK
153030. DSPDMAC_AUDCHSEL_CHAN_INCR
153031. DSPDMAC_AUDCHSEL_INST_OFFSET
153032. DSPDMAC_AUDCHSEL_MODULE_OFFSET
153033. DSPDMAC_AUD_CHSEL_CHANNEL_COUNT
153034. DSPDMAC_CHIP_OFFSET
153035. DSPDMAC_CHNLPROP_AC_HIBIT
153036. DSPDMAC_CHNLPROP_AC_LOBIT
153037. DSPDMAC_CHNLPROP_AC_MASK
153038. DSPDMAC_CHNLPROP_DCON_HIBIT
153039. DSPDMAC_CHNLPROP_DCON_LOBIT
153040. DSPDMAC_CHNLPROP_DCON_MASK
153041. DSPDMAC_CHNLPROP_ENH_HIBIT
153042. DSPDMAC_CHNLPROP_ENH_LOBIT
153043. DSPDMAC_CHNLPROP_ENH_MASK
153044. DSPDMAC_CHNLPROP_FFS_HIBIT
153045. DSPDMAC_CHNLPROP_FFS_LOBIT
153046. DSPDMAC_CHNLPROP_FFS_MASK
153047. DSPDMAC_CHNLPROP_INST_OFFSET
153048. DSPDMAC_CHNLPROP_MODULE_OFFSET
153049. DSPDMAC_CHNLPROP_MSPCE_HIBIT
153050. DSPDMAC_CHNLPROP_MSPCE_LOBIT
153051. DSPDMAC_CHNLPROP_MSPCE_MASK
153052. DSPDMAC_CHNLPROP_NAJ_HIBIT
153053. DSPDMAC_CHNLPROP_NAJ_LOBIT
153054. DSPDMAC_CHNLPROP_NAJ_MASK
153055. DSPDMAC_CHNLSTART_DIS_HIBIT
153056. DSPDMAC_CHNLSTART_DIS_LOBIT
153057. DSPDMAC_CHNLSTART_DIS_MASK
153058. DSPDMAC_CHNLSTART_EN_HIBIT
153059. DSPDMAC_CHNLSTART_EN_LOBIT
153060. DSPDMAC_CHNLSTART_EN_MASK
153061. DSPDMAC_CHNLSTART_INST_OFFSET
153062. DSPDMAC_CHNLSTART_MODULE_OFFSET
153063. DSPDMAC_CHNLSTART_VAI1_HIBIT
153064. DSPDMAC_CHNLSTART_VAI1_LOBIT
153065. DSPDMAC_CHNLSTART_VAI1_MASK
153066. DSPDMAC_CHNLSTART_VAI2_HIBIT
153067. DSPDMAC_CHNLSTART_VAI2_LOBIT
153068. DSPDMAC_CHNLSTART_VAI2_MASK
153069. DSPDMAC_CHNLSTATUS_AIO_HIBIT
153070. DSPDMAC_CHNLSTATUS_AIO_LOBIT
153071. DSPDMAC_CHNLSTATUS_AIO_MASK
153072. DSPDMAC_CHNLSTATUS_AIU_HIBIT
153073. DSPDMAC_CHNLSTATUS_AIU_LOBIT
153074. DSPDMAC_CHNLSTATUS_AIU_MASK
153075. DSPDMAC_CHNLSTATUS_AOO_HIBIT
153076. DSPDMAC_CHNLSTATUS_AOO_LOBIT
153077. DSPDMAC_CHNLSTATUS_AOO_MASK
153078. DSPDMAC_CHNLSTATUS_AOU_HIBIT
153079. DSPDMAC_CHNLSTATUS_AOU_LOBIT
153080. DSPDMAC_CHNLSTATUS_AOU_MASK
153081. DSPDMAC_CHNLSTATUS_IEN_HIBIT
153082. DSPDMAC_CHNLSTATUS_IEN_LOBIT
153083. DSPDMAC_CHNLSTATUS_IEN_MASK
153084. DSPDMAC_CHNLSTATUS_INST_OFFSET
153085. DSPDMAC_CHNLSTATUS_ISC_HIBIT
153086. DSPDMAC_CHNLSTATUS_ISC_LOBIT
153087. DSPDMAC_CHNLSTATUS_ISC_MASK
153088. DSPDMAC_CHNLSTATUS_MODULE_OFFSET
153089. DSPDMAC_CHNLSTATUS_VAI0_HIBIT
153090. DSPDMAC_CHNLSTATUS_VAI0_LOBIT
153091. DSPDMAC_CHNLSTATUS_VAI0_MASK
153092. DSPDMAC_DMACFG_AICS_HIBIT
153093. DSPDMAC_DMACFG_AICS_LOBIT
153094. DSPDMAC_DMACFG_AICS_MASK
153095. DSPDMAC_DMACFG_AINCR_HIBIT
153096. DSPDMAC_DMACFG_AINCR_LOBIT
153097. DSPDMAC_DMACFG_AINCR_MASK
153098. DSPDMAC_DMACFG_AINCR_XANDY
153099. DSPDMAC_DMACFG_AINCR_XORY
153100. DSPDMAC_DMACFG_AJUMP_HIBIT
153101. DSPDMAC_DMACFG_AJUMP_LOBIT
153102. DSPDMAC_DMACFG_AJUMP_MASK
153103. DSPDMAC_DMACFG_AMODE_GINTLV
153104. DSPDMAC_DMACFG_AMODE_HIBIT
153105. DSPDMAC_DMACFG_AMODE_LINEAR
153106. DSPDMAC_DMACFG_AMODE_LOBIT
153107. DSPDMAC_DMACFG_AMODE_MASK
153108. DSPDMAC_DMACFG_AMODE_RSV1
153109. DSPDMAC_DMACFG_AMODE_WINTLV
153110. DSPDMAC_DMACFG_CHAN_INCR
153111. DSPDMAC_DMACFG_DBADR_HIBIT
153112. DSPDMAC_DMACFG_DBADR_LOBIT
153113. DSPDMAC_DMACFG_DBADR_MASK
153114. DSPDMAC_DMACFG_DWR_DMA_RD
153115. DSPDMAC_DMACFG_DWR_DMA_WR
153116. DSPDMAC_DMACFG_DWR_HIBIT
153117. DSPDMAC_DMACFG_DWR_LOBIT
153118. DSPDMAC_DMACFG_DWR_MASK
153119. DSPDMAC_DMACFG_INST_OFFSET
153120. DSPDMAC_DMACFG_LK_HIBIT
153121. DSPDMAC_DMACFG_LK_LOBIT
153122. DSPDMAC_DMACFG_LK_MASK
153123. DSPDMAC_DMACFG_LP_HIBIT
153124. DSPDMAC_DMACFG_LP_LOBIT
153125. DSPDMAC_DMACFG_LP_LOOPING
153126. DSPDMAC_DMACFG_LP_MASK
153127. DSPDMAC_DMACFG_LP_SINGLE
153128. DSPDMAC_DMACFG_MODULE_OFFSET
153129. DSPDMAC_DMA_CFG_CHANNEL_COUNT
153130. DSPDMAC_DSPADRGOFS_CHAN_INCR
153131. DSPDMAC_DSPADRGOFS_GBBFR_HIBIT
153132. DSPDMAC_DSPADRGOFS_GBBFR_LOBIT
153133. DSPDMAC_DSPADRGOFS_GBBFR_MASK
153134. DSPDMAC_DSPADRGOFS_GBOFS_HIBIT
153135. DSPDMAC_DSPADRGOFS_GBOFS_LOBIT
153136. DSPDMAC_DSPADRGOFS_GBOFS_MASK
153137. DSPDMAC_DSPADRGOFS_GBS_HIBIT
153138. DSPDMAC_DSPADRGOFS_GBS_LOBIT
153139. DSPDMAC_DSPADRGOFS_GBS_MASK
153140. DSPDMAC_DSPADRGOFS_GCBFR_HIBIT
153141. DSPDMAC_DSPADRGOFS_GCBFR_LOBIT
153142. DSPDMAC_DSPADRGOFS_GCBFR_MASK
153143. DSPDMAC_DSPADRGOFS_GCOFS_HIBIT
153144. DSPDMAC_DSPADRGOFS_GCOFS_LOBIT
153145. DSPDMAC_DSPADRGOFS_GCOFS_MASK
153146. DSPDMAC_DSPADRGOFS_GCS_HIBIT
153147. DSPDMAC_DSPADRGOFS_GCS_LOBIT
153148. DSPDMAC_DSPADRGOFS_GCS_MASK
153149. DSPDMAC_DSPADRGOFS_INST_OFFSET
153150. DSPDMAC_DSPADRGOFS_MODULE_OFFSET
153151. DSPDMAC_DSPADROFS_BOFS_HIBIT
153152. DSPDMAC_DSPADROFS_BOFS_LOBIT
153153. DSPDMAC_DSPADROFS_BOFS_MASK
153154. DSPDMAC_DSPADROFS_CHAN_INCR
153155. DSPDMAC_DSPADROFS_COFS_HIBIT
153156. DSPDMAC_DSPADROFS_COFS_LOBIT
153157. DSPDMAC_DSPADROFS_COFS_MASK
153158. DSPDMAC_DSPADROFS_INST_OFFSET
153159. DSPDMAC_DSPADROFS_MODULE_OFFSET
153160. DSPDMAC_DSPADRWOFS_CHAN_INCR
153161. DSPDMAC_DSPADRWOFS_INST_OFFSET
153162. DSPDMAC_DSPADRWOFS_MODULE_OFFSET
153163. DSPDMAC_DSPADRWOFS_WBBFR_HIBIT
153164. DSPDMAC_DSPADRWOFS_WBBFR_LOBIT
153165. DSPDMAC_DSPADRWOFS_WBBFR_MASK
153166. DSPDMAC_DSPADRWOFS_WBOFS_HIBIT
153167. DSPDMAC_DSPADRWOFS_WBOFS_LOBIT
153168. DSPDMAC_DSPADRWOFS_WBOFS_MASK
153169. DSPDMAC_DSPADRWOFS_WCBFR_HIBIT
153170. DSPDMAC_DSPADRWOFS_WCBFR_LOBIT
153171. DSPDMAC_DSPADRWOFS_WCBFR_MASK
153172. DSPDMAC_DSPADRWOFS_WCOFS_HIBIT
153173. DSPDMAC_DSPADRWOFS_WCOFS_LOBIT
153174. DSPDMAC_DSPADRWOFS_WCOFS_MASK
153175. DSPDMAC_DSP_ADR_GOFS_CHANNEL_COUNT
153176. DSPDMAC_DSP_ADR_OFS_CHANNEL_COUNT
153177. DSPDMAC_DSP_ADR_WOFS_CHANNEL_COUNT
153178. DSPDMAC_IRQCNT_BICNT_HIBIT
153179. DSPDMAC_IRQCNT_BICNT_LOBIT
153180. DSPDMAC_IRQCNT_BICNT_MASK
153181. DSPDMAC_IRQCNT_CHAN_INCR
153182. DSPDMAC_IRQCNT_CICNT_HIBIT
153183. DSPDMAC_IRQCNT_CICNT_LOBIT
153184. DSPDMAC_IRQCNT_CICNT_MASK
153185. DSPDMAC_IRQCNT_INST_OFFSET
153186. DSPDMAC_IRQCNT_MODULE_OFFSET
153187. DSPDMAC_IRQ_CNT_CHANNEL_COUNT
153188. DSPDMAC_XFRCNT_BCNT_HIBIT
153189. DSPDMAC_XFRCNT_BCNT_LOBIT
153190. DSPDMAC_XFRCNT_BCNT_MASK
153191. DSPDMAC_XFRCNT_CCNT_HIBIT
153192. DSPDMAC_XFRCNT_CCNT_LOBIT
153193. DSPDMAC_XFRCNT_CCNT_MASK
153194. DSPDMAC_XFRCNT_CHAN_INCR
153195. DSPDMAC_XFRCNT_INST_OFFSET
153196. DSPDMAC_XFRCNT_MODULE_OFFSET
153197. DSPDMAC_XFR_CNT_CHANNEL_COUNT
153198. DSPEIOC
153199. DSPEI_FIRMWARE
153200. DSPEP_FIRMWARE
153201. DSPFREQGUAR_MASK
153202. DSPFREQGUAR_MASK_CHV
153203. DSPFREQGUAR_SHIFT
153204. DSPFREQGUAR_SHIFT_CHV
153205. DSPFREQSTAT_MASK
153206. DSPFREQSTAT_MASK_CHV
153207. DSPFREQSTAT_SHIFT
153208. DSPFREQSTAT_SHIFT_CHV
153209. DSPFW1
153210. DSPFW2
153211. DSPFW3
153212. DSPFW4
153213. DSPFW5
153214. DSPFW6
153215. DSPFW7
153216. DSPFW7_CHV
153217. DSPFW8_CHV
153218. DSPFW9_CHV
153219. DSPFW_CURSORA_MASK
153220. DSPFW_CURSORA_SHIFT
153221. DSPFW_CURSORA_WM1_MASK
153222. DSPFW_CURSORA_WM1_SHIFT
153223. DSPFW_CURSORB_MASK
153224. DSPFW_CURSORB_SHIFT
153225. DSPFW_CURSORB_WM1_MASK
153226. DSPFW_CURSORB_WM1_SHIFT
153227. DSPFW_CURSORC_MASK
153228. DSPFW_CURSORC_SHIFT
153229. DSPFW_CURSORC_WM1_MASK
153230. DSPFW_CURSORC_WM1_SHIFT
153231. DSPFW_CURSOR_SR_MASK
153232. DSPFW_CURSOR_SR_SHIFT
153233. DSPFW_CURSOR_SR_WM1_MASK
153234. DSPFW_CURSOR_SR_WM1_SHIFT
153235. DSPFW_FBC_HPLL_SR_MASK
153236. DSPFW_FBC_HPLL_SR_SHIFT
153237. DSPFW_FBC_SR_EN
153238. DSPFW_FBC_SR_MASK
153239. DSPFW_FBC_SR_SHIFT
153240. DSPFW_HPLL_CURSOR_MASK
153241. DSPFW_HPLL_CURSOR_SHIFT
153242. DSPFW_HPLL_SR_EN
153243. DSPFW_HPLL_SR_MASK
153244. DSPFW_HPLL_SR_SHIFT
153245. DSPFW_PLANEA_HI_MASK
153246. DSPFW_PLANEA_HI_SHIFT
153247. DSPFW_PLANEA_MASK
153248. DSPFW_PLANEA_MASK_VLV
153249. DSPFW_PLANEA_SHIFT
153250. DSPFW_PLANEA_WM1_HI_MASK
153251. DSPFW_PLANEA_WM1_HI_SHIFT
153252. DSPFW_PLANEA_WM1_MASK
153253. DSPFW_PLANEA_WM1_SHIFT
153254. DSPFW_PLANEB_HI_MASK
153255. DSPFW_PLANEB_HI_SHIFT
153256. DSPFW_PLANEB_MASK
153257. DSPFW_PLANEB_MASK_VLV
153258. DSPFW_PLANEB_SHIFT
153259. DSPFW_PLANEB_WM1_HI_MASK
153260. DSPFW_PLANEB_WM1_HI_SHIFT
153261. DSPFW_PLANEB_WM1_MASK
153262. DSPFW_PLANEB_WM1_SHIFT
153263. DSPFW_PLANEC_HI_MASK
153264. DSPFW_PLANEC_HI_SHIFT
153265. DSPFW_PLANEC_MASK_VLV
153266. DSPFW_PLANEC_OLD_MASK
153267. DSPFW_PLANEC_OLD_SHIFT
153268. DSPFW_PLANEC_SHIFT
153269. DSPFW_PLANEC_WM1_HI_MASK
153270. DSPFW_PLANEC_WM1_HI_SHIFT
153271. DSPFW_PLANEC_WM1_MASK
153272. DSPFW_PLANEC_WM1_SHIFT
153273. DSPFW_SPRITEA_HI_MASK
153274. DSPFW_SPRITEA_HI_SHIFT
153275. DSPFW_SPRITEA_MASK
153276. DSPFW_SPRITEA_MASK_VLV
153277. DSPFW_SPRITEA_SHIFT
153278. DSPFW_SPRITEA_WM1_HI_MASK
153279. DSPFW_SPRITEA_WM1_HI_SHIFT
153280. DSPFW_SPRITEA_WM1_MASK
153281. DSPFW_SPRITEA_WM1_SHIFT
153282. DSPFW_SPRITEB_HI_MASK
153283. DSPFW_SPRITEB_HI_SHIFT
153284. DSPFW_SPRITEB_MASK
153285. DSPFW_SPRITEB_MASK_VLV
153286. DSPFW_SPRITEB_SHIFT
153287. DSPFW_SPRITEB_WM1_HI_MASK
153288. DSPFW_SPRITEB_WM1_HI_SHIFT
153289. DSPFW_SPRITEB_WM1_MASK
153290. DSPFW_SPRITEB_WM1_SHIFT
153291. DSPFW_SPRITEC_HI_MASK
153292. DSPFW_SPRITEC_HI_SHIFT
153293. DSPFW_SPRITEC_MASK_VLV
153294. DSPFW_SPRITEC_SHIFT
153295. DSPFW_SPRITEC_WM1_HI_MASK
153296. DSPFW_SPRITEC_WM1_HI_SHIFT
153297. DSPFW_SPRITEC_WM1_MASK
153298. DSPFW_SPRITEC_WM1_SHIFT
153299. DSPFW_SPRITED_HI_MASK
153300. DSPFW_SPRITED_HI_SHIFT
153301. DSPFW_SPRITED_MASK_VLV
153302. DSPFW_SPRITED_SHIFT
153303. DSPFW_SPRITED_WM1_HI_MASK
153304. DSPFW_SPRITED_WM1_HI_SHIFT
153305. DSPFW_SPRITED_WM1_MASK
153306. DSPFW_SPRITED_WM1_SHIFT
153307. DSPFW_SPRITEE_HI_MASK
153308. DSPFW_SPRITEE_HI_SHIFT
153309. DSPFW_SPRITEE_MASK_VLV
153310. DSPFW_SPRITEE_SHIFT
153311. DSPFW_SPRITEE_WM1_HI_MASK
153312. DSPFW_SPRITEE_WM1_HI_SHIFT
153313. DSPFW_SPRITEE_WM1_MASK
153314. DSPFW_SPRITEE_WM1_SHIFT
153315. DSPFW_SPRITEF_HI_MASK
153316. DSPFW_SPRITEF_HI_SHIFT
153317. DSPFW_SPRITEF_MASK_VLV
153318. DSPFW_SPRITEF_SHIFT
153319. DSPFW_SPRITEF_WM1_HI_MASK
153320. DSPFW_SPRITEF_WM1_HI_SHIFT
153321. DSPFW_SPRITEF_WM1_MASK
153322. DSPFW_SPRITEF_WM1_SHIFT
153323. DSPFW_SR_HI_MASK
153324. DSPFW_SR_HI_SHIFT
153325. DSPFW_SR_MASK
153326. DSPFW_SR_SHIFT
153327. DSPFW_SR_WM1_HI_MASK
153328. DSPFW_SR_WM1_HI_SHIFT
153329. DSPFW_SR_WM1_MASK
153330. DSPFW_SR_WM1_SHIFT
153331. DSPGAMC
153332. DSPHOWM
153333. DSPHOWM1
153334. DSPICS_RST_B
153335. DSPIC_RST_B
153336. DSPINT0
153337. DSPINTCONTEXTINTMODREG
153338. DSPI_DMA_BUFSIZE
153339. DSPI_DMA_MODE
153340. DSPI_EOQ_MODE
153341. DSPI_FIFO_SIZE
153342. DSPI_TCFQ_MODE
153343. DSPLINOFF
153344. DSPMICRO_END
153345. DSPMICRO_START
153346. DSPOFFRAMRET_HWPOFF
153347. DSPOFFSET
153348. DSPOFF_HWPOFF
153349. DSPPIMAP_END
153350. DSPPIMAP_START
153351. DSPPOCTL
153352. DSPPOMAP_END
153353. DSPPOMAP_START
153354. DSPPOS
153355. DSPP_0
153356. DSPP_1
153357. DSPP_2
153358. DSPP_3
153359. DSPP_IGC_COLOR0_RAM_LUTN
153360. DSPP_IGC_COLOR1_RAM_LUTN
153361. DSPP_IGC_COLOR2_RAM_LUTN
153362. DSPP_MAX
153363. DSPQ_BUFF_SIZE
153364. DSPQ_DATA_BUFF
153365. DSPQ_OFFSET
153366. DSPSIZE
153367. DSPSTRIDE
153368. DSPSURF
153369. DSPSURFLIVE
153370. DSPSURF_TO_PIPE
153371. DSPS_REG
153372. DSPTILEOFF
153373. DSPTOPC_BASED
153374. DSPWIN_SET
153375. DSPXRAM_END
153376. DSPXRAM_START
153377. DSPYRAM_END
153378. DSPYRAM_START
153379. DSP_3780I_CONFIG_SETTINGS
153380. DSP_56361
153381. DSP_AUDIOFORM_INVALID
153382. DSP_AUDIOFORM_MM_32BE
153383. DSP_AUDIOFORM_MM_32LE
153384. DSP_AUDIOFORM_MS_16LE
153385. DSP_AUDIOFORM_MS_24LE
153386. DSP_AUDIOFORM_MS_32LE
153387. DSP_AUDIOFORM_MS_8
153388. DSP_AUDIOFORM_SS_16LE
153389. DSP_AUDIOFORM_SS_24LE
153390. DSP_AUDIOFORM_SS_32BE
153391. DSP_AUDIOFORM_SS_32LE
153392. DSP_AUDIOFORM_SS_8
153393. DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE
153394. DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE
153395. DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE
153396. DSP_AUTO_CDCLK_GATE_DISABLE
153397. DSP_AUX_MEM_BASE
153398. DSP_BANK_BASE
153399. DSP_BASE
153400. DSP_BASE_ADDR
153401. DSP_BF_ACCEPT
153402. DSP_BF_DISABLE
153403. DSP_BF_ENABLE_KEY
153404. DSP_BF_REJECT
153405. DSP_BIND_CENTER_LFE
153406. DSP_BIND_FRONT
153407. DSP_BIND_HANDSET
153408. DSP_BIND_I2S
153409. DSP_BIND_MIC
153410. DSP_BIND_MODEM1
153411. DSP_BIND_MODEM2
153412. DSP_BIND_QUERY
153413. DSP_BIND_SPDIF
153414. DSP_BIND_SURR
153415. DSP_BOOT_DELAY_IN_MS
153416. DSP_BOOT_DOMAIN
153417. DSP_BUSMASTER_CFG_1
153418. DSP_BUSMASTER_CFG_2
153419. DSP_BusMasterCfg1Index
153420. DSP_BusMasterCfg2Index
153421. DSP_CAPTURE_INIT_LATENCY
153422. DSP_CAP_BATCH
153423. DSP_CAP_BIND
153424. DSP_CAP_COPROC
153425. DSP_CAP_DUPLEX
153426. DSP_CAP_MMAP
153427. DSP_CAP_MULTI
153428. DSP_CAP_REALTIME
153429. DSP_CAP_REVISION
153430. DSP_CAP_TRIGGER
153431. DSP_CHANNEL_MIXER_ROUTES
153432. DSP_CHIP_OFFSET
153433. DSP_CHIP_RESET
153434. DSP_CKCTL
153435. DSP_CLK_36MHZ_SELECT
153436. DSP_CLOCK_CONTROL_1
153437. DSP_CLOCK_CONTROL_2
153438. DSP_CLOCK_ENABLE
153439. DSP_CODE_BYTE_OFFSET
153440. DSP_CODE_BYTE_SIZE
153441. DSP_COMMAND
153442. DSP_COMMAND_GALAXY_8
153443. DSP_COMMAND_GALAXY_9
153444. DSP_COMMAND_GET_VERSION
153445. DSP_CONFIG
153446. DSP_CONFIG_REG_BASE
153447. DSP_CONF_JOIN
153448. DSP_CONF_SPLIT
153449. DSP_CONTROL
153450. DSP_CRYSTAL_VOICE_LATENCY
153451. DSP_CTRL1
153452. DSP_CTRL2
153453. DSP_CTRL3
153454. DSP_CTRL4
153455. DSP_ChipID
153456. DSP_ChipReset
153457. DSP_ClockControl_1
153458. DSP_ClockControl_2
153459. DSP_ConfigAddress
153460. DSP_ConfigData
153461. DSP_DATAVAIL
153462. DSP_DBGCNTL_EXEC_HIBIT
153463. DSP_DBGCNTL_EXEC_LOBIT
153464. DSP_DBGCNTL_EXEC_MASK
153465. DSP_DBGCNTL_INST_OFFSET
153466. DSP_DBGCNTL_MODULE_OFFSET
153467. DSP_DBGCNTL_SS_HIBIT
153468. DSP_DBGCNTL_SS_LOBIT
153469. DSP_DBGCNTL_SS_MASK
153470. DSP_DBGCNTL_STATE_HIBIT
153471. DSP_DBGCNTL_STATE_LOBIT
153472. DSP_DBGCNTL_STATE_MASK
153473. DSP_DEFAULT
153474. DSP_DELAY
153475. DSP_DIFFERED_COMMAND_MASK
153476. DSP_DMA_WRITE_BUFLEN_INIT
153477. DSP_DMA_WRITE_BUFLEN_OVLY
153478. DSP_DOWNLOADED
153479. DSP_DOWNLOADING
153480. DSP_DOWNLOAD_FAILED
153481. DSP_DOWNLOAD_INIT
153482. DSP_DRAM_ADDR_OFFSET
153483. DSP_DTMF_NPOINTS
153484. DSP_ECHO_OFF
153485. DSP_ECHO_ON
153486. DSP_EN
153487. DSP_ENABLE
153488. DSP_EXT_CMD_SET
153489. DSP_FIFO_SR_WM_MASK
153490. DSP_FIFO_SR_WM_SHIFT
153491. DSP_FLAG_MIDI_INPUT
153492. DSP_FLAG_PROFESSIONAL_SPDIF
153493. DSP_FLAG_SPDIF_NONAUDIO
153494. DSP_FNC_LOAD_3G_ASIC
153495. DSP_FNC_LOAD_GINA24_ASIC
153496. DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC
153497. DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC
153498. DSP_FNC_LOAD_LAYLA_ASIC
153499. DSP_FNC_LOAD_MONA_EXTERNAL_ASIC
153500. DSP_FNC_LOAD_MONA_PCI_CARD_ASIC
153501. DSP_FNC_SET_COMMPAGE_ADDR
153502. DSP_GPIO_DRIVER_ENABLE_15_8
153503. DSP_GPIO_MODE_15_8
153504. DSP_GPIO_OUTPUT_DATA_15_8
153505. DSP_GpioDriverEnable_15_8
153506. DSP_GpioModeControl_15_8
153507. DSP_GpioOutputData_15_8
153508. DSP_HBRIDGE_CFG_1
153509. DSP_HBRIDGE_CFG_2
153510. DSP_HBRIDGE_CONTROL
153511. DSP_HBUS_TIMER_CFG
153512. DSP_HBridgeCfg1Index
153513. DSP_HBridgeCfg2Index
153514. DSP_HBridgeControl
153515. DSP_HBusTimerCfgIndex
153516. DSP_HELP
153517. DSP_HOLD_VALID_INTR
153518. DSP_HOLD_VALID_INTR_CLR
153519. DSP_HOLD_VALID_INTR_EN
153520. DSP_HOLD_VALID_INTR_MASK
153521. DSP_IDLE
153522. DSP_IDLECT1
153523. DSP_IDLECT2
153524. DSP_IDLE_DELAY
153525. DSP_IDLE_MODE
153526. DSP_IEC958_CHANNEL
153527. DSP_INIT_MSS
153528. DSP_INT
153529. DSP_IPI_2420_PHYS
153530. DSP_IPI_2420_SIZE
153531. DSP_IPI_2420_VIRT
153532. DSP_ISA_PROT_CFG
153533. DSP_ISA_SLAVE_CONTROL
153534. DSP_Interrupt
153535. DSP_IsaProtCfgIndex
153536. DSP_IsaSlaveControl
153537. DSP_IsaSlaveStatus
153538. DSP_JITTER
153539. DSP_LBUS_TIMEOUT_DISABLE
153540. DSP_LBusTimeoutDisable
153541. DSP_LINE_NUM
153542. DSP_LINE_NUM_MASK
153543. DSP_LOAD_ATTEMPT_PERIOD
153544. DSP_LOOP_LATENCY
153545. DSP_MASK
153546. DSP_MAXAUDIOINPUTS
153547. DSP_MAXAUDIOOUTPUTS
153548. DSP_MAXFIFO_PM5_ENABLE
153549. DSP_MAXFIFO_PM5_STATUS
153550. DSP_MAXPIPES
153551. DSP_MAX_MODULES
153552. DSP_MAX_PCM_CHANNELS
153553. DSP_MAX_SCB_DESC
153554. DSP_MAX_SCB_NAME
153555. DSP_MAX_SRC_NR
153556. DSP_MAX_SYMBOLS
153557. DSP_MAX_SYMBOL_NAME
153558. DSP_MAX_TASK_DESC
153559. DSP_MAX_TASK_NAME
153560. DSP_MEM_2420_PHYS
153561. DSP_MEM_2420_SIZE
153562. DSP_MEM_2420_VIRT
153563. DSP_MIDI_OUT_FIFO_SIZE
153564. DSP_MIX_OFF
153565. DSP_MIX_ON
153566. DSP_MMU_2420_PHYS
153567. DSP_MMU_2420_SIZE
153568. DSP_MMU_2420_VIRT
153569. DSP_MU_CHAN_NUM
153570. DSP_MsaAddrHigh
153571. DSP_MsaAddrLow
153572. DSP_MsaDataDSISHigh
153573. DSP_MsaDataISLow
153574. DSP_MspBootDomain
153575. DSP_NUMIO
153576. DSP_OFF
153577. DSP_OFMT_RAW10
153578. DSP_OFMT_RAW8
153579. DSP_OFMT_RGB
153580. DSP_OFMT_YUV
153581. DSP_ON
153582. DSP_ON_OFF
153583. DSP_OPT_NOHARDWARE
153584. DSP_OPT_ULAW
153585. DSP_OUTPUT_MIXER_ROUTES
153586. DSP_PARAMETER_BYTE_OFFSET
153587. DSP_PARAMETER_BYTE_SIZE
153588. DSP_PASSKEY
153589. DSP_PCM_CENTER_LFE_CHANNEL
153590. DSP_PCM_MAIN_CHANNEL
153591. DSP_PCM_REAR_CHANNEL
153592. DSP_PCM_S71_CHANNEL
153593. DSP_PIPELINE_CFG
153594. DSP_PLANE_A_FIFO_WM1_SHIFT
153595. DSP_PLANE_B_FIFO_WM1_SHIFT
153596. DSP_PLANE_C_FIFO_WM_MASK
153597. DSP_PLANE_C_FIFO_WM_SHIFT
153598. DSP_PLAYBACK_INIT_LATENCY
153599. DSP_PLAY_ENHANCEMENT_LATENCY
153600. DSP_PLL_SOURCE_SHIFT
153601. DSP_PORT_COMMAND
153602. DSP_PORT_CONTROL_REG_A
153603. DSP_PORT_CONTROL_REG_B
153604. DSP_PORT_CONTROL_REG_C
153605. DSP_PORT_DATA_AVAIL
153606. DSP_PORT_MEMORY_DATA
153607. DSP_PORT_MEMORY_INDEX
153608. DSP_PORT_MEMORY_TYPE
153609. DSP_PORT_READ
153610. DSP_PORT_RESET
153611. DSP_PORT_STATUS
153612. DSP_PORT_TIMER_COUNT
153613. DSP_POWER_MGMT_CFG
153614. DSP_PRECISION
153615. DSP_PowerMgCfgIndex
153616. DSP_READ
153617. DSP_RECEIVE_OFF
153618. DSP_RECEIVE_ON
153619. DSP_REG
153620. DSP_RESET
153621. DSP_RESET_DISABLE
153622. DSP_RESET_ENABLE
153623. DSP_RESTORE
153624. DSP_RETRY
153625. DSP_RST
153626. DSP_RSTCT2
153627. DSP_RSTCT2_WD_PER_EN
153628. DSP_RSTX
153629. DSP_ReadAndClear
153630. DSP_SAMPLE_BYTE_OFFSET
153631. DSP_SAMPLE_BYTE_SIZE
153632. DSP_SAVE
153633. DSP_SHOW
153634. DSP_SIGNATURE
153635. DSP_SLEEP_SAVE_DSP_IDLECT2
153636. DSP_SLEEP_SAVE_SIZE
153637. DSP_SLEEP_SAVE_START
153638. DSP_SPACING
153639. DSP_SPDIF_STATUS_HW_ENABLED
153640. DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED
153641. DSP_SPDIF_STATUS_OUTPUT_ENABLED
153642. DSP_SPDIF_STATUS_PLAYBACK_OPEN
153643. DSP_SPEAKER_OUT_LATENCY
153644. DSP_SPOS_DC
153645. DSP_SPOS_DCDC
153646. DSP_SPOS_DCDCHI
153647. DSP_SPOS_DCDCLO
153648. DSP_SPOS_DC_DC
153649. DSP_SPOS_UU
153650. DSP_SPOS_UUHI
153651. DSP_SPOS_UULO
153652. DSP_SPOS_UUUU
153653. DSP_SQI_AVG_ERR
153654. DSP_SQI_ERR_DETECTED
153655. DSP_STATUS
153656. DSP_SYS_MMU_CONFIG
153657. DSP_SYS_MMU_CONFIG_EN_SHIFT
153658. DSP_SYS_REVISION
153659. DSP_TAP10
153660. DSP_TONE_PATT_OFF
153661. DSP_TONE_PATT_ON
153662. DSP_TXDATA_OFF
153663. DSP_TXDATA_ON
153664. DSP_TX_DEJITTER
153665. DSP_TX_DEJ_OFF
153666. DSP_UART_CFG_1
153667. DSP_UART_CFG_2
153668. DSP_UartCfg1Index
153669. DSP_UartCfg2Index
153670. DSP_VC_ACK_INT
153671. DSP_VC_ADD_AUDIO_BUFFER
153672. DSP_VC_GO_COMATOSE
153673. DSP_VC_METERS_OFF
153674. DSP_VC_METERS_ON
153675. DSP_VC_MIDI_WRITE
153676. DSP_VC_RESET
153677. DSP_VC_SET_GD_AUDIO_STATE
153678. DSP_VC_SET_LAYLA24_FREQUENCY_REG
153679. DSP_VC_SET_LAYLA_SAMPLE_RATE
153680. DSP_VC_SET_VMIXER_GAIN
153681. DSP_VC_START_TRANSFER
153682. DSP_VC_STOP_TRANSFER
153683. DSP_VC_TEST_ASIC
153684. DSP_VC_UPDATE_CLOCKS
153685. DSP_VC_UPDATE_FLAGS
153686. DSP_VC_UPDATE_INGAIN
153687. DSP_VC_UPDATE_OUTVOL
153688. DSP_VC_WRITE_CONTROL_REG
153689. DSP_VOL_CHANGE_RX
153690. DSP_VOL_CHANGE_TX
153691. DSP_VOL_IN
153692. DSP_VOL_OUT
153693. DSP_WRITE
153694. DSP_XCLKS_PER_QW
153695. DSR
153696. DSRCR
153697. DSRCR_ADCL
153698. DSRCR_FRCL
153699. DSRCR_HBCL
153700. DSRCR_MASK
153701. DSRCR_RICL
153702. DSRCR_TVCL
153703. DSRCR_VBCL
153704. DSRWP_DSR_BG_RQ
153705. DSRWP_DSR_MASK
153706. DSRWP_DSR_PRIORITY_0
153707. DSRWP_DSR_PRIORITY_1
153708. DSRWP_DSR_PRIORITY_2
153709. DSRWP_DSR_PRIORITY_3
153710. DSRWP_DSR_PRIORITY_MASK
153711. DSRWP_DSR_RQ_PENDING
153712. DSRXON
153713. DSR_ACT
153714. DSR_AOS
153715. DSR_AVAILABLE
153716. DSR_BOF
153717. DSR_BYTES
153718. DSR_CAF
153719. DSR_COA
153720. DSR_COF
153721. DSR_CTD
153722. DSR_DE
153723. DSR_DPS
153724. DSR_DWE
153725. DSR_EBD
153726. DSR_EOM
153727. DSR_EOT
153728. DSR_ERASE_STATUS
153729. DSR_ERR
153730. DSR_ESS
153731. DSR_ETAD
153732. DSR_ETBD
153733. DSR_IP
153734. DSR_MCO
153735. DSR_NVF
153736. DSR_ON
153737. DSR_PERROR
153738. DSR_PORT0
153739. DSR_PORT1
153740. DSR_PROGRAM_STATUS
153741. DSR_PSS
153742. DSR_READY_STATUS
153743. DSR_REF
153744. DSR_RPS
153745. DSR_RX
153746. DSR_SAD
153747. DSR_SELECT
153748. DSR_SVF
153749. DSR_TCO
153750. DSR_TIMEOUT
153751. DSR_TTD
153752. DSR_TX
153753. DSR_UDRF
153754. DSR_VPPS
153755. DSR_VTD
153756. DSR_WBF
153757. DSR_WCF
153758. DSR_WEF
153759. DSR_WNF
153760. DSR_WTD
153761. DSR_nACK
153762. DSR_nBUSY
153763. DSR_nFAULT
153764. DSR_nPRINT
153765. DSR_state
153766. DSSCMD_IREAD64_CR
153767. DSSCMD_IREAD64_CX
153768. DSSCMD_IWRITE64_CR
153769. DSSCMD_IWRITE64_CX
153770. DSSDBG
153771. DSSERR
153772. DSSINFO
153773. DSSR
153774. DSSR_ADC
153775. DSSR_DFB
153776. DSSR_FRM
153777. DSSR_HBK
153778. DSSR_RINT
153779. DSSR_TVR
153780. DSSR_VBK
153781. DSSR_VC0FB_DSA0
153782. DSSR_VC0FB_DSA1
153783. DSSR_VC0FB_DSA2
153784. DSSR_VC0FB_INIT
153785. DSSR_VC0FB_MASK
153786. DSSR_VC1FB_DSA0
153787. DSSR_VC1FB_DSA1
153788. DSSR_VC1FB_DSA2
153789. DSSR_VC1FB_INIT
153790. DSSR_VC1FB_MASK
153791. DSSUNIT_CLOCK_GATE_DISABLE
153792. DSSWARN
153793. DSS_CLK_AHB
153794. DSS_CLK_PCLK
153795. DSS_CLK_SRC_FCK
153796. DSS_CLK_SRC_HDMI_PLL
153797. DSS_CLK_SRC_PLL1_1
153798. DSS_CLK_SRC_PLL1_2
153799. DSS_CLK_SRC_PLL1_3
153800. DSS_CLK_SRC_PLL2_1
153801. DSS_CLK_SRC_PLL2_2
153802. DSS_CLK_SRC_PLL2_3
153803. DSS_CONTROL
153804. DSS_CTL1
153805. DSS_CTL2
153806. DSS_DSI_CONTENT_DCS
153807. DSS_DSI_CONTENT_GENERIC
153808. DSS_DVB
153809. DSS_HDMI_M_PCLK
153810. DSS_IO_PAD_MODE_BYPASS
153811. DSS_IO_PAD_MODE_RESET
153812. DSS_IO_PAD_MODE_RFBI
153813. DSS_MODEL_DRA7
153814. DSS_MODEL_OMAP2
153815. DSS_MODEL_OMAP3
153816. DSS_MODEL_OMAP4
153817. DSS_MODEL_OMAP5
153818. DSS_PLL_CONTROL
153819. DSS_PLL_DSI1
153820. DSS_PLL_DSI2
153821. DSS_PLL_HDMI
153822. DSS_PLL_MAX_HSDIVS
153823. DSS_PLL_TYPE_A
153824. DSS_PLL_TYPE_B
153825. DSS_PLL_VIDEO1
153826. DSS_PLL_VIDEO2
153827. DSS_REG
153828. DSS_REVISION
153829. DSS_SDI_CONTROL
153830. DSS_SDI_STATUS
153831. DSS_SECURITY_OP
153832. DSS_SUBSYS_NAME
153833. DSS_SYSCONFIG
153834. DSS_SYSSTATUS
153835. DSS_SZ_REGS
153836. DSS_VENC_TV_CLK
153837. DSS_WB_LCD1_MGR
153838. DSS_WB_LCD2_MGR
153839. DSS_WB_LCD3_MGR
153840. DSS_WB_OVL0
153841. DSS_WB_OVL1
153842. DSS_WB_OVL2
153843. DSS_WB_OVL3
153844. DSS_WB_TV_MGR
153845. DST
153846. DST1
153847. DST16BUF
153848. DST16BUF_DS_OFFSET2
153849. DST2
153850. DST32BUF
153851. DST32BUF_DS_OFFSET3
153852. DST4BUF
153853. DST4BUF_DS_OFFSET0
153854. DST8BUF
153855. DST8BUF_DS_OFFSET1
153856. DSTAGP
153857. DSTATE_DOT_CLOCK_GATING
153858. DSTATE_GFX_CLOCK_GATING
153859. DSTATE_GFX_RESET_I830
153860. DSTATE_PLL_D3_OFF
153861. DSTATUS
153862. DSTATUS2
153863. DSTATUS3
153864. DSTAT_REG
153865. DSTBASE
153866. DSTCACHE_CTLSTAT
153867. DSTCACHE_MODE
153868. DSTFORMAT
153869. DSTID_DPD
153870. DSTID_SCC
153871. DSTMODE
153872. DSTN_CONTROL
153873. DSTN_CONTROL_LG
153874. DSTPCLK
153875. DSTR_VERSION
153876. DSTS
153877. DSTSCLR
153878. DSTSIZE
153879. DSTS_ENUMSPD_FS
153880. DSTS_ENUMSPD_FS48
153881. DSTS_ENUMSPD_HS
153882. DSTS_ENUMSPD_LS
153883. DSTS_ENUMSPD_MASK
153884. DSTS_ENUMSPD_SHIFT
153885. DSTS_ERRATICERR
153886. DSTS_SOFFN
153887. DSTS_SOFFN_LIMIT
153888. DSTS_SOFFN_MASK
153889. DSTS_SOFFN_SHIFT
153890. DSTS_SUSPSTS
153891. DSTT_ADDR_MASK
153892. DSTT_ADDR_SHIFT
153893. DSTT_LENGTH_MASK
153894. DSTT_LENGTH_SHIFT
153895. DSTT_TYPE
153896. DSTVIDEO
153897. DSTXY
153898. DST_15BPP
153899. DST_16BPP
153900. DST_16BPP_ARGB4444
153901. DST_16BPP_VYUY422
153902. DST_16BPP_YVYU422
153903. DST_1BPP
153904. DST_24BPP
153905. DST_24_ROTATION_ENABLE
153906. DST_32BPP
153907. DST_32BPP_AYUV444
153908. DST_4BPP
153909. DST_8BPP
153910. DST_8BPP_RGB332
153911. DST_8BPP_RGB8
153912. DST_8BPP_Y8
153913. DST_ABT
153914. DST_ADDR
153915. DST_ADDR_MASK
153916. DST_ADDR_SHIFT
153917. DST_BASE_ADDR_REG
153918. DST_BRES_DEC
153919. DST_BRES_ERR
153920. DST_BRES_INC
153921. DST_BRES_LNTH
153922. DST_BRES_LNTH_SUB
153923. DST_BRES_SIGN
153924. DST_BRES_T1_LNTH
153925. DST_BRES_T2_LNTH
153926. DST_CA_DEBUG
153927. DST_CA_ERROR
153928. DST_CA_INFO
153929. DST_CA_NOTICE
153930. DST_CNTL
153931. DST_COLORKEY_CTRL_REG
153932. DST_COLORKEY_DR_MAX_REG
153933. DST_COLORKEY_DR_MIN_REG
153934. DST_COLOR_MODE_REG
153935. DST_COMMON_H
153936. DST_CRC
153937. DST_EOM
153938. DST_EOT
153939. DST_EQ_SRC
153940. DST_FACTOR_M0
153941. DST_FAKE_RTABLE
153942. DST_FEATURE_ECN_CA
153943. DST_FEATURE_ECN_MASK
153944. DST_FEATURE_MASK
153945. DST_HEIGHT
153946. DST_HEIGHT_WIDTH
153947. DST_HEIGHT_WIDTH_8
153948. DST_HEIGHT_WIDTH_BW
153949. DST_HEIGHT_Y
153950. DST_HOST
153951. DST_HOST_BIG_ENDIAN_EN
153952. DST_IG_ENABLE
153953. DST_IG_READ
153954. DST_IG_TS
153955. DST_IG_WRITE
153956. DST_INDEX
153957. DST_INT_RAW_REG
153958. DST_IP4
153959. DST_KEY_ENABLE
153960. DST_LAST_PEL
153961. DST_LEFT_TOP_REG
153962. DST_LENGTH_MASK
153963. DST_LENGTH_SHIFT
153964. DST_LINE_END
153965. DST_LINE_START
153966. DST_MAP_IB_MASK
153967. DST_MAP_IB_SHIFT
153968. DST_MAP_OB_MASK
153969. DST_MAP_OB_SHIFT
153970. DST_MASK
153971. DST_MAXBURST
153972. DST_METADATA
153973. DST_METRICS_FLAGS
153974. DST_METRICS_PTR
153975. DST_METRICS_READ_ONLY
153976. DST_METRICS_REFCOUNTED
153977. DST_NOCOUNT
153978. DST_NOPOLICY
153979. DST_NORMAL_DOUBLE
153980. DST_NOXFRM
153981. DST_OBSOLETE_DEAD
153982. DST_OBSOLETE_FORCE_CHK
153983. DST_OBSOLETE_KILL
153984. DST_OBSOLETE_NONE
153985. DST_OFFSET
153986. DST_OFFSET_MASK
153987. DST_OFF_PITCH
153988. DST_OP
153989. DST_OP_NO_MARK
153990. DST_OSB
153991. DST_OVR
153992. DST_PAT_DIRECT_REG
153993. DST_PIPE_CONFIG
153994. DST_PITCH
153995. DST_PITCH_MASK
153996. DST_PITCH_OFFSET
153997. DST_PITCH_OFFSET_C
153998. DST_POLYGON_ENABLE
153999. DST_POLYLINE_NONLAST
154000. DST_POLY_EDGE
154001. DST_PORT
154002. DST_PREFETCH
154003. DST_QUEUE_OFF_BASE
154004. DST_RASTER_STALL
154005. DST_RBIT
154006. DST_RBUF_0_BASEADDR_OFFSET
154007. DST_RBUF_0_ENDADDR_OFFSET
154008. DST_RBUF_0_FULL_MARK_OFFSET
154009. DST_RBUF_0_RDADDR_OFFSET
154010. DST_RBUF_0_WRADDR_OFFSET
154011. DST_RBUF_1_BASEADDR_OFFSET
154012. DST_RBUF_1_ENDADDR_OFFSET
154013. DST_RBUF_1_FULL_MARK_OFFSET
154014. DST_RBUF_1_RDADDR_OFFSET
154015. DST_RBUF_1_WRADDR_OFFSET
154016. DST_RBUF_2_BASEADDR_OFFSET
154017. DST_RBUF_2_ENDADDR_OFFSET
154018. DST_RBUF_2_FULL_MARK_OFFSET
154019. DST_RBUF_2_RDADDR_OFFSET
154020. DST_RBUF_2_WRADDR_OFFSET
154021. DST_RBUF_3_BASEADDR_OFFSET
154022. DST_RBUF_3_ENDADDR_OFFSET
154023. DST_RBUF_3_FULL_MARK_OFFSET
154024. DST_RBUF_3_RDADDR_OFFSET
154025. DST_RBUF_3_WRADDR_OFFSET
154026. DST_RBUF_4_BASEADDR_OFFSET
154027. DST_RBUF_4_ENDADDR_OFFSET
154028. DST_RBUF_4_FULL_MARK_OFFSET
154029. DST_RBUF_4_RDADDR_OFFSET
154030. DST_RBUF_4_WRADDR_OFFSET
154031. DST_RBUF_5_BASEADDR_OFFSET
154032. DST_RBUF_5_ENDADDR_OFFSET
154033. DST_RBUF_5_FULL_MARK_OFFSET
154034. DST_RBUF_5_RDADDR_OFFSET
154035. DST_RBUF_5_WRADDR_OFFSET
154036. DST_REWRITE_IP4
154037. DST_REWRITE_IP6_0
154038. DST_REWRITE_IP6_1
154039. DST_REWRITE_IP6_2
154040. DST_REWRITE_IP6_3
154041. DST_REWRITE_PORT4
154042. DST_REWRITE_PORT6
154043. DST_RIGHT_BOTTOM_REG
154044. DST_SEL
154045. DST_SELECT_REG
154046. DST_SHRT
154047. DST_STRIDE_REG
154048. DST_TRAIL_X_LEFT_TO_RIGHT
154049. DST_TRAIL_X_RIGHT_TO_LEFT
154050. DST_TRAP_FILL_LEFT_TO_RIGHT
154051. DST_TRAP_FILL_RIGHT_TO_LEFT
154052. DST_TYPE
154053. DST_TYPE_HAS_ANALOG
154054. DST_TYPE_HAS_CA
154055. DST_TYPE_HAS_DBOARD
154056. DST_TYPE_HAS_DISEQC3
154057. DST_TYPE_HAS_DISEQC4
154058. DST_TYPE_HAS_DISEQC5
154059. DST_TYPE_HAS_FW_1
154060. DST_TYPE_HAS_FW_2
154061. DST_TYPE_HAS_FW_3
154062. DST_TYPE_HAS_FW_BUILD
154063. DST_TYPE_HAS_INC_COUNT
154064. DST_TYPE_HAS_MAC
154065. DST_TYPE_HAS_MOTO
154066. DST_TYPE_HAS_MULTI_FE
154067. DST_TYPE_HAS_NEWTUNE_2
154068. DST_TYPE_HAS_OBS_REGS
154069. DST_TYPE_HAS_SESSION
154070. DST_TYPE_HAS_SYMDIV
154071. DST_TYPE_HAS_TS188
154072. DST_TYPE_HAS_TS204
154073. DST_TYPE_HAS_VLF
154074. DST_TYPE_IS_ATSC
154075. DST_TYPE_IS_CABLE
154076. DST_TYPE_IS_SAT
154077. DST_TYPE_IS_TERR
154078. DST_UDR
154079. DST_VPORT
154080. DST_WIDTH
154081. DST_WIDTH_HEIGHT
154082. DST_WIDTH_X
154083. DST_WIDTH_X_INCY
154084. DST_X
154085. DST_XFRM_QUEUE
154086. DST_XFRM_TUNNEL
154087. DST_X_LEFT_TO_RIGHT
154088. DST_X_LEFT_TO_RIGHT_S
154089. DST_X_MAJOR
154090. DST_X_MAJOR_S
154091. DST_X_RIGHT_TO_LEFT
154092. DST_X_RIGHT_TO_LEFT_S
154093. DST_X_SUB
154094. DST_X_TILE
154095. DST_X_WIDTH
154096. DST_X_Y
154097. DST_Y
154098. DST_Y_BOTTOM_TO_TOP
154099. DST_Y_BOTTOM_TO_TOP_S
154100. DST_Y_MAJOR
154101. DST_Y_MAJOR_S
154102. DST_Y_SUB
154103. DST_Y_TILE
154104. DST_Y_TOP_TO_BOTTOM
154105. DST_Y_TOP_TO_BOTTOM_S
154106. DST_Y_X
154107. DST_Y_X__ALIAS__
154108. DSU_ACTIVE_CPU_MASK
154109. DSU_ASSOCIATED_CPU_MASK
154110. DSU_CPUMASK_ATTR
154111. DSU_EVENT_ATTR
154112. DSU_EXT_ATTR
154113. DSU_FORMAT_ATTR
154114. DSU_PMU_COUNTER_MASK
154115. DSU_PMU_COUNTER_WIDTH
154116. DSU_PMU_EVT_CHAIN
154117. DSU_PMU_EVT_CYCLES
154118. DSU_PMU_HW_COUNTER_MASK
154119. DSU_PMU_IDX_CYCLE_COUNTER
154120. DSU_PMU_MAX_COMMON_EVENTS
154121. DSU_PMU_MAX_HW_CNTRS
154122. DSYSR
154123. DSYSR_DEN
154124. DSYSR_DRES
154125. DSYSR_DSEC
154126. DSYSR_ILTS
154127. DSYSR_IUPD
154128. DSYSR_SCM_INT_NONE
154129. DSYSR_SCM_INT_SYNC
154130. DSYSR_SCM_INT_VIDEO
154131. DSYSR_SCM_MASK
154132. DSYSR_TVM_MASK
154133. DSYSR_TVM_MASTER
154134. DSYSR_TVM_SWITCH
154135. DSYSR_TVM_TVSYNC
154136. DSZ
154137. DS_16ST_0
154138. DS_16ST_1
154139. DS_16ST_10
154140. DS_16ST_11
154141. DS_16ST_12
154142. DS_16ST_13
154143. DS_16ST_14
154144. DS_16ST_15
154145. DS_16ST_2
154146. DS_16ST_3
154147. DS_16ST_4
154148. DS_16ST_5
154149. DS_16ST_6
154150. DS_16ST_7
154151. DS_16ST_8
154152. DS_16ST_9
154153. DS_1BIT_IM_VAL
154154. DS_1BIT_MASK
154155. DS_2BIT_IM_VAL
154156. DS_2BIT_MASK
154157. DS_4BIT_IM_VAL
154158. DS_4BIT_MASK
154159. DS_4WE_0
154160. DS_4WE_1
154161. DS_4WE_2
154162. DS_4WE_3
154163. DS_ACTIVE
154164. DS_ADDS
154165. DS_CNFG
154166. DS_CONFIGURED
154167. DS_CONNECTED
154168. DS_DATA
154169. DS_DESTINATION_TIMEOUT
154170. DS_DFLT
154171. DS_DISABLED
154172. DS_DIV
154173. DS_DIV_MASK
154174. DS_DIV_SHIFT
154175. DS_ENABLED
154176. DS_ERROR
154177. DS_ERROR_SHRINK
154178. DS_ERROR_SPACE_MD
154179. DS_GREW
154180. DS_GREW_FROM_ZERO
154181. DS_HS_DONE
154182. DS_HS_START
154183. DS_HW_CAL_DIS
154184. DS_HW_CAL_EN
154185. DS_HW_CAL_ENABLE
154186. DS_IDLE
154187. DS_INITIALIZED
154188. DS_INIT_ACK
154189. DS_INIT_NACK
154190. DS_INIT_REQ
154191. DS_INVOCATION_COUNT
154192. DS_INVOCATION_COUNT_UDW
154193. DS_INV_HDL
154194. DS_IN_ERROR
154195. DS_IN_RECOVERY
154196. DS_IPC_DEFAULT
154197. DS_JITTER_COUNT_SRC_SEL
154198. DS_JITTER_COUNT_SRC_SEL0
154199. DS_JITTER_COUNT_SRC_SEL1
154200. DS_M31_0
154201. DS_M31_1
154202. DS_MASK
154203. DS_MTHD_NO_PIXEL_DROP
154204. DS_MTHD_PIXEL_DROP
154205. DS_NACK
154206. DS_NON_OPERATIONAL
154207. DS_NULL
154208. DS_OK
154209. DS_OPERATIONAL
154210. DS_PARA_IE_ID
154211. DS_PARA_IE_LEN
154212. DS_PG_CNTL
154213. DS_PG_CNTL_MASK
154214. DS_PG_CNTL_SHIFT
154215. DS_PG_EN
154216. DS_PG_EN_MASK
154217. DS_PG_EN_SHIFT
154218. DS_PORT_IN_RESET
154219. DS_POWR
154220. DS_PRI_DATA
154221. DS_PRI_REQUEST
154222. DS_PRI_UPDATE
154223. DS_RECEIVER
154224. DS_REF_IS_EXT_GENLOCK
154225. DS_REF_IS_PCIE
154226. DS_REF_IS_XTALIN
154227. DS_REF_SRC
154228. DS_REG_ACK
154229. DS_REG_DUP
154230. DS_REG_NACK
154231. DS_REG_REQ
154232. DS_REG_VER_NACK
154233. DS_REPEATER
154234. DS_SHIFT
154235. DS_SHRUNK
154236. DS_SH_DIV
154237. DS_SH_DIV_MASK
154238. DS_SH_DIV_SHIFT
154239. DS_SIZE
154240. DS_SOURCE_TIMEOUT
154241. DS_SPD_ADDR
154242. DS_SPD_CNFG
154243. DS_SPD_DFLT
154244. DS_SPD_POWR
154245. DS_STALLED
154246. DS_ST_ATBRR
154247. DS_ST_CMISS
154248. DS_ST_CMPLT
154249. DS_ST_EXEC
154250. DS_ST_FAULT
154251. DS_ST_FLTCMP
154252. DS_ST_KILL
154253. DS_ST_QBUSY
154254. DS_ST_STOP
154255. DS_ST_UPDTPC
154256. DS_ST_WFE
154257. DS_ST_WFP
154258. DS_SUSP
154259. DS_SYNC
154260. DS_TO_FS
154261. DS_TYPE
154262. DS_TYPE_UNKNOWN
154263. DS_UNCHANGED
154264. DS_UNKNOWN
154265. DS_UNREG_ACK
154266. DS_UNREG_NACK
154267. DS_UNREG_REQ
154268. DS_VAR_DELETE_REQ
154269. DS_VAR_DELETE_RESP
154270. DS_VAR_INVALID_VAL
154271. DS_VAR_INVALID_VAR
154272. DS_VAR_NOT_PRESENT
154273. DS_VAR_NO_SPACE
154274. DS_VAR_SET_REQ
154275. DS_VAR_SET_RESP
154276. DS_VAR_SUCCESS
154277. DT2801_CMD
154278. DT2801_DATA
154279. DT2801_MAX_DMA_SIZE
154280. DT2801_STATUS
154281. DT2801_TIMEOUT
154282. DT2811_ADCSR_ADBUSY
154283. DT2811_ADCSR_ADDONE
154284. DT2811_ADCSR_ADERROR
154285. DT2811_ADCSR_ADMODE
154286. DT2811_ADCSR_CLRERROR
154287. DT2811_ADCSR_DMAENB
154288. DT2811_ADCSR_INTENB
154289. DT2811_ADCSR_REG
154290. DT2811_ADDATA_HI_REG
154291. DT2811_ADDATA_LO_REG
154292. DT2811_ADGCR_CHAN
154293. DT2811_ADGCR_GAIN
154294. DT2811_ADGCR_REG
154295. DT2811_DADATA_HI_REG
154296. DT2811_DADATA_LO_REG
154297. DT2811_DI_REG
154298. DT2811_DO_REG
154299. DT2811_OSC_BASE
154300. DT2811_TMRCTR_EXPONENT
154301. DT2811_TMRCTR_MANTISSA
154302. DT2811_TMRCTR_REG
154303. DT2814_BUSY
154304. DT2814_CHANMASK
154305. DT2814_CSR
154306. DT2814_DATA
154307. DT2814_ENB
154308. DT2814_ERR
154309. DT2814_FINISH
154310. DT2814_MAX_SPEED
154311. DT2814_TIMEOUT
154312. DT2815_DATA
154313. DT2815_STATUS
154314. DT2817_CR
154315. DT2817_DATA
154316. DT2821_ADCSR_ADCLK
154317. DT2821_ADCSR_ADDONE
154318. DT2821_ADCSR_ADERR
154319. DT2821_ADCSR_CHAN
154320. DT2821_ADCSR_GS
154321. DT2821_ADCSR_IADDONE
154322. DT2821_ADCSR_MUXBUSY
154323. DT2821_ADCSR_REG
154324. DT2821_ADDAT_REG
154325. DT2821_CHANCSR_LLE
154326. DT2821_CHANCSR_NUMB
154327. DT2821_CHANCSR_REG
154328. DT2821_CHANCSR_TO_PRESLA
154329. DT2821_DACSR_DACLK
154330. DT2821_DACSR_DACRDY
154331. DT2821_DACSR_DAERR
154332. DT2821_DACSR_HBOE
154333. DT2821_DACSR_IDARDY
154334. DT2821_DACSR_LBOE
154335. DT2821_DACSR_REG
154336. DT2821_DACSR_SSEL
154337. DT2821_DACSR_YSEL
154338. DT2821_DADAT_REG
154339. DT2821_DIODAT_REG
154340. DT2821_DIVIDER_MAX
154341. DT2821_OSC_BASE
154342. DT2821_OSC_MAX
154343. DT2821_PRESCALE
154344. DT2821_PRESCALE_MAX
154345. DT2821_SUPCSR_ADCINIT
154346. DT2821_SUPCSR_BDINIT
154347. DT2821_SUPCSR_BUFFB
154348. DT2821_SUPCSR_CLRDMADNE
154349. DT2821_SUPCSR_DACINIT
154350. DT2821_SUPCSR_DACON
154351. DT2821_SUPCSR_DDMA
154352. DT2821_SUPCSR_DMAD
154353. DT2821_SUPCSR_DS
154354. DT2821_SUPCSR_DS_AD_CLK
154355. DT2821_SUPCSR_DS_AD_TRIG
154356. DT2821_SUPCSR_DS_DA_CLK
154357. DT2821_SUPCSR_DS_PIO
154358. DT2821_SUPCSR_ERRINTEN
154359. DT2821_SUPCSR_PRLD
154360. DT2821_SUPCSR_REG
154361. DT2821_SUPCSR_SCDN
154362. DT2821_SUPCSR_STRIG
154363. DT2821_SUPCSR_XCLK
154364. DT2821_SUPCSR_XTRIG
154365. DT2821_TMRCTR_DIVIDER
154366. DT2821_TMRCTR_PRESCALE
154367. DT2821_TMRCTR_REG
154368. DT2IF
154369. DT3155_DEVICE_ID
154370. DT3155_ID
154371. DT3155_NAME
154372. DT3155_VERSION
154373. DT3155_VER_EXT
154374. DT3155_VER_MAJ
154375. DT3155_VER_MIN
154376. DT8THPGNODEBYTES
154377. DT8THPGNODESLOTS
154378. DT8THPGNODETSLOTS
154379. DT9812_CALIBRATE_POT
154380. DT9812_DEVID_DT9812_10
154381. DT9812_DEVID_DT9812_2PT5
154382. DT9812_DIAGS_BOARD_INFO_ADDR
154383. DT9812_GAIN_0PT25
154384. DT9812_GAIN_0PT5
154385. DT9812_GAIN_1
154386. DT9812_GAIN_16
154387. DT9812_GAIN_2
154388. DT9812_GAIN_4
154389. DT9812_GAIN_8
154390. DT9812_LEAST_USB_FIRMWARE_CMD_CODE
154391. DT9812_MAX_NUM_MULTI_BYTE_RDS
154392. DT9812_MAX_NUM_MULTI_BYTE_RMWS
154393. DT9812_MAX_NUM_MULTI_BYTE_WRTS
154394. DT9812_MAX_READ_CMD_PIPE_SIZE
154395. DT9812_MAX_USB_FIRMWARE_CMD_CODE
154396. DT9812_MAX_WRITE_CMD_PIPE_SIZE
154397. DT9812_RMW_MULTI_BYTE_REG
154398. DT9812_RMW_SINGLE_BYTE_REG
154399. DT9812_R_FLASH_DATA
154400. DT9812_R_MULTI_BYTE_DEV
154401. DT9812_R_MULTI_BYTE_REG
154402. DT9812_R_MULTI_BYTE_SMBUS
154403. DT9812_R_MULTI_BYTE_USBMEM
154404. DT9812_R_SINGLE_BYTE_DEV
154405. DT9812_R_SINGLE_BYTE_REG
154406. DT9812_R_SINGLE_BYTE_SMBUS
154407. DT9812_R_SINGLE_VALUE_CMD
154408. DT9812_START_SUBSYSTEM
154409. DT9812_STOP_SUBSYSTEM
154410. DT9812_USB_TIMEOUT
154411. DT9812_W_CGL
154412. DT9812_W_CGL_DAC
154413. DT9812_W_DAC_FIFO_SIZE
154414. DT9812_W_DAC_THRESHOLD
154415. DT9812_W_FLASH_DATA
154416. DT9812_W_INT_ON_CHANGE_MASK
154417. DT9812_W_MULTI_BYTE_DEV
154418. DT9812_W_MULTI_BYTE_REG
154419. DT9812_W_MULTI_BYTE_SMBUS
154420. DT9812_W_MULTI_BYTE_USBMEM
154421. DT9812_W_SINGLE_BYTE_DEV
154422. DT9812_W_SINGLE_BYTE_REG
154423. DT9812_W_SINGLE_BYTE_SMBUS
154424. DT9812_W_SINGLE_VALUE_CMD
154425. DTADR
154426. DTAERROR_NO_METHOD_STATUS
154427. DTAG_MASK
154428. DTB
154429. DTBC
154430. DTB_EXTRA_SPACE
154431. DTC
154432. DTCH
154433. DTCHE
154434. DTCLR
154435. DTCM1_CK
154436. DTCM2_CK
154437. DTCMR
154438. DTCM_OFFSET
154439. DTCN0
154440. DTCR
154441. DTCR0
154442. DTCR_CTE
154443. DTCR_EBE
154444. DTCR_ETAE
154445. DTCR_ETBE
154446. DTCR_MOE
154447. DTCR_SAIE
154448. DTCR_TOE
154449. DTCR_TTE
154450. DTCR_VTE
154451. DTCR_WTE
154452. DTC_0
154453. DTC_0_MASK
154454. DTC_0_SHIFT
154455. DTC_H
154456. DTC_VERSION
154457. DTD_1D_MASK
154458. DTD_1D_SHFT
154459. DTD_ADDR_MASK
154460. DTD_ALIGNMENT
154461. DTD_CHAN_MASK
154462. DTD_CHAN_SHFT
154463. DTD_DATA_TYPE_MASK
154464. DTD_DATA_TYPE_SHFT
154465. DTD_DESC_START_MASK
154466. DTD_DESC_START_SHIFT
154467. DTD_DIR_IN
154468. DTD_DIR_MASK
154469. DTD_DIR_OUT
154470. DTD_DIR_SHFT
154471. DTD_DROP_DATA_MASK
154472. DTD_DROP_DATA_SHIFT
154473. DTD_ERROR_MASK
154474. DTD_EVEN_LINE_SKIP_MASK
154475. DTD_EVEN_LINE_SKIP_SHFT
154476. DTD_FIELD_MASK
154477. DTD_FIELD_SHFT
154478. DTD_FLAG_HSYNC_POSITIVE
154479. DTD_FLAG_INTERLACE
154480. DTD_FLAG_VSYNC_POSITIVE
154481. DTD_FRAME_HEIGHT_MASK
154482. DTD_FRAME_HEIGHT_SHFT
154483. DTD_FRAME_WIDTH_MASK
154484. DTD_FRAME_WIDTH_SHFT
154485. DTD_HANGOVER
154486. DTD_H_START_MASK
154487. DTD_H_START_SHFT
154488. DTD_IOC
154489. DTD_LENGTH_BIT_POS
154490. DTD_LINE_LENGTH_MASK
154491. DTD_LINE_LENGTH_SHFT
154492. DTD_LINE_STRIDE_MASK
154493. DTD_LINE_STRIDE_SHFT
154494. DTD_MAX_HEIGHT_MASK
154495. DTD_MAX_HEIGHT_SHFT
154496. DTD_MAX_WIDTH_MASK
154497. DTD_MAX_WIDTH_SHFT
154498. DTD_MODE_MASK
154499. DTD_MODE_SHFT
154500. DTD_NEXT_CHAN_MASK
154501. DTD_NEXT_CHAN_SHFT
154502. DTD_NEXT_TERMINATE
154503. DTD_NOTIFY
154504. DTD_NOTIFY_MASK
154505. DTD_NOTIFY_SHFT
154506. DTD_NO_NOTIFY
154507. DTD_ODD_LINE_SKIP_MASK
154508. DTD_ODD_LINE_SKIP_SHFT
154509. DTD_PACKET_SIZE
154510. DTD_PKT_TYPE
154511. DTD_PKT_TYPE_MASK
154512. DTD_PKT_TYPE_SHFT
154513. DTD_PRI_MASK
154514. DTD_PRI_SHFT
154515. DTD_RESERVED_FIELDS
154516. DTD_STATUS_ACTIVE
154517. DTD_STATUS_DATA_BUFF_ERR
154518. DTD_STATUS_HALTED
154519. DTD_STATUS_TRANSACTION_ERR
154520. DTD_USE_DESC_MASK
154521. DTD_USE_DESC_SHIFT
154522. DTD_V_START_MASK
154523. DTD_V_START_SHFT
154524. DTD_WRITE_DESC_MASK
154525. DTD_WRITE_DESC_SHIFT
154526. DTD_XFER_HEIGHT_MASK
154527. DTD_XFER_HEIGHT_SHFT
154528. DTEN
154529. DTENTRYSTART
154530. DTER0
154531. DTERR
154532. DTE_ADDR_DUMMY
154533. DTE_FLAG_GV
154534. DTE_FLAG_IOTLB
154535. DTE_FLAG_IR
154536. DTE_FLAG_IW
154537. DTE_FLAG_MASK
154538. DTE_FLAG_TV
154539. DTE_FLAG_V
154540. DTE_GCR3_INDEX_A
154541. DTE_GCR3_INDEX_B
154542. DTE_GCR3_INDEX_C
154543. DTE_GCR3_SHIFT_A
154544. DTE_GCR3_SHIFT_B
154545. DTE_GCR3_SHIFT_C
154546. DTE_GCR3_VAL_A
154547. DTE_GCR3_VAL_B
154548. DTE_GCR3_VAL_C
154549. DTE_GLX_MASK
154550. DTE_GLX_SHIFT
154551. DTE_IRQ_PHYS_ADDR_MASK
154552. DTE_IRQ_REMAP_ENABLE
154553. DTE_IRQ_REMAP_INTCTL
154554. DTE_IRQ_REMAP_INTCTL_MASK
154555. DTE_IRQ_TABLE_LEN
154556. DTE_IRQ_TABLE_LEN_MASK
154557. DTE_NCO_INC_DEFAULT
154558. DTE_NCO_INC_REG
154559. DTE_NCO_LOW_TIME_REG
154560. DTE_NCO_MAX_NS
154561. DTE_NCO_OVERFLOW_REG
154562. DTE_NCO_SUM2_MASK
154563. DTE_NCO_SUM2_SHIFT
154564. DTE_NCO_SUM3_MASK
154565. DTE_NCO_SUM3_SHIFT
154566. DTE_NCO_SUM3_WR_SHIFT
154567. DTE_NCO_TIME_REG
154568. DTE_NCO_TS_WRAP_LSHIFT
154569. DTE_NCO_TS_WRAP_MASK
154570. DTE_NUM_REGS_TO_RESTORE
154571. DTE_PPB_ADJ
154572. DTE_WRAP_AROUND_NSEC_SHIFT
154573. DTFULLPGNODEBYTES
154574. DTFULLPGNODESLOTS
154575. DTFULLPGNODETSLOTS
154576. DTF_RD_MASK
154577. DTF_RD_WR_MASK
154578. DTF_WR_MASK
154579. DTF_WR_RD_MASK
154580. DTG_CONTROL
154581. DTG_CTL_ENABLE
154582. DTG_CTL_SCREEN_REFRESH
154583. DTG_HORIZ_DISPLAY
154584. DTG_HORIZ_EXTENT
154585. DTG_HSYNC_END
154586. DTG_HSYNC_END_COMP
154587. DTG_HSYNC_START
154588. DTG_VERT_DISPLAY
154589. DTG_VERT_EXTENT
154590. DTG_VERT_SHORT
154591. DTG_VSYNC_END
154592. DTG_VSYNC_START
154593. DTHALFPGNODEBYTES
154594. DTHALFPGNODESLOTS
154595. DTHALFPGNODETSLOTS
154596. DTIAdapter
154597. DTIHDRDATALEN
154598. DTIHDRSIZE
154599. DTIM_EXPIRED
154600. DTIM_FALSE
154601. DTIM_PERIOD_AVAIL
154602. DTIM_PERIOD_I
154603. DTIM_TRUE
154604. DTK
154605. DTKNQR1
154606. DTKNQR2
154607. DTKNQR3
154608. DTKNQR4
154609. DTK_ADDR_SPACE_I2C_TYPE_II
154610. DTK_ADDR_SPACE_I2C_TYPE_III
154611. DTK_ADDR_SPACE_XDATA
154612. DTLB_ARF_WAYS
154613. DTLB_FIXED
154614. DTLB_HIT_BIT
154615. DTLB_LAST_VAR_UNRESTRICTED
154616. DTLB_LOAD_MISS
154617. DTLB_MR_MASK
154618. DTLB_OFFSET
154619. DTLB_REAL_MISS_EXITS
154620. DTLB_SMP_CONVERT_MASK
154621. DTLB_TR_MASK
154622. DTLB_UP_CONVERT_MASK
154623. DTLB_VIRT_MISS_EXITS
154624. DTLB_WAY_PGD
154625. DTLHDRDATALEN
154626. DTLHDRDATALEN_LEGACY
154627. DTLHDRSIZE
154628. DTLK_CLEAR
154629. DTLK_INTERROGATE
154630. DTLK_IO_EXTENT
154631. DTLK_MAX_RETRIES
154632. DTLK_MINOR
154633. DTLK_STATUS
154634. DTLN
154635. DTLN_MASK
154636. DTLOCK
154637. DTL_LOG_ALL
154638. DTL_LOG_CEDE
154639. DTL_LOG_FAULT
154640. DTL_LOG_PREEMPT
154641. DTMF_HFC_COEF
154642. DTMF_TONE_MASK
154643. DTMF_TONE_START
154644. DTMF_TONE_STOP
154645. DTMF_TONE_VAL
154646. DTMISS
154647. DTMR0
154648. DTN_INFO
154649. DTN_INFO_BEGIN
154650. DTN_INFO_END
154651. DTN_INFO_MICRO_SEC
154652. DTO
154653. DTO_EN
154654. DTO_LOAD
154655. DTO_LSB_FIRST
154656. DTO_MASK
154657. DTO_MSB_FIRST
154658. DTO_RESL_DOUBLE
154659. DTO_RESL_NORMAL
154660. DTO_SHIFT
154661. DTO_SOURCE_ID0
154662. DTO_SOURCE_ID1
154663. DTO_SOURCE_ID2
154664. DTO_SOURCE_ID3
154665. DTO_SOURCE_ID4
154666. DTO_SOURCE_ID5
154667. DTO_SOURCE_UNKNOWN
154668. DTPAGEMAXSLOT
154669. DTPR0
154670. DTPR1
154671. DTQTRPGNODEBYTES
154672. DTQTRPGNODESLOTS
154673. DTQTRPGNODETSLOTS
154674. DTR
154675. DTRACE
154676. DTRAN_CTRL_DM_START
154677. DTRAN_MODE_ADDR_MODE
154678. DTRAN_MODE_BUS_WIDTH
154679. DTRAN_MODE_CH_NUM_CH0
154680. DTRAN_MODE_CH_NUM_CH1
154681. DTRC_ARID
154682. DTRC_ARID0
154683. DTRC_ARID0_MASK
154684. DTRC_ARID0_SHIFT
154685. DTRC_ARID1
154686. DTRC_ARID1_MASK
154687. DTRC_ARID1_SHIFT
154688. DTRC_ARID2
154689. DTRC_ARID2_MASK
154690. DTRC_ARID2_SHIFT
154691. DTRC_ARID3
154692. DTRC_ARID3_MASK
154693. DTRC_ARID3_SHIFT
154694. DTRC_DEC2DDR_ARID
154695. DTRC_DECOMPRESS_BYPASS
154696. DTRC_DETILE_CTRL
154697. DTRC_F0_CTRL
154698. DTRC_F1_CTRL
154699. DTRIG_SUSPEND_ESCAPE
154700. DTRIG_UNKNOWN
154701. DTRIG_VECTOR_CI
154702. DTROOTMAXSLOT
154703. DTRR0
154704. DTRREQ
154705. DTRXOFF
154706. DTR_ON
154707. DTR_OP
154708. DTR_PORT0
154709. DTR_PORT1
154710. DTR_TST_CLRFF
154711. DTSC_CFG_MODE
154712. DTSC_CFG_MODE_PERIODIC
154713. DTSC_PTAT_AVG
154714. DTSC_VREF5_AVG
154715. DTSC_VREF_AVG
154716. DTSEC_ECNTRL_GMIIM
154717. DTSEC_ECNTRL_QSGMIIM
154718. DTSEC_ECNTRL_R100M
154719. DTSEC_ECNTRL_RPM
154720. DTSEC_ECNTRL_SGMIIM
154721. DTSEC_ECNTRL_TBIM
154722. DTSEC_EVENTS_MASK
154723. DTSEC_HASH_TABLE_SIZE
154724. DTSEC_ID2_INT_REDUCED_OFF
154725. DTSEC_IMASK_ABRTEN
154726. DTSEC_IMASK_BREN
154727. DTSEC_IMASK_BTEN
154728. DTSEC_IMASK_CRLEN
154729. DTSEC_IMASK_GRSCEN
154730. DTSEC_IMASK_GTSCEN
154731. DTSEC_IMASK_IFERREN
154732. DTSEC_IMASK_LCEN
154733. DTSEC_IMASK_MAGEN
154734. DTSEC_IMASK_MMRDEN
154735. DTSEC_IMASK_MMWREN
154736. DTSEC_IMASK_MSROEN
154737. DTSEC_IMASK_RDPEEN
154738. DTSEC_IMASK_RXCEN
154739. DTSEC_IMASK_TDPEEN
154740. DTSEC_IMASK_TXCEN
154741. DTSEC_IMASK_TXEEN
154742. DTSEC_IMASK_XFUNEN
154743. DTSEC_SUPPORTED
154744. DTSF_APPLY_FAIL
154745. DTSF_PLUGIN
154746. DTSF_REVERT_FAIL
154747. DTSF_V1
154748. DTSLOTDATALEN
154749. DTSLOTDATASIZE
154750. DTSLOTHDRSIZE
154751. DTSLOTSIZE
154752. DTS_AUTOMATIC
154753. DTS_BIT6_MODE
154754. DTS_BIT8_MODE
154755. DTS_CFGR1_OFFSET
154756. DTS_CIFR_OFFSET
154757. DTS_CRIT
154758. DTS_CRIT_HYST
154759. DTS_DIODE_REG_DIG_VAL
154760. DTS_DIODE_REG_FLAGS_MSK
154761. DTS_DIODE_REG_FLAGS_PASS_ONCE
154762. DTS_DIODE_REG_FLAGS_PASS_ONCE_POS
154763. DTS_DIODE_REG_FLAGS_VREFS_ID
154764. DTS_DIODE_REG_FLAGS_VREFS_ID_POS
154765. DTS_DIODE_REG_PASS_ONCE
154766. DTS_DIODE_REG_VREF_HIGH
154767. DTS_DIODE_REG_VREF_ID
154768. DTS_DIODE_REG_VREF_LOW
154769. DTS_DIRECT_WITHOUT_MEASURE
154770. DTS_DR_OFFSET
154771. DTS_ITENR_OFFSET
154772. DTS_ITR1_OFFSET
154773. DTS_MEASUREMENT_NOTIFICATION
154774. DTS_MEASUREMENT_NOTIF_WIDE
154775. DTS_OVER_WRITE
154776. DTS_RAMPVALR_OFFSET
154777. DTS_REQUEST_READ
154778. DTS_SR_OFFSET
154779. DTS_T0VALR1_OFFSET
154780. DTS_TRIGGER_CMD_FLAGS_TEMP
154781. DTS_TRIGGER_CMD_FLAGS_VOLT
154782. DTS_T_CPU1_CH_REG
154783. DTS_T_CPU1_C_REG
154784. DTS_T_CPU1_WH_REG
154785. DTS_T_CPU1_W_REG
154786. DTS_T_CTRL0_REG
154787. DTS_T_CTRL1_REG
154788. DTS_USE_CHAIN_A
154789. DTS_USE_CHAIN_B
154790. DTS_USE_CHAIN_C
154791. DTS_USE_TOP
154792. DTS_WARN
154793. DTS_WARN_HYST
154794. DTSaddress
154795. DTU
154796. DTU0
154797. DTU1
154798. DTU2
154799. DTU3
154800. DTUS
154801. DTUSX
154802. DTV5100_DEMOD_ADDR
154803. DTV5100_DEMOD_READ
154804. DTV5100_DEMOD_WRITE
154805. DTV5100_TUNER_ADDR
154806. DTV5100_TUNER_READ
154807. DTV5100_TUNER_WRITE
154808. DTV5100_USB_TIMEOUT
154809. DTV6
154810. DTV7
154811. DTV78
154812. DTV7_8
154813. DTV8
154814. DTV_API_VERSION
154815. DTV_ATSCMH_FIC_VER
154816. DTV_ATSCMH_NOG
154817. DTV_ATSCMH_PARADE_ID
154818. DTV_ATSCMH_PRC
154819. DTV_ATSCMH_RS_CODE_MODE_PRI
154820. DTV_ATSCMH_RS_CODE_MODE_SEC
154821. DTV_ATSCMH_RS_FRAME_ENSEMBLE
154822. DTV_ATSCMH_RS_FRAME_MODE
154823. DTV_ATSCMH_SCCC_BLOCK_MODE
154824. DTV_ATSCMH_SCCC_CODE_MODE_A
154825. DTV_ATSCMH_SCCC_CODE_MODE_B
154826. DTV_ATSCMH_SCCC_CODE_MODE_C
154827. DTV_ATSCMH_SCCC_CODE_MODE_D
154828. DTV_ATSCMH_SGN
154829. DTV_ATSCMH_TNOG
154830. DTV_BANDWIDTH_HZ
154831. DTV_BCLK_A_MARK
154832. DTV_BCLK_B_MARK
154833. DTV_CLEAR
154834. DTV_CODE_RATE_HP
154835. DTV_CODE_RATE_LP
154836. DTV_DATA_A_MARK
154837. DTV_DATA_B_MARK
154838. DTV_DELIVERY_SYSTEM
154839. DTV_DISEQC_MASTER
154840. DTV_DISEQC_SLAVE_REPLY
154841. DTV_DVBT2_PLP_ID_LEGACY
154842. DTV_ENUM_DELSYS
154843. DTV_FE_CAPABILITY
154844. DTV_FE_CAPABILITY_COUNT
154845. DTV_FREQUENCY
154846. DTV_GUARD_INTERVAL
154847. DTV_HIERARCHY
154848. DTV_INNER_FEC
154849. DTV_INTERLEAVING
154850. DTV_INVERSION
154851. DTV_IOCTL_MAX_MSGS
154852. DTV_ISDBS_TS_ID_LEGACY
154853. DTV_ISDBT_LAYERA_FEC
154854. DTV_ISDBT_LAYERA_MODULATION
154855. DTV_ISDBT_LAYERA_SEGMENT_COUNT
154856. DTV_ISDBT_LAYERA_TIME_INTERLEAVING
154857. DTV_ISDBT_LAYERB_FEC
154858. DTV_ISDBT_LAYERB_MODULATION
154859. DTV_ISDBT_LAYERB_SEGMENT_COUNT
154860. DTV_ISDBT_LAYERB_TIME_INTERLEAVING
154861. DTV_ISDBT_LAYERC_FEC
154862. DTV_ISDBT_LAYERC_MODULATION
154863. DTV_ISDBT_LAYERC_SEGMENT_COUNT
154864. DTV_ISDBT_LAYERC_TIME_INTERLEAVING
154865. DTV_ISDBT_LAYER_ENABLED
154866. DTV_ISDBT_PARTIAL_RECEPTION
154867. DTV_ISDBT_SB_SEGMENT_COUNT
154868. DTV_ISDBT_SB_SEGMENT_IDX
154869. DTV_ISDBT_SB_SUBCHANNEL_ID
154870. DTV_ISDBT_SOUND_BROADCASTING
154871. DTV_LNA
154872. DTV_MAX_COMMAND
154873. DTV_MODULATION
154874. DTV_PILOT
154875. DTV_PORTA_CONTROL_REG_BASE
154876. DTV_PORTB_CONTROL_REG_BASE
154877. DTV_PSYNC_A_MARK
154878. DTV_PSYNC_B_MARK
154879. DTV_ROLLOFF
154880. DTV_SCRAMBLING_SEQUENCE_INDEX
154881. DTV_STAT_CNR
154882. DTV_STAT_ERROR_BLOCK_COUNT
154883. DTV_STAT_POST_ERROR_BIT_COUNT
154884. DTV_STAT_POST_TOTAL_BIT_COUNT
154885. DTV_STAT_PRE_ERROR_BIT_COUNT
154886. DTV_STAT_PRE_TOTAL_BIT_COUNT
154887. DTV_STAT_SIGNAL_STRENGTH
154888. DTV_STAT_TOTAL_BLOCK_COUNT
154889. DTV_STREAM_ID
154890. DTV_SYMBOL_RATE
154891. DTV_TONE
154892. DTV_TRANSMISSION_MODE
154893. DTV_TUNE
154894. DTV_TYPES
154895. DTV_UNDEFINED
154896. DTV_VALID_A_MARK
154897. DTV_VALID_B_MARK
154898. DTV_VOLTAGE
154899. DTX
154900. DTXFSTS
154901. DTXMR0
154902. DTX_REG
154903. DTYPE1
154904. DTYPE2
154905. DTYPE3
154906. DTYPE4
154907. DTYPE5
154908. DTYPE6
154909. DTYP_MASK
154910. DTYP_SHIFT
154911. DT_100THS
154912. DT_ADDRRNGHI
154913. DT_ADDRRNGLO
154914. DT_ALARM_EN
154915. DT_BINDINGS_ASPEED_CLOCK_H
154916. DT_BINDINGS_AST2600_CLOCK_H
154917. DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
154918. DT_BINDINGS_CLK_LOCHNAGAR_H
154919. DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
154920. DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
154921. DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
154922. DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
154923. DT_BINDINGS_DDR_H
154924. DT_BINDINGS_MEMORY_TEGRA114_MC_H
154925. DT_BINDINGS_MEMORY_TEGRA124_MC_H
154926. DT_BINDINGS_MEMORY_TEGRA186_MC_H
154927. DT_BINDINGS_MEMORY_TEGRA20_MC_H
154928. DT_BINDINGS_MEMORY_TEGRA210_MC_H
154929. DT_BINDINGS_MEMORY_TEGRA30_MC_H
154930. DT_BINDINGS_NBPFAXI_H
154931. DT_BINDINGS_PINCTRL_LOCHNAGAR_H
154932. DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
154933. DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
154934. DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
154935. DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
154936. DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
154937. DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
154938. DT_BINDINGS_SOUND_MADERA_H
154939. DT_BINDING_RESET_IMX7_H
154940. DT_BINDING_RESET_IMX8MQ_H
154941. DT_BLK
154942. DT_C6000_DSBT_BASE
154943. DT_C6000_DSBT_INDEX
154944. DT_C6000_DSBT_SIZE
154945. DT_C6000_PREEMPTMAP
154946. DT_CHR
154947. DT_CLK
154948. DT_CLOCK_OXSEMI_OX810SE_H
154949. DT_CLOCK_OXSEMI_OX820_H
154950. DT_COLS
154951. DT_COMPILER
154952. DT_CPUADDR_TO_ATTR
154953. DT_CPUADDR_TO_TARGET
154954. DT_CS
154955. DT_C_CLEAR_ERR
154956. DT_C_READ_AD
154957. DT_C_READ_ADIM
154958. DT_C_READ_DIG
154959. DT_C_READ_ERRREG
154960. DT_C_RESET
154961. DT_C_SET_AD
154962. DT_C_SET_CLOCK
154963. DT_C_SET_DA
154964. DT_C_SET_DIGIN
154965. DT_C_SET_DIGOUT
154966. DT_C_STOP
154967. DT_C_TEST
154968. DT_C_WRITE_DA
154969. DT_C_WRITE_DAIM
154970. DT_C_WRITE_DIG
154971. DT_DATA_ATTR_SUFFIX
154972. DT_DAYS
154973. DT_DAY_ALM1
154974. DT_DEBUG
154975. DT_DIGITAL_IN
154976. DT_DIR
154977. DT_EEMPTY
154978. DT_ENCODING
154979. DT_EOS
154980. DT_EXTENDED_IDS
154981. DT_FAULT_ATTR_SUFFIX
154982. DT_FEMPTY
154983. DT_FEMPTY_IC
154984. DT_FEMPTY_IS
154985. DT_FEMPTY_ND
154986. DT_FEND
154987. DT_FIFO
154988. DT_FINI
154989. DT_FLAGS_1
154990. DT_FLAGS_TO_TYPE
154991. DT_FMID
154992. DT_FSINGLE
154993. DT_FSTART
154994. DT_FWI2
154995. DT_GETPAGE
154996. DT_GETSEARCH
154997. DT_GETSTBL
154998. DT_HASH
154999. DT_HIOS
155000. DT_HIPROC
155001. DT_HOURS
155002. DT_HOUR_ALM1
155003. DT_HOUR_ALM2
155004. DT_ID
155005. DT_IIDMA
155006. DT_IN
155007. DT_INIT
155008. DT_ISP2031
155009. DT_ISP2061
155010. DT_ISP2071
155011. DT_ISP2081
155012. DT_ISP2089
155013. DT_ISP2100
155014. DT_ISP2200
155015. DT_ISP2200A
155016. DT_ISP2261
155017. DT_ISP2271
155018. DT_ISP2281
155019. DT_ISP2289
155020. DT_ISP2300
155021. DT_ISP2312
155022. DT_ISP2322
155023. DT_ISP2422
155024. DT_ISP2432
155025. DT_ISP2532
155026. DT_ISP5422
155027. DT_ISP5432
155028. DT_ISP6312
155029. DT_ISP6322
155030. DT_ISP8001
155031. DT_ISP8021
155032. DT_ISP8031
155033. DT_ISP8044
155034. DT_ISP8432
155035. DT_ISPFX00
155036. DT_ISP_LAST
155037. DT_JMPREL
155038. DT_LEMPTY
155039. DT_LINK
155040. DT_LINKFIX
155041. DT_LNK
155042. DT_LOAD_MEM
155043. DT_LOOS
155044. DT_LOPROC
155045. DT_MACHINE_START
155046. DT_MASK
155047. DT_MAX
155048. DT_MEM_ALLOC
155049. DT_MINUTES
155050. DT_MINUTE_ALM1
155051. DT_MINUTE_ALM2
155052. DT_MIPS_BASE_ADDRESS
155053. DT_MIPS_CONFLICT
155054. DT_MIPS_CONFLICTNO
155055. DT_MIPS_FLAGS
155056. DT_MIPS_GOTSYM
155057. DT_MIPS_HIPAGENO
155058. DT_MIPS_ICHECKSUM
155059. DT_MIPS_IVERSION
155060. DT_MIPS_LIBLIST
155061. DT_MIPS_LIBLISTNO
155062. DT_MIPS_LOCAL_GOTNO
155063. DT_MIPS_RLD_MAP
155064. DT_MIPS_RLD_VERSION
155065. DT_MIPS_SYMTABNO
155066. DT_MIPS_TIME_STAMP
155067. DT_MIPS_UNREFEXTNO
155068. DT_MOD_CONT
155069. DT_MOD_DMA
155070. DT_MOD_EXTCLK
155071. DT_MOD_EXTTRIG
155072. DT_MONTHS
155073. DT_MONTH_ALM1
155074. DT_NEEDED
155075. DT_NULL
155076. DT_OEM_001
155077. DT_OUT
155078. DT_PAGE
155079. DT_PLTGOT
155080. DT_PLTREL
155081. DT_PLTRELSZ
155082. DT_PUTPAGE
155083. DT_READ_MEM
155084. DT_REG
155085. DT_REL
155086. DT_RELA
155087. DT_RELACOUNT
155088. DT_RELAENT
155089. DT_RELASZ
155090. DT_RELCOUNT
155091. DT_RELENT
155092. DT_RELSZ
155093. DT_RESET_OXSEMI_OX810SE_H
155094. DT_RESET_OXSEMI_OX820_H
155095. DT_RPATH
155096. DT_SECOND_ALM1
155097. DT_SECS
155098. DT_SET_DIC
155099. DT_SHIFT
155100. DT_SOCK
155101. DT_SONAME
155102. DT_START_TASK
155103. DT_STRSZ
155104. DT_STRTAB
155105. DT_SXFR
155106. DT_SYMBOLIC
155107. DT_SYMENT
155108. DT_SYMTAB
155109. DT_S_COMMAND
155110. DT_S_COMPOSITE_ERROR
155111. DT_S_DATA_IN_FULL
155112. DT_S_DATA_OUT_READY
155113. DT_S_READY
155114. DT_T10_PI
155115. DT_TEXTREL
155116. DT_THRESHOLD_ATTR_SUFFIX
155117. DT_TIMESTAMP1
155118. DT_TIMESTAMP2
155119. DT_TIMESTAMP3
155120. DT_TS_MODE
155121. DT_TYPE_IO
155122. DT_TYPE_MEM32
155123. DT_UNKNOWN
155124. DT_VALRNGHI
155125. DT_VALRNGLO
155126. DT_VERDEF
155127. DT_VERDEFNUM
155128. DT_VERNEED
155129. DT_VERNEEDNUM
155130. DT_VERSYM
155131. DT_WEEKDAYS
155132. DT_WEEKDAY_ALM2
155133. DT_WHT
155134. DT_YEARS
155135. DT_ZIO_SUPPORTED
155136. DTableDesc
155137. DText
155138. DU
155139. DU0_CDE
155140. DU0_CDE_MARK
155141. DU0_DB0
155142. DU0_DB0_MARK
155143. DU0_DB1
155144. DU0_DB1_MARK
155145. DU0_DB2
155146. DU0_DB2_C0_MARK
155147. DU0_DB2_MARK
155148. DU0_DB3
155149. DU0_DB3_C1_MARK
155150. DU0_DB3_MARK
155151. DU0_DB4
155152. DU0_DB4_C2_MARK
155153. DU0_DB4_MARK
155154. DU0_DB5
155155. DU0_DB5_C3_MARK
155156. DU0_DB5_MARK
155157. DU0_DB6
155158. DU0_DB6_C4_MARK
155159. DU0_DB6_MARK
155160. DU0_DB7
155161. DU0_DB7_C5_MARK
155162. DU0_DB7_MARK
155163. DU0_DG0
155164. DU0_DG0_DATA8_MARK
155165. DU0_DG0_MARK
155166. DU0_DG1
155167. DU0_DG1_DATA9_MARK
155168. DU0_DG1_MARK
155169. DU0_DG2
155170. DU0_DG2_C6_DATA10_MARK
155171. DU0_DG2_MARK
155172. DU0_DG3
155173. DU0_DG3_C7_DATA11_MARK
155174. DU0_DG3_MARK
155175. DU0_DG4
155176. DU0_DG4_MARK
155177. DU0_DG4_Y0_DATA12_MARK
155178. DU0_DG5
155179. DU0_DG5_MARK
155180. DU0_DG5_Y1_DATA13_MARK
155181. DU0_DG6
155182. DU0_DG6_MARK
155183. DU0_DG6_Y2_DATA14_MARK
155184. DU0_DG7
155185. DU0_DG7_MARK
155186. DU0_DG7_Y3_DATA15_MARK
155187. DU0_DISP_CSYNC_N_DE
155188. DU0_DISP_MARK
155189. DU0_DOTCLKIN
155190. DU0_DOTCLKIN_MARK
155191. DU0_DOTCLKOUT
155192. DU0_DOTCLKOUT0_MARK
155193. DU0_DOTCLKOUT1_MARK
155194. DU0_DOTCLKOUTB
155195. DU0_DOTCLKOUT_MARK
155196. DU0_DOTCLKO_UT0_MARK
155197. DU0_DOTCLKO_UT1_MARK
155198. DU0_DR0
155199. DU0_DR0_DATA0_MARK
155200. DU0_DR0_MARK
155201. DU0_DR19
155202. DU0_DR1_DATA1_MARK
155203. DU0_DR1_MARK
155204. DU0_DR2
155205. DU0_DR2_MARK
155206. DU0_DR2_Y4_DATA2_MARK
155207. DU0_DR3
155208. DU0_DR3_MARK
155209. DU0_DR3_Y5_DATA3_MARK
155210. DU0_DR4
155211. DU0_DR4_MARK
155212. DU0_DR4_Y6_DATA4_MARK
155213. DU0_DR5
155214. DU0_DR5_MARK
155215. DU0_DR5_Y7_DATA5_MARK
155216. DU0_DR6
155217. DU0_DR6_MARK
155218. DU0_DR6_Y8_DATA6_MARK
155219. DU0_DR7
155220. DU0_DR7_MARK
155221. DU0_DR7_Y9_DATA7_MARK
155222. DU0_EXHSYNC_DU0_HSYNC_MARK
155223. DU0_EXHSYNC_N_CSYNC_N_HSYNC_N
155224. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
155225. DU0_EXODDF_DU0_ODDF_MARK
155226. DU0_EXVSYNC_DU0_VSYNC_MARK
155227. DU0_EXVSYNC_N_VSYNC_N_CSYNC_N
155228. DU0_ODDF_N_CLAMP
155229. DU0_REG_OFFSET
155230. DU1_CDE_MARK
155231. DU1_DB0_MARK
155232. DU1_DB1_MARK
155233. DU1_DB2_C0_DATA12_MARK
155234. DU1_DB2_MARK
155235. DU1_DB3_C1_DATA13_MARK
155236. DU1_DB3_MARK
155237. DU1_DB4_C2_DATA14_MARK
155238. DU1_DB4_MARK
155239. DU1_DB5_C3_DATA15_MARK
155240. DU1_DB5_MARK
155241. DU1_DB6_C4_MARK
155242. DU1_DB6_MARK
155243. DU1_DB7_C5_MARK
155244. DU1_DB7_MARK
155245. DU1_DG0_MARK
155246. DU1_DG1_MARK
155247. DU1_DG2_C6_DATA6_MARK
155248. DU1_DG2_MARK
155249. DU1_DG3_C7_DATA7_MARK
155250. DU1_DG3_MARK
155251. DU1_DG4_MARK
155252. DU1_DG4_Y0_DATA8_MARK
155253. DU1_DG5_MARK
155254. DU1_DG5_Y1_DATA9_MARK
155255. DU1_DG6_MARK
155256. DU1_DG6_Y2_DATA10_MARK
155257. DU1_DG7_MARK
155258. DU1_DG7_Y3_DATA11_MARK
155259. DU1_DISP_MARK
155260. DU1_DOTCLKIN_B_MARK
155261. DU1_DOTCLKIN_C_MARK
155262. DU1_DOTCLKIN_MARK
155263. DU1_DOTCLKOUT0_MARK
155264. DU1_DOTCLKOUT1_MARK
155265. DU1_DOTCLKOUT_MARK
155266. DU1_DR0_MARK
155267. DU1_DR1_MARK
155268. DU1_DR2_MARK
155269. DU1_DR2_Y4_DATA0_MARK
155270. DU1_DR3_MARK
155271. DU1_DR3_Y5_DATA1_MARK
155272. DU1_DR4_MARK
155273. DU1_DR4_Y6_DATA2_MARK
155274. DU1_DR5_MARK
155275. DU1_DR5_Y7_DATA3_MARK
155276. DU1_DR6_DATA4_MARK
155277. DU1_DR6_MARK
155278. DU1_DR7_DATA5_MARK
155279. DU1_DR7_MARK
155280. DU1_EXHSYNC_DU1_HSYNC_MARK
155281. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
155282. DU1_EXVSYNC_DU1_VSYNC_MARK
155283. DU1_REG_OFFSET
155284. DU2_CDE_MARK
155285. DU2_DB0_MARK
155286. DU2_DB1_MARK
155287. DU2_DB2_MARK
155288. DU2_DB3_MARK
155289. DU2_DB4_MARK
155290. DU2_DB5_MARK
155291. DU2_DB6_MARK
155292. DU2_DB7_MARK
155293. DU2_DG0_MARK
155294. DU2_DG1_MARK
155295. DU2_DG2_MARK
155296. DU2_DG3_MARK
155297. DU2_DG4_MARK
155298. DU2_DG5_MARK
155299. DU2_DG6_MARK
155300. DU2_DG7_MARK
155301. DU2_DISP_MARK
155302. DU2_DR0_MARK
155303. DU2_DR1_MARK
155304. DU2_DR2_MARK
155305. DU2_DR3_MARK
155306. DU2_DR4_MARK
155307. DU2_DR5_MARK
155308. DU2_DR6_MARK
155309. DU2_DR7_MARK
155310. DU2_EXHSYNC_DU2_HSYNC_MARK
155311. DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
155312. DU2_EXVSYNC_DU2_VSYNC_MARK
155313. DU2_REG_OFFSET
155314. DU3_REG_OFFSET
155315. DUALMAC_DUALPHY
155316. DUALMAC_SINGLEPHY
155317. DUALSHOCK4_CONTROLLER
155318. DUALSHOCK4_CONTROLLER_BT
155319. DUALSHOCK4_CONTROLLER_USB
155320. DUALSHOCK4_DONGLE
155321. DUALTOUCH_REG_OFF
155322. DUALTOUCH_REG_ON
155323. DUALTOUCH_STABILIZE_OFF
155324. DUALTOUCH_STABILIZE_ON
155325. DUAL_CHANNEL
155326. DUAL_CLK_MODE_MASK
155327. DUAL_CLK_MODE_SHIFT
155328. DUAL_EDGE_ENABLE
155329. DUAL_LINK_FRONT_BACK
155330. DUAL_LINK_MODE_FRONTBACK
155331. DUAL_LINK_MODE_FRONT_BACK
155332. DUAL_LINK_MODE_INTERLEAVE
155333. DUAL_LINK_MODE_MASK
155334. DUAL_LINK_MODE_PIXEL_ALTERNATIVE
155335. DUAL_LINK_MODE_SHIFT
155336. DUAL_LINK_NOT_SUPPORTED
155337. DUAL_LINK_PIXEL_ALT
155338. DUAL_MAC_CTRL_CH_MASK
155339. DUAL_MAC_CTRL_ID
155340. DUAL_MEDIA
155341. DUAL_MLVDS_CTL
155342. DUAL_MLVDS_LINE_END
155343. DUAL_MLVDS_LINE_START
155344. DUAL_MLVDS_PIXEL_R_CNT_L
155345. DUAL_MLVDS_PIXEL_R_CNT_R
155346. DUAL_MLVDS_PIXEL_R_START_L
155347. DUAL_MLVDS_PIXEL_R_START_R
155348. DUAL_MLVDS_PIXEL_W_END_L
155349. DUAL_MLVDS_PIXEL_W_END_R
155350. DUAL_MLVDS_PIXEL_W_START_L
155351. DUAL_MLVDS_PIXEL_W_START_R
155352. DUAL_PORT_CAP
155353. DUAL_PORT_CNTL_ADDR
155354. DUAL_RATE_MODE
155355. DUAL_ROLE_CFG0
155356. DUAL_ROLE_CFG1
155357. DUAL_ROLE_CFG1_POLL_TIMEOUT
155358. DUAL_TFT_MASK
155359. DUAL_TFT_OFF
155360. DUAL_TFT_OFFSET
155361. DUAL_TFT_ON
155362. DUAL_TFT_USAGE
155363. DUAL_TOUCH
155364. DUAL_TSF_RESET_P2P
155365. DUAL_TSF_RESET_TSF0
155366. DUAL_TSF_RESET_TSF1
155367. DUAL_TSF_RST_P2P
155368. DUAL_TSF_TX_OK
155369. DUAL_VOLT_OCR_BIT
155370. DUART16552_1_ADDR
155371. DUART16552_1_INTNUM
155372. DUART16552_2_ADDR
155373. DUART16552_2_INTNUM
155374. DUART16552_INTNUM
155375. DUART16552_PADDR
155376. DUART16552_XTAL_FREQ
155377. DUARTBASE
155378. DUART_CHANREG_SPACING
155379. DUART_IMRISR_SPACING
155380. DUART_INCHNG_SPACING
155381. DUART_MAX_CHIP
155382. DUART_MAX_SIDE
155383. DUCTRL
155384. DUI
155385. DUIS
155386. DUMB12_RGB444_0
155387. DUMB12_RGB444_1
155388. DUMB16_RGB565_0
155389. DUMB16_RGB565_1
155390. DUMB18_RGB666_0
155391. DUMB18_RGB666_1
155392. DUMB24_RGB888_0
155393. DUMB_BLANK
155394. DUMB_FRAMEDONE
155395. DUMB_FRAMEDONE_ENA
155396. DUMB_FRAMEDONE_ENA_MASK
155397. DUMB_FRAMEDONE_LEVEL
155398. DUMB_FRAMEDONE_LEVEL_MASK
155399. DUMB_FRAMEDONE_MASK
155400. DUMB_MASK
155401. DUMB_MODE_RGB444
155402. DUMB_MODE_RGB444_UPPER
155403. DUMB_MODE_RGB565
155404. DUMB_MODE_RGB565_UPPER
155405. DUMB_MODE_RGB666
155406. DUMB_MODE_RGB666_UPPER
155407. DUMB_MODE_RGB888
155408. DUMMY
155409. DUMMY2_BD_BUFFER
155410. DUMMYSPRITEMEMSIZE
155411. DUMMY_304
155412. DUMMY_ALLOCO_AREA_SIZE
155413. DUMMY_BD_BUFFER
155414. DUMMY_BIT
155415. DUMMY_BYTES
155416. DUMMY_CAPSRC
155417. DUMMY_CLK
155418. DUMMY_COLUMNS
155419. DUMMY_CSDEASSERT
155420. DUMMY_CYCLES
155421. DUMMY_DELAY_ACCESS
155422. DUMMY_DEVICE_DOMAIN_INFO
155423. DUMMY_ENCRYPTION_ENABLED
155424. DUMMY_ENDPOINTS
155425. DUMMY_ETH_HDR_LEN
155426. DUMMY_FID
155427. DUMMY_INDEX_ACCELX
155428. DUMMY_INDEX_DIFFVOLTAGE_1M2
155429. DUMMY_INDEX_DIFFVOLTAGE_3M4
155430. DUMMY_INDEX_VOLTAGE_0
155431. DUMMY_MAGIC
155432. DUMMY_MARK
155433. DUMMY_PACKET_EVENT_ID
155434. DUMMY_PADS_1
155435. DUMMY_PADS_2
155436. DUMMY_PADS_4
155437. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
155438. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT
155439. DUMMY_PARENT
155440. DUMMY_PKT_LEN
155441. DUMMY_PORT_ID
155442. DUMMY_PTR
155443. DUMMY_RATE
155444. DUMMY_READ
155445. DUMMY_REG_RESET_0
155446. DUMMY_RH_RESET
155447. DUMMY_RH_RUNNING
155448. DUMMY_RH_SUSPENDED
155449. DUMMY_ROWS
155450. DUMMY_RX_NON_BUFFERABLE
155451. DUMMY_STM_MAX
155452. DUMMY_VOLUME
155453. DUMMY_WRITTEN_PAGE
155454. DUMP
155455. DUMP1
155456. DUMPBITS
155457. DUMPCMD_RSP_BUFFER
155458. DUMPCORE
155459. DUMPCOREAV
155460. DUMPCOREAV2
155461. DUMPPHY
155462. DUMPPLL
155463. DUMPREG
155464. DUMP_ADDR
155465. DUMP_ALL
155466. DUMP_ALL_PRESETS
155467. DUMP_BLOCK_RSV
155468. DUMP_BLOCK_SIZE
155469. DUMP_BLOCK_SIZE_MAX
155470. DUMP_BYTES
155471. DUMP_CCW_STR
155472. DUMP_CHAIN_EXCHG
155473. DUMP_CHAIN_EXLOGIN
155474. DUMP_CHAIN_FCE
155475. DUMP_CHAIN_LAST
155476. DUMP_CHAIN_MQ
155477. DUMP_CHAIN_QUEUE
155478. DUMP_CHAIN_VARIANT
155479. DUMP_CHIP_E1
155480. DUMP_CHIP_E1H
155481. DUMP_CHIP_E2
155482. DUMP_CHIP_E3A0
155483. DUMP_CHIP_E3B0
155484. DUMP_COP0_REG
155485. DUMP_DEVICE_ERROR
155486. DUMP_ELS
155487. DUMP_EXCEP
155488. DUMP_FCP_STR
155489. DUMP_FIELD
155490. DUMP_FLAGS
155491. DUMP_FRAME_BEACON
155492. DUMP_FRAME_RXDONE
155493. DUMP_FRAME_TX
155494. DUMP_FRAME_TXDONE
155495. DUMP_HEADER_VERSION
155496. DUMP_INIT
155497. DUMP_IO
155498. DUMP_IT_BACK
155499. DUMP_JITED
155500. DUMP_L2_ECC_TAG_ON_ERROR
155501. DUMP_LAST
155502. DUMP_LINE_MAX
155503. DUMP_MAX_BYTES
155504. DUMP_MAX_PRESETS
155505. DUMP_MBX
155506. DUMP_MSGS
155507. DUMP_NAME_LEN
155508. DUMP_NONE
155509. DUMP_NONE_STR
155510. DUMP_NVMELS
155511. DUMP_OBTAINED
155512. DUMP_ONE
155513. DUMP_ORIG
155514. DUMP_PACKETS
155515. DUMP_PATH_0
155516. DUMP_PATH_1
155517. DUMP_PREFIX_ADDRESS
155518. DUMP_PREFIX_NONE
155519. DUMP_PREFIX_OFFSET
155520. DUMP_QDEV_ARRAY
155521. DUMP_QDEV_DMA_FIELD
155522. DUMP_QDEV_FIELD
155523. DUMP_REG
155524. DUMP_REGS
155525. DUMP_STAT
155526. DUMP_TM_MAP
155527. DUMP_TX_FIFO_FLUSH
155528. DUMP_TYPE
155529. DUMP_TYPE_CCW
155530. DUMP_TYPE_FCP
155531. DUMP_TYPE_FSP
155532. DUMP_TYPE_NONE
155533. DUMP_VALUE
155534. DUMP_VAR
155535. DUMP_WIDTH
155536. DUMP_XGMAC
155537. DUMP_XLATED
155538. DUMP_printk
155539. DUN
155540. DUODOCK_SONIC_PROM_BASE
155541. DUODOCK_SONIC_REGISTERS
155542. DUP
155543. DUPLEX_FULL
155544. DUPLEX_HALF
155545. DUPLEX_INVALID
155546. DUPLEX_MODE
155547. DUPLEX_STATUS
155548. DUPLEX_UNFORCED
155549. DUPLEX_UNKNOWN
155550. DUPLICATE_BOARD
155551. DUPLICATE_ENTRY
155552. DUPLICATE_RX_CACHE_LENGTH
155553. DUPLX_MODE
155554. DUPMODE_BITS
155555. DUPS1_GATING_DIS
155556. DUPS2_GATING_DIS
155557. DUPS3_GATING_DIS
155558. DUPS_MASK
155559. DUR
155560. DUR_WAIT_RESET
155561. DUTY
155562. DUTYCTRL_ADRS
155563. DUTY_CTRL_PWM1_FALL_POINT
155564. DUTY_CTRL_PWM1_RISE_FALL_MASK
155565. DUTY_CTRL_PWM1_RISE_POINT
155566. DUTY_CTRL_PWM2_FALL_POINT
155567. DUTY_CTRL_PWM2_RISE_FALL_MASK
155568. DUTY_CTRL_PWM2_RISE_POINT
155569. DUTY_CYCLE_HIGH_MAX
155570. DUTY_CYCLE_HIGH_MIN
155571. DUTY_CYCLE_HIGH_OFFSET
155572. DU_DOTCLKIN0_MARK
155573. DU_DOTCLKIN1_MARK
155574. DU_DOTCLKIN2_MARK
155575. DV1_PANEL_HEIGHT
155576. DV1_PANEL_WIDTH
155577. DV331812_17
155578. DV331812_33
155579. DV331812_MASK
155580. DV331812_POWEROFF
155581. DV331812_POWERON
155582. DV331812_VDD1
155583. DV3318_AUTO_PWR_OFF
155584. DV3318_DETECT_EN
155585. DV3318_OCP_CLR
155586. DV3318_OCP_DETECT
155587. DV3318_OCP_EVER
155588. DV3318_OCP_GlITCH_TIME_MASK
155589. DV3318_OCP_INT_CLR
155590. DV3318_OCP_INT_EN
155591. DV3318_OCP_NOW
155592. DV3318_OCP_TIME_MASK
155593. DVA
155594. DVB3_EVENT_FE_LOCK
155595. DVB3_EVENT_FE_UNLOCK
155596. DVB3_EVENT_HOTPLUG
155597. DVB3_EVENT_INIT
155598. DVB3_EVENT_SLEEP
155599. DVB3_EVENT_UNC_ERR
155600. DVB3_EVENT_UNC_OK
155601. DVBC_6
155602. DVBC_8
155603. DVBFE_ALGO_CUSTOM
155604. DVBFE_ALGO_HW
155605. DVBFE_ALGO_RECOVERY
155606. DVBFE_ALGO_SEARCH_AGAIN
155607. DVBFE_ALGO_SEARCH_ASLEEP
155608. DVBFE_ALGO_SEARCH_ERROR
155609. DVBFE_ALGO_SEARCH_FAILED
155610. DVBFE_ALGO_SEARCH_INVALID
155611. DVBFE_ALGO_SEARCH_SUCCESS
155612. DVBFE_ALGO_SW
155613. DVBS1_ENABLE
155614. DVBS2_16APSK_2_3
155615. DVBS2_16APSK_3_4
155616. DVBS2_16APSK_4_5
155617. DVBS2_16APSK_5_6
155618. DVBS2_16APSK_8_9
155619. DVBS2_16APSK_9_10
155620. DVBS2_16K
155621. DVBS2_32APSK_3_4
155622. DVBS2_32APSK_4_5
155623. DVBS2_32APSK_5_6
155624. DVBS2_32APSK_8_9
155625. DVBS2_32APSK_9_10
155626. DVBS2_64K
155627. DVBS2_8PSK_2_3
155628. DVBS2_8PSK_3_4
155629. DVBS2_8PSK_3_5
155630. DVBS2_8PSK_5_6
155631. DVBS2_8PSK_8_9
155632. DVBS2_8PSK_9_10
155633. DVBS2_DEMOD_LOCK
155634. DVBS2_DEMOD_NOLOCK
155635. DVBS2_DUMMY_PLF
155636. DVBS2_ENABLE
155637. DVBS2_FEC_LOCK
155638. DVBS2_FEC_NOLOCK
155639. DVBS2_QPSK_1_2
155640. DVBS2_QPSK_1_3
155641. DVBS2_QPSK_1_4
155642. DVBS2_QPSK_2_3
155643. DVBS2_QPSK_2_5
155644. DVBS2_QPSK_3_4
155645. DVBS2_QPSK_3_5
155646. DVBS2_QPSK_4_5
155647. DVBS2_QPSK_5_6
155648. DVBS2_QPSK_8_9
155649. DVBS2_QPSK_9_10
155650. DVBSKY_BUF_LEN
155651. DVBSKY_FE_M88DS3103
155652. DVBSKY_FE_M88RS6000
155653. DVBSKY_FE_NULL
155654. DVBSKY_FE_SIT2
155655. DVBSKY_MSG_DELAY
155656. DVBT2_6
155657. DVBT2_7
155658. DVBT2_8
155659. DVBT2_PROFILE_ANY
155660. DVBT2_PROFILE_BASE
155661. DVBT2_PROFILE_LITE
155662. DVBT_6
155663. DVBT_7
155664. DVBT_8
155665. DVBT_AAGC_HOLD
155666. DVBT_AAGC_LOOP_GAIN
155667. DVBT_ACI_DET_IND
155668. DVBT_AD7_SETTING
155669. DVBT_AD_AVI
155670. DVBT_AD_AVQ
155671. DVBT_AD_AV_REF
155672. DVBT_AD_EN_REG
155673. DVBT_AD_EN_REG1
155674. DVBT_AGC_TARG_VAL
155675. DVBT_AGC_TARG_VAL_0
155676. DVBT_AGC_TARG_VAL_8_1
155677. DVBT_ALPHAIIR_DIF
155678. DVBT_ALPHAIIR_N
155679. DVBT_BDA_CONTROL_MSG_ID
155680. DVBT_BER_PASS_SCAL
155681. DVBT_BTHD_D3
155682. DVBT_BTHD_P3
155683. DVBT_BW_INDEX
155684. DVBT_CCI_M0
155685. DVBT_CCI_M1
155686. DVBT_CCI_M2
155687. DVBT_CCI_M3
155688. DVBT_CCI_MON_SCAL
155689. DVBT_CCI_THRE
155690. DVBT_CDIV_PH0
155691. DVBT_CDIV_PH1
155692. DVBT_CE_EST_EVM
155693. DVBT_CE_FFSM_BYPASS
155694. DVBT_CFREQ_OFF
155695. DVBT_CFREQ_OFF_RATIO
155696. DVBT_CKOUTPAR
155697. DVBT_CKOUTPAR_PID
155698. DVBT_CKOUTPAR_PIP
155699. DVBT_CKOUT_PWR
155700. DVBT_CKOUT_PWR_PID
155701. DVBT_CKOUT_PWR_PIP
155702. DVBT_CR_THD_SET2
155703. DVBT_DAGC_TRG_VAL
155704. DVBT_DAGC_VAL
155705. DVBT_EN_AGC_PGA
155706. DVBT_EN_BBIN
155707. DVBT_EN_BK_TRK
155708. DVBT_EN_CACQ_NOTCH
155709. DVBT_EN_GI_PGA
155710. DVBT_EN_IF_AGC
155711. DVBT_EN_RF_AGC
155712. DVBT_EN_TRK_SPAN
155713. DVBT_ERR_DUR
155714. DVBT_ERR_LVL
155715. DVBT_ERR_LVL_PID
155716. DVBT_ERR_LVL_PIP
155717. DVBT_FFT_MODE_IDX
155718. DVBT_FSM_STAGE
155719. DVBT_FUNC4_REG0
155720. DVBT_FUNC4_REG1
155721. DVBT_FUNC4_REG10
155722. DVBT_FUNC4_REG2
155723. DVBT_FUNC4_REG3
155724. DVBT_FUNC4_REG4
155725. DVBT_FUNC4_REG5
155726. DVBT_FUNC4_REG6
155727. DVBT_FUNC4_REG7
155728. DVBT_FUNC4_REG8
155729. DVBT_FUNC4_REG9
155730. DVBT_FUNC5_REG0
155731. DVBT_FUNC5_REG1
155732. DVBT_FUNC5_REG10
155733. DVBT_FUNC5_REG11
155734. DVBT_FUNC5_REG12
155735. DVBT_FUNC5_REG13
155736. DVBT_FUNC5_REG14
155737. DVBT_FUNC5_REG15
155738. DVBT_FUNC5_REG16
155739. DVBT_FUNC5_REG17
155740. DVBT_FUNC5_REG18
155741. DVBT_FUNC5_REG2
155742. DVBT_FUNC5_REG3
155743. DVBT_FUNC5_REG4
155744. DVBT_FUNC5_REG5
155745. DVBT_FUNC5_REG6
155746. DVBT_FUNC5_REG7
155747. DVBT_FUNC5_REG8
155748. DVBT_FUNC5_REG9
155749. DVBT_GI_IDX
155750. DVBT_GI_PGA_STATE
155751. DVBT_IF_AGC_MAN
155752. DVBT_IF_AGC_MAN_VAL
155753. DVBT_IF_AGC_MAX
155754. DVBT_IF_AGC_MIN
155755. DVBT_IF_AGC_VAL
155756. DVBT_IIC_REPEAT
155757. DVBT_INTER_CNT_LEN
155758. DVBT_K1_CR_STEP12
155759. DVBT_KB_P1
155760. DVBT_KB_P2
155761. DVBT_KB_P3
155762. DVBT_KRF
155763. DVBT_KRF1
155764. DVBT_KRF2
155765. DVBT_KRF3
155766. DVBT_KRF4
155767. DVBT_LOCK_TH
155768. DVBT_LOCK_TH_LEN
155769. DVBT_LOOP_GAIN2_3_0
155770. DVBT_LOOP_GAIN2_4
155771. DVBT_LOOP_GAIN3
155772. DVBT_LOOP_GAIN_3_0
155773. DVBT_LOOP_GAIN_4
155774. DVBT_MGD_THD0
155775. DVBT_MGD_THD1
155776. DVBT_MGD_THD2
155777. DVBT_MGD_THD3
155778. DVBT_MGD_THD4
155779. DVBT_MGD_THD5
155780. DVBT_MGD_THD6
155781. DVBT_MGD_THD7
155782. DVBT_MPEG_IO_OPT_1_0
155783. DVBT_MPEG_IO_OPT_2_2
155784. DVBT_OPT_ADC_IQ
155785. DVBT_PD_DA8
155786. DVBT_PIP_ON
155787. DVBT_POLAR_IF_AGC
155788. DVBT_POLAR_RF_AGC
155789. DVBT_PSET_IFFREQ
155790. DVBT_REG_4MSEL
155791. DVBT_REG_BIT_NAME
155792. DVBT_REG_BIT_NAME_ITEM_TERMINATOR
155793. DVBT_REG_GPE
155794. DVBT_REG_GPO
155795. DVBT_REG_MON
155796. DVBT_REG_MONSEL
155797. DVBT_REG_PFREQ_1_0
155798. DVBT_REG_PI
155799. DVBT_RF_AGC_MAN
155800. DVBT_RF_AGC_MAN_VAL
155801. DVBT_RF_AGC_MAX
155802. DVBT_RF_AGC_MIN
155803. DVBT_RF_AGC_VAL
155804. DVBT_RSAMP_RATIO
155805. DVBT_RSD_BER_EST
155806. DVBT_RSD_BER_FAIL_VAL
155807. DVBT_RSSI_R
155808. DVBT_RX_CONSTEL
155809. DVBT_RX_C_RATE_HP
155810. DVBT_RX_C_RATE_LP
155811. DVBT_RX_HIER
155812. DVBT_SCALE1_B92
155813. DVBT_SCALE1_B93
155814. DVBT_SCALE1_BA7
155815. DVBT_SCALE1_BA9
155816. DVBT_SCALE1_BAA
155817. DVBT_SCALE1_BAB
155818. DVBT_SCALE1_BAC
155819. DVBT_SCALE1_BB0
155820. DVBT_SCALE1_BB1
155821. DVBT_SERIAL
155822. DVBT_SER_LSB
155823. DVBT_SFREQ_OFF
155824. DVBT_SM_PASS
155825. DVBT_SOFT_RST
155826. DVBT_SPEC_INIT_0
155827. DVBT_SPEC_INIT_1
155828. DVBT_SPEC_INIT_2
155829. DVBT_SPEC_INV
155830. DVBT_SYNC_DUR
155831. DVBT_SYNC_LVL
155832. DVBT_SYNC_LVL_PID
155833. DVBT_SYNC_LVL_PIP
155834. DVBT_TEST_REG_1
155835. DVBT_TEST_REG_2
155836. DVBT_TEST_REG_3
155837. DVBT_TEST_REG_4
155838. DVBT_THD_DW1
155839. DVBT_THD_LOCK_DW
155840. DVBT_THD_LOCK_UP
155841. DVBT_THD_UP1
155842. DVBT_TRK_KC_I2
155843. DVBT_TRK_KC_P2
155844. DVBT_TRK_KS_I2
155845. DVBT_TRK_KS_P2
155846. DVBT_TR_THD_SET2
155847. DVBT_TR_WAIT_MIN_8K
155848. DVBT_UPDATE_REG_2
155849. DVBT_VAL_LVL
155850. DVBT_VAL_LVL_PID
155851. DVBT_VAL_LVL_PIP
155852. DVBT_VTOP
155853. DVBT_VTOP1
155854. DVBT_VTOP2
155855. DVBT_VTOP3
155856. DVBUSDIS
155857. DVBUSPULSE
155858. DVBV3_ATSC
155859. DVBV3_OFDM
155860. DVBV3_QAM
155861. DVBV3_QPSK
155862. DVBV3_UNKNOWN
155863. DVB_ADAC_CRYSTAL
155864. DVB_ADAC_MSP34x0
155865. DVB_ADAC_MSP34x5
155866. DVB_ADAC_NONE
155867. DVB_ADAC_TI
155868. DVB_API_VERSION
155869. DVB_API_VERSION_MINOR
155870. DVB_BT8XX_H
155871. DVB_BUF_TYPE_CAPTURE
155872. DVB_CA_EN50221_CAMCHANGE_INSERTED
155873. DVB_CA_EN50221_CAMCHANGE_REMOVED
155874. DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE
155875. DVB_CA_EN50221_FLAG_IRQ_DA
155876. DVB_CA_EN50221_FLAG_IRQ_FR
155877. DVB_CA_EN50221_POLL_CAM_CHANGED
155878. DVB_CA_EN50221_POLL_CAM_PRESENT
155879. DVB_CA_EN50221_POLL_CAM_READY
155880. DVB_CA_SLOTSTATE_INVALID
155881. DVB_CA_SLOTSTATE_LINKINIT
155882. DVB_CA_SLOTSTATE_NONE
155883. DVB_CA_SLOTSTATE_RUNNING
155884. DVB_CA_SLOTSTATE_UNINITIALISED
155885. DVB_CA_SLOTSTATE_VALIDATE
155886. DVB_CA_SLOTSTATE_WAITFR
155887. DVB_CA_SLOTSTATE_WAITREADY
155888. DVB_DEFINE_MOD_OPT_ADAPTER_NR
155889. DVB_DEMUX_MASK_MAX
155890. DVB_DEVICE_AUDIO
155891. DVB_DEVICE_CA
155892. DVB_DEVICE_DEMUX
155893. DVB_DEVICE_DVR
155894. DVB_DEVICE_FRONTEND
155895. DVB_DEVICE_NET
155896. DVB_DEVICE_OSD
155897. DVB_DEVICE_SEC
155898. DVB_DEVICE_VIDEO
155899. DVB_DUMMY_FE_H
155900. DVB_EXCEPT_SLICE
155901. DVB_EXTENSION_START
155902. DVB_FE_DEVICE_REMOVED
155903. DVB_FE_DEVICE_RESUME
155904. DVB_FE_NORMAL_EXIT
155905. DVB_FE_NO_EXIT
155906. DVB_FRONTEND_COMPONENT_DEMOD
155907. DVB_FRONTEND_COMPONENT_TUNER
155908. DVB_GOP_START
155909. DVB_IX2505V_H
155910. DVB_MAJOR
155911. DVB_MAX_ADAPTERS
155912. DVB_MAX_IDS
155913. DVB_NET_DEVICES_MAX
155914. DVB_NET_FEEDTYPE_MPE
155915. DVB_NET_FEEDTYPE_ULE
155916. DVB_NET_MULTICAST_MAX
155917. DVB_PICTURE_START
155918. DVB_PLL_ENV57H1XD5
155919. DVB_PLL_LG_Z201
155920. DVB_PLL_MAX
155921. DVB_PLL_OPERA1
155922. DVB_PLL_PHILIPS_SD1878_TDA8261
155923. DVB_PLL_SAMSUNG_DTOS403IH102A
155924. DVB_PLL_SAMSUNG_TBDU18132
155925. DVB_PLL_SAMSUNG_TBMU24112
155926. DVB_PLL_SAMSUNG_TBMV
155927. DVB_PLL_SAMSUNG_TDTC9251DH0
155928. DVB_PLL_TDA665X
155929. DVB_PLL_TDA665X_EARTH_PT1
155930. DVB_PLL_TDED4
155931. DVB_PLL_TDEE4
155932. DVB_PLL_TDHU2
155933. DVB_PLL_THOMSON_DTT7520X
155934. DVB_PLL_THOMSON_DTT7579
155935. DVB_PLL_THOMSON_DTT759X
155936. DVB_PLL_TUA6010XS
155937. DVB_PLL_TUA6034
155938. DVB_PLL_TUA6034_FRIIO
155939. DVB_PLL_UNDEFINED
155940. DVB_PLL_UNKNOWN_1
155941. DVB_RC_CORE
155942. DVB_RC_LEGACY
155943. DVB_RINGBUFFER_PEEK
155944. DVB_RINGBUFFER_PKTHDRSIZE
155945. DVB_RINGBUFFER_SKIP
155946. DVB_RINGBUFFER_WRITE_BYTE
155947. DVB_SEQUENCE_END
155948. DVB_SEQUENCE_ERROR
155949. DVB_SEQUENCE_HEADER
155950. DVB_UNSET
155951. DVB_USB_ADAP_HAS_PID_FILTER
155952. DVB_USB_ADAP_NEED_PID_FILTERING
155953. DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF
155954. DVB_USB_ADAP_RECEIVES_204_BYTE_TS
155955. DVB_USB_ADAP_RECEIVES_RAW_PAYLOAD
155956. DVB_USB_ADAP_STATE_DVB
155957. DVB_USB_ADAP_STATE_INIT
155958. DVB_USB_COMMON_H
155959. DVB_USB_DEBUG_STATUS
155960. DVB_USB_DEVICE
155961. DVB_USB_FE_TS_TYPE_188
155962. DVB_USB_FE_TS_TYPE_204
155963. DVB_USB_FE_TS_TYPE_RAW
155964. DVB_USB_H
155965. DVB_USB_ID_MAX_NUM
155966. DVB_USB_IS_AN_I2C_ADAPTER
155967. DVB_USB_LOG_PREFIX
155968. DVB_USB_RC_NEC_EMPTY
155969. DVB_USB_RC_NEC_KEY_PRESSED
155970. DVB_USB_RC_NEC_KEY_REPEATED
155971. DVB_USB_STATE_DVB
155972. DVB_USB_STATE_I2C
155973. DVB_USB_STATE_INIT
155974. DVB_USB_STATE_REMOTE
155975. DVB_USB_STREAM_BULK
155976. DVB_USB_STREAM_ISOC
155977. DVB_USER_START
155978. DVB_V2_MAX_SIZE
155979. DVB_VB2_NAME_MAX
155980. DVB_VB2_STATE_INIT
155981. DVB_VB2_STATE_NONE
155982. DVB_VB2_STATE_REQBUFS
155983. DVB_VB2_STATE_STREAMON
155984. DVB_ZL10036_H
155985. DVC
155986. DVCO_RATE_TO_MULT
155987. DVCSR
155988. DVCSR_VCnFB2_DSA0
155989. DVCSR_VCnFB2_DSA1
155990. DVCSR_VCnFB2_DSA2
155991. DVCSR_VCnFB2_INIT
155992. DVCSR_VCnFB2_MASK
155993. DVCSR_VCnFB_DSA0
155994. DVCSR_VCnFB_DSA1
155995. DVCSR_VCnFB_DSA2
155996. DVCSR_VCnFB_INIT
155997. DVCSR_VCnFB_MASK
155998. DVC_ADINR
155999. DVC_CTRL_REG1
156000. DVC_CTRL_REG1_INTR_EN
156001. DVC_CTRL_REG3
156002. DVC_CTRL_REG3_I2C_DONE_INTR_EN
156003. DVC_CTRL_REG3_SW_PROG
156004. DVC_DVUCR
156005. DVC_DVUER
156006. DVC_DVUIR
156007. DVC_MUTE_MARK
156008. DVC_NAME
156009. DVC_STATUS
156010. DVC_STATUS_I2C_DONE_INTR
156011. DVC_SWRSR
156012. DVC_VOL0R
156013. DVC_VOL1R
156014. DVC_VOL2R
156015. DVC_VOL3R
156016. DVC_VOL4R
156017. DVC_VOL5R
156018. DVC_VOL6R
156019. DVC_VOL7R
156020. DVC_VOLxR
156021. DVC_VRCTR
156022. DVC_VRDBR
156023. DVC_VRPDR
156024. DVC_ZCMCR
156025. DVDBG
156026. DVDCopyrightImpUse
156027. DVDD
156028. DVDET
156029. DVDET_VDEF
156030. DVDET_VDES
156031. DVD_AUTH
156032. DVD_AUTH_ESTABLISHED
156033. DVD_AUTH_FAILURE
156034. DVD_CGMS_RESTRICTED
156035. DVD_CGMS_SINGLE
156036. DVD_CGMS_UNRESTRICTED
156037. DVD_CPM_COPYRIGHTED
156038. DVD_CPM_NO_COPYRIGHT
156039. DVD_CP_SEC_EXIST
156040. DVD_CP_SEC_NONE
156041. DVD_HOST_SEND_CHALLENGE
156042. DVD_HOST_SEND_KEY2
156043. DVD_HOST_SEND_RPC_STATE
156044. DVD_INVALIDATE_AGID
156045. DVD_LAYERS
156046. DVD_LU_SEND_AGID
156047. DVD_LU_SEND_ASF
156048. DVD_LU_SEND_CHALLENGE
156049. DVD_LU_SEND_KEY1
156050. DVD_LU_SEND_RPC_STATE
156051. DVD_LU_SEND_TITLE_KEY
156052. DVD_PORT_DMA
156053. DVD_READ_STRUCT
156054. DVD_STRUCT_BCA
156055. DVD_STRUCT_COPYRIGHT
156056. DVD_STRUCT_DISCKEY
156057. DVD_STRUCT_MANUFACT
156058. DVD_STRUCT_PHYSICAL
156059. DVD_WRITE_STRUCT
156060. DVECTRL
156061. DVECTRL_VEVENT
156062. DVECTRL_VFETCH
156063. DVER
156064. DVFS
156065. DVFS_ARM100OPPOK
156066. DVFS_ARM50OPPOK
156067. DVFS_ARMEXTCLKOK
156068. DVFS_DFLL_RESET_SHIFT
156069. DVFS_GO
156070. DVFS_INITSTATUS
156071. DVFS_MAX_REGFIELDS
156072. DVFS_NOCHGTCLKOK
156073. DVF_Analog
156074. DVF_ByteStream
156075. DVF_CCIR656
156076. DVF_CODE
156077. DVF_ExtField
156078. DVF_ExtVSYNC
156079. DVGA_CONTROL_MODE_ENABLE
156080. DVGA_CONTROL_OVERSCAN_COLOR_EN
156081. DVGA_CONTROL_OVERSCAN_TIMING_SELECT
156082. DVGA_CONTROL_ROTATE
156083. DVGA_CONTROL_SYNC_POLARITY_SELECT
156084. DVGA_CONTROL_TIMING_SELECT
156085. DVICO_BLUEBIRD_DUAL_1_COLD
156086. DVICO_BLUEBIRD_DUAL_1_WARM
156087. DVICO_BLUEBIRD_DUAL_2_COLD
156088. DVICO_BLUEBIRD_DUAL_2_WARM
156089. DVICO_BLUEBIRD_DUAL_4
156090. DVICO_BLUEBIRD_DUAL_4_REV_2
156091. DVICO_BLUEBIRD_DVB_T_NANO_2
156092. DVICO_BLUEBIRD_DVB_T_NANO_2_NFW_WARM
156093. DVICO_BLUEBIRD_LG064F_COLD
156094. DVICO_BLUEBIRD_LG064F_WARM
156095. DVICO_BLUEBIRD_LGZ201_COLD
156096. DVICO_BLUEBIRD_LGZ201_WARM
156097. DVICO_BLUEBIRD_TH7579_COLD
156098. DVICO_BLUEBIRD_TH7579_WARM
156099. DVID
156100. DVI_CTRL_SII164
156101. DVI_Device
156102. DVI_HDMI_DONGLE_ADDRESS
156103. DVI_I2C_CNTL_1
156104. DVI_PANEL_ID0_640X480
156105. DVI_PANEL_ID1_1024x768
156106. DVI_PANEL_ID1_1280x1024
156107. DVI_PANEL_ID1_1280x768
156108. DVI_PANEL_ID1_1400x1050
156109. DVI_PANEL_ID1_1600x1200
156110. DVI_PANEL_ID1_800x600
156111. DVLNUM
156112. DVLNUM_VLINE
156113. DVMA_ALIGN
156114. DVMA_DEBUG
156115. DVMA_END
156116. DVMA_PAGE_ALIGN
156117. DVMA_PAGE_MASK
156118. DVMA_PAGE_SHIFT
156119. DVMA_PAGE_SIZE
156120. DVMA_PMEG_END
156121. DVMA_PMEG_START
156122. DVMA_REGION_SIZE
156123. DVMA_SIZE
156124. DVMA_START
156125. DVMA_VADDR
156126. DVMM_CNTL__DBG_DCE_VMID_MASK
156127. DVMM_CNTL__DBG_DCE_VMID__SHIFT
156128. DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK
156129. DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT
156130. DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK
156131. DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT
156132. DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK
156133. DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT
156134. DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK
156135. DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT
156136. DVMM_CNTL__OVERRIDE_SNOOP_MASK
156137. DVMM_CNTL__OVERRIDE_SNOOP__SHIFT
156138. DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK
156139. DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT
156140. DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK
156141. DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT
156142. DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK
156143. DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT
156144. DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
156145. DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
156146. DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
156147. DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
156148. DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
156149. DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
156150. DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
156151. DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
156152. DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
156153. DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
156154. DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
156155. DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
156156. DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
156157. DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
156158. DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
156159. DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
156160. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK
156161. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT
156162. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK
156163. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT
156164. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK
156165. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT
156166. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK
156167. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT
156168. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK
156169. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT
156170. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK
156171. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT
156172. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK
156173. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT
156174. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK
156175. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT
156176. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK
156177. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT
156178. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK
156179. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT
156180. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK
156181. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT
156182. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK
156183. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT
156184. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK
156185. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT
156186. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK
156187. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT
156188. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK
156189. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT
156190. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK
156191. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT
156192. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK
156193. DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT
156194. DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK
156195. DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT
156196. DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK
156197. DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT
156198. DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK
156199. DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT
156200. DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK
156201. DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT
156202. DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK
156203. DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT
156204. DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK
156205. DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT
156206. DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK
156207. DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT
156208. DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK
156209. DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT
156210. DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK
156211. DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT
156212. DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK
156213. DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT
156214. DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK
156215. DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT
156216. DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK
156217. DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT
156218. DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK
156219. DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT
156220. DVM_OP_MODE
156221. DVOA
156222. DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK
156223. DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT
156224. DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK
156225. DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT
156226. DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK
156227. DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT
156228. DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK
156229. DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT
156230. DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK
156231. DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT
156232. DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO
156233. DVOACLKC_IN_PHASE
156234. DVOACLKC_IN_PHASE_WITH_PCLK_DVO
156235. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK
156236. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT
156237. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK
156238. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT
156239. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK
156240. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT
156241. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK
156242. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT
156243. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK
156244. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT
156245. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK
156246. DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT
156247. DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK
156248. DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT
156249. DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK
156250. DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT
156251. DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO
156252. DVOACLKC_MVP_IN_PHASE
156253. DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO
156254. DVOACLKC_MVP_SKEW_PHASE_OVERRIDE
156255. DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE
156256. DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE
156257. DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK
156258. DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT
156259. DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK
156260. DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT
156261. DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK
156262. DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT
156263. DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK
156264. DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT
156265. DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK
156266. DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT
156267. DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO
156268. DVOACLKD_IN_PHASE
156269. DVOACLKD_IN_PHASE_WITH_PCLK_DVO
156270. DVOACLK_COARSE_SKEW_CNTL
156271. DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS
156272. DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS
156273. DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS
156274. DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS
156275. DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS
156276. DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS
156277. DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP
156278. DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS
156279. DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS
156280. DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS
156281. DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS
156282. DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS
156283. DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS
156284. DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS
156285. DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS
156286. DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS
156287. DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS
156288. DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS
156289. DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS
156290. DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS
156291. DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS
156292. DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP
156293. DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS
156294. DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS
156295. DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS
156296. DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS
156297. DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS
156298. DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS
156299. DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS
156300. DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS
156301. DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT
156302. DVOACLK_FINE_SKEW_CNTL
156303. DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP
156304. DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS
156305. DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS
156306. DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP
156307. DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS
156308. DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS
156309. DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS
156310. DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT
156311. DVOA_PORT
156312. DVOA_SRCDIM
156313. DVOB
156314. DVOB_PORT
156315. DVOB_SRCDIM
156316. DVOC
156317. DVOC_PORT
156318. DVOC_SRCDIM
156319. DVOL_CTL_DVMUTE_OFF
156320. DVOL_CTL_DVMUTE_ON
156321. DVO_AWG_CTRL_EN
156322. DVO_AWG_DIGSYNC_CTRL
156323. DVO_AWG_FRAME_BASED_SYNC
156324. DVO_B
156325. DVO_BLANK_ACTIVE_HIGH
156326. DVO_BORDER_ENABLE
156327. DVO_C
156328. DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK
156329. DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT
156330. DVO_CONTROL__DVO_COLOR_FORMAT_MASK
156331. DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT
156332. DVO_CONTROL__DVO_CTL3_MASK
156333. DVO_CONTROL__DVO_CTL3__SHIFT
156334. DVO_CONTROL__DVO_DE_POLARITY_MASK
156335. DVO_CONTROL__DVO_DE_POLARITY__SHIFT
156336. DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK
156337. DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT
156338. DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK
156339. DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT
156340. DVO_CONTROL__DVO_HSYNC_POLARITY_MASK
156341. DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT
156342. DVO_CONTROL__DVO_INVERT_DVOCLK_MASK
156343. DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT
156344. DVO_CONTROL__DVO_RATE_SELECT_MASK
156345. DVO_CONTROL__DVO_RATE_SELECT__SHIFT
156346. DVO_CONTROL__DVO_RESET_FIFO_MASK
156347. DVO_CONTROL__DVO_RESET_FIFO__SHIFT
156348. DVO_CONTROL__DVO_SDRCLK_SEL_MASK
156349. DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT
156350. DVO_CONTROL__DVO_SYNC_PHASE_MASK
156351. DVO_CONTROL__DVO_SYNC_PHASE__SHIFT
156352. DVO_CONTROL__DVO_VSYNC_POLARITY_MASK
156353. DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT
156354. DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK
156355. DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT
156356. DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK
156357. DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT
156358. DVO_CRC_EN__DVO_CRC2_EN_MASK
156359. DVO_CRC_EN__DVO_CRC2_EN__SHIFT
156360. DVO_D
156361. DVO_DATA_ORDER_FP
156362. DVO_DATA_ORDER_GBRG
156363. DVO_DATA_ORDER_GBRG_ERRATA
156364. DVO_DATA_ORDER_I740
156365. DVO_DATA_ORDER_RGGB
156366. DVO_DATA_ORDER_RGGB_ERRATA
156367. DVO_DELAY
156368. DVO_DIGSYNC_INSTR_I
156369. DVO_DOF_CFG
156370. DVO_DOF_EN
156371. DVO_DOF_EN_HIGHBYTE
156372. DVO_DOF_EN_LOWBYTE
156373. DVO_DOF_EN_MIDBYTE
156374. DVO_DOF_MOD_COUNT_SHIFT
156375. DVO_ENABLE
156376. DVO_ENABLE_RST
156377. DVO_ENABLE_RST_DISABLE
156378. DVO_ENABLE_RST_ENABLE
156379. DVO_ENABLE__DVO_ENABLE_MASK
156380. DVO_ENABLE__DVO_ENABLE__SHIFT
156381. DVO_ENABLE__DVO_PIXEL_WIDTH_MASK
156382. DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT
156383. DVO_ENCODER_CONFIG_24BIT
156384. DVO_ENCODER_CONFIG_DDR_SPEED
156385. DVO_ENCODER_CONFIG_LOW12BIT
156386. DVO_ENCODER_CONFIG_OUTPUT_SEL
156387. DVO_ENCODER_CONFIG_RATE_SEL
156388. DVO_ENCODER_CONFIG_SDR_SPEED
156389. DVO_ENCODER_CONFIG_UPPER12BIT
156390. DVO_ENCODER_CONTROL_PARAMETERS
156391. DVO_ENCODER_CONTROL_PARAMETERS_LAST
156392. DVO_ENCODER_CONTROL_PARAMETERS_V1_4
156393. DVO_ENCODER_CONTROL_PARAMETERS_V3
156394. DVO_ENCODER_CONTROL_PS_ALLOCATION
156395. DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST
156396. DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4
156397. DVO_ENCODER_CONTROL_PS_ALLOCATION_V3
156398. DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK
156399. DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT
156400. DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK
156401. DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT
156402. DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK
156403. DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT
156404. DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK
156405. DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT
156406. DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK
156407. DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT
156408. DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK
156409. DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT
156410. DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK
156411. DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT
156412. DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK
156413. DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT
156414. DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK
156415. DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT
156416. DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK
156417. DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT
156418. DVO_HSYNC_ACTIVE_HIGH
156419. DVO_HSYNC_DISABLE
156420. DVO_HSYNC_TRISTATE
156421. DVO_LUT_CB_B
156422. DVO_LUT_CB_B_DEL
156423. DVO_LUT_CR_R
156424. DVO_LUT_CR_R_DEL
156425. DVO_LUT_HOLD
156426. DVO_LUT_PROG_HIGH
156427. DVO_LUT_PROG_LOW
156428. DVO_LUT_PROG_MID
156429. DVO_LUT_Y_G
156430. DVO_LUT_Y_G_DEL
156431. DVO_LUT_ZERO
156432. DVO_OUTPUT_CONTROL_PARAMETERS
156433. DVO_OUTPUT_CONTROL_PARAMETERS_V3
156434. DVO_OUTPUT_CONTROL_PS_ALLOCATION
156435. DVO_OUTPUT_CSTATE_PIXELS
156436. DVO_OUTPUT_SOURCE_SIZE_PIXELS
156437. DVO_OUTPUT__DVO_CLOCK_MODE_MASK
156438. DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT
156439. DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK
156440. DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT
156441. DVO_PIPE_SEL
156442. DVO_PIPE_SEL_MASK
156443. DVO_PIPE_SEL_SHIFT
156444. DVO_PIPE_STALL
156445. DVO_PIPE_STALL_MASK
156446. DVO_PIPE_STALL_TV
156447. DVO_PIPE_STALL_UNUSED
156448. DVO_PORT_CRT
156449. DVO_PORT_DPA
156450. DVO_PORT_DPB
156451. DVO_PORT_DPC
156452. DVO_PORT_DPD
156453. DVO_PORT_DPE
156454. DVO_PORT_DPF
156455. DVO_PORT_HDMIA
156456. DVO_PORT_HDMIB
156457. DVO_PORT_HDMIC
156458. DVO_PORT_HDMID
156459. DVO_PORT_HDMIE
156460. DVO_PORT_HDMIF
156461. DVO_PORT_LVDS
156462. DVO_PORT_MIPIA
156463. DVO_PORT_MIPIB
156464. DVO_PORT_MIPIC
156465. DVO_PORT_MIPID
156466. DVO_PORT_TV
156467. DVO_PRESERVE_MASK
156468. DVO_SIL1178
156469. DVO_SIL164
156470. DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK
156471. DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT
156472. DVO_SOFT_RESET
156473. DVO_SOFT_RESET_0
156474. DVO_SOFT_RESET_1
156475. DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK
156476. DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT
156477. DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK
156478. DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT
156479. DVO_SRCDIM_HORIZONTAL_SHIFT
156480. DVO_SRCDIM_VERTICAL_SHIFT
156481. DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK
156482. DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT
156483. DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK
156484. DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT
156485. DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK
156486. DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT
156487. DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK
156488. DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT
156489. DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK
156490. DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT
156491. DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK
156492. DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT
156493. DVO_STRENGTH_CONTROL__DVO_SN_MASK
156494. DVO_STRENGTH_CONTROL__DVO_SN__SHIFT
156495. DVO_STRENGTH_CONTROL__DVO_SP_MASK
156496. DVO_STRENGTH_CONTROL__DVO_SP__SHIFT
156497. DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK
156498. DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT
156499. DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK
156500. DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT
156501. DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK
156502. DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT
156503. DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK
156504. DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT
156505. DVO_USE_VGA_SYNC
156506. DVO_VREF_CONTROL__DVO_VREFCAL_MASK
156507. DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT
156508. DVO_VREF_CONTROL__DVO_VREFPON_MASK
156509. DVO_VREF_CONTROL__DVO_VREFPON__SHIFT
156510. DVO_VREF_CONTROL__DVO_VREFSEL_MASK
156511. DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT
156512. DVO_VSYNC_ACTIVE_HIGH
156513. DVO_VSYNC_DISABLE
156514. DVO_VSYNC_TRISTATE
156515. DVP_BFO
156516. DVP_BFS
156517. DVP_CTL
156518. DVP_CTL_DIS
156519. DVP_CTL_ENA
156520. DVP_CTL_RST
156521. DVP_HLFLN
156522. DVP_HLFLN_SD
156523. DVP_ITM
156524. DVP_ITS
156525. DVP_IT_FIFO
156526. DVP_IT_VSB
156527. DVP_IT_VST
156528. DVP_PKZ
156529. DVP_RGB
156530. DVP_STA
156531. DVP_TFO
156532. DVP_TFS
156533. DVP_VBP
156534. DVP_VMP
156535. DVP_VTP
156536. DVRFLT_SEL
156537. DVR_BUFFER_SIZE
156538. DVR_FEED
156539. DVR_TSOUT
156540. DVSCNTR
156541. DVSE
156542. DVSGAMCMAX_ILK
156543. DVSGAMC_G4X
156544. DVSGAMC_ILK
156545. DVSKEYMAX
156546. DVSKEYMSK
156547. DVSKEYVAL
156548. DVSLINOFF
156549. DVSPOS
156550. DVSQ
156551. DVSQS
156552. DVSQ_MASK
156553. DVSSCALE
156554. DVSSIZE
156555. DVSSTRIDE
156556. DVSSURF
156557. DVSSURFLIVE
156558. DVST
156559. DVSTCTR
156560. DVSTCTR0
156561. DVSTCTR1
156562. DVSTILEOFF
156563. DVSUNIT_CLOCK_GATE_DISABLE
156564. DVSUP_HIGH
156565. DVSUP_LOW
156566. DVSUP_MEDIUM
156567. DVSUP_TURBO
156568. DVS_BUCK_IDLE_MASK
156569. DVS_BUCK_RUN_MASK
156570. DVS_BUCK_SUSP_MASK
156571. DVS_DEST_KEY
156572. DVS_ENABLE
156573. DVS_FILTER_ENHANCING
156574. DVS_FILTER_MASK
156575. DVS_FILTER_MEDIUM
156576. DVS_FILTER_SOFTENING
156577. DVS_FORMAT_RGBX101010
156578. DVS_FORMAT_RGBX161616
156579. DVS_FORMAT_RGBX888
156580. DVS_FORMAT_YUV422
156581. DVS_GAMMA_ENABLE
156582. DVS_HIGH
156583. DVS_LOW
156584. DVS_PIPE_CSC_ENABLE
156585. DVS_PIXFORMAT_MASK
156586. DVS_RGB_ORDER_XBGR
156587. DVS_ROTATE_180
156588. DVS_SCALE_ENABLE
156589. DVS_SEL_V0
156590. DVS_SEL_V1
156591. DVS_SEL_V2
156592. DVS_SEL_V3
156593. DVS_SOURCE_KEY
156594. DVS_TILED
156595. DVS_TRICKLE_FEED_DISABLE
156596. DVS_VERTICAL_OFFSET_ENABLE
156597. DVS_VERTICAL_OFFSET_HALF
156598. DVS_YUV_BYTE_ORDER_MASK
156599. DVS_YUV_FORMAT_BT709
156600. DVS_YUV_ORDER_UYVY
156601. DVS_YUV_ORDER_VYUY
156602. DVS_YUV_ORDER_YUYV
156603. DVS_YUV_ORDER_YVYU
156604. DVS_YUV_RANGE_CORRECTION_DISABLE
156605. DVT01
156606. DVT01_VBPS
156607. DVT01_VT
156608. DVT02
156609. DVT02_VAS
156610. DVT02_VTBS
156611. DVT03
156612. DVT03_VBBS
156613. DVT03_VFPS
156614. DV_CLKI_MARK
156615. DV_CLK_MARK
156616. DV_CbAlign
156617. DV_CrAlign
156618. DV_D0_MARK
156619. DV_D10_MARK
156620. DV_D11_MARK
156621. DV_D12_MARK
156622. DV_D13_MARK
156623. DV_D14_MARK
156624. DV_D15_MARK
156625. DV_D1_MARK
156626. DV_D2_MARK
156627. DV_D3_MARK
156628. DV_D4_MARK
156629. DV_D5_MARK
156630. DV_D6_MARK
156631. DV_D7_MARK
156632. DV_D8_MARK
156633. DV_D9_MARK
156634. DV_DATA0_MARK
156635. DV_DATA10_MARK
156636. DV_DATA11_MARK
156637. DV_DATA12_MARK
156638. DV_DATA13_MARK
156639. DV_DATA14_MARK
156640. DV_DATA15_MARK
156641. DV_DATA16_MARK
156642. DV_DATA17_MARK
156643. DV_DATA18_MARK
156644. DV_DATA19_MARK
156645. DV_DATA1_MARK
156646. DV_DATA20_MARK
156647. DV_DATA21_MARK
156648. DV_DATA22_MARK
156649. DV_DATA23_MARK
156650. DV_DATA2_MARK
156651. DV_DATA3_MARK
156652. DV_DATA4_MARK
156653. DV_DATA5_MARK
156654. DV_DATA6_MARK
156655. DV_DATA7_MARK
156656. DV_DATA8_MARK
156657. DV_DATA9_MARK
156658. DV_HSYNC_MARK
156659. DV_LOOPS
156660. DV_RETRIES
156661. DV_SET
156662. DV_TIMEOUT
156663. DV_VSYNC_MARK
156664. DV_Y0Align
156665. DV_Y1Align
156666. DW
156667. DW0_ADDRESS
156668. DW0_DIRECT
156669. DW0_ENDPNT
156670. DW0_FORMAT
156671. DW0_HALTED
156672. DW0_MAXPKTSIZ
156673. DW0_SNDNAK
156674. DW0_SPEED
156675. DW0_TOGCRY
156676. DW0_VALID_BIT
156677. DW1_SE_USB_LOSPEED
156678. DW1_TRANS_BULK
156679. DW1_TRANS_INT
156680. DW1_TRANS_SPLIT
156681. DW1_XBUFSRTAD
156682. DW1_YBUFSRTAD
156683. DW2101_FIRMWARE
156684. DW2102_FIRMWARE
156685. DW2102_LED_CTRL
156686. DW2102_RC_QUERY
156687. DW2102_VOLTAGE_CTRL
156688. DW2104_FIRMWARE
156689. DW210X_READ_MSG
156690. DW210X_WRITE_MSG
156691. DW28_OLDO_DYN_PWR_DOWN_EN
156692. DW2_BUFROUND
156693. DW2_COMPCODE
156694. DW2_DATATOG
156695. DW2_DELAYINT
156696. DW2_DIRPID
156697. DW2_ERRORCNT
156698. DW2_POLINTERV
156699. DW2_RELPOLPOS
156700. DW2_RTRYDELAY
156701. DW2_STARTFRM
156702. DW3101_FIRMWARE
156703. DW3_ACTIVE_BIT
156704. DW3_BABBLE_BIT
156705. DW3_BUFSIZE
156706. DW3_COMPCODE0
156707. DW3_COMPCODE1
156708. DW3_ERROR_BIT
156709. DW3_HALT_BIT
156710. DW3_PKTLEN0
156711. DW3_PKTLEN1
156712. DW3_TOTBYECNT
156713. DW64_CIE_ID
156714. DW6_OLDO_DYN_PWR_DOWN_EN
156715. DW8
156716. DW8051_CLK_EN
156717. DW8051_INT
156718. DW9714_CTRL_DELAY_US
156719. DW9714_CTRL_STEPS
156720. DW9714_DEFAULT_S
156721. DW9714_FOCUS_STEPS
156722. DW9714_MAX_FOCUS_POS
156723. DW9714_NAME
156724. DW9714_VAL
156725. DW9807_CTL_ADDR
156726. DW9807_CTRL_DELAY_US
156727. DW9807_CTRL_STEPS
156728. DW9807_FOCUS_STEPS
156729. DW9807_LSB_ADDR
156730. DW9807_MAX_FOCUS_POS
156731. DW9807_MODE_ADDR
156732. DW9807_MSB_ADDR
156733. DW9807_RESONANCE_ADDR
156734. DW9807_STATUS_ADDR
156735. DWAPB_MAX_PORTS
156736. DWARFNUM2OFFSET
156737. DWARF_ARCH_RA_REG
156738. DWARF_CIE_Z_AUGMENTATION
156739. DWARF_DEBUG
156740. DWARF_EH_FRAME
156741. DWARF_FRAME_CFA_REG_EXP
156742. DWARF_FRAME_CFA_REG_OFFSET
156743. DWARF_FRAME_MIN_REQ
156744. DWARF_MINIMAL_REGS
156745. DWARF_REG_MIN_REQ
156746. DWARF_REG_OFFSET
156747. DWARF_UNDEFINED
156748. DWARF_VAL_OFFSET
156749. DWAXIDMAC_ARWLEN_1
156750. DWAXIDMAC_ARWLEN_128
156751. DWAXIDMAC_ARWLEN_16
156752. DWAXIDMAC_ARWLEN_2
156753. DWAXIDMAC_ARWLEN_256
156754. DWAXIDMAC_ARWLEN_32
156755. DWAXIDMAC_ARWLEN_4
156756. DWAXIDMAC_ARWLEN_64
156757. DWAXIDMAC_ARWLEN_8
156758. DWAXIDMAC_ARWLEN_MAX
156759. DWAXIDMAC_ARWLEN_MIN
156760. DWAXIDMAC_BURST_TRANS_LEN_1
156761. DWAXIDMAC_BURST_TRANS_LEN_1024
156762. DWAXIDMAC_BURST_TRANS_LEN_128
156763. DWAXIDMAC_BURST_TRANS_LEN_16
156764. DWAXIDMAC_BURST_TRANS_LEN_256
156765. DWAXIDMAC_BURST_TRANS_LEN_32
156766. DWAXIDMAC_BURST_TRANS_LEN_4
156767. DWAXIDMAC_BURST_TRANS_LEN_512
156768. DWAXIDMAC_BURST_TRANS_LEN_64
156769. DWAXIDMAC_BURST_TRANS_LEN_8
156770. DWAXIDMAC_CH_CTL_L_INC
156771. DWAXIDMAC_CH_CTL_L_NOINC
156772. DWAXIDMAC_HS_SEL_HW
156773. DWAXIDMAC_HS_SEL_SW
156774. DWAXIDMAC_IRQ_ABORTED
156775. DWAXIDMAC_IRQ_ALL
156776. DWAXIDMAC_IRQ_ALL_ERR
156777. DWAXIDMAC_IRQ_BLOCK_TRF
156778. DWAXIDMAC_IRQ_DEC_ERR
156779. DWAXIDMAC_IRQ_DISABLED
156780. DWAXIDMAC_IRQ_DMA_TRF
156781. DWAXIDMAC_IRQ_DST_DEC_ERR
156782. DWAXIDMAC_IRQ_DST_SLV_ERR
156783. DWAXIDMAC_IRQ_DST_TRAN
156784. DWAXIDMAC_IRQ_INVALID_ERR
156785. DWAXIDMAC_IRQ_LLI_RD_DEC_ERR
156786. DWAXIDMAC_IRQ_LLI_RD_SLV_ERR
156787. DWAXIDMAC_IRQ_LLI_WR_DEC_ERR
156788. DWAXIDMAC_IRQ_LLI_WR_SLV_ERR
156789. DWAXIDMAC_IRQ_LOCK_CLEARED
156790. DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR
156791. DWAXIDMAC_IRQ_NONE
156792. DWAXIDMAC_IRQ_RD2RWO_ERR
156793. DWAXIDMAC_IRQ_SHADOWREG_ERR
156794. DWAXIDMAC_IRQ_SRC_DEC_ERR
156795. DWAXIDMAC_IRQ_SRC_SLV_ERR
156796. DWAXIDMAC_IRQ_SRC_SUSPENDED
156797. DWAXIDMAC_IRQ_SRC_TRAN
156798. DWAXIDMAC_IRQ_SUSPENDED
156799. DWAXIDMAC_IRQ_WR2RO_ERR
156800. DWAXIDMAC_IRQ_WRONCHEN_ERR
156801. DWAXIDMAC_IRQ_WRONHOLD_ERR
156802. DWAXIDMAC_MBLK_TYPE_CONTIGUOUS
156803. DWAXIDMAC_MBLK_TYPE_LL
156804. DWAXIDMAC_MBLK_TYPE_RELOAD
156805. DWAXIDMAC_MBLK_TYPE_SHADOW_REG
156806. DWAXIDMAC_TRANS_WIDTH_128
156807. DWAXIDMAC_TRANS_WIDTH_16
156808. DWAXIDMAC_TRANS_WIDTH_256
156809. DWAXIDMAC_TRANS_WIDTH_32
156810. DWAXIDMAC_TRANS_WIDTH_512
156811. DWAXIDMAC_TRANS_WIDTH_64
156812. DWAXIDMAC_TRANS_WIDTH_8
156813. DWAXIDMAC_TRANS_WIDTH_MAX
156814. DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC
156815. DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC
156816. DWAXIDMAC_TT_FC_MEM_TO_PER_DST
156817. DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC
156818. DWAXIDMAC_TT_FC_PER_TO_MEM_SRC
156819. DWAXIDMAC_TT_FC_PER_TO_PER_DMAC
156820. DWAXIDMAC_TT_FC_PER_TO_PER_DST
156821. DWAXIDMAC_TT_FC_PER_TO_PER_SRC
156822. DWA_NOTIF_PORTSTATUS
156823. DWA_NOTIF_RWAKE
156824. DWBC_COMMON_MASK_SH_LIST_DCN1_0
156825. DWBC_COMMON_MASK_SH_LIST_DCN2_0
156826. DWBC_COMMON_REG_LIST_DCN1_0
156827. DWBC_COMMON_REG_LIST_DCN2_0
156828. DWBC_REG_FIELD_LIST
156829. DWBC_REG_FIELD_LIST_DCN2_0
156830. DWB_CNV_OUT_BPC_10BPC
156831. DWB_CNV_OUT_BPC_8BPC
156832. DWB_COSITED_SUBSAMPLING
156833. DWB_DATA_DEPTH_WARMUP_10BPC
156834. DWB_DATA_DEPTH_WARMUP_8BPC
156835. DWB_DATA_DEPTH_WARMUP_ENUM
156836. DWB_FRAME_CAPTURE_DISABLE
156837. DWB_FRAME_CAPTURE_ENABLE
156838. DWB_GMC_WARM_UP_DISABLE
156839. DWB_GMC_WARM_UP_ENABLE
156840. DWB_GMC_WARM_UP_ENABLE_ENUM
156841. DWB_INTERSTITIAL_SUBSAMPLING
156842. DWB_MCIF_BUF_COUNT
156843. DWB_MODE_WARMUP_420
156844. DWB_MODE_WARMUP_444
156845. DWB_MODE_WARMUP_ENUM
156846. DWB_OUTPUT_PIXEL_DEPTH_10BPC
156847. DWB_OUTPUT_PIXEL_DEPTH_8BPC
156848. DWB_OUTSIDE_PIX_STRATEGY_BLACK
156849. DWB_OUTSIDE_PIX_STRATEGY_EDGE
156850. DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK
156851. DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT
156852. DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK
156853. DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT
156854. DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK
156855. DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT
156856. DWB_STEREO_EYE_LEFT
156857. DWB_STEREO_EYE_RIGHT
156858. DWB_STEREO_TYPE_FRAME_PACKING
156859. DWB_STEREO_TYPE_FRAME_SEQUENTIAL
156860. DWB_SW_V2
156861. DWC2_CAP_PARAM_HNP_SRP_CAPABLE
156862. DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
156863. DWC2_CAP_PARAM_SRP_ONLY_CAPABLE
156864. DWC2_CMPL_DONE
156865. DWC2_CMPL_STOP
156866. DWC2_CONTROL_DATA
156867. DWC2_CONTROL_SETUP
156868. DWC2_CONTROL_STATUS
156869. DWC2_CORE_REV_2_71a
156870. DWC2_CORE_REV_2_72a
156871. DWC2_CORE_REV_2_80a
156872. DWC2_CORE_REV_2_90a
156873. DWC2_CORE_REV_2_91a
156874. DWC2_CORE_REV_2_92a
156875. DWC2_CORE_REV_2_94a
156876. DWC2_CORE_REV_3_00a
156877. DWC2_CORE_REV_3_10a
156878. DWC2_CORE_REV_4_00a
156879. DWC2_CTRL_BUFF_SIZE
156880. DWC2_ELEMENTS_PER_LS_BITMAP
156881. DWC2_EP0_DATA_IN
156882. DWC2_EP0_DATA_OUT
156883. DWC2_EP0_SETUP
156884. DWC2_EP0_STATUS_IN
156885. DWC2_EP0_STATUS_OUT
156886. DWC2_FS_IOT_ID
156887. DWC2_FS_IOT_REV_1_00a
156888. DWC2_HCD_STATUS_BUF_SIZE
156889. DWC2_HCSPLT_XACTPOS_ALL
156890. DWC2_HCSPLT_XACTPOS_BEGIN
156891. DWC2_HCSPLT_XACTPOS_END
156892. DWC2_HCSPLT_XACTPOS_MID
156893. DWC2_HC_PID_DATA0
156894. DWC2_HC_PID_DATA1
156895. DWC2_HC_PID_DATA2
156896. DWC2_HC_PID_MDATA
156897. DWC2_HC_PID_SETUP
156898. DWC2_HC_XFER_ACK
156899. DWC2_HC_XFER_AHB_ERR
156900. DWC2_HC_XFER_BABBLE_ERR
156901. DWC2_HC_XFER_COMPLETE
156902. DWC2_HC_XFER_DATA_TOGGLE_ERR
156903. DWC2_HC_XFER_FRAME_OVERRUN
156904. DWC2_HC_XFER_NAK
156905. DWC2_HC_XFER_NO_HALT_STATUS
156906. DWC2_HC_XFER_NYET
156907. DWC2_HC_XFER_PERIODIC_INCOMPLETE
156908. DWC2_HC_XFER_STALL
156909. DWC2_HC_XFER_URB_COMPLETE
156910. DWC2_HC_XFER_URB_DEQUEUE
156911. DWC2_HC_XFER_XACT_ERR
156912. DWC2_HS_IOT_ID
156913. DWC2_HS_IOT_REV_1_00a
156914. DWC2_HS_PERIODIC_US_PER_UFRAME
156915. DWC2_HS_SCHEDULE_UFRAMES
156916. DWC2_HS_SCHEDULE_US
156917. DWC2_KMEM_UNALIGNED_BUF_SIZE
156918. DWC2_L0
156919. DWC2_L1
156920. DWC2_L2
156921. DWC2_L3
156922. DWC2_LS_PERIODIC_SLICES_PER_FRAME
156923. DWC2_LS_PERIODIC_US_PER_FRAME
156924. DWC2_LS_SCHEDULE_FRAMES
156925. DWC2_LS_SCHEDULE_SLICES
156926. DWC2_NAKS_BEFORE_DELAY
156927. DWC2_NUM_SUPPLIES
156928. DWC2_OTG_ID
156929. DWC2_PHY_TYPE_PARAM_FS
156930. DWC2_PHY_TYPE_PARAM_ULPI
156931. DWC2_PHY_TYPE_PARAM_UTMI
156932. DWC2_POWER_DOWN_PARAM_HIBERNATION
156933. DWC2_POWER_DOWN_PARAM_NONE
156934. DWC2_POWER_DOWN_PARAM_PARTIAL
156935. DWC2_RETRY_WAIT_DELAY
156936. DWC2_ROUND_US_TO_SLICE
156937. DWC2_SLICES_PER_UFRAME
156938. DWC2_SPEED_PARAM_FULL
156939. DWC2_SPEED_PARAM_HIGH
156940. DWC2_SPEED_PARAM_LOW
156941. DWC2_TRACE_SCHEDULER
156942. DWC2_TRACE_SCHEDULER_VB
156943. DWC2_TRANSACTION_ALL
156944. DWC2_TRANSACTION_NONE
156945. DWC2_TRANSACTION_NON_PERIODIC
156946. DWC2_TRANSACTION_PERIODIC
156947. DWC2_UNRESERVE_DELAY
156948. DWC2_USB_DMA_ALIGN
156949. DWC2_US_PER_SLICE
156950. DWC2_US_PER_UFRAME
156951. DWC31_GRXFIFOSIZ_RXFDEP
156952. DWC31_GRXTHRCFG_MAXRXBURSTSIZE
156953. DWC31_GRXTHRCFG_PKTCNTSEL
156954. DWC31_GRXTHRCFG_RXPKTCNT
156955. DWC31_GTXFIFOSIZ_TXFDEF
156956. DWC31_GTXFIFOSIZ_TXFRAMNUM
156957. DWC31_GTXTHRCFG_MAXTXBURSTSIZE
156958. DWC31_GTXTHRCFG_PKTCNTSEL
156959. DWC31_GTXTHRCFG_TXPKTCNT
156960. DWC31_MAXRXBURSTSIZE_PRD
156961. DWC31_MAXTXBURSTSIZE_PRD
156962. DWC31_RXTHRNUMPKTSEL_HS_PRD
156963. DWC31_RXTHRNUMPKTSEL_PRD
156964. DWC31_RXTHRNUMPKT_HS_PRD
156965. DWC31_RXTHRNUMPKT_PRD
156966. DWC31_TXTHRNUMPKTSEL_HS_PRD
156967. DWC31_TXTHRNUMPKTSEL_PRD
156968. DWC31_TXTHRNUMPKT_HS_PRD
156969. DWC31_TXTHRNUMPKT_PRD
156970. DWC31_VERSIONTYPE_EA01
156971. DWC31_VERSIONTYPE_EA02
156972. DWC31_VERSIONTYPE_EA03
156973. DWC31_VERSIONTYPE_EA04
156974. DWC31_VERSIONTYPE_EA05
156975. DWC31_VERSIONTYPE_EA06
156976. DWC3_ALIGN_FRAME
156977. DWC3_AUXEVENTQ
156978. DWC3_BOUNCE_SIZE
156979. DWC3_DALEPENA
156980. DWC3_DALEPENA_EP
156981. DWC3_DCFG
156982. DWC3_DCFG_DEVADDR
156983. DWC3_DCFG_DEVADDR_MASK
156984. DWC3_DCFG_FULLSPEED
156985. DWC3_DCFG_HIGHSPEED
156986. DWC3_DCFG_LOWSPEED
156987. DWC3_DCFG_LPM_CAP
156988. DWC3_DCFG_NUMP
156989. DWC3_DCFG_NUMP_MASK
156990. DWC3_DCFG_NUMP_SHIFT
156991. DWC3_DCFG_SPEED_MASK
156992. DWC3_DCFG_SUPERSPEED
156993. DWC3_DCFG_SUPERSPEED_PLUS
156994. DWC3_DCTL
156995. DWC3_DCTL_ACCEPTU1ENA
156996. DWC3_DCTL_ACCEPTU2ENA
156997. DWC3_DCTL_APPL1RES
156998. DWC3_DCTL_CRS
156999. DWC3_DCTL_CSFTRST
157000. DWC3_DCTL_CSS
157001. DWC3_DCTL_HIRD_THRES
157002. DWC3_DCTL_HIRD_THRES_MASK
157003. DWC3_DCTL_INITU1ENA
157004. DWC3_DCTL_INITU2ENA
157005. DWC3_DCTL_KEEP_CONNECT
157006. DWC3_DCTL_L1_HIBER_EN
157007. DWC3_DCTL_LSFTRST
157008. DWC3_DCTL_NYET_THRES
157009. DWC3_DCTL_RUN_STOP
157010. DWC3_DCTL_TRGTULST
157011. DWC3_DCTL_TRGTULST_MASK
157012. DWC3_DCTL_TRGTULST_RX_DET
157013. DWC3_DCTL_TRGTULST_SS_DIS
157014. DWC3_DCTL_TRGTULST_SS_INACT
157015. DWC3_DCTL_TRGTULST_U2
157016. DWC3_DCTL_TRGTULST_U3
157017. DWC3_DCTL_TSTCTRL_MASK
157018. DWC3_DCTL_ULSTCHNGREQ
157019. DWC3_DCTL_ULSTCHNGREQ_MASK
157020. DWC3_DCTL_ULSTCHNG_COMPLIANCE
157021. DWC3_DCTL_ULSTCHNG_LOOPBACK
157022. DWC3_DCTL_ULSTCHNG_NO_ACTION
157023. DWC3_DCTL_ULSTCHNG_RECOVERY
157024. DWC3_DCTL_ULSTCHNG_RX_DETECT
157025. DWC3_DCTL_ULSTCHNG_SS_DISABLED
157026. DWC3_DCTL_ULSTCHNG_SS_INACTIVE
157027. DWC3_DEFAULT_AUTOSUSPEND_DELAY
157028. DWC3_DEFAULT_U1_DEV_EXIT_LAT
157029. DWC3_DEFAULT_U2_DEV_EXIT_LAT
157030. DWC3_DEPCFG_ACTION_INIT
157031. DWC3_DEPCFG_ACTION_MODIFY
157032. DWC3_DEPCFG_ACTION_RESTORE
157033. DWC3_DEPCFG_BINTERVAL_M1
157034. DWC3_DEPCFG_BULK_BASED
157035. DWC3_DEPCFG_BURST_SIZE
157036. DWC3_DEPCFG_DATA_SEQ_NUM
157037. DWC3_DEPCFG_EP_NUMBER
157038. DWC3_DEPCFG_EP_TYPE
157039. DWC3_DEPCFG_FIFO_BASED
157040. DWC3_DEPCFG_FIFO_ERROR_EN
157041. DWC3_DEPCFG_FIFO_NUMBER
157042. DWC3_DEPCFG_IGN_SEQ_NUM
157043. DWC3_DEPCFG_INT_NUM
157044. DWC3_DEPCFG_MAX_PACKET_SIZE
157045. DWC3_DEPCFG_STREAM_CAPABLE
157046. DWC3_DEPCFG_STREAM_EVENT_EN
157047. DWC3_DEPCFG_XFER_COMPLETE_EN
157048. DWC3_DEPCFG_XFER_IN_PROGRESS_EN
157049. DWC3_DEPCFG_XFER_NOT_READY_EN
157050. DWC3_DEPCMD
157051. DWC3_DEPCMDPAR0
157052. DWC3_DEPCMDPAR1
157053. DWC3_DEPCMDPAR2
157054. DWC3_DEPCMD_CLEARPENDIN
157055. DWC3_DEPCMD_CLEARSTALL
157056. DWC3_DEPCMD_CMD
157057. DWC3_DEPCMD_CMDACT
157058. DWC3_DEPCMD_CMDIOC
157059. DWC3_DEPCMD_DEPSTARTCFG
157060. DWC3_DEPCMD_ENDTRANSFER
157061. DWC3_DEPCMD_GETEPSTATE
157062. DWC3_DEPCMD_GETSEQNUMBER
157063. DWC3_DEPCMD_GET_RSC_IDX
157064. DWC3_DEPCMD_HIPRI_FORCERM
157065. DWC3_DEPCMD_PARAM
157066. DWC3_DEPCMD_PARAM_SHIFT
157067. DWC3_DEPCMD_SETEPCONFIG
157068. DWC3_DEPCMD_SETSTALL
157069. DWC3_DEPCMD_SETTRANSFRESOURCE
157070. DWC3_DEPCMD_STARTTRANSFER
157071. DWC3_DEPCMD_STATUS
157072. DWC3_DEPCMD_TYPE_BULK
157073. DWC3_DEPCMD_TYPE_CONTROL
157074. DWC3_DEPCMD_TYPE_INTR
157075. DWC3_DEPCMD_TYPE_ISOC
157076. DWC3_DEPCMD_UPDATETRANSFER
157077. DWC3_DEPEVT_EPCMDCMPLT
157078. DWC3_DEPEVT_RXTXFIFOEVT
157079. DWC3_DEPEVT_STREAMEVT
157080. DWC3_DEPEVT_XFERCOMPLETE
157081. DWC3_DEPEVT_XFERINPROGRESS
157082. DWC3_DEPEVT_XFERNOTREADY
157083. DWC3_DEPXFERCFG_NUM_XFER_RES
157084. DWC3_DEP_BASE
157085. DWC3_DESCFETCHQ
157086. DWC3_DEVICE_EVENT_CMD_CMPL
157087. DWC3_DEVICE_EVENT_CONNECT_DONE
157088. DWC3_DEVICE_EVENT_DISCONNECT
157089. DWC3_DEVICE_EVENT_EOPF
157090. DWC3_DEVICE_EVENT_ERRATIC_ERROR
157091. DWC3_DEVICE_EVENT_HIBER_REQ
157092. DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
157093. DWC3_DEVICE_EVENT_OVERFLOW
157094. DWC3_DEVICE_EVENT_RESET
157095. DWC3_DEVICE_EVENT_SOF
157096. DWC3_DEVICE_EVENT_WAKEUP
157097. DWC3_DEVICE_REGS_END
157098. DWC3_DEVICE_REGS_START
157099. DWC3_DEVTEN
157100. DWC3_DEVTEN_CMDCMPLTEN
157101. DWC3_DEVTEN_CONNECTDONEEN
157102. DWC3_DEVTEN_DISCONNEVTEN
157103. DWC3_DEVTEN_EOPFEN
157104. DWC3_DEVTEN_ERRTICERREN
157105. DWC3_DEVTEN_EVNTOVERFLOWEN
157106. DWC3_DEVTEN_HIBERNATIONREQEVTEN
157107. DWC3_DEVTEN_SOFEN
157108. DWC3_DEVTEN_ULSTCNGEN
157109. DWC3_DEVTEN_USBRSTEN
157110. DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
157111. DWC3_DEVTEN_WKUPEVTEN
157112. DWC3_DEV_IMOD
157113. DWC3_DEV_IMOD_COUNT_MASK
157114. DWC3_DEV_IMOD_COUNT_SHIFT
157115. DWC3_DEV_IMOD_INTERVAL_MASK
157116. DWC3_DEV_IMOD_INTERVAL_SHIFT
157117. DWC3_DGCMD
157118. DWC3_DGCMDPAR
157119. DWC3_DGCMDPAR_FIFO_NUM
157120. DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT
157121. DWC3_DGCMDPAR_LOOPBACK_DIS
157122. DWC3_DGCMDPAR_LOOPBACK_ENA
157123. DWC3_DGCMDPAR_RX_FIFO
157124. DWC3_DGCMDPAR_TX_FIFO
157125. DWC3_DGCMD_ALL_FIFO_FLUSH
157126. DWC3_DGCMD_CMDACT
157127. DWC3_DGCMD_CMDIOC
157128. DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK
157129. DWC3_DGCMD_SELECTED_FIFO_FLUSH
157130. DWC3_DGCMD_SET_ENDPOINT_NRDY
157131. DWC3_DGCMD_SET_LMP
157132. DWC3_DGCMD_SET_PERIODIC_PAR
157133. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI
157134. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO
157135. DWC3_DGCMD_STATUS
157136. DWC3_DGCMD_XMIT_FUNCTION
157137. DWC3_DSTS
157138. DWC3_DSTS_CONNECTSPD
157139. DWC3_DSTS_COREIDLE
157140. DWC3_DSTS_DCNRD
157141. DWC3_DSTS_DEVCTRLHLT
157142. DWC3_DSTS_FULLSPEED
157143. DWC3_DSTS_HIGHSPEED
157144. DWC3_DSTS_LOWSPEED
157145. DWC3_DSTS_PWRUPREQ
157146. DWC3_DSTS_RSS
157147. DWC3_DSTS_RXFIFOEMPTY
157148. DWC3_DSTS_SOFFN
157149. DWC3_DSTS_SOFFN_MASK
157150. DWC3_DSTS_SSS
157151. DWC3_DSTS_SUPERSPEED
157152. DWC3_DSTS_SUPERSPEED_PLUS
157153. DWC3_DSTS_USBLNKST
157154. DWC3_DSTS_USBLNKST_MASK
157155. DWC3_ENDPOINTS_NUM
157156. DWC3_EP0_COMPLETE
157157. DWC3_EP0_DIR_IN
157158. DWC3_EP0_NRDY_DATA
157159. DWC3_EP0_NRDY_STATUS
157160. DWC3_EP0_SETUP_SIZE
157161. DWC3_EP0_UNKNOWN
157162. DWC3_EP_DELAY_START
157163. DWC3_EP_DIRECTION_RX
157164. DWC3_EP_DIRECTION_TX
157165. DWC3_EP_ENABLED
157166. DWC3_EP_END_TRANSFER_PENDING
157167. DWC3_EP_FLAG_STALLED
157168. DWC3_EP_FLAG_WEDGED
157169. DWC3_EP_PENDING_REQUEST
157170. DWC3_EP_STALL
157171. DWC3_EP_TRANSFER_STARTED
157172. DWC3_EP_WEDGE
157173. DWC3_EVENTQ
157174. DWC3_EVENT_BUFFERS_SIZE
157175. DWC3_EVENT_PENDING
157176. DWC3_EVENT_TYPE_CARKIT
157177. DWC3_EVENT_TYPE_DEV
157178. DWC3_EVENT_TYPE_I2C
157179. DWC3_EVENT_TYPE_MASK
157180. DWC3_EXYNOS_MAX_CLOCKS
157181. DWC3_GBUSERRADDR0
157182. DWC3_GBUSERRADDR1
157183. DWC3_GCTL
157184. DWC3_GCTL_CLK_BUS
157185. DWC3_GCTL_CLK_MASK
157186. DWC3_GCTL_CLK_PIPE
157187. DWC3_GCTL_CLK_PIPEHALF
157188. DWC3_GCTL_CORESOFTRESET
157189. DWC3_GCTL_DISSCRAMBLE
157190. DWC3_GCTL_DSBLCLKGTNG
157191. DWC3_GCTL_GBLHIBERNATIONEN
157192. DWC3_GCTL_PRTCAP
157193. DWC3_GCTL_PRTCAPDIR
157194. DWC3_GCTL_PRTCAP_DEVICE
157195. DWC3_GCTL_PRTCAP_HOST
157196. DWC3_GCTL_PRTCAP_OTG
157197. DWC3_GCTL_PWRDNSCALE
157198. DWC3_GCTL_RAMCLKSEL
157199. DWC3_GCTL_SCALEDOWN
157200. DWC3_GCTL_SCALEDOWN_MASK
157201. DWC3_GCTL_SOFITPSYNC
157202. DWC3_GCTL_U2EXIT_LFPS
157203. DWC3_GCTL_U2RSTECN
157204. DWC3_GDBGBMU
157205. DWC3_GDBGEPINFO0
157206. DWC3_GDBGEPINFO1
157207. DWC3_GDBGFIFOSPACE
157208. DWC3_GDBGFIFOSPACE_NUM
157209. DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE
157210. DWC3_GDBGFIFOSPACE_TYPE
157211. DWC3_GDBGLSP
157212. DWC3_GDBGLSPMUX
157213. DWC3_GDBGLSPMUX_DEVSELECT
157214. DWC3_GDBGLSPMUX_ENDBC
157215. DWC3_GDBGLSPMUX_EPSELECT
157216. DWC3_GDBGLSPMUX_HOSTSELECT
157217. DWC3_GDBGLTSSM
157218. DWC3_GEVNTADRHI
157219. DWC3_GEVNTADRLO
157220. DWC3_GEVNTCOUNT
157221. DWC3_GEVNTCOUNT_EHB
157222. DWC3_GEVNTCOUNT_MASK
157223. DWC3_GEVNTSIZ
157224. DWC3_GEVNTSIZ_INTMASK
157225. DWC3_GEVNTSIZ_SIZE
157226. DWC3_GEVTEN
157227. DWC3_GFLADJ
157228. DWC3_GFLADJ_30MHZ_MASK
157229. DWC3_GFLADJ_30MHZ_SDBND_SEL
157230. DWC3_GGPIO
157231. DWC3_GHWPARAMS0
157232. DWC3_GHWPARAMS0_AWIDTH
157233. DWC3_GHWPARAMS0_MBUS_TYPE
157234. DWC3_GHWPARAMS0_MDWIDTH
157235. DWC3_GHWPARAMS0_MODE
157236. DWC3_GHWPARAMS0_MODE_DRD
157237. DWC3_GHWPARAMS0_MODE_GADGET
157238. DWC3_GHWPARAMS0_MODE_HOST
157239. DWC3_GHWPARAMS0_SBUS_TYPE
157240. DWC3_GHWPARAMS0_SDWIDTH
157241. DWC3_GHWPARAMS1
157242. DWC3_GHWPARAMS1_ENDBC
157243. DWC3_GHWPARAMS1_EN_PWROPT
157244. DWC3_GHWPARAMS1_EN_PWROPT_CLK
157245. DWC3_GHWPARAMS1_EN_PWROPT_HIB
157246. DWC3_GHWPARAMS1_EN_PWROPT_NO
157247. DWC3_GHWPARAMS1_PWROPT
157248. DWC3_GHWPARAMS1_PWROPT_MASK
157249. DWC3_GHWPARAMS2
157250. DWC3_GHWPARAMS3
157251. DWC3_GHWPARAMS3_FSPHY_IFC
157252. DWC3_GHWPARAMS3_FSPHY_IFC_DIS
157253. DWC3_GHWPARAMS3_FSPHY_IFC_ENA
157254. DWC3_GHWPARAMS3_HSPHY_IFC
157255. DWC3_GHWPARAMS3_HSPHY_IFC_DIS
157256. DWC3_GHWPARAMS3_HSPHY_IFC_ULPI
157257. DWC3_GHWPARAMS3_HSPHY_IFC_UTMI
157258. DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI
157259. DWC3_GHWPARAMS3_SSPHY_IFC
157260. DWC3_GHWPARAMS3_SSPHY_IFC_DIS
157261. DWC3_GHWPARAMS3_SSPHY_IFC_GEN1
157262. DWC3_GHWPARAMS3_SSPHY_IFC_GEN2
157263. DWC3_GHWPARAMS4
157264. DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS
157265. DWC3_GHWPARAMS5
157266. DWC3_GHWPARAMS6
157267. DWC3_GHWPARAMS6_ADPSUPPORT
157268. DWC3_GHWPARAMS6_BCSUPPORT
157269. DWC3_GHWPARAMS6_EN_FPGA
157270. DWC3_GHWPARAMS6_HNPSUPPORT
157271. DWC3_GHWPARAMS6_OTG3SUPPORT
157272. DWC3_GHWPARAMS6_SRPSUPPORT
157273. DWC3_GHWPARAMS7
157274. DWC3_GHWPARAMS7_RAM1_DEPTH
157275. DWC3_GHWPARAMS7_RAM2_DEPTH
157276. DWC3_GHWPARAMS8
157277. DWC3_GLOBALS_REGS_END
157278. DWC3_GLOBALS_REGS_START
157279. DWC3_GPRTBIMAP0
157280. DWC3_GPRTBIMAP1
157281. DWC3_GPRTBIMAP_FS0
157282. DWC3_GPRTBIMAP_FS1
157283. DWC3_GPRTBIMAP_HS0
157284. DWC3_GPRTBIMAP_HS1
157285. DWC3_GRXFIFOSIZ
157286. DWC3_GRXFIFOSIZ_RXFDEP
157287. DWC3_GRXTHRCFG
157288. DWC3_GRXTHRCFG_MAXRXBURSTSIZE
157289. DWC3_GRXTHRCFG_PKTCNTSEL
157290. DWC3_GRXTHRCFG_RXPKTCNT
157291. DWC3_GSBUSCFG0
157292. DWC3_GSBUSCFG0_INCR128BRSTENA
157293. DWC3_GSBUSCFG0_INCR16BRSTENA
157294. DWC3_GSBUSCFG0_INCR256BRSTENA
157295. DWC3_GSBUSCFG0_INCR32BRSTENA
157296. DWC3_GSBUSCFG0_INCR4BRSTENA
157297. DWC3_GSBUSCFG0_INCR64BRSTENA
157298. DWC3_GSBUSCFG0_INCR8BRSTENA
157299. DWC3_GSBUSCFG0_INCRBRSTENA
157300. DWC3_GSBUSCFG0_INCRBRST_MASK
157301. DWC3_GSBUSCFG1
157302. DWC3_GSNPSID
157303. DWC3_GSNPSID_MASK
157304. DWC3_GSNPSREV_MASK
157305. DWC3_GSTS
157306. DWC3_GSTS_ADP_IP
157307. DWC3_GSTS_BC_IP
157308. DWC3_GSTS_BUS_ERR_ADDR_VLD
157309. DWC3_GSTS_CSR_TIMEOUT
157310. DWC3_GSTS_CURMOD
157311. DWC3_GSTS_CURMOD_DEVICE
157312. DWC3_GSTS_CURMOD_HOST
157313. DWC3_GSTS_DEVICE_IP
157314. DWC3_GSTS_HOST_IP
157315. DWC3_GSTS_OTG_IP
157316. DWC3_GTXFIFOSIZ
157317. DWC3_GTXFIFOSIZ_TXFDEF
157318. DWC3_GTXFIFOSIZ_TXFSTADDR
157319. DWC3_GTXTHRCFG
157320. DWC3_GUCTL
157321. DWC3_GUCTL1
157322. DWC3_GUCTL1_DEV_L1_EXIT_BY_HW
157323. DWC3_GUCTL1_PARKMODE_DISABLE_SS
157324. DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS
157325. DWC3_GUCTL2
157326. DWC3_GUCTL2_RST_ACTBITLATER
157327. DWC3_GUCTL_HSTINAUTORETRY
157328. DWC3_GUID
157329. DWC3_GUSB2I2CCTL
157330. DWC3_GUSB2PHYACC
157331. DWC3_GUSB2PHYACC_ADDR
157332. DWC3_GUSB2PHYACC_BUSY
157333. DWC3_GUSB2PHYACC_DATA
157334. DWC3_GUSB2PHYACC_EXTEND_ADDR
157335. DWC3_GUSB2PHYACC_NEWREGREQ
157336. DWC3_GUSB2PHYACC_WRITE
157337. DWC3_GUSB2PHYCFG
157338. DWC3_GUSB2PHYCFG_ENBLSLPM
157339. DWC3_GUSB2PHYCFG_PHYIF
157340. DWC3_GUSB2PHYCFG_PHYIF_MASK
157341. DWC3_GUSB2PHYCFG_PHYSOFTRST
157342. DWC3_GUSB2PHYCFG_SUSPHY
157343. DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS
157344. DWC3_GUSB2PHYCFG_ULPI_UTMI
157345. DWC3_GUSB2PHYCFG_USBTRDTIM
157346. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK
157347. DWC3_GUSB3PIPECTL
157348. DWC3_GUSB3PIPECTL_DEP1P2P3
157349. DWC3_GUSB3PIPECTL_DEP1P2P3_EN
157350. DWC3_GUSB3PIPECTL_DEP1P2P3_MASK
157351. DWC3_GUSB3PIPECTL_DEPOCHANGE
157352. DWC3_GUSB3PIPECTL_DISRXDETINP3
157353. DWC3_GUSB3PIPECTL_LFPSFILT
157354. DWC3_GUSB3PIPECTL_PHYSOFTRST
157355. DWC3_GUSB3PIPECTL_REQP1P2P3
157356. DWC3_GUSB3PIPECTL_RX_DETOPOLL
157357. DWC3_GUSB3PIPECTL_SUSPHY
157358. DWC3_GUSB3PIPECTL_TX_DEEPH
157359. DWC3_GUSB3PIPECTL_TX_DEEPH_MASK
157360. DWC3_GUSB3PIPECTL_U2SSINP3OK
157361. DWC3_GUSB3PIPECTL_UX_EXIT_PX
157362. DWC3_HAS_OTG
157363. DWC3_HAS_PERIPHERAL
157364. DWC3_HAS_XHCI
157365. DWC3_ISOC_MAX_RETRIES
157366. DWC3_LINK_STATE_CMPLY
157367. DWC3_LINK_STATE_HRESET
157368. DWC3_LINK_STATE_LPBK
157369. DWC3_LINK_STATE_MASK
157370. DWC3_LINK_STATE_POLL
157371. DWC3_LINK_STATE_RECOV
157372. DWC3_LINK_STATE_RESET
157373. DWC3_LINK_STATE_RESUME
157374. DWC3_LINK_STATE_RX_DET
157375. DWC3_LINK_STATE_SS_DIS
157376. DWC3_LINK_STATE_SS_INACT
157377. DWC3_LINK_STATE_U0
157378. DWC3_LINK_STATE_U1
157379. DWC3_LINK_STATE_U2
157380. DWC3_LINK_STATE_U3
157381. DWC3_LSP_MUX_UNSELECTED
157382. DWC3_MAX_HIBER_SCRATCHBUFS
157383. DWC3_MDWIDTH
157384. DWC3_MODE
157385. DWC3_MSG_MAX
157386. DWC3_NUM_EPS
157387. DWC3_NUM_EPS_MASK
157388. DWC3_NUM_INT
157389. DWC3_NUM_IN_EPS
157390. DWC3_NUM_IN_EPS_MASK
157391. DWC3_OCFG
157392. DWC3_OCFG_DISPWRCUTTOFF
157393. DWC3_OCFG_HIBDISMASK
157394. DWC3_OCFG_HNPCAP
157395. DWC3_OCFG_OTGVERSION
157396. DWC3_OCFG_SFTRSTMASK
157397. DWC3_OCFG_SRPCAP
157398. DWC3_OCTL
157399. DWC3_OCTL_DEVSETHNPEN
157400. DWC3_OCTL_HNPREQ
157401. DWC3_OCTL_HSTSETHNPEN
157402. DWC3_OCTL_OTG3GOERR
157403. DWC3_OCTL_PERIMODE
157404. DWC3_OCTL_PRTPWRCTL
157405. DWC3_OCTL_SESREQ
157406. DWC3_OCTL_TERMSELIDPULSE
157407. DWC3_OEVT
157408. DWC3_OEVTEN
157409. DWC3_OEVTEN_ADEVBHOSTENDEN
157410. DWC3_OEVTEN_ADEVHNPCHNGEN
157411. DWC3_OEVTEN_ADEVHOSTEN
157412. DWC3_OEVTEN_ADEVIDLEEN
157413. DWC3_OEVTEN_ADEVSESSENDDETEN
157414. DWC3_OEVTEN_ADEVSRPDETEN
157415. DWC3_OEVTEN_BDEVBHOSTENDEN
157416. DWC3_OEVTEN_BDEVHNPCHNGEN
157417. DWC3_OEVTEN_BDEVSESSVLDDETEN
157418. DWC3_OEVTEN_BDEVVBUSCHNGEN
157419. DWC3_OEVTEN_CONIDSTSCHNGEN
157420. DWC3_OEVTEN_DEVRUNSTPSETEN
157421. DWC3_OEVTEN_HIBENTRYEN
157422. DWC3_OEVTEN_HRRCONFNOTIFEN
157423. DWC3_OEVTEN_HRRINITNOTIFEN
157424. DWC3_OEVTEN_XHCIRUNSTPSETEN
157425. DWC3_OEVT_ADEVBHOSTEND
157426. DWC3_OEVT_ADEVHNPCHNG
157427. DWC3_OEVT_ADEVHOST
157428. DWC3_OEVT_ADEVIDLE
157429. DWC3_OEVT_ADEVSESSENDDET
157430. DWC3_OEVT_ADEVSRPDET
157431. DWC3_OEVT_BDEVBHOSTEND
157432. DWC3_OEVT_BDEVHNPCHNG
157433. DWC3_OEVT_BDEVSESSVLDDET
157434. DWC3_OEVT_BDEVVBUSCHNG
157435. DWC3_OEVT_BSESSVLD
157436. DWC3_OEVT_CONIDSTSCHNG
157437. DWC3_OEVT_DEVICEMODE
157438. DWC3_OEVT_DEVRUNSTPSET
157439. DWC3_OEVT_ERROR
157440. DWC3_OEVT_HIBENTRY
157441. DWC3_OEVT_HRRCONFNOTIF
157442. DWC3_OEVT_HRRINITNOTIF
157443. DWC3_OEVT_HSTNEGSTS
157444. DWC3_OEVT_SESREQSTS
157445. DWC3_OEVT_XHCIRUNSTPSET
157446. DWC3_OMAP_UTMI_MODE_HW
157447. DWC3_OMAP_UTMI_MODE_SW
157448. DWC3_OMAP_UTMI_MODE_UNKNOWN
157449. DWC3_OSTS
157450. DWC3_OSTS_BSESVLD
157451. DWC3_OSTS_CONIDSTS
157452. DWC3_OSTS_DEVRUNSTP
157453. DWC3_OSTS_PERIPHERALSTATE
157454. DWC3_OSTS_VBUSVLD
157455. DWC3_OSTS_XHCIPRTPOWER
157456. DWC3_OSTS_XHCIRUNSTP
157457. DWC3_OTG_ALL_EVENTS
157458. DWC3_OTG_REGS_END
157459. DWC3_OTG_REGS_START
157460. DWC3_OTG_ROLE_DEVICE
157461. DWC3_OTG_ROLE_HOST
157462. DWC3_OTG_ROLE_IDLE
157463. DWC3_PHY_UNKNOWN
157464. DWC3_PHY_USB2
157465. DWC3_PHY_USB3
157466. DWC3_PSTATQ
157467. DWC3_PULL_UP_TIMEOUT
157468. DWC3_RAM1_DEPTH
157469. DWC3_REQUEST_STATUS_CANCELLED
157470. DWC3_REQUEST_STATUS_COMPLETED
157471. DWC3_REQUEST_STATUS_QUEUED
157472. DWC3_REQUEST_STATUS_STARTED
157473. DWC3_REQUEST_STATUS_UNKNOWN
157474. DWC3_REVISION_173A
157475. DWC3_REVISION_175A
157476. DWC3_REVISION_180A
157477. DWC3_REVISION_183A
157478. DWC3_REVISION_185A
157479. DWC3_REVISION_187A
157480. DWC3_REVISION_188A
157481. DWC3_REVISION_190A
157482. DWC3_REVISION_194A
157483. DWC3_REVISION_200A
157484. DWC3_REVISION_202A
157485. DWC3_REVISION_210A
157486. DWC3_REVISION_220A
157487. DWC3_REVISION_230A
157488. DWC3_REVISION_240A
157489. DWC3_REVISION_250A
157490. DWC3_REVISION_260A
157491. DWC3_REVISION_270A
157492. DWC3_REVISION_280A
157493. DWC3_REVISION_290A
157494. DWC3_REVISION_300A
157495. DWC3_REVISION_310A
157496. DWC3_REVISION_330A
157497. DWC3_REVISION_IS_DWC31
157498. DWC3_RXFIFO
157499. DWC3_RXINFOQ
157500. DWC3_RXREQQ
157501. DWC3_SCRATCHBUF_SIZE
157502. DWC3_TRBCTL_CONTROL_DATA
157503. DWC3_TRBCTL_CONTROL_SETUP
157504. DWC3_TRBCTL_CONTROL_STATUS2
157505. DWC3_TRBCTL_CONTROL_STATUS3
157506. DWC3_TRBCTL_ISOCHRONOUS
157507. DWC3_TRBCTL_ISOCHRONOUS_FIRST
157508. DWC3_TRBCTL_LINK_TRB
157509. DWC3_TRBCTL_NORMAL
157510. DWC3_TRBCTL_TYPE
157511. DWC3_TRBSTS_MISSED_ISOC
157512. DWC3_TRBSTS_OK
157513. DWC3_TRBSTS_SETUP_PENDING
157514. DWC3_TRB_CTRL_CHN
157515. DWC3_TRB_CTRL_CSP
157516. DWC3_TRB_CTRL_GET_SID_SOFN
157517. DWC3_TRB_CTRL_HWO
157518. DWC3_TRB_CTRL_IOC
157519. DWC3_TRB_CTRL_ISP_IMI
157520. DWC3_TRB_CTRL_LST
157521. DWC3_TRB_CTRL_SID_SOFN
157522. DWC3_TRB_CTRL_TRBCTL
157523. DWC3_TRB_NUM
157524. DWC3_TRB_SIZE_LENGTH
157525. DWC3_TRB_SIZE_MASK
157526. DWC3_TRB_SIZE_PCM1
157527. DWC3_TRB_SIZE_TRBSTS
157528. DWC3_TRB_STS_XFER_IN_PROG
157529. DWC3_TXFIFO
157530. DWC3_TXREQQ
157531. DWC3_ULPI_ADDR
157532. DWC3_USB31_REVISION_110A
157533. DWC3_USB31_REVISION_120A
157534. DWC3_USB31_REVISION_160A
157535. DWC3_USB31_REVISION_170A
157536. DWC3_USB31_REVISION_180A
157537. DWC3_USB31_REVISION_190A
157538. DWC3_VER_NUMBER
157539. DWC3_VER_TYPE
157540. DWC3_XHCI_REGS_END
157541. DWC3_XHCI_REGS_START
157542. DWC3_XHCI_RESOURCES_NUM
157543. DWC_CFGH_DST_PER
157544. DWC_CFGH_DS_UPD_EN
157545. DWC_CFGH_FCMODE
157546. DWC_CFGH_FIFO_MODE
157547. DWC_CFGH_PROTCTL
157548. DWC_CFGH_PROTCTL_BUFFER
157549. DWC_CFGH_PROTCTL_CACHE
157550. DWC_CFGH_PROTCTL_DATA
157551. DWC_CFGH_PROTCTL_PRIV
157552. DWC_CFGH_SRC_PER
157553. DWC_CFGH_SS_UPD_EN
157554. DWC_CFGL_CH_PRIOR
157555. DWC_CFGL_CH_PRIOR_MASK
157556. DWC_CFGL_CH_SUSP
157557. DWC_CFGL_FIFO_EMPTY
157558. DWC_CFGL_HS_DST
157559. DWC_CFGL_HS_DST_POL
157560. DWC_CFGL_HS_SRC
157561. DWC_CFGL_HS_SRC_POL
157562. DWC_CFGL_LOCK_BUS
157563. DWC_CFGL_LOCK_BUS_BLOCK
157564. DWC_CFGL_LOCK_BUS_XACT
157565. DWC_CFGL_LOCK_BUS_XFER
157566. DWC_CFGL_LOCK_CH
157567. DWC_CFGL_LOCK_CH_BLOCK
157568. DWC_CFGL_LOCK_CH_XACT
157569. DWC_CFGL_LOCK_CH_XFER
157570. DWC_CFGL_MAX_BURST
157571. DWC_CFGL_RELOAD_DAR
157572. DWC_CFGL_RELOAD_SAR
157573. DWC_CTLH_BLOCK_TS
157574. DWC_CTLH_BLOCK_TS_MASK
157575. DWC_CTLH_DONE
157576. DWC_CTLL_DMS
157577. DWC_CTLL_DST_DEC
157578. DWC_CTLL_DST_FIX
157579. DWC_CTLL_DST_INC
157580. DWC_CTLL_DST_MSIZE
157581. DWC_CTLL_DST_WIDTH
157582. DWC_CTLL_D_SCAT_EN
157583. DWC_CTLL_FC
157584. DWC_CTLL_FC_M2M
157585. DWC_CTLL_FC_M2P
157586. DWC_CTLL_FC_P2M
157587. DWC_CTLL_FC_P2P
157588. DWC_CTLL_INT_EN
157589. DWC_CTLL_LLP_D_EN
157590. DWC_CTLL_LLP_S_EN
157591. DWC_CTLL_SMS
157592. DWC_CTLL_SRC_DEC
157593. DWC_CTLL_SRC_FIX
157594. DWC_CTLL_SRC_INC
157595. DWC_CTLL_SRC_MSIZE
157596. DWC_CTLL_SRC_WIDTH
157597. DWC_CTLL_S_GATH_EN
157598. DWC_DSR_DSC
157599. DWC_DSR_DSI
157600. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
157601. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
157602. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
157603. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
157604. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
157605. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
157606. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
157607. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
157608. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
157609. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
157610. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK
157611. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT
157612. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
157613. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
157614. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
157615. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
157616. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
157617. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
157618. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
157619. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
157620. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
157621. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
157622. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
157623. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
157624. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
157625. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
157626. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
157627. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
157628. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
157629. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
157630. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
157631. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
157632. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
157633. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
157634. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
157635. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
157636. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
157637. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
157638. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
157639. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
157640. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
157641. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
157642. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK
157643. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
157644. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK
157645. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
157646. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK
157647. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
157648. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
157649. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
157650. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
157651. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
157652. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
157653. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
157654. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
157655. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
157656. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
157657. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
157658. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
157659. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
157660. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
157661. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
157662. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
157663. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
157664. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
157665. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
157666. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
157667. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
157668. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
157669. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
157670. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
157671. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
157672. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
157673. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
157674. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
157675. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
157676. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
157677. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
157678. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
157679. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
157680. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
157681. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
157682. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
157683. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
157684. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
157685. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
157686. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
157687. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
157688. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK
157689. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
157690. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK
157691. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
157692. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
157693. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
157694. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
157695. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
157696. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
157697. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
157698. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
157699. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
157700. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK
157701. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
157702. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
157703. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
157704. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
157705. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
157706. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
157707. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
157708. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
157709. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
157710. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
157711. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
157712. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__NC32_MASK
157713. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT
157714. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
157715. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
157716. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
157717. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
157718. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
157719. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
157720. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
157721. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
157722. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
157723. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
157724. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK
157725. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
157726. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
157727. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
157728. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
157729. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
157730. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
157731. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
157732. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
157733. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
157734. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
157735. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
157736. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK
157737. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
157738. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
157739. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
157740. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
157741. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
157742. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
157743. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
157744. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
157745. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
157746. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK
157747. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT
157748. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
157749. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
157750. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
157751. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
157752. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
157753. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
157754. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
157755. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
157756. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
157757. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
157758. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
157759. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
157760. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
157761. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
157762. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
157763. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
157764. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
157765. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
157766. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
157767. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
157768. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__NC20_MASK
157769. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__NC20__SHIFT
157770. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK
157771. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT
157772. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
157773. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
157774. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
157775. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
157776. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
157777. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
157778. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK
157779. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
157780. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK
157781. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
157782. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
157783. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
157784. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK
157785. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
157786. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK
157787. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
157788. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK
157789. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT
157790. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
157791. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
157792. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK
157793. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT
157794. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK
157795. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT
157796. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
157797. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
157798. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK
157799. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT
157800. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_gd_MASK
157801. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_gd__SHIFT
157802. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccm_MASK
157803. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT
157804. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccp_MASK
157805. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT
157806. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vptx_MASK
157807. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT
157808. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg0_MASK
157809. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT
157810. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg1_MASK
157811. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT
157812. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK
157813. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT
157814. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__override_regref_0_MASK
157815. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT
157816. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK
157817. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT
157818. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_nbias_MASK
157819. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT
157820. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_pbias_MASK
157821. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT
157822. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK
157823. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT
157824. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfm_MASK
157825. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT
157826. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfp_MASK
157827. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT
157828. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsm_MASK
157829. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT
157830. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsp_MASK
157831. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT
157832. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_vcm_MASK
157833. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT
157834. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
157835. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
157836. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK
157837. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
157838. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
157839. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
157840. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
157841. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
157842. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
157843. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
157844. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
157845. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
157846. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK
157847. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT
157848. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK
157849. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
157850. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__nc_MASK
157851. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__nc__SHIFT
157852. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_nmos_MASK
157853. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_nmos__SHIFT
157854. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_pmos_MASK
157855. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_pmos__SHIFT
157856. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__override_rxdetref_MASK
157857. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT
157858. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
157859. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
157860. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
157861. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
157862. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
157863. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
157864. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
157865. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
157866. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK
157867. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
157868. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
157869. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
157870. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
157871. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
157872. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
157873. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
157874. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
157875. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
157876. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
157877. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
157878. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
157879. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
157880. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
157881. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
157882. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
157883. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
157884. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
157885. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
157886. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
157887. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
157888. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
157889. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
157890. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
157891. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
157892. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
157893. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
157894. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
157895. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
157896. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
157897. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
157898. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK
157899. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
157900. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK
157901. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
157902. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
157903. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
157904. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK
157905. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
157906. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
157907. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
157908. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
157909. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
157910. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK
157911. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
157912. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
157913. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
157914. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
157915. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
157916. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
157917. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
157918. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
157919. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
157920. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
157921. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
157922. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
157923. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
157924. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK
157925. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
157926. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK
157927. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT
157928. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_MASK
157929. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT
157930. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK
157931. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
157932. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
157933. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
157934. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK
157935. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
157936. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK
157937. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
157938. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK
157939. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
157940. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK
157941. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT
157942. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
157943. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
157944. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
157945. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
157946. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
157947. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
157948. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
157949. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
157950. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
157951. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
157952. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
157953. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
157954. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
157955. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
157956. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
157957. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
157958. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
157959. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
157960. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
157961. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
157962. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
157963. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
157964. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
157965. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
157966. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
157967. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
157968. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
157969. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
157970. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
157971. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
157972. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
157973. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
157974. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
157975. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
157976. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
157977. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
157978. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
157979. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
157980. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
157981. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
157982. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
157983. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
157984. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
157985. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
157986. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
157987. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
157988. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
157989. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
157990. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
157991. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
157992. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
157993. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
157994. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
157995. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
157996. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
157997. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
157998. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
157999. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
158000. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
158001. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
158002. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
158003. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
158004. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
158005. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
158006. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
158007. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
158008. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
158009. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
158010. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
158011. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
158012. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
158013. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
158014. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
158015. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
158016. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
158017. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
158018. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
158019. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
158020. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
158021. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
158022. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
158023. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
158024. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
158025. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
158026. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
158027. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
158028. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
158029. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
158030. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
158031. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
158032. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
158033. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
158034. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
158035. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
158036. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
158037. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
158038. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
158039. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
158040. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
158041. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
158042. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
158043. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
158044. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
158045. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
158046. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
158047. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
158048. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
158049. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
158050. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
158051. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
158052. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
158053. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
158054. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
158055. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
158056. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
158057. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
158058. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
158059. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
158060. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
158061. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
158062. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
158063. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
158064. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
158065. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
158066. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
158067. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
158068. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
158069. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
158070. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
158071. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
158072. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
158073. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
158074. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
158075. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
158076. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
158077. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
158078. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
158079. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
158080. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
158081. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
158082. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
158083. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
158084. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
158085. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
158086. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
158087. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
158088. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
158089. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
158090. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
158091. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
158092. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
158093. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
158094. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
158095. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
158096. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
158097. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
158098. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
158099. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
158100. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
158101. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
158102. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
158103. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
158104. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
158105. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
158106. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
158107. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
158108. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
158109. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
158110. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
158111. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
158112. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
158113. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
158114. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
158115. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
158116. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
158117. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
158118. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
158119. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
158120. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
158121. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
158122. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
158123. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
158124. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
158125. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
158126. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
158127. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
158128. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
158129. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
158130. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
158131. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
158132. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
158133. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
158134. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
158135. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
158136. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
158137. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
158138. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
158139. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
158140. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
158141. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
158142. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
158143. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
158144. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
158145. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
158146. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
158147. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
158148. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
158149. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
158150. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
158151. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
158152. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
158153. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
158154. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
158155. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
158156. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
158157. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
158158. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
158159. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
158160. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
158161. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
158162. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
158163. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
158164. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
158165. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
158166. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
158167. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
158168. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
158169. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
158170. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
158171. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
158172. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
158173. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
158174. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
158175. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
158176. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
158177. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
158178. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
158179. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
158180. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
158181. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
158182. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
158183. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
158184. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
158185. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
158186. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK
158187. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
158188. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
158189. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
158190. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
158191. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
158192. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
158193. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
158194. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
158195. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
158196. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
158197. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
158198. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
158199. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
158200. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
158201. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
158202. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
158203. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
158204. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
158205. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
158206. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
158207. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
158208. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
158209. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
158210. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
158211. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
158212. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
158213. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
158214. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
158215. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
158216. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
158217. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
158218. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
158219. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
158220. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
158221. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
158222. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
158223. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
158224. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
158225. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
158226. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
158227. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
158228. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
158229. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
158230. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
158231. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
158232. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
158233. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
158234. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
158235. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
158236. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
158237. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
158238. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
158239. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
158240. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
158241. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
158242. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
158243. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
158244. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
158245. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
158246. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
158247. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
158248. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
158249. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
158250. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
158251. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
158252. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
158253. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
158254. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
158255. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
158256. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
158257. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
158258. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
158259. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
158260. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
158261. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
158262. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
158263. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
158264. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
158265. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
158266. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
158267. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
158268. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
158269. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
158270. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
158271. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
158272. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
158273. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
158274. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
158275. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
158276. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
158277. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
158278. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
158279. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
158280. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
158281. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
158282. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
158283. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
158284. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
158285. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
158286. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
158287. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
158288. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
158289. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
158290. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
158291. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
158292. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
158293. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
158294. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
158295. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
158296. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
158297. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
158298. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
158299. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
158300. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
158301. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
158302. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
158303. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
158304. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
158305. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
158306. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
158307. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
158308. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
158309. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
158310. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
158311. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
158312. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
158313. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
158314. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
158315. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
158316. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
158317. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
158318. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
158319. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
158320. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
158321. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
158322. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
158323. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
158324. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
158325. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
158326. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
158327. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
158328. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
158329. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
158330. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
158331. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
158332. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
158333. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
158334. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
158335. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
158336. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
158337. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
158338. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
158339. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
158340. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
158341. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
158342. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
158343. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
158344. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
158345. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
158346. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
158347. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
158348. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
158349. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
158350. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
158351. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
158352. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
158353. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
158354. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
158355. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
158356. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
158357. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
158358. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
158359. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
158360. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
158361. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
158362. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
158363. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
158364. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
158365. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
158366. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
158367. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
158368. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
158369. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
158370. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
158371. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
158372. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
158373. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
158374. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
158375. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
158376. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
158377. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
158378. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
158379. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
158380. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
158381. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
158382. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
158383. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
158384. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
158385. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
158386. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
158387. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
158388. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
158389. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
158390. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
158391. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
158392. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
158393. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
158394. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
158395. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
158396. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
158397. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
158398. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
158399. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
158400. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
158401. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
158402. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
158403. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
158404. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
158405. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
158406. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
158407. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
158408. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
158409. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
158410. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
158411. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
158412. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
158413. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
158414. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
158415. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
158416. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
158417. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
158418. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
158419. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
158420. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
158421. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
158422. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
158423. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
158424. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
158425. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
158426. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
158427. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
158428. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
158429. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
158430. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
158431. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
158432. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
158433. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
158434. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
158435. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
158436. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
158437. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
158438. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
158439. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
158440. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
158441. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
158442. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
158443. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
158444. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
158445. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
158446. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
158447. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
158448. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
158449. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
158450. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
158451. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
158452. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
158453. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
158454. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
158455. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
158456. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
158457. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
158458. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
158459. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
158460. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
158461. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
158462. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
158463. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
158464. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
158465. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
158466. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
158467. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
158468. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
158469. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
158470. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
158471. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
158472. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
158473. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
158474. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
158475. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
158476. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
158477. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
158478. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
158479. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
158480. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
158481. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
158482. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
158483. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
158484. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
158485. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
158486. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
158487. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
158488. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
158489. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
158490. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
158491. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
158492. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
158493. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
158494. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
158495. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
158496. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
158497. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
158498. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
158499. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
158500. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
158501. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
158502. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
158503. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
158504. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
158505. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
158506. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
158507. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
158508. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
158509. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
158510. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
158511. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
158512. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
158513. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
158514. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
158515. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
158516. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
158517. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
158518. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
158519. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
158520. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
158521. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
158522. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
158523. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
158524. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
158525. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
158526. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
158527. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
158528. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
158529. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
158530. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
158531. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
158532. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
158533. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
158534. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
158535. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
158536. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
158537. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
158538. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
158539. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
158540. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
158541. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
158542. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
158543. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
158544. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
158545. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
158546. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
158547. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
158548. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
158549. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
158550. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
158551. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
158552. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
158553. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
158554. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
158555. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
158556. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
158557. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
158558. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
158559. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
158560. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
158561. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
158562. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
158563. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
158564. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
158565. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
158566. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
158567. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
158568. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
158569. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
158570. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
158571. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
158572. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
158573. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
158574. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
158575. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
158576. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
158577. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
158578. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
158579. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
158580. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
158581. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
158582. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
158583. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
158584. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
158585. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
158586. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
158587. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
158588. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
158589. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
158590. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
158591. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
158592. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
158593. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
158594. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
158595. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
158596. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
158597. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
158598. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
158599. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
158600. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
158601. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
158602. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
158603. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
158604. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
158605. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
158606. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
158607. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
158608. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
158609. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
158610. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
158611. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
158612. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
158613. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
158614. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
158615. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
158616. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
158617. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
158618. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
158619. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
158620. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
158621. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
158622. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
158623. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
158624. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
158625. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
158626. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
158627. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
158628. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
158629. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
158630. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
158631. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
158632. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
158633. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
158634. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
158635. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
158636. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
158637. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
158638. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
158639. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
158640. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
158641. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
158642. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
158643. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
158644. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
158645. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
158646. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
158647. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
158648. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
158649. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
158650. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
158651. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
158652. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
158653. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
158654. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
158655. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
158656. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
158657. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
158658. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
158659. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
158660. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
158661. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
158662. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
158663. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
158664. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
158665. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
158666. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
158667. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
158668. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
158669. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
158670. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
158671. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
158672. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
158673. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
158674. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
158675. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
158676. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
158677. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
158678. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
158679. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
158680. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
158681. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
158682. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
158683. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
158684. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
158685. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
158686. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
158687. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
158688. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
158689. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
158690. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
158691. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
158692. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
158693. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
158694. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
158695. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
158696. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
158697. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
158698. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
158699. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
158700. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
158701. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
158702. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
158703. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
158704. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
158705. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
158706. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
158707. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
158708. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
158709. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
158710. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
158711. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
158712. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
158713. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
158714. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
158715. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
158716. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
158717. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
158718. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
158719. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
158720. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
158721. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
158722. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
158723. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
158724. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
158725. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
158726. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
158727. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
158728. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
158729. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
158730. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
158731. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
158732. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
158733. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
158734. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
158735. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
158736. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
158737. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
158738. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
158739. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
158740. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
158741. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
158742. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK
158743. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT
158744. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__MODE_MASK
158745. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT
158746. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
158747. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
158748. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK
158749. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT
158750. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK
158751. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT
158752. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__OV14_MASK
158753. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT
158754. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
158755. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
158756. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
158757. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
158758. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
158759. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
158760. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
158761. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
158762. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
158763. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
158764. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
158765. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
158766. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
158767. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
158768. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
158769. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
158770. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
158771. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
158772. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
158773. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
158774. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
158775. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
158776. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
158777. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
158778. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
158779. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
158780. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
158781. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
158782. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
158783. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
158784. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
158785. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
158786. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
158787. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
158788. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
158789. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
158790. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
158791. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
158792. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
158793. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
158794. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
158795. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
158796. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
158797. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
158798. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
158799. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
158800. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
158801. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
158802. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
158803. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
158804. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
158805. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
158806. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
158807. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
158808. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
158809. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
158810. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
158811. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
158812. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
158813. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
158814. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
158815. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
158816. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
158817. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
158818. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
158819. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
158820. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
158821. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
158822. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
158823. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
158824. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
158825. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
158826. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
158827. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
158828. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
158829. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
158830. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
158831. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
158832. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
158833. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
158834. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
158835. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
158836. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
158837. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
158838. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
158839. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
158840. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
158841. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
158842. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
158843. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
158844. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
158845. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
158846. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
158847. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
158848. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
158849. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
158850. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
158851. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
158852. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
158853. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
158854. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
158855. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
158856. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
158857. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
158858. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
158859. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
158860. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
158861. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
158862. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
158863. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
158864. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
158865. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
158866. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
158867. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
158868. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
158869. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
158870. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
158871. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
158872. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
158873. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
158874. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
158875. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
158876. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
158877. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
158878. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
158879. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
158880. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
158881. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
158882. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
158883. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
158884. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
158885. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
158886. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
158887. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
158888. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
158889. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
158890. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
158891. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
158892. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
158893. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
158894. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
158895. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
158896. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
158897. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
158898. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
158899. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
158900. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
158901. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
158902. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
158903. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
158904. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
158905. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
158906. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
158907. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
158908. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
158909. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
158910. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
158911. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
158912. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
158913. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
158914. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
158915. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
158916. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
158917. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
158918. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
158919. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
158920. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
158921. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
158922. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
158923. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
158924. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
158925. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
158926. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
158927. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
158928. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
158929. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
158930. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
158931. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
158932. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
158933. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
158934. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
158935. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
158936. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
158937. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
158938. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
158939. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
158940. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
158941. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
158942. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
158943. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
158944. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
158945. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
158946. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
158947. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
158948. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
158949. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
158950. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
158951. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
158952. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
158953. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
158954. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
158955. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
158956. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
158957. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
158958. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
158959. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
158960. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
158961. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
158962. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
158963. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
158964. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
158965. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
158966. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
158967. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
158968. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
158969. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
158970. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
158971. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
158972. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
158973. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
158974. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
158975. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
158976. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
158977. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
158978. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
158979. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
158980. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
158981. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
158982. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
158983. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
158984. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
158985. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
158986. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
158987. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
158988. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
158989. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
158990. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
158991. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
158992. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
158993. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
158994. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
158995. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
158996. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
158997. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
158998. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
158999. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
159000. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
159001. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
159002. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
159003. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
159004. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
159005. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
159006. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
159007. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
159008. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
159009. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
159010. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
159011. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
159012. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
159013. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
159014. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
159015. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
159016. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
159017. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
159018. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
159019. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
159020. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
159021. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
159022. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
159023. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
159024. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
159025. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
159026. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
159027. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
159028. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
159029. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
159030. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
159031. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
159032. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
159033. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
159034. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
159035. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
159036. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
159037. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
159038. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
159039. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
159040. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
159041. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
159042. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
159043. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
159044. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
159045. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
159046. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
159047. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
159048. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
159049. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
159050. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
159051. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
159052. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
159053. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
159054. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
159055. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
159056. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
159057. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
159058. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
159059. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
159060. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
159061. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
159062. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
159063. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
159064. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
159065. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
159066. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
159067. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
159068. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
159069. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
159070. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
159071. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
159072. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
159073. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
159074. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
159075. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
159076. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
159077. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
159078. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
159079. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
159080. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
159081. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
159082. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
159083. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
159084. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
159085. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
159086. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
159087. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
159088. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
159089. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
159090. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
159091. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
159092. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
159093. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
159094. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
159095. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
159096. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK
159097. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT
159098. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK
159099. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT
159100. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
159101. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
159102. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
159103. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
159104. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
159105. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
159106. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
159107. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
159108. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
159109. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
159110. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
159111. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
159112. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
159113. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
159114. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
159115. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
159116. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
159117. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
159118. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
159119. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
159120. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
159121. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
159122. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
159123. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
159124. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
159125. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
159126. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
159127. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
159128. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
159129. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
159130. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
159131. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
159132. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
159133. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
159134. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
159135. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
159136. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
159137. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
159138. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
159139. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
159140. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
159141. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
159142. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
159143. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
159144. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
159145. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
159146. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
159147. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
159148. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
159149. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
159150. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
159151. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
159152. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
159153. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
159154. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
159155. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
159156. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
159157. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
159158. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
159159. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
159160. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
159161. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
159162. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
159163. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
159164. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
159165. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
159166. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
159167. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
159168. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
159169. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
159170. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
159171. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
159172. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
159173. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
159174. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
159175. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
159176. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
159177. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
159178. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
159179. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
159180. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
159181. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
159182. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
159183. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
159184. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
159185. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
159186. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
159187. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
159188. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
159189. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
159190. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
159191. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
159192. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
159193. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
159194. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
159195. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
159196. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
159197. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
159198. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
159199. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
159200. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
159201. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
159202. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
159203. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
159204. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
159205. DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
159206. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
159207. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
159208. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
159209. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
159210. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
159211. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
159212. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
159213. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
159214. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
159215. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
159216. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK
159217. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT
159218. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
159219. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
159220. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
159221. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
159222. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
159223. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
159224. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
159225. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
159226. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
159227. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
159228. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
159229. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
159230. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
159231. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
159232. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
159233. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
159234. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
159235. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
159236. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
159237. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
159238. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
159239. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
159240. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
159241. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
159242. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
159243. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
159244. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
159245. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
159246. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
159247. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
159248. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK
159249. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
159250. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK
159251. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
159252. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK
159253. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
159254. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
159255. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
159256. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
159257. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
159258. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
159259. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
159260. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
159261. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
159262. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
159263. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
159264. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
159265. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
159266. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
159267. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
159268. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
159269. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
159270. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
159271. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
159272. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
159273. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
159274. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
159275. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
159276. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
159277. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
159278. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
159279. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
159280. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
159281. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
159282. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
159283. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
159284. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
159285. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
159286. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
159287. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
159288. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
159289. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
159290. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
159291. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
159292. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
159293. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
159294. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK
159295. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
159296. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK
159297. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
159298. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
159299. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
159300. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
159301. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
159302. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
159303. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
159304. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
159305. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
159306. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK
159307. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
159308. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
159309. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
159310. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
159311. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
159312. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
159313. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
159314. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
159315. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
159316. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
159317. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
159318. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__NC32_MASK
159319. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT
159320. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
159321. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
159322. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
159323. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
159324. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
159325. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
159326. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
159327. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
159328. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
159329. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
159330. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK
159331. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
159332. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
159333. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
159334. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
159335. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
159336. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
159337. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
159338. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
159339. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
159340. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
159341. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
159342. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK
159343. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
159344. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
159345. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
159346. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
159347. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
159348. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
159349. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
159350. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
159351. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
159352. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK
159353. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT
159354. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
159355. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
159356. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
159357. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
159358. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
159359. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
159360. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
159361. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
159362. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
159363. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
159364. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
159365. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
159366. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
159367. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
159368. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
159369. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
159370. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
159371. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
159372. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
159373. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
159374. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__NC20_MASK
159375. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__NC20__SHIFT
159376. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK
159377. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT
159378. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
159379. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
159380. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
159381. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
159382. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
159383. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
159384. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK
159385. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
159386. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK
159387. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
159388. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
159389. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
159390. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK
159391. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
159392. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK
159393. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
159394. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK
159395. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT
159396. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
159397. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
159398. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK
159399. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT
159400. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK
159401. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT
159402. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
159403. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
159404. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK
159405. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT
159406. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_gd_MASK
159407. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_gd__SHIFT
159408. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccm_MASK
159409. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT
159410. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccp_MASK
159411. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT
159412. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vptx_MASK
159413. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT
159414. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg0_MASK
159415. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT
159416. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg1_MASK
159417. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT
159418. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK
159419. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT
159420. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__override_regref_0_MASK
159421. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT
159422. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK
159423. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT
159424. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_nbias_MASK
159425. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT
159426. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_pbias_MASK
159427. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT
159428. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK
159429. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT
159430. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfm_MASK
159431. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT
159432. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfp_MASK
159433. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT
159434. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsm_MASK
159435. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT
159436. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsp_MASK
159437. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT
159438. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_vcm_MASK
159439. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT
159440. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
159441. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
159442. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK
159443. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
159444. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
159445. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
159446. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
159447. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
159448. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
159449. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
159450. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
159451. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
159452. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK
159453. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT
159454. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK
159455. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
159456. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__nc_MASK
159457. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__nc__SHIFT
159458. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_nmos_MASK
159459. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_nmos__SHIFT
159460. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_pmos_MASK
159461. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_pmos__SHIFT
159462. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__override_rxdetref_MASK
159463. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT
159464. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
159465. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
159466. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
159467. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
159468. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
159469. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
159470. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
159471. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
159472. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK
159473. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
159474. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
159475. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
159476. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
159477. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
159478. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
159479. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
159480. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
159481. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
159482. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
159483. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
159484. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
159485. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
159486. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
159487. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
159488. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
159489. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
159490. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
159491. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
159492. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
159493. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
159494. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
159495. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
159496. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
159497. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
159498. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
159499. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
159500. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
159501. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
159502. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
159503. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
159504. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK
159505. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
159506. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK
159507. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
159508. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
159509. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
159510. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK
159511. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
159512. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
159513. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
159514. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
159515. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
159516. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK
159517. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
159518. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
159519. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
159520. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
159521. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
159522. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
159523. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
159524. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
159525. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
159526. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
159527. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
159528. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
159529. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
159530. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK
159531. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
159532. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK
159533. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT
159534. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_MASK
159535. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT
159536. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK
159537. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
159538. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
159539. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
159540. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK
159541. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
159542. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK
159543. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
159544. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK
159545. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
159546. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK
159547. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT
159548. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
159549. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
159550. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
159551. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
159552. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
159553. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
159554. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
159555. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
159556. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
159557. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
159558. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
159559. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
159560. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
159561. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
159562. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
159563. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
159564. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
159565. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
159566. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
159567. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
159568. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
159569. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
159570. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
159571. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
159572. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
159573. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
159574. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
159575. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
159576. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
159577. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
159578. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
159579. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
159580. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
159581. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
159582. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
159583. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
159584. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
159585. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
159586. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
159587. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
159588. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
159589. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
159590. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
159591. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
159592. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
159593. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
159594. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
159595. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
159596. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
159597. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
159598. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
159599. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
159600. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
159601. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
159602. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
159603. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
159604. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
159605. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
159606. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
159607. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
159608. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
159609. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
159610. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
159611. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
159612. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
159613. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
159614. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
159615. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
159616. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
159617. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
159618. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
159619. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
159620. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
159621. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
159622. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
159623. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
159624. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
159625. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
159626. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
159627. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
159628. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
159629. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
159630. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
159631. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
159632. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
159633. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
159634. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
159635. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
159636. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
159637. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
159638. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
159639. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
159640. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
159641. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
159642. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
159643. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
159644. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
159645. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
159646. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
159647. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
159648. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
159649. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
159650. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
159651. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
159652. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
159653. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
159654. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
159655. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
159656. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
159657. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
159658. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
159659. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
159660. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
159661. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
159662. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
159663. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
159664. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
159665. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
159666. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
159667. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
159668. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
159669. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
159670. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
159671. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
159672. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
159673. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
159674. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
159675. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
159676. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
159677. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
159678. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
159679. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
159680. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
159681. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
159682. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
159683. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
159684. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
159685. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
159686. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
159687. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
159688. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
159689. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
159690. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
159691. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
159692. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
159693. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
159694. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
159695. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
159696. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
159697. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
159698. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
159699. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
159700. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
159701. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
159702. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
159703. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
159704. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
159705. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
159706. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
159707. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
159708. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
159709. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
159710. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
159711. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
159712. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
159713. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
159714. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
159715. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
159716. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
159717. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
159718. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
159719. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
159720. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
159721. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
159722. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
159723. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
159724. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
159725. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
159726. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
159727. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
159728. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
159729. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
159730. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
159731. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
159732. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
159733. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
159734. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
159735. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
159736. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
159737. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
159738. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
159739. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
159740. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
159741. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
159742. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
159743. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
159744. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
159745. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
159746. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
159747. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
159748. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
159749. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
159750. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
159751. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
159752. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
159753. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
159754. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
159755. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
159756. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
159757. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
159758. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
159759. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
159760. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
159761. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
159762. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
159763. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
159764. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
159765. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
159766. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
159767. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
159768. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
159769. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
159770. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
159771. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
159772. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
159773. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
159774. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
159775. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
159776. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
159777. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
159778. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
159779. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
159780. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
159781. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
159782. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
159783. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
159784. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
159785. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
159786. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
159787. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
159788. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
159789. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
159790. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
159791. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
159792. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK
159793. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
159794. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
159795. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
159796. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
159797. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
159798. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
159799. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
159800. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
159801. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
159802. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
159803. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
159804. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
159805. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
159806. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
159807. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
159808. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
159809. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
159810. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
159811. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
159812. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
159813. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
159814. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
159815. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
159816. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
159817. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
159818. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
159819. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
159820. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
159821. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
159822. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
159823. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
159824. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
159825. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
159826. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
159827. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
159828. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
159829. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
159830. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
159831. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
159832. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
159833. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
159834. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
159835. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
159836. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
159837. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
159838. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
159839. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
159840. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
159841. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
159842. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
159843. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
159844. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
159845. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
159846. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
159847. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
159848. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
159849. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
159850. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
159851. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
159852. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
159853. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
159854. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
159855. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
159856. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
159857. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
159858. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
159859. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
159860. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
159861. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
159862. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
159863. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
159864. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
159865. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
159866. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
159867. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
159868. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
159869. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
159870. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
159871. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
159872. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
159873. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
159874. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
159875. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
159876. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
159877. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
159878. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
159879. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
159880. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
159881. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
159882. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
159883. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
159884. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
159885. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
159886. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
159887. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
159888. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
159889. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
159890. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
159891. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
159892. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
159893. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
159894. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
159895. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
159896. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
159897. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
159898. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
159899. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
159900. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
159901. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
159902. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
159903. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
159904. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
159905. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
159906. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
159907. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
159908. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
159909. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
159910. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
159911. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
159912. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
159913. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
159914. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
159915. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
159916. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
159917. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
159918. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
159919. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
159920. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
159921. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
159922. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
159923. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
159924. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
159925. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
159926. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
159927. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
159928. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
159929. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
159930. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
159931. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
159932. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
159933. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
159934. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
159935. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
159936. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
159937. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
159938. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
159939. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
159940. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
159941. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
159942. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
159943. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
159944. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
159945. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
159946. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
159947. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
159948. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
159949. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
159950. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
159951. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
159952. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
159953. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
159954. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
159955. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
159956. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
159957. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
159958. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
159959. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
159960. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
159961. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
159962. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
159963. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
159964. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
159965. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
159966. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
159967. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
159968. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
159969. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
159970. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
159971. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
159972. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
159973. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
159974. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
159975. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
159976. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
159977. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
159978. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
159979. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
159980. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
159981. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
159982. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
159983. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
159984. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
159985. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
159986. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
159987. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
159988. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
159989. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
159990. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
159991. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
159992. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
159993. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
159994. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
159995. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
159996. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
159997. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
159998. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
159999. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
160000. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
160001. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
160002. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
160003. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
160004. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
160005. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
160006. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
160007. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
160008. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
160009. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
160010. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
160011. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
160012. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
160013. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
160014. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
160015. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
160016. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
160017. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
160018. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
160019. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
160020. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
160021. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
160022. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
160023. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
160024. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
160025. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
160026. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
160027. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
160028. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
160029. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
160030. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
160031. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
160032. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
160033. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
160034. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
160035. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
160036. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
160037. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
160038. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
160039. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
160040. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
160041. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
160042. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
160043. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
160044. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
160045. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
160046. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
160047. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
160048. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
160049. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
160050. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
160051. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
160052. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
160053. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
160054. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
160055. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
160056. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
160057. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
160058. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
160059. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
160060. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
160061. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
160062. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
160063. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
160064. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
160065. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
160066. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
160067. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
160068. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
160069. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
160070. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
160071. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
160072. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
160073. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
160074. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
160075. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
160076. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
160077. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
160078. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
160079. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
160080. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
160081. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
160082. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
160083. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
160084. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
160085. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
160086. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
160087. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
160088. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
160089. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
160090. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
160091. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
160092. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
160093. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
160094. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
160095. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
160096. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
160097. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
160098. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
160099. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
160100. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
160101. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
160102. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
160103. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
160104. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
160105. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
160106. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
160107. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
160108. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
160109. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
160110. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
160111. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
160112. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
160113. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
160114. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
160115. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
160116. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
160117. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
160118. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
160119. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
160120. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
160121. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
160122. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
160123. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
160124. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
160125. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
160126. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
160127. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
160128. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
160129. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
160130. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
160131. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
160132. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
160133. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
160134. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
160135. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
160136. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
160137. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
160138. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
160139. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
160140. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
160141. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
160142. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
160143. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
160144. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
160145. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
160146. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
160147. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
160148. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
160149. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
160150. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
160151. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
160152. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
160153. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
160154. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
160155. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
160156. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
160157. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
160158. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
160159. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
160160. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
160161. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
160162. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
160163. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
160164. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
160165. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
160166. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
160167. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
160168. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
160169. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
160170. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
160171. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
160172. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
160173. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
160174. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
160175. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
160176. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
160177. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
160178. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
160179. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
160180. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
160181. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
160182. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
160183. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
160184. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
160185. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
160186. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
160187. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
160188. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
160189. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
160190. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
160191. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
160192. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
160193. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
160194. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
160195. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
160196. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
160197. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
160198. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
160199. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
160200. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
160201. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
160202. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
160203. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
160204. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
160205. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
160206. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
160207. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
160208. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
160209. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
160210. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
160211. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
160212. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
160213. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
160214. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
160215. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
160216. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
160217. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
160218. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
160219. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
160220. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
160221. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
160222. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
160223. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
160224. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
160225. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
160226. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
160227. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
160228. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
160229. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
160230. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
160231. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
160232. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
160233. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
160234. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
160235. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
160236. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
160237. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
160238. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
160239. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
160240. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
160241. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
160242. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
160243. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
160244. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
160245. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
160246. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
160247. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
160248. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
160249. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
160250. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
160251. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
160252. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
160253. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
160254. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
160255. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
160256. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
160257. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
160258. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
160259. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
160260. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
160261. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
160262. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
160263. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
160264. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
160265. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
160266. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
160267. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
160268. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
160269. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
160270. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
160271. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
160272. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
160273. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
160274. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
160275. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
160276. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
160277. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
160278. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
160279. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
160280. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
160281. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
160282. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
160283. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
160284. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
160285. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
160286. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
160287. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
160288. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
160289. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
160290. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
160291. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
160292. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
160293. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
160294. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
160295. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
160296. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
160297. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
160298. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
160299. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
160300. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
160301. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
160302. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
160303. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
160304. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
160305. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
160306. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
160307. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
160308. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
160309. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
160310. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
160311. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
160312. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
160313. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
160314. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
160315. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
160316. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
160317. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
160318. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
160319. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
160320. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
160321. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
160322. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
160323. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
160324. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
160325. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
160326. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
160327. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
160328. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
160329. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
160330. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
160331. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
160332. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
160333. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
160334. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
160335. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
160336. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
160337. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
160338. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
160339. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
160340. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
160341. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
160342. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
160343. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
160344. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
160345. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
160346. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
160347. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
160348. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK
160349. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT
160350. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK
160351. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT
160352. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
160353. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
160354. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK
160355. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT
160356. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK
160357. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT
160358. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK
160359. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT
160360. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
160361. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
160362. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
160363. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
160364. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
160365. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
160366. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
160367. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
160368. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
160369. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
160370. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
160371. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
160372. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
160373. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
160374. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
160375. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
160376. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
160377. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
160378. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
160379. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
160380. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
160381. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
160382. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
160383. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
160384. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
160385. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
160386. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
160387. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
160388. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
160389. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
160390. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
160391. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
160392. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
160393. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
160394. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
160395. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
160396. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
160397. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
160398. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
160399. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
160400. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
160401. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
160402. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
160403. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
160404. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
160405. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
160406. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
160407. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
160408. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
160409. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
160410. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
160411. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
160412. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
160413. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
160414. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
160415. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
160416. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
160417. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
160418. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
160419. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
160420. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
160421. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
160422. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
160423. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
160424. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
160425. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
160426. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
160427. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
160428. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
160429. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
160430. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
160431. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
160432. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
160433. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
160434. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
160435. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
160436. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
160437. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
160438. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
160439. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
160440. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
160441. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
160442. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
160443. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
160444. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
160445. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
160446. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
160447. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
160448. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
160449. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
160450. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
160451. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
160452. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
160453. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
160454. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
160455. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
160456. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
160457. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
160458. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
160459. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
160460. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
160461. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
160462. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
160463. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
160464. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
160465. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
160466. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
160467. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
160468. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
160469. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
160470. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
160471. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
160472. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
160473. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
160474. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
160475. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
160476. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
160477. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
160478. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
160479. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
160480. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
160481. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
160482. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
160483. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
160484. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
160485. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
160486. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
160487. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
160488. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
160489. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
160490. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
160491. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
160492. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
160493. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
160494. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
160495. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
160496. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
160497. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
160498. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
160499. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
160500. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
160501. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
160502. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
160503. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
160504. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
160505. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
160506. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
160507. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
160508. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
160509. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
160510. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
160511. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
160512. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
160513. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
160514. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
160515. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
160516. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
160517. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
160518. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
160519. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
160520. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
160521. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
160522. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
160523. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
160524. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
160525. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
160526. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
160527. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
160528. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
160529. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
160530. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
160531. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
160532. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
160533. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
160534. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
160535. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
160536. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
160537. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
160538. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
160539. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
160540. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
160541. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
160542. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
160543. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
160544. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
160545. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
160546. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
160547. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
160548. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
160549. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
160550. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
160551. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
160552. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
160553. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
160554. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
160555. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
160556. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
160557. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
160558. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
160559. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
160560. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
160561. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
160562. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
160563. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
160564. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
160565. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
160566. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
160567. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
160568. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
160569. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
160570. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
160571. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
160572. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
160573. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
160574. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
160575. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
160576. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
160577. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
160578. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
160579. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
160580. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
160581. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
160582. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
160583. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
160584. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
160585. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
160586. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
160587. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
160588. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
160589. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
160590. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
160591. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
160592. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
160593. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
160594. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
160595. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
160596. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
160597. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
160598. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
160599. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
160600. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
160601. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
160602. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
160603. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
160604. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
160605. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
160606. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
160607. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
160608. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
160609. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
160610. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
160611. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
160612. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
160613. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
160614. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
160615. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
160616. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
160617. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
160618. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
160619. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
160620. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
160621. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
160622. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
160623. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
160624. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
160625. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
160626. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
160627. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
160628. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
160629. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
160630. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
160631. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
160632. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
160633. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
160634. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
160635. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
160636. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
160637. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
160638. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
160639. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
160640. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
160641. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
160642. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
160643. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
160644. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
160645. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
160646. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
160647. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
160648. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
160649. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
160650. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
160651. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
160652. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
160653. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
160654. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
160655. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
160656. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
160657. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
160658. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
160659. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
160660. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
160661. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
160662. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
160663. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
160664. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
160665. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
160666. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
160667. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
160668. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
160669. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
160670. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
160671. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
160672. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
160673. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
160674. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
160675. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
160676. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
160677. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
160678. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
160679. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
160680. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
160681. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
160682. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
160683. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
160684. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
160685. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
160686. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
160687. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
160688. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
160689. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
160690. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
160691. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
160692. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
160693. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
160694. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
160695. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
160696. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
160697. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
160698. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
160699. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
160700. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
160701. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
160702. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK
160703. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT
160704. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK
160705. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT
160706. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
160707. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
160708. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
160709. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
160710. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
160711. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
160712. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
160713. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
160714. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
160715. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
160716. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
160717. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
160718. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
160719. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
160720. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
160721. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
160722. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
160723. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
160724. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
160725. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
160726. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
160727. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
160728. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
160729. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
160730. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
160731. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
160732. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
160733. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
160734. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
160735. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
160736. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
160737. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
160738. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
160739. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
160740. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
160741. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
160742. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
160743. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
160744. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
160745. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
160746. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
160747. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
160748. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
160749. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
160750. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
160751. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
160752. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
160753. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
160754. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
160755. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
160756. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
160757. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
160758. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
160759. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
160760. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
160761. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
160762. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
160763. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
160764. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
160765. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
160766. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
160767. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
160768. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
160769. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
160770. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
160771. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
160772. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
160773. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
160774. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
160775. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
160776. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
160777. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
160778. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
160779. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
160780. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
160781. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
160782. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
160783. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
160784. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
160785. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
160786. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
160787. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
160788. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
160789. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
160790. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
160791. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
160792. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
160793. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
160794. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
160795. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
160796. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
160797. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
160798. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
160799. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
160800. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
160801. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
160802. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
160803. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
160804. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
160805. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
160806. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
160807. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
160808. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
160809. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
160810. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
160811. DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
160812. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
160813. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
160814. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
160815. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
160816. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
160817. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
160818. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
160819. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
160820. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
160821. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
160822. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK
160823. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT
160824. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
160825. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
160826. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
160827. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
160828. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
160829. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
160830. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
160831. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
160832. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
160833. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
160834. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
160835. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
160836. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
160837. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
160838. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
160839. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
160840. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
160841. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
160842. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
160843. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
160844. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
160845. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
160846. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
160847. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
160848. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
160849. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
160850. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
160851. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
160852. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
160853. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
160854. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK
160855. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
160856. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK
160857. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
160858. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK
160859. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
160860. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
160861. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
160862. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
160863. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
160864. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
160865. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
160866. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
160867. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
160868. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
160869. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
160870. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
160871. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
160872. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
160873. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
160874. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
160875. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
160876. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
160877. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
160878. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
160879. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
160880. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
160881. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
160882. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
160883. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
160884. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
160885. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
160886. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
160887. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
160888. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
160889. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
160890. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
160891. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
160892. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
160893. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
160894. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
160895. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
160896. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
160897. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
160898. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
160899. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
160900. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK
160901. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
160902. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK
160903. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
160904. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
160905. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
160906. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
160907. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
160908. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
160909. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
160910. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
160911. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
160912. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK
160913. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
160914. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
160915. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
160916. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
160917. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
160918. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
160919. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
160920. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
160921. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
160922. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
160923. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
160924. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__NC32_MASK
160925. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT
160926. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
160927. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
160928. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
160929. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
160930. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
160931. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
160932. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
160933. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
160934. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
160935. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
160936. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK
160937. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
160938. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
160939. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
160940. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
160941. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
160942. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
160943. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
160944. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
160945. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
160946. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
160947. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
160948. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK
160949. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
160950. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
160951. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
160952. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
160953. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
160954. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
160955. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
160956. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
160957. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
160958. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK
160959. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT
160960. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
160961. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
160962. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
160963. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
160964. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
160965. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
160966. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
160967. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
160968. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
160969. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
160970. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
160971. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
160972. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
160973. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
160974. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
160975. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
160976. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
160977. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
160978. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
160979. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
160980. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__NC20_MASK
160981. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__NC20__SHIFT
160982. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK
160983. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT
160984. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
160985. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
160986. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
160987. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
160988. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
160989. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
160990. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK
160991. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
160992. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK
160993. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
160994. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
160995. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
160996. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK
160997. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
160998. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK
160999. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
161000. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK
161001. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT
161002. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
161003. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
161004. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK
161005. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT
161006. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK
161007. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT
161008. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
161009. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
161010. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK
161011. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT
161012. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_gd_MASK
161013. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_gd__SHIFT
161014. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccm_MASK
161015. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT
161016. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccp_MASK
161017. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT
161018. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vptx_MASK
161019. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT
161020. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg0_MASK
161021. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT
161022. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg1_MASK
161023. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT
161024. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK
161025. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT
161026. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__override_regref_0_MASK
161027. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT
161028. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK
161029. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT
161030. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_nbias_MASK
161031. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT
161032. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_pbias_MASK
161033. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT
161034. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK
161035. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT
161036. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfm_MASK
161037. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT
161038. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfp_MASK
161039. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT
161040. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsm_MASK
161041. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT
161042. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsp_MASK
161043. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT
161044. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_vcm_MASK
161045. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT
161046. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
161047. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
161048. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK
161049. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
161050. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
161051. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
161052. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
161053. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
161054. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
161055. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
161056. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
161057. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
161058. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK
161059. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT
161060. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK
161061. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
161062. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__nc_MASK
161063. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__nc__SHIFT
161064. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_nmos_MASK
161065. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_nmos__SHIFT
161066. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_pmos_MASK
161067. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_pmos__SHIFT
161068. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__override_rxdetref_MASK
161069. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT
161070. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
161071. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
161072. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
161073. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
161074. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
161075. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
161076. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
161077. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
161078. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK
161079. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
161080. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
161081. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
161082. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
161083. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
161084. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
161085. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
161086. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
161087. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
161088. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
161089. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
161090. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
161091. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
161092. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
161093. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
161094. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
161095. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
161096. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
161097. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
161098. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
161099. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
161100. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
161101. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
161102. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
161103. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
161104. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
161105. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
161106. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
161107. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
161108. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
161109. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
161110. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK
161111. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
161112. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK
161113. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
161114. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
161115. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
161116. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK
161117. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
161118. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
161119. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
161120. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
161121. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
161122. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK
161123. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
161124. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
161125. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
161126. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
161127. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
161128. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
161129. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
161130. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
161131. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
161132. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
161133. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
161134. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
161135. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
161136. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK
161137. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
161138. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK
161139. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT
161140. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_MASK
161141. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT
161142. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK
161143. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
161144. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
161145. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
161146. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK
161147. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
161148. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK
161149. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
161150. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK
161151. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
161152. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK
161153. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT
161154. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
161155. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
161156. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
161157. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
161158. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
161159. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
161160. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
161161. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
161162. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
161163. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
161164. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
161165. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
161166. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
161167. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
161168. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
161169. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
161170. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
161171. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
161172. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
161173. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
161174. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
161175. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
161176. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
161177. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
161178. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
161179. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
161180. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
161181. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
161182. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
161183. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
161184. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
161185. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
161186. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
161187. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
161188. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
161189. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
161190. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
161191. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
161192. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
161193. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
161194. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
161195. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
161196. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
161197. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
161198. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
161199. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
161200. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
161201. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
161202. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
161203. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
161204. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
161205. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
161206. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
161207. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
161208. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
161209. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
161210. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
161211. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
161212. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
161213. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
161214. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
161215. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
161216. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
161217. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
161218. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
161219. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
161220. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
161221. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
161222. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
161223. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
161224. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
161225. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
161226. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
161227. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
161228. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
161229. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
161230. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
161231. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
161232. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
161233. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
161234. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
161235. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
161236. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
161237. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
161238. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
161239. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
161240. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
161241. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
161242. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
161243. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
161244. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
161245. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
161246. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
161247. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
161248. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
161249. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
161250. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
161251. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
161252. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
161253. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
161254. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
161255. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
161256. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
161257. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
161258. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
161259. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
161260. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
161261. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
161262. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
161263. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
161264. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
161265. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
161266. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
161267. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
161268. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
161269. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
161270. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
161271. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
161272. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
161273. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
161274. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
161275. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
161276. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
161277. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
161278. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
161279. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
161280. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
161281. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
161282. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
161283. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
161284. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
161285. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
161286. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
161287. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
161288. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
161289. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
161290. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
161291. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
161292. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
161293. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
161294. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
161295. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
161296. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
161297. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
161298. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
161299. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
161300. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
161301. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
161302. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
161303. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
161304. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
161305. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
161306. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
161307. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
161308. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
161309. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
161310. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
161311. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
161312. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
161313. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
161314. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
161315. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
161316. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
161317. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
161318. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
161319. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
161320. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
161321. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
161322. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
161323. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
161324. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
161325. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
161326. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
161327. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
161328. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
161329. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
161330. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
161331. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
161332. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
161333. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
161334. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
161335. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
161336. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
161337. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
161338. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
161339. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
161340. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
161341. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
161342. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
161343. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
161344. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
161345. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
161346. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
161347. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
161348. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
161349. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
161350. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
161351. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
161352. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
161353. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
161354. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
161355. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
161356. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
161357. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
161358. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
161359. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
161360. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
161361. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
161362. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
161363. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
161364. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
161365. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
161366. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
161367. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
161368. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
161369. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
161370. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
161371. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
161372. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
161373. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
161374. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
161375. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
161376. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
161377. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
161378. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
161379. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
161380. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
161381. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
161382. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
161383. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
161384. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
161385. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
161386. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
161387. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
161388. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
161389. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
161390. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
161391. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
161392. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
161393. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
161394. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
161395. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
161396. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
161397. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
161398. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK
161399. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
161400. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
161401. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
161402. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
161403. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
161404. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
161405. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
161406. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
161407. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
161408. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
161409. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
161410. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
161411. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
161412. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
161413. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
161414. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
161415. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
161416. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
161417. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
161418. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
161419. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
161420. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
161421. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
161422. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
161423. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
161424. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
161425. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
161426. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
161427. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
161428. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
161429. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
161430. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
161431. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
161432. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
161433. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
161434. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
161435. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
161436. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
161437. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
161438. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
161439. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
161440. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
161441. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
161442. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
161443. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
161444. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
161445. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
161446. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
161447. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
161448. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
161449. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
161450. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
161451. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
161452. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
161453. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
161454. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
161455. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
161456. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
161457. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
161458. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
161459. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
161460. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
161461. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
161462. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
161463. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
161464. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
161465. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
161466. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
161467. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
161468. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
161469. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
161470. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
161471. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
161472. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
161473. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
161474. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
161475. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
161476. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
161477. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
161478. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
161479. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
161480. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
161481. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
161482. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
161483. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
161484. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
161485. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
161486. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
161487. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
161488. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
161489. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
161490. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
161491. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
161492. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
161493. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
161494. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
161495. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
161496. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
161497. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
161498. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
161499. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
161500. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
161501. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
161502. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
161503. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
161504. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
161505. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
161506. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
161507. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
161508. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
161509. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
161510. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
161511. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
161512. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
161513. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
161514. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
161515. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
161516. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
161517. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
161518. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
161519. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
161520. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
161521. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
161522. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
161523. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
161524. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
161525. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
161526. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
161527. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
161528. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
161529. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
161530. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
161531. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
161532. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
161533. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
161534. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
161535. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
161536. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
161537. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
161538. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
161539. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
161540. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
161541. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
161542. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
161543. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
161544. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
161545. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
161546. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
161547. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
161548. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
161549. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
161550. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
161551. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
161552. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
161553. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
161554. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
161555. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
161556. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
161557. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
161558. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
161559. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
161560. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
161561. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
161562. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
161563. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
161564. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
161565. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
161566. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
161567. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
161568. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
161569. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
161570. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
161571. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
161572. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
161573. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
161574. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
161575. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
161576. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
161577. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
161578. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
161579. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
161580. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
161581. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
161582. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
161583. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
161584. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
161585. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
161586. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
161587. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
161588. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
161589. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
161590. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
161591. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
161592. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
161593. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
161594. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
161595. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
161596. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
161597. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
161598. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
161599. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
161600. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
161601. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
161602. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
161603. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
161604. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
161605. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
161606. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
161607. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
161608. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
161609. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
161610. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
161611. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
161612. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
161613. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
161614. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
161615. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
161616. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
161617. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
161618. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
161619. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
161620. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
161621. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
161622. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
161623. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
161624. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
161625. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
161626. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
161627. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
161628. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
161629. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
161630. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
161631. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
161632. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
161633. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
161634. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
161635. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
161636. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
161637. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
161638. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
161639. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
161640. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
161641. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
161642. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
161643. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
161644. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
161645. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
161646. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
161647. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
161648. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
161649. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
161650. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
161651. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
161652. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
161653. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
161654. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
161655. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
161656. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
161657. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
161658. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
161659. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
161660. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
161661. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
161662. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
161663. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
161664. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
161665. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
161666. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
161667. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
161668. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
161669. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
161670. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
161671. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
161672. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
161673. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
161674. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
161675. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
161676. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
161677. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
161678. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
161679. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
161680. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
161681. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
161682. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
161683. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
161684. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
161685. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
161686. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
161687. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
161688. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
161689. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
161690. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
161691. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
161692. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
161693. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
161694. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
161695. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
161696. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
161697. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
161698. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
161699. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
161700. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
161701. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
161702. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
161703. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
161704. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
161705. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
161706. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
161707. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
161708. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
161709. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
161710. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
161711. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
161712. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
161713. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
161714. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
161715. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
161716. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
161717. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
161718. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
161719. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
161720. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
161721. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
161722. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
161723. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
161724. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
161725. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
161726. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
161727. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
161728. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
161729. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
161730. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
161731. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
161732. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
161733. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
161734. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
161735. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
161736. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
161737. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
161738. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
161739. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
161740. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
161741. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
161742. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
161743. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
161744. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
161745. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
161746. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
161747. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
161748. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
161749. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
161750. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
161751. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
161752. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
161753. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
161754. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
161755. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
161756. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
161757. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
161758. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
161759. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
161760. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
161761. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
161762. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
161763. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
161764. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
161765. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
161766. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
161767. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
161768. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
161769. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
161770. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
161771. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
161772. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
161773. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
161774. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
161775. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
161776. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
161777. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
161778. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
161779. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
161780. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
161781. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
161782. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
161783. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
161784. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
161785. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
161786. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
161787. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
161788. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
161789. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
161790. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
161791. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
161792. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
161793. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
161794. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
161795. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
161796. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
161797. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
161798. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
161799. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
161800. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
161801. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
161802. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
161803. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
161804. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
161805. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
161806. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
161807. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
161808. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
161809. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
161810. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
161811. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
161812. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
161813. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
161814. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
161815. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
161816. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
161817. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
161818. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
161819. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
161820. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
161821. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
161822. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
161823. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
161824. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
161825. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
161826. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
161827. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
161828. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
161829. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
161830. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
161831. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
161832. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
161833. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
161834. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
161835. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
161836. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
161837. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
161838. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
161839. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
161840. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
161841. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
161842. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
161843. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
161844. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
161845. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
161846. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
161847. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
161848. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
161849. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
161850. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
161851. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
161852. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
161853. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
161854. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
161855. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
161856. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
161857. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
161858. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
161859. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
161860. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
161861. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
161862. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
161863. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
161864. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
161865. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
161866. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
161867. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
161868. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
161869. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
161870. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
161871. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
161872. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
161873. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
161874. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
161875. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
161876. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
161877. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
161878. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
161879. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
161880. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
161881. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
161882. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
161883. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
161884. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
161885. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
161886. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
161887. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
161888. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
161889. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
161890. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
161891. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
161892. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
161893. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
161894. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
161895. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
161896. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
161897. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
161898. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
161899. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
161900. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
161901. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
161902. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
161903. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
161904. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
161905. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
161906. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
161907. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
161908. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
161909. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
161910. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
161911. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
161912. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
161913. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
161914. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
161915. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
161916. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
161917. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
161918. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
161919. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
161920. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
161921. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
161922. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
161923. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
161924. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
161925. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
161926. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
161927. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
161928. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
161929. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
161930. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
161931. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
161932. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
161933. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
161934. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
161935. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
161936. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
161937. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
161938. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
161939. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
161940. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
161941. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
161942. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
161943. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
161944. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
161945. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
161946. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
161947. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
161948. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
161949. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
161950. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
161951. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
161952. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
161953. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
161954. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK
161955. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT
161956. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK
161957. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT
161958. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
161959. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
161960. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK
161961. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT
161962. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK
161963. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT
161964. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK
161965. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT
161966. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
161967. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
161968. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
161969. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
161970. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
161971. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
161972. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
161973. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
161974. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
161975. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
161976. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
161977. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
161978. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
161979. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
161980. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
161981. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
161982. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
161983. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
161984. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
161985. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
161986. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
161987. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
161988. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
161989. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
161990. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
161991. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
161992. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
161993. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
161994. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
161995. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
161996. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
161997. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
161998. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
161999. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
162000. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
162001. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
162002. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
162003. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
162004. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
162005. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
162006. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
162007. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
162008. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
162009. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
162010. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
162011. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
162012. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
162013. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
162014. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
162015. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
162016. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
162017. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
162018. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
162019. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
162020. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
162021. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
162022. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
162023. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
162024. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
162025. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
162026. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
162027. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
162028. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
162029. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
162030. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
162031. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
162032. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
162033. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
162034. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
162035. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
162036. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
162037. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
162038. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
162039. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
162040. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
162041. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
162042. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
162043. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
162044. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
162045. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
162046. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
162047. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
162048. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
162049. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
162050. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
162051. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
162052. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
162053. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
162054. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
162055. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
162056. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
162057. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
162058. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
162059. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
162060. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
162061. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
162062. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
162063. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
162064. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
162065. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
162066. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
162067. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
162068. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
162069. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
162070. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
162071. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
162072. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
162073. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
162074. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
162075. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
162076. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
162077. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
162078. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
162079. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
162080. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
162081. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
162082. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
162083. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
162084. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
162085. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
162086. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
162087. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
162088. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
162089. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
162090. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
162091. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
162092. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
162093. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
162094. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
162095. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
162096. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
162097. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
162098. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
162099. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
162100. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
162101. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
162102. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
162103. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
162104. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
162105. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
162106. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
162107. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
162108. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
162109. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
162110. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
162111. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
162112. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
162113. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
162114. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
162115. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
162116. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
162117. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
162118. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
162119. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
162120. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
162121. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
162122. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
162123. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
162124. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
162125. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
162126. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
162127. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
162128. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
162129. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
162130. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
162131. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
162132. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
162133. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
162134. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
162135. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
162136. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
162137. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
162138. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
162139. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
162140. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
162141. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
162142. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
162143. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
162144. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
162145. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
162146. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
162147. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
162148. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
162149. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
162150. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
162151. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
162152. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
162153. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
162154. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
162155. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
162156. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
162157. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
162158. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
162159. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
162160. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
162161. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
162162. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
162163. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
162164. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
162165. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
162166. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
162167. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
162168. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
162169. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
162170. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
162171. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
162172. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
162173. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
162174. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
162175. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
162176. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
162177. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
162178. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
162179. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
162180. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
162181. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
162182. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
162183. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
162184. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
162185. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
162186. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
162187. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
162188. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
162189. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
162190. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
162191. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
162192. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
162193. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
162194. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
162195. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
162196. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
162197. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
162198. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
162199. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
162200. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
162201. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
162202. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
162203. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
162204. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
162205. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
162206. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
162207. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
162208. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
162209. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
162210. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
162211. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
162212. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
162213. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
162214. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
162215. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
162216. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
162217. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
162218. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
162219. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
162220. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
162221. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
162222. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
162223. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
162224. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
162225. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
162226. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
162227. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
162228. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
162229. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
162230. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
162231. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
162232. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
162233. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
162234. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
162235. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
162236. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
162237. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
162238. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
162239. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
162240. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
162241. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
162242. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
162243. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
162244. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
162245. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
162246. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
162247. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
162248. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
162249. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
162250. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
162251. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
162252. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
162253. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
162254. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
162255. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
162256. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
162257. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
162258. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
162259. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
162260. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
162261. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
162262. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
162263. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
162264. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
162265. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
162266. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
162267. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
162268. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
162269. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
162270. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
162271. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
162272. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
162273. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
162274. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
162275. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
162276. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
162277. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
162278. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
162279. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
162280. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
162281. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
162282. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
162283. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
162284. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
162285. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
162286. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
162287. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
162288. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
162289. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
162290. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
162291. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
162292. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
162293. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
162294. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
162295. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
162296. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
162297. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
162298. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
162299. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
162300. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
162301. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
162302. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
162303. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
162304. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
162305. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
162306. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
162307. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
162308. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK
162309. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT
162310. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK
162311. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT
162312. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
162313. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
162314. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
162315. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
162316. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
162317. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
162318. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
162319. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
162320. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
162321. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
162322. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
162323. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
162324. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
162325. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
162326. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
162327. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
162328. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
162329. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
162330. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
162331. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
162332. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
162333. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
162334. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
162335. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
162336. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
162337. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
162338. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
162339. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
162340. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
162341. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
162342. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
162343. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
162344. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
162345. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
162346. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
162347. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
162348. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
162349. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
162350. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
162351. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
162352. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
162353. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
162354. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
162355. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
162356. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
162357. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
162358. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
162359. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
162360. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
162361. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
162362. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
162363. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
162364. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
162365. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
162366. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
162367. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
162368. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
162369. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
162370. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
162371. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
162372. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
162373. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
162374. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
162375. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
162376. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
162377. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
162378. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
162379. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
162380. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
162381. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
162382. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
162383. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
162384. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
162385. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
162386. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
162387. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
162388. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
162389. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
162390. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
162391. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
162392. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
162393. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
162394. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
162395. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
162396. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
162397. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
162398. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
162399. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
162400. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
162401. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
162402. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
162403. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
162404. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
162405. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
162406. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
162407. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
162408. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
162409. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
162410. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
162411. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
162412. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
162413. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
162414. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
162415. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
162416. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
162417. DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
162418. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
162419. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
162420. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
162421. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
162422. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
162423. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
162424. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
162425. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
162426. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
162427. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
162428. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK
162429. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT
162430. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
162431. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
162432. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
162433. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
162434. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
162435. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
162436. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
162437. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
162438. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
162439. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
162440. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
162441. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
162442. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
162443. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
162444. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
162445. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
162446. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
162447. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
162448. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
162449. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
162450. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
162451. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
162452. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
162453. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
162454. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
162455. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
162456. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
162457. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
162458. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
162459. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
162460. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK
162461. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
162462. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK
162463. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
162464. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK
162465. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
162466. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
162467. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
162468. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
162469. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
162470. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
162471. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
162472. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
162473. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
162474. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
162475. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
162476. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
162477. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
162478. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
162479. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
162480. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
162481. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
162482. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
162483. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
162484. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
162485. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
162486. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
162487. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
162488. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
162489. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
162490. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
162491. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
162492. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
162493. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
162494. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
162495. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
162496. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
162497. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
162498. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
162499. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
162500. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
162501. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
162502. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
162503. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
162504. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
162505. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
162506. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK
162507. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
162508. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK
162509. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
162510. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
162511. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
162512. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
162513. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
162514. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
162515. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
162516. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
162517. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
162518. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK
162519. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
162520. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
162521. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
162522. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
162523. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
162524. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
162525. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
162526. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
162527. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
162528. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
162529. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
162530. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__NC32_MASK
162531. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT
162532. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
162533. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
162534. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
162535. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
162536. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
162537. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
162538. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
162539. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
162540. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
162541. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
162542. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK
162543. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
162544. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
162545. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
162546. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
162547. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
162548. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
162549. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
162550. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
162551. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
162552. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
162553. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
162554. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK
162555. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
162556. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
162557. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
162558. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
162559. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
162560. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
162561. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
162562. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
162563. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
162564. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK
162565. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT
162566. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
162567. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
162568. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
162569. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
162570. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
162571. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
162572. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
162573. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
162574. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
162575. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
162576. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
162577. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
162578. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
162579. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
162580. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
162581. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
162582. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
162583. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
162584. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
162585. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
162586. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__NC20_MASK
162587. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__NC20__SHIFT
162588. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK
162589. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT
162590. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
162591. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
162592. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
162593. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
162594. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
162595. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
162596. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK
162597. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
162598. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK
162599. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
162600. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
162601. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
162602. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK
162603. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
162604. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK
162605. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
162606. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK
162607. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT
162608. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
162609. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
162610. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK
162611. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT
162612. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK
162613. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT
162614. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
162615. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
162616. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK
162617. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT
162618. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_gd_MASK
162619. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_gd__SHIFT
162620. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccm_MASK
162621. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT
162622. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccp_MASK
162623. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT
162624. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vptx_MASK
162625. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT
162626. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg0_MASK
162627. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT
162628. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg1_MASK
162629. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT
162630. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK
162631. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT
162632. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__override_regref_0_MASK
162633. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT
162634. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK
162635. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT
162636. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_nbias_MASK
162637. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT
162638. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_pbias_MASK
162639. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT
162640. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK
162641. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT
162642. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfm_MASK
162643. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT
162644. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfp_MASK
162645. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT
162646. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsm_MASK
162647. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT
162648. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsp_MASK
162649. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT
162650. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_vcm_MASK
162651. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT
162652. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
162653. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
162654. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK
162655. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
162656. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
162657. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
162658. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
162659. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
162660. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
162661. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
162662. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
162663. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
162664. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK
162665. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT
162666. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK
162667. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
162668. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__nc_MASK
162669. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__nc__SHIFT
162670. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_nmos_MASK
162671. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_nmos__SHIFT
162672. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_pmos_MASK
162673. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_pmos__SHIFT
162674. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__override_rxdetref_MASK
162675. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT
162676. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
162677. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
162678. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
162679. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
162680. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
162681. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
162682. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
162683. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
162684. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK
162685. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
162686. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
162687. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
162688. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
162689. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
162690. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
162691. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
162692. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
162693. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
162694. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
162695. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
162696. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
162697. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
162698. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
162699. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
162700. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
162701. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
162702. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
162703. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
162704. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
162705. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
162706. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
162707. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
162708. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
162709. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
162710. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
162711. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
162712. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
162713. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
162714. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
162715. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
162716. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK
162717. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
162718. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK
162719. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
162720. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
162721. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
162722. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK
162723. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
162724. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
162725. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
162726. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
162727. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
162728. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK
162729. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
162730. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
162731. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
162732. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
162733. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
162734. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
162735. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
162736. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
162737. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
162738. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
162739. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
162740. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
162741. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
162742. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK
162743. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
162744. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK
162745. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT
162746. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_MASK
162747. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT
162748. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK
162749. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
162750. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
162751. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
162752. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK
162753. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
162754. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK
162755. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
162756. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK
162757. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
162758. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK
162759. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT
162760. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
162761. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
162762. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
162763. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
162764. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
162765. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
162766. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
162767. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
162768. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
162769. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
162770. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
162771. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
162772. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
162773. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
162774. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
162775. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
162776. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
162777. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
162778. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
162779. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
162780. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
162781. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
162782. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
162783. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
162784. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
162785. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
162786. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
162787. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
162788. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
162789. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
162790. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
162791. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
162792. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
162793. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
162794. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
162795. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
162796. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
162797. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
162798. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
162799. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
162800. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
162801. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
162802. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
162803. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
162804. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
162805. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
162806. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
162807. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
162808. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
162809. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
162810. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
162811. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
162812. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
162813. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
162814. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
162815. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
162816. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
162817. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
162818. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
162819. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
162820. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
162821. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
162822. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
162823. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
162824. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
162825. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
162826. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
162827. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
162828. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
162829. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
162830. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
162831. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
162832. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
162833. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
162834. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
162835. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
162836. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
162837. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
162838. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
162839. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
162840. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
162841. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
162842. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
162843. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
162844. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
162845. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
162846. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
162847. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
162848. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
162849. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
162850. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
162851. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
162852. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
162853. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
162854. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
162855. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
162856. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
162857. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
162858. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
162859. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
162860. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
162861. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
162862. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
162863. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
162864. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
162865. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
162866. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
162867. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
162868. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
162869. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
162870. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
162871. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
162872. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
162873. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
162874. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
162875. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
162876. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
162877. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
162878. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
162879. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
162880. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
162881. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
162882. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
162883. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
162884. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
162885. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
162886. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
162887. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
162888. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
162889. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
162890. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
162891. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
162892. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
162893. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
162894. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
162895. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
162896. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
162897. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
162898. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
162899. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
162900. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
162901. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
162902. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
162903. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
162904. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
162905. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
162906. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
162907. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
162908. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
162909. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
162910. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
162911. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
162912. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
162913. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
162914. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
162915. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
162916. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
162917. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
162918. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
162919. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
162920. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
162921. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
162922. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
162923. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
162924. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
162925. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
162926. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
162927. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
162928. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
162929. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
162930. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
162931. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
162932. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
162933. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
162934. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
162935. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
162936. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
162937. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
162938. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
162939. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
162940. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
162941. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
162942. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
162943. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
162944. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
162945. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
162946. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
162947. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
162948. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
162949. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
162950. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
162951. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
162952. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
162953. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
162954. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
162955. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
162956. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
162957. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
162958. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
162959. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
162960. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
162961. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
162962. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
162963. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
162964. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
162965. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
162966. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
162967. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
162968. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
162969. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
162970. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
162971. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
162972. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
162973. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
162974. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
162975. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
162976. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
162977. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
162978. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
162979. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
162980. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
162981. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
162982. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
162983. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
162984. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
162985. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
162986. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
162987. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
162988. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
162989. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
162990. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
162991. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
162992. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
162993. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
162994. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
162995. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
162996. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
162997. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
162998. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
162999. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
163000. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
163001. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
163002. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
163003. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
163004. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK
163005. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
163006. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
163007. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
163008. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
163009. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
163010. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
163011. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
163012. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
163013. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
163014. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
163015. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
163016. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
163017. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
163018. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
163019. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
163020. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
163021. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
163022. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
163023. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
163024. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
163025. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
163026. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
163027. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
163028. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
163029. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
163030. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
163031. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
163032. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
163033. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
163034. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
163035. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
163036. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
163037. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
163038. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
163039. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
163040. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
163041. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
163042. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
163043. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
163044. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
163045. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
163046. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
163047. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
163048. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
163049. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
163050. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
163051. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
163052. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
163053. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
163054. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
163055. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
163056. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
163057. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
163058. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
163059. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
163060. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
163061. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
163062. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
163063. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
163064. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
163065. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
163066. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
163067. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
163068. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
163069. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
163070. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
163071. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
163072. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
163073. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
163074. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
163075. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
163076. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
163077. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
163078. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
163079. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
163080. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
163081. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
163082. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
163083. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
163084. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
163085. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
163086. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
163087. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
163088. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
163089. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
163090. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
163091. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
163092. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
163093. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
163094. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
163095. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
163096. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
163097. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
163098. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
163099. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
163100. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
163101. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
163102. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
163103. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
163104. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
163105. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
163106. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
163107. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
163108. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
163109. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
163110. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
163111. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
163112. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
163113. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
163114. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
163115. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
163116. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
163117. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
163118. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
163119. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
163120. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
163121. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
163122. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
163123. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
163124. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
163125. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
163126. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
163127. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
163128. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
163129. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
163130. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
163131. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
163132. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
163133. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
163134. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
163135. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
163136. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
163137. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
163138. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
163139. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
163140. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
163141. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
163142. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
163143. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
163144. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
163145. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
163146. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
163147. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
163148. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
163149. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
163150. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
163151. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
163152. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
163153. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
163154. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
163155. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
163156. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
163157. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
163158. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
163159. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
163160. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
163161. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
163162. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
163163. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
163164. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
163165. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
163166. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
163167. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
163168. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
163169. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
163170. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
163171. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
163172. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
163173. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
163174. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
163175. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
163176. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
163177. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
163178. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
163179. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
163180. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
163181. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
163182. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
163183. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
163184. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
163185. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
163186. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
163187. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
163188. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
163189. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
163190. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
163191. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
163192. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
163193. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
163194. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
163195. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
163196. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
163197. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
163198. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
163199. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
163200. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
163201. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
163202. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
163203. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
163204. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
163205. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
163206. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
163207. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
163208. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
163209. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
163210. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
163211. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
163212. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
163213. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
163214. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
163215. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
163216. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
163217. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
163218. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
163219. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
163220. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
163221. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
163222. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
163223. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
163224. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
163225. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
163226. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
163227. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
163228. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
163229. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
163230. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
163231. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
163232. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
163233. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
163234. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
163235. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
163236. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
163237. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
163238. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
163239. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
163240. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
163241. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
163242. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
163243. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
163244. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
163245. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
163246. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
163247. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
163248. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
163249. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
163250. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
163251. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
163252. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
163253. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
163254. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
163255. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
163256. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
163257. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
163258. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
163259. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
163260. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
163261. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
163262. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
163263. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
163264. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
163265. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
163266. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
163267. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
163268. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
163269. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
163270. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
163271. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
163272. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
163273. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
163274. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
163275. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
163276. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
163277. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
163278. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
163279. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
163280. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
163281. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
163282. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
163283. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
163284. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
163285. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
163286. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
163287. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
163288. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
163289. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
163290. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
163291. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
163292. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
163293. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
163294. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
163295. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
163296. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
163297. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
163298. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
163299. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
163300. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
163301. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
163302. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
163303. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
163304. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
163305. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
163306. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
163307. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
163308. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
163309. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
163310. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
163311. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
163312. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
163313. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
163314. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
163315. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
163316. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
163317. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
163318. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
163319. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
163320. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
163321. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
163322. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
163323. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
163324. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
163325. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
163326. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
163327. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
163328. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
163329. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
163330. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
163331. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
163332. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
163333. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
163334. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
163335. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
163336. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
163337. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
163338. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
163339. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
163340. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
163341. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
163342. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
163343. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
163344. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
163345. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
163346. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
163347. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
163348. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
163349. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
163350. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
163351. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
163352. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
163353. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
163354. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
163355. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
163356. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
163357. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
163358. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
163359. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
163360. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
163361. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
163362. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
163363. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
163364. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
163365. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
163366. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
163367. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
163368. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
163369. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
163370. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
163371. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
163372. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
163373. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
163374. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
163375. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
163376. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
163377. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
163378. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
163379. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
163380. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
163381. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
163382. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
163383. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
163384. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
163385. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
163386. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
163387. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
163388. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
163389. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
163390. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
163391. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
163392. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
163393. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
163394. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
163395. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
163396. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
163397. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
163398. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
163399. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
163400. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
163401. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
163402. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
163403. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
163404. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
163405. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
163406. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
163407. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
163408. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
163409. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
163410. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
163411. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
163412. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
163413. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
163414. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
163415. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
163416. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
163417. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
163418. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
163419. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
163420. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
163421. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
163422. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
163423. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
163424. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
163425. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
163426. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
163427. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
163428. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
163429. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
163430. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
163431. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
163432. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
163433. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
163434. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
163435. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
163436. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
163437. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
163438. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
163439. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
163440. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
163441. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
163442. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
163443. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
163444. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
163445. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
163446. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
163447. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
163448. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
163449. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
163450. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
163451. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
163452. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
163453. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
163454. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
163455. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
163456. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
163457. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
163458. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
163459. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
163460. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
163461. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
163462. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
163463. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
163464. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
163465. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
163466. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
163467. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
163468. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
163469. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
163470. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
163471. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
163472. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
163473. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
163474. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
163475. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
163476. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
163477. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
163478. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
163479. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
163480. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
163481. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
163482. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
163483. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
163484. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
163485. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
163486. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
163487. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
163488. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
163489. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
163490. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
163491. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
163492. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
163493. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
163494. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
163495. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
163496. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
163497. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
163498. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
163499. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
163500. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
163501. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
163502. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
163503. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
163504. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
163505. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
163506. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
163507. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
163508. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
163509. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
163510. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
163511. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
163512. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
163513. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
163514. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
163515. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
163516. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
163517. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
163518. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
163519. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
163520. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
163521. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
163522. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
163523. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
163524. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
163525. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
163526. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
163527. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
163528. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
163529. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
163530. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
163531. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
163532. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
163533. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
163534. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
163535. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
163536. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
163537. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
163538. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
163539. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
163540. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
163541. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
163542. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
163543. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
163544. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
163545. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
163546. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
163547. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
163548. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
163549. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
163550. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
163551. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
163552. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
163553. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
163554. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
163555. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
163556. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
163557. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
163558. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
163559. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
163560. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK
163561. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT
163562. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__MODE_MASK
163563. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT
163564. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
163565. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
163566. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK
163567. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT
163568. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK
163569. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT
163570. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__OV14_MASK
163571. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT
163572. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
163573. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
163574. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
163575. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
163576. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
163577. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
163578. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
163579. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
163580. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
163581. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
163582. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
163583. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
163584. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
163585. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
163586. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
163587. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
163588. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
163589. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
163590. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
163591. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
163592. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
163593. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
163594. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
163595. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
163596. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
163597. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
163598. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
163599. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
163600. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
163601. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
163602. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
163603. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
163604. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
163605. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
163606. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
163607. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
163608. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
163609. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
163610. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
163611. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
163612. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
163613. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
163614. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
163615. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
163616. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
163617. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
163618. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
163619. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
163620. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
163621. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
163622. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
163623. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
163624. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
163625. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
163626. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
163627. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
163628. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
163629. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
163630. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
163631. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
163632. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
163633. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
163634. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
163635. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
163636. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
163637. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
163638. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
163639. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
163640. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
163641. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
163642. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
163643. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
163644. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
163645. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
163646. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
163647. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
163648. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
163649. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
163650. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
163651. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
163652. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
163653. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
163654. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
163655. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
163656. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
163657. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
163658. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
163659. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
163660. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
163661. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
163662. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
163663. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
163664. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
163665. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
163666. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
163667. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
163668. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
163669. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
163670. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
163671. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
163672. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
163673. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
163674. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
163675. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
163676. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
163677. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
163678. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
163679. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
163680. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
163681. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
163682. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
163683. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
163684. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
163685. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
163686. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
163687. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
163688. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
163689. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
163690. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
163691. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
163692. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
163693. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
163694. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
163695. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
163696. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
163697. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
163698. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
163699. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
163700. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
163701. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
163702. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
163703. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
163704. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
163705. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
163706. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
163707. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
163708. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
163709. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
163710. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
163711. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
163712. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
163713. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
163714. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
163715. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
163716. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
163717. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
163718. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
163719. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
163720. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
163721. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
163722. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
163723. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
163724. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
163725. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
163726. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
163727. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
163728. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
163729. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
163730. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
163731. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
163732. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
163733. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
163734. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
163735. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
163736. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
163737. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
163738. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
163739. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
163740. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
163741. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
163742. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
163743. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
163744. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
163745. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
163746. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
163747. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
163748. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
163749. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
163750. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
163751. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
163752. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
163753. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
163754. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
163755. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
163756. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
163757. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
163758. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
163759. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
163760. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
163761. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
163762. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
163763. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
163764. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
163765. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
163766. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
163767. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
163768. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
163769. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
163770. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
163771. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
163772. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
163773. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
163774. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
163775. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
163776. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
163777. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
163778. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
163779. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
163780. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
163781. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
163782. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
163783. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
163784. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
163785. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
163786. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
163787. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
163788. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
163789. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
163790. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
163791. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
163792. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
163793. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
163794. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
163795. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
163796. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
163797. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
163798. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
163799. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
163800. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
163801. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
163802. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
163803. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
163804. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
163805. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
163806. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
163807. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
163808. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
163809. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
163810. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
163811. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
163812. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
163813. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
163814. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
163815. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
163816. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
163817. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
163818. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
163819. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
163820. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
163821. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
163822. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
163823. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
163824. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
163825. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
163826. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
163827. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
163828. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
163829. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
163830. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
163831. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
163832. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
163833. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
163834. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
163835. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
163836. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
163837. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
163838. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
163839. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
163840. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
163841. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
163842. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
163843. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
163844. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
163845. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
163846. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
163847. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
163848. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
163849. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
163850. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
163851. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
163852. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
163853. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
163854. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
163855. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
163856. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
163857. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
163858. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
163859. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
163860. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
163861. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
163862. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
163863. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
163864. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
163865. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
163866. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
163867. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
163868. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
163869. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
163870. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
163871. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
163872. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
163873. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
163874. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
163875. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
163876. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
163877. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
163878. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
163879. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
163880. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
163881. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
163882. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
163883. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
163884. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
163885. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
163886. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
163887. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
163888. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
163889. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
163890. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
163891. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
163892. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
163893. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
163894. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
163895. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
163896. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
163897. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
163898. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
163899. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
163900. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
163901. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
163902. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
163903. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
163904. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
163905. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
163906. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
163907. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
163908. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
163909. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
163910. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
163911. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
163912. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
163913. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
163914. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK
163915. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT
163916. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK
163917. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT
163918. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
163919. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
163920. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
163921. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
163922. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
163923. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
163924. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
163925. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
163926. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
163927. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
163928. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
163929. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
163930. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
163931. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
163932. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
163933. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
163934. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
163935. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
163936. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
163937. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
163938. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
163939. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
163940. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
163941. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
163942. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
163943. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
163944. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
163945. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
163946. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
163947. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
163948. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
163949. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
163950. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
163951. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
163952. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
163953. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
163954. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
163955. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
163956. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
163957. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
163958. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
163959. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
163960. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
163961. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
163962. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
163963. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
163964. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
163965. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
163966. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
163967. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
163968. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
163969. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
163970. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
163971. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
163972. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
163973. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
163974. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
163975. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
163976. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
163977. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
163978. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
163979. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
163980. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
163981. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
163982. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
163983. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
163984. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
163985. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
163986. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
163987. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
163988. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
163989. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
163990. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
163991. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
163992. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
163993. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
163994. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
163995. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
163996. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
163997. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
163998. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
163999. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
164000. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
164001. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
164002. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
164003. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
164004. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
164005. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
164006. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
164007. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
164008. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
164009. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
164010. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
164011. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
164012. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
164013. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
164014. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
164015. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
164016. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
164017. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
164018. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
164019. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
164020. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
164021. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
164022. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
164023. DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
164024. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
164025. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
164026. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
164027. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
164028. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
164029. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
164030. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
164031. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
164032. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
164033. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
164034. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK
164035. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT
164036. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
164037. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
164038. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
164039. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
164040. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
164041. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
164042. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
164043. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
164044. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
164045. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
164046. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
164047. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
164048. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
164049. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
164050. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
164051. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
164052. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
164053. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
164054. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
164055. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
164056. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
164057. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
164058. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
164059. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
164060. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
164061. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
164062. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
164063. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
164064. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
164065. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
164066. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK
164067. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
164068. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK
164069. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
164070. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK
164071. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
164072. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
164073. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
164074. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
164075. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
164076. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
164077. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
164078. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
164079. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
164080. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
164081. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
164082. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
164083. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
164084. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
164085. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
164086. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
164087. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
164088. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
164089. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
164090. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
164091. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
164092. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
164093. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
164094. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
164095. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
164096. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
164097. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
164098. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
164099. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
164100. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
164101. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
164102. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
164103. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
164104. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
164105. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
164106. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
164107. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
164108. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
164109. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
164110. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
164111. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
164112. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK
164113. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
164114. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK
164115. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
164116. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
164117. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
164118. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
164119. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
164120. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
164121. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
164122. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
164123. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
164124. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK
164125. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
164126. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
164127. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
164128. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
164129. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
164130. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
164131. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
164132. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
164133. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
164134. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
164135. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
164136. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__NC32_MASK
164137. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT
164138. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
164139. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
164140. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
164141. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
164142. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
164143. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
164144. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
164145. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
164146. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
164147. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
164148. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK
164149. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
164150. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
164151. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
164152. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
164153. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
164154. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
164155. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
164156. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
164157. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
164158. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
164159. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
164160. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK
164161. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
164162. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
164163. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
164164. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
164165. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
164166. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
164167. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
164168. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
164169. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
164170. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK
164171. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT
164172. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
164173. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
164174. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
164175. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
164176. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
164177. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
164178. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
164179. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
164180. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
164181. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
164182. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
164183. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
164184. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
164185. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
164186. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
164187. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
164188. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
164189. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
164190. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
164191. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
164192. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__NC20_MASK
164193. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__NC20__SHIFT
164194. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK
164195. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT
164196. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
164197. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
164198. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
164199. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
164200. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
164201. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
164202. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK
164203. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
164204. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK
164205. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
164206. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
164207. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
164208. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK
164209. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
164210. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK
164211. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
164212. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK
164213. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT
164214. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
164215. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
164216. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK
164217. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT
164218. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK
164219. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT
164220. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
164221. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
164222. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK
164223. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT
164224. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_gd_MASK
164225. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_gd__SHIFT
164226. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccm_MASK
164227. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT
164228. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccp_MASK
164229. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT
164230. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vptx_MASK
164231. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT
164232. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg0_MASK
164233. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT
164234. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg1_MASK
164235. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT
164236. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK
164237. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT
164238. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__override_regref_0_MASK
164239. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT
164240. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK
164241. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT
164242. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_nbias_MASK
164243. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT
164244. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_pbias_MASK
164245. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT
164246. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK
164247. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT
164248. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfm_MASK
164249. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT
164250. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfp_MASK
164251. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT
164252. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsm_MASK
164253. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT
164254. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsp_MASK
164255. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT
164256. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_vcm_MASK
164257. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT
164258. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
164259. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
164260. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK
164261. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
164262. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
164263. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
164264. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
164265. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
164266. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
164267. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
164268. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
164269. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
164270. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK
164271. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT
164272. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK
164273. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
164274. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__nc_MASK
164275. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__nc__SHIFT
164276. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_nmos_MASK
164277. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_nmos__SHIFT
164278. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_pmos_MASK
164279. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_pmos__SHIFT
164280. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__override_rxdetref_MASK
164281. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT
164282. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
164283. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
164284. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
164285. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
164286. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
164287. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
164288. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
164289. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
164290. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK
164291. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
164292. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
164293. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
164294. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
164295. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
164296. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
164297. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
164298. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
164299. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
164300. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
164301. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
164302. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
164303. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
164304. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
164305. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
164306. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
164307. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
164308. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
164309. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
164310. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
164311. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
164312. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
164313. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
164314. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
164315. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
164316. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
164317. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
164318. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
164319. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
164320. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
164321. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
164322. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK
164323. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
164324. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK
164325. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
164326. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
164327. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
164328. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK
164329. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
164330. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
164331. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
164332. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
164333. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
164334. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK
164335. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
164336. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
164337. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
164338. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
164339. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
164340. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
164341. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
164342. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
164343. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
164344. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
164345. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
164346. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
164347. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
164348. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK
164349. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
164350. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK
164351. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT
164352. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_MASK
164353. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT
164354. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK
164355. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
164356. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
164357. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
164358. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK
164359. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
164360. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK
164361. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
164362. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK
164363. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
164364. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK
164365. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT
164366. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
164367. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
164368. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
164369. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
164370. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
164371. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
164372. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
164373. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
164374. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
164375. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
164376. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
164377. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
164378. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
164379. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
164380. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
164381. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
164382. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
164383. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
164384. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
164385. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
164386. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
164387. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
164388. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
164389. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
164390. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
164391. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
164392. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
164393. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
164394. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
164395. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
164396. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
164397. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
164398. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
164399. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
164400. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
164401. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
164402. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
164403. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
164404. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
164405. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
164406. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
164407. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
164408. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
164409. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
164410. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
164411. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
164412. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
164413. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
164414. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
164415. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
164416. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
164417. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
164418. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
164419. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
164420. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
164421. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
164422. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
164423. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
164424. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
164425. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
164426. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
164427. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
164428. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
164429. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
164430. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
164431. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
164432. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
164433. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
164434. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
164435. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
164436. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
164437. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
164438. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
164439. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
164440. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
164441. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
164442. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
164443. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
164444. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
164445. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
164446. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
164447. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
164448. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
164449. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
164450. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
164451. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
164452. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
164453. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
164454. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
164455. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
164456. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
164457. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
164458. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
164459. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
164460. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
164461. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
164462. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
164463. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
164464. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
164465. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
164466. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
164467. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
164468. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
164469. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
164470. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
164471. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
164472. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
164473. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
164474. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
164475. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
164476. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
164477. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
164478. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
164479. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
164480. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
164481. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
164482. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
164483. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
164484. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
164485. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
164486. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
164487. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
164488. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
164489. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
164490. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
164491. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
164492. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
164493. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
164494. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
164495. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
164496. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
164497. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
164498. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
164499. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
164500. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
164501. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
164502. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
164503. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
164504. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
164505. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
164506. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
164507. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
164508. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
164509. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
164510. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
164511. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
164512. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
164513. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
164514. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
164515. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
164516. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
164517. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
164518. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
164519. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
164520. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
164521. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
164522. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
164523. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
164524. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
164525. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
164526. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
164527. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
164528. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
164529. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
164530. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
164531. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
164532. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
164533. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
164534. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
164535. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
164536. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
164537. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
164538. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
164539. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
164540. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
164541. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
164542. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
164543. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
164544. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
164545. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
164546. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
164547. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
164548. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
164549. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
164550. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
164551. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
164552. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
164553. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
164554. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
164555. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
164556. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
164557. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
164558. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
164559. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
164560. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
164561. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
164562. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
164563. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
164564. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
164565. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
164566. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
164567. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
164568. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
164569. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
164570. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
164571. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
164572. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
164573. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
164574. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
164575. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
164576. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
164577. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
164578. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
164579. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
164580. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
164581. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
164582. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
164583. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
164584. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
164585. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
164586. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
164587. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
164588. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
164589. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
164590. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
164591. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
164592. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
164593. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
164594. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
164595. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
164596. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
164597. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
164598. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
164599. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
164600. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
164601. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
164602. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
164603. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
164604. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
164605. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
164606. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
164607. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
164608. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
164609. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
164610. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK
164611. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
164612. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
164613. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
164614. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
164615. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
164616. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
164617. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
164618. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
164619. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
164620. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
164621. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
164622. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
164623. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
164624. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
164625. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
164626. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
164627. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
164628. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
164629. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
164630. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
164631. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
164632. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
164633. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
164634. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
164635. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
164636. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
164637. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
164638. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
164639. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
164640. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
164641. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
164642. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
164643. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
164644. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
164645. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
164646. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
164647. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
164648. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
164649. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
164650. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
164651. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
164652. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
164653. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
164654. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
164655. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
164656. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
164657. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
164658. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
164659. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
164660. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
164661. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
164662. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
164663. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
164664. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
164665. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
164666. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
164667. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
164668. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
164669. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
164670. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
164671. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
164672. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
164673. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
164674. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
164675. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
164676. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
164677. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
164678. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
164679. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
164680. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
164681. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
164682. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
164683. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
164684. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
164685. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
164686. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
164687. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
164688. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
164689. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
164690. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
164691. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
164692. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
164693. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
164694. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
164695. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
164696. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
164697. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
164698. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
164699. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
164700. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
164701. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
164702. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
164703. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
164704. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
164705. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
164706. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
164707. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
164708. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
164709. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
164710. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
164711. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
164712. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
164713. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
164714. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
164715. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
164716. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
164717. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
164718. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
164719. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
164720. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
164721. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
164722. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
164723. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
164724. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
164725. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
164726. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
164727. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
164728. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
164729. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
164730. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
164731. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
164732. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
164733. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
164734. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
164735. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
164736. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
164737. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
164738. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
164739. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
164740. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
164741. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
164742. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
164743. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
164744. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
164745. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
164746. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
164747. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
164748. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
164749. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
164750. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
164751. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
164752. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
164753. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
164754. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
164755. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
164756. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
164757. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
164758. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
164759. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
164760. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
164761. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
164762. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
164763. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
164764. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
164765. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
164766. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
164767. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
164768. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
164769. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
164770. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
164771. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
164772. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
164773. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
164774. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
164775. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
164776. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
164777. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
164778. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
164779. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
164780. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
164781. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
164782. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
164783. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
164784. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
164785. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
164786. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
164787. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
164788. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
164789. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
164790. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
164791. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
164792. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
164793. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
164794. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
164795. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
164796. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
164797. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
164798. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
164799. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
164800. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
164801. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
164802. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
164803. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
164804. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
164805. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
164806. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
164807. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
164808. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
164809. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
164810. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
164811. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
164812. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
164813. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
164814. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
164815. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
164816. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
164817. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
164818. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
164819. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
164820. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
164821. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
164822. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
164823. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
164824. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
164825. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
164826. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
164827. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
164828. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
164829. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
164830. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
164831. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
164832. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
164833. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
164834. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
164835. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
164836. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
164837. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
164838. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
164839. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
164840. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
164841. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
164842. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
164843. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
164844. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
164845. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
164846. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
164847. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
164848. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
164849. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
164850. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
164851. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
164852. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
164853. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
164854. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
164855. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
164856. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
164857. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
164858. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
164859. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
164860. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
164861. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
164862. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
164863. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
164864. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
164865. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
164866. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
164867. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
164868. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
164869. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
164870. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
164871. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
164872. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
164873. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
164874. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
164875. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
164876. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
164877. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
164878. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
164879. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
164880. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
164881. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
164882. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
164883. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
164884. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
164885. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
164886. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
164887. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
164888. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
164889. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
164890. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
164891. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
164892. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
164893. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
164894. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
164895. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
164896. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
164897. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
164898. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
164899. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
164900. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
164901. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
164902. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
164903. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
164904. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
164905. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
164906. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
164907. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
164908. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
164909. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
164910. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
164911. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
164912. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
164913. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
164914. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
164915. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
164916. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
164917. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
164918. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
164919. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
164920. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
164921. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
164922. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
164923. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
164924. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
164925. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
164926. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
164927. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
164928. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
164929. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
164930. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
164931. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
164932. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
164933. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
164934. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
164935. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
164936. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
164937. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
164938. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
164939. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
164940. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
164941. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
164942. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
164943. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
164944. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
164945. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
164946. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
164947. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
164948. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
164949. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
164950. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
164951. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
164952. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
164953. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
164954. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
164955. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
164956. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
164957. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
164958. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
164959. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
164960. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
164961. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
164962. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
164963. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
164964. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
164965. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
164966. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
164967. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
164968. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
164969. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
164970. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
164971. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
164972. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
164973. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
164974. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
164975. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
164976. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
164977. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
164978. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
164979. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
164980. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
164981. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
164982. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
164983. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
164984. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
164985. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
164986. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
164987. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
164988. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
164989. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
164990. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
164991. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
164992. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
164993. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
164994. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
164995. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
164996. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
164997. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
164998. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
164999. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
165000. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
165001. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
165002. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
165003. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
165004. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
165005. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
165006. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
165007. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
165008. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
165009. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
165010. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
165011. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
165012. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
165013. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
165014. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
165015. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
165016. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
165017. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
165018. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
165019. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
165020. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
165021. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
165022. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
165023. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
165024. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
165025. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
165026. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
165027. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
165028. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
165029. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
165030. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
165031. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
165032. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
165033. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
165034. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
165035. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
165036. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
165037. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
165038. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
165039. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
165040. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
165041. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
165042. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
165043. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
165044. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
165045. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
165046. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
165047. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
165048. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
165049. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
165050. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
165051. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
165052. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
165053. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
165054. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
165055. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
165056. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
165057. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
165058. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
165059. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
165060. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
165061. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
165062. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
165063. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
165064. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
165065. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
165066. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
165067. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
165068. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
165069. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
165070. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
165071. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
165072. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
165073. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
165074. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
165075. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
165076. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
165077. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
165078. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
165079. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
165080. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
165081. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
165082. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
165083. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
165084. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
165085. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
165086. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
165087. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
165088. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
165089. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
165090. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
165091. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
165092. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
165093. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
165094. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
165095. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
165096. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
165097. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
165098. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
165099. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
165100. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
165101. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
165102. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
165103. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
165104. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
165105. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
165106. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
165107. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
165108. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
165109. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
165110. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
165111. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
165112. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
165113. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
165114. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
165115. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
165116. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
165117. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
165118. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
165119. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
165120. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
165121. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
165122. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
165123. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
165124. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
165125. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
165126. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
165127. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
165128. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
165129. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
165130. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
165131. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
165132. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
165133. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
165134. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
165135. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
165136. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
165137. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
165138. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
165139. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
165140. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
165141. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
165142. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
165143. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
165144. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
165145. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
165146. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
165147. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
165148. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
165149. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
165150. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
165151. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
165152. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
165153. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
165154. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
165155. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
165156. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
165157. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
165158. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
165159. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
165160. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
165161. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
165162. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
165163. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
165164. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
165165. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
165166. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK
165167. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT
165168. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK
165169. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT
165170. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
165171. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
165172. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK
165173. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT
165174. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK
165175. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT
165176. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK
165177. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT
165178. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
165179. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
165180. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
165181. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
165182. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
165183. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
165184. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
165185. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
165186. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
165187. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
165188. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
165189. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
165190. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
165191. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
165192. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
165193. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
165194. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
165195. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
165196. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
165197. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
165198. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
165199. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
165200. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
165201. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
165202. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
165203. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
165204. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
165205. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
165206. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
165207. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
165208. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
165209. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
165210. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
165211. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
165212. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
165213. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
165214. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
165215. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
165216. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
165217. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
165218. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
165219. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
165220. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
165221. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
165222. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
165223. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
165224. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
165225. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
165226. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
165227. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
165228. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
165229. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
165230. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
165231. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
165232. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
165233. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
165234. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
165235. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
165236. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
165237. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
165238. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
165239. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
165240. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
165241. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
165242. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
165243. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
165244. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
165245. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
165246. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
165247. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
165248. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
165249. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
165250. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
165251. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
165252. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
165253. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
165254. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
165255. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
165256. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
165257. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
165258. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
165259. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
165260. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
165261. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
165262. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
165263. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
165264. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
165265. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
165266. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
165267. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
165268. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
165269. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
165270. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
165271. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
165272. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
165273. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
165274. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
165275. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
165276. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
165277. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
165278. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
165279. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
165280. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
165281. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
165282. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
165283. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
165284. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
165285. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
165286. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
165287. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
165288. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
165289. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
165290. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
165291. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
165292. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
165293. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
165294. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
165295. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
165296. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
165297. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
165298. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
165299. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
165300. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
165301. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
165302. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
165303. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
165304. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
165305. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
165306. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
165307. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
165308. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
165309. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
165310. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
165311. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
165312. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
165313. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
165314. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
165315. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
165316. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
165317. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
165318. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
165319. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
165320. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
165321. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
165322. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
165323. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
165324. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
165325. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
165326. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
165327. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
165328. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
165329. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
165330. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
165331. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
165332. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
165333. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
165334. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
165335. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
165336. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
165337. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
165338. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
165339. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
165340. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
165341. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
165342. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
165343. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
165344. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
165345. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
165346. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
165347. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
165348. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
165349. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
165350. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
165351. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
165352. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
165353. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
165354. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
165355. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
165356. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
165357. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
165358. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
165359. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
165360. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
165361. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
165362. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
165363. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
165364. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
165365. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
165366. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
165367. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
165368. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
165369. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
165370. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
165371. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
165372. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
165373. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
165374. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
165375. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
165376. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
165377. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
165378. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
165379. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
165380. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
165381. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
165382. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
165383. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
165384. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
165385. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
165386. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
165387. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
165388. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
165389. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
165390. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
165391. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
165392. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
165393. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
165394. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
165395. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
165396. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
165397. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
165398. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
165399. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
165400. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
165401. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
165402. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
165403. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
165404. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
165405. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
165406. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
165407. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
165408. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
165409. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
165410. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
165411. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
165412. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
165413. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
165414. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
165415. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
165416. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
165417. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
165418. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
165419. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
165420. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
165421. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
165422. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
165423. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
165424. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
165425. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
165426. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
165427. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
165428. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
165429. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
165430. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
165431. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
165432. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
165433. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
165434. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
165435. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
165436. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
165437. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
165438. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
165439. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
165440. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
165441. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
165442. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
165443. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
165444. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
165445. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
165446. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
165447. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
165448. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
165449. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
165450. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
165451. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
165452. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
165453. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
165454. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
165455. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
165456. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
165457. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
165458. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
165459. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
165460. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
165461. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
165462. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
165463. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
165464. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
165465. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
165466. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
165467. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
165468. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
165469. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
165470. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
165471. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
165472. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
165473. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
165474. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
165475. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
165476. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
165477. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
165478. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
165479. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
165480. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
165481. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
165482. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
165483. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
165484. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
165485. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
165486. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
165487. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
165488. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
165489. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
165490. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
165491. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
165492. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
165493. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
165494. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
165495. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
165496. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
165497. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
165498. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
165499. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
165500. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
165501. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
165502. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
165503. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
165504. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
165505. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
165506. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
165507. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
165508. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
165509. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
165510. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
165511. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
165512. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
165513. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
165514. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
165515. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
165516. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
165517. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
165518. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
165519. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
165520. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK
165521. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT
165522. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK
165523. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT
165524. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
165525. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
165526. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
165527. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
165528. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
165529. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
165530. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
165531. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
165532. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
165533. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
165534. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
165535. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
165536. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
165537. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
165538. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
165539. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
165540. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
165541. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
165542. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
165543. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
165544. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
165545. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
165546. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
165547. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
165548. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
165549. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
165550. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
165551. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
165552. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
165553. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
165554. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
165555. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
165556. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
165557. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
165558. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
165559. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
165560. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
165561. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
165562. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
165563. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
165564. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
165565. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
165566. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
165567. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
165568. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
165569. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
165570. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
165571. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
165572. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
165573. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
165574. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
165575. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
165576. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
165577. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
165578. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
165579. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
165580. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
165581. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
165582. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
165583. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
165584. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
165585. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
165586. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
165587. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
165588. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
165589. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
165590. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
165591. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
165592. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
165593. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
165594. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
165595. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
165596. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
165597. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
165598. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
165599. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
165600. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
165601. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
165602. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
165603. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
165604. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
165605. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
165606. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
165607. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
165608. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
165609. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
165610. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
165611. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
165612. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
165613. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
165614. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
165615. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
165616. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
165617. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
165618. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
165619. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
165620. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
165621. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
165622. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
165623. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
165624. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
165625. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
165626. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
165627. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
165628. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
165629. DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
165630. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK
165631. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
165632. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK
165633. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT
165634. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK
165635. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
165636. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK
165637. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
165638. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK
165639. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
165640. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK
165641. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
165642. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK
165643. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
165644. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK
165645. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
165646. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK
165647. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
165648. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK
165649. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
165650. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK
165651. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
165652. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK
165653. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
165654. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK
165655. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
165656. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK
165657. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
165658. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK
165659. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
165660. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK
165661. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
165662. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK
165663. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
165664. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK
165665. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
165666. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK
165667. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
165668. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK
165669. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
165670. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK
165671. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
165672. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK
165673. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
165674. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK
165675. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
165676. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK
165677. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
165678. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK
165679. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
165680. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK
165681. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
165682. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK
165683. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
165684. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK
165685. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
165686. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK
165687. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
165688. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK
165689. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
165690. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK
165691. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
165692. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK
165693. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
165694. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK
165695. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
165696. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK
165697. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
165698. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK
165699. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
165700. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK
165701. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
165702. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK
165703. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
165704. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK
165705. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
165706. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK
165707. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
165708. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK
165709. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
165710. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK
165711. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
165712. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK
165713. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
165714. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK
165715. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
165716. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK
165717. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
165718. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK
165719. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
165720. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK
165721. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
165722. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK
165723. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
165724. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK
165725. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
165726. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK
165727. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
165728. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK
165729. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
165730. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK
165731. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
165732. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK
165733. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
165734. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK
165735. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
165736. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK
165737. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
165738. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK
165739. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
165740. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK
165741. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
165742. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK
165743. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
165744. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK
165745. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
165746. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK
165747. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
165748. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK
165749. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
165750. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK
165751. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
165752. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK
165753. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
165754. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK
165755. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
165756. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK
165757. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
165758. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK
165759. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
165760. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK
165761. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
165762. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK
165763. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
165764. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK
165765. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
165766. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK
165767. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
165768. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK
165769. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
165770. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK
165771. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
165772. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK
165773. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
165774. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK
165775. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
165776. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK
165777. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
165778. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK
165779. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
165780. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK
165781. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
165782. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK
165783. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
165784. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK
165785. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
165786. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK
165787. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
165788. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK
165789. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
165790. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK
165791. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
165792. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK
165793. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
165794. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK
165795. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
165796. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK
165797. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
165798. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK
165799. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
165800. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK
165801. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
165802. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK
165803. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
165804. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK
165805. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
165806. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK
165807. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
165808. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK
165809. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
165810. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK
165811. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
165812. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK
165813. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
165814. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK
165815. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
165816. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK
165817. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
165818. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK
165819. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
165820. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK
165821. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
165822. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK
165823. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
165824. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK
165825. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
165826. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK
165827. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
165828. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK
165829. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
165830. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK
165831. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
165832. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK
165833. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
165834. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK
165835. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
165836. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK
165837. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
165838. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK
165839. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
165840. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK
165841. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
165842. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK
165843. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
165844. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK
165845. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
165846. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK
165847. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
165848. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK
165849. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
165850. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK
165851. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
165852. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK
165853. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
165854. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK
165855. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
165856. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK
165857. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
165858. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK
165859. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
165860. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK
165861. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
165862. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK
165863. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
165864. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK
165865. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
165866. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK
165867. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
165868. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK
165869. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
165870. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK
165871. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
165872. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK
165873. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
165874. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK
165875. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
165876. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK
165877. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
165878. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK
165879. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
165880. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK
165881. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
165882. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK
165883. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
165884. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK
165885. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
165886. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK
165887. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
165888. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK
165889. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
165890. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK
165891. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
165892. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK
165893. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
165894. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK
165895. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
165896. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK
165897. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
165898. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK
165899. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
165900. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK
165901. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
165902. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK
165903. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
165904. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK
165905. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
165906. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK
165907. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
165908. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK
165909. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
165910. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK
165911. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
165912. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK
165913. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
165914. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK
165915. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
165916. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK
165917. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
165918. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK
165919. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
165920. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK
165921. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
165922. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK
165923. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
165924. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK
165925. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
165926. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK
165927. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
165928. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK
165929. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
165930. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK
165931. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
165932. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK
165933. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
165934. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK
165935. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
165936. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK
165937. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
165938. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK
165939. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
165940. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK
165941. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
165942. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK
165943. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
165944. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK
165945. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
165946. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK
165947. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
165948. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK
165949. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
165950. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK
165951. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
165952. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK
165953. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
165954. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK
165955. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
165956. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK
165957. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
165958. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK
165959. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
165960. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK
165961. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
165962. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK
165963. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
165964. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK
165965. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
165966. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK
165967. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
165968. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK
165969. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
165970. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK
165971. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
165972. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK
165973. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
165974. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK
165975. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
165976. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK
165977. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
165978. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK
165979. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
165980. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK
165981. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
165982. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK
165983. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
165984. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK
165985. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
165986. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK
165987. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
165988. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK
165989. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
165990. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK
165991. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
165992. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK
165993. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
165994. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK
165995. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
165996. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK
165997. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
165998. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK
165999. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
166000. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK
166001. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
166002. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK
166003. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
166004. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK
166005. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
166006. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK
166007. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
166008. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK
166009. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
166010. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK
166011. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
166012. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK
166013. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
166014. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK
166015. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
166016. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK
166017. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
166018. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK
166019. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
166020. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK
166021. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
166022. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK
166023. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
166024. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK
166025. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
166026. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK
166027. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
166028. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK
166029. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
166030. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK
166031. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
166032. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK
166033. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
166034. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK
166035. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
166036. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK
166037. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
166038. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK
166039. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
166040. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK
166041. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
166042. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK
166043. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
166044. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK
166045. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
166046. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK
166047. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
166048. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK
166049. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
166050. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK
166051. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
166052. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK
166053. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
166054. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK
166055. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
166056. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK
166057. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
166058. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK
166059. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
166060. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK
166061. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
166062. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK
166063. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
166064. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK
166065. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
166066. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK
166067. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
166068. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK
166069. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
166070. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK
166071. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
166072. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK
166073. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
166074. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK
166075. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
166076. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK
166077. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
166078. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK
166079. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
166080. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK
166081. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
166082. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK
166083. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
166084. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK
166085. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
166086. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK
166087. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
166088. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK
166089. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
166090. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK
166091. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
166092. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK
166093. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
166094. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK
166095. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
166096. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK
166097. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
166098. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK
166099. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
166100. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK
166101. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
166102. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK
166103. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
166104. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK
166105. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
166106. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK
166107. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
166108. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK
166109. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
166110. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK
166111. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
166112. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK
166113. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
166114. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK
166115. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
166116. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK
166117. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
166118. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK
166119. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
166120. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK
166121. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
166122. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK
166123. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
166124. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK
166125. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
166126. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK
166127. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
166128. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK
166129. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
166130. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK
166131. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
166132. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK
166133. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
166134. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK
166135. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
166136. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK
166137. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
166138. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK
166139. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
166140. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK
166141. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
166142. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK
166143. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
166144. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK
166145. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
166146. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK
166147. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
166148. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK
166149. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
166150. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK
166151. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
166152. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK
166153. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
166154. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK
166155. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
166156. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK
166157. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
166158. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK
166159. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
166160. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK
166161. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
166162. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK
166163. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
166164. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK
166165. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
166166. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK
166167. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
166168. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK
166169. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
166170. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK
166171. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
166172. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK
166173. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
166174. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK
166175. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
166176. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK
166177. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
166178. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK
166179. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
166180. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK
166181. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
166182. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK
166183. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
166184. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK
166185. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
166186. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK
166187. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
166188. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK
166189. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
166190. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK
166191. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
166192. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK
166193. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
166194. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK
166195. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
166196. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK
166197. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
166198. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK
166199. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
166200. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK
166201. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
166202. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK
166203. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
166204. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK
166205. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
166206. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK
166207. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
166208. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK
166209. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
166210. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK
166211. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
166212. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK
166213. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
166214. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK
166215. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
166216. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK
166217. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
166218. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK
166219. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
166220. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK
166221. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
166222. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK
166223. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
166224. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK
166225. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
166226. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK
166227. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
166228. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK
166229. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
166230. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK
166231. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
166232. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK
166233. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
166234. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK
166235. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
166236. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK
166237. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
166238. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK
166239. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
166240. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK
166241. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
166242. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK
166243. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
166244. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK
166245. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
166246. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK
166247. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
166248. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK
166249. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
166250. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK
166251. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
166252. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK
166253. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
166254. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK
166255. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
166256. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK
166257. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
166258. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK
166259. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
166260. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK
166261. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
166262. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK
166263. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
166264. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK
166265. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
166266. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK
166267. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
166268. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK
166269. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
166270. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK
166271. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
166272. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK
166273. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
166274. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK
166275. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
166276. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK
166277. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
166278. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK
166279. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
166280. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK
166281. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
166282. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK
166283. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
166284. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK
166285. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
166286. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK
166287. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
166288. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK
166289. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
166290. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK
166291. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
166292. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK
166293. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
166294. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK
166295. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
166296. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK
166297. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
166298. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK
166299. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
166300. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK
166301. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
166302. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK
166303. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
166304. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK
166305. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
166306. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK
166307. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
166308. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK
166309. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
166310. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK
166311. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
166312. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK
166313. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
166314. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK
166315. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
166316. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK
166317. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
166318. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK
166319. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
166320. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK
166321. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
166322. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK
166323. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
166324. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK
166325. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
166326. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK
166327. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
166328. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK
166329. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
166330. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK
166331. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
166332. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK
166333. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
166334. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK
166335. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
166336. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK
166337. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
166338. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK
166339. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
166340. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK
166341. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
166342. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK
166343. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
166344. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK
166345. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
166346. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK
166347. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
166348. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK
166349. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
166350. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK
166351. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
166352. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK
166353. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
166354. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK
166355. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
166356. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK
166357. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
166358. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK
166359. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
166360. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK
166361. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
166362. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK
166363. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
166364. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK
166365. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
166366. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK
166367. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
166368. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK
166369. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
166370. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK
166371. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
166372. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK
166373. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
166374. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK
166375. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
166376. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK
166377. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
166378. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK
166379. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
166380. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK
166381. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
166382. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK
166383. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
166384. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK
166385. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
166386. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK
166387. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
166388. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK
166389. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
166390. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK
166391. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
166392. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK
166393. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
166394. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK
166395. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
166396. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK
166397. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
166398. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK
166399. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
166400. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK
166401. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
166402. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK
166403. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
166404. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK
166405. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
166406. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK
166407. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
166408. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK
166409. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
166410. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK
166411. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
166412. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK
166413. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
166414. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK
166415. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
166416. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK
166417. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
166418. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK
166419. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
166420. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK
166421. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
166422. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK
166423. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
166424. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK
166425. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
166426. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK
166427. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
166428. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK
166429. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
166430. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK
166431. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
166432. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK
166433. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
166434. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK
166435. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
166436. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK
166437. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
166438. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK
166439. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
166440. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK
166441. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
166442. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK
166443. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
166444. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK
166445. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
166446. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK
166447. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
166448. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK
166449. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
166450. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK
166451. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
166452. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK
166453. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
166454. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK
166455. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
166456. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK
166457. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
166458. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK
166459. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
166460. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK
166461. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
166462. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK
166463. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
166464. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK
166465. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
166466. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK
166467. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
166468. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK
166469. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
166470. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK
166471. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
166472. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK
166473. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
166474. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK
166475. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
166476. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK
166477. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
166478. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK
166479. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
166480. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK
166481. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
166482. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK
166483. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
166484. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK
166485. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
166486. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK
166487. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
166488. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK
166489. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
166490. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK
166491. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
166492. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK
166493. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
166494. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK
166495. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
166496. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK
166497. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
166498. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK
166499. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
166500. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK
166501. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
166502. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK
166503. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
166504. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK
166505. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
166506. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK
166507. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
166508. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK
166509. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
166510. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK
166511. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
166512. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK
166513. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
166514. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK
166515. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
166516. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK
166517. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
166518. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK
166519. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
166520. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK
166521. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
166522. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK
166523. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
166524. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK
166525. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
166526. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK
166527. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
166528. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK
166529. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
166530. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK
166531. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
166532. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK
166533. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
166534. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK
166535. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
166536. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK
166537. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
166538. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK
166539. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
166540. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK
166541. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
166542. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK
166543. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
166544. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK
166545. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
166546. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK
166547. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
166548. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK
166549. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
166550. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK
166551. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
166552. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK
166553. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
166554. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK
166555. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
166556. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK
166557. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
166558. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK
166559. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
166560. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK
166561. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
166562. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK
166563. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
166564. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK
166565. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
166566. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK
166567. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
166568. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK
166569. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
166570. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK
166571. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
166572. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK
166573. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
166574. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK
166575. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
166576. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK
166577. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
166578. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK
166579. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
166580. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK
166581. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
166582. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK
166583. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
166584. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK
166585. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
166586. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK
166587. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
166588. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK
166589. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
166590. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK
166591. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
166592. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK
166593. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
166594. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK
166595. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
166596. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK
166597. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
166598. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK
166599. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
166600. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK
166601. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
166602. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK
166603. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
166604. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK
166605. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
166606. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK
166607. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
166608. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK
166609. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
166610. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK
166611. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
166612. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK
166613. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
166614. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK
166615. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
166616. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK
166617. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
166618. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK
166619. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
166620. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK
166621. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
166622. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK
166623. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
166624. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK
166625. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
166626. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK
166627. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
166628. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK
166629. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
166630. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK
166631. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
166632. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK
166633. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
166634. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK
166635. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
166636. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK
166637. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
166638. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK
166639. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
166640. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK
166641. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
166642. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK
166643. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
166644. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK
166645. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
166646. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK
166647. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
166648. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK
166649. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
166650. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK
166651. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
166652. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK
166653. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
166654. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK
166655. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
166656. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK
166657. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
166658. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK
166659. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
166660. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK
166661. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
166662. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK
166663. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
166664. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK
166665. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
166666. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK
166667. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
166668. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK
166669. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
166670. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK
166671. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
166672. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK
166673. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
166674. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK
166675. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
166676. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK
166677. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
166678. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK
166679. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
166680. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK
166681. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
166682. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK
166683. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
166684. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK
166685. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
166686. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK
166687. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
166688. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK
166689. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
166690. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK
166691. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
166692. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK
166693. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
166694. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK
166695. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
166696. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK
166697. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
166698. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK
166699. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
166700. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK
166701. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
166702. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK
166703. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
166704. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK
166705. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
166706. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK
166707. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
166708. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK
166709. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
166710. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK
166711. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
166712. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK
166713. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
166714. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK
166715. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
166716. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK
166717. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
166718. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK
166719. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
166720. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK
166721. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
166722. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK
166723. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
166724. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK
166725. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
166726. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK
166727. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
166728. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK
166729. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
166730. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK
166731. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
166732. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK
166733. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
166734. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK
166735. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
166736. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK
166737. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
166738. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK
166739. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
166740. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK
166741. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
166742. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK
166743. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
166744. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK
166745. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
166746. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK
166747. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
166748. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK
166749. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
166750. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK
166751. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
166752. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK
166753. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
166754. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK
166755. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
166756. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK
166757. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
166758. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK
166759. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
166760. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK
166761. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
166762. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK
166763. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
166764. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK
166765. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
166766. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK
166767. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
166768. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK
166769. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
166770. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK
166771. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
166772. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK
166773. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
166774. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK
166775. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
166776. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK
166777. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
166778. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK
166779. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
166780. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK
166781. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
166782. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK
166783. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
166784. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK
166785. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
166786. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK
166787. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
166788. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK
166789. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
166790. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK
166791. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
166792. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK
166793. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
166794. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK
166795. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
166796. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK
166797. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
166798. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK
166799. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
166800. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK
166801. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
166802. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK
166803. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
166804. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK
166805. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
166806. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK
166807. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
166808. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK
166809. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
166810. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK
166811. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
166812. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK
166813. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
166814. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK
166815. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
166816. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK
166817. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
166818. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK
166819. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
166820. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK
166821. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
166822. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK
166823. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
166824. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK
166825. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
166826. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK
166827. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
166828. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK
166829. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
166830. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK
166831. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
166832. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK
166833. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
166834. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK
166835. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
166836. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK
166837. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
166838. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK
166839. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
166840. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK
166841. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
166842. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK
166843. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
166844. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK
166845. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
166846. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK
166847. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
166848. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK
166849. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
166850. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK
166851. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
166852. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK
166853. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
166854. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK
166855. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
166856. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK
166857. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
166858. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK
166859. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
166860. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK
166861. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
166862. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK
166863. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
166864. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK
166865. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
166866. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK
166867. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
166868. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK
166869. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
166870. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK
166871. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
166872. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK
166873. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
166874. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK
166875. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
166876. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK
166877. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
166878. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK
166879. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
166880. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK
166881. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
166882. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK
166883. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
166884. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK
166885. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
166886. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK
166887. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
166888. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK
166889. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
166890. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK
166891. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
166892. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK
166893. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
166894. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK
166895. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
166896. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK
166897. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
166898. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK
166899. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
166900. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK
166901. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
166902. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK
166903. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
166904. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK
166905. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
166906. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK
166907. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
166908. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK
166909. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
166910. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK
166911. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
166912. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK
166913. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
166914. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK
166915. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
166916. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK
166917. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
166918. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK
166919. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
166920. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK
166921. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
166922. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK
166923. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
166924. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK
166925. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
166926. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK
166927. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
166928. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK
166929. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
166930. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK
166931. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
166932. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK
166933. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
166934. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK
166935. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
166936. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK
166937. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
166938. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK
166939. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
166940. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK
166941. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
166942. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK
166943. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
166944. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK
166945. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
166946. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK
166947. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
166948. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK
166949. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
166950. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK
166951. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
166952. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK
166953. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
166954. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK
166955. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
166956. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK
166957. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
166958. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK
166959. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
166960. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK
166961. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
166962. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK
166963. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
166964. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK
166965. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
166966. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK
166967. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
166968. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK
166969. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
166970. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK
166971. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
166972. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK
166973. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
166974. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK
166975. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
166976. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK
166977. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
166978. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK
166979. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
166980. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK
166981. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
166982. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK
166983. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
166984. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK
166985. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
166986. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK
166987. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
166988. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK
166989. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
166990. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK
166991. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
166992. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK
166993. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
166994. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK
166995. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
166996. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK
166997. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
166998. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK
166999. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
167000. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK
167001. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
167002. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK
167003. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
167004. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK
167005. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
167006. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK
167007. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
167008. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK
167009. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
167010. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK
167011. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
167012. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK
167013. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
167014. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK
167015. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
167016. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK
167017. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
167018. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK
167019. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
167020. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK
167021. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
167022. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK
167023. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
167024. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK
167025. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
167026. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK
167027. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
167028. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK
167029. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
167030. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK
167031. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
167032. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK
167033. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
167034. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK
167035. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
167036. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK
167037. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
167038. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK
167039. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
167040. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK
167041. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
167042. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK
167043. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
167044. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK
167045. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
167046. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK
167047. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
167048. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK
167049. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
167050. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK
167051. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
167052. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK
167053. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
167054. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK
167055. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
167056. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK
167057. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
167058. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK
167059. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
167060. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK
167061. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
167062. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK
167063. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
167064. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK
167065. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
167066. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK
167067. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
167068. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK
167069. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
167070. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK
167071. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
167072. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK
167073. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
167074. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK
167075. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
167076. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK
167077. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
167078. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK
167079. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
167080. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK
167081. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
167082. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK
167083. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
167084. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK
167085. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
167086. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK
167087. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
167088. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK
167089. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
167090. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK
167091. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
167092. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK
167093. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
167094. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK
167095. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
167096. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK
167097. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
167098. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK
167099. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
167100. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK
167101. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
167102. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK
167103. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
167104. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK
167105. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
167106. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK
167107. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
167108. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK
167109. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
167110. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK
167111. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
167112. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK
167113. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
167114. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK
167115. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
167116. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK
167117. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
167118. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK
167119. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
167120. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK
167121. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
167122. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK
167123. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
167124. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK
167125. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
167126. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK
167127. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
167128. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK
167129. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
167130. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK
167131. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
167132. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK
167133. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
167134. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK
167135. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
167136. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK
167137. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
167138. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK
167139. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
167140. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK
167141. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
167142. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK
167143. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
167144. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK
167145. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
167146. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK
167147. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
167148. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK
167149. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
167150. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK
167151. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
167152. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK
167153. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
167154. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK
167155. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
167156. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK
167157. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
167158. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK
167159. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
167160. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK
167161. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
167162. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK
167163. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
167164. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK
167165. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
167166. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK
167167. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
167168. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK
167169. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
167170. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK
167171. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
167172. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK
167173. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
167174. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK
167175. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
167176. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK
167177. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
167178. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK
167179. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
167180. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK
167181. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
167182. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK
167183. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
167184. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK
167185. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
167186. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK
167187. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
167188. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK
167189. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
167190. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK
167191. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
167192. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK
167193. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
167194. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK
167195. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
167196. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK
167197. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
167198. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK
167199. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
167200. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK
167201. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
167202. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK
167203. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
167204. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK
167205. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
167206. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK
167207. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
167208. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK
167209. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
167210. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK
167211. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
167212. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK
167213. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
167214. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK
167215. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
167216. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK
167217. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
167218. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK
167219. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
167220. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK
167221. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
167222. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK
167223. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
167224. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK
167225. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
167226. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK
167227. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
167228. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK
167229. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
167230. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK
167231. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
167232. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK
167233. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
167234. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK
167235. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
167236. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK
167237. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
167238. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK
167239. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
167240. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK
167241. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
167242. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK
167243. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
167244. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK
167245. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
167246. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK
167247. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
167248. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK
167249. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
167250. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK
167251. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
167252. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK
167253. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
167254. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK
167255. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
167256. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK
167257. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
167258. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK
167259. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
167260. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK
167261. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
167262. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK
167263. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
167264. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK
167265. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
167266. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK
167267. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
167268. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK
167269. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
167270. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK
167271. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
167272. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK
167273. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
167274. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK
167275. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
167276. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK
167277. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
167278. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK
167279. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
167280. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK
167281. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
167282. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK
167283. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
167284. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK
167285. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
167286. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK
167287. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
167288. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK
167289. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
167290. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK
167291. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
167292. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK
167293. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
167294. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK
167295. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
167296. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK
167297. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
167298. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK
167299. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
167300. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK
167301. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
167302. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK
167303. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
167304. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK
167305. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
167306. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK
167307. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
167308. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK
167309. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
167310. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK
167311. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
167312. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK
167313. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
167314. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK
167315. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
167316. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK
167317. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
167318. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK
167319. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
167320. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK
167321. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
167322. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK
167323. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
167324. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK
167325. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
167326. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK
167327. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
167328. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK
167329. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
167330. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK
167331. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
167332. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK
167333. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
167334. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK
167335. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
167336. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK
167337. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
167338. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK
167339. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
167340. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK
167341. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
167342. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK
167343. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
167344. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK
167345. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
167346. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK
167347. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
167348. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK
167349. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
167350. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK
167351. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
167352. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK
167353. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
167354. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK
167355. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
167356. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK
167357. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
167358. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK
167359. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
167360. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK
167361. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
167362. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK
167363. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
167364. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK
167365. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
167366. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK
167367. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
167368. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK
167369. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
167370. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK
167371. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
167372. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK
167373. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
167374. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK
167375. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
167376. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK
167377. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
167378. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK
167379. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
167380. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK
167381. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
167382. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK
167383. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
167384. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK
167385. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
167386. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK
167387. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
167388. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK
167389. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
167390. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK
167391. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
167392. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK
167393. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
167394. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK
167395. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
167396. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK
167397. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
167398. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK
167399. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
167400. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK
167401. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
167402. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK
167403. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
167404. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK
167405. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
167406. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK
167407. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
167408. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK
167409. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
167410. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK
167411. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
167412. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK
167413. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
167414. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK
167415. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
167416. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK
167417. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
167418. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK
167419. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
167420. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK
167421. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
167422. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK
167423. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
167424. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK
167425. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
167426. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK
167427. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
167428. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK
167429. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
167430. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK
167431. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
167432. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK
167433. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
167434. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK
167435. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
167436. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK
167437. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
167438. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK
167439. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
167440. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK
167441. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
167442. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK
167443. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
167444. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK
167445. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
167446. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK
167447. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
167448. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK
167449. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
167450. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK
167451. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
167452. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK
167453. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
167454. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK
167455. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
167456. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK
167457. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
167458. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK
167459. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
167460. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK
167461. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
167462. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK
167463. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
167464. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK
167465. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
167466. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK
167467. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
167468. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK
167469. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
167470. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK
167471. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
167472. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK
167473. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
167474. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK
167475. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
167476. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK
167477. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
167478. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK
167479. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
167480. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK
167481. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
167482. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK
167483. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
167484. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK
167485. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
167486. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK
167487. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
167488. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK
167489. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
167490. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK
167491. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
167492. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK
167493. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
167494. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK
167495. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
167496. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK
167497. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
167498. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK
167499. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
167500. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK
167501. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
167502. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK
167503. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
167504. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK
167505. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
167506. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK
167507. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
167508. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK
167509. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
167510. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK
167511. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
167512. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK
167513. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
167514. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK
167515. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
167516. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK
167517. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
167518. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK
167519. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
167520. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK
167521. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
167522. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK
167523. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
167524. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK
167525. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
167526. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK
167527. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
167528. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK
167529. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
167530. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK
167531. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
167532. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK
167533. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
167534. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK
167535. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
167536. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK
167537. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
167538. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK
167539. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
167540. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK
167541. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
167542. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK
167543. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
167544. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK
167545. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
167546. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK
167547. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
167548. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK
167549. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
167550. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK
167551. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
167552. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK
167553. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
167554. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK
167555. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
167556. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK
167557. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
167558. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK
167559. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
167560. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK
167561. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
167562. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK
167563. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
167564. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK
167565. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
167566. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK
167567. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
167568. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK
167569. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
167570. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK
167571. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
167572. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK
167573. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
167574. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK
167575. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
167576. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK
167577. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
167578. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK
167579. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
167580. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK
167581. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
167582. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK
167583. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
167584. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK
167585. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
167586. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK
167587. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
167588. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK
167589. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
167590. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK
167591. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
167592. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK
167593. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
167594. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK
167595. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
167596. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK
167597. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
167598. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK
167599. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
167600. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK
167601. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
167602. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK
167603. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
167604. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK
167605. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
167606. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK
167607. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
167608. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK
167609. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
167610. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK
167611. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
167612. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK
167613. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
167614. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK
167615. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
167616. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK
167617. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
167618. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK
167619. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
167620. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK
167621. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
167622. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK
167623. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
167624. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK
167625. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
167626. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK
167627. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
167628. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK
167629. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
167630. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK
167631. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
167632. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK
167633. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
167634. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK
167635. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
167636. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK
167637. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
167638. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK
167639. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
167640. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK
167641. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
167642. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK
167643. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
167644. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK
167645. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
167646. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK
167647. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
167648. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK
167649. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
167650. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK
167651. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
167652. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK
167653. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
167654. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK
167655. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
167656. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK
167657. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
167658. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK
167659. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
167660. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK
167661. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
167662. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK
167663. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
167664. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK
167665. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
167666. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK
167667. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
167668. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK
167669. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
167670. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK
167671. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
167672. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK
167673. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
167674. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK
167675. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
167676. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK
167677. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
167678. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK
167679. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
167680. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK
167681. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
167682. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK
167683. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
167684. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK
167685. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
167686. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK
167687. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
167688. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK
167689. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
167690. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK
167691. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
167692. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK
167693. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
167694. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK
167695. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
167696. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK
167697. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
167698. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK
167699. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
167700. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK
167701. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
167702. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK
167703. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
167704. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK
167705. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
167706. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK
167707. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
167708. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK
167709. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
167710. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK
167711. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
167712. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK
167713. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
167714. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK
167715. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
167716. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK
167717. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
167718. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK
167719. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
167720. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK
167721. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
167722. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK
167723. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
167724. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK
167725. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
167726. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK
167727. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
167728. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK
167729. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
167730. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK
167731. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
167732. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK
167733. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
167734. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK
167735. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
167736. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK
167737. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
167738. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK
167739. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
167740. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK
167741. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
167742. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK
167743. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
167744. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK
167745. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
167746. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK
167747. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
167748. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK
167749. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
167750. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK
167751. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
167752. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK
167753. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
167754. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK
167755. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
167756. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK
167757. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
167758. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK
167759. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
167760. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK
167761. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
167762. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK
167763. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
167764. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK
167765. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
167766. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK
167767. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
167768. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK
167769. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
167770. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK
167771. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
167772. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK
167773. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
167774. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK
167775. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
167776. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK
167777. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
167778. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK
167779. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
167780. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK
167781. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
167782. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK
167783. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
167784. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK
167785. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
167786. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK
167787. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
167788. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK
167789. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
167790. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK
167791. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
167792. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK
167793. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
167794. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK
167795. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
167796. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK
167797. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
167798. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK
167799. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
167800. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK
167801. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
167802. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK
167803. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
167804. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK
167805. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
167806. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK
167807. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
167808. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK
167809. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
167810. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK
167811. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
167812. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK
167813. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
167814. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK
167815. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
167816. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK
167817. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
167818. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK
167819. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
167820. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK
167821. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
167822. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK
167823. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
167824. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK
167825. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
167826. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK
167827. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
167828. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK
167829. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
167830. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK
167831. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
167832. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK
167833. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
167834. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK
167835. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
167836. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK
167837. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
167838. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK
167839. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
167840. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK
167841. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
167842. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK
167843. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
167844. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK
167845. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
167846. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK
167847. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
167848. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK
167849. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
167850. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK
167851. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
167852. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK
167853. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
167854. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK
167855. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
167856. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK
167857. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
167858. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK
167859. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
167860. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK
167861. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
167862. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK
167863. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
167864. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK
167865. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
167866. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK
167867. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
167868. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK
167869. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
167870. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK
167871. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
167872. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK
167873. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
167874. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK
167875. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
167876. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK
167877. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
167878. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK
167879. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
167880. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK
167881. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
167882. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK
167883. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
167884. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK
167885. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
167886. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK
167887. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
167888. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK
167889. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
167890. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK
167891. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
167892. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK
167893. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
167894. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK
167895. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
167896. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK
167897. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
167898. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK
167899. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
167900. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK
167901. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
167902. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK
167903. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
167904. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK
167905. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
167906. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK
167907. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
167908. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK
167909. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
167910. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK
167911. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
167912. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK
167913. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
167914. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK
167915. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
167916. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK
167917. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
167918. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK
167919. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
167920. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK
167921. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
167922. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK
167923. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
167924. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK
167925. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
167926. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK
167927. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
167928. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK
167929. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
167930. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK
167931. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
167932. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK
167933. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
167934. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK
167935. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
167936. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK
167937. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
167938. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK
167939. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
167940. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK
167941. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
167942. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK
167943. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
167944. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK
167945. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
167946. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK
167947. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
167948. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK
167949. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
167950. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK
167951. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
167952. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK
167953. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
167954. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK
167955. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
167956. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK
167957. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
167958. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK
167959. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
167960. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK
167961. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
167962. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK
167963. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
167964. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK
167965. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
167966. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK
167967. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
167968. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK
167969. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
167970. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK
167971. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
167972. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK
167973. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
167974. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK
167975. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
167976. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK
167977. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
167978. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK
167979. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
167980. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK
167981. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
167982. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK
167983. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
167984. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK
167985. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
167986. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK
167987. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
167988. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK
167989. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
167990. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK
167991. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
167992. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK
167993. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
167994. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK
167995. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
167996. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK
167997. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
167998. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK
167999. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
168000. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK
168001. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
168002. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK
168003. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
168004. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK
168005. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
168006. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK
168007. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
168008. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK
168009. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
168010. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK
168011. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
168012. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK
168013. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
168014. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK
168015. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
168016. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK
168017. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
168018. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK
168019. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
168020. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK
168021. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
168022. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK
168023. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
168024. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK
168025. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
168026. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK
168027. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
168028. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK
168029. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
168030. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK
168031. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
168032. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK
168033. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
168034. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK
168035. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
168036. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK
168037. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
168038. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK
168039. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
168040. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK
168041. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
168042. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK
168043. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
168044. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK
168045. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
168046. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK
168047. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
168048. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK
168049. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
168050. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK
168051. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
168052. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK
168053. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
168054. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK
168055. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
168056. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK
168057. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
168058. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK
168059. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
168060. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK
168061. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
168062. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK
168063. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
168064. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK
168065. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
168066. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK
168067. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
168068. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK
168069. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
168070. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK
168071. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
168072. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK
168073. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
168074. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK
168075. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
168076. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK
168077. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
168078. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK
168079. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
168080. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK
168081. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
168082. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK
168083. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
168084. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK
168085. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
168086. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK
168087. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
168088. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK
168089. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
168090. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK
168091. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
168092. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK
168093. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
168094. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK
168095. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
168096. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK
168097. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
168098. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK
168099. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
168100. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK
168101. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
168102. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK
168103. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
168104. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK
168105. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
168106. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK
168107. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
168108. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK
168109. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
168110. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK
168111. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
168112. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK
168113. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
168114. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK
168115. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
168116. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK
168117. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
168118. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK
168119. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
168120. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK
168121. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
168122. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK
168123. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
168124. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK
168125. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
168126. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK
168127. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
168128. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK
168129. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
168130. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
168131. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
168132. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
168133. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
168134. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
168135. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
168136. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
168137. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
168138. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
168139. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
168140. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
168141. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
168142. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
168143. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
168144. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
168145. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
168146. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
168147. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
168148. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
168149. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
168150. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
168151. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
168152. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
168153. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
168154. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
168155. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
168156. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
168157. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
168158. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
168159. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
168160. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
168161. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
168162. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
168163. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
168164. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
168165. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
168166. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
168167. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
168168. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
168169. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
168170. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK
168171. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
168172. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK
168173. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT
168174. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK
168175. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
168176. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK
168177. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
168178. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK
168179. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
168180. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK
168181. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
168182. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK
168183. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
168184. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK
168185. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
168186. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK
168187. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
168188. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK
168189. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
168190. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK
168191. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
168192. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK
168193. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
168194. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK
168195. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
168196. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK
168197. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
168198. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK
168199. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
168200. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK
168201. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
168202. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK
168203. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
168204. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK
168205. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
168206. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK
168207. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
168208. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK
168209. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
168210. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK
168211. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
168212. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK
168213. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
168214. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK
168215. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
168216. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK
168217. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
168218. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK
168219. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
168220. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK
168221. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
168222. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK
168223. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
168224. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK
168225. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
168226. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK
168227. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
168228. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK
168229. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
168230. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK
168231. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
168232. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK
168233. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
168234. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK
168235. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
168236. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK
168237. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
168238. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK
168239. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
168240. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK
168241. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
168242. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK
168243. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
168244. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK
168245. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
168246. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK
168247. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
168248. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK
168249. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
168250. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK
168251. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
168252. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK
168253. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
168254. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK
168255. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
168256. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK
168257. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
168258. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK
168259. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
168260. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK
168261. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
168262. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK
168263. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
168264. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK
168265. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
168266. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK
168267. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
168268. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK
168269. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
168270. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK
168271. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
168272. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK
168273. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
168274. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK
168275. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
168276. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK
168277. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
168278. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK
168279. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
168280. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK
168281. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
168282. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK
168283. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
168284. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK
168285. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
168286. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK
168287. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
168288. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK
168289. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
168290. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK
168291. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
168292. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK
168293. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
168294. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK
168295. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
168296. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK
168297. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
168298. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK
168299. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
168300. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK
168301. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
168302. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK
168303. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
168304. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK
168305. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
168306. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK
168307. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
168308. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK
168309. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
168310. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK
168311. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
168312. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK
168313. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
168314. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK
168315. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
168316. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK
168317. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
168318. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK
168319. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
168320. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK
168321. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
168322. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK
168323. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
168324. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK
168325. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
168326. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK
168327. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
168328. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK
168329. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
168330. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK
168331. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
168332. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK
168333. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
168334. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK
168335. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
168336. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK
168337. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
168338. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK
168339. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
168340. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK
168341. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
168342. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK
168343. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
168344. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK
168345. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
168346. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK
168347. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
168348. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK
168349. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
168350. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK
168351. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
168352. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK
168353. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
168354. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK
168355. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
168356. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK
168357. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
168358. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK
168359. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
168360. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK
168361. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
168362. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK
168363. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
168364. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK
168365. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
168366. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK
168367. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
168368. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK
168369. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
168370. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK
168371. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
168372. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK
168373. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
168374. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK
168375. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
168376. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK
168377. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
168378. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK
168379. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
168380. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK
168381. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
168382. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK
168383. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
168384. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK
168385. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
168386. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK
168387. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
168388. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK
168389. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
168390. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK
168391. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
168392. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK
168393. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
168394. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK
168395. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
168396. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK
168397. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
168398. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK
168399. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
168400. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK
168401. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
168402. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK
168403. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
168404. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK
168405. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
168406. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK
168407. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
168408. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK
168409. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
168410. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK
168411. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
168412. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK
168413. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
168414. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK
168415. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
168416. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK
168417. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
168418. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK
168419. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
168420. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK
168421. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
168422. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK
168423. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
168424. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK
168425. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
168426. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK
168427. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
168428. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK
168429. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
168430. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK
168431. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
168432. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK
168433. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
168434. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK
168435. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
168436. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK
168437. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
168438. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK
168439. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
168440. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK
168441. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
168442. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK
168443. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
168444. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK
168445. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
168446. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK
168447. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
168448. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK
168449. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
168450. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK
168451. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
168452. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK
168453. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
168454. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK
168455. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
168456. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK
168457. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
168458. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK
168459. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
168460. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK
168461. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
168462. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK
168463. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
168464. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK
168465. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
168466. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK
168467. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
168468. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK
168469. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
168470. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK
168471. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
168472. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK
168473. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
168474. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK
168475. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
168476. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK
168477. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
168478. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK
168479. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
168480. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK
168481. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
168482. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK
168483. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
168484. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK
168485. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
168486. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK
168487. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
168488. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK
168489. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
168490. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK
168491. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
168492. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK
168493. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
168494. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK
168495. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
168496. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK
168497. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
168498. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK
168499. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
168500. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK
168501. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
168502. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK
168503. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
168504. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK
168505. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
168506. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK
168507. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
168508. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK
168509. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
168510. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK
168511. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
168512. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK
168513. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
168514. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK
168515. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
168516. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK
168517. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
168518. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK
168519. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
168520. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK
168521. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
168522. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK
168523. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
168524. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK
168525. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
168526. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK
168527. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
168528. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK
168529. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
168530. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK
168531. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
168532. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK
168533. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
168534. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK
168535. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
168536. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK
168537. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
168538. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK
168539. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
168540. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK
168541. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
168542. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK
168543. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
168544. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK
168545. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
168546. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK
168547. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
168548. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK
168549. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
168550. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK
168551. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
168552. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK
168553. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
168554. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK
168555. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
168556. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK
168557. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
168558. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK
168559. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
168560. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK
168561. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
168562. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK
168563. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
168564. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK
168565. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
168566. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK
168567. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
168568. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK
168569. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
168570. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK
168571. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
168572. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK
168573. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
168574. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK
168575. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
168576. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK
168577. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
168578. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK
168579. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
168580. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK
168581. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
168582. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK
168583. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
168584. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK
168585. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
168586. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK
168587. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
168588. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK
168589. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
168590. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK
168591. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
168592. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK
168593. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
168594. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK
168595. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
168596. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK
168597. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
168598. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK
168599. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
168600. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK
168601. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
168602. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK
168603. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
168604. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK
168605. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
168606. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK
168607. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
168608. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK
168609. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
168610. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK
168611. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
168612. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK
168613. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
168614. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK
168615. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
168616. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK
168617. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
168618. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK
168619. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
168620. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK
168621. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
168622. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK
168623. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
168624. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK
168625. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
168626. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK
168627. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
168628. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK
168629. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
168630. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK
168631. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
168632. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK
168633. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
168634. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK
168635. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
168636. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK
168637. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
168638. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK
168639. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
168640. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK
168641. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
168642. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK
168643. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
168644. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK
168645. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
168646. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK
168647. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
168648. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK
168649. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
168650. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK
168651. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
168652. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK
168653. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
168654. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK
168655. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
168656. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK
168657. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
168658. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK
168659. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
168660. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK
168661. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
168662. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK
168663. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
168664. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK
168665. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
168666. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK
168667. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
168668. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK
168669. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
168670. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK
168671. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
168672. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK
168673. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
168674. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK
168675. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
168676. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK
168677. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
168678. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK
168679. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
168680. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK
168681. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
168682. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK
168683. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
168684. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK
168685. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
168686. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK
168687. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
168688. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK
168689. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
168690. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK
168691. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
168692. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK
168693. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
168694. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK
168695. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
168696. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK
168697. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
168698. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK
168699. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
168700. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK
168701. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
168702. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK
168703. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
168704. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK
168705. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
168706. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK
168707. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
168708. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK
168709. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
168710. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK
168711. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
168712. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK
168713. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
168714. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK
168715. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
168716. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK
168717. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
168718. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK
168719. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
168720. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK
168721. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
168722. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK
168723. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
168724. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK
168725. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
168726. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK
168727. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
168728. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK
168729. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
168730. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK
168731. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
168732. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK
168733. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
168734. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK
168735. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
168736. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK
168737. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
168738. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK
168739. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
168740. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK
168741. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
168742. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK
168743. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
168744. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK
168745. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
168746. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK
168747. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
168748. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK
168749. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
168750. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK
168751. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
168752. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK
168753. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
168754. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK
168755. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
168756. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK
168757. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
168758. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK
168759. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
168760. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK
168761. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
168762. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK
168763. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
168764. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK
168765. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
168766. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK
168767. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
168768. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK
168769. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
168770. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK
168771. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
168772. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK
168773. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
168774. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK
168775. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
168776. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK
168777. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
168778. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK
168779. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
168780. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK
168781. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
168782. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK
168783. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
168784. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK
168785. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
168786. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK
168787. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
168788. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK
168789. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
168790. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK
168791. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
168792. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK
168793. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
168794. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK
168795. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
168796. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK
168797. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
168798. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK
168799. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
168800. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK
168801. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
168802. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK
168803. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
168804. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK
168805. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
168806. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK
168807. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
168808. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK
168809. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
168810. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK
168811. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
168812. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK
168813. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
168814. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK
168815. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
168816. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK
168817. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
168818. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK
168819. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
168820. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK
168821. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
168822. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK
168823. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
168824. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK
168825. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
168826. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK
168827. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
168828. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK
168829. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
168830. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK
168831. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
168832. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK
168833. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
168834. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK
168835. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
168836. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK
168837. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
168838. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK
168839. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
168840. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK
168841. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
168842. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK
168843. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
168844. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK
168845. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
168846. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK
168847. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
168848. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK
168849. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
168850. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK
168851. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
168852. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK
168853. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
168854. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK
168855. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
168856. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK
168857. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
168858. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK
168859. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
168860. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK
168861. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
168862. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK
168863. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
168864. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK
168865. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
168866. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK
168867. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
168868. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK
168869. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
168870. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK
168871. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
168872. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK
168873. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
168874. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK
168875. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
168876. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK
168877. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
168878. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK
168879. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
168880. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK
168881. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
168882. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK
168883. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
168884. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK
168885. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
168886. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK
168887. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
168888. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK
168889. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
168890. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK
168891. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
168892. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK
168893. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
168894. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK
168895. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
168896. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK
168897. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
168898. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK
168899. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
168900. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK
168901. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
168902. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK
168903. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
168904. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK
168905. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
168906. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK
168907. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
168908. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK
168909. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
168910. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK
168911. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
168912. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK
168913. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
168914. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK
168915. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
168916. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK
168917. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
168918. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK
168919. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
168920. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK
168921. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
168922. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK
168923. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
168924. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK
168925. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
168926. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK
168927. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
168928. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK
168929. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
168930. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK
168931. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
168932. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK
168933. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
168934. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK
168935. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
168936. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK
168937. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
168938. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK
168939. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
168940. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK
168941. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
168942. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK
168943. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
168944. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK
168945. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
168946. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK
168947. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
168948. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK
168949. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
168950. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK
168951. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
168952. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK
168953. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
168954. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK
168955. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
168956. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK
168957. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
168958. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK
168959. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
168960. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK
168961. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
168962. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK
168963. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
168964. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK
168965. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
168966. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK
168967. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
168968. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK
168969. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
168970. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK
168971. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
168972. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK
168973. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
168974. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK
168975. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
168976. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK
168977. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
168978. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK
168979. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
168980. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK
168981. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
168982. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK
168983. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
168984. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK
168985. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
168986. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK
168987. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
168988. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK
168989. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
168990. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK
168991. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
168992. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK
168993. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
168994. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK
168995. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
168996. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK
168997. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
168998. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK
168999. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
169000. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK
169001. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
169002. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK
169003. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
169004. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK
169005. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
169006. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK
169007. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
169008. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK
169009. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
169010. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK
169011. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
169012. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK
169013. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
169014. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK
169015. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
169016. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK
169017. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
169018. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK
169019. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
169020. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK
169021. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
169022. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK
169023. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
169024. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK
169025. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
169026. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK
169027. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
169028. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK
169029. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
169030. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK
169031. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
169032. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK
169033. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
169034. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK
169035. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
169036. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK
169037. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
169038. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK
169039. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
169040. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK
169041. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
169042. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK
169043. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
169044. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK
169045. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
169046. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK
169047. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
169048. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK
169049. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
169050. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK
169051. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
169052. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK
169053. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
169054. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK
169055. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
169056. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK
169057. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
169058. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK
169059. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
169060. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK
169061. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
169062. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK
169063. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
169064. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK
169065. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
169066. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK
169067. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
169068. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK
169069. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
169070. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK
169071. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
169072. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK
169073. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
169074. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK
169075. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
169076. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK
169077. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
169078. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK
169079. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
169080. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK
169081. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
169082. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK
169083. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
169084. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK
169085. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
169086. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK
169087. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
169088. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK
169089. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
169090. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK
169091. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
169092. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK
169093. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
169094. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK
169095. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
169096. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK
169097. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
169098. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK
169099. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
169100. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK
169101. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
169102. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK
169103. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
169104. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK
169105. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
169106. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK
169107. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
169108. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK
169109. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
169110. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK
169111. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
169112. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK
169113. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
169114. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK
169115. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
169116. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK
169117. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
169118. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK
169119. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
169120. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK
169121. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
169122. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK
169123. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
169124. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK
169125. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
169126. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK
169127. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
169128. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK
169129. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
169130. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK
169131. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
169132. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK
169133. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
169134. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK
169135. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
169136. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK
169137. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
169138. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK
169139. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
169140. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK
169141. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
169142. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK
169143. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
169144. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK
169145. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
169146. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK
169147. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
169148. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK
169149. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
169150. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK
169151. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
169152. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK
169153. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
169154. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK
169155. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
169156. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK
169157. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
169158. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK
169159. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
169160. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK
169161. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
169162. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK
169163. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
169164. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK
169165. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
169166. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK
169167. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
169168. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK
169169. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
169170. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK
169171. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
169172. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK
169173. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
169174. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK
169175. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
169176. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK
169177. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
169178. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK
169179. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
169180. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK
169181. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
169182. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK
169183. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
169184. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK
169185. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
169186. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK
169187. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
169188. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK
169189. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
169190. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK
169191. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
169192. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK
169193. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
169194. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK
169195. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
169196. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK
169197. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
169198. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK
169199. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
169200. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK
169201. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
169202. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK
169203. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
169204. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK
169205. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
169206. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK
169207. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
169208. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK
169209. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
169210. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK
169211. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
169212. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK
169213. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
169214. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK
169215. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
169216. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK
169217. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
169218. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK
169219. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
169220. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK
169221. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
169222. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK
169223. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
169224. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK
169225. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
169226. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK
169227. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
169228. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK
169229. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
169230. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK
169231. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
169232. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK
169233. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
169234. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK
169235. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
169236. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK
169237. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
169238. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK
169239. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
169240. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK
169241. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
169242. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK
169243. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
169244. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK
169245. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
169246. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK
169247. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
169248. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK
169249. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
169250. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK
169251. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
169252. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK
169253. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
169254. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK
169255. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
169256. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK
169257. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
169258. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK
169259. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
169260. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK
169261. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
169262. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK
169263. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
169264. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK
169265. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
169266. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK
169267. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
169268. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK
169269. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
169270. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK
169271. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
169272. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK
169273. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
169274. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK
169275. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
169276. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK
169277. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
169278. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK
169279. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
169280. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK
169281. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
169282. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK
169283. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
169284. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK
169285. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
169286. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK
169287. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
169288. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK
169289. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
169290. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK
169291. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
169292. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK
169293. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
169294. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK
169295. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
169296. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK
169297. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
169298. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK
169299. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
169300. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK
169301. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
169302. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK
169303. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
169304. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK
169305. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
169306. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK
169307. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
169308. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK
169309. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
169310. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK
169311. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
169312. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK
169313. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
169314. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK
169315. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
169316. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK
169317. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
169318. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK
169319. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
169320. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK
169321. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
169322. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK
169323. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
169324. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK
169325. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
169326. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK
169327. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
169328. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK
169329. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
169330. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK
169331. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
169332. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK
169333. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
169334. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK
169335. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
169336. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK
169337. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
169338. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK
169339. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
169340. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK
169341. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
169342. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK
169343. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
169344. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK
169345. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
169346. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK
169347. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
169348. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK
169349. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
169350. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK
169351. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
169352. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK
169353. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
169354. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK
169355. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
169356. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK
169357. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
169358. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK
169359. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
169360. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK
169361. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
169362. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK
169363. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
169364. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK
169365. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
169366. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK
169367. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
169368. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK
169369. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
169370. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK
169371. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
169372. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK
169373. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
169374. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK
169375. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
169376. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK
169377. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
169378. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK
169379. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
169380. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK
169381. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
169382. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK
169383. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
169384. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK
169385. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
169386. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK
169387. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
169388. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK
169389. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
169390. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK
169391. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
169392. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK
169393. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
169394. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK
169395. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
169396. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK
169397. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
169398. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK
169399. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
169400. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK
169401. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
169402. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK
169403. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
169404. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK
169405. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
169406. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK
169407. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
169408. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK
169409. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
169410. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK
169411. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
169412. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK
169413. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
169414. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK
169415. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
169416. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK
169417. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
169418. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK
169419. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
169420. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK
169421. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
169422. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK
169423. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
169424. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK
169425. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
169426. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK
169427. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
169428. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK
169429. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
169430. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK
169431. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
169432. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK
169433. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
169434. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK
169435. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
169436. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK
169437. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
169438. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK
169439. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
169440. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK
169441. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
169442. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK
169443. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
169444. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK
169445. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
169446. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK
169447. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
169448. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK
169449. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
169450. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK
169451. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
169452. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK
169453. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
169454. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK
169455. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
169456. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK
169457. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
169458. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK
169459. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
169460. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK
169461. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
169462. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK
169463. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
169464. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK
169465. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
169466. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK
169467. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
169468. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK
169469. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
169470. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK
169471. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
169472. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK
169473. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
169474. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK
169475. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
169476. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK
169477. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
169478. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK
169479. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
169480. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK
169481. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
169482. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK
169483. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
169484. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK
169485. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
169486. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK
169487. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
169488. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK
169489. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
169490. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK
169491. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
169492. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK
169493. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
169494. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK
169495. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
169496. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK
169497. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
169498. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK
169499. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
169500. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK
169501. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
169502. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK
169503. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
169504. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK
169505. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
169506. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK
169507. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
169508. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK
169509. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
169510. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK
169511. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
169512. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK
169513. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
169514. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK
169515. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
169516. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK
169517. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
169518. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK
169519. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
169520. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK
169521. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
169522. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK
169523. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
169524. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK
169525. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
169526. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK
169527. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
169528. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK
169529. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
169530. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK
169531. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
169532. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK
169533. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
169534. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK
169535. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
169536. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK
169537. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
169538. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK
169539. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
169540. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK
169541. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
169542. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK
169543. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
169544. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK
169545. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
169546. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK
169547. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
169548. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK
169549. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
169550. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK
169551. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
169552. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK
169553. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
169554. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK
169555. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
169556. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK
169557. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
169558. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK
169559. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
169560. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK
169561. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
169562. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK
169563. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
169564. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK
169565. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
169566. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK
169567. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
169568. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK
169569. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
169570. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK
169571. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
169572. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK
169573. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
169574. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK
169575. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
169576. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK
169577. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
169578. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK
169579. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
169580. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK
169581. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
169582. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK
169583. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
169584. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK
169585. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
169586. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK
169587. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
169588. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK
169589. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
169590. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK
169591. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
169592. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK
169593. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
169594. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK
169595. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
169596. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK
169597. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
169598. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK
169599. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
169600. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK
169601. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
169602. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK
169603. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
169604. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK
169605. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
169606. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK
169607. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
169608. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK
169609. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
169610. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK
169611. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
169612. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK
169613. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
169614. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK
169615. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
169616. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK
169617. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
169618. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK
169619. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
169620. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK
169621. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
169622. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK
169623. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
169624. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK
169625. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
169626. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK
169627. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
169628. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK
169629. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
169630. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK
169631. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
169632. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK
169633. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
169634. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK
169635. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
169636. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK
169637. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
169638. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK
169639. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
169640. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK
169641. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
169642. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK
169643. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
169644. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK
169645. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
169646. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK
169647. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
169648. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK
169649. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
169650. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK
169651. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
169652. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK
169653. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
169654. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK
169655. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
169656. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK
169657. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
169658. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK
169659. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
169660. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK
169661. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
169662. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK
169663. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
169664. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK
169665. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
169666. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK
169667. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
169668. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK
169669. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
169670. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK
169671. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
169672. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK
169673. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
169674. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK
169675. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
169676. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK
169677. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
169678. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK
169679. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
169680. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK
169681. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
169682. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK
169683. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
169684. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK
169685. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
169686. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK
169687. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
169688. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK
169689. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
169690. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK
169691. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
169692. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK
169693. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
169694. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK
169695. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
169696. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK
169697. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
169698. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK
169699. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
169700. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK
169701. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
169702. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK
169703. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
169704. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK
169705. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
169706. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK
169707. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
169708. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK
169709. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
169710. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK
169711. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
169712. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK
169713. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
169714. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK
169715. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
169716. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK
169717. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
169718. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK
169719. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
169720. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK
169721. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
169722. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK
169723. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
169724. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK
169725. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
169726. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK
169727. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
169728. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK
169729. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
169730. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK
169731. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
169732. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK
169733. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
169734. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK
169735. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
169736. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK
169737. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
169738. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK
169739. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
169740. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK
169741. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
169742. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK
169743. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
169744. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK
169745. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
169746. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK
169747. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
169748. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK
169749. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
169750. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK
169751. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
169752. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK
169753. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
169754. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK
169755. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
169756. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK
169757. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
169758. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK
169759. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
169760. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK
169761. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
169762. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK
169763. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
169764. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK
169765. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
169766. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK
169767. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
169768. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK
169769. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
169770. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK
169771. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
169772. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK
169773. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
169774. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK
169775. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
169776. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK
169777. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
169778. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK
169779. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
169780. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK
169781. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
169782. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK
169783. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
169784. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK
169785. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
169786. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK
169787. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
169788. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK
169789. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
169790. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK
169791. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
169792. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK
169793. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
169794. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK
169795. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
169796. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK
169797. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
169798. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK
169799. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
169800. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK
169801. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
169802. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK
169803. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
169804. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK
169805. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
169806. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK
169807. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
169808. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK
169809. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
169810. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK
169811. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
169812. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK
169813. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
169814. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK
169815. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
169816. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK
169817. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
169818. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK
169819. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
169820. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK
169821. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
169822. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK
169823. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
169824. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK
169825. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
169826. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK
169827. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
169828. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK
169829. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
169830. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK
169831. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
169832. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK
169833. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
169834. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK
169835. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
169836. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK
169837. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
169838. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK
169839. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
169840. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK
169841. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
169842. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK
169843. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
169844. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK
169845. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
169846. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK
169847. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
169848. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK
169849. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
169850. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK
169851. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
169852. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK
169853. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
169854. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK
169855. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
169856. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK
169857. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
169858. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK
169859. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
169860. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK
169861. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
169862. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK
169863. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
169864. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK
169865. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
169866. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK
169867. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
169868. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK
169869. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
169870. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK
169871. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
169872. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK
169873. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
169874. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK
169875. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
169876. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK
169877. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
169878. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK
169879. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
169880. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK
169881. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
169882. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK
169883. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
169884. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK
169885. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
169886. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK
169887. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
169888. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK
169889. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
169890. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK
169891. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
169892. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK
169893. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
169894. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK
169895. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
169896. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK
169897. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
169898. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK
169899. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
169900. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK
169901. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
169902. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK
169903. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
169904. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK
169905. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
169906. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK
169907. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
169908. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK
169909. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
169910. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK
169911. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
169912. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK
169913. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
169914. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK
169915. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
169916. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK
169917. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
169918. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK
169919. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
169920. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK
169921. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
169922. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK
169923. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
169924. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK
169925. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
169926. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK
169927. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
169928. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK
169929. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
169930. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK
169931. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
169932. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK
169933. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
169934. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK
169935. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
169936. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK
169937. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
169938. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK
169939. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
169940. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK
169941. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
169942. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK
169943. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
169944. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK
169945. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
169946. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK
169947. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
169948. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK
169949. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
169950. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK
169951. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
169952. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK
169953. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
169954. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK
169955. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
169956. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK
169957. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
169958. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK
169959. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
169960. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK
169961. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
169962. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK
169963. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
169964. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK
169965. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
169966. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK
169967. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
169968. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK
169969. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
169970. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK
169971. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
169972. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK
169973. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
169974. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK
169975. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
169976. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK
169977. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
169978. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK
169979. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
169980. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK
169981. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
169982. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK
169983. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
169984. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK
169985. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
169986. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK
169987. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
169988. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK
169989. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
169990. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK
169991. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
169992. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK
169993. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
169994. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK
169995. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
169996. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK
169997. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
169998. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK
169999. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
170000. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK
170001. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
170002. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK
170003. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
170004. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK
170005. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
170006. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK
170007. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
170008. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK
170009. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
170010. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK
170011. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
170012. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK
170013. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
170014. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK
170015. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
170016. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK
170017. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
170018. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK
170019. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
170020. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK
170021. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
170022. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK
170023. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
170024. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK
170025. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
170026. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK
170027. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
170028. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK
170029. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
170030. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK
170031. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
170032. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK
170033. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
170034. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK
170035. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
170036. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK
170037. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
170038. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK
170039. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
170040. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK
170041. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
170042. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK
170043. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
170044. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK
170045. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
170046. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK
170047. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
170048. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK
170049. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
170050. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK
170051. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
170052. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK
170053. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
170054. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK
170055. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
170056. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK
170057. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
170058. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK
170059. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
170060. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK
170061. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
170062. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK
170063. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
170064. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK
170065. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
170066. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK
170067. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
170068. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK
170069. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
170070. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK
170071. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
170072. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK
170073. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
170074. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK
170075. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
170076. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK
170077. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
170078. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK
170079. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
170080. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK
170081. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
170082. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK
170083. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
170084. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK
170085. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
170086. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK
170087. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
170088. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK
170089. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
170090. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK
170091. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
170092. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK
170093. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
170094. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK
170095. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
170096. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK
170097. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
170098. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK
170099. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
170100. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK
170101. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
170102. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK
170103. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
170104. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK
170105. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
170106. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK
170107. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
170108. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK
170109. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
170110. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK
170111. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
170112. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK
170113. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
170114. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK
170115. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
170116. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK
170117. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
170118. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK
170119. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
170120. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK
170121. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
170122. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK
170123. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
170124. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK
170125. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
170126. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK
170127. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
170128. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK
170129. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
170130. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK
170131. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
170132. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK
170133. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
170134. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK
170135. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
170136. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK
170137. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
170138. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK
170139. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
170140. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK
170141. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
170142. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK
170143. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
170144. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK
170145. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
170146. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK
170147. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
170148. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK
170149. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
170150. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK
170151. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
170152. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK
170153. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
170154. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK
170155. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
170156. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK
170157. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
170158. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK
170159. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
170160. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK
170161. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
170162. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK
170163. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
170164. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK
170165. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
170166. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK
170167. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
170168. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK
170169. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
170170. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK
170171. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
170172. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK
170173. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
170174. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK
170175. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
170176. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK
170177. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
170178. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK
170179. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
170180. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK
170181. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
170182. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK
170183. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
170184. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK
170185. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
170186. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK
170187. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
170188. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK
170189. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
170190. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK
170191. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
170192. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK
170193. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
170194. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK
170195. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
170196. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK
170197. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
170198. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK
170199. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
170200. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK
170201. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
170202. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK
170203. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
170204. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK
170205. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
170206. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK
170207. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
170208. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK
170209. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
170210. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK
170211. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
170212. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK
170213. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
170214. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK
170215. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
170216. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK
170217. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
170218. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK
170219. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
170220. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK
170221. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
170222. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK
170223. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
170224. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK
170225. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
170226. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK
170227. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
170228. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK
170229. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
170230. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK
170231. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
170232. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK
170233. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
170234. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK
170235. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
170236. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK
170237. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
170238. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK
170239. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
170240. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK
170241. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
170242. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK
170243. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
170244. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK
170245. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
170246. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK
170247. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
170248. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK
170249. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
170250. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK
170251. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
170252. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK
170253. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
170254. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK
170255. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
170256. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK
170257. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
170258. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK
170259. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
170260. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK
170261. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
170262. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK
170263. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
170264. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK
170265. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
170266. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK
170267. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
170268. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK
170269. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
170270. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK
170271. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
170272. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK
170273. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
170274. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK
170275. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
170276. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK
170277. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
170278. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK
170279. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
170280. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK
170281. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
170282. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK
170283. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
170284. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK
170285. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
170286. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK
170287. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
170288. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK
170289. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
170290. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK
170291. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
170292. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK
170293. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
170294. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK
170295. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
170296. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK
170297. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
170298. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK
170299. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
170300. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK
170301. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
170302. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK
170303. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
170304. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK
170305. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
170306. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK
170307. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
170308. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK
170309. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
170310. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK
170311. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
170312. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK
170313. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
170314. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK
170315. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
170316. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK
170317. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
170318. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK
170319. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
170320. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK
170321. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
170322. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK
170323. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
170324. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK
170325. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
170326. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK
170327. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
170328. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK
170329. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
170330. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK
170331. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
170332. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK
170333. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
170334. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK
170335. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
170336. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK
170337. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
170338. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK
170339. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
170340. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK
170341. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
170342. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK
170343. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
170344. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK
170345. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
170346. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK
170347. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
170348. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK
170349. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
170350. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK
170351. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
170352. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK
170353. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
170354. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK
170355. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
170356. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK
170357. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
170358. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK
170359. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
170360. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK
170361. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
170362. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK
170363. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
170364. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK
170365. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
170366. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK
170367. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
170368. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK
170369. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
170370. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK
170371. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
170372. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK
170373. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
170374. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK
170375. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
170376. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK
170377. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
170378. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK
170379. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
170380. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK
170381. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
170382. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK
170383. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
170384. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK
170385. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
170386. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK
170387. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
170388. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK
170389. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
170390. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK
170391. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
170392. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK
170393. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
170394. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK
170395. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
170396. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK
170397. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
170398. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK
170399. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
170400. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK
170401. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
170402. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK
170403. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
170404. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK
170405. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
170406. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK
170407. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
170408. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK
170409. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
170410. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK
170411. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
170412. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK
170413. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
170414. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK
170415. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
170416. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK
170417. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
170418. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK
170419. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
170420. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK
170421. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
170422. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK
170423. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
170424. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK
170425. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
170426. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK
170427. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
170428. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK
170429. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
170430. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK
170431. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
170432. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK
170433. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
170434. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK
170435. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
170436. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK
170437. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
170438. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK
170439. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
170440. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK
170441. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
170442. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK
170443. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
170444. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK
170445. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
170446. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK
170447. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
170448. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK
170449. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
170450. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK
170451. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
170452. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK
170453. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
170454. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK
170455. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
170456. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK
170457. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
170458. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK
170459. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
170460. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK
170461. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
170462. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK
170463. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
170464. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK
170465. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
170466. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK
170467. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
170468. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK
170469. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
170470. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK
170471. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
170472. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK
170473. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
170474. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK
170475. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
170476. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK
170477. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
170478. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK
170479. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
170480. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK
170481. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
170482. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK
170483. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
170484. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK
170485. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
170486. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK
170487. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
170488. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK
170489. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
170490. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK
170491. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
170492. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK
170493. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
170494. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK
170495. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
170496. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK
170497. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
170498. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK
170499. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
170500. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK
170501. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
170502. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK
170503. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
170504. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK
170505. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
170506. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK
170507. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
170508. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK
170509. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
170510. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK
170511. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
170512. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK
170513. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
170514. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK
170515. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
170516. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK
170517. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
170518. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK
170519. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
170520. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK
170521. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
170522. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK
170523. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
170524. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK
170525. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
170526. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK
170527. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
170528. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK
170529. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
170530. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK
170531. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
170532. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK
170533. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
170534. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK
170535. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
170536. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK
170537. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
170538. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK
170539. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
170540. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK
170541. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
170542. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK
170543. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
170544. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK
170545. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
170546. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK
170547. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
170548. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK
170549. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
170550. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK
170551. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
170552. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK
170553. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
170554. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK
170555. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
170556. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK
170557. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
170558. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK
170559. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
170560. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK
170561. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
170562. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK
170563. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
170564. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK
170565. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
170566. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK
170567. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
170568. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK
170569. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
170570. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK
170571. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
170572. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK
170573. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
170574. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK
170575. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
170576. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK
170577. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
170578. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK
170579. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
170580. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK
170581. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
170582. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK
170583. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
170584. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK
170585. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
170586. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK
170587. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
170588. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK
170589. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
170590. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK
170591. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
170592. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK
170593. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
170594. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK
170595. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
170596. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK
170597. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
170598. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK
170599. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
170600. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK
170601. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
170602. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK
170603. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
170604. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK
170605. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
170606. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK
170607. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
170608. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK
170609. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
170610. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK
170611. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
170612. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK
170613. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
170614. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK
170615. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
170616. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK
170617. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
170618. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK
170619. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
170620. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK
170621. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
170622. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK
170623. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
170624. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK
170625. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
170626. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK
170627. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
170628. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK
170629. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
170630. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK
170631. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
170632. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK
170633. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
170634. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK
170635. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
170636. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK
170637. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
170638. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK
170639. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
170640. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK
170641. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
170642. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK
170643. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
170644. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK
170645. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
170646. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK
170647. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
170648. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK
170649. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
170650. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK
170651. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
170652. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK
170653. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
170654. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK
170655. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
170656. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK
170657. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
170658. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK
170659. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
170660. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK
170661. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
170662. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK
170663. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
170664. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK
170665. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
170666. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK
170667. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
170668. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK
170669. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
170670. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
170671. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
170672. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
170673. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
170674. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
170675. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
170676. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
170677. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
170678. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
170679. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
170680. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
170681. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
170682. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
170683. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
170684. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
170685. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
170686. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
170687. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
170688. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
170689. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
170690. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
170691. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
170692. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
170693. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
170694. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
170695. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
170696. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
170697. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
170698. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
170699. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
170700. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
170701. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
170702. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
170703. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
170704. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
170705. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
170706. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
170707. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
170708. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
170709. DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
170710. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK
170711. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT
170712. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK
170713. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT
170714. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK
170715. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT
170716. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK
170717. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT
170718. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK
170719. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT
170720. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK
170721. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT
170722. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK
170723. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT
170724. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK
170725. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT
170726. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
170727. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
170728. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
170729. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
170730. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
170731. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
170732. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
170733. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
170734. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
170735. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
170736. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
170737. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
170738. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
170739. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
170740. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
170741. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
170742. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
170743. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
170744. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
170745. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
170746. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
170747. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
170748. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
170749. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
170750. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
170751. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
170752. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
170753. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
170754. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
170755. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
170756. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
170757. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
170758. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
170759. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
170760. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
170761. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
170762. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
170763. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
170764. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
170765. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
170766. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
170767. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
170768. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
170769. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
170770. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
170771. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
170772. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
170773. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
170774. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
170775. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
170776. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
170777. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
170778. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
170779. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
170780. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
170781. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
170782. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
170783. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
170784. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
170785. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
170786. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
170787. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
170788. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
170789. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
170790. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
170791. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
170792. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
170793. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
170794. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
170795. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
170796. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
170797. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
170798. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
170799. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
170800. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
170801. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
170802. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
170803. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
170804. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
170805. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
170806. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
170807. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
170808. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
170809. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
170810. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
170811. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
170812. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
170813. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
170814. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
170815. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
170816. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
170817. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
170818. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
170819. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
170820. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
170821. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
170822. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
170823. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
170824. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
170825. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
170826. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
170827. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
170828. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
170829. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
170830. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
170831. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
170832. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
170833. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
170834. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
170835. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
170836. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
170837. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
170838. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
170839. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
170840. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
170841. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
170842. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
170843. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
170844. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
170845. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
170846. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
170847. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
170848. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
170849. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
170850. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
170851. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
170852. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
170853. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
170854. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
170855. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
170856. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
170857. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
170858. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
170859. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
170860. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
170861. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
170862. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
170863. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
170864. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
170865. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
170866. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
170867. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
170868. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
170869. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
170870. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
170871. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
170872. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
170873. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
170874. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
170875. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
170876. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
170877. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
170878. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
170879. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
170880. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
170881. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
170882. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
170883. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
170884. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
170885. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
170886. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
170887. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
170888. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
170889. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
170890. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
170891. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
170892. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
170893. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
170894. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
170895. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
170896. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
170897. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
170898. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
170899. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
170900. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
170901. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
170902. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
170903. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
170904. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
170905. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
170906. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
170907. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
170908. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
170909. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
170910. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
170911. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
170912. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
170913. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
170914. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
170915. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
170916. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
170917. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
170918. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
170919. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
170920. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
170921. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
170922. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
170923. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
170924. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
170925. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
170926. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
170927. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
170928. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
170929. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
170930. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
170931. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
170932. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
170933. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
170934. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
170935. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
170936. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
170937. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
170938. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
170939. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
170940. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
170941. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
170942. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
170943. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
170944. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
170945. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
170946. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
170947. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
170948. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
170949. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
170950. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
170951. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
170952. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
170953. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
170954. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
170955. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
170956. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
170957. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
170958. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
170959. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
170960. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
170961. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
170962. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
170963. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
170964. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
170965. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
170966. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
170967. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
170968. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK
170969. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
170970. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
170971. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
170972. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
170973. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
170974. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
170975. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
170976. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
170977. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
170978. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
170979. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
170980. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
170981. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
170982. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
170983. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
170984. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
170985. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
170986. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
170987. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
170988. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
170989. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
170990. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
170991. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
170992. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
170993. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
170994. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
170995. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
170996. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK
170997. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
170998. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
170999. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
171000. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
171001. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
171002. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK
171003. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT
171004. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
171005. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
171006. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
171007. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
171008. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
171009. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
171010. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
171011. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
171012. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
171013. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
171014. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
171015. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
171016. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
171017. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
171018. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
171019. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
171020. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
171021. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
171022. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
171023. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
171024. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
171025. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
171026. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
171027. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
171028. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
171029. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
171030. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
171031. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
171032. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
171033. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
171034. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
171035. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
171036. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
171037. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
171038. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
171039. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
171040. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
171041. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
171042. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
171043. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
171044. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
171045. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
171046. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
171047. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
171048. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
171049. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
171050. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
171051. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
171052. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
171053. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
171054. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
171055. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
171056. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
171057. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
171058. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
171059. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
171060. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
171061. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
171062. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
171063. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
171064. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
171065. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
171066. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
171067. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
171068. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
171069. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
171070. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
171071. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
171072. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
171073. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
171074. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
171075. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
171076. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
171077. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
171078. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
171079. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
171080. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
171081. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
171082. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
171083. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
171084. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
171085. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
171086. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
171087. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
171088. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
171089. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
171090. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
171091. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
171092. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
171093. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
171094. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
171095. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
171096. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
171097. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
171098. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
171099. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
171100. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
171101. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
171102. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
171103. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
171104. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
171105. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
171106. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
171107. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
171108. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
171109. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
171110. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
171111. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
171112. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
171113. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
171114. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
171115. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
171116. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
171117. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
171118. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
171119. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
171120. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
171121. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
171122. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
171123. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
171124. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
171125. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
171126. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
171127. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
171128. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
171129. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
171130. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
171131. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
171132. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
171133. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
171134. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
171135. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
171136. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
171137. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
171138. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
171139. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
171140. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
171141. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
171142. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
171143. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
171144. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
171145. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
171146. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
171147. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
171148. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
171149. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
171150. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
171151. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
171152. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
171153. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
171154. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
171155. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
171156. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
171157. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
171158. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
171159. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
171160. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
171161. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
171162. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
171163. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
171164. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
171165. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
171166. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
171167. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
171168. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
171169. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
171170. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
171171. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
171172. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
171173. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
171174. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
171175. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
171176. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
171177. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
171178. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
171179. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
171180. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
171181. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
171182. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
171183. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
171184. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
171185. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
171186. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
171187. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
171188. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
171189. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
171190. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
171191. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
171192. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
171193. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
171194. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
171195. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
171196. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
171197. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
171198. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
171199. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
171200. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
171201. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
171202. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
171203. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
171204. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
171205. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
171206. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
171207. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
171208. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
171209. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
171210. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
171211. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
171212. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
171213. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
171214. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
171215. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
171216. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
171217. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
171218. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
171219. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
171220. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
171221. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
171222. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
171223. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
171224. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
171225. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
171226. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
171227. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
171228. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
171229. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
171230. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
171231. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
171232. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
171233. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
171234. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
171235. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
171236. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
171237. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
171238. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
171239. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
171240. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
171241. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
171242. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
171243. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
171244. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
171245. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
171246. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
171247. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
171248. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
171249. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
171250. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
171251. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
171252. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
171253. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
171254. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
171255. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
171256. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
171257. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
171258. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
171259. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
171260. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
171261. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
171262. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
171263. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
171264. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
171265. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
171266. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
171267. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
171268. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
171269. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
171270. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
171271. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
171272. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
171273. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
171274. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
171275. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
171276. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
171277. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
171278. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
171279. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
171280. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
171281. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
171282. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
171283. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
171284. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
171285. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
171286. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
171287. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
171288. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
171289. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
171290. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
171291. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
171292. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
171293. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
171294. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
171295. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
171296. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
171297. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
171298. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
171299. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
171300. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
171301. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
171302. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
171303. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
171304. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
171305. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
171306. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
171307. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
171308. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
171309. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
171310. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
171311. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
171312. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
171313. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
171314. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
171315. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
171316. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
171317. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
171318. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
171319. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
171320. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
171321. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
171322. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
171323. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
171324. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
171325. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
171326. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
171327. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
171328. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
171329. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
171330. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
171331. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
171332. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
171333. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
171334. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
171335. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
171336. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
171337. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
171338. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
171339. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
171340. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
171341. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
171342. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
171343. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
171344. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
171345. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
171346. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
171347. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
171348. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
171349. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
171350. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
171351. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
171352. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
171353. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
171354. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
171355. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
171356. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
171357. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
171358. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
171359. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
171360. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
171361. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
171362. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
171363. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
171364. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
171365. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
171366. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
171367. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
171368. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
171369. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
171370. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
171371. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
171372. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
171373. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
171374. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
171375. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
171376. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
171377. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
171378. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
171379. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
171380. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
171381. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
171382. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
171383. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
171384. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
171385. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
171386. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
171387. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
171388. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
171389. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
171390. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK
171391. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT
171392. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK
171393. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT
171394. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK
171395. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT
171396. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK
171397. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT
171398. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK
171399. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT
171400. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK
171401. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT
171402. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK
171403. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT
171404. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK
171405. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT
171406. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
171407. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
171408. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
171409. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
171410. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
171411. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
171412. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
171413. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
171414. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
171415. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
171416. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
171417. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
171418. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
171419. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
171420. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
171421. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
171422. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
171423. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
171424. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
171425. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
171426. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
171427. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
171428. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
171429. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
171430. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
171431. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
171432. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
171433. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
171434. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
171435. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
171436. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
171437. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
171438. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
171439. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
171440. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
171441. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
171442. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
171443. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
171444. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
171445. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
171446. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
171447. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
171448. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
171449. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
171450. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
171451. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
171452. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
171453. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
171454. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
171455. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
171456. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
171457. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
171458. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
171459. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
171460. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
171461. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
171462. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
171463. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
171464. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
171465. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
171466. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
171467. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
171468. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
171469. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
171470. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
171471. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
171472. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
171473. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
171474. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
171475. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
171476. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
171477. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
171478. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
171479. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
171480. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
171481. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
171482. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
171483. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
171484. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
171485. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
171486. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
171487. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
171488. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
171489. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
171490. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
171491. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
171492. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
171493. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
171494. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
171495. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
171496. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
171497. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
171498. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
171499. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
171500. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
171501. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
171502. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
171503. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
171504. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
171505. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
171506. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
171507. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
171508. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
171509. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
171510. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
171511. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
171512. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
171513. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
171514. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
171515. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
171516. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
171517. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
171518. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
171519. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
171520. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
171521. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
171522. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
171523. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
171524. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
171525. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
171526. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
171527. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
171528. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
171529. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
171530. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
171531. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
171532. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
171533. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
171534. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
171535. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
171536. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
171537. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
171538. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
171539. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
171540. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
171541. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
171542. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
171543. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
171544. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
171545. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
171546. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
171547. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
171548. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
171549. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
171550. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
171551. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
171552. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
171553. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
171554. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
171555. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
171556. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
171557. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
171558. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
171559. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
171560. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
171561. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
171562. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
171563. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
171564. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
171565. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
171566. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
171567. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
171568. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
171569. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
171570. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
171571. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
171572. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
171573. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
171574. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
171575. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
171576. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
171577. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
171578. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
171579. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
171580. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
171581. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
171582. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
171583. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
171584. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
171585. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
171586. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
171587. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
171588. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
171589. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
171590. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
171591. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
171592. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
171593. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
171594. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
171595. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
171596. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
171597. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
171598. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
171599. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
171600. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
171601. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
171602. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
171603. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
171604. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
171605. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
171606. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
171607. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
171608. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
171609. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
171610. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
171611. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
171612. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
171613. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
171614. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
171615. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
171616. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
171617. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
171618. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
171619. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
171620. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
171621. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
171622. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
171623. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
171624. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
171625. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
171626. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
171627. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
171628. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
171629. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
171630. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
171631. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
171632. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
171633. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
171634. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
171635. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
171636. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
171637. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
171638. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
171639. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
171640. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
171641. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
171642. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
171643. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
171644. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
171645. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
171646. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
171647. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
171648. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK
171649. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
171650. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
171651. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
171652. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
171653. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
171654. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
171655. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
171656. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
171657. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
171658. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
171659. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
171660. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
171661. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
171662. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
171663. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
171664. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
171665. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
171666. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
171667. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
171668. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
171669. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
171670. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
171671. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
171672. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
171673. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
171674. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
171675. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
171676. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK
171677. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
171678. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
171679. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
171680. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
171681. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
171682. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK
171683. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT
171684. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
171685. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
171686. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
171687. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
171688. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
171689. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
171690. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
171691. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
171692. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
171693. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
171694. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
171695. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
171696. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
171697. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
171698. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
171699. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
171700. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
171701. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
171702. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
171703. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
171704. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
171705. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
171706. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
171707. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
171708. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
171709. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
171710. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
171711. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
171712. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
171713. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
171714. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
171715. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
171716. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
171717. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
171718. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
171719. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
171720. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
171721. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
171722. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
171723. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
171724. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
171725. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
171726. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
171727. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
171728. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
171729. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
171730. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
171731. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
171732. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
171733. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
171734. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
171735. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
171736. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
171737. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
171738. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
171739. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
171740. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
171741. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
171742. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
171743. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
171744. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
171745. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
171746. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
171747. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
171748. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
171749. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
171750. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
171751. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
171752. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
171753. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
171754. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
171755. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
171756. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
171757. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
171758. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
171759. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
171760. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
171761. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
171762. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
171763. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
171764. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
171765. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
171766. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
171767. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
171768. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
171769. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
171770. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
171771. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
171772. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
171773. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
171774. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
171775. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
171776. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
171777. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
171778. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
171779. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
171780. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
171781. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
171782. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
171783. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
171784. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
171785. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
171786. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
171787. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
171788. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
171789. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
171790. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
171791. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
171792. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
171793. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
171794. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
171795. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
171796. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
171797. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
171798. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
171799. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
171800. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
171801. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
171802. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
171803. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
171804. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
171805. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
171806. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
171807. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
171808. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
171809. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
171810. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
171811. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
171812. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
171813. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
171814. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
171815. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
171816. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
171817. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
171818. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
171819. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
171820. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
171821. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
171822. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
171823. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
171824. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
171825. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
171826. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
171827. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
171828. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
171829. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
171830. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
171831. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
171832. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
171833. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
171834. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
171835. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
171836. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
171837. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
171838. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
171839. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
171840. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
171841. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
171842. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
171843. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
171844. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
171845. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
171846. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
171847. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
171848. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
171849. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
171850. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
171851. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
171852. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
171853. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
171854. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
171855. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
171856. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
171857. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
171858. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
171859. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
171860. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
171861. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
171862. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
171863. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
171864. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
171865. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
171866. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
171867. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
171868. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
171869. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
171870. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
171871. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
171872. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
171873. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
171874. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
171875. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
171876. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
171877. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
171878. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
171879. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
171880. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
171881. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
171882. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
171883. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
171884. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
171885. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
171886. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
171887. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
171888. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
171889. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
171890. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
171891. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
171892. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
171893. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
171894. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
171895. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
171896. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
171897. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
171898. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
171899. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
171900. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
171901. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
171902. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
171903. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
171904. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
171905. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
171906. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
171907. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
171908. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
171909. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
171910. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
171911. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
171912. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
171913. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
171914. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
171915. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
171916. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
171917. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
171918. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
171919. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
171920. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
171921. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
171922. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
171923. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
171924. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
171925. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
171926. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
171927. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
171928. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
171929. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
171930. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
171931. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
171932. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
171933. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
171934. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
171935. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
171936. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
171937. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
171938. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
171939. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
171940. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
171941. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
171942. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
171943. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
171944. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
171945. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
171946. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
171947. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
171948. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
171949. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
171950. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
171951. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
171952. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
171953. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
171954. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
171955. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
171956. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
171957. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
171958. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
171959. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
171960. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
171961. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
171962. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
171963. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
171964. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
171965. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
171966. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
171967. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
171968. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
171969. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
171970. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
171971. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
171972. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
171973. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
171974. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
171975. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
171976. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
171977. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
171978. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
171979. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
171980. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
171981. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
171982. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
171983. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
171984. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
171985. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
171986. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
171987. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
171988. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
171989. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
171990. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
171991. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
171992. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
171993. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
171994. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
171995. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
171996. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
171997. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
171998. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
171999. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
172000. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
172001. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
172002. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
172003. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
172004. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
172005. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
172006. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
172007. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
172008. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
172009. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
172010. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
172011. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
172012. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
172013. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
172014. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
172015. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
172016. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
172017. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
172018. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
172019. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
172020. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
172021. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
172022. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
172023. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
172024. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
172025. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
172026. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
172027. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
172028. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
172029. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
172030. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
172031. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
172032. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
172033. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
172034. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
172035. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
172036. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
172037. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
172038. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
172039. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
172040. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
172041. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
172042. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
172043. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
172044. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
172045. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
172046. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
172047. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
172048. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
172049. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
172050. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
172051. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
172052. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
172053. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
172054. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
172055. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
172056. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
172057. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
172058. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
172059. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
172060. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
172061. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
172062. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
172063. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
172064. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
172065. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
172066. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
172067. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
172068. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
172069. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
172070. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK
172071. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT
172072. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK
172073. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT
172074. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK
172075. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT
172076. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK
172077. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT
172078. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK
172079. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT
172080. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK
172081. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT
172082. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK
172083. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT
172084. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK
172085. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT
172086. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
172087. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
172088. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
172089. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
172090. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
172091. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
172092. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
172093. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
172094. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
172095. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
172096. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
172097. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
172098. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
172099. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
172100. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
172101. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
172102. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
172103. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
172104. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
172105. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
172106. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
172107. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
172108. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
172109. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
172110. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
172111. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
172112. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
172113. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172114. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
172115. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
172116. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
172117. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
172118. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
172119. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
172120. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
172121. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172122. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
172123. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
172124. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
172125. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
172126. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
172127. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
172128. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
172129. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
172130. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
172131. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
172132. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
172133. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172134. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
172135. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
172136. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
172137. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
172138. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
172139. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
172140. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
172141. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172142. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
172143. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
172144. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
172145. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
172146. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
172147. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
172148. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
172149. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
172150. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
172151. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
172152. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
172153. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
172154. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
172155. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
172156. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
172157. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
172158. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
172159. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
172160. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
172161. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
172162. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
172163. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
172164. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
172165. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
172166. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
172167. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
172168. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
172169. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
172170. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
172171. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
172172. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
172173. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
172174. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
172175. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
172176. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
172177. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
172178. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
172179. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
172180. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
172181. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
172182. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
172183. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
172184. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
172185. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
172186. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
172187. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
172188. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
172189. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
172190. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
172191. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
172192. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
172193. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
172194. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
172195. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
172196. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
172197. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
172198. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
172199. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
172200. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
172201. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
172202. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
172203. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
172204. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
172205. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
172206. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
172207. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
172208. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
172209. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
172210. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
172211. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
172212. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
172213. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
172214. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
172215. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
172216. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
172217. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
172218. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
172219. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
172220. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
172221. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
172222. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
172223. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
172224. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
172225. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
172226. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
172227. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
172228. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
172229. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
172230. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
172231. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
172232. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
172233. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
172234. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
172235. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
172236. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
172237. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
172238. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
172239. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
172240. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
172241. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
172242. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
172243. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
172244. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
172245. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
172246. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
172247. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
172248. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
172249. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
172250. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
172251. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
172252. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
172253. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
172254. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
172255. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
172256. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
172257. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
172258. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
172259. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
172260. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
172261. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
172262. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
172263. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
172264. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
172265. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
172266. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
172267. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
172268. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
172269. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
172270. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
172271. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
172272. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
172273. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
172274. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
172275. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
172276. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
172277. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
172278. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
172279. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
172280. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
172281. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
172282. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
172283. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
172284. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
172285. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
172286. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
172287. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
172288. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
172289. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
172290. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
172291. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
172292. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
172293. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
172294. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
172295. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
172296. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
172297. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
172298. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
172299. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
172300. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
172301. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
172302. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
172303. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
172304. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
172305. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
172306. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
172307. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
172308. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
172309. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
172310. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
172311. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
172312. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
172313. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
172314. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
172315. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
172316. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
172317. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
172318. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
172319. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
172320. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
172321. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
172322. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
172323. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
172324. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
172325. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
172326. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
172327. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
172328. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK
172329. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
172330. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
172331. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
172332. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
172333. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
172334. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
172335. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
172336. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
172337. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
172338. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
172339. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
172340. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
172341. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
172342. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
172343. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
172344. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
172345. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
172346. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
172347. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
172348. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
172349. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
172350. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
172351. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
172352. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
172353. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
172354. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
172355. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
172356. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK
172357. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
172358. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
172359. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
172360. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
172361. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
172362. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK
172363. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT
172364. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
172365. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
172366. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
172367. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
172368. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
172369. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
172370. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
172371. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
172372. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
172373. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
172374. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
172375. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
172376. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
172377. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
172378. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
172379. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
172380. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
172381. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
172382. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
172383. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
172384. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
172385. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
172386. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
172387. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
172388. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
172389. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
172390. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
172391. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
172392. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
172393. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
172394. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
172395. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
172396. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
172397. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
172398. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
172399. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
172400. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
172401. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
172402. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
172403. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
172404. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
172405. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
172406. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
172407. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
172408. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
172409. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
172410. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
172411. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
172412. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
172413. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
172414. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
172415. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
172416. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
172417. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
172418. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
172419. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
172420. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
172421. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
172422. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
172423. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
172424. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
172425. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
172426. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
172427. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
172428. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
172429. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
172430. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
172431. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
172432. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
172433. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
172434. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
172435. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
172436. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
172437. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
172438. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
172439. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
172440. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
172441. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
172442. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
172443. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
172444. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
172445. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
172446. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
172447. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
172448. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
172449. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
172450. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
172451. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
172452. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
172453. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
172454. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
172455. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
172456. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
172457. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
172458. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
172459. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
172460. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
172461. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
172462. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
172463. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
172464. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
172465. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
172466. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
172467. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
172468. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
172469. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
172470. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
172471. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
172472. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
172473. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
172474. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
172475. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
172476. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
172477. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
172478. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
172479. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
172480. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
172481. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
172482. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
172483. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
172484. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
172485. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
172486. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
172487. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
172488. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
172489. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
172490. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
172491. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
172492. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
172493. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
172494. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
172495. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
172496. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
172497. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
172498. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
172499. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
172500. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
172501. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
172502. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
172503. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
172504. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
172505. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
172506. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
172507. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
172508. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
172509. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
172510. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
172511. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
172512. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
172513. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
172514. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
172515. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
172516. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
172517. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
172518. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
172519. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
172520. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
172521. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
172522. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
172523. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
172524. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
172525. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
172526. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
172527. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
172528. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
172529. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
172530. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
172531. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
172532. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
172533. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
172534. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
172535. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
172536. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
172537. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
172538. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
172539. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
172540. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
172541. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
172542. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
172543. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
172544. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
172545. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
172546. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
172547. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
172548. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
172549. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
172550. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
172551. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
172552. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
172553. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
172554. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
172555. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
172556. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
172557. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
172558. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
172559. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
172560. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
172561. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
172562. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
172563. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
172564. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
172565. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
172566. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
172567. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
172568. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
172569. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
172570. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
172571. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
172572. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
172573. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
172574. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
172575. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
172576. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
172577. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
172578. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
172579. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
172580. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
172581. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
172582. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
172583. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
172584. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
172585. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
172586. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
172587. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
172588. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
172589. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
172590. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
172591. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
172592. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
172593. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
172594. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
172595. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
172596. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
172597. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
172598. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
172599. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
172600. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
172601. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
172602. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
172603. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
172604. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
172605. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
172606. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
172607. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
172608. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
172609. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
172610. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
172611. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
172612. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
172613. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
172614. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
172615. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
172616. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
172617. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
172618. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
172619. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
172620. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
172621. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
172622. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
172623. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
172624. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
172625. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
172626. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
172627. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
172628. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
172629. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
172630. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
172631. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
172632. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
172633. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
172634. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
172635. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
172636. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
172637. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
172638. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
172639. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
172640. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
172641. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
172642. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
172643. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
172644. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
172645. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
172646. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
172647. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
172648. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
172649. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
172650. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
172651. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
172652. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
172653. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
172654. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
172655. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
172656. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
172657. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
172658. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
172659. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
172660. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
172661. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
172662. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
172663. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
172664. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
172665. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
172666. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
172667. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
172668. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
172669. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
172670. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
172671. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
172672. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
172673. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
172674. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
172675. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
172676. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
172677. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
172678. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
172679. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
172680. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
172681. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
172682. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
172683. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
172684. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
172685. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
172686. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
172687. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
172688. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
172689. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
172690. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
172691. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
172692. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
172693. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
172694. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
172695. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
172696. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
172697. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
172698. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
172699. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
172700. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
172701. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
172702. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
172703. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
172704. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
172705. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
172706. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
172707. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
172708. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
172709. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
172710. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
172711. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
172712. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
172713. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
172714. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
172715. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
172716. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
172717. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
172718. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
172719. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
172720. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
172721. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
172722. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
172723. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
172724. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
172725. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
172726. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
172727. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
172728. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
172729. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
172730. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
172731. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
172732. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
172733. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
172734. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
172735. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
172736. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
172737. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
172738. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
172739. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
172740. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
172741. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
172742. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
172743. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
172744. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
172745. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
172746. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
172747. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
172748. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
172749. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
172750. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK
172751. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT
172752. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK
172753. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT
172754. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK
172755. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT
172756. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK
172757. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT
172758. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK
172759. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT
172760. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK
172761. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT
172762. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK
172763. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT
172764. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK
172765. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT
172766. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
172767. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
172768. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
172769. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
172770. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
172771. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
172772. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
172773. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
172774. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
172775. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
172776. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
172777. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
172778. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
172779. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
172780. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
172781. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
172782. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
172783. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
172784. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
172785. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
172786. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
172787. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
172788. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
172789. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
172790. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
172791. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
172792. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
172793. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172794. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
172795. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
172796. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
172797. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
172798. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
172799. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
172800. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
172801. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172802. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
172803. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
172804. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
172805. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
172806. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
172807. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
172808. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
172809. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
172810. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
172811. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
172812. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
172813. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172814. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
172815. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
172816. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
172817. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
172818. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
172819. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
172820. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
172821. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
172822. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
172823. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
172824. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
172825. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
172826. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
172827. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
172828. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
172829. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
172830. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
172831. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
172832. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
172833. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
172834. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
172835. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
172836. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
172837. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
172838. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
172839. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
172840. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
172841. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
172842. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
172843. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
172844. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
172845. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
172846. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
172847. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
172848. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
172849. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
172850. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
172851. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
172852. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
172853. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
172854. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
172855. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
172856. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
172857. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
172858. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
172859. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
172860. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
172861. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
172862. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
172863. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
172864. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
172865. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
172866. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
172867. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
172868. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
172869. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
172870. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
172871. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
172872. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
172873. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
172874. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
172875. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
172876. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
172877. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
172878. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
172879. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
172880. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
172881. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
172882. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
172883. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
172884. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
172885. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
172886. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
172887. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
172888. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
172889. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
172890. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
172891. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
172892. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
172893. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
172894. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
172895. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
172896. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
172897. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
172898. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
172899. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
172900. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
172901. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
172902. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
172903. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
172904. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
172905. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
172906. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
172907. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
172908. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
172909. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
172910. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
172911. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
172912. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
172913. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
172914. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
172915. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
172916. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
172917. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
172918. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
172919. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
172920. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
172921. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
172922. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
172923. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
172924. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
172925. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
172926. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
172927. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
172928. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
172929. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
172930. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
172931. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
172932. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
172933. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
172934. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
172935. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
172936. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
172937. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
172938. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
172939. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
172940. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
172941. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
172942. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
172943. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
172944. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
172945. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
172946. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
172947. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
172948. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
172949. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
172950. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
172951. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
172952. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
172953. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
172954. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
172955. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
172956. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
172957. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
172958. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
172959. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
172960. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
172961. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
172962. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
172963. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
172964. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
172965. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
172966. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
172967. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
172968. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
172969. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
172970. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
172971. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
172972. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
172973. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
172974. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
172975. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
172976. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
172977. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
172978. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
172979. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
172980. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
172981. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
172982. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
172983. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
172984. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
172985. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
172986. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
172987. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
172988. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
172989. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
172990. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
172991. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
172992. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
172993. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
172994. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
172995. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
172996. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
172997. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
172998. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
172999. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
173000. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
173001. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
173002. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
173003. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
173004. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
173005. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
173006. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
173007. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
173008. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK
173009. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
173010. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
173011. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
173012. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
173013. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
173014. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
173015. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
173016. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
173017. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
173018. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
173019. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
173020. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
173021. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
173022. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
173023. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
173024. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
173025. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
173026. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
173027. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
173028. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
173029. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
173030. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
173031. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
173032. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
173033. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
173034. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
173035. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
173036. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK
173037. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
173038. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
173039. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
173040. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
173041. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
173042. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK
173043. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT
173044. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
173045. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
173046. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
173047. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
173048. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
173049. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
173050. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
173051. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
173052. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
173053. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
173054. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
173055. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
173056. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
173057. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
173058. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
173059. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
173060. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
173061. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
173062. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
173063. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
173064. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
173065. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
173066. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
173067. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
173068. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
173069. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
173070. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
173071. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
173072. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
173073. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
173074. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
173075. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
173076. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
173077. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
173078. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
173079. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
173080. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
173081. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
173082. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
173083. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
173084. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
173085. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
173086. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
173087. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
173088. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
173089. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
173090. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
173091. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
173092. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
173093. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
173094. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
173095. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
173096. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
173097. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
173098. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
173099. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
173100. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
173101. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
173102. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
173103. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
173104. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
173105. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
173106. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
173107. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
173108. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
173109. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
173110. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
173111. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
173112. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
173113. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
173114. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
173115. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
173116. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
173117. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
173118. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
173119. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
173120. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
173121. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
173122. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
173123. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
173124. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
173125. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
173126. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
173127. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
173128. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
173129. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
173130. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
173131. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
173132. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
173133. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
173134. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
173135. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
173136. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
173137. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
173138. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
173139. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
173140. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
173141. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
173142. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
173143. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
173144. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
173145. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
173146. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
173147. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
173148. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
173149. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
173150. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
173151. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
173152. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
173153. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
173154. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
173155. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
173156. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
173157. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
173158. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
173159. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
173160. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
173161. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
173162. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
173163. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
173164. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
173165. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
173166. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
173167. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
173168. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
173169. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
173170. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
173171. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
173172. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
173173. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
173174. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
173175. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
173176. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
173177. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
173178. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
173179. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
173180. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
173181. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
173182. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
173183. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
173184. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
173185. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
173186. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
173187. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
173188. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
173189. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
173190. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
173191. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
173192. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
173193. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
173194. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
173195. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
173196. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
173197. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
173198. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
173199. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
173200. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
173201. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
173202. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
173203. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
173204. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
173205. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
173206. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
173207. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
173208. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
173209. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
173210. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
173211. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
173212. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
173213. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
173214. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
173215. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
173216. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
173217. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
173218. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
173219. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
173220. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
173221. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
173222. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
173223. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
173224. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
173225. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
173226. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
173227. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
173228. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
173229. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
173230. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
173231. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
173232. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
173233. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
173234. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
173235. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
173236. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
173237. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
173238. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
173239. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
173240. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
173241. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
173242. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
173243. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
173244. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
173245. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
173246. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
173247. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
173248. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
173249. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
173250. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
173251. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
173252. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
173253. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
173254. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
173255. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
173256. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
173257. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
173258. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
173259. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
173260. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
173261. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
173262. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
173263. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
173264. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
173265. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
173266. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
173267. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
173268. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
173269. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
173270. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
173271. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
173272. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
173273. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
173274. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
173275. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
173276. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
173277. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
173278. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
173279. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
173280. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
173281. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
173282. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
173283. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
173284. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
173285. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
173286. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
173287. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
173288. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
173289. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
173290. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
173291. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
173292. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
173293. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
173294. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
173295. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
173296. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
173297. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
173298. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
173299. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
173300. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
173301. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
173302. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
173303. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
173304. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
173305. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
173306. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
173307. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
173308. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
173309. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
173310. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
173311. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
173312. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
173313. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
173314. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
173315. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
173316. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
173317. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
173318. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
173319. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
173320. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
173321. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
173322. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
173323. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
173324. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
173325. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
173326. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
173327. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
173328. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
173329. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
173330. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
173331. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
173332. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
173333. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
173334. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
173335. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
173336. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
173337. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
173338. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
173339. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
173340. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
173341. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
173342. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
173343. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
173344. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
173345. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
173346. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
173347. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
173348. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
173349. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
173350. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
173351. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
173352. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
173353. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
173354. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
173355. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
173356. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
173357. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
173358. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
173359. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
173360. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
173361. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
173362. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
173363. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
173364. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
173365. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
173366. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
173367. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
173368. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
173369. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
173370. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
173371. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
173372. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
173373. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
173374. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
173375. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
173376. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
173377. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
173378. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
173379. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
173380. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
173381. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
173382. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
173383. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
173384. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
173385. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
173386. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
173387. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
173388. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
173389. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
173390. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
173391. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
173392. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
173393. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
173394. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
173395. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
173396. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
173397. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
173398. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
173399. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
173400. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
173401. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
173402. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
173403. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
173404. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
173405. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
173406. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
173407. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
173408. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
173409. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
173410. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
173411. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
173412. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
173413. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
173414. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
173415. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
173416. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
173417. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
173418. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
173419. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
173420. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
173421. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
173422. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
173423. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
173424. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
173425. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
173426. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
173427. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
173428. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
173429. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
173430. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK
173431. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT
173432. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK
173433. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT
173434. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK
173435. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT
173436. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK
173437. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT
173438. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK
173439. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT
173440. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK
173441. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT
173442. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK
173443. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT
173444. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK
173445. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT
173446. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
173447. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
173448. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
173449. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
173450. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
173451. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
173452. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
173453. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
173454. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
173455. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
173456. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
173457. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
173458. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
173459. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
173460. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
173461. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
173462. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
173463. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
173464. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
173465. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
173466. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
173467. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
173468. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
173469. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
173470. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
173471. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
173472. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
173473. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
173474. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
173475. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
173476. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
173477. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
173478. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
173479. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
173480. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
173481. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
173482. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
173483. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
173484. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
173485. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
173486. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
173487. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
173488. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
173489. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
173490. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
173491. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
173492. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
173493. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
173494. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
173495. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
173496. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
173497. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
173498. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
173499. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
173500. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
173501. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
173502. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
173503. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
173504. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
173505. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
173506. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
173507. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
173508. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
173509. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
173510. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
173511. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
173512. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
173513. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
173514. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
173515. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
173516. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
173517. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
173518. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
173519. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
173520. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
173521. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
173522. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
173523. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
173524. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
173525. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
173526. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
173527. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
173528. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
173529. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
173530. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
173531. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
173532. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
173533. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
173534. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
173535. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
173536. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
173537. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
173538. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
173539. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
173540. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
173541. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
173542. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
173543. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
173544. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
173545. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
173546. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
173547. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
173548. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
173549. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
173550. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
173551. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
173552. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
173553. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
173554. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
173555. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
173556. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
173557. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
173558. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
173559. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
173560. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
173561. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
173562. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
173563. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
173564. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
173565. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
173566. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
173567. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
173568. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
173569. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
173570. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
173571. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
173572. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
173573. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
173574. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
173575. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
173576. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
173577. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
173578. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
173579. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
173580. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
173581. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
173582. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
173583. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
173584. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
173585. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
173586. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
173587. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
173588. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
173589. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
173590. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
173591. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
173592. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
173593. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
173594. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
173595. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
173596. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
173597. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
173598. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
173599. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
173600. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
173601. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
173602. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
173603. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
173604. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
173605. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
173606. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
173607. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
173608. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
173609. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
173610. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
173611. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
173612. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
173613. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
173614. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
173615. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
173616. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
173617. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
173618. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
173619. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
173620. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
173621. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
173622. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
173623. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
173624. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
173625. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
173626. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
173627. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
173628. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
173629. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
173630. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
173631. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
173632. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
173633. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
173634. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
173635. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
173636. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
173637. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
173638. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
173639. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
173640. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
173641. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
173642. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
173643. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
173644. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
173645. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
173646. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
173647. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
173648. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
173649. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
173650. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
173651. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
173652. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
173653. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
173654. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
173655. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
173656. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
173657. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
173658. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
173659. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
173660. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
173661. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
173662. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
173663. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
173664. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
173665. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
173666. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
173667. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
173668. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
173669. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
173670. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
173671. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
173672. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
173673. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
173674. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
173675. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
173676. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
173677. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
173678. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
173679. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
173680. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
173681. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
173682. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
173683. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
173684. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
173685. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
173686. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
173687. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
173688. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK
173689. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
173690. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
173691. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
173692. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
173693. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
173694. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
173695. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
173696. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
173697. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
173698. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
173699. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
173700. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
173701. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
173702. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
173703. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
173704. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
173705. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
173706. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
173707. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
173708. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
173709. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
173710. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
173711. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
173712. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
173713. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
173714. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
173715. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
173716. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK
173717. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
173718. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
173719. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
173720. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
173721. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
173722. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK
173723. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT
173724. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
173725. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
173726. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
173727. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
173728. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
173729. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
173730. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
173731. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
173732. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
173733. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
173734. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
173735. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
173736. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
173737. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
173738. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
173739. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
173740. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
173741. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
173742. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
173743. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
173744. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
173745. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
173746. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
173747. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
173748. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
173749. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
173750. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
173751. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
173752. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
173753. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
173754. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
173755. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
173756. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
173757. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
173758. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
173759. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
173760. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
173761. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
173762. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
173763. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
173764. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
173765. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
173766. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
173767. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
173768. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
173769. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
173770. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
173771. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
173772. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
173773. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
173774. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
173775. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
173776. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
173777. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
173778. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
173779. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
173780. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
173781. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
173782. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
173783. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
173784. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
173785. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
173786. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
173787. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
173788. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
173789. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
173790. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
173791. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
173792. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
173793. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
173794. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
173795. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
173796. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
173797. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
173798. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
173799. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
173800. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
173801. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
173802. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
173803. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
173804. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
173805. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
173806. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
173807. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
173808. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
173809. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
173810. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
173811. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
173812. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
173813. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
173814. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
173815. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
173816. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
173817. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
173818. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
173819. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
173820. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
173821. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
173822. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
173823. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
173824. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
173825. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
173826. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
173827. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
173828. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
173829. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
173830. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
173831. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
173832. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
173833. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
173834. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
173835. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
173836. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
173837. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
173838. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
173839. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
173840. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
173841. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
173842. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
173843. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
173844. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
173845. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
173846. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
173847. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
173848. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
173849. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
173850. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
173851. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
173852. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
173853. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
173854. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
173855. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
173856. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
173857. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
173858. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
173859. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
173860. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
173861. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
173862. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
173863. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
173864. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
173865. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
173866. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
173867. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
173868. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
173869. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
173870. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
173871. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
173872. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
173873. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
173874. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
173875. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
173876. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
173877. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
173878. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
173879. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
173880. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
173881. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
173882. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
173883. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
173884. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
173885. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
173886. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
173887. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
173888. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
173889. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
173890. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
173891. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
173892. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
173893. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
173894. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
173895. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
173896. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
173897. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
173898. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
173899. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
173900. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
173901. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
173902. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
173903. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
173904. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
173905. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
173906. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
173907. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
173908. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
173909. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
173910. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
173911. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
173912. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
173913. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
173914. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
173915. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
173916. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
173917. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
173918. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
173919. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
173920. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
173921. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
173922. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
173923. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
173924. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
173925. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
173926. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
173927. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
173928. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
173929. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
173930. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
173931. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
173932. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
173933. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
173934. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
173935. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
173936. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
173937. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
173938. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
173939. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
173940. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
173941. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
173942. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
173943. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
173944. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
173945. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
173946. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
173947. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
173948. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
173949. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
173950. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
173951. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
173952. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
173953. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
173954. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
173955. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
173956. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
173957. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
173958. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
173959. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
173960. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
173961. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
173962. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
173963. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
173964. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
173965. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
173966. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
173967. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
173968. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
173969. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
173970. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
173971. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
173972. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
173973. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
173974. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
173975. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
173976. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
173977. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
173978. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
173979. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
173980. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
173981. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
173982. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
173983. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
173984. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
173985. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
173986. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
173987. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
173988. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
173989. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
173990. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
173991. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
173992. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
173993. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
173994. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
173995. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
173996. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
173997. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
173998. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
173999. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
174000. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
174001. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
174002. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
174003. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
174004. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
174005. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
174006. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
174007. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
174008. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
174009. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
174010. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
174011. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
174012. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
174013. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
174014. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
174015. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
174016. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
174017. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
174018. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
174019. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
174020. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
174021. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
174022. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
174023. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
174024. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
174025. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
174026. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
174027. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
174028. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
174029. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
174030. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
174031. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
174032. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
174033. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
174034. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
174035. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
174036. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
174037. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
174038. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
174039. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
174040. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
174041. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
174042. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
174043. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
174044. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
174045. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
174046. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
174047. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
174048. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
174049. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
174050. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
174051. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
174052. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
174053. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
174054. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
174055. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
174056. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
174057. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
174058. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
174059. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
174060. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
174061. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
174062. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
174063. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
174064. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
174065. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
174066. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
174067. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
174068. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
174069. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
174070. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
174071. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
174072. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
174073. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
174074. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
174075. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
174076. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
174077. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
174078. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
174079. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
174080. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
174081. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
174082. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
174083. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
174084. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
174085. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
174086. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
174087. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
174088. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
174089. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
174090. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
174091. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
174092. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
174093. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
174094. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
174095. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
174096. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
174097. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
174098. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
174099. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
174100. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
174101. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
174102. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
174103. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
174104. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
174105. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
174106. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
174107. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
174108. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
174109. DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
174110. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__NC74_MASK
174111. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__NC74__SHIFT
174112. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__RESERVED_15_8_MASK
174113. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__RESERVED_15_8__SHIFT
174114. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__bypass_bg_MASK
174115. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__bypass_bg__SHIFT
174116. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__chop_en_MASK
174117. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__chop_en__SHIFT
174118. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__vref_sel_fastreg_MASK
174119. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__vref_sel_fastreg__SHIFT
174120. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
174121. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
174122. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK
174123. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
174124. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK
174125. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
174126. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
174127. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
174128. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK
174129. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
174130. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK
174131. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
174132. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK
174133. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
174134. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK
174135. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
174136. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK
174137. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
174138. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
174139. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
174140. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
174141. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
174142. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK
174143. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT
174144. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
174145. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
174146. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK
174147. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
174148. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK
174149. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT
174150. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
174151. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
174152. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK
174153. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
174154. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
174155. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
174156. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__NC76_MASK
174157. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT
174158. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
174159. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
174160. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__atb_select_MASK
174161. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT
174162. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK
174163. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT
174164. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK
174165. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT
174166. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK
174167. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
174168. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK
174169. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT
174170. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK
174171. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT
174172. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC40_MASK
174173. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC40__SHIFT
174174. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC76_MASK
174175. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC76__SHIFT
174176. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK
174177. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
174178. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK
174179. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT
174180. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
174181. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
174182. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK
174183. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT
174184. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK
174185. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT
174186. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
174187. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
174188. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK
174189. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
174190. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK
174191. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
174192. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
174193. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
174194. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK
174195. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
174196. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK
174197. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT
174198. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
174199. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
174200. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK
174201. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
174202. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK
174203. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
174204. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
174205. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
174206. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK
174207. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
174208. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK
174209. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
174210. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK
174211. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
174212. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK
174213. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
174214. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK
174215. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
174216. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
174217. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
174218. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
174219. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
174220. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK
174221. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT
174222. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
174223. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
174224. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK
174225. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
174226. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK
174227. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT
174228. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
174229. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
174230. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK
174231. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
174232. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
174233. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
174234. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__NC76_MASK
174235. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT
174236. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
174237. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
174238. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__atb_select_MASK
174239. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT
174240. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK
174241. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT
174242. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK
174243. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT
174244. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK
174245. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
174246. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK
174247. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT
174248. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK
174249. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT
174250. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC40_MASK
174251. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC40__SHIFT
174252. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC76_MASK
174253. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC76__SHIFT
174254. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK
174255. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
174256. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK
174257. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT
174258. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
174259. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
174260. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK
174261. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT
174262. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK
174263. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT
174264. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
174265. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
174266. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK
174267. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
174268. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK
174269. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
174270. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
174271. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
174272. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK
174273. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
174274. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK
174275. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT
174276. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
174277. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
174278. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK
174279. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT
174280. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK
174281. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
174282. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK
174283. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
174284. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK
174285. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
174286. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
174287. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
174288. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
174289. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
174290. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
174291. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
174292. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK
174293. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
174294. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
174295. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
174296. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
174297. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
174298. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
174299. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
174300. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
174301. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
174302. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK
174303. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
174304. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
174305. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
174306. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
174307. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
174308. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
174309. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
174310. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
174311. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
174312. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
174313. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
174314. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
174315. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
174316. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
174317. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
174318. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
174319. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
174320. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
174321. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
174322. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
174323. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
174324. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
174325. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
174326. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
174327. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
174328. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
174329. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
174330. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
174331. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
174332. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
174333. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
174334. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
174335. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
174336. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
174337. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
174338. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
174339. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
174340. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
174341. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
174342. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
174343. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
174344. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
174345. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
174346. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
174347. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
174348. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
174349. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
174350. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
174351. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
174352. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
174353. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
174354. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
174355. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
174356. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
174357. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
174358. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
174359. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
174360. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
174361. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
174362. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
174363. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
174364. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
174365. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
174366. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
174367. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
174368. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
174369. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
174370. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
174371. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
174372. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
174373. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
174374. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
174375. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
174376. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
174377. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
174378. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
174379. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
174380. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
174381. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
174382. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
174383. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
174384. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
174385. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
174386. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
174387. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
174388. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
174389. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
174390. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK
174391. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT
174392. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
174393. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
174394. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__BG_EN_MASK
174395. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__BG_EN__SHIFT
174396. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK
174397. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT
174398. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK
174399. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT
174400. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK
174401. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT
174402. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
174403. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
174404. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK
174405. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT
174406. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
174407. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
174408. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK
174409. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT
174410. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK
174411. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT
174412. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK
174413. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
174414. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK
174415. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT
174416. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK
174417. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
174418. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK
174419. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT
174420. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK
174421. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT
174422. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK
174423. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT
174424. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK
174425. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
174426. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI__data_MASK
174427. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI__data__SHIFT
174428. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO__data_MASK
174429. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO__data__SHIFT
174430. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
174431. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
174432. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
174433. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
174434. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
174435. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
174436. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
174437. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
174438. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
174439. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
174440. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
174441. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
174442. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
174443. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
174444. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
174445. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
174446. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
174447. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
174448. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
174449. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
174450. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
174451. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
174452. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
174453. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
174454. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
174455. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
174456. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
174457. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
174458. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
174459. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
174460. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
174461. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
174462. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
174463. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
174464. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
174465. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
174466. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
174467. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
174468. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
174469. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
174470. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
174471. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
174472. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
174473. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
174474. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
174475. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
174476. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
174477. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
174478. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
174479. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
174480. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
174481. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
174482. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
174483. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
174484. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
174485. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
174486. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
174487. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
174488. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
174489. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
174490. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
174491. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
174492. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
174493. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
174494. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
174495. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
174496. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
174497. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
174498. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
174499. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
174500. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
174501. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
174502. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
174503. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
174504. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
174505. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
174506. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
174507. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
174508. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
174509. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
174510. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
174511. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
174512. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
174513. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
174514. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
174515. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
174516. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
174517. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
174518. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
174519. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
174520. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
174521. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
174522. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
174523. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
174524. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
174525. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
174526. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
174527. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
174528. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
174529. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
174530. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
174531. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
174532. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
174533. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
174534. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
174535. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
174536. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
174537. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
174538. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
174539. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
174540. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
174541. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
174542. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
174543. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
174544. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
174545. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
174546. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
174547. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
174548. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
174549. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
174550. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
174551. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
174552. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
174553. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
174554. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
174555. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
174556. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
174557. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
174558. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
174559. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
174560. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
174561. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
174562. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
174563. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
174564. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
174565. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
174566. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
174567. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
174568. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
174569. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
174570. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
174571. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
174572. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
174573. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
174574. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
174575. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
174576. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
174577. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
174578. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
174579. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
174580. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
174581. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
174582. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
174583. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
174584. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
174585. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
174586. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
174587. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
174588. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
174589. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
174590. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
174591. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
174592. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
174593. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
174594. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
174595. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
174596. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
174597. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
174598. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
174599. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
174600. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
174601. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
174602. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
174603. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
174604. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
174605. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
174606. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
174607. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
174608. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
174609. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
174610. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
174611. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
174612. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
174613. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
174614. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
174615. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
174616. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
174617. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
174618. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
174619. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
174620. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
174621. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
174622. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
174623. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
174624. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
174625. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
174626. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
174627. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
174628. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
174629. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
174630. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
174631. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
174632. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
174633. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
174634. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
174635. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
174636. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
174637. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
174638. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
174639. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
174640. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
174641. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
174642. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
174643. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
174644. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
174645. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
174646. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
174647. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
174648. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
174649. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
174650. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
174651. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
174652. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
174653. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
174654. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
174655. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
174656. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
174657. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
174658. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
174659. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
174660. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
174661. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
174662. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
174663. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
174664. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
174665. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
174666. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
174667. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
174668. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
174669. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
174670. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
174671. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
174672. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
174673. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
174674. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
174675. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
174676. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
174677. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
174678. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
174679. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
174680. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
174681. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
174682. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
174683. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
174684. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
174685. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
174686. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
174687. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
174688. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
174689. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
174690. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
174691. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
174692. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
174693. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
174694. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
174695. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
174696. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
174697. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
174698. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
174699. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
174700. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
174701. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
174702. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
174703. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
174704. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
174705. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
174706. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
174707. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
174708. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
174709. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
174710. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
174711. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
174712. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
174713. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
174714. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
174715. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
174716. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
174717. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
174718. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
174719. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
174720. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
174721. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
174722. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
174723. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
174724. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
174725. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
174726. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
174727. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
174728. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
174729. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
174730. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
174731. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
174732. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
174733. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
174734. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
174735. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
174736. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
174737. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
174738. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
174739. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
174740. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
174741. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
174742. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
174743. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
174744. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
174745. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
174746. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
174747. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
174748. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
174749. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
174750. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
174751. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
174752. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
174753. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
174754. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
174755. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
174756. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
174757. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
174758. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
174759. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
174760. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
174761. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
174762. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
174763. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
174764. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
174765. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
174766. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
174767. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
174768. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
174769. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
174770. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
174771. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
174772. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
174773. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
174774. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK
174775. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
174776. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
174777. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
174778. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
174779. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
174780. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
174781. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
174782. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
174783. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
174784. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
174785. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
174786. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
174787. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
174788. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
174789. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
174790. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
174791. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
174792. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
174793. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
174794. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
174795. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
174796. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
174797. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
174798. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
174799. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
174800. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
174801. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
174802. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK
174803. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
174804. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK
174805. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
174806. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK
174807. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
174808. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__STAT_MASK
174809. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT
174810. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
174811. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
174812. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
174813. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
174814. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
174815. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
174816. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
174817. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
174818. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
174819. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
174820. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
174821. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
174822. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
174823. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
174824. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
174825. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
174826. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
174827. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
174828. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
174829. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
174830. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
174831. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
174832. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
174833. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
174834. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
174835. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
174836. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
174837. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
174838. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
174839. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
174840. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
174841. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
174842. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
174843. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
174844. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
174845. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
174846. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
174847. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
174848. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
174849. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
174850. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
174851. DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
174852. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__NC74_MASK
174853. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__NC74__SHIFT
174854. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__RESERVED_15_8_MASK
174855. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__RESERVED_15_8__SHIFT
174856. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__bypass_bg_MASK
174857. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__bypass_bg__SHIFT
174858. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__chop_en_MASK
174859. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__chop_en__SHIFT
174860. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__vref_sel_fastreg_MASK
174861. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__vref_sel_fastreg__SHIFT
174862. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
174863. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
174864. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK
174865. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
174866. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK
174867. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
174868. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
174869. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
174870. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK
174871. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
174872. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK
174873. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
174874. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK
174875. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
174876. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK
174877. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
174878. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK
174879. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
174880. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
174881. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
174882. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
174883. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
174884. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_gd_MASK
174885. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT
174886. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
174887. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
174888. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK
174889. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
174890. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vp_MASK
174891. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT
174892. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
174893. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
174894. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK
174895. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
174896. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
174897. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
174898. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__NC76_MASK
174899. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__NC76__SHIFT
174900. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
174901. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
174902. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__atb_select_MASK
174903. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT
174904. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK
174905. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT
174906. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK
174907. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT
174908. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK
174909. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
174910. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK
174911. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT
174912. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK
174913. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT
174914. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC40_MASK
174915. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC40__SHIFT
174916. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC76_MASK
174917. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC76__SHIFT
174918. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK
174919. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
174920. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK
174921. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT
174922. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
174923. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
174924. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__cal_reg_MASK
174925. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT
174926. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__enable_reg_MASK
174927. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT
174928. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
174929. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
174930. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK
174931. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
174932. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK
174933. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
174934. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
174935. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
174936. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK
174937. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
174938. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__reset_reg_MASK
174939. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT
174940. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
174941. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
174942. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK
174943. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
174944. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK
174945. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
174946. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
174947. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
174948. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK
174949. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
174950. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK
174951. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
174952. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK
174953. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
174954. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK
174955. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
174956. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK
174957. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
174958. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
174959. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
174960. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
174961. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
174962. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_gd_MASK
174963. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT
174964. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
174965. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
174966. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK
174967. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
174968. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vp_MASK
174969. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT
174970. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
174971. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
174972. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK
174973. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
174974. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
174975. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
174976. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__NC76_MASK
174977. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__NC76__SHIFT
174978. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
174979. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
174980. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__atb_select_MASK
174981. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT
174982. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK
174983. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT
174984. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK
174985. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT
174986. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK
174987. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
174988. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK
174989. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT
174990. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK
174991. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT
174992. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC40_MASK
174993. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC40__SHIFT
174994. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC76_MASK
174995. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC76__SHIFT
174996. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK
174997. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
174998. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK
174999. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT
175000. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
175001. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
175002. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__cal_reg_MASK
175003. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT
175004. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__enable_reg_MASK
175005. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT
175006. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
175007. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
175008. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK
175009. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
175010. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK
175011. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
175012. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
175013. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
175014. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK
175015. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
175016. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__reset_reg_MASK
175017. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT
175018. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
175019. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
175020. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_atb_MASK
175021. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT
175022. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK
175023. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
175024. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK
175025. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
175026. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK
175027. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
175028. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
175029. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
175030. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
175031. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
175032. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
175033. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
175034. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK
175035. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
175036. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
175037. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
175038. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
175039. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
175040. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
175041. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
175042. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
175043. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
175044. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK
175045. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
175046. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
175047. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
175048. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
175049. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
175050. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
175051. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
175052. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
175053. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
175054. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
175055. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
175056. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
175057. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
175058. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
175059. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
175060. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
175061. DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
175062. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
175063. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
175064. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
175065. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
175066. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
175067. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
175068. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
175069. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
175070. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
175071. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
175072. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
175073. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
175074. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
175075. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
175076. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
175077. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
175078. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
175079. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
175080. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
175081. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
175082. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
175083. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
175084. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
175085. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
175086. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
175087. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
175088. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
175089. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
175090. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
175091. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
175092. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
175093. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
175094. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
175095. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
175096. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
175097. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
175098. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
175099. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
175100. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
175101. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
175102. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
175103. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
175104. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
175105. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
175106. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
175107. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
175108. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
175109. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
175110. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
175111. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
175112. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
175113. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
175114. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
175115. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
175116. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
175117. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
175118. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
175119. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
175120. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
175121. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
175122. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
175123. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
175124. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
175125. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
175126. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
175127. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
175128. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
175129. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
175130. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
175131. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
175132. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK
175133. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT
175134. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
175135. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
175136. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__BG_EN_MASK
175137. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__BG_EN__SHIFT
175138. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK
175139. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT
175140. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK
175141. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT
175142. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__PHY_RESET_MASK
175143. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT
175144. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
175145. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
175146. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK
175147. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT
175148. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
175149. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
175150. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK
175151. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT
175152. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK
175153. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT
175154. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK
175155. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
175156. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK
175157. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT
175158. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK
175159. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
175160. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK
175161. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT
175162. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK
175163. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT
175164. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK
175165. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT
175166. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK
175167. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
175168. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI__data_MASK
175169. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI__data__SHIFT
175170. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO__data_MASK
175171. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO__data__SHIFT
175172. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
175173. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
175174. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
175175. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
175176. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
175177. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
175178. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
175179. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
175180. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
175181. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
175182. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
175183. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
175184. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
175185. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
175186. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
175187. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
175188. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
175189. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
175190. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
175191. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
175192. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
175193. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
175194. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
175195. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
175196. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
175197. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
175198. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
175199. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
175200. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
175201. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
175202. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
175203. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
175204. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
175205. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
175206. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
175207. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
175208. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
175209. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
175210. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
175211. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
175212. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
175213. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
175214. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
175215. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
175216. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
175217. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
175218. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
175219. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
175220. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
175221. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
175222. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
175223. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
175224. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
175225. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
175226. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
175227. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
175228. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
175229. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
175230. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
175231. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
175232. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
175233. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
175234. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
175235. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
175236. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
175237. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
175238. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
175239. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
175240. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
175241. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
175242. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
175243. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
175244. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
175245. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
175246. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
175247. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
175248. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
175249. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
175250. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
175251. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
175252. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
175253. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
175254. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
175255. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
175256. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
175257. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
175258. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
175259. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
175260. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
175261. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
175262. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
175263. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
175264. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
175265. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
175266. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
175267. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
175268. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
175269. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
175270. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
175271. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
175272. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
175273. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
175274. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
175275. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
175276. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
175277. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
175278. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
175279. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
175280. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
175281. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
175282. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
175283. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
175284. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
175285. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
175286. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
175287. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
175288. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
175289. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
175290. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
175291. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
175292. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
175293. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
175294. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
175295. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
175296. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
175297. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
175298. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
175299. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
175300. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
175301. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
175302. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
175303. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
175304. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
175305. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
175306. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
175307. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
175308. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
175309. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
175310. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
175311. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
175312. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
175313. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
175314. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
175315. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
175316. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
175317. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
175318. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
175319. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
175320. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
175321. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
175322. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
175323. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
175324. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
175325. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
175326. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
175327. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
175328. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
175329. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
175330. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
175331. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
175332. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
175333. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
175334. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
175335. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
175336. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
175337. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
175338. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
175339. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
175340. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
175341. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
175342. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
175343. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
175344. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
175345. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
175346. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
175347. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
175348. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
175349. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
175350. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
175351. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
175352. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
175353. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
175354. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
175355. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
175356. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
175357. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
175358. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
175359. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
175360. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
175361. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
175362. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
175363. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
175364. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
175365. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
175366. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
175367. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
175368. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
175369. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
175370. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
175371. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
175372. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
175373. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
175374. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
175375. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
175376. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
175377. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
175378. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
175379. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
175380. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
175381. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
175382. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
175383. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
175384. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
175385. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
175386. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
175387. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
175388. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
175389. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
175390. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
175391. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
175392. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
175393. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
175394. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
175395. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
175396. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
175397. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
175398. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
175399. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
175400. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
175401. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
175402. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
175403. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
175404. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
175405. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
175406. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
175407. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
175408. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
175409. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
175410. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
175411. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
175412. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
175413. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
175414. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
175415. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
175416. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
175417. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
175418. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
175419. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
175420. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
175421. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
175422. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
175423. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
175424. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
175425. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
175426. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
175427. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
175428. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
175429. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
175430. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
175431. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
175432. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
175433. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
175434. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
175435. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
175436. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
175437. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
175438. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
175439. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
175440. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
175441. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
175442. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
175443. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
175444. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
175445. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
175446. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
175447. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
175448. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
175449. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
175450. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
175451. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
175452. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
175453. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
175454. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
175455. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
175456. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
175457. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
175458. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
175459. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
175460. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
175461. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
175462. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
175463. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
175464. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
175465. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
175466. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
175467. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
175468. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
175469. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
175470. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
175471. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
175472. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
175473. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
175474. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
175475. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
175476. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
175477. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
175478. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
175479. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
175480. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
175481. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
175482. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
175483. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
175484. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
175485. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
175486. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
175487. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
175488. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
175489. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
175490. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
175491. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
175492. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
175493. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
175494. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
175495. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
175496. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
175497. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
175498. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
175499. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
175500. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
175501. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
175502. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
175503. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
175504. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
175505. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
175506. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
175507. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
175508. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
175509. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
175510. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
175511. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
175512. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
175513. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
175514. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
175515. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
175516. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK
175517. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
175518. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
175519. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
175520. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
175521. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
175522. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
175523. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
175524. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
175525. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
175526. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
175527. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
175528. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
175529. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
175530. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
175531. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
175532. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
175533. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
175534. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
175535. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
175536. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
175537. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
175538. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
175539. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
175540. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
175541. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
175542. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
175543. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
175544. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK
175545. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
175546. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK
175547. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
175548. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK
175549. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
175550. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__STAT_MASK
175551. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__STAT__SHIFT
175552. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
175553. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
175554. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
175555. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
175556. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
175557. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
175558. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
175559. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
175560. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
175561. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
175562. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
175563. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
175564. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
175565. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
175566. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
175567. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
175568. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
175569. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
175570. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
175571. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
175572. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
175573. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
175574. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
175575. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
175576. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
175577. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
175578. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
175579. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
175580. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
175581. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
175582. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
175583. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
175584. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
175585. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
175586. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
175587. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
175588. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
175589. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
175590. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
175591. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
175592. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
175593. DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
175594. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
175595. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
175596. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
175597. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
175598. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
175599. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
175600. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
175601. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
175602. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
175603. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
175604. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK
175605. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT
175606. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
175607. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
175608. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
175609. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
175610. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
175611. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
175612. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
175613. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
175614. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
175615. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
175616. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
175617. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
175618. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
175619. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
175620. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
175621. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
175622. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
175623. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
175624. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
175625. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
175626. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
175627. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
175628. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
175629. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
175630. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
175631. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
175632. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
175633. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
175634. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
175635. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
175636. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK
175637. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
175638. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK
175639. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
175640. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK
175641. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
175642. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
175643. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
175644. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
175645. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
175646. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
175647. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
175648. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
175649. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
175650. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
175651. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
175652. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
175653. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
175654. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
175655. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
175656. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
175657. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
175658. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
175659. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
175660. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
175661. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
175662. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
175663. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
175664. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
175665. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
175666. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
175667. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
175668. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
175669. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
175670. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
175671. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
175672. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
175673. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
175674. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
175675. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
175676. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
175677. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
175678. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
175679. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
175680. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
175681. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
175682. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK
175683. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
175684. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK
175685. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
175686. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
175687. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
175688. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
175689. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
175690. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
175691. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
175692. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
175693. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
175694. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK
175695. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
175696. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
175697. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
175698. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
175699. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
175700. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
175701. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
175702. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
175703. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
175704. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
175705. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
175706. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__NC32_MASK
175707. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT
175708. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
175709. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
175710. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
175711. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
175712. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
175713. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
175714. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
175715. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
175716. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
175717. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
175718. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK
175719. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
175720. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
175721. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
175722. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
175723. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
175724. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
175725. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
175726. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
175727. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
175728. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
175729. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
175730. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK
175731. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
175732. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
175733. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
175734. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
175735. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
175736. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
175737. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
175738. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
175739. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
175740. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK
175741. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT
175742. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
175743. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
175744. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
175745. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
175746. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
175747. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
175748. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
175749. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
175750. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
175751. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
175752. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
175753. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
175754. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
175755. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
175756. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
175757. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
175758. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
175759. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
175760. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
175761. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
175762. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__NC20_MASK
175763. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__NC20__SHIFT
175764. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK
175765. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT
175766. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
175767. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
175768. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
175769. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
175770. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
175771. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
175772. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK
175773. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
175774. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK
175775. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
175776. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
175777. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
175778. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK
175779. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
175780. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK
175781. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
175782. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK
175783. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT
175784. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
175785. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
175786. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK
175787. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT
175788. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK
175789. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT
175790. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
175791. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
175792. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK
175793. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT
175794. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_gd_MASK
175795. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_gd__SHIFT
175796. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccm_MASK
175797. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT
175798. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccp_MASK
175799. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT
175800. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vptx_MASK
175801. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT
175802. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg0_MASK
175803. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT
175804. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg1_MASK
175805. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT
175806. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK
175807. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT
175808. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__override_regref_0_MASK
175809. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT
175810. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK
175811. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT
175812. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_nbias_MASK
175813. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT
175814. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_pbias_MASK
175815. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT
175816. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK
175817. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT
175818. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfm_MASK
175819. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT
175820. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfp_MASK
175821. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT
175822. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsm_MASK
175823. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT
175824. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsp_MASK
175825. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT
175826. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_vcm_MASK
175827. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT
175828. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
175829. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
175830. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK
175831. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
175832. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
175833. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
175834. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
175835. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
175836. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
175837. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
175838. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
175839. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
175840. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK
175841. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT
175842. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK
175843. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
175844. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__nc_MASK
175845. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__nc__SHIFT
175846. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_nmos_MASK
175847. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_nmos__SHIFT
175848. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_pmos_MASK
175849. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_pmos__SHIFT
175850. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__override_rxdetref_MASK
175851. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT
175852. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
175853. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
175854. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
175855. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
175856. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
175857. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
175858. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
175859. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
175860. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK
175861. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
175862. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
175863. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
175864. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
175865. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
175866. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
175867. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
175868. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
175869. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
175870. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
175871. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
175872. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
175873. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
175874. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
175875. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
175876. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
175877. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
175878. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
175879. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
175880. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
175881. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
175882. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
175883. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
175884. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
175885. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
175886. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
175887. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
175888. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
175889. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
175890. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
175891. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
175892. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK
175893. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
175894. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK
175895. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
175896. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
175897. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
175898. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK
175899. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
175900. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
175901. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
175902. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
175903. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
175904. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK
175905. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
175906. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
175907. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
175908. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
175909. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
175910. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
175911. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
175912. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
175913. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
175914. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
175915. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
175916. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
175917. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
175918. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK
175919. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
175920. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK
175921. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT
175922. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_MASK
175923. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT
175924. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK
175925. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
175926. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
175927. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
175928. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK
175929. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
175930. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK
175931. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
175932. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK
175933. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
175934. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK
175935. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT
175936. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
175937. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
175938. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
175939. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
175940. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
175941. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
175942. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
175943. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
175944. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
175945. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
175946. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
175947. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
175948. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
175949. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
175950. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
175951. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
175952. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
175953. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
175954. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
175955. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
175956. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
175957. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
175958. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
175959. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
175960. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
175961. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
175962. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
175963. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
175964. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
175965. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
175966. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
175967. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
175968. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
175969. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
175970. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
175971. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
175972. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
175973. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
175974. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
175975. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
175976. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
175977. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
175978. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
175979. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
175980. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
175981. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
175982. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
175983. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
175984. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
175985. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
175986. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
175987. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
175988. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
175989. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
175990. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
175991. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
175992. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
175993. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
175994. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
175995. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
175996. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
175997. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
175998. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
175999. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
176000. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
176001. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
176002. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
176003. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
176004. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
176005. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
176006. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
176007. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
176008. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
176009. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
176010. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
176011. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
176012. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
176013. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
176014. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
176015. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
176016. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
176017. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
176018. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
176019. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
176020. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
176021. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
176022. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
176023. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
176024. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
176025. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
176026. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
176027. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
176028. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
176029. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
176030. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
176031. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
176032. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
176033. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
176034. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
176035. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
176036. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
176037. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
176038. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
176039. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
176040. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
176041. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
176042. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
176043. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
176044. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
176045. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
176046. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
176047. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
176048. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
176049. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
176050. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
176051. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
176052. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
176053. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
176054. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
176055. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
176056. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
176057. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
176058. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
176059. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
176060. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
176061. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
176062. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
176063. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
176064. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
176065. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
176066. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
176067. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
176068. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
176069. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
176070. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
176071. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
176072. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
176073. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
176074. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
176075. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
176076. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
176077. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
176078. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
176079. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
176080. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
176081. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
176082. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
176083. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
176084. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
176085. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
176086. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
176087. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
176088. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
176089. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
176090. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
176091. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
176092. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
176093. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
176094. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
176095. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
176096. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
176097. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
176098. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
176099. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
176100. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
176101. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
176102. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
176103. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
176104. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
176105. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
176106. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
176107. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
176108. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
176109. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
176110. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
176111. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
176112. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
176113. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
176114. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
176115. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
176116. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
176117. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
176118. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
176119. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
176120. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
176121. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
176122. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
176123. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
176124. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
176125. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
176126. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
176127. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
176128. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
176129. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
176130. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
176131. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
176132. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
176133. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
176134. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
176135. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
176136. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
176137. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
176138. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
176139. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
176140. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
176141. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
176142. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
176143. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
176144. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
176145. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
176146. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
176147. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
176148. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
176149. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
176150. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
176151. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
176152. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
176153. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
176154. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
176155. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
176156. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
176157. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
176158. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
176159. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
176160. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
176161. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
176162. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
176163. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
176164. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
176165. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
176166. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
176167. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
176168. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
176169. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
176170. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
176171. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
176172. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
176173. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
176174. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
176175. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
176176. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
176177. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
176178. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
176179. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
176180. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK
176181. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
176182. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
176183. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
176184. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
176185. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
176186. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
176187. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
176188. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
176189. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
176190. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
176191. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
176192. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
176193. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
176194. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
176195. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
176196. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
176197. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
176198. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
176199. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
176200. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
176201. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
176202. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
176203. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
176204. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
176205. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
176206. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
176207. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
176208. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
176209. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
176210. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
176211. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
176212. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
176213. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
176214. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
176215. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
176216. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
176217. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
176218. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
176219. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
176220. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
176221. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
176222. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
176223. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
176224. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
176225. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
176226. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
176227. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
176228. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
176229. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
176230. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
176231. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
176232. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
176233. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
176234. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
176235. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
176236. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
176237. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
176238. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
176239. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
176240. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
176241. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
176242. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
176243. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
176244. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
176245. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
176246. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
176247. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
176248. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
176249. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
176250. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
176251. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
176252. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
176253. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
176254. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
176255. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
176256. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
176257. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
176258. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
176259. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
176260. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
176261. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
176262. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
176263. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
176264. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
176265. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
176266. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
176267. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
176268. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
176269. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
176270. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
176271. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
176272. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
176273. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
176274. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
176275. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
176276. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
176277. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
176278. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
176279. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
176280. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
176281. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
176282. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
176283. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
176284. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
176285. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
176286. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
176287. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
176288. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
176289. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
176290. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
176291. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
176292. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
176293. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
176294. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
176295. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
176296. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
176297. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
176298. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
176299. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
176300. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
176301. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
176302. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
176303. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
176304. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
176305. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
176306. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
176307. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
176308. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
176309. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
176310. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
176311. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
176312. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
176313. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
176314. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
176315. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
176316. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
176317. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
176318. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
176319. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
176320. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
176321. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
176322. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
176323. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
176324. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
176325. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
176326. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
176327. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
176328. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
176329. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
176330. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
176331. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
176332. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
176333. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
176334. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
176335. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
176336. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
176337. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
176338. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
176339. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
176340. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
176341. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
176342. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
176343. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
176344. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
176345. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
176346. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
176347. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
176348. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
176349. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
176350. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
176351. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
176352. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
176353. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
176354. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
176355. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
176356. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
176357. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
176358. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
176359. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
176360. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
176361. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
176362. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
176363. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
176364. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
176365. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
176366. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
176367. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
176368. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
176369. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
176370. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
176371. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
176372. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
176373. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
176374. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
176375. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
176376. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
176377. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
176378. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
176379. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
176380. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
176381. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
176382. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
176383. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
176384. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
176385. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
176386. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
176387. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
176388. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
176389. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
176390. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
176391. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
176392. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
176393. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
176394. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
176395. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
176396. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
176397. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
176398. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
176399. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
176400. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
176401. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
176402. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
176403. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
176404. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
176405. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
176406. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
176407. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
176408. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
176409. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
176410. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
176411. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
176412. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
176413. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
176414. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
176415. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
176416. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
176417. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
176418. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
176419. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
176420. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
176421. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
176422. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
176423. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
176424. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
176425. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
176426. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
176427. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
176428. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
176429. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
176430. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
176431. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
176432. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
176433. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
176434. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
176435. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
176436. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
176437. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
176438. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
176439. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
176440. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
176441. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
176442. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
176443. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
176444. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
176445. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
176446. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
176447. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
176448. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
176449. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
176450. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
176451. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
176452. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
176453. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
176454. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
176455. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
176456. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
176457. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
176458. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
176459. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
176460. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
176461. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
176462. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
176463. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
176464. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
176465. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
176466. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
176467. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
176468. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
176469. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
176470. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
176471. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
176472. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
176473. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
176474. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
176475. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
176476. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
176477. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
176478. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
176479. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
176480. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
176481. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
176482. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
176483. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
176484. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
176485. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
176486. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
176487. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
176488. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
176489. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
176490. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
176491. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
176492. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
176493. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
176494. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
176495. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
176496. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
176497. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
176498. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
176499. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
176500. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
176501. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
176502. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
176503. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
176504. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
176505. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
176506. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
176507. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
176508. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
176509. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
176510. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
176511. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
176512. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
176513. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
176514. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
176515. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
176516. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
176517. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
176518. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
176519. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
176520. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
176521. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
176522. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
176523. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
176524. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
176525. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
176526. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
176527. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
176528. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
176529. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
176530. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
176531. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
176532. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
176533. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
176534. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
176535. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
176536. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
176537. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
176538. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
176539. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
176540. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
176541. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
176542. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
176543. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
176544. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
176545. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
176546. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
176547. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
176548. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
176549. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
176550. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
176551. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
176552. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
176553. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
176554. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
176555. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
176556. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
176557. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
176558. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
176559. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
176560. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
176561. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
176562. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
176563. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
176564. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
176565. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
176566. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
176567. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
176568. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
176569. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
176570. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
176571. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
176572. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
176573. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
176574. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
176575. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
176576. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
176577. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
176578. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
176579. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
176580. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
176581. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
176582. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
176583. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
176584. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
176585. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
176586. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
176587. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
176588. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
176589. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
176590. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
176591. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
176592. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
176593. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
176594. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
176595. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
176596. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
176597. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
176598. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
176599. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
176600. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
176601. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
176602. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
176603. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
176604. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
176605. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
176606. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
176607. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
176608. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
176609. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
176610. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
176611. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
176612. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
176613. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
176614. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
176615. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
176616. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
176617. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
176618. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
176619. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
176620. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
176621. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
176622. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
176623. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
176624. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
176625. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
176626. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
176627. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
176628. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
176629. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
176630. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
176631. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
176632. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
176633. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
176634. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
176635. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
176636. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
176637. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
176638. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
176639. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
176640. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
176641. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
176642. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
176643. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
176644. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
176645. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
176646. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
176647. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
176648. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
176649. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
176650. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
176651. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
176652. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
176653. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
176654. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
176655. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
176656. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
176657. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
176658. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
176659. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
176660. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
176661. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
176662. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
176663. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
176664. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
176665. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
176666. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
176667. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
176668. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
176669. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
176670. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
176671. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
176672. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
176673. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
176674. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
176675. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
176676. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
176677. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
176678. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
176679. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
176680. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
176681. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
176682. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
176683. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
176684. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
176685. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
176686. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
176687. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
176688. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
176689. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
176690. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
176691. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
176692. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
176693. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
176694. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
176695. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
176696. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
176697. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
176698. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
176699. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
176700. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
176701. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
176702. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
176703. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
176704. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
176705. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
176706. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
176707. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
176708. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
176709. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
176710. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
176711. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
176712. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
176713. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
176714. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
176715. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
176716. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
176717. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
176718. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
176719. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
176720. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
176721. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
176722. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
176723. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
176724. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
176725. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
176726. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
176727. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
176728. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
176729. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
176730. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
176731. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
176732. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
176733. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
176734. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
176735. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
176736. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK
176737. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT
176738. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__MODE_MASK
176739. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT
176740. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
176741. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
176742. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK
176743. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT
176744. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK
176745. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT
176746. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__OV14_MASK
176747. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT
176748. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
176749. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
176750. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
176751. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
176752. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
176753. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
176754. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
176755. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
176756. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
176757. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
176758. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
176759. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
176760. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
176761. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
176762. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
176763. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
176764. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
176765. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
176766. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
176767. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
176768. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
176769. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
176770. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
176771. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
176772. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
176773. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
176774. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
176775. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
176776. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
176777. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
176778. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
176779. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
176780. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
176781. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
176782. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
176783. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
176784. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
176785. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
176786. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
176787. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
176788. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
176789. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
176790. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
176791. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
176792. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
176793. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
176794. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
176795. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
176796. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
176797. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
176798. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
176799. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
176800. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
176801. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
176802. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
176803. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
176804. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
176805. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
176806. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
176807. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
176808. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
176809. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
176810. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
176811. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
176812. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
176813. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
176814. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
176815. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
176816. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
176817. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
176818. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
176819. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
176820. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
176821. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
176822. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
176823. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
176824. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
176825. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
176826. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
176827. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
176828. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
176829. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
176830. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
176831. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
176832. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
176833. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
176834. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
176835. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
176836. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
176837. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
176838. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
176839. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
176840. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
176841. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
176842. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
176843. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
176844. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
176845. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
176846. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
176847. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
176848. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
176849. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
176850. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
176851. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
176852. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
176853. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
176854. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
176855. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
176856. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
176857. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
176858. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
176859. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
176860. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
176861. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
176862. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
176863. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
176864. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
176865. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
176866. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
176867. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
176868. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
176869. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
176870. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
176871. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
176872. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
176873. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
176874. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
176875. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
176876. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
176877. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
176878. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
176879. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
176880. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
176881. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
176882. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
176883. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
176884. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
176885. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
176886. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
176887. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
176888. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
176889. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
176890. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
176891. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
176892. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
176893. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
176894. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
176895. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
176896. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
176897. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
176898. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
176899. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
176900. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
176901. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
176902. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
176903. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
176904. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
176905. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
176906. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
176907. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
176908. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
176909. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
176910. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
176911. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
176912. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
176913. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
176914. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
176915. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
176916. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
176917. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
176918. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
176919. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
176920. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
176921. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
176922. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
176923. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
176924. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
176925. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
176926. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
176927. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
176928. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
176929. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
176930. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
176931. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
176932. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
176933. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
176934. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
176935. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
176936. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
176937. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
176938. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
176939. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
176940. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
176941. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
176942. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
176943. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
176944. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
176945. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
176946. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
176947. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
176948. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
176949. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
176950. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
176951. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
176952. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
176953. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
176954. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
176955. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
176956. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
176957. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
176958. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
176959. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
176960. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
176961. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
176962. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
176963. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
176964. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
176965. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
176966. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
176967. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
176968. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
176969. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
176970. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
176971. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
176972. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
176973. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
176974. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
176975. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
176976. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
176977. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
176978. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
176979. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
176980. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
176981. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
176982. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
176983. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
176984. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
176985. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
176986. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
176987. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
176988. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
176989. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
176990. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
176991. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
176992. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
176993. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
176994. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
176995. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
176996. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
176997. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
176998. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
176999. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
177000. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
177001. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
177002. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
177003. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
177004. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
177005. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
177006. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
177007. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
177008. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
177009. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
177010. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
177011. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
177012. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
177013. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
177014. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
177015. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
177016. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
177017. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
177018. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
177019. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
177020. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
177021. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
177022. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
177023. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
177024. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
177025. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
177026. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
177027. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
177028. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
177029. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
177030. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
177031. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
177032. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
177033. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
177034. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
177035. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
177036. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
177037. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
177038. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
177039. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
177040. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
177041. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
177042. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
177043. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
177044. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
177045. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
177046. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
177047. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
177048. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
177049. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
177050. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
177051. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
177052. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
177053. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
177054. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
177055. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
177056. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
177057. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
177058. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
177059. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
177060. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
177061. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
177062. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
177063. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
177064. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
177065. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
177066. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
177067. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
177068. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
177069. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
177070. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
177071. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
177072. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
177073. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
177074. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
177075. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
177076. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
177077. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
177078. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
177079. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
177080. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
177081. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
177082. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
177083. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
177084. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
177085. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
177086. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
177087. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
177088. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
177089. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
177090. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK
177091. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT
177092. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK
177093. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT
177094. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
177095. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
177096. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
177097. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
177098. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
177099. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
177100. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
177101. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
177102. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
177103. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
177104. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
177105. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
177106. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
177107. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
177108. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
177109. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
177110. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
177111. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
177112. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
177113. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
177114. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
177115. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
177116. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
177117. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
177118. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
177119. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
177120. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
177121. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
177122. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
177123. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
177124. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
177125. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
177126. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
177127. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
177128. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
177129. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
177130. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
177131. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
177132. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
177133. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
177134. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
177135. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
177136. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
177137. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
177138. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
177139. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
177140. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
177141. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
177142. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
177143. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
177144. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
177145. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
177146. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
177147. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
177148. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
177149. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
177150. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
177151. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
177152. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
177153. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
177154. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
177155. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
177156. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
177157. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
177158. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
177159. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
177160. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
177161. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
177162. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
177163. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
177164. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
177165. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
177166. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
177167. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
177168. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
177169. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
177170. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
177171. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
177172. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
177173. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
177174. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
177175. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
177176. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
177177. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
177178. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
177179. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
177180. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
177181. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
177182. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
177183. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
177184. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
177185. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
177186. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
177187. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
177188. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
177189. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
177190. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
177191. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
177192. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
177193. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
177194. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
177195. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
177196. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
177197. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
177198. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
177199. DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
177200. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
177201. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
177202. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
177203. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
177204. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
177205. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
177206. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
177207. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
177208. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
177209. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
177210. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK
177211. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT
177212. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
177213. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
177214. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
177215. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
177216. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
177217. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
177218. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
177219. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
177220. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
177221. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
177222. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
177223. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
177224. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
177225. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
177226. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
177227. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
177228. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
177229. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
177230. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
177231. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
177232. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
177233. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
177234. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
177235. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
177236. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
177237. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
177238. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
177239. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
177240. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
177241. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
177242. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK
177243. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
177244. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK
177245. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
177246. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK
177247. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
177248. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
177249. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
177250. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
177251. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
177252. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
177253. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
177254. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
177255. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
177256. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
177257. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
177258. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
177259. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
177260. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
177261. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
177262. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
177263. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
177264. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
177265. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
177266. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
177267. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
177268. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
177269. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
177270. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
177271. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
177272. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
177273. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
177274. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
177275. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
177276. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
177277. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
177278. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
177279. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
177280. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
177281. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
177282. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
177283. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
177284. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
177285. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
177286. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
177287. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
177288. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK
177289. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
177290. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK
177291. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
177292. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
177293. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
177294. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
177295. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
177296. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
177297. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
177298. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
177299. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
177300. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK
177301. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
177302. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
177303. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
177304. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
177305. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
177306. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
177307. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
177308. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
177309. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
177310. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
177311. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
177312. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__NC32_MASK
177313. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT
177314. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
177315. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
177316. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
177317. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
177318. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
177319. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
177320. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
177321. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
177322. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
177323. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
177324. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK
177325. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
177326. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
177327. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
177328. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
177329. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
177330. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
177331. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
177332. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
177333. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
177334. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
177335. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
177336. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK
177337. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
177338. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
177339. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
177340. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
177341. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
177342. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
177343. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
177344. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
177345. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
177346. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK
177347. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT
177348. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
177349. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
177350. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
177351. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
177352. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
177353. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
177354. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
177355. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
177356. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
177357. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
177358. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
177359. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
177360. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
177361. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
177362. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
177363. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
177364. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
177365. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
177366. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
177367. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
177368. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__NC20_MASK
177369. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__NC20__SHIFT
177370. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK
177371. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT
177372. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
177373. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
177374. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
177375. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
177376. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
177377. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
177378. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK
177379. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
177380. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK
177381. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
177382. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
177383. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
177384. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK
177385. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
177386. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK
177387. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
177388. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK
177389. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT
177390. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
177391. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
177392. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK
177393. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT
177394. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK
177395. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT
177396. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
177397. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
177398. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK
177399. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT
177400. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_gd_MASK
177401. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_gd__SHIFT
177402. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccm_MASK
177403. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT
177404. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccp_MASK
177405. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT
177406. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vptx_MASK
177407. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT
177408. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg0_MASK
177409. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT
177410. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg1_MASK
177411. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT
177412. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK
177413. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT
177414. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__override_regref_0_MASK
177415. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT
177416. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK
177417. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT
177418. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_nbias_MASK
177419. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT
177420. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_pbias_MASK
177421. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT
177422. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK
177423. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT
177424. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfm_MASK
177425. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT
177426. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfp_MASK
177427. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT
177428. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsm_MASK
177429. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT
177430. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsp_MASK
177431. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT
177432. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_vcm_MASK
177433. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT
177434. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
177435. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
177436. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK
177437. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
177438. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
177439. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
177440. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
177441. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
177442. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
177443. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
177444. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
177445. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
177446. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK
177447. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT
177448. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK
177449. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
177450. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__nc_MASK
177451. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__nc__SHIFT
177452. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_nmos_MASK
177453. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_nmos__SHIFT
177454. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_pmos_MASK
177455. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_pmos__SHIFT
177456. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__override_rxdetref_MASK
177457. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT
177458. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
177459. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
177460. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
177461. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
177462. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
177463. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
177464. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
177465. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
177466. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK
177467. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
177468. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
177469. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
177470. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
177471. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
177472. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
177473. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
177474. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
177475. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
177476. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
177477. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
177478. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
177479. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
177480. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
177481. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
177482. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
177483. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
177484. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
177485. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
177486. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
177487. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
177488. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
177489. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
177490. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
177491. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
177492. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
177493. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
177494. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
177495. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
177496. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
177497. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
177498. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK
177499. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
177500. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK
177501. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
177502. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
177503. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
177504. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK
177505. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
177506. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
177507. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
177508. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
177509. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
177510. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK
177511. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
177512. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
177513. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
177514. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
177515. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
177516. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
177517. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
177518. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
177519. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
177520. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
177521. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
177522. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
177523. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
177524. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK
177525. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
177526. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK
177527. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT
177528. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_MASK
177529. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT
177530. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK
177531. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
177532. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
177533. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
177534. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK
177535. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
177536. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK
177537. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
177538. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK
177539. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
177540. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK
177541. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT
177542. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
177543. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
177544. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
177545. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
177546. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
177547. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
177548. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
177549. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
177550. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
177551. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
177552. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
177553. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
177554. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
177555. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
177556. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
177557. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
177558. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
177559. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
177560. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
177561. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
177562. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
177563. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
177564. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
177565. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
177566. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
177567. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
177568. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
177569. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
177570. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
177571. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
177572. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
177573. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
177574. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
177575. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
177576. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
177577. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
177578. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
177579. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
177580. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
177581. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
177582. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
177583. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
177584. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
177585. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
177586. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
177587. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
177588. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
177589. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
177590. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
177591. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
177592. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
177593. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
177594. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
177595. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
177596. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
177597. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
177598. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
177599. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
177600. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
177601. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
177602. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
177603. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
177604. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
177605. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
177606. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
177607. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
177608. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
177609. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
177610. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
177611. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
177612. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
177613. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
177614. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
177615. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
177616. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
177617. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
177618. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
177619. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
177620. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
177621. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
177622. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
177623. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
177624. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
177625. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
177626. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
177627. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
177628. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
177629. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
177630. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
177631. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
177632. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
177633. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
177634. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
177635. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
177636. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
177637. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
177638. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
177639. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
177640. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
177641. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
177642. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
177643. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
177644. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
177645. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
177646. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
177647. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
177648. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
177649. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
177650. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
177651. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
177652. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
177653. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
177654. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
177655. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
177656. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
177657. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
177658. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
177659. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
177660. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
177661. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
177662. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
177663. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
177664. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
177665. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
177666. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
177667. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
177668. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
177669. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
177670. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
177671. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
177672. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
177673. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
177674. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
177675. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
177676. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
177677. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
177678. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
177679. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
177680. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
177681. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
177682. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
177683. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
177684. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
177685. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
177686. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
177687. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
177688. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
177689. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
177690. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
177691. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
177692. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
177693. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
177694. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
177695. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
177696. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
177697. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
177698. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
177699. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
177700. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
177701. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
177702. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
177703. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
177704. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
177705. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
177706. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
177707. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
177708. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
177709. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
177710. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
177711. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
177712. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
177713. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
177714. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
177715. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
177716. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
177717. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
177718. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
177719. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
177720. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
177721. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
177722. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
177723. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
177724. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
177725. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
177726. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
177727. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
177728. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
177729. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
177730. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
177731. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
177732. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
177733. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
177734. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
177735. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
177736. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
177737. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
177738. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
177739. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
177740. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
177741. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
177742. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
177743. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
177744. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
177745. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
177746. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
177747. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
177748. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
177749. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
177750. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
177751. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
177752. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
177753. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
177754. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
177755. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
177756. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
177757. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
177758. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
177759. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
177760. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
177761. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
177762. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
177763. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
177764. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
177765. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
177766. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
177767. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
177768. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
177769. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
177770. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
177771. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
177772. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
177773. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
177774. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
177775. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
177776. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
177777. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
177778. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
177779. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
177780. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
177781. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
177782. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
177783. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
177784. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
177785. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
177786. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK
177787. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
177788. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
177789. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
177790. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
177791. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
177792. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
177793. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
177794. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
177795. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
177796. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
177797. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
177798. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
177799. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
177800. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
177801. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
177802. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
177803. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
177804. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
177805. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
177806. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
177807. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
177808. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
177809. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
177810. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
177811. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
177812. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
177813. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
177814. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
177815. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
177816. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
177817. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
177818. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
177819. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
177820. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
177821. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
177822. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
177823. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
177824. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
177825. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
177826. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
177827. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
177828. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
177829. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
177830. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
177831. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
177832. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
177833. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
177834. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
177835. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
177836. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
177837. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
177838. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
177839. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
177840. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
177841. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
177842. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
177843. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
177844. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
177845. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
177846. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
177847. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
177848. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
177849. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
177850. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
177851. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
177852. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
177853. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
177854. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
177855. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
177856. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
177857. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
177858. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
177859. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
177860. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
177861. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
177862. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
177863. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
177864. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
177865. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
177866. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
177867. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
177868. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
177869. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
177870. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
177871. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
177872. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
177873. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
177874. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
177875. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
177876. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
177877. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
177878. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
177879. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
177880. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
177881. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
177882. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
177883. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
177884. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
177885. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
177886. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
177887. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
177888. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
177889. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
177890. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
177891. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
177892. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
177893. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
177894. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
177895. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
177896. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
177897. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
177898. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
177899. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
177900. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
177901. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
177902. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
177903. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
177904. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
177905. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
177906. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
177907. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
177908. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
177909. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
177910. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
177911. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
177912. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
177913. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
177914. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
177915. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
177916. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
177917. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
177918. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
177919. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
177920. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
177921. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
177922. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
177923. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
177924. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
177925. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
177926. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
177927. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
177928. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
177929. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
177930. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
177931. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
177932. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
177933. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
177934. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
177935. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
177936. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
177937. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
177938. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
177939. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
177940. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
177941. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
177942. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
177943. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
177944. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
177945. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
177946. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
177947. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
177948. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
177949. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
177950. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
177951. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
177952. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
177953. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
177954. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
177955. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
177956. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
177957. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
177958. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
177959. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
177960. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
177961. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
177962. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
177963. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
177964. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
177965. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
177966. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
177967. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
177968. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
177969. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
177970. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
177971. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
177972. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
177973. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
177974. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
177975. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
177976. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
177977. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
177978. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
177979. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
177980. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
177981. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
177982. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
177983. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
177984. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
177985. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
177986. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
177987. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
177988. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
177989. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
177990. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
177991. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
177992. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
177993. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
177994. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
177995. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
177996. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
177997. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
177998. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
177999. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
178000. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
178001. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
178002. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
178003. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
178004. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
178005. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
178006. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
178007. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
178008. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
178009. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
178010. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
178011. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
178012. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
178013. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
178014. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
178015. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
178016. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
178017. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
178018. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
178019. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
178020. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
178021. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
178022. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
178023. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
178024. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
178025. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
178026. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
178027. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
178028. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
178029. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
178030. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
178031. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
178032. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
178033. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
178034. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
178035. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
178036. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
178037. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
178038. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
178039. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
178040. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
178041. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
178042. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
178043. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
178044. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
178045. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
178046. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
178047. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
178048. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
178049. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
178050. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
178051. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
178052. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
178053. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
178054. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
178055. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
178056. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
178057. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
178058. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
178059. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
178060. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
178061. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
178062. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
178063. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
178064. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
178065. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
178066. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
178067. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
178068. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
178069. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
178070. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
178071. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
178072. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
178073. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
178074. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
178075. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
178076. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
178077. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
178078. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
178079. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
178080. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
178081. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
178082. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
178083. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
178084. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
178085. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
178086. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
178087. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
178088. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
178089. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
178090. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
178091. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
178092. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
178093. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
178094. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
178095. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
178096. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
178097. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
178098. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
178099. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
178100. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
178101. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
178102. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
178103. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
178104. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
178105. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
178106. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
178107. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
178108. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
178109. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
178110. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
178111. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
178112. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
178113. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
178114. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
178115. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
178116. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
178117. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
178118. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
178119. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
178120. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
178121. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
178122. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
178123. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
178124. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
178125. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
178126. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
178127. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
178128. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
178129. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
178130. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
178131. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
178132. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
178133. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
178134. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
178135. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
178136. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
178137. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
178138. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
178139. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
178140. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
178141. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
178142. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
178143. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
178144. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
178145. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
178146. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
178147. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
178148. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
178149. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
178150. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
178151. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
178152. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
178153. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
178154. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
178155. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
178156. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
178157. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
178158. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
178159. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
178160. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
178161. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
178162. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
178163. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
178164. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
178165. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
178166. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
178167. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
178168. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
178169. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
178170. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
178171. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
178172. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
178173. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
178174. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
178175. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
178176. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
178177. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
178178. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
178179. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
178180. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
178181. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
178182. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
178183. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
178184. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
178185. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
178186. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
178187. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
178188. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
178189. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
178190. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
178191. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
178192. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
178193. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
178194. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
178195. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
178196. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
178197. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
178198. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
178199. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
178200. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
178201. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
178202. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
178203. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
178204. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
178205. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
178206. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
178207. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
178208. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
178209. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
178210. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
178211. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
178212. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
178213. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
178214. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
178215. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
178216. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
178217. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
178218. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
178219. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
178220. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
178221. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
178222. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
178223. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
178224. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
178225. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
178226. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
178227. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
178228. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
178229. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
178230. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
178231. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
178232. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
178233. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
178234. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
178235. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
178236. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
178237. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
178238. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
178239. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
178240. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
178241. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
178242. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
178243. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
178244. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
178245. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
178246. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
178247. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
178248. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
178249. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
178250. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
178251. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
178252. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
178253. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
178254. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
178255. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
178256. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
178257. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
178258. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
178259. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
178260. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
178261. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
178262. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
178263. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
178264. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
178265. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
178266. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
178267. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
178268. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
178269. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
178270. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
178271. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
178272. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
178273. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
178274. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
178275. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
178276. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
178277. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
178278. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
178279. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
178280. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
178281. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
178282. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
178283. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
178284. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
178285. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
178286. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
178287. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
178288. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
178289. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
178290. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
178291. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
178292. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
178293. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
178294. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
178295. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
178296. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
178297. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
178298. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
178299. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
178300. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
178301. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
178302. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
178303. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
178304. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
178305. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
178306. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
178307. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
178308. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
178309. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
178310. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
178311. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
178312. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
178313. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
178314. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
178315. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
178316. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
178317. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
178318. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
178319. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
178320. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
178321. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
178322. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
178323. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
178324. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
178325. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
178326. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
178327. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
178328. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
178329. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
178330. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
178331. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
178332. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
178333. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
178334. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
178335. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
178336. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
178337. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
178338. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
178339. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
178340. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
178341. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
178342. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK
178343. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT
178344. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK
178345. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT
178346. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
178347. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
178348. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK
178349. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT
178350. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK
178351. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT
178352. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK
178353. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT
178354. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
178355. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
178356. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
178357. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
178358. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
178359. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
178360. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
178361. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
178362. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
178363. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
178364. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
178365. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
178366. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
178367. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
178368. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
178369. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
178370. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
178371. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
178372. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
178373. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
178374. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
178375. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
178376. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
178377. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
178378. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
178379. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
178380. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
178381. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
178382. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
178383. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
178384. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
178385. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
178386. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
178387. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
178388. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
178389. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
178390. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
178391. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
178392. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
178393. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
178394. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
178395. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
178396. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
178397. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
178398. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
178399. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
178400. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
178401. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
178402. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
178403. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
178404. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
178405. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
178406. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
178407. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
178408. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
178409. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
178410. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
178411. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
178412. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
178413. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
178414. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
178415. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
178416. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
178417. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
178418. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
178419. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
178420. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
178421. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
178422. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
178423. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
178424. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
178425. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
178426. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
178427. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
178428. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
178429. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
178430. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
178431. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
178432. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
178433. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
178434. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
178435. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
178436. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
178437. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
178438. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
178439. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
178440. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
178441. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
178442. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
178443. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
178444. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
178445. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
178446. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
178447. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
178448. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
178449. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
178450. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
178451. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
178452. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
178453. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
178454. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
178455. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
178456. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
178457. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
178458. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
178459. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
178460. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
178461. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
178462. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
178463. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
178464. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
178465. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
178466. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
178467. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
178468. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
178469. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
178470. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
178471. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
178472. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
178473. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
178474. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
178475. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
178476. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
178477. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
178478. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
178479. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
178480. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
178481. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
178482. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
178483. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
178484. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
178485. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
178486. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
178487. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
178488. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
178489. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
178490. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
178491. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
178492. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
178493. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
178494. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
178495. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
178496. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
178497. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
178498. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
178499. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
178500. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
178501. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
178502. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
178503. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
178504. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
178505. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
178506. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
178507. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
178508. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
178509. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
178510. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
178511. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
178512. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
178513. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
178514. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
178515. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
178516. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
178517. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
178518. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
178519. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
178520. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
178521. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
178522. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
178523. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
178524. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
178525. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
178526. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
178527. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
178528. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
178529. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
178530. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
178531. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
178532. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
178533. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
178534. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
178535. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
178536. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
178537. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
178538. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
178539. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
178540. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
178541. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
178542. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
178543. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
178544. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
178545. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
178546. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
178547. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
178548. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
178549. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
178550. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
178551. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
178552. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
178553. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
178554. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
178555. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
178556. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
178557. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
178558. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
178559. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
178560. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
178561. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
178562. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
178563. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
178564. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
178565. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
178566. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
178567. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
178568. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
178569. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
178570. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
178571. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
178572. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
178573. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
178574. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
178575. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
178576. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
178577. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
178578. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
178579. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
178580. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
178581. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
178582. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
178583. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
178584. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
178585. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
178586. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
178587. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
178588. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
178589. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
178590. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
178591. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
178592. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
178593. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
178594. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
178595. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
178596. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
178597. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
178598. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
178599. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
178600. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
178601. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
178602. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
178603. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
178604. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
178605. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
178606. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
178607. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
178608. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
178609. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
178610. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
178611. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
178612. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
178613. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
178614. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
178615. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
178616. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
178617. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
178618. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
178619. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
178620. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
178621. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
178622. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
178623. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
178624. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
178625. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
178626. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
178627. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
178628. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
178629. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
178630. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
178631. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
178632. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
178633. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
178634. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
178635. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
178636. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
178637. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
178638. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
178639. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
178640. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
178641. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
178642. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
178643. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
178644. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
178645. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
178646. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
178647. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
178648. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
178649. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
178650. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
178651. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
178652. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
178653. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
178654. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
178655. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
178656. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
178657. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
178658. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
178659. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
178660. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
178661. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
178662. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
178663. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
178664. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
178665. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
178666. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
178667. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
178668. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
178669. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
178670. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
178671. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
178672. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
178673. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
178674. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
178675. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
178676. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
178677. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
178678. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
178679. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
178680. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
178681. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
178682. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
178683. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
178684. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
178685. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
178686. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
178687. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
178688. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
178689. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
178690. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
178691. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
178692. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
178693. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
178694. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
178695. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
178696. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK
178697. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT
178698. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK
178699. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT
178700. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
178701. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
178702. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
178703. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
178704. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
178705. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
178706. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
178707. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
178708. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
178709. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
178710. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
178711. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
178712. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
178713. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
178714. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
178715. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
178716. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
178717. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
178718. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
178719. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
178720. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
178721. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
178722. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
178723. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
178724. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
178725. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
178726. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
178727. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
178728. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
178729. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
178730. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
178731. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
178732. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
178733. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
178734. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
178735. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
178736. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
178737. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
178738. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
178739. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
178740. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
178741. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
178742. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
178743. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
178744. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
178745. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
178746. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
178747. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
178748. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
178749. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
178750. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
178751. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
178752. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
178753. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
178754. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
178755. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
178756. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
178757. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
178758. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
178759. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
178760. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
178761. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
178762. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
178763. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
178764. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
178765. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
178766. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
178767. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
178768. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
178769. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
178770. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
178771. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
178772. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
178773. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
178774. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
178775. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
178776. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
178777. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
178778. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
178779. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
178780. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
178781. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
178782. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
178783. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
178784. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
178785. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
178786. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
178787. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
178788. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
178789. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
178790. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
178791. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
178792. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
178793. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
178794. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
178795. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
178796. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
178797. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
178798. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
178799. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
178800. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
178801. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
178802. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
178803. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
178804. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
178805. DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
178806. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
178807. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
178808. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
178809. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
178810. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
178811. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
178812. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
178813. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
178814. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
178815. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
178816. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK
178817. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT
178818. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
178819. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
178820. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
178821. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
178822. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
178823. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
178824. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
178825. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
178826. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
178827. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
178828. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
178829. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
178830. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
178831. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
178832. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
178833. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
178834. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
178835. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
178836. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
178837. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
178838. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
178839. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
178840. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
178841. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
178842. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
178843. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
178844. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
178845. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
178846. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
178847. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
178848. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK
178849. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
178850. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK
178851. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
178852. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK
178853. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
178854. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
178855. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
178856. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
178857. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
178858. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
178859. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
178860. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
178861. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
178862. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
178863. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
178864. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
178865. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
178866. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
178867. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
178868. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
178869. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
178870. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
178871. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
178872. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
178873. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
178874. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
178875. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
178876. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
178877. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
178878. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
178879. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
178880. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
178881. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
178882. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
178883. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
178884. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
178885. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
178886. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
178887. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
178888. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
178889. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
178890. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
178891. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
178892. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
178893. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
178894. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK
178895. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
178896. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK
178897. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
178898. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
178899. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
178900. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
178901. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
178902. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
178903. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
178904. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
178905. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
178906. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK
178907. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
178908. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
178909. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
178910. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
178911. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
178912. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
178913. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
178914. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
178915. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
178916. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
178917. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
178918. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__NC32_MASK
178919. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT
178920. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
178921. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
178922. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
178923. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
178924. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
178925. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
178926. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
178927. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
178928. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
178929. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
178930. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK
178931. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
178932. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
178933. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
178934. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
178935. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
178936. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
178937. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
178938. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
178939. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
178940. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
178941. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
178942. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK
178943. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
178944. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
178945. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
178946. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
178947. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
178948. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
178949. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
178950. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
178951. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
178952. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK
178953. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT
178954. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
178955. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
178956. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
178957. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
178958. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
178959. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
178960. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
178961. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
178962. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
178963. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
178964. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
178965. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
178966. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
178967. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
178968. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
178969. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
178970. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
178971. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
178972. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
178973. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
178974. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__NC20_MASK
178975. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__NC20__SHIFT
178976. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK
178977. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT
178978. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
178979. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
178980. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
178981. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
178982. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
178983. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
178984. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK
178985. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
178986. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK
178987. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
178988. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
178989. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
178990. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK
178991. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
178992. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK
178993. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
178994. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK
178995. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT
178996. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
178997. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
178998. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK
178999. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT
179000. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK
179001. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT
179002. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
179003. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
179004. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK
179005. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT
179006. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_gd_MASK
179007. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_gd__SHIFT
179008. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccm_MASK
179009. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT
179010. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccp_MASK
179011. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT
179012. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vptx_MASK
179013. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT
179014. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg0_MASK
179015. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT
179016. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg1_MASK
179017. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT
179018. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK
179019. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT
179020. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__override_regref_0_MASK
179021. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT
179022. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK
179023. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT
179024. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_nbias_MASK
179025. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT
179026. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_pbias_MASK
179027. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT
179028. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK
179029. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT
179030. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfm_MASK
179031. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT
179032. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfp_MASK
179033. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT
179034. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsm_MASK
179035. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT
179036. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsp_MASK
179037. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT
179038. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_vcm_MASK
179039. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT
179040. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
179041. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
179042. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK
179043. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
179044. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
179045. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
179046. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
179047. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
179048. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
179049. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
179050. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
179051. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
179052. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK
179053. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT
179054. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK
179055. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
179056. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__nc_MASK
179057. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__nc__SHIFT
179058. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_nmos_MASK
179059. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_nmos__SHIFT
179060. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_pmos_MASK
179061. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_pmos__SHIFT
179062. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__override_rxdetref_MASK
179063. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT
179064. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
179065. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
179066. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
179067. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
179068. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
179069. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
179070. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
179071. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
179072. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK
179073. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
179074. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
179075. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
179076. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
179077. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
179078. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
179079. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
179080. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
179081. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
179082. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
179083. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
179084. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
179085. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
179086. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
179087. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
179088. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
179089. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
179090. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
179091. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
179092. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
179093. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
179094. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
179095. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
179096. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
179097. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
179098. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
179099. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
179100. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
179101. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
179102. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
179103. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
179104. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK
179105. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
179106. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK
179107. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
179108. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
179109. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
179110. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK
179111. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
179112. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
179113. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
179114. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
179115. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
179116. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK
179117. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
179118. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
179119. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
179120. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
179121. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
179122. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
179123. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
179124. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
179125. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
179126. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
179127. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
179128. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
179129. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
179130. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK
179131. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
179132. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK
179133. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT
179134. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_MASK
179135. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT
179136. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK
179137. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
179138. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
179139. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
179140. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK
179141. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
179142. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK
179143. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
179144. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK
179145. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
179146. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK
179147. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT
179148. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
179149. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
179150. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
179151. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
179152. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
179153. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
179154. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
179155. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
179156. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
179157. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
179158. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
179159. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
179160. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
179161. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
179162. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
179163. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
179164. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
179165. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
179166. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
179167. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
179168. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
179169. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
179170. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
179171. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
179172. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
179173. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
179174. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
179175. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
179176. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
179177. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
179178. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
179179. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
179180. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
179181. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
179182. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
179183. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
179184. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
179185. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
179186. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
179187. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
179188. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
179189. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
179190. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
179191. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
179192. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
179193. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
179194. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
179195. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
179196. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
179197. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
179198. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
179199. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
179200. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
179201. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
179202. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
179203. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
179204. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
179205. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
179206. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
179207. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
179208. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
179209. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
179210. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
179211. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
179212. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
179213. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
179214. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
179215. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
179216. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
179217. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
179218. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
179219. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
179220. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
179221. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
179222. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
179223. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
179224. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
179225. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
179226. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
179227. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
179228. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
179229. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
179230. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
179231. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
179232. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
179233. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
179234. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
179235. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
179236. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
179237. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
179238. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
179239. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
179240. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
179241. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
179242. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
179243. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
179244. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
179245. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
179246. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
179247. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
179248. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
179249. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
179250. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
179251. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
179252. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
179253. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
179254. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
179255. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
179256. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
179257. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
179258. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
179259. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
179260. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
179261. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
179262. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
179263. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
179264. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
179265. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
179266. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
179267. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
179268. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
179269. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
179270. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
179271. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
179272. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
179273. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
179274. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
179275. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
179276. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
179277. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
179278. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
179279. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
179280. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
179281. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
179282. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
179283. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
179284. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
179285. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
179286. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
179287. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
179288. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
179289. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
179290. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
179291. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
179292. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
179293. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
179294. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
179295. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
179296. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
179297. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
179298. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
179299. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
179300. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
179301. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
179302. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
179303. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
179304. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
179305. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
179306. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
179307. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
179308. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
179309. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
179310. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
179311. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
179312. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
179313. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
179314. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
179315. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
179316. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
179317. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
179318. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
179319. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
179320. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
179321. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
179322. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
179323. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
179324. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
179325. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
179326. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
179327. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
179328. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
179329. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
179330. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
179331. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
179332. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
179333. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
179334. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
179335. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
179336. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
179337. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
179338. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
179339. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
179340. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
179341. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
179342. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
179343. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
179344. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
179345. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
179346. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
179347. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
179348. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
179349. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
179350. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
179351. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
179352. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
179353. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
179354. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
179355. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
179356. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
179357. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
179358. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
179359. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
179360. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
179361. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
179362. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
179363. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
179364. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
179365. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
179366. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
179367. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
179368. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
179369. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
179370. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
179371. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
179372. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
179373. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
179374. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
179375. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
179376. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
179377. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
179378. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
179379. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
179380. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
179381. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
179382. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
179383. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
179384. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
179385. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
179386. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
179387. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
179388. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
179389. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
179390. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
179391. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
179392. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK
179393. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
179394. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
179395. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
179396. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
179397. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
179398. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
179399. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
179400. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
179401. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
179402. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
179403. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
179404. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
179405. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
179406. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
179407. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
179408. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
179409. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
179410. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
179411. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
179412. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
179413. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
179414. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
179415. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
179416. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
179417. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
179418. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
179419. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
179420. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
179421. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
179422. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
179423. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
179424. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
179425. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
179426. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
179427. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
179428. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
179429. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
179430. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
179431. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
179432. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
179433. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
179434. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
179435. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
179436. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
179437. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
179438. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
179439. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
179440. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
179441. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
179442. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
179443. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
179444. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
179445. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
179446. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
179447. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
179448. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
179449. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
179450. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
179451. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
179452. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
179453. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
179454. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
179455. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
179456. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
179457. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
179458. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
179459. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
179460. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
179461. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
179462. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
179463. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
179464. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
179465. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
179466. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
179467. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
179468. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
179469. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
179470. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
179471. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
179472. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
179473. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
179474. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
179475. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
179476. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
179477. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
179478. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
179479. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
179480. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
179481. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
179482. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
179483. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
179484. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
179485. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
179486. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
179487. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
179488. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
179489. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
179490. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
179491. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
179492. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
179493. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
179494. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
179495. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
179496. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
179497. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
179498. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
179499. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
179500. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
179501. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
179502. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
179503. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
179504. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
179505. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
179506. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
179507. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
179508. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
179509. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
179510. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
179511. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
179512. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
179513. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
179514. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
179515. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
179516. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
179517. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
179518. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
179519. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
179520. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
179521. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
179522. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
179523. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
179524. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
179525. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
179526. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
179527. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
179528. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
179529. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
179530. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
179531. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
179532. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
179533. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
179534. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
179535. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
179536. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
179537. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
179538. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
179539. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
179540. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
179541. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
179542. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
179543. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
179544. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
179545. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
179546. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
179547. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
179548. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
179549. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
179550. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
179551. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
179552. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
179553. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
179554. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
179555. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
179556. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
179557. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
179558. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
179559. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
179560. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
179561. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
179562. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
179563. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
179564. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
179565. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
179566. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
179567. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
179568. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
179569. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
179570. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
179571. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
179572. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
179573. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
179574. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
179575. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
179576. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
179577. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
179578. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
179579. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
179580. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
179581. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
179582. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
179583. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
179584. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
179585. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
179586. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
179587. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
179588. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
179589. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
179590. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
179591. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
179592. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
179593. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
179594. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
179595. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
179596. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
179597. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
179598. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
179599. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
179600. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
179601. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
179602. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
179603. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
179604. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
179605. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
179606. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
179607. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
179608. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
179609. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
179610. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
179611. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
179612. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
179613. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
179614. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
179615. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
179616. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
179617. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
179618. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
179619. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
179620. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
179621. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
179622. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
179623. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
179624. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
179625. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
179626. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
179627. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
179628. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
179629. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
179630. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
179631. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
179632. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
179633. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
179634. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
179635. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
179636. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
179637. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
179638. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
179639. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
179640. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
179641. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
179642. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
179643. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
179644. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
179645. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
179646. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
179647. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
179648. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
179649. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
179650. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
179651. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
179652. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
179653. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
179654. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
179655. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
179656. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
179657. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
179658. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
179659. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
179660. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
179661. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
179662. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
179663. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
179664. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
179665. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
179666. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
179667. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
179668. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
179669. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
179670. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
179671. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
179672. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
179673. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
179674. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
179675. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
179676. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
179677. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
179678. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
179679. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
179680. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
179681. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
179682. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
179683. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
179684. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
179685. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
179686. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
179687. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
179688. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
179689. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
179690. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
179691. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
179692. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
179693. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
179694. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
179695. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
179696. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
179697. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
179698. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
179699. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
179700. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
179701. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
179702. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
179703. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
179704. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
179705. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
179706. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
179707. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
179708. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
179709. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
179710. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
179711. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
179712. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
179713. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
179714. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
179715. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
179716. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
179717. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
179718. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
179719. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
179720. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
179721. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
179722. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
179723. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
179724. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
179725. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
179726. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
179727. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
179728. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
179729. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
179730. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
179731. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
179732. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
179733. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
179734. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
179735. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
179736. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
179737. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
179738. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
179739. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
179740. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
179741. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
179742. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
179743. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
179744. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
179745. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
179746. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
179747. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
179748. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
179749. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
179750. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
179751. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
179752. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
179753. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
179754. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
179755. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
179756. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
179757. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
179758. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
179759. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
179760. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
179761. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
179762. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
179763. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
179764. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
179765. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
179766. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
179767. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
179768. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
179769. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
179770. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
179771. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
179772. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
179773. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
179774. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
179775. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
179776. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
179777. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
179778. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
179779. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
179780. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
179781. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
179782. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
179783. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
179784. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
179785. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
179786. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
179787. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
179788. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
179789. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
179790. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
179791. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
179792. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
179793. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
179794. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
179795. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
179796. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
179797. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
179798. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
179799. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
179800. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
179801. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
179802. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
179803. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
179804. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
179805. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
179806. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
179807. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
179808. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
179809. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
179810. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
179811. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
179812. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
179813. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
179814. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
179815. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
179816. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
179817. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
179818. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
179819. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
179820. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
179821. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
179822. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
179823. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
179824. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
179825. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
179826. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
179827. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
179828. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
179829. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
179830. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
179831. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
179832. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
179833. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
179834. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
179835. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
179836. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
179837. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
179838. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
179839. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
179840. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
179841. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
179842. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
179843. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
179844. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
179845. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
179846. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
179847. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
179848. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
179849. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
179850. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
179851. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
179852. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
179853. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
179854. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
179855. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
179856. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
179857. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
179858. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
179859. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
179860. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
179861. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
179862. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
179863. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
179864. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
179865. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
179866. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
179867. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
179868. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
179869. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
179870. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
179871. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
179872. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
179873. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
179874. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
179875. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
179876. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
179877. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
179878. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
179879. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
179880. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
179881. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
179882. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
179883. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
179884. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
179885. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
179886. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
179887. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
179888. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
179889. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
179890. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
179891. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
179892. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
179893. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
179894. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
179895. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
179896. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
179897. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
179898. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
179899. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
179900. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
179901. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
179902. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
179903. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
179904. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
179905. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
179906. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
179907. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
179908. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
179909. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
179910. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
179911. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
179912. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
179913. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
179914. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
179915. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
179916. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
179917. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
179918. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
179919. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
179920. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
179921. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
179922. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
179923. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
179924. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
179925. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
179926. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
179927. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
179928. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
179929. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
179930. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
179931. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
179932. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
179933. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
179934. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
179935. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
179936. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
179937. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
179938. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
179939. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
179940. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
179941. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
179942. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
179943. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
179944. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
179945. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
179946. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
179947. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
179948. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK
179949. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT
179950. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK
179951. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT
179952. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
179953. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
179954. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK
179955. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT
179956. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK
179957. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT
179958. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK
179959. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT
179960. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
179961. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
179962. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
179963. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
179964. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
179965. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
179966. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
179967. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
179968. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
179969. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
179970. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
179971. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
179972. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
179973. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
179974. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
179975. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
179976. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
179977. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
179978. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
179979. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
179980. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
179981. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
179982. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
179983. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
179984. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
179985. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
179986. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
179987. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
179988. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
179989. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
179990. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
179991. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
179992. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
179993. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
179994. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
179995. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
179996. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
179997. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
179998. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
179999. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
180000. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
180001. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
180002. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
180003. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
180004. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
180005. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
180006. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
180007. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
180008. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
180009. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
180010. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
180011. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
180012. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
180013. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
180014. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
180015. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
180016. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
180017. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
180018. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
180019. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
180020. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
180021. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
180022. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
180023. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
180024. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
180025. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
180026. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
180027. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
180028. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
180029. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
180030. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
180031. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
180032. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
180033. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
180034. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
180035. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
180036. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
180037. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
180038. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
180039. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
180040. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
180041. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
180042. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
180043. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
180044. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
180045. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
180046. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
180047. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
180048. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
180049. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
180050. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
180051. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
180052. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
180053. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
180054. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
180055. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
180056. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
180057. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
180058. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
180059. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
180060. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
180061. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
180062. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
180063. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
180064. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
180065. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
180066. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
180067. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
180068. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
180069. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
180070. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
180071. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
180072. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
180073. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
180074. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
180075. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
180076. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
180077. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
180078. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
180079. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
180080. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
180081. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
180082. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
180083. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
180084. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
180085. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
180086. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
180087. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
180088. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
180089. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
180090. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
180091. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
180092. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
180093. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
180094. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
180095. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
180096. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
180097. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
180098. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
180099. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
180100. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
180101. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
180102. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
180103. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
180104. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
180105. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
180106. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
180107. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
180108. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
180109. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
180110. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
180111. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
180112. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
180113. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
180114. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
180115. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
180116. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
180117. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
180118. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
180119. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
180120. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
180121. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
180122. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
180123. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
180124. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
180125. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
180126. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
180127. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
180128. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
180129. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
180130. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
180131. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
180132. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
180133. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
180134. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
180135. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
180136. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
180137. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
180138. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
180139. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
180140. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
180141. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
180142. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
180143. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
180144. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
180145. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
180146. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
180147. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
180148. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
180149. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
180150. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
180151. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
180152. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
180153. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
180154. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
180155. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
180156. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
180157. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
180158. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
180159. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
180160. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
180161. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
180162. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
180163. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
180164. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
180165. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
180166. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
180167. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
180168. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
180169. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
180170. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
180171. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
180172. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
180173. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
180174. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
180175. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
180176. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
180177. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
180178. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
180179. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
180180. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
180181. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
180182. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
180183. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
180184. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
180185. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
180186. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
180187. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
180188. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
180189. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
180190. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
180191. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
180192. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
180193. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
180194. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
180195. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
180196. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
180197. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
180198. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
180199. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
180200. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
180201. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
180202. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
180203. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
180204. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
180205. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
180206. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
180207. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
180208. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
180209. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
180210. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
180211. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
180212. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
180213. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
180214. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
180215. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
180216. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
180217. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
180218. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
180219. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
180220. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
180221. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
180222. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
180223. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
180224. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
180225. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
180226. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
180227. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
180228. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
180229. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
180230. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
180231. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
180232. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
180233. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
180234. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
180235. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
180236. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
180237. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
180238. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
180239. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
180240. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
180241. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
180242. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
180243. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
180244. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
180245. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
180246. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
180247. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
180248. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
180249. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
180250. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
180251. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
180252. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
180253. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
180254. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
180255. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
180256. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
180257. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
180258. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
180259. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
180260. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
180261. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
180262. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
180263. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
180264. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
180265. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
180266. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
180267. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
180268. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
180269. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
180270. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
180271. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
180272. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
180273. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
180274. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
180275. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
180276. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
180277. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
180278. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
180279. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
180280. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
180281. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
180282. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
180283. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
180284. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
180285. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
180286. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
180287. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
180288. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
180289. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
180290. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
180291. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
180292. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
180293. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
180294. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
180295. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
180296. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
180297. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
180298. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
180299. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
180300. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
180301. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
180302. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK
180303. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT
180304. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK
180305. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT
180306. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
180307. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
180308. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
180309. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
180310. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
180311. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
180312. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
180313. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
180314. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
180315. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
180316. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
180317. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
180318. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
180319. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
180320. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
180321. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
180322. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
180323. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
180324. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
180325. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
180326. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
180327. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
180328. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
180329. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
180330. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
180331. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
180332. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
180333. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
180334. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
180335. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
180336. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
180337. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
180338. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
180339. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
180340. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
180341. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
180342. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
180343. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
180344. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
180345. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
180346. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
180347. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
180348. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
180349. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
180350. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
180351. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
180352. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
180353. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
180354. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
180355. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
180356. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
180357. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
180358. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
180359. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
180360. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
180361. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
180362. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
180363. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
180364. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
180365. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
180366. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
180367. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
180368. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
180369. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
180370. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
180371. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
180372. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
180373. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
180374. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
180375. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
180376. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
180377. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
180378. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
180379. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
180380. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
180381. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
180382. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
180383. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
180384. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
180385. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
180386. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
180387. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
180388. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
180389. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
180390. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
180391. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
180392. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
180393. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
180394. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
180395. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
180396. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
180397. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
180398. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
180399. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
180400. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
180401. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
180402. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
180403. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
180404. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
180405. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
180406. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
180407. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
180408. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
180409. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
180410. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
180411. DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
180412. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
180413. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
180414. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
180415. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
180416. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
180417. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
180418. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
180419. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
180420. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
180421. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
180422. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK
180423. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT
180424. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
180425. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
180426. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
180427. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
180428. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
180429. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
180430. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
180431. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
180432. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
180433. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
180434. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
180435. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
180436. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
180437. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
180438. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
180439. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
180440. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
180441. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
180442. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
180443. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
180444. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
180445. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
180446. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
180447. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
180448. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
180449. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
180450. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
180451. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
180452. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
180453. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
180454. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK
180455. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
180456. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK
180457. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
180458. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK
180459. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
180460. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
180461. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
180462. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
180463. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
180464. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
180465. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
180466. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
180467. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
180468. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
180469. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
180470. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
180471. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
180472. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
180473. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
180474. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
180475. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
180476. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
180477. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
180478. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
180479. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
180480. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
180481. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
180482. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
180483. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
180484. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
180485. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
180486. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
180487. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
180488. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
180489. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
180490. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
180491. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
180492. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
180493. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
180494. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
180495. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
180496. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
180497. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
180498. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
180499. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
180500. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK
180501. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
180502. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK
180503. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
180504. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
180505. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
180506. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
180507. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
180508. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
180509. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
180510. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
180511. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
180512. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK
180513. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
180514. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
180515. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
180516. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
180517. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
180518. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
180519. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
180520. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
180521. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
180522. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
180523. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
180524. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__NC32_MASK
180525. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT
180526. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
180527. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
180528. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
180529. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
180530. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
180531. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
180532. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
180533. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
180534. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
180535. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
180536. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK
180537. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
180538. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
180539. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
180540. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
180541. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
180542. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
180543. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
180544. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
180545. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
180546. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
180547. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
180548. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK
180549. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
180550. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
180551. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
180552. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
180553. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
180554. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
180555. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
180556. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
180557. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
180558. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK
180559. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT
180560. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
180561. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
180562. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
180563. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
180564. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
180565. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
180566. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
180567. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
180568. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
180569. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
180570. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
180571. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
180572. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
180573. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
180574. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
180575. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
180576. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
180577. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
180578. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
180579. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
180580. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__NC20_MASK
180581. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__NC20__SHIFT
180582. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK
180583. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT
180584. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
180585. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
180586. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
180587. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
180588. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
180589. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
180590. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK
180591. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
180592. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK
180593. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
180594. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
180595. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
180596. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK
180597. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
180598. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK
180599. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
180600. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK
180601. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT
180602. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
180603. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
180604. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK
180605. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT
180606. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK
180607. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT
180608. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
180609. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
180610. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK
180611. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT
180612. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_gd_MASK
180613. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_gd__SHIFT
180614. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccm_MASK
180615. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT
180616. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccp_MASK
180617. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT
180618. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vptx_MASK
180619. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT
180620. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg0_MASK
180621. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT
180622. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg1_MASK
180623. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT
180624. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK
180625. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT
180626. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__override_regref_0_MASK
180627. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT
180628. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK
180629. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT
180630. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_nbias_MASK
180631. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT
180632. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_pbias_MASK
180633. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT
180634. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK
180635. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT
180636. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfm_MASK
180637. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT
180638. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfp_MASK
180639. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT
180640. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsm_MASK
180641. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT
180642. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsp_MASK
180643. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT
180644. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_vcm_MASK
180645. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT
180646. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
180647. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
180648. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK
180649. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
180650. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
180651. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
180652. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
180653. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
180654. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
180655. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
180656. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
180657. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
180658. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK
180659. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT
180660. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK
180661. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
180662. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__nc_MASK
180663. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__nc__SHIFT
180664. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_nmos_MASK
180665. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_nmos__SHIFT
180666. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_pmos_MASK
180667. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_pmos__SHIFT
180668. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__override_rxdetref_MASK
180669. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT
180670. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
180671. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
180672. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
180673. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
180674. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
180675. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
180676. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
180677. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
180678. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK
180679. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
180680. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
180681. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
180682. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
180683. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
180684. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
180685. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
180686. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
180687. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
180688. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
180689. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
180690. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
180691. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
180692. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
180693. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
180694. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
180695. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
180696. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
180697. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
180698. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
180699. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
180700. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
180701. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
180702. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
180703. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
180704. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
180705. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
180706. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
180707. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
180708. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
180709. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
180710. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK
180711. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
180712. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK
180713. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
180714. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
180715. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
180716. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK
180717. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
180718. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
180719. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
180720. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
180721. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
180722. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK
180723. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
180724. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
180725. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
180726. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
180727. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
180728. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
180729. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
180730. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
180731. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
180732. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
180733. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
180734. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
180735. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
180736. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK
180737. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
180738. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK
180739. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT
180740. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_MASK
180741. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT
180742. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK
180743. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
180744. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
180745. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
180746. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK
180747. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
180748. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK
180749. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
180750. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK
180751. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
180752. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK
180753. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT
180754. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
180755. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
180756. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
180757. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
180758. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
180759. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
180760. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
180761. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
180762. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
180763. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
180764. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
180765. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
180766. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
180767. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
180768. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
180769. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
180770. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
180771. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
180772. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
180773. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
180774. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
180775. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
180776. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
180777. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
180778. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
180779. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
180780. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
180781. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
180782. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
180783. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
180784. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
180785. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
180786. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
180787. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
180788. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
180789. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
180790. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
180791. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
180792. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
180793. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
180794. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
180795. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
180796. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
180797. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
180798. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
180799. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
180800. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
180801. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
180802. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
180803. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
180804. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
180805. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
180806. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
180807. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
180808. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
180809. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
180810. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
180811. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
180812. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
180813. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
180814. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
180815. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
180816. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
180817. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
180818. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
180819. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
180820. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
180821. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
180822. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
180823. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
180824. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
180825. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
180826. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
180827. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
180828. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
180829. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
180830. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
180831. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
180832. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
180833. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
180834. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
180835. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
180836. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
180837. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
180838. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
180839. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
180840. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
180841. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
180842. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
180843. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
180844. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
180845. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
180846. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
180847. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
180848. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
180849. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
180850. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
180851. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
180852. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
180853. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
180854. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
180855. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
180856. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
180857. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
180858. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
180859. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
180860. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
180861. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
180862. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
180863. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
180864. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
180865. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
180866. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
180867. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
180868. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
180869. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
180870. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
180871. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
180872. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
180873. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
180874. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
180875. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
180876. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
180877. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
180878. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
180879. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
180880. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
180881. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
180882. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
180883. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
180884. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
180885. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
180886. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
180887. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
180888. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
180889. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
180890. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
180891. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
180892. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
180893. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
180894. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
180895. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
180896. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
180897. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
180898. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
180899. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
180900. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
180901. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
180902. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
180903. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
180904. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
180905. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
180906. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
180907. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
180908. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
180909. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
180910. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
180911. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
180912. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
180913. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
180914. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
180915. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
180916. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
180917. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
180918. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
180919. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
180920. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
180921. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
180922. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
180923. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
180924. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
180925. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
180926. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
180927. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
180928. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
180929. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
180930. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
180931. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
180932. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
180933. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
180934. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
180935. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
180936. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
180937. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
180938. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
180939. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
180940. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
180941. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
180942. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
180943. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
180944. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
180945. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
180946. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
180947. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
180948. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
180949. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
180950. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
180951. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
180952. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
180953. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
180954. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
180955. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
180956. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
180957. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
180958. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
180959. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
180960. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
180961. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
180962. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
180963. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
180964. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
180965. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
180966. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
180967. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
180968. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
180969. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
180970. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
180971. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
180972. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
180973. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
180974. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
180975. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
180976. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
180977. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
180978. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
180979. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
180980. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
180981. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
180982. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
180983. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
180984. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
180985. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
180986. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
180987. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
180988. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
180989. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
180990. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
180991. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
180992. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
180993. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
180994. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
180995. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
180996. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
180997. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
180998. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK
180999. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
181000. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
181001. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
181002. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
181003. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
181004. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
181005. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
181006. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
181007. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
181008. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
181009. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
181010. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
181011. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
181012. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
181013. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
181014. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
181015. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
181016. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
181017. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
181018. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
181019. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
181020. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
181021. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
181022. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
181023. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
181024. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
181025. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
181026. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
181027. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
181028. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
181029. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
181030. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
181031. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
181032. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
181033. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
181034. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
181035. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
181036. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
181037. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
181038. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
181039. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
181040. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
181041. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
181042. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
181043. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
181044. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
181045. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
181046. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
181047. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
181048. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
181049. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
181050. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
181051. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
181052. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
181053. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
181054. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
181055. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
181056. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
181057. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
181058. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
181059. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
181060. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
181061. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
181062. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
181063. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
181064. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
181065. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
181066. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
181067. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
181068. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
181069. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
181070. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
181071. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
181072. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
181073. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
181074. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
181075. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
181076. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
181077. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
181078. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
181079. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
181080. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
181081. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
181082. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
181083. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
181084. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
181085. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
181086. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
181087. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
181088. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
181089. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
181090. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
181091. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
181092. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
181093. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
181094. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
181095. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
181096. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
181097. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
181098. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
181099. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
181100. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
181101. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
181102. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
181103. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
181104. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
181105. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
181106. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
181107. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
181108. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
181109. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
181110. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
181111. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
181112. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
181113. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
181114. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
181115. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
181116. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
181117. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
181118. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
181119. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
181120. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
181121. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
181122. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
181123. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
181124. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
181125. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
181126. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
181127. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
181128. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
181129. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
181130. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
181131. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
181132. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
181133. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
181134. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
181135. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
181136. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
181137. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
181138. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
181139. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
181140. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
181141. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
181142. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
181143. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
181144. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
181145. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
181146. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
181147. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
181148. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
181149. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
181150. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
181151. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
181152. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
181153. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
181154. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
181155. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
181156. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
181157. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
181158. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
181159. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
181160. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
181161. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
181162. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
181163. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
181164. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
181165. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
181166. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
181167. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
181168. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
181169. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
181170. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
181171. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
181172. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
181173. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
181174. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
181175. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
181176. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
181177. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
181178. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
181179. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
181180. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
181181. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
181182. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
181183. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
181184. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
181185. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
181186. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
181187. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
181188. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
181189. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
181190. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
181191. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
181192. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
181193. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
181194. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
181195. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
181196. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
181197. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
181198. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
181199. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
181200. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
181201. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
181202. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
181203. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
181204. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
181205. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
181206. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
181207. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
181208. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
181209. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
181210. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
181211. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
181212. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
181213. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
181214. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
181215. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
181216. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
181217. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
181218. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
181219. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
181220. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
181221. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
181222. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
181223. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
181224. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
181225. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
181226. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
181227. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
181228. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
181229. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
181230. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
181231. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
181232. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
181233. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
181234. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
181235. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
181236. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
181237. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
181238. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
181239. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
181240. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
181241. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
181242. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
181243. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
181244. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
181245. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
181246. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
181247. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
181248. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
181249. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
181250. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
181251. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
181252. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
181253. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
181254. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
181255. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
181256. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
181257. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
181258. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
181259. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
181260. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
181261. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
181262. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
181263. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
181264. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
181265. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
181266. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
181267. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
181268. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
181269. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
181270. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
181271. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
181272. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
181273. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
181274. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
181275. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
181276. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
181277. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
181278. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
181279. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
181280. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
181281. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
181282. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
181283. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
181284. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
181285. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
181286. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
181287. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
181288. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
181289. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
181290. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
181291. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
181292. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
181293. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
181294. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
181295. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
181296. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
181297. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
181298. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
181299. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
181300. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
181301. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
181302. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
181303. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
181304. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
181305. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
181306. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
181307. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
181308. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
181309. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
181310. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
181311. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
181312. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
181313. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
181314. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
181315. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
181316. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
181317. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
181318. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
181319. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
181320. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
181321. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
181322. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
181323. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
181324. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
181325. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
181326. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
181327. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
181328. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
181329. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
181330. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
181331. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
181332. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
181333. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
181334. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
181335. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
181336. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
181337. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
181338. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
181339. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
181340. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
181341. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
181342. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
181343. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
181344. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
181345. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
181346. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
181347. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
181348. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
181349. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
181350. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
181351. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
181352. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
181353. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
181354. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
181355. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
181356. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
181357. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
181358. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
181359. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
181360. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
181361. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
181362. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
181363. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
181364. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
181365. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
181366. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
181367. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
181368. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
181369. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
181370. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
181371. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
181372. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
181373. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
181374. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
181375. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
181376. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
181377. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
181378. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
181379. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
181380. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
181381. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
181382. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
181383. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
181384. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
181385. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
181386. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
181387. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
181388. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
181389. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
181390. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
181391. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
181392. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
181393. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
181394. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
181395. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
181396. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
181397. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
181398. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
181399. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
181400. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
181401. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
181402. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
181403. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
181404. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
181405. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
181406. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
181407. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
181408. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
181409. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
181410. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
181411. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
181412. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
181413. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
181414. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
181415. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
181416. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
181417. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
181418. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
181419. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
181420. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
181421. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
181422. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
181423. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
181424. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
181425. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
181426. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
181427. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
181428. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
181429. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
181430. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
181431. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
181432. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
181433. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
181434. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
181435. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
181436. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
181437. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
181438. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
181439. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
181440. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
181441. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
181442. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
181443. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
181444. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
181445. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
181446. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
181447. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
181448. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
181449. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
181450. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
181451. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
181452. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
181453. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
181454. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
181455. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
181456. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
181457. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
181458. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
181459. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
181460. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
181461. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
181462. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
181463. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
181464. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
181465. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
181466. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
181467. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
181468. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
181469. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
181470. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
181471. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
181472. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
181473. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
181474. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
181475. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
181476. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
181477. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
181478. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
181479. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
181480. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
181481. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
181482. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
181483. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
181484. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
181485. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
181486. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
181487. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
181488. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
181489. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
181490. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
181491. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
181492. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
181493. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
181494. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
181495. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
181496. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
181497. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
181498. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
181499. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
181500. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
181501. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
181502. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
181503. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
181504. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
181505. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
181506. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
181507. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
181508. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
181509. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
181510. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
181511. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
181512. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
181513. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
181514. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
181515. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
181516. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
181517. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
181518. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
181519. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
181520. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
181521. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
181522. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
181523. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
181524. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
181525. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
181526. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
181527. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
181528. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
181529. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
181530. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
181531. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
181532. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
181533. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
181534. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
181535. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
181536. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
181537. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
181538. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
181539. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
181540. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
181541. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
181542. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
181543. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
181544. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
181545. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
181546. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
181547. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
181548. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
181549. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
181550. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
181551. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
181552. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
181553. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
181554. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK
181555. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT
181556. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__MODE_MASK
181557. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT
181558. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
181559. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
181560. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK
181561. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT
181562. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK
181563. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT
181564. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__OV14_MASK
181565. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT
181566. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
181567. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
181568. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
181569. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
181570. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
181571. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
181572. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
181573. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
181574. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
181575. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
181576. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
181577. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
181578. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
181579. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
181580. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
181581. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
181582. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
181583. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
181584. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
181585. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
181586. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
181587. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
181588. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
181589. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
181590. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
181591. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
181592. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
181593. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
181594. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
181595. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
181596. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
181597. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
181598. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
181599. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
181600. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
181601. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
181602. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
181603. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
181604. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
181605. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
181606. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
181607. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
181608. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
181609. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
181610. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
181611. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
181612. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
181613. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
181614. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
181615. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
181616. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
181617. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
181618. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
181619. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
181620. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
181621. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
181622. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
181623. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
181624. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
181625. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
181626. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
181627. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
181628. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
181629. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
181630. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
181631. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
181632. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
181633. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
181634. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
181635. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
181636. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
181637. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
181638. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
181639. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
181640. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
181641. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
181642. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
181643. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
181644. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
181645. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
181646. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
181647. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
181648. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
181649. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
181650. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
181651. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
181652. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
181653. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
181654. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
181655. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
181656. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
181657. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
181658. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
181659. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
181660. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
181661. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
181662. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
181663. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
181664. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
181665. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
181666. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
181667. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
181668. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
181669. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
181670. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
181671. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
181672. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
181673. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
181674. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
181675. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
181676. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
181677. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
181678. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
181679. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
181680. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
181681. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
181682. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
181683. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
181684. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
181685. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
181686. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
181687. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
181688. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
181689. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
181690. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
181691. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
181692. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
181693. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
181694. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
181695. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
181696. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
181697. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
181698. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
181699. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
181700. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
181701. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
181702. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
181703. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
181704. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
181705. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
181706. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
181707. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
181708. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
181709. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
181710. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
181711. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
181712. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
181713. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
181714. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
181715. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
181716. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
181717. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
181718. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
181719. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
181720. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
181721. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
181722. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
181723. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
181724. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
181725. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
181726. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
181727. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
181728. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
181729. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
181730. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
181731. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
181732. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
181733. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
181734. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
181735. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
181736. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
181737. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
181738. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
181739. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
181740. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
181741. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
181742. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
181743. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
181744. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
181745. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
181746. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
181747. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
181748. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
181749. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
181750. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
181751. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
181752. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
181753. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
181754. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
181755. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
181756. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
181757. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
181758. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
181759. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
181760. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
181761. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
181762. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
181763. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
181764. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
181765. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
181766. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
181767. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
181768. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
181769. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
181770. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
181771. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
181772. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
181773. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
181774. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
181775. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
181776. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
181777. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
181778. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
181779. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
181780. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
181781. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
181782. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
181783. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
181784. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
181785. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
181786. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
181787. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
181788. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
181789. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
181790. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
181791. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
181792. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
181793. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
181794. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
181795. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
181796. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
181797. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
181798. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
181799. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
181800. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
181801. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
181802. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
181803. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
181804. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
181805. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
181806. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
181807. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
181808. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
181809. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
181810. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
181811. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
181812. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
181813. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
181814. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
181815. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
181816. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
181817. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
181818. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
181819. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
181820. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
181821. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
181822. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
181823. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
181824. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
181825. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
181826. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
181827. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
181828. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
181829. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
181830. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
181831. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
181832. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
181833. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
181834. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
181835. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
181836. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
181837. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
181838. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
181839. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
181840. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
181841. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
181842. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
181843. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
181844. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
181845. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
181846. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
181847. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
181848. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
181849. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
181850. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
181851. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
181852. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
181853. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
181854. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
181855. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
181856. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
181857. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
181858. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
181859. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
181860. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
181861. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
181862. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
181863. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
181864. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
181865. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
181866. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
181867. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
181868. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
181869. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
181870. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
181871. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
181872. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
181873. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
181874. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
181875. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
181876. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
181877. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
181878. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
181879. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
181880. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
181881. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
181882. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
181883. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
181884. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
181885. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
181886. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
181887. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
181888. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
181889. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
181890. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
181891. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
181892. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
181893. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
181894. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
181895. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
181896. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
181897. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
181898. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
181899. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
181900. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
181901. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
181902. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
181903. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
181904. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
181905. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
181906. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
181907. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
181908. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK
181909. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT
181910. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK
181911. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT
181912. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
181913. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
181914. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
181915. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
181916. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
181917. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
181918. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
181919. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
181920. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
181921. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
181922. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
181923. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
181924. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
181925. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
181926. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
181927. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
181928. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
181929. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
181930. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
181931. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
181932. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
181933. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
181934. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
181935. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
181936. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
181937. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
181938. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
181939. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
181940. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
181941. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
181942. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
181943. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
181944. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
181945. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
181946. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
181947. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
181948. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
181949. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
181950. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
181951. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
181952. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
181953. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
181954. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
181955. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
181956. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
181957. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
181958. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
181959. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
181960. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
181961. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
181962. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
181963. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
181964. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
181965. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
181966. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
181967. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
181968. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
181969. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
181970. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
181971. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
181972. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
181973. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
181974. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
181975. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
181976. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
181977. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
181978. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
181979. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
181980. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
181981. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
181982. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
181983. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
181984. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
181985. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
181986. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
181987. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
181988. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
181989. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
181990. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
181991. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
181992. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
181993. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
181994. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
181995. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
181996. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
181997. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
181998. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
181999. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
182000. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
182001. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
182002. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
182003. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
182004. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
182005. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
182006. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
182007. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
182008. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
182009. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
182010. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
182011. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
182012. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
182013. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
182014. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
182015. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
182016. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
182017. DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
182018. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
182019. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
182020. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
182021. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
182022. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
182023. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
182024. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
182025. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
182026. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
182027. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
182028. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK
182029. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT
182030. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
182031. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
182032. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
182033. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
182034. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
182035. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
182036. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
182037. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
182038. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
182039. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
182040. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
182041. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
182042. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
182043. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
182044. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
182045. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
182046. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
182047. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
182048. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
182049. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
182050. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
182051. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
182052. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
182053. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
182054. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
182055. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
182056. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
182057. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
182058. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
182059. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
182060. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK
182061. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
182062. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK
182063. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
182064. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK
182065. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
182066. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
182067. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
182068. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
182069. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
182070. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
182071. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
182072. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
182073. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
182074. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
182075. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
182076. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
182077. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
182078. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
182079. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
182080. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
182081. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
182082. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
182083. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
182084. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
182085. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
182086. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
182087. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
182088. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
182089. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
182090. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
182091. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
182092. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
182093. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
182094. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
182095. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
182096. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
182097. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
182098. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
182099. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
182100. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
182101. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
182102. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
182103. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
182104. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
182105. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
182106. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK
182107. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
182108. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK
182109. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
182110. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
182111. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
182112. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
182113. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
182114. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
182115. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
182116. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
182117. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
182118. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK
182119. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
182120. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
182121. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
182122. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
182123. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
182124. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
182125. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
182126. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
182127. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
182128. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
182129. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
182130. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__NC32_MASK
182131. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT
182132. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
182133. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
182134. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
182135. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
182136. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
182137. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
182138. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
182139. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
182140. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
182141. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
182142. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK
182143. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
182144. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
182145. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
182146. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
182147. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
182148. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
182149. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
182150. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
182151. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
182152. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
182153. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
182154. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK
182155. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
182156. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
182157. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
182158. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
182159. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
182160. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
182161. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
182162. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
182163. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
182164. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK
182165. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT
182166. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
182167. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
182168. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
182169. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
182170. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
182171. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
182172. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
182173. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
182174. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
182175. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
182176. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
182177. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
182178. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
182179. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
182180. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
182181. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
182182. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
182183. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
182184. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
182185. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
182186. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__NC20_MASK
182187. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__NC20__SHIFT
182188. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK
182189. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT
182190. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
182191. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
182192. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
182193. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
182194. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
182195. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
182196. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK
182197. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
182198. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK
182199. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
182200. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
182201. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
182202. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK
182203. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
182204. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK
182205. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
182206. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK
182207. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT
182208. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
182209. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
182210. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK
182211. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT
182212. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK
182213. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT
182214. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
182215. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
182216. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK
182217. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT
182218. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_gd_MASK
182219. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_gd__SHIFT
182220. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccm_MASK
182221. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT
182222. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccp_MASK
182223. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT
182224. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vptx_MASK
182225. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT
182226. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg0_MASK
182227. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT
182228. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg1_MASK
182229. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT
182230. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK
182231. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT
182232. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__override_regref_0_MASK
182233. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT
182234. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK
182235. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT
182236. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_nbias_MASK
182237. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT
182238. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_pbias_MASK
182239. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT
182240. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK
182241. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT
182242. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfm_MASK
182243. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT
182244. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfp_MASK
182245. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT
182246. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsm_MASK
182247. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT
182248. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsp_MASK
182249. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT
182250. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_vcm_MASK
182251. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT
182252. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
182253. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
182254. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK
182255. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
182256. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
182257. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
182258. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
182259. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
182260. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
182261. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
182262. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
182263. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
182264. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK
182265. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT
182266. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK
182267. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
182268. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__nc_MASK
182269. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__nc__SHIFT
182270. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_nmos_MASK
182271. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_nmos__SHIFT
182272. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_pmos_MASK
182273. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_pmos__SHIFT
182274. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__override_rxdetref_MASK
182275. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT
182276. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
182277. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
182278. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
182279. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
182280. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
182281. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
182282. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
182283. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
182284. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK
182285. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
182286. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
182287. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
182288. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
182289. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
182290. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
182291. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
182292. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
182293. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
182294. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
182295. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
182296. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
182297. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
182298. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
182299. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
182300. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
182301. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
182302. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
182303. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
182304. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
182305. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
182306. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
182307. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
182308. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
182309. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
182310. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
182311. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
182312. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
182313. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
182314. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
182315. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
182316. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK
182317. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
182318. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK
182319. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
182320. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
182321. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
182322. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK
182323. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
182324. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
182325. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
182326. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
182327. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
182328. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK
182329. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
182330. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
182331. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
182332. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
182333. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
182334. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
182335. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
182336. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
182337. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
182338. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
182339. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
182340. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
182341. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
182342. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK
182343. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
182344. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK
182345. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT
182346. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_MASK
182347. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT
182348. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK
182349. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
182350. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
182351. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
182352. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK
182353. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
182354. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK
182355. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
182356. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK
182357. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
182358. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK
182359. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT
182360. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
182361. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
182362. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
182363. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
182364. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
182365. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
182366. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
182367. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
182368. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
182369. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
182370. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
182371. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
182372. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
182373. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
182374. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
182375. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
182376. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
182377. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
182378. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
182379. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
182380. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
182381. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
182382. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
182383. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
182384. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
182385. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
182386. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
182387. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
182388. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
182389. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
182390. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
182391. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
182392. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
182393. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
182394. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
182395. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
182396. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
182397. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
182398. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
182399. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
182400. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
182401. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
182402. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
182403. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
182404. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
182405. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
182406. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
182407. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
182408. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
182409. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
182410. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
182411. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
182412. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
182413. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
182414. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
182415. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
182416. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
182417. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
182418. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
182419. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
182420. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
182421. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
182422. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
182423. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
182424. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
182425. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
182426. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
182427. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
182428. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
182429. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
182430. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
182431. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
182432. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
182433. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
182434. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
182435. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
182436. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
182437. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
182438. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
182439. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
182440. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
182441. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
182442. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
182443. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
182444. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
182445. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
182446. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
182447. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
182448. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
182449. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
182450. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
182451. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
182452. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
182453. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
182454. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
182455. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
182456. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
182457. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
182458. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
182459. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
182460. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
182461. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
182462. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
182463. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
182464. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
182465. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
182466. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
182467. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
182468. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
182469. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
182470. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
182471. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
182472. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
182473. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
182474. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
182475. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
182476. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
182477. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
182478. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
182479. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
182480. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
182481. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
182482. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
182483. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
182484. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
182485. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
182486. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
182487. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
182488. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
182489. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
182490. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
182491. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
182492. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
182493. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
182494. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
182495. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
182496. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
182497. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
182498. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
182499. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
182500. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
182501. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
182502. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
182503. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
182504. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
182505. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
182506. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
182507. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
182508. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
182509. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
182510. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
182511. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
182512. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
182513. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
182514. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
182515. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
182516. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
182517. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
182518. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
182519. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
182520. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
182521. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
182522. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
182523. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
182524. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
182525. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
182526. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
182527. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
182528. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
182529. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
182530. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
182531. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
182532. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
182533. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
182534. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
182535. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
182536. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
182537. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
182538. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
182539. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
182540. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
182541. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
182542. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
182543. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
182544. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
182545. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
182546. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
182547. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
182548. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
182549. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
182550. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
182551. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
182552. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
182553. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
182554. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
182555. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
182556. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
182557. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
182558. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
182559. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
182560. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
182561. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
182562. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
182563. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
182564. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
182565. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
182566. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
182567. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
182568. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
182569. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
182570. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
182571. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
182572. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
182573. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
182574. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
182575. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
182576. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
182577. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
182578. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
182579. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
182580. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
182581. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
182582. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
182583. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
182584. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
182585. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
182586. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
182587. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
182588. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
182589. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
182590. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
182591. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
182592. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
182593. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
182594. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
182595. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
182596. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
182597. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
182598. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
182599. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
182600. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
182601. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
182602. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
182603. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
182604. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK
182605. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
182606. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
182607. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
182608. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
182609. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
182610. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
182611. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
182612. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
182613. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
182614. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
182615. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
182616. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
182617. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
182618. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
182619. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
182620. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
182621. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
182622. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
182623. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
182624. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
182625. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
182626. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
182627. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
182628. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
182629. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
182630. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
182631. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
182632. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
182633. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
182634. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
182635. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
182636. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
182637. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
182638. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
182639. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
182640. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
182641. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
182642. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
182643. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
182644. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
182645. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
182646. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
182647. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
182648. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
182649. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
182650. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
182651. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
182652. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
182653. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
182654. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
182655. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
182656. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
182657. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
182658. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
182659. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
182660. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
182661. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
182662. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
182663. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
182664. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
182665. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
182666. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
182667. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
182668. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
182669. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
182670. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
182671. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
182672. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
182673. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
182674. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
182675. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
182676. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
182677. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
182678. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
182679. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
182680. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
182681. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
182682. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
182683. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
182684. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
182685. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
182686. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
182687. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
182688. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
182689. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
182690. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
182691. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
182692. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
182693. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
182694. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
182695. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
182696. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
182697. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
182698. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
182699. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
182700. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
182701. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
182702. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
182703. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
182704. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
182705. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
182706. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
182707. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
182708. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
182709. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
182710. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
182711. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
182712. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
182713. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
182714. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
182715. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
182716. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
182717. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
182718. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
182719. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
182720. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
182721. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
182722. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
182723. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
182724. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
182725. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
182726. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
182727. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
182728. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
182729. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
182730. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
182731. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
182732. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
182733. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
182734. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
182735. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
182736. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
182737. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
182738. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
182739. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
182740. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
182741. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
182742. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
182743. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
182744. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
182745. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
182746. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
182747. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
182748. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
182749. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
182750. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
182751. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
182752. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
182753. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
182754. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
182755. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
182756. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
182757. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
182758. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
182759. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
182760. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
182761. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
182762. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
182763. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
182764. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
182765. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
182766. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
182767. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
182768. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
182769. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
182770. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
182771. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
182772. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
182773. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
182774. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
182775. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
182776. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
182777. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
182778. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
182779. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
182780. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
182781. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
182782. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
182783. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
182784. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
182785. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
182786. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
182787. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
182788. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
182789. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
182790. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
182791. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
182792. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
182793. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
182794. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
182795. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
182796. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
182797. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
182798. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
182799. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
182800. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
182801. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
182802. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
182803. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
182804. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
182805. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
182806. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
182807. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
182808. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
182809. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
182810. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
182811. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
182812. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
182813. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
182814. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
182815. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
182816. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
182817. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
182818. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
182819. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
182820. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
182821. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
182822. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
182823. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
182824. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
182825. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
182826. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
182827. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
182828. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
182829. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
182830. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
182831. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
182832. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
182833. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
182834. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
182835. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
182836. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
182837. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
182838. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
182839. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
182840. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
182841. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
182842. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
182843. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
182844. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
182845. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
182846. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
182847. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
182848. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
182849. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
182850. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
182851. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
182852. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
182853. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
182854. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
182855. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
182856. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
182857. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
182858. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
182859. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
182860. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
182861. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
182862. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
182863. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
182864. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
182865. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
182866. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
182867. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
182868. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
182869. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
182870. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
182871. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
182872. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
182873. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
182874. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
182875. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
182876. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
182877. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
182878. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
182879. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
182880. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
182881. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
182882. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
182883. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
182884. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
182885. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
182886. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
182887. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
182888. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
182889. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
182890. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
182891. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
182892. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
182893. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
182894. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
182895. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
182896. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
182897. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
182898. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
182899. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
182900. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
182901. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
182902. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
182903. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
182904. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
182905. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
182906. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
182907. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
182908. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
182909. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
182910. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
182911. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
182912. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
182913. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
182914. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
182915. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
182916. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
182917. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
182918. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
182919. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
182920. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
182921. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
182922. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
182923. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
182924. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
182925. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
182926. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
182927. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
182928. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
182929. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
182930. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
182931. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
182932. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
182933. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
182934. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
182935. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
182936. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
182937. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
182938. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
182939. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
182940. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
182941. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
182942. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
182943. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
182944. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
182945. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
182946. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
182947. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
182948. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
182949. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
182950. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
182951. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
182952. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
182953. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
182954. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
182955. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
182956. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
182957. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
182958. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
182959. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
182960. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
182961. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
182962. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
182963. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
182964. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
182965. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
182966. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
182967. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
182968. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
182969. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
182970. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
182971. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
182972. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
182973. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
182974. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
182975. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
182976. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
182977. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
182978. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
182979. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
182980. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
182981. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
182982. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
182983. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
182984. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
182985. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
182986. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
182987. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
182988. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
182989. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
182990. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
182991. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
182992. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
182993. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
182994. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
182995. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
182996. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
182997. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
182998. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
182999. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
183000. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
183001. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
183002. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
183003. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
183004. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
183005. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
183006. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
183007. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
183008. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
183009. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
183010. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
183011. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
183012. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
183013. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
183014. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
183015. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
183016. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
183017. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
183018. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
183019. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
183020. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
183021. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
183022. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
183023. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
183024. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
183025. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
183026. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
183027. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
183028. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
183029. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
183030. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
183031. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
183032. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
183033. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
183034. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
183035. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
183036. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
183037. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
183038. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
183039. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
183040. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
183041. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
183042. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
183043. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
183044. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
183045. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
183046. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
183047. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
183048. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
183049. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
183050. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
183051. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
183052. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
183053. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
183054. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
183055. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
183056. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
183057. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
183058. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
183059. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
183060. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
183061. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
183062. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
183063. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
183064. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
183065. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
183066. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
183067. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
183068. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
183069. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
183070. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
183071. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
183072. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
183073. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
183074. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
183075. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
183076. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
183077. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
183078. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
183079. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
183080. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
183081. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
183082. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
183083. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
183084. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
183085. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
183086. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
183087. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
183088. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
183089. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
183090. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
183091. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
183092. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
183093. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
183094. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
183095. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
183096. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
183097. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
183098. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
183099. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
183100. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
183101. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
183102. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
183103. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
183104. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
183105. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
183106. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
183107. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
183108. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
183109. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
183110. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
183111. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
183112. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
183113. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
183114. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
183115. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
183116. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
183117. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
183118. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
183119. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
183120. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
183121. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
183122. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
183123. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
183124. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
183125. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
183126. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
183127. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
183128. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
183129. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
183130. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
183131. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
183132. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
183133. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
183134. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
183135. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
183136. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
183137. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
183138. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
183139. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
183140. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
183141. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
183142. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
183143. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
183144. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
183145. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
183146. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
183147. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
183148. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
183149. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
183150. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
183151. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
183152. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
183153. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
183154. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
183155. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
183156. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
183157. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
183158. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
183159. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
183160. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK
183161. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT
183162. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK
183163. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT
183164. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
183165. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
183166. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK
183167. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT
183168. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK
183169. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT
183170. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK
183171. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT
183172. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
183173. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
183174. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
183175. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
183176. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
183177. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
183178. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
183179. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
183180. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
183181. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
183182. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
183183. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
183184. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
183185. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
183186. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
183187. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
183188. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
183189. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
183190. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
183191. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
183192. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
183193. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
183194. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
183195. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
183196. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
183197. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
183198. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
183199. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
183200. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
183201. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
183202. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
183203. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
183204. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
183205. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
183206. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
183207. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
183208. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
183209. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
183210. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
183211. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
183212. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
183213. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
183214. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
183215. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
183216. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
183217. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
183218. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
183219. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
183220. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
183221. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
183222. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
183223. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
183224. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
183225. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
183226. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
183227. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
183228. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
183229. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
183230. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
183231. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
183232. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
183233. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
183234. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
183235. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
183236. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
183237. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
183238. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
183239. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
183240. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
183241. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
183242. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
183243. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
183244. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
183245. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
183246. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
183247. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
183248. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
183249. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
183250. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
183251. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
183252. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
183253. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
183254. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
183255. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
183256. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
183257. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
183258. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
183259. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
183260. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
183261. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
183262. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
183263. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
183264. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
183265. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
183266. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
183267. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
183268. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
183269. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
183270. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
183271. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
183272. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
183273. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
183274. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
183275. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
183276. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
183277. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
183278. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
183279. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
183280. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
183281. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
183282. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
183283. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
183284. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
183285. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
183286. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
183287. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
183288. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
183289. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
183290. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
183291. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
183292. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
183293. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
183294. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
183295. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
183296. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
183297. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
183298. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
183299. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
183300. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
183301. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
183302. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
183303. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
183304. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
183305. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
183306. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
183307. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
183308. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
183309. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
183310. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
183311. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
183312. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
183313. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
183314. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
183315. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
183316. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
183317. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
183318. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
183319. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
183320. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
183321. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
183322. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
183323. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
183324. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
183325. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
183326. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
183327. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
183328. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
183329. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
183330. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
183331. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
183332. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
183333. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
183334. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
183335. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
183336. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
183337. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
183338. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
183339. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
183340. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
183341. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
183342. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
183343. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
183344. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
183345. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
183346. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
183347. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
183348. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
183349. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
183350. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
183351. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
183352. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
183353. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
183354. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
183355. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
183356. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
183357. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
183358. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
183359. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
183360. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
183361. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
183362. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
183363. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
183364. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
183365. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
183366. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
183367. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
183368. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
183369. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
183370. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
183371. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
183372. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
183373. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
183374. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
183375. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
183376. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
183377. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
183378. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
183379. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
183380. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
183381. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
183382. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
183383. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
183384. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
183385. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
183386. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
183387. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
183388. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
183389. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
183390. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
183391. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
183392. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
183393. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
183394. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
183395. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
183396. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
183397. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
183398. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
183399. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
183400. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
183401. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
183402. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
183403. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
183404. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
183405. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
183406. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
183407. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
183408. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
183409. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
183410. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
183411. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
183412. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
183413. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
183414. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
183415. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
183416. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
183417. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
183418. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
183419. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
183420. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
183421. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
183422. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
183423. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
183424. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
183425. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
183426. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
183427. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
183428. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
183429. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
183430. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
183431. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
183432. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
183433. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
183434. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
183435. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
183436. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
183437. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
183438. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
183439. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
183440. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
183441. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
183442. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
183443. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
183444. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
183445. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
183446. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
183447. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
183448. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
183449. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
183450. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
183451. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
183452. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
183453. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
183454. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
183455. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
183456. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
183457. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
183458. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
183459. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
183460. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
183461. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
183462. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
183463. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
183464. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
183465. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
183466. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
183467. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
183468. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
183469. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
183470. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
183471. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
183472. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
183473. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
183474. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
183475. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
183476. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
183477. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
183478. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
183479. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
183480. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
183481. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
183482. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
183483. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
183484. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
183485. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
183486. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
183487. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
183488. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
183489. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
183490. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
183491. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
183492. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
183493. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
183494. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
183495. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
183496. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
183497. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
183498. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
183499. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
183500. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
183501. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
183502. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
183503. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
183504. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
183505. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
183506. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
183507. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
183508. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
183509. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
183510. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
183511. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
183512. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
183513. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
183514. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK
183515. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT
183516. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK
183517. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT
183518. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
183519. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
183520. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
183521. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
183522. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
183523. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
183524. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
183525. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
183526. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
183527. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
183528. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
183529. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
183530. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
183531. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
183532. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
183533. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
183534. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
183535. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
183536. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
183537. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
183538. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
183539. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
183540. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
183541. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
183542. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
183543. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
183544. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
183545. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
183546. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
183547. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
183548. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
183549. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
183550. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
183551. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
183552. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
183553. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
183554. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
183555. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
183556. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
183557. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
183558. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
183559. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
183560. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
183561. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
183562. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
183563. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
183564. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
183565. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
183566. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
183567. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
183568. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
183569. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
183570. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
183571. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
183572. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
183573. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
183574. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
183575. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
183576. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
183577. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
183578. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
183579. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
183580. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
183581. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
183582. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
183583. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
183584. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
183585. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
183586. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
183587. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
183588. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
183589. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
183590. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
183591. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
183592. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
183593. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
183594. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
183595. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
183596. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
183597. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
183598. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
183599. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
183600. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
183601. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
183602. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
183603. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
183604. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
183605. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
183606. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
183607. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
183608. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
183609. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
183610. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
183611. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
183612. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
183613. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
183614. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
183615. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
183616. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
183617. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
183618. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
183619. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
183620. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
183621. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
183622. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
183623. DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
183624. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK
183625. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
183626. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK
183627. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT
183628. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK
183629. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
183630. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK
183631. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
183632. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK
183633. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
183634. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK
183635. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
183636. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK
183637. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
183638. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK
183639. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
183640. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK
183641. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
183642. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK
183643. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
183644. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK
183645. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
183646. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK
183647. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
183648. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK
183649. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
183650. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK
183651. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
183652. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK
183653. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
183654. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK
183655. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
183656. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK
183657. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
183658. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK
183659. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
183660. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK
183661. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
183662. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK
183663. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
183664. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK
183665. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
183666. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK
183667. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
183668. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK
183669. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
183670. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK
183671. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
183672. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK
183673. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
183674. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK
183675. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
183676. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK
183677. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
183678. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK
183679. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
183680. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK
183681. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
183682. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK
183683. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
183684. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK
183685. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
183686. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK
183687. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
183688. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK
183689. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
183690. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK
183691. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
183692. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK
183693. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
183694. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK
183695. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
183696. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK
183697. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
183698. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK
183699. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
183700. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK
183701. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
183702. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK
183703. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
183704. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK
183705. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
183706. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK
183707. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
183708. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK
183709. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
183710. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK
183711. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
183712. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK
183713. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
183714. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK
183715. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
183716. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK
183717. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
183718. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK
183719. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
183720. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK
183721. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
183722. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK
183723. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
183724. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK
183725. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
183726. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK
183727. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
183728. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK
183729. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
183730. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK
183731. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
183732. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK
183733. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
183734. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK
183735. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
183736. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK
183737. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
183738. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK
183739. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
183740. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK
183741. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
183742. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK
183743. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
183744. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK
183745. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
183746. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK
183747. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
183748. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK
183749. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
183750. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK
183751. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
183752. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK
183753. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
183754. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK
183755. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
183756. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK
183757. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
183758. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK
183759. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
183760. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK
183761. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
183762. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK
183763. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
183764. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK
183765. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
183766. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK
183767. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
183768. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK
183769. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
183770. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK
183771. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
183772. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK
183773. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
183774. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK
183775. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
183776. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK
183777. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
183778. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK
183779. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
183780. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK
183781. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
183782. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK
183783. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
183784. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK
183785. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
183786. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK
183787. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
183788. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK
183789. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
183790. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK
183791. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
183792. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK
183793. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
183794. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK
183795. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
183796. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK
183797. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
183798. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK
183799. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
183800. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK
183801. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
183802. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK
183803. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
183804. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK
183805. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
183806. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK
183807. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
183808. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK
183809. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
183810. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK
183811. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
183812. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK
183813. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
183814. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK
183815. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
183816. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK
183817. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
183818. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK
183819. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
183820. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK
183821. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
183822. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK
183823. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
183824. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK
183825. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
183826. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK
183827. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
183828. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK
183829. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
183830. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK
183831. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
183832. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK
183833. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
183834. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK
183835. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
183836. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK
183837. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
183838. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK
183839. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
183840. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK
183841. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
183842. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK
183843. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
183844. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK
183845. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
183846. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK
183847. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
183848. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK
183849. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
183850. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK
183851. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
183852. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK
183853. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
183854. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK
183855. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
183856. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK
183857. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
183858. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK
183859. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
183860. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK
183861. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
183862. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK
183863. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
183864. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK
183865. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
183866. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK
183867. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
183868. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK
183869. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
183870. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK
183871. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
183872. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK
183873. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
183874. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK
183875. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
183876. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK
183877. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
183878. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK
183879. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
183880. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK
183881. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
183882. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK
183883. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
183884. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK
183885. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
183886. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK
183887. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
183888. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK
183889. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
183890. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK
183891. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
183892. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK
183893. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
183894. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK
183895. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
183896. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK
183897. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
183898. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK
183899. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
183900. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK
183901. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
183902. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK
183903. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
183904. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK
183905. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
183906. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK
183907. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
183908. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK
183909. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
183910. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK
183911. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
183912. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK
183913. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
183914. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK
183915. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
183916. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK
183917. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
183918. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK
183919. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
183920. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK
183921. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
183922. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK
183923. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
183924. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK
183925. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
183926. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK
183927. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
183928. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK
183929. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
183930. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK
183931. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
183932. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK
183933. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
183934. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK
183935. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
183936. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK
183937. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
183938. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK
183939. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
183940. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK
183941. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
183942. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK
183943. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
183944. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK
183945. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
183946. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK
183947. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
183948. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK
183949. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
183950. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK
183951. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
183952. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK
183953. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
183954. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK
183955. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
183956. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK
183957. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
183958. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK
183959. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
183960. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK
183961. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
183962. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK
183963. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
183964. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK
183965. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
183966. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK
183967. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
183968. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK
183969. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
183970. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK
183971. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
183972. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK
183973. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
183974. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK
183975. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
183976. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK
183977. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
183978. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK
183979. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
183980. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK
183981. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
183982. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK
183983. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
183984. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK
183985. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
183986. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK
183987. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
183988. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK
183989. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
183990. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK
183991. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
183992. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK
183993. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
183994. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK
183995. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
183996. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK
183997. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
183998. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK
183999. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
184000. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK
184001. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
184002. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK
184003. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
184004. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK
184005. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
184006. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK
184007. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
184008. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK
184009. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
184010. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK
184011. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
184012. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK
184013. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
184014. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK
184015. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
184016. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK
184017. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
184018. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK
184019. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
184020. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK
184021. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
184022. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK
184023. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
184024. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK
184025. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
184026. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK
184027. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
184028. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK
184029. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
184030. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK
184031. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
184032. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK
184033. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
184034. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK
184035. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
184036. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK
184037. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
184038. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK
184039. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
184040. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK
184041. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
184042. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK
184043. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
184044. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK
184045. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
184046. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK
184047. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
184048. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK
184049. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
184050. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK
184051. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
184052. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK
184053. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
184054. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK
184055. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
184056. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK
184057. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
184058. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK
184059. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
184060. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK
184061. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
184062. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK
184063. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
184064. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK
184065. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
184066. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK
184067. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
184068. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK
184069. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
184070. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK
184071. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
184072. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK
184073. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
184074. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK
184075. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
184076. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK
184077. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
184078. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK
184079. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
184080. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK
184081. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
184082. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK
184083. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
184084. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK
184085. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
184086. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK
184087. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
184088. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK
184089. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
184090. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK
184091. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
184092. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK
184093. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
184094. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK
184095. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
184096. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK
184097. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
184098. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK
184099. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
184100. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK
184101. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
184102. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK
184103. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
184104. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK
184105. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
184106. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK
184107. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
184108. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK
184109. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
184110. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK
184111. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
184112. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK
184113. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
184114. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK
184115. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
184116. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK
184117. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
184118. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK
184119. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
184120. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK
184121. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
184122. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK
184123. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
184124. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK
184125. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
184126. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK
184127. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
184128. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK
184129. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
184130. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK
184131. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
184132. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK
184133. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
184134. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK
184135. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
184136. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK
184137. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
184138. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK
184139. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
184140. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK
184141. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
184142. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK
184143. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
184144. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK
184145. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
184146. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK
184147. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
184148. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK
184149. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
184150. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK
184151. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
184152. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK
184153. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
184154. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK
184155. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
184156. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK
184157. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
184158. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK
184159. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
184160. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK
184161. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
184162. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK
184163. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
184164. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK
184165. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
184166. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK
184167. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
184168. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK
184169. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
184170. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK
184171. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
184172. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK
184173. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
184174. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK
184175. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
184176. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK
184177. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
184178. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK
184179. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
184180. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK
184181. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
184182. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK
184183. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
184184. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK
184185. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
184186. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK
184187. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
184188. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK
184189. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
184190. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK
184191. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
184192. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK
184193. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
184194. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK
184195. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
184196. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK
184197. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
184198. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK
184199. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
184200. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK
184201. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
184202. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK
184203. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
184204. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK
184205. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
184206. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK
184207. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
184208. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK
184209. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
184210. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK
184211. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
184212. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK
184213. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
184214. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK
184215. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
184216. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK
184217. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
184218. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK
184219. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
184220. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK
184221. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
184222. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK
184223. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
184224. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK
184225. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
184226. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK
184227. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
184228. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK
184229. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
184230. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK
184231. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
184232. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK
184233. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
184234. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK
184235. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
184236. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK
184237. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
184238. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK
184239. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
184240. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK
184241. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
184242. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK
184243. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
184244. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK
184245. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
184246. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK
184247. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
184248. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK
184249. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
184250. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK
184251. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
184252. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK
184253. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
184254. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK
184255. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
184256. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK
184257. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
184258. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK
184259. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
184260. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK
184261. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
184262. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK
184263. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
184264. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK
184265. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
184266. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK
184267. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
184268. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK
184269. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
184270. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK
184271. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
184272. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK
184273. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
184274. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK
184275. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
184276. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK
184277. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
184278. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK
184279. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
184280. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK
184281. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
184282. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK
184283. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
184284. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK
184285. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
184286. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK
184287. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
184288. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK
184289. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
184290. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK
184291. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
184292. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK
184293. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
184294. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK
184295. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
184296. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK
184297. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
184298. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK
184299. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
184300. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK
184301. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
184302. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK
184303. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
184304. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK
184305. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
184306. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK
184307. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
184308. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK
184309. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
184310. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK
184311. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
184312. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK
184313. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
184314. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK
184315. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
184316. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK
184317. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
184318. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK
184319. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
184320. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK
184321. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
184322. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK
184323. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
184324. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK
184325. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
184326. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK
184327. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
184328. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK
184329. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
184330. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK
184331. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
184332. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK
184333. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
184334. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK
184335. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
184336. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK
184337. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
184338. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK
184339. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
184340. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK
184341. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
184342. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK
184343. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
184344. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK
184345. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
184346. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK
184347. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
184348. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK
184349. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
184350. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK
184351. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
184352. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK
184353. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
184354. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK
184355. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
184356. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK
184357. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
184358. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK
184359. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
184360. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK
184361. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
184362. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK
184363. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
184364. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK
184365. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
184366. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK
184367. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
184368. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK
184369. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
184370. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK
184371. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
184372. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK
184373. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
184374. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK
184375. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
184376. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK
184377. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
184378. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK
184379. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
184380. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK
184381. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
184382. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK
184383. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
184384. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK
184385. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
184386. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK
184387. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
184388. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK
184389. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
184390. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK
184391. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
184392. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK
184393. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
184394. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK
184395. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
184396. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK
184397. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
184398. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK
184399. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
184400. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK
184401. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
184402. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK
184403. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
184404. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK
184405. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
184406. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK
184407. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
184408. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK
184409. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
184410. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK
184411. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
184412. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK
184413. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
184414. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK
184415. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
184416. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK
184417. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
184418. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK
184419. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
184420. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK
184421. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
184422. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK
184423. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
184424. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK
184425. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
184426. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK
184427. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
184428. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK
184429. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
184430. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK
184431. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
184432. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK
184433. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
184434. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK
184435. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
184436. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK
184437. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
184438. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK
184439. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
184440. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK
184441. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
184442. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK
184443. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
184444. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK
184445. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
184446. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK
184447. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
184448. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK
184449. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
184450. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK
184451. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
184452. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK
184453. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
184454. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK
184455. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
184456. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK
184457. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
184458. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK
184459. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
184460. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK
184461. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
184462. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK
184463. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
184464. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK
184465. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
184466. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK
184467. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
184468. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK
184469. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
184470. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK
184471. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
184472. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK
184473. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
184474. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK
184475. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
184476. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK
184477. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
184478. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK
184479. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
184480. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK
184481. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
184482. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK
184483. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
184484. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK
184485. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
184486. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK
184487. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
184488. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK
184489. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
184490. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK
184491. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
184492. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK
184493. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
184494. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK
184495. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
184496. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK
184497. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
184498. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK
184499. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
184500. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK
184501. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
184502. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK
184503. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
184504. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK
184505. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
184506. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK
184507. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
184508. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK
184509. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
184510. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK
184511. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
184512. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK
184513. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
184514. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK
184515. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
184516. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK
184517. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
184518. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK
184519. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
184520. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK
184521. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
184522. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK
184523. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
184524. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK
184525. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
184526. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK
184527. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
184528. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK
184529. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
184530. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK
184531. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
184532. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK
184533. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
184534. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK
184535. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
184536. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK
184537. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
184538. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK
184539. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
184540. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK
184541. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
184542. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK
184543. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
184544. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK
184545. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
184546. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK
184547. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
184548. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK
184549. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
184550. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK
184551. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
184552. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK
184553. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
184554. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK
184555. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
184556. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK
184557. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
184558. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK
184559. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
184560. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK
184561. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
184562. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK
184563. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
184564. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK
184565. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
184566. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK
184567. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
184568. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK
184569. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
184570. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK
184571. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
184572. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK
184573. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
184574. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK
184575. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
184576. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK
184577. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
184578. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK
184579. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
184580. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK
184581. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
184582. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK
184583. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
184584. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK
184585. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
184586. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK
184587. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
184588. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK
184589. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
184590. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK
184591. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
184592. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK
184593. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
184594. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK
184595. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
184596. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK
184597. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
184598. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK
184599. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
184600. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK
184601. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
184602. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK
184603. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
184604. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK
184605. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
184606. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK
184607. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
184608. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK
184609. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
184610. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK
184611. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
184612. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK
184613. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
184614. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK
184615. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
184616. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK
184617. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
184618. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK
184619. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
184620. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK
184621. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
184622. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK
184623. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
184624. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK
184625. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
184626. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK
184627. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
184628. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK
184629. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
184630. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK
184631. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
184632. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK
184633. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
184634. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK
184635. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
184636. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK
184637. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
184638. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK
184639. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
184640. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK
184641. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
184642. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK
184643. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
184644. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK
184645. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
184646. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK
184647. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
184648. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK
184649. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
184650. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK
184651. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
184652. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK
184653. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
184654. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK
184655. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
184656. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK
184657. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
184658. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK
184659. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
184660. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK
184661. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
184662. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK
184663. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
184664. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK
184665. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
184666. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK
184667. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
184668. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK
184669. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
184670. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK
184671. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
184672. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK
184673. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
184674. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK
184675. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
184676. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK
184677. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
184678. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK
184679. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
184680. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK
184681. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
184682. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK
184683. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
184684. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK
184685. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
184686. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK
184687. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
184688. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK
184689. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
184690. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK
184691. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
184692. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK
184693. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
184694. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK
184695. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
184696. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK
184697. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
184698. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK
184699. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
184700. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK
184701. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
184702. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK
184703. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
184704. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK
184705. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
184706. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK
184707. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
184708. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK
184709. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
184710. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK
184711. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
184712. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK
184713. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
184714. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK
184715. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
184716. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK
184717. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
184718. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK
184719. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
184720. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK
184721. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
184722. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK
184723. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
184724. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK
184725. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
184726. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK
184727. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
184728. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK
184729. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
184730. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK
184731. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
184732. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK
184733. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
184734. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK
184735. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
184736. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK
184737. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
184738. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK
184739. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
184740. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK
184741. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
184742. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK
184743. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
184744. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK
184745. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
184746. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK
184747. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
184748. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK
184749. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
184750. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK
184751. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
184752. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK
184753. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
184754. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK
184755. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
184756. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK
184757. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
184758. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK
184759. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
184760. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK
184761. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
184762. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK
184763. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
184764. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK
184765. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
184766. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK
184767. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
184768. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK
184769. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
184770. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK
184771. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
184772. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK
184773. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
184774. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK
184775. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
184776. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK
184777. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
184778. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK
184779. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
184780. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK
184781. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
184782. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK
184783. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
184784. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK
184785. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
184786. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK
184787. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
184788. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK
184789. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
184790. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK
184791. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
184792. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK
184793. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
184794. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK
184795. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
184796. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK
184797. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
184798. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK
184799. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
184800. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK
184801. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
184802. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK
184803. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
184804. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK
184805. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
184806. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK
184807. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
184808. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK
184809. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
184810. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK
184811. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
184812. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK
184813. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
184814. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK
184815. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
184816. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK
184817. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
184818. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK
184819. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
184820. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK
184821. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
184822. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK
184823. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
184824. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK
184825. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
184826. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK
184827. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
184828. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK
184829. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
184830. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK
184831. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
184832. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK
184833. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
184834. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK
184835. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
184836. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK
184837. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
184838. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK
184839. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
184840. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK
184841. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
184842. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK
184843. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
184844. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK
184845. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
184846. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK
184847. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
184848. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK
184849. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
184850. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK
184851. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
184852. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK
184853. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
184854. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK
184855. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
184856. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK
184857. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
184858. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK
184859. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
184860. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK
184861. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
184862. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK
184863. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
184864. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK
184865. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
184866. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK
184867. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
184868. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK
184869. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
184870. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK
184871. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
184872. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK
184873. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
184874. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK
184875. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
184876. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK
184877. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
184878. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK
184879. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
184880. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK
184881. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
184882. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK
184883. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
184884. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK
184885. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
184886. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK
184887. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
184888. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK
184889. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
184890. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK
184891. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
184892. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK
184893. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
184894. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK
184895. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
184896. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK
184897. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
184898. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK
184899. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
184900. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK
184901. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
184902. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK
184903. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
184904. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK
184905. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
184906. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK
184907. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
184908. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK
184909. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
184910. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK
184911. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
184912. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK
184913. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
184914. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK
184915. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
184916. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK
184917. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
184918. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK
184919. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
184920. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK
184921. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
184922. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK
184923. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
184924. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK
184925. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
184926. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK
184927. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
184928. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK
184929. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
184930. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK
184931. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
184932. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK
184933. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
184934. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK
184935. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
184936. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK
184937. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
184938. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK
184939. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
184940. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK
184941. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
184942. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK
184943. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
184944. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK
184945. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
184946. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK
184947. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
184948. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK
184949. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
184950. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK
184951. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
184952. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK
184953. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
184954. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK
184955. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
184956. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK
184957. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
184958. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK
184959. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
184960. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK
184961. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
184962. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK
184963. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
184964. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK
184965. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
184966. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK
184967. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
184968. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK
184969. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
184970. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK
184971. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
184972. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK
184973. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
184974. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK
184975. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
184976. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK
184977. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
184978. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK
184979. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
184980. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK
184981. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
184982. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK
184983. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
184984. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK
184985. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
184986. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK
184987. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
184988. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK
184989. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
184990. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK
184991. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
184992. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK
184993. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
184994. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK
184995. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
184996. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK
184997. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
184998. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK
184999. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
185000. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK
185001. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
185002. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK
185003. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
185004. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK
185005. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
185006. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK
185007. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
185008. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK
185009. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
185010. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK
185011. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
185012. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK
185013. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
185014. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK
185015. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
185016. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK
185017. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
185018. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK
185019. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
185020. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK
185021. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
185022. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK
185023. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
185024. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK
185025. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
185026. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK
185027. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
185028. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK
185029. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
185030. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK
185031. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
185032. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK
185033. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
185034. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK
185035. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
185036. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK
185037. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
185038. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK
185039. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
185040. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK
185041. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
185042. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK
185043. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
185044. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK
185045. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
185046. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK
185047. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
185048. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK
185049. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
185050. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK
185051. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
185052. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK
185053. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
185054. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK
185055. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
185056. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK
185057. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
185058. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK
185059. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
185060. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK
185061. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
185062. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK
185063. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
185064. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK
185065. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
185066. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK
185067. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
185068. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK
185069. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
185070. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK
185071. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
185072. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK
185073. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
185074. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK
185075. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
185076. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK
185077. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
185078. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK
185079. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
185080. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK
185081. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
185082. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK
185083. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
185084. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK
185085. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
185086. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK
185087. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
185088. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK
185089. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
185090. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK
185091. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
185092. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK
185093. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
185094. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK
185095. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
185096. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK
185097. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
185098. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK
185099. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
185100. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK
185101. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
185102. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK
185103. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
185104. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK
185105. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
185106. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK
185107. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
185108. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK
185109. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
185110. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK
185111. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
185112. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK
185113. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
185114. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK
185115. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
185116. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK
185117. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
185118. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK
185119. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
185120. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK
185121. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
185122. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK
185123. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
185124. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK
185125. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
185126. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK
185127. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
185128. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK
185129. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
185130. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK
185131. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
185132. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK
185133. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
185134. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK
185135. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
185136. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK
185137. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
185138. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK
185139. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
185140. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK
185141. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
185142. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK
185143. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
185144. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK
185145. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
185146. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK
185147. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
185148. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK
185149. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
185150. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK
185151. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
185152. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK
185153. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
185154. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK
185155. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
185156. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK
185157. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
185158. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK
185159. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
185160. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK
185161. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
185162. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK
185163. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
185164. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK
185165. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
185166. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK
185167. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
185168. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK
185169. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
185170. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK
185171. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
185172. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK
185173. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
185174. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK
185175. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
185176. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK
185177. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
185178. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK
185179. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
185180. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK
185181. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
185182. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK
185183. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
185184. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK
185185. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
185186. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK
185187. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
185188. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK
185189. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
185190. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK
185191. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
185192. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK
185193. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
185194. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK
185195. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
185196. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK
185197. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
185198. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK
185199. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
185200. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK
185201. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
185202. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK
185203. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
185204. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK
185205. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
185206. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK
185207. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
185208. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK
185209. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
185210. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK
185211. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
185212. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK
185213. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
185214. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK
185215. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
185216. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK
185217. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
185218. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK
185219. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
185220. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK
185221. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
185222. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK
185223. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
185224. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK
185225. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
185226. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK
185227. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
185228. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK
185229. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
185230. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK
185231. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
185232. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK
185233. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
185234. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK
185235. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
185236. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK
185237. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
185238. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK
185239. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
185240. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK
185241. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
185242. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK
185243. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
185244. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK
185245. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
185246. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK
185247. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
185248. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK
185249. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
185250. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK
185251. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
185252. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK
185253. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
185254. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK
185255. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
185256. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK
185257. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
185258. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK
185259. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
185260. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK
185261. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
185262. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK
185263. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
185264. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK
185265. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
185266. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK
185267. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
185268. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK
185269. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
185270. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK
185271. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
185272. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK
185273. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
185274. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK
185275. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
185276. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK
185277. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
185278. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK
185279. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
185280. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK
185281. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
185282. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK
185283. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
185284. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK
185285. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
185286. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK
185287. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
185288. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK
185289. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
185290. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK
185291. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
185292. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK
185293. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
185294. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK
185295. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
185296. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK
185297. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
185298. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK
185299. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
185300. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK
185301. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
185302. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK
185303. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
185304. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK
185305. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
185306. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK
185307. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
185308. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK
185309. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
185310. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK
185311. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
185312. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK
185313. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
185314. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK
185315. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
185316. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK
185317. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
185318. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK
185319. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
185320. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK
185321. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
185322. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK
185323. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
185324. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK
185325. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
185326. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK
185327. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
185328. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK
185329. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
185330. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK
185331. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
185332. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK
185333. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
185334. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK
185335. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
185336. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK
185337. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
185338. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK
185339. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
185340. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK
185341. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
185342. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK
185343. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
185344. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK
185345. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
185346. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK
185347. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
185348. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK
185349. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
185350. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK
185351. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
185352. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK
185353. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
185354. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK
185355. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
185356. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK
185357. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
185358. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK
185359. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
185360. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK
185361. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
185362. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK
185363. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
185364. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK
185365. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
185366. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK
185367. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
185368. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK
185369. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
185370. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK
185371. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
185372. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK
185373. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
185374. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK
185375. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
185376. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK
185377. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
185378. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK
185379. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
185380. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK
185381. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
185382. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK
185383. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
185384. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK
185385. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
185386. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK
185387. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
185388. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK
185389. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
185390. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK
185391. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
185392. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK
185393. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
185394. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK
185395. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
185396. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK
185397. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
185398. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK
185399. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
185400. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK
185401. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
185402. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK
185403. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
185404. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK
185405. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
185406. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK
185407. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
185408. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK
185409. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
185410. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK
185411. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
185412. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK
185413. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
185414. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK
185415. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
185416. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK
185417. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
185418. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK
185419. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
185420. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK
185421. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
185422. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK
185423. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
185424. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK
185425. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
185426. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK
185427. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
185428. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK
185429. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
185430. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK
185431. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
185432. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK
185433. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
185434. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK
185435. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
185436. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK
185437. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
185438. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK
185439. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
185440. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK
185441. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
185442. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK
185443. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
185444. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK
185445. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
185446. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK
185447. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
185448. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK
185449. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
185450. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK
185451. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
185452. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK
185453. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
185454. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK
185455. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
185456. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK
185457. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
185458. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK
185459. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
185460. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK
185461. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
185462. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK
185463. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
185464. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK
185465. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
185466. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK
185467. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
185468. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK
185469. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
185470. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK
185471. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
185472. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK
185473. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
185474. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK
185475. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
185476. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK
185477. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
185478. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK
185479. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
185480. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK
185481. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
185482. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK
185483. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
185484. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK
185485. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
185486. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK
185487. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
185488. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK
185489. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
185490. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK
185491. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
185492. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK
185493. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
185494. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK
185495. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
185496. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK
185497. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
185498. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK
185499. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
185500. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK
185501. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
185502. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK
185503. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
185504. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK
185505. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
185506. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK
185507. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
185508. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK
185509. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
185510. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK
185511. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
185512. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK
185513. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
185514. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK
185515. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
185516. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK
185517. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
185518. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK
185519. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
185520. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK
185521. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
185522. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK
185523. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
185524. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK
185525. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
185526. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK
185527. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
185528. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK
185529. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
185530. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK
185531. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
185532. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK
185533. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
185534. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK
185535. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
185536. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK
185537. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
185538. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK
185539. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
185540. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK
185541. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
185542. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK
185543. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
185544. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK
185545. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
185546. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK
185547. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
185548. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK
185549. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
185550. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK
185551. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
185552. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK
185553. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
185554. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK
185555. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
185556. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK
185557. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
185558. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK
185559. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
185560. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK
185561. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
185562. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK
185563. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
185564. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK
185565. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
185566. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK
185567. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
185568. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK
185569. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
185570. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK
185571. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
185572. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK
185573. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
185574. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK
185575. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
185576. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK
185577. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
185578. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK
185579. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
185580. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK
185581. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
185582. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK
185583. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
185584. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK
185585. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
185586. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK
185587. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
185588. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK
185589. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
185590. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK
185591. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
185592. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK
185593. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
185594. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK
185595. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
185596. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK
185597. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
185598. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK
185599. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
185600. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK
185601. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
185602. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK
185603. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
185604. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK
185605. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
185606. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK
185607. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
185608. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK
185609. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
185610. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK
185611. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
185612. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK
185613. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
185614. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK
185615. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
185616. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK
185617. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
185618. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK
185619. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
185620. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK
185621. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
185622. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK
185623. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
185624. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK
185625. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
185626. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK
185627. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
185628. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK
185629. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
185630. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK
185631. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
185632. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK
185633. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
185634. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK
185635. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
185636. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK
185637. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
185638. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK
185639. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
185640. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK
185641. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
185642. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK
185643. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
185644. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK
185645. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
185646. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK
185647. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
185648. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK
185649. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
185650. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK
185651. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
185652. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK
185653. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
185654. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK
185655. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
185656. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK
185657. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
185658. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK
185659. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
185660. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK
185661. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
185662. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK
185663. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
185664. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK
185665. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
185666. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK
185667. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
185668. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK
185669. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
185670. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK
185671. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
185672. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK
185673. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
185674. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK
185675. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
185676. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK
185677. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
185678. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK
185679. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
185680. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK
185681. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
185682. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK
185683. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
185684. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK
185685. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
185686. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK
185687. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
185688. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK
185689. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
185690. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK
185691. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
185692. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK
185693. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
185694. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK
185695. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
185696. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK
185697. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
185698. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK
185699. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
185700. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK
185701. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
185702. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK
185703. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
185704. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK
185705. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
185706. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK
185707. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
185708. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK
185709. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
185710. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK
185711. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
185712. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK
185713. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
185714. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK
185715. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
185716. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK
185717. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
185718. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK
185719. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
185720. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK
185721. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
185722. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK
185723. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
185724. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK
185725. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
185726. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK
185727. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
185728. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK
185729. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
185730. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK
185731. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
185732. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK
185733. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
185734. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK
185735. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
185736. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK
185737. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
185738. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK
185739. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
185740. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK
185741. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
185742. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK
185743. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
185744. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK
185745. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
185746. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK
185747. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
185748. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK
185749. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
185750. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK
185751. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
185752. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK
185753. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
185754. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK
185755. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
185756. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK
185757. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
185758. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK
185759. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
185760. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK
185761. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
185762. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK
185763. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
185764. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK
185765. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
185766. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK
185767. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
185768. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK
185769. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
185770. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK
185771. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
185772. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK
185773. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
185774. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK
185775. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
185776. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK
185777. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
185778. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK
185779. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
185780. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK
185781. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
185782. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK
185783. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
185784. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK
185785. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
185786. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK
185787. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
185788. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK
185789. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
185790. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK
185791. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
185792. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK
185793. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
185794. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK
185795. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
185796. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK
185797. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
185798. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK
185799. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
185800. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK
185801. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
185802. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK
185803. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
185804. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK
185805. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
185806. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK
185807. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
185808. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK
185809. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
185810. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK
185811. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
185812. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK
185813. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
185814. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK
185815. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
185816. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK
185817. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
185818. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK
185819. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
185820. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK
185821. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
185822. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK
185823. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
185824. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK
185825. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
185826. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK
185827. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
185828. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK
185829. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
185830. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK
185831. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
185832. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK
185833. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
185834. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK
185835. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
185836. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK
185837. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
185838. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK
185839. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
185840. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK
185841. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
185842. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK
185843. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
185844. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK
185845. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
185846. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK
185847. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
185848. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK
185849. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
185850. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK
185851. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
185852. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK
185853. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
185854. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK
185855. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
185856. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK
185857. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
185858. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK
185859. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
185860. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK
185861. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
185862. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK
185863. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
185864. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK
185865. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
185866. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK
185867. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
185868. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK
185869. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
185870. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK
185871. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
185872. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK
185873. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
185874. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK
185875. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
185876. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK
185877. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
185878. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK
185879. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
185880. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK
185881. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
185882. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK
185883. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
185884. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK
185885. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
185886. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK
185887. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
185888. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK
185889. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
185890. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK
185891. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
185892. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK
185893. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
185894. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK
185895. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
185896. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK
185897. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
185898. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK
185899. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
185900. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK
185901. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
185902. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK
185903. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
185904. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK
185905. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
185906. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK
185907. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
185908. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK
185909. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
185910. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK
185911. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
185912. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK
185913. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
185914. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK
185915. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
185916. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK
185917. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
185918. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK
185919. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
185920. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK
185921. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
185922. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK
185923. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
185924. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK
185925. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
185926. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK
185927. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
185928. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK
185929. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
185930. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK
185931. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
185932. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK
185933. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
185934. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK
185935. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
185936. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK
185937. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
185938. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK
185939. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
185940. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK
185941. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
185942. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK
185943. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
185944. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK
185945. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
185946. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK
185947. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
185948. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK
185949. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
185950. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK
185951. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
185952. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK
185953. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
185954. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK
185955. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
185956. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK
185957. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
185958. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK
185959. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
185960. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK
185961. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
185962. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK
185963. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
185964. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK
185965. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
185966. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK
185967. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
185968. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK
185969. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
185970. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK
185971. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
185972. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK
185973. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
185974. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK
185975. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
185976. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK
185977. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
185978. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK
185979. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
185980. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK
185981. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
185982. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK
185983. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
185984. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK
185985. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
185986. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK
185987. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
185988. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK
185989. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
185990. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK
185991. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
185992. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK
185993. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
185994. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK
185995. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
185996. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK
185997. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
185998. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK
185999. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
186000. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK
186001. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
186002. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK
186003. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
186004. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK
186005. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
186006. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK
186007. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
186008. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK
186009. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
186010. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK
186011. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
186012. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK
186013. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
186014. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK
186015. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
186016. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK
186017. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
186018. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK
186019. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
186020. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK
186021. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
186022. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK
186023. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
186024. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK
186025. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
186026. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK
186027. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
186028. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK
186029. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
186030. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK
186031. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
186032. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK
186033. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
186034. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK
186035. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
186036. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK
186037. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
186038. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK
186039. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
186040. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK
186041. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
186042. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK
186043. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
186044. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK
186045. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
186046. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK
186047. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
186048. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK
186049. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
186050. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK
186051. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
186052. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK
186053. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
186054. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK
186055. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
186056. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK
186057. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
186058. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK
186059. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
186060. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK
186061. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
186062. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK
186063. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
186064. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK
186065. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
186066. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK
186067. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
186068. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK
186069. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
186070. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK
186071. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
186072. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK
186073. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
186074. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK
186075. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
186076. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK
186077. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
186078. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK
186079. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
186080. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK
186081. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
186082. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK
186083. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
186084. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK
186085. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
186086. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK
186087. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
186088. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK
186089. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
186090. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK
186091. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
186092. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK
186093. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
186094. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK
186095. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
186096. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK
186097. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
186098. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK
186099. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
186100. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK
186101. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
186102. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK
186103. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
186104. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK
186105. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
186106. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK
186107. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
186108. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK
186109. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
186110. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK
186111. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
186112. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK
186113. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
186114. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK
186115. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
186116. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK
186117. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
186118. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK
186119. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
186120. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK
186121. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
186122. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK
186123. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
186124. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
186125. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
186126. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
186127. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
186128. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
186129. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
186130. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
186131. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
186132. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
186133. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
186134. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
186135. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
186136. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
186137. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
186138. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
186139. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
186140. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
186141. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
186142. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
186143. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
186144. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
186145. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
186146. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
186147. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
186148. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
186149. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
186150. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
186151. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
186152. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
186153. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
186154. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
186155. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
186156. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
186157. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
186158. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
186159. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
186160. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
186161. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
186162. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
186163. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
186164. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK
186165. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
186166. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK
186167. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT
186168. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK
186169. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
186170. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK
186171. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
186172. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK
186173. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
186174. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK
186175. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
186176. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK
186177. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
186178. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK
186179. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
186180. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK
186181. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
186182. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK
186183. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
186184. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK
186185. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
186186. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK
186187. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
186188. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK
186189. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
186190. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK
186191. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
186192. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK
186193. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
186194. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK
186195. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
186196. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK
186197. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
186198. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK
186199. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
186200. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK
186201. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
186202. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK
186203. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
186204. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK
186205. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
186206. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK
186207. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
186208. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK
186209. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
186210. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK
186211. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
186212. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK
186213. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
186214. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK
186215. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
186216. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK
186217. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
186218. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK
186219. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
186220. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK
186221. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
186222. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK
186223. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
186224. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK
186225. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
186226. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK
186227. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
186228. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK
186229. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
186230. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK
186231. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
186232. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK
186233. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
186234. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK
186235. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
186236. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK
186237. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
186238. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK
186239. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
186240. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK
186241. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
186242. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK
186243. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
186244. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK
186245. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
186246. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK
186247. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
186248. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK
186249. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
186250. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK
186251. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
186252. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK
186253. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
186254. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK
186255. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
186256. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK
186257. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
186258. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK
186259. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
186260. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK
186261. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
186262. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK
186263. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
186264. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK
186265. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
186266. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK
186267. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
186268. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK
186269. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
186270. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK
186271. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
186272. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK
186273. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
186274. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK
186275. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
186276. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK
186277. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
186278. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK
186279. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
186280. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK
186281. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
186282. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK
186283. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
186284. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK
186285. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
186286. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK
186287. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
186288. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK
186289. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
186290. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK
186291. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
186292. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK
186293. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
186294. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK
186295. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
186296. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK
186297. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
186298. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK
186299. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
186300. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK
186301. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
186302. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK
186303. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
186304. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK
186305. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
186306. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK
186307. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
186308. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK
186309. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
186310. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK
186311. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
186312. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK
186313. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
186314. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK
186315. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
186316. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK
186317. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
186318. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK
186319. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
186320. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK
186321. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
186322. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK
186323. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
186324. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK
186325. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
186326. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK
186327. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
186328. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK
186329. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
186330. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK
186331. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
186332. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK
186333. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
186334. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK
186335. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
186336. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK
186337. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
186338. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK
186339. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
186340. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK
186341. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
186342. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK
186343. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
186344. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK
186345. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
186346. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK
186347. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
186348. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK
186349. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
186350. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK
186351. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
186352. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK
186353. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
186354. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK
186355. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
186356. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK
186357. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
186358. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK
186359. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
186360. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK
186361. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
186362. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK
186363. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
186364. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK
186365. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
186366. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK
186367. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
186368. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK
186369. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
186370. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK
186371. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
186372. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK
186373. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
186374. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK
186375. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
186376. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK
186377. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
186378. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK
186379. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
186380. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK
186381. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
186382. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK
186383. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
186384. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK
186385. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
186386. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK
186387. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
186388. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK
186389. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
186390. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK
186391. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
186392. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK
186393. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
186394. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK
186395. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
186396. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK
186397. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
186398. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK
186399. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
186400. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK
186401. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
186402. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK
186403. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
186404. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK
186405. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
186406. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK
186407. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
186408. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK
186409. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
186410. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK
186411. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
186412. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK
186413. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
186414. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK
186415. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
186416. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK
186417. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
186418. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK
186419. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
186420. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK
186421. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
186422. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK
186423. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
186424. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK
186425. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
186426. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK
186427. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
186428. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK
186429. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
186430. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK
186431. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
186432. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK
186433. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
186434. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK
186435. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
186436. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK
186437. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
186438. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK
186439. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
186440. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK
186441. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
186442. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK
186443. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
186444. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK
186445. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
186446. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK
186447. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
186448. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK
186449. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
186450. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK
186451. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
186452. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK
186453. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
186454. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK
186455. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
186456. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK
186457. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
186458. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK
186459. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
186460. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK
186461. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
186462. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK
186463. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
186464. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK
186465. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
186466. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK
186467. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
186468. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK
186469. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
186470. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK
186471. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
186472. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK
186473. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
186474. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK
186475. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
186476. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK
186477. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
186478. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK
186479. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
186480. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK
186481. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
186482. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK
186483. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
186484. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK
186485. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
186486. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK
186487. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
186488. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK
186489. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
186490. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK
186491. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
186492. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK
186493. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
186494. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK
186495. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
186496. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK
186497. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
186498. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK
186499. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
186500. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK
186501. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
186502. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK
186503. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
186504. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK
186505. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
186506. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK
186507. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
186508. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK
186509. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
186510. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK
186511. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
186512. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK
186513. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
186514. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK
186515. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
186516. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK
186517. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
186518. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK
186519. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
186520. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK
186521. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
186522. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK
186523. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
186524. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK
186525. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
186526. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK
186527. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
186528. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK
186529. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
186530. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK
186531. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
186532. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK
186533. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
186534. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK
186535. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
186536. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK
186537. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
186538. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK
186539. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
186540. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK
186541. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
186542. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK
186543. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
186544. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK
186545. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
186546. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK
186547. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
186548. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK
186549. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
186550. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK
186551. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
186552. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK
186553. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
186554. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK
186555. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
186556. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK
186557. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
186558. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK
186559. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
186560. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK
186561. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
186562. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK
186563. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
186564. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK
186565. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
186566. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK
186567. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
186568. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK
186569. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
186570. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK
186571. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
186572. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK
186573. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
186574. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK
186575. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
186576. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK
186577. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
186578. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK
186579. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
186580. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK
186581. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
186582. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK
186583. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
186584. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK
186585. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
186586. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK
186587. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
186588. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK
186589. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
186590. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK
186591. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
186592. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK
186593. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
186594. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK
186595. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
186596. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK
186597. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
186598. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK
186599. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
186600. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK
186601. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
186602. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK
186603. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
186604. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK
186605. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
186606. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK
186607. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
186608. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK
186609. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
186610. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK
186611. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
186612. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK
186613. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
186614. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK
186615. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
186616. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK
186617. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
186618. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK
186619. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
186620. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK
186621. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
186622. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK
186623. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
186624. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK
186625. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
186626. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK
186627. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
186628. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK
186629. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
186630. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK
186631. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
186632. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK
186633. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
186634. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK
186635. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
186636. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK
186637. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
186638. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK
186639. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
186640. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK
186641. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
186642. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK
186643. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
186644. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK
186645. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
186646. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK
186647. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
186648. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK
186649. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
186650. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK
186651. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
186652. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK
186653. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
186654. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK
186655. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
186656. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK
186657. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
186658. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK
186659. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
186660. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK
186661. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
186662. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK
186663. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
186664. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK
186665. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
186666. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK
186667. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
186668. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK
186669. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
186670. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK
186671. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
186672. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK
186673. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
186674. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK
186675. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
186676. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK
186677. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
186678. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK
186679. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
186680. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK
186681. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
186682. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK
186683. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
186684. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK
186685. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
186686. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK
186687. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
186688. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK
186689. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
186690. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK
186691. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
186692. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK
186693. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
186694. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK
186695. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
186696. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK
186697. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
186698. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK
186699. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
186700. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK
186701. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
186702. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK
186703. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
186704. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK
186705. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
186706. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK
186707. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
186708. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK
186709. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
186710. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK
186711. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
186712. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK
186713. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
186714. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK
186715. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
186716. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK
186717. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
186718. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK
186719. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
186720. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK
186721. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
186722. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK
186723. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
186724. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK
186725. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
186726. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK
186727. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
186728. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK
186729. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
186730. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK
186731. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
186732. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK
186733. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
186734. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK
186735. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
186736. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK
186737. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
186738. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK
186739. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
186740. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK
186741. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
186742. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK
186743. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
186744. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK
186745. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
186746. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK
186747. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
186748. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK
186749. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
186750. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK
186751. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
186752. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK
186753. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
186754. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK
186755. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
186756. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK
186757. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
186758. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK
186759. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
186760. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK
186761. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
186762. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK
186763. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
186764. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK
186765. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
186766. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK
186767. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
186768. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK
186769. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
186770. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK
186771. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
186772. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK
186773. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
186774. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK
186775. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
186776. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK
186777. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
186778. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK
186779. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
186780. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK
186781. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
186782. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK
186783. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
186784. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK
186785. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
186786. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK
186787. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
186788. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK
186789. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
186790. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK
186791. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
186792. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK
186793. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
186794. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK
186795. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
186796. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK
186797. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
186798. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK
186799. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
186800. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK
186801. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
186802. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK
186803. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
186804. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK
186805. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
186806. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK
186807. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
186808. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK
186809. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
186810. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK
186811. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
186812. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK
186813. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
186814. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK
186815. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
186816. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK
186817. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
186818. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK
186819. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
186820. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK
186821. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
186822. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK
186823. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
186824. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK
186825. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
186826. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK
186827. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
186828. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK
186829. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
186830. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK
186831. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
186832. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK
186833. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
186834. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK
186835. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
186836. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK
186837. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
186838. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK
186839. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
186840. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK
186841. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
186842. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK
186843. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
186844. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK
186845. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
186846. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK
186847. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
186848. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK
186849. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
186850. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK
186851. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
186852. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK
186853. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
186854. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK
186855. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
186856. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK
186857. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
186858. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK
186859. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
186860. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK
186861. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
186862. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK
186863. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
186864. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK
186865. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
186866. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK
186867. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
186868. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK
186869. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
186870. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK
186871. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
186872. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK
186873. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
186874. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK
186875. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
186876. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK
186877. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
186878. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK
186879. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
186880. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK
186881. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
186882. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK
186883. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
186884. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK
186885. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
186886. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK
186887. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
186888. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK
186889. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
186890. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK
186891. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
186892. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK
186893. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
186894. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK
186895. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
186896. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK
186897. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
186898. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK
186899. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
186900. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK
186901. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
186902. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK
186903. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
186904. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK
186905. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
186906. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK
186907. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
186908. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK
186909. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
186910. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK
186911. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
186912. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK
186913. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
186914. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK
186915. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
186916. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK
186917. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
186918. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK
186919. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
186920. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK
186921. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
186922. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK
186923. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
186924. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK
186925. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
186926. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK
186927. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
186928. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK
186929. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
186930. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK
186931. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
186932. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK
186933. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
186934. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK
186935. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
186936. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK
186937. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
186938. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK
186939. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
186940. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK
186941. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
186942. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK
186943. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
186944. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK
186945. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
186946. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK
186947. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
186948. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK
186949. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
186950. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK
186951. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
186952. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK
186953. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
186954. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK
186955. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
186956. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK
186957. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
186958. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK
186959. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
186960. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK
186961. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
186962. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK
186963. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
186964. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK
186965. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
186966. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK
186967. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
186968. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK
186969. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
186970. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK
186971. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
186972. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK
186973. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
186974. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK
186975. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
186976. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK
186977. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
186978. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK
186979. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
186980. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK
186981. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
186982. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK
186983. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
186984. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK
186985. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
186986. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK
186987. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
186988. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK
186989. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
186990. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK
186991. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
186992. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK
186993. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
186994. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK
186995. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
186996. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK
186997. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
186998. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK
186999. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
187000. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK
187001. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
187002. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK
187003. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
187004. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK
187005. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
187006. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK
187007. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
187008. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK
187009. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
187010. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK
187011. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
187012. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK
187013. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
187014. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK
187015. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
187016. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK
187017. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
187018. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK
187019. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
187020. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK
187021. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
187022. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK
187023. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
187024. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK
187025. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
187026. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK
187027. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
187028. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK
187029. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
187030. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK
187031. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
187032. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK
187033. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
187034. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK
187035. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
187036. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK
187037. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
187038. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK
187039. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
187040. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK
187041. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
187042. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK
187043. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
187044. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK
187045. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
187046. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK
187047. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
187048. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK
187049. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
187050. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK
187051. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
187052. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK
187053. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
187054. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK
187055. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
187056. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK
187057. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
187058. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK
187059. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
187060. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK
187061. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
187062. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK
187063. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
187064. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK
187065. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
187066. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK
187067. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
187068. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK
187069. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
187070. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK
187071. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
187072. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK
187073. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
187074. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK
187075. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
187076. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK
187077. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
187078. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK
187079. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
187080. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK
187081. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
187082. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK
187083. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
187084. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK
187085. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
187086. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK
187087. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
187088. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK
187089. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
187090. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK
187091. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
187092. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK
187093. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
187094. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK
187095. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
187096. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK
187097. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
187098. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK
187099. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
187100. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK
187101. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
187102. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK
187103. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
187104. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK
187105. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
187106. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK
187107. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
187108. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK
187109. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
187110. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK
187111. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
187112. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK
187113. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
187114. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK
187115. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
187116. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK
187117. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
187118. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK
187119. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
187120. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK
187121. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
187122. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK
187123. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
187124. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK
187125. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
187126. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK
187127. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
187128. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK
187129. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
187130. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK
187131. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
187132. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK
187133. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
187134. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK
187135. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
187136. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK
187137. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
187138. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK
187139. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
187140. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK
187141. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
187142. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK
187143. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
187144. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK
187145. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
187146. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK
187147. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
187148. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK
187149. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
187150. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK
187151. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
187152. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK
187153. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
187154. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK
187155. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
187156. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK
187157. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
187158. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK
187159. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
187160. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK
187161. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
187162. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK
187163. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
187164. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK
187165. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
187166. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK
187167. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
187168. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK
187169. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
187170. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK
187171. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
187172. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK
187173. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
187174. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK
187175. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
187176. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK
187177. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
187178. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK
187179. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
187180. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK
187181. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
187182. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK
187183. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
187184. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK
187185. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
187186. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK
187187. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
187188. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK
187189. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
187190. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK
187191. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
187192. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK
187193. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
187194. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK
187195. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
187196. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK
187197. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
187198. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK
187199. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
187200. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK
187201. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
187202. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK
187203. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
187204. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK
187205. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
187206. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK
187207. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
187208. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK
187209. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
187210. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK
187211. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
187212. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK
187213. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
187214. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK
187215. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
187216. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK
187217. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
187218. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK
187219. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
187220. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK
187221. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
187222. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK
187223. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
187224. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK
187225. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
187226. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK
187227. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
187228. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK
187229. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
187230. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK
187231. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
187232. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK
187233. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
187234. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK
187235. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
187236. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK
187237. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
187238. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK
187239. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
187240. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK
187241. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
187242. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK
187243. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
187244. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK
187245. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
187246. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK
187247. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
187248. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK
187249. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
187250. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK
187251. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
187252. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK
187253. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
187254. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK
187255. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
187256. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK
187257. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
187258. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK
187259. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
187260. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK
187261. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
187262. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK
187263. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
187264. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK
187265. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
187266. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK
187267. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
187268. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK
187269. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
187270. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK
187271. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
187272. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK
187273. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
187274. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK
187275. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
187276. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK
187277. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
187278. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK
187279. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
187280. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK
187281. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
187282. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK
187283. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
187284. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK
187285. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
187286. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK
187287. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
187288. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK
187289. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
187290. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK
187291. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
187292. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK
187293. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
187294. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK
187295. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
187296. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK
187297. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
187298. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK
187299. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
187300. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK
187301. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
187302. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK
187303. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
187304. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK
187305. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
187306. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK
187307. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
187308. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK
187309. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
187310. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK
187311. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
187312. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK
187313. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
187314. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK
187315. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
187316. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK
187317. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
187318. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK
187319. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
187320. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK
187321. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
187322. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK
187323. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
187324. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK
187325. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
187326. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK
187327. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
187328. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK
187329. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
187330. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK
187331. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
187332. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK
187333. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
187334. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK
187335. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
187336. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK
187337. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
187338. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK
187339. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
187340. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK
187341. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
187342. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK
187343. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
187344. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK
187345. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
187346. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK
187347. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
187348. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK
187349. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
187350. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK
187351. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
187352. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK
187353. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
187354. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK
187355. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
187356. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK
187357. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
187358. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK
187359. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
187360. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK
187361. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
187362. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK
187363. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
187364. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK
187365. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
187366. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK
187367. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
187368. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK
187369. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
187370. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK
187371. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
187372. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK
187373. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
187374. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK
187375. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
187376. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK
187377. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
187378. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK
187379. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
187380. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK
187381. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
187382. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK
187383. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
187384. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK
187385. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
187386. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK
187387. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
187388. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK
187389. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
187390. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK
187391. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
187392. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK
187393. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
187394. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK
187395. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
187396. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK
187397. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
187398. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK
187399. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
187400. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK
187401. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
187402. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK
187403. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
187404. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK
187405. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
187406. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK
187407. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
187408. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK
187409. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
187410. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK
187411. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
187412. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK
187413. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
187414. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK
187415. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
187416. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK
187417. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
187418. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK
187419. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
187420. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK
187421. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
187422. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK
187423. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
187424. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK
187425. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
187426. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK
187427. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
187428. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK
187429. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
187430. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK
187431. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
187432. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK
187433. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
187434. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK
187435. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
187436. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK
187437. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
187438. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK
187439. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
187440. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK
187441. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
187442. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK
187443. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
187444. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK
187445. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
187446. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK
187447. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
187448. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK
187449. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
187450. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK
187451. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
187452. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK
187453. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
187454. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK
187455. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
187456. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK
187457. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
187458. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK
187459. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
187460. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK
187461. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
187462. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK
187463. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
187464. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK
187465. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
187466. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK
187467. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
187468. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK
187469. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
187470. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK
187471. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
187472. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK
187473. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
187474. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK
187475. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
187476. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK
187477. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
187478. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK
187479. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
187480. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK
187481. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
187482. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK
187483. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
187484. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK
187485. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
187486. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK
187487. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
187488. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK
187489. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
187490. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK
187491. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
187492. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK
187493. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
187494. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK
187495. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
187496. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK
187497. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
187498. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK
187499. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
187500. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK
187501. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
187502. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK
187503. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
187504. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK
187505. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
187506. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK
187507. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
187508. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK
187509. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
187510. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK
187511. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
187512. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK
187513. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
187514. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK
187515. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
187516. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK
187517. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
187518. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK
187519. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
187520. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK
187521. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
187522. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK
187523. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
187524. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK
187525. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
187526. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK
187527. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
187528. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK
187529. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
187530. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK
187531. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
187532. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK
187533. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
187534. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK
187535. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
187536. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK
187537. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
187538. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK
187539. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
187540. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK
187541. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
187542. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK
187543. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
187544. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK
187545. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
187546. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK
187547. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
187548. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK
187549. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
187550. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK
187551. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
187552. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK
187553. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
187554. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK
187555. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
187556. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK
187557. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
187558. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK
187559. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
187560. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK
187561. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
187562. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK
187563. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
187564. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK
187565. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
187566. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK
187567. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
187568. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK
187569. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
187570. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK
187571. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
187572. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK
187573. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
187574. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK
187575. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
187576. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK
187577. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
187578. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK
187579. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
187580. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK
187581. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
187582. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK
187583. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
187584. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK
187585. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
187586. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK
187587. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
187588. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK
187589. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
187590. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK
187591. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
187592. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK
187593. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
187594. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK
187595. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
187596. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK
187597. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
187598. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK
187599. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
187600. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK
187601. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
187602. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK
187603. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
187604. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK
187605. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
187606. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK
187607. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
187608. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK
187609. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
187610. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK
187611. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
187612. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK
187613. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
187614. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK
187615. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
187616. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK
187617. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
187618. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK
187619. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
187620. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK
187621. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
187622. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK
187623. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
187624. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK
187625. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
187626. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK
187627. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
187628. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK
187629. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
187630. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK
187631. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
187632. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK
187633. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
187634. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK
187635. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
187636. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK
187637. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
187638. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK
187639. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
187640. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK
187641. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
187642. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK
187643. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
187644. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK
187645. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
187646. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK
187647. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
187648. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK
187649. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
187650. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK
187651. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
187652. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK
187653. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
187654. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK
187655. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
187656. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK
187657. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
187658. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK
187659. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
187660. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK
187661. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
187662. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK
187663. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
187664. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK
187665. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
187666. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK
187667. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
187668. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK
187669. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
187670. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK
187671. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
187672. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK
187673. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
187674. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK
187675. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
187676. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK
187677. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
187678. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK
187679. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
187680. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK
187681. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
187682. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK
187683. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
187684. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK
187685. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
187686. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK
187687. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
187688. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK
187689. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
187690. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK
187691. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
187692. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK
187693. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
187694. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK
187695. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
187696. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK
187697. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
187698. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK
187699. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
187700. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK
187701. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
187702. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK
187703. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
187704. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK
187705. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
187706. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK
187707. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
187708. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK
187709. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
187710. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK
187711. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
187712. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK
187713. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
187714. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK
187715. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
187716. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK
187717. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
187718. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK
187719. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
187720. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK
187721. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
187722. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK
187723. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
187724. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK
187725. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
187726. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK
187727. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
187728. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK
187729. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
187730. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK
187731. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
187732. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK
187733. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
187734. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK
187735. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
187736. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK
187737. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
187738. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK
187739. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
187740. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK
187741. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
187742. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK
187743. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
187744. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK
187745. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
187746. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK
187747. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
187748. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK
187749. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
187750. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK
187751. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
187752. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK
187753. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
187754. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK
187755. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
187756. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK
187757. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
187758. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK
187759. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
187760. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK
187761. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
187762. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK
187763. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
187764. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK
187765. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
187766. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK
187767. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
187768. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK
187769. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
187770. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK
187771. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
187772. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK
187773. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
187774. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK
187775. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
187776. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK
187777. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
187778. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK
187779. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
187780. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK
187781. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
187782. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK
187783. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
187784. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK
187785. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
187786. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK
187787. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
187788. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK
187789. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
187790. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK
187791. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
187792. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK
187793. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
187794. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK
187795. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
187796. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK
187797. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
187798. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK
187799. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
187800. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK
187801. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
187802. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK
187803. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
187804. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK
187805. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
187806. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK
187807. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
187808. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK
187809. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
187810. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK
187811. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
187812. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK
187813. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
187814. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK
187815. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
187816. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK
187817. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
187818. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK
187819. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
187820. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK
187821. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
187822. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK
187823. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
187824. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK
187825. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
187826. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK
187827. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
187828. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK
187829. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
187830. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK
187831. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
187832. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK
187833. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
187834. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK
187835. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
187836. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK
187837. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
187838. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK
187839. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
187840. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK
187841. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
187842. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK
187843. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
187844. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK
187845. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
187846. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK
187847. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
187848. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK
187849. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
187850. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK
187851. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
187852. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK
187853. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
187854. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK
187855. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
187856. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK
187857. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
187858. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK
187859. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
187860. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK
187861. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
187862. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK
187863. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
187864. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK
187865. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
187866. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK
187867. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
187868. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK
187869. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
187870. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK
187871. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
187872. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK
187873. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
187874. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK
187875. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
187876. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK
187877. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
187878. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK
187879. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
187880. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK
187881. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
187882. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK
187883. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
187884. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK
187885. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
187886. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK
187887. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
187888. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK
187889. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
187890. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK
187891. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
187892. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK
187893. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
187894. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK
187895. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
187896. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK
187897. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
187898. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK
187899. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
187900. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK
187901. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
187902. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK
187903. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
187904. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK
187905. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
187906. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK
187907. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
187908. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK
187909. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
187910. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK
187911. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
187912. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK
187913. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
187914. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK
187915. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
187916. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK
187917. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
187918. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK
187919. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
187920. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK
187921. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
187922. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK
187923. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
187924. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK
187925. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
187926. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK
187927. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
187928. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK
187929. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
187930. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK
187931. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
187932. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK
187933. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
187934. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK
187935. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
187936. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK
187937. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
187938. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK
187939. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
187940. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK
187941. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
187942. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK
187943. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
187944. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK
187945. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
187946. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK
187947. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
187948. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK
187949. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
187950. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK
187951. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
187952. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK
187953. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
187954. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK
187955. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
187956. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK
187957. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
187958. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK
187959. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
187960. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK
187961. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
187962. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK
187963. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
187964. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK
187965. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
187966. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK
187967. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
187968. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK
187969. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
187970. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK
187971. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
187972. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK
187973. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
187974. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK
187975. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
187976. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK
187977. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
187978. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK
187979. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
187980. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK
187981. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
187982. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK
187983. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
187984. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK
187985. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
187986. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK
187987. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
187988. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK
187989. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
187990. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK
187991. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
187992. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK
187993. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
187994. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK
187995. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
187996. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK
187997. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
187998. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK
187999. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
188000. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK
188001. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
188002. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK
188003. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
188004. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK
188005. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
188006. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK
188007. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
188008. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK
188009. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
188010. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK
188011. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
188012. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK
188013. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
188014. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK
188015. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
188016. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK
188017. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
188018. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK
188019. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
188020. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK
188021. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
188022. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK
188023. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
188024. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK
188025. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
188026. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK
188027. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
188028. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK
188029. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
188030. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK
188031. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
188032. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK
188033. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
188034. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK
188035. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
188036. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK
188037. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
188038. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK
188039. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
188040. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK
188041. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
188042. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK
188043. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
188044. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK
188045. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
188046. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK
188047. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
188048. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK
188049. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
188050. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK
188051. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
188052. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK
188053. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
188054. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK
188055. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
188056. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK
188057. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
188058. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK
188059. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
188060. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK
188061. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
188062. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK
188063. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
188064. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK
188065. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
188066. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK
188067. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
188068. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK
188069. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
188070. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK
188071. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
188072. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK
188073. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
188074. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK
188075. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
188076. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK
188077. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
188078. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK
188079. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
188080. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK
188081. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
188082. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK
188083. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
188084. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK
188085. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
188086. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK
188087. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
188088. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK
188089. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
188090. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK
188091. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
188092. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK
188093. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
188094. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK
188095. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
188096. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK
188097. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
188098. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK
188099. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
188100. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK
188101. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
188102. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK
188103. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
188104. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK
188105. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
188106. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK
188107. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
188108. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK
188109. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
188110. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK
188111. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
188112. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK
188113. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
188114. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK
188115. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
188116. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK
188117. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
188118. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK
188119. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
188120. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK
188121. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
188122. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK
188123. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
188124. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK
188125. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
188126. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK
188127. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
188128. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK
188129. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
188130. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK
188131. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
188132. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK
188133. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
188134. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK
188135. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
188136. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK
188137. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
188138. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK
188139. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
188140. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK
188141. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
188142. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK
188143. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
188144. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK
188145. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
188146. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK
188147. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
188148. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK
188149. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
188150. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK
188151. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
188152. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK
188153. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
188154. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK
188155. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
188156. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK
188157. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
188158. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK
188159. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
188160. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK
188161. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
188162. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK
188163. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
188164. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK
188165. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
188166. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK
188167. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
188168. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK
188169. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
188170. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK
188171. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
188172. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK
188173. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
188174. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK
188175. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
188176. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK
188177. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
188178. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK
188179. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
188180. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK
188181. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
188182. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK
188183. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
188184. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK
188185. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
188186. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK
188187. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
188188. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK
188189. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
188190. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK
188191. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
188192. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK
188193. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
188194. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK
188195. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
188196. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK
188197. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
188198. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK
188199. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
188200. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK
188201. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
188202. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK
188203. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
188204. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK
188205. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
188206. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK
188207. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
188208. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK
188209. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
188210. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK
188211. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
188212. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK
188213. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
188214. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK
188215. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
188216. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK
188217. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
188218. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK
188219. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
188220. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK
188221. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
188222. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK
188223. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
188224. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK
188225. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
188226. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK
188227. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
188228. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK
188229. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
188230. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK
188231. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
188232. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK
188233. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
188234. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK
188235. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
188236. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK
188237. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
188238. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK
188239. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
188240. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK
188241. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
188242. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK
188243. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
188244. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK
188245. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
188246. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK
188247. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
188248. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK
188249. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
188250. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK
188251. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
188252. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK
188253. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
188254. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK
188255. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
188256. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK
188257. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
188258. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK
188259. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
188260. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK
188261. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
188262. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK
188263. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
188264. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK
188265. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
188266. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK
188267. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
188268. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK
188269. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
188270. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK
188271. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
188272. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK
188273. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
188274. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK
188275. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
188276. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK
188277. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
188278. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK
188279. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
188280. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK
188281. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
188282. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK
188283. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
188284. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK
188285. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
188286. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK
188287. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
188288. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK
188289. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
188290. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK
188291. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
188292. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK
188293. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
188294. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK
188295. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
188296. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK
188297. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
188298. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK
188299. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
188300. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK
188301. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
188302. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK
188303. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
188304. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK
188305. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
188306. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK
188307. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
188308. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK
188309. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
188310. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK
188311. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
188312. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK
188313. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
188314. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK
188315. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
188316. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK
188317. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
188318. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK
188319. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
188320. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK
188321. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
188322. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK
188323. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
188324. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK
188325. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
188326. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK
188327. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
188328. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK
188329. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
188330. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK
188331. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
188332. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK
188333. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
188334. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK
188335. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
188336. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK
188337. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
188338. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK
188339. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
188340. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK
188341. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
188342. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK
188343. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
188344. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK
188345. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
188346. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK
188347. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
188348. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK
188349. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
188350. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK
188351. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
188352. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK
188353. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
188354. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK
188355. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
188356. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK
188357. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
188358. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK
188359. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
188360. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK
188361. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
188362. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK
188363. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
188364. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK
188365. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
188366. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK
188367. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
188368. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK
188369. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
188370. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK
188371. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
188372. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK
188373. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
188374. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK
188375. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
188376. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK
188377. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
188378. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK
188379. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
188380. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK
188381. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
188382. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK
188383. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
188384. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK
188385. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
188386. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK
188387. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
188388. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK
188389. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
188390. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK
188391. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
188392. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK
188393. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
188394. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK
188395. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
188396. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK
188397. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
188398. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK
188399. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
188400. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK
188401. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
188402. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK
188403. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
188404. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK
188405. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
188406. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK
188407. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
188408. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK
188409. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
188410. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK
188411. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
188412. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK
188413. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
188414. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK
188415. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
188416. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK
188417. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
188418. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK
188419. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
188420. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK
188421. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
188422. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK
188423. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
188424. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK
188425. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
188426. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK
188427. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
188428. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK
188429. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
188430. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK
188431. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
188432. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK
188433. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
188434. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK
188435. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
188436. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK
188437. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
188438. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK
188439. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
188440. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK
188441. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
188442. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK
188443. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
188444. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK
188445. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
188446. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK
188447. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
188448. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK
188449. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
188450. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK
188451. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
188452. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK
188453. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
188454. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK
188455. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
188456. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK
188457. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
188458. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK
188459. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
188460. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK
188461. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
188462. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK
188463. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
188464. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK
188465. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
188466. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK
188467. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
188468. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK
188469. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
188470. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK
188471. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
188472. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK
188473. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
188474. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK
188475. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
188476. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK
188477. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
188478. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK
188479. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
188480. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK
188481. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
188482. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK
188483. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
188484. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK
188485. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
188486. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK
188487. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
188488. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK
188489. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
188490. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK
188491. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
188492. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK
188493. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
188494. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK
188495. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
188496. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK
188497. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
188498. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK
188499. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
188500. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK
188501. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
188502. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK
188503. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
188504. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK
188505. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
188506. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK
188507. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
188508. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK
188509. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
188510. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK
188511. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
188512. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK
188513. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
188514. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK
188515. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
188516. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK
188517. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
188518. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK
188519. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
188520. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK
188521. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
188522. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK
188523. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
188524. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK
188525. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
188526. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK
188527. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
188528. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK
188529. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
188530. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK
188531. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
188532. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK
188533. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
188534. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK
188535. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
188536. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK
188537. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
188538. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK
188539. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
188540. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK
188541. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
188542. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK
188543. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
188544. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK
188545. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
188546. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK
188547. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
188548. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK
188549. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
188550. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK
188551. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
188552. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK
188553. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
188554. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK
188555. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
188556. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK
188557. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
188558. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK
188559. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
188560. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK
188561. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
188562. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK
188563. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
188564. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK
188565. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
188566. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK
188567. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
188568. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK
188569. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
188570. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK
188571. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
188572. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK
188573. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
188574. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK
188575. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
188576. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK
188577. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
188578. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK
188579. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
188580. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK
188581. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
188582. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK
188583. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
188584. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK
188585. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
188586. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK
188587. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
188588. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK
188589. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
188590. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK
188591. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
188592. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK
188593. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
188594. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK
188595. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
188596. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK
188597. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
188598. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK
188599. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
188600. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK
188601. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
188602. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK
188603. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
188604. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK
188605. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
188606. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK
188607. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
188608. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK
188609. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
188610. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK
188611. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
188612. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK
188613. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
188614. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK
188615. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
188616. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK
188617. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
188618. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK
188619. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
188620. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK
188621. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
188622. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK
188623. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
188624. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK
188625. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
188626. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK
188627. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
188628. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK
188629. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
188630. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK
188631. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
188632. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK
188633. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
188634. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK
188635. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
188636. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK
188637. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
188638. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK
188639. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
188640. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK
188641. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
188642. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK
188643. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
188644. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK
188645. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
188646. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK
188647. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
188648. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK
188649. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
188650. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK
188651. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
188652. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK
188653. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
188654. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK
188655. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
188656. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK
188657. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
188658. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK
188659. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
188660. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK
188661. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
188662. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK
188663. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
188664. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
188665. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
188666. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
188667. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
188668. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
188669. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
188670. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
188671. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
188672. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
188673. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
188674. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
188675. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
188676. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
188677. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
188678. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
188679. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
188680. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
188681. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
188682. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
188683. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
188684. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
188685. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
188686. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
188687. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
188688. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
188689. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
188690. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
188691. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
188692. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
188693. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
188694. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
188695. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
188696. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
188697. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
188698. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
188699. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
188700. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
188701. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
188702. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
188703. DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
188704. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK
188705. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT
188706. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK
188707. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT
188708. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK
188709. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT
188710. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK
188711. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT
188712. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK
188713. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT
188714. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK
188715. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT
188716. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK
188717. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT
188718. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK
188719. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT
188720. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
188721. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
188722. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
188723. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
188724. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
188725. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
188726. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
188727. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
188728. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
188729. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
188730. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
188731. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
188732. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
188733. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
188734. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
188735. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
188736. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
188737. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
188738. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
188739. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
188740. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
188741. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
188742. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
188743. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
188744. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
188745. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
188746. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
188747. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
188748. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
188749. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
188750. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
188751. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
188752. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
188753. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
188754. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
188755. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
188756. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
188757. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
188758. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
188759. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
188760. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
188761. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
188762. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
188763. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
188764. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
188765. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
188766. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
188767. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
188768. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
188769. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
188770. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
188771. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
188772. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
188773. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
188774. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
188775. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
188776. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
188777. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
188778. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
188779. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
188780. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
188781. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
188782. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
188783. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
188784. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
188785. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
188786. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
188787. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
188788. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
188789. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
188790. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
188791. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
188792. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
188793. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
188794. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
188795. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
188796. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
188797. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
188798. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
188799. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
188800. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
188801. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
188802. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
188803. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
188804. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
188805. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
188806. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
188807. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
188808. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
188809. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
188810. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
188811. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
188812. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
188813. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
188814. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
188815. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
188816. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
188817. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
188818. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
188819. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
188820. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
188821. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
188822. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
188823. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
188824. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
188825. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
188826. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
188827. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
188828. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
188829. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
188830. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
188831. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
188832. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
188833. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
188834. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
188835. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
188836. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
188837. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
188838. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
188839. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
188840. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
188841. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
188842. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
188843. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
188844. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
188845. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
188846. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
188847. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
188848. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
188849. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
188850. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
188851. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
188852. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
188853. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
188854. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
188855. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
188856. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
188857. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
188858. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
188859. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
188860. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
188861. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
188862. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
188863. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
188864. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
188865. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
188866. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
188867. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
188868. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
188869. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
188870. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
188871. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
188872. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
188873. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
188874. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
188875. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
188876. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
188877. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
188878. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
188879. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
188880. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
188881. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
188882. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
188883. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
188884. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
188885. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
188886. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
188887. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
188888. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
188889. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
188890. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
188891. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
188892. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
188893. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
188894. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
188895. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
188896. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
188897. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
188898. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
188899. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
188900. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
188901. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
188902. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
188903. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
188904. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
188905. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
188906. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
188907. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
188908. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
188909. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
188910. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
188911. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
188912. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
188913. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
188914. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
188915. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
188916. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
188917. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
188918. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
188919. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
188920. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
188921. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
188922. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
188923. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
188924. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
188925. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
188926. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
188927. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
188928. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
188929. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
188930. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
188931. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
188932. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
188933. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
188934. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
188935. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
188936. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
188937. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
188938. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
188939. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
188940. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
188941. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
188942. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
188943. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
188944. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
188945. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
188946. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
188947. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
188948. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
188949. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
188950. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
188951. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
188952. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
188953. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
188954. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
188955. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
188956. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
188957. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
188958. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
188959. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
188960. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
188961. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
188962. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK
188963. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
188964. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
188965. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
188966. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
188967. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
188968. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
188969. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
188970. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
188971. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
188972. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
188973. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
188974. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
188975. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
188976. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
188977. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
188978. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
188979. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
188980. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
188981. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
188982. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
188983. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
188984. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
188985. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
188986. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
188987. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
188988. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
188989. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
188990. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK
188991. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
188992. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
188993. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
188994. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
188995. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
188996. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK
188997. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT
188998. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
188999. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
189000. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
189001. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
189002. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
189003. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
189004. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
189005. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
189006. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
189007. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
189008. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
189009. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
189010. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
189011. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
189012. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
189013. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
189014. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
189015. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
189016. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
189017. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
189018. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
189019. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
189020. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
189021. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
189022. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
189023. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
189024. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
189025. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
189026. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
189027. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
189028. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
189029. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
189030. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
189031. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
189032. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
189033. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
189034. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
189035. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
189036. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
189037. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
189038. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
189039. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
189040. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
189041. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
189042. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
189043. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
189044. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
189045. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
189046. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
189047. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
189048. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
189049. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
189050. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
189051. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
189052. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
189053. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
189054. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
189055. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
189056. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
189057. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
189058. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
189059. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
189060. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
189061. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
189062. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
189063. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
189064. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
189065. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
189066. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
189067. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
189068. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
189069. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
189070. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
189071. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
189072. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
189073. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
189074. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
189075. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
189076. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
189077. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
189078. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
189079. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
189080. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
189081. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
189082. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
189083. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
189084. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
189085. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
189086. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
189087. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
189088. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
189089. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
189090. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
189091. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
189092. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
189093. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
189094. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
189095. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
189096. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
189097. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
189098. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
189099. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
189100. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
189101. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
189102. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
189103. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
189104. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
189105. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
189106. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
189107. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
189108. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
189109. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
189110. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
189111. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
189112. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
189113. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
189114. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
189115. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
189116. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
189117. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
189118. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
189119. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
189120. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
189121. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
189122. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
189123. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
189124. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
189125. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
189126. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
189127. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
189128. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
189129. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
189130. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
189131. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
189132. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
189133. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
189134. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
189135. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
189136. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
189137. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
189138. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
189139. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
189140. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
189141. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
189142. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
189143. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
189144. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
189145. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
189146. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
189147. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
189148. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
189149. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
189150. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
189151. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
189152. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
189153. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
189154. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
189155. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
189156. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
189157. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
189158. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
189159. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
189160. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
189161. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
189162. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
189163. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
189164. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
189165. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
189166. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
189167. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
189168. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
189169. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
189170. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
189171. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
189172. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
189173. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
189174. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
189175. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
189176. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
189177. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
189178. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
189179. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
189180. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
189181. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
189182. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
189183. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
189184. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
189185. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
189186. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
189187. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
189188. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
189189. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
189190. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
189191. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
189192. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
189193. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
189194. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
189195. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
189196. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
189197. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
189198. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
189199. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
189200. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
189201. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
189202. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
189203. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
189204. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
189205. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
189206. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
189207. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
189208. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
189209. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
189210. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
189211. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
189212. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
189213. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
189214. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
189215. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
189216. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
189217. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
189218. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
189219. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
189220. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
189221. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
189222. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
189223. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
189224. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
189225. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
189226. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
189227. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
189228. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
189229. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
189230. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
189231. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
189232. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
189233. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
189234. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
189235. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
189236. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
189237. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
189238. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
189239. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
189240. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
189241. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
189242. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
189243. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
189244. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
189245. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
189246. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
189247. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
189248. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
189249. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
189250. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
189251. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
189252. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
189253. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
189254. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
189255. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
189256. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
189257. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
189258. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
189259. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
189260. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
189261. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
189262. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
189263. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
189264. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
189265. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
189266. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
189267. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
189268. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
189269. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
189270. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
189271. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
189272. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
189273. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
189274. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
189275. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
189276. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
189277. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
189278. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
189279. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
189280. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
189281. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
189282. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
189283. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
189284. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
189285. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
189286. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
189287. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
189288. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
189289. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
189290. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
189291. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
189292. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
189293. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
189294. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
189295. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
189296. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
189297. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
189298. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
189299. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
189300. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
189301. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
189302. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
189303. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
189304. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
189305. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
189306. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
189307. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
189308. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
189309. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
189310. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
189311. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
189312. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
189313. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
189314. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
189315. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
189316. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
189317. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
189318. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
189319. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
189320. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
189321. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
189322. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
189323. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
189324. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
189325. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
189326. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
189327. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
189328. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
189329. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
189330. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
189331. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
189332. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
189333. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
189334. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
189335. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
189336. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
189337. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
189338. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
189339. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
189340. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
189341. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
189342. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
189343. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
189344. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
189345. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
189346. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
189347. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
189348. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
189349. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
189350. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
189351. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
189352. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
189353. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
189354. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
189355. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
189356. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
189357. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
189358. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
189359. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
189360. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
189361. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
189362. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
189363. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
189364. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
189365. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
189366. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
189367. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
189368. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
189369. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
189370. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
189371. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
189372. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
189373. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
189374. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
189375. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
189376. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
189377. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
189378. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
189379. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
189380. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
189381. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
189382. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
189383. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
189384. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK
189385. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT
189386. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK
189387. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT
189388. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK
189389. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT
189390. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK
189391. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT
189392. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK
189393. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT
189394. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK
189395. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT
189396. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK
189397. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT
189398. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK
189399. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT
189400. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
189401. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
189402. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
189403. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
189404. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
189405. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
189406. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
189407. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
189408. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
189409. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
189410. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
189411. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
189412. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
189413. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
189414. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
189415. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
189416. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
189417. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
189418. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
189419. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
189420. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
189421. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
189422. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
189423. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
189424. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
189425. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
189426. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
189427. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
189428. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
189429. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
189430. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
189431. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
189432. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
189433. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
189434. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
189435. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
189436. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
189437. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
189438. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
189439. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
189440. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
189441. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
189442. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
189443. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
189444. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
189445. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
189446. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
189447. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
189448. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
189449. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
189450. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
189451. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
189452. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
189453. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
189454. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
189455. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
189456. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
189457. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
189458. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
189459. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
189460. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
189461. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
189462. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
189463. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
189464. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
189465. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
189466. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
189467. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
189468. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
189469. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
189470. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
189471. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
189472. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
189473. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
189474. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
189475. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
189476. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
189477. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
189478. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
189479. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
189480. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
189481. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
189482. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
189483. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
189484. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
189485. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
189486. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
189487. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
189488. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
189489. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
189490. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
189491. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
189492. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
189493. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
189494. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
189495. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
189496. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
189497. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
189498. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
189499. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
189500. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
189501. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
189502. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
189503. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
189504. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
189505. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
189506. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
189507. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
189508. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
189509. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
189510. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
189511. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
189512. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
189513. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
189514. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
189515. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
189516. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
189517. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
189518. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
189519. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
189520. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
189521. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
189522. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
189523. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
189524. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
189525. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
189526. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
189527. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
189528. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
189529. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
189530. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
189531. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
189532. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
189533. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
189534. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
189535. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
189536. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
189537. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
189538. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
189539. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
189540. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
189541. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
189542. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
189543. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
189544. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
189545. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
189546. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
189547. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
189548. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
189549. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
189550. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
189551. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
189552. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
189553. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
189554. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
189555. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
189556. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
189557. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
189558. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
189559. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
189560. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
189561. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
189562. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
189563. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
189564. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
189565. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
189566. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
189567. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
189568. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
189569. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
189570. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
189571. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
189572. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
189573. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
189574. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
189575. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
189576. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
189577. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
189578. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
189579. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
189580. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
189581. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
189582. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
189583. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
189584. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
189585. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
189586. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
189587. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
189588. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
189589. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
189590. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
189591. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
189592. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
189593. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
189594. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
189595. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
189596. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
189597. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
189598. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
189599. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
189600. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
189601. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
189602. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
189603. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
189604. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
189605. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
189606. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
189607. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
189608. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
189609. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
189610. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
189611. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
189612. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
189613. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
189614. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
189615. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
189616. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
189617. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
189618. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
189619. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
189620. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
189621. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
189622. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
189623. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
189624. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
189625. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
189626. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
189627. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
189628. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
189629. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
189630. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
189631. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
189632. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
189633. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
189634. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
189635. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
189636. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
189637. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
189638. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
189639. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
189640. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
189641. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
189642. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK
189643. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
189644. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
189645. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
189646. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
189647. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
189648. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
189649. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
189650. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
189651. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
189652. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
189653. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
189654. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
189655. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
189656. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
189657. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
189658. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
189659. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
189660. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
189661. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
189662. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
189663. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
189664. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
189665. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
189666. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
189667. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
189668. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
189669. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
189670. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK
189671. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
189672. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
189673. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
189674. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
189675. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
189676. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK
189677. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT
189678. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
189679. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
189680. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
189681. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
189682. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
189683. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
189684. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
189685. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
189686. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
189687. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
189688. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
189689. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
189690. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
189691. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
189692. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
189693. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
189694. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
189695. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
189696. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
189697. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
189698. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
189699. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
189700. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
189701. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
189702. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
189703. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
189704. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
189705. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
189706. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
189707. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
189708. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
189709. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
189710. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
189711. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
189712. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
189713. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
189714. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
189715. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
189716. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
189717. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
189718. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
189719. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
189720. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
189721. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
189722. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
189723. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
189724. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
189725. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
189726. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
189727. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
189728. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
189729. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
189730. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
189731. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
189732. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
189733. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
189734. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
189735. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
189736. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
189737. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
189738. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
189739. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
189740. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
189741. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
189742. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
189743. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
189744. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
189745. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
189746. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
189747. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
189748. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
189749. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
189750. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
189751. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
189752. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
189753. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
189754. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
189755. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
189756. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
189757. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
189758. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
189759. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
189760. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
189761. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
189762. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
189763. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
189764. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
189765. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
189766. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
189767. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
189768. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
189769. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
189770. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
189771. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
189772. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
189773. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
189774. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
189775. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
189776. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
189777. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
189778. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
189779. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
189780. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
189781. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
189782. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
189783. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
189784. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
189785. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
189786. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
189787. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
189788. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
189789. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
189790. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
189791. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
189792. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
189793. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
189794. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
189795. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
189796. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
189797. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
189798. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
189799. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
189800. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
189801. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
189802. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
189803. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
189804. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
189805. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
189806. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
189807. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
189808. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
189809. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
189810. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
189811. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
189812. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
189813. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
189814. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
189815. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
189816. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
189817. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
189818. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
189819. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
189820. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
189821. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
189822. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
189823. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
189824. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
189825. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
189826. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
189827. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
189828. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
189829. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
189830. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
189831. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
189832. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
189833. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
189834. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
189835. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
189836. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
189837. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
189838. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
189839. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
189840. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
189841. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
189842. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
189843. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
189844. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
189845. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
189846. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
189847. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
189848. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
189849. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
189850. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
189851. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
189852. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
189853. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
189854. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
189855. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
189856. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
189857. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
189858. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
189859. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
189860. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
189861. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
189862. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
189863. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
189864. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
189865. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
189866. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
189867. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
189868. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
189869. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
189870. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
189871. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
189872. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
189873. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
189874. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
189875. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
189876. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
189877. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
189878. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
189879. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
189880. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
189881. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
189882. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
189883. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
189884. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
189885. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
189886. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
189887. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
189888. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
189889. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
189890. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
189891. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
189892. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
189893. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
189894. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
189895. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
189896. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
189897. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
189898. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
189899. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
189900. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
189901. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
189902. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
189903. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
189904. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
189905. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
189906. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
189907. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
189908. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
189909. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
189910. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
189911. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
189912. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
189913. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
189914. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
189915. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
189916. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
189917. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
189918. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
189919. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
189920. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
189921. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
189922. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
189923. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
189924. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
189925. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
189926. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
189927. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
189928. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
189929. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
189930. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
189931. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
189932. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
189933. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
189934. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
189935. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
189936. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
189937. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
189938. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
189939. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
189940. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
189941. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
189942. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
189943. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
189944. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
189945. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
189946. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
189947. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
189948. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
189949. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
189950. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
189951. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
189952. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
189953. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
189954. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
189955. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
189956. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
189957. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
189958. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
189959. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
189960. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
189961. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
189962. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
189963. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
189964. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
189965. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
189966. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
189967. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
189968. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
189969. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
189970. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
189971. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
189972. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
189973. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
189974. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
189975. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
189976. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
189977. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
189978. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
189979. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
189980. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
189981. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
189982. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
189983. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
189984. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
189985. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
189986. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
189987. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
189988. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
189989. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
189990. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
189991. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
189992. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
189993. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
189994. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
189995. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
189996. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
189997. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
189998. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
189999. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
190000. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
190001. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
190002. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
190003. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
190004. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
190005. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
190006. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
190007. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
190008. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
190009. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
190010. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
190011. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
190012. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
190013. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
190014. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
190015. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
190016. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
190017. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
190018. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
190019. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
190020. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
190021. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
190022. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
190023. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
190024. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
190025. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
190026. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
190027. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
190028. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
190029. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
190030. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
190031. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
190032. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
190033. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
190034. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
190035. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
190036. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
190037. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
190038. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
190039. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
190040. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
190041. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
190042. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
190043. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
190044. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
190045. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
190046. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
190047. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
190048. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
190049. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
190050. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
190051. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
190052. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
190053. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
190054. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
190055. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
190056. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
190057. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
190058. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
190059. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
190060. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
190061. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
190062. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
190063. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
190064. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK
190065. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT
190066. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK
190067. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT
190068. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK
190069. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT
190070. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK
190071. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT
190072. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK
190073. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT
190074. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK
190075. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT
190076. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK
190077. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT
190078. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK
190079. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT
190080. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
190081. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
190082. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
190083. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
190084. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
190085. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
190086. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
190087. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
190088. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
190089. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
190090. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
190091. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
190092. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
190093. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
190094. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
190095. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
190096. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
190097. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
190098. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
190099. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
190100. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
190101. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
190102. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
190103. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
190104. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
190105. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
190106. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
190107. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190108. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
190109. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
190110. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
190111. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
190112. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
190113. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
190114. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
190115. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190116. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
190117. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
190118. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
190119. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
190120. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
190121. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
190122. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
190123. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
190124. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
190125. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
190126. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
190127. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190128. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
190129. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
190130. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
190131. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
190132. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
190133. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
190134. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
190135. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190136. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
190137. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
190138. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
190139. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
190140. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
190141. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
190142. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
190143. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
190144. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
190145. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
190146. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
190147. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
190148. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
190149. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
190150. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
190151. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
190152. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
190153. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
190154. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
190155. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
190156. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
190157. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
190158. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
190159. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
190160. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
190161. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
190162. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
190163. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
190164. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
190165. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
190166. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
190167. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
190168. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
190169. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
190170. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
190171. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
190172. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
190173. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
190174. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
190175. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
190176. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
190177. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
190178. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
190179. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
190180. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
190181. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
190182. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
190183. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
190184. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
190185. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
190186. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
190187. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
190188. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
190189. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
190190. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
190191. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
190192. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
190193. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
190194. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
190195. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
190196. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
190197. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
190198. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
190199. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
190200. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
190201. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
190202. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
190203. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
190204. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
190205. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
190206. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
190207. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
190208. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
190209. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
190210. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
190211. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
190212. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
190213. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
190214. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
190215. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
190216. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
190217. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
190218. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
190219. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
190220. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
190221. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
190222. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
190223. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
190224. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
190225. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
190226. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
190227. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
190228. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
190229. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
190230. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
190231. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
190232. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
190233. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
190234. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
190235. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
190236. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
190237. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
190238. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
190239. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
190240. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
190241. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
190242. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
190243. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
190244. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
190245. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
190246. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
190247. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
190248. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
190249. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
190250. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
190251. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
190252. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
190253. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
190254. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
190255. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
190256. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
190257. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
190258. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
190259. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
190260. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
190261. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
190262. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
190263. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
190264. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
190265. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
190266. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
190267. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
190268. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
190269. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
190270. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
190271. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
190272. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
190273. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
190274. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
190275. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
190276. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
190277. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
190278. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
190279. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
190280. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
190281. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
190282. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
190283. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
190284. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
190285. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
190286. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
190287. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
190288. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
190289. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
190290. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
190291. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
190292. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
190293. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
190294. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
190295. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
190296. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
190297. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
190298. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
190299. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
190300. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
190301. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
190302. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
190303. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
190304. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
190305. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
190306. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
190307. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
190308. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
190309. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
190310. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
190311. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
190312. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
190313. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
190314. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
190315. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
190316. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
190317. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
190318. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
190319. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
190320. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
190321. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
190322. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK
190323. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
190324. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
190325. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
190326. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
190327. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
190328. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
190329. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
190330. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
190331. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
190332. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
190333. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
190334. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
190335. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
190336. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
190337. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
190338. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
190339. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
190340. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
190341. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
190342. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
190343. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
190344. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
190345. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
190346. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
190347. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
190348. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
190349. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
190350. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK
190351. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
190352. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
190353. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
190354. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
190355. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
190356. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK
190357. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT
190358. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
190359. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
190360. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
190361. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
190362. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
190363. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
190364. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
190365. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
190366. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
190367. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
190368. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
190369. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
190370. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
190371. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
190372. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
190373. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
190374. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
190375. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
190376. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
190377. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
190378. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
190379. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
190380. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
190381. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
190382. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
190383. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
190384. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
190385. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
190386. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
190387. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
190388. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
190389. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
190390. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
190391. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
190392. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
190393. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
190394. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
190395. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
190396. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
190397. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
190398. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
190399. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
190400. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
190401. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
190402. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
190403. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
190404. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
190405. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
190406. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
190407. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
190408. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
190409. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
190410. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
190411. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
190412. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
190413. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
190414. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
190415. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
190416. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
190417. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
190418. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
190419. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
190420. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
190421. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
190422. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
190423. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
190424. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
190425. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
190426. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
190427. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
190428. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
190429. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
190430. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
190431. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
190432. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
190433. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
190434. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
190435. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
190436. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
190437. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
190438. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
190439. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
190440. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
190441. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
190442. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
190443. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
190444. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
190445. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
190446. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
190447. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
190448. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
190449. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
190450. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
190451. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
190452. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
190453. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
190454. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
190455. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
190456. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
190457. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
190458. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
190459. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
190460. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
190461. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
190462. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
190463. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
190464. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
190465. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
190466. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
190467. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
190468. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
190469. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
190470. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
190471. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
190472. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
190473. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
190474. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
190475. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
190476. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
190477. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
190478. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
190479. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
190480. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
190481. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
190482. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
190483. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
190484. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
190485. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
190486. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
190487. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
190488. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
190489. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
190490. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
190491. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
190492. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
190493. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
190494. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
190495. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
190496. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
190497. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
190498. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
190499. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
190500. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
190501. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
190502. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
190503. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
190504. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
190505. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
190506. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
190507. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
190508. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
190509. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
190510. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
190511. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
190512. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
190513. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
190514. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
190515. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
190516. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
190517. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
190518. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
190519. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
190520. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
190521. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
190522. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
190523. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
190524. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
190525. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
190526. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
190527. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
190528. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
190529. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
190530. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
190531. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
190532. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
190533. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
190534. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
190535. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
190536. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
190537. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
190538. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
190539. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
190540. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
190541. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
190542. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
190543. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
190544. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
190545. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
190546. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
190547. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
190548. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
190549. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
190550. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
190551. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
190552. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
190553. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
190554. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
190555. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
190556. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
190557. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
190558. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
190559. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
190560. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
190561. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
190562. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
190563. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
190564. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
190565. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
190566. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
190567. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
190568. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
190569. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
190570. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
190571. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
190572. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
190573. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
190574. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
190575. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
190576. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
190577. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
190578. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
190579. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
190580. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
190581. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
190582. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
190583. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
190584. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
190585. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
190586. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
190587. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
190588. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
190589. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
190590. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
190591. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
190592. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
190593. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
190594. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
190595. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
190596. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
190597. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
190598. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
190599. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
190600. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
190601. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
190602. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
190603. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
190604. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
190605. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
190606. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
190607. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
190608. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
190609. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
190610. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
190611. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
190612. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
190613. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
190614. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
190615. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
190616. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
190617. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
190618. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
190619. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
190620. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
190621. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
190622. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
190623. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
190624. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
190625. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
190626. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
190627. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
190628. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
190629. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
190630. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
190631. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
190632. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
190633. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
190634. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
190635. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
190636. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
190637. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
190638. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
190639. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
190640. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
190641. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
190642. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
190643. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
190644. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
190645. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
190646. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
190647. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
190648. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
190649. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
190650. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
190651. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
190652. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
190653. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
190654. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
190655. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
190656. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
190657. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
190658. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
190659. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
190660. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
190661. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
190662. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
190663. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
190664. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
190665. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
190666. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
190667. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
190668. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
190669. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
190670. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
190671. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
190672. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
190673. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
190674. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
190675. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
190676. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
190677. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
190678. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
190679. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
190680. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
190681. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
190682. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
190683. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
190684. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
190685. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
190686. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
190687. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
190688. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
190689. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
190690. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
190691. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
190692. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
190693. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
190694. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
190695. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
190696. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
190697. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
190698. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
190699. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
190700. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
190701. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
190702. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
190703. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
190704. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
190705. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
190706. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
190707. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
190708. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
190709. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
190710. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
190711. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
190712. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
190713. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
190714. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
190715. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
190716. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
190717. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
190718. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
190719. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
190720. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
190721. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
190722. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
190723. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
190724. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
190725. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
190726. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
190727. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
190728. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
190729. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
190730. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
190731. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
190732. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
190733. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
190734. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
190735. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
190736. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
190737. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
190738. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
190739. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
190740. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
190741. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
190742. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
190743. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
190744. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK
190745. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT
190746. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK
190747. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT
190748. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK
190749. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT
190750. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK
190751. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT
190752. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK
190753. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT
190754. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK
190755. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT
190756. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK
190757. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT
190758. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK
190759. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT
190760. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
190761. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
190762. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
190763. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
190764. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
190765. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
190766. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
190767. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
190768. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
190769. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
190770. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
190771. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
190772. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
190773. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
190774. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
190775. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
190776. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
190777. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
190778. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
190779. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
190780. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
190781. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
190782. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
190783. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
190784. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
190785. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
190786. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
190787. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190788. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
190789. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
190790. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
190791. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
190792. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
190793. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
190794. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
190795. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190796. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
190797. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
190798. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
190799. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
190800. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
190801. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
190802. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
190803. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
190804. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
190805. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
190806. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
190807. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190808. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
190809. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
190810. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
190811. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
190812. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
190813. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
190814. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
190815. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
190816. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
190817. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
190818. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
190819. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
190820. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
190821. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
190822. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
190823. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
190824. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
190825. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
190826. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
190827. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
190828. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
190829. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
190830. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
190831. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
190832. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
190833. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
190834. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
190835. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
190836. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
190837. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
190838. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
190839. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
190840. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
190841. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
190842. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
190843. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
190844. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
190845. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
190846. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
190847. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
190848. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
190849. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
190850. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
190851. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
190852. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
190853. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
190854. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
190855. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
190856. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
190857. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
190858. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
190859. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
190860. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
190861. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
190862. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
190863. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
190864. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
190865. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
190866. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
190867. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
190868. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
190869. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
190870. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
190871. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
190872. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
190873. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
190874. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
190875. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
190876. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
190877. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
190878. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
190879. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
190880. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
190881. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
190882. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
190883. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
190884. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
190885. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
190886. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
190887. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
190888. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
190889. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
190890. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
190891. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
190892. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
190893. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
190894. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
190895. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
190896. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
190897. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
190898. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
190899. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
190900. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
190901. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
190902. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
190903. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
190904. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
190905. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
190906. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
190907. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
190908. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
190909. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
190910. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
190911. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
190912. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
190913. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
190914. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
190915. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
190916. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
190917. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
190918. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
190919. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
190920. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
190921. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
190922. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
190923. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
190924. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
190925. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
190926. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
190927. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
190928. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
190929. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
190930. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
190931. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
190932. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
190933. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
190934. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
190935. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
190936. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
190937. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
190938. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
190939. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
190940. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
190941. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
190942. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
190943. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
190944. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
190945. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
190946. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
190947. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
190948. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
190949. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
190950. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
190951. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
190952. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
190953. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
190954. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
190955. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
190956. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
190957. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
190958. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
190959. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
190960. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
190961. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
190962. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
190963. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
190964. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
190965. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
190966. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
190967. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
190968. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
190969. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
190970. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
190971. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
190972. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
190973. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
190974. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
190975. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
190976. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
190977. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
190978. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
190979. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
190980. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
190981. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
190982. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
190983. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
190984. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
190985. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
190986. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
190987. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
190988. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
190989. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
190990. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
190991. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
190992. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
190993. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
190994. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
190995. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
190996. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
190997. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
190998. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
190999. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
191000. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
191001. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
191002. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK
191003. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
191004. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
191005. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
191006. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
191007. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
191008. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
191009. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
191010. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
191011. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
191012. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
191013. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
191014. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
191015. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
191016. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
191017. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
191018. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
191019. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
191020. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
191021. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
191022. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
191023. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
191024. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
191025. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
191026. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
191027. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
191028. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
191029. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
191030. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK
191031. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
191032. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
191033. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
191034. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
191035. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
191036. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK
191037. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT
191038. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
191039. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
191040. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
191041. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
191042. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
191043. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
191044. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
191045. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
191046. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
191047. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
191048. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
191049. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
191050. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
191051. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
191052. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
191053. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
191054. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
191055. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
191056. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
191057. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
191058. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
191059. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
191060. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
191061. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
191062. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
191063. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
191064. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
191065. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
191066. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
191067. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
191068. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
191069. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
191070. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
191071. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
191072. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
191073. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
191074. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
191075. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
191076. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
191077. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
191078. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
191079. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
191080. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
191081. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
191082. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
191083. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
191084. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
191085. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
191086. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
191087. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
191088. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
191089. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
191090. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
191091. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
191092. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
191093. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
191094. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
191095. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
191096. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
191097. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
191098. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
191099. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
191100. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
191101. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
191102. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
191103. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
191104. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
191105. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
191106. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
191107. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
191108. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
191109. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
191110. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
191111. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
191112. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
191113. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
191114. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
191115. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
191116. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
191117. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
191118. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
191119. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
191120. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
191121. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
191122. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
191123. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
191124. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
191125. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
191126. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
191127. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
191128. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
191129. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
191130. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
191131. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
191132. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
191133. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
191134. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
191135. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
191136. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
191137. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
191138. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
191139. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
191140. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
191141. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
191142. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
191143. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
191144. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
191145. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
191146. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
191147. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
191148. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
191149. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
191150. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
191151. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
191152. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
191153. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
191154. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
191155. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
191156. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
191157. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
191158. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
191159. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
191160. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
191161. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
191162. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
191163. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
191164. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
191165. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
191166. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
191167. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
191168. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
191169. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
191170. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
191171. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
191172. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
191173. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
191174. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
191175. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
191176. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
191177. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
191178. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
191179. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
191180. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
191181. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
191182. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
191183. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
191184. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
191185. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
191186. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
191187. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
191188. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
191189. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
191190. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
191191. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
191192. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
191193. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
191194. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
191195. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
191196. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
191197. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
191198. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
191199. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
191200. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
191201. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
191202. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
191203. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
191204. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
191205. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
191206. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
191207. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
191208. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
191209. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
191210. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
191211. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
191212. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
191213. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
191214. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
191215. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
191216. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
191217. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
191218. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
191219. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
191220. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
191221. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
191222. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
191223. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
191224. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
191225. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
191226. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
191227. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
191228. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
191229. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
191230. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
191231. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
191232. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
191233. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
191234. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
191235. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
191236. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
191237. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
191238. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
191239. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
191240. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
191241. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
191242. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
191243. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
191244. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
191245. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
191246. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
191247. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
191248. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
191249. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
191250. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
191251. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
191252. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
191253. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
191254. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
191255. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
191256. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
191257. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
191258. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
191259. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
191260. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
191261. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
191262. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
191263. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
191264. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
191265. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
191266. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
191267. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
191268. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
191269. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
191270. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
191271. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
191272. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
191273. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
191274. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
191275. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
191276. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
191277. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
191278. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
191279. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
191280. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
191281. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
191282. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
191283. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
191284. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
191285. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
191286. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
191287. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
191288. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
191289. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
191290. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
191291. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
191292. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
191293. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
191294. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
191295. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
191296. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
191297. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
191298. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
191299. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
191300. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
191301. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
191302. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
191303. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
191304. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
191305. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
191306. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
191307. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
191308. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
191309. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
191310. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
191311. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
191312. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
191313. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
191314. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
191315. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
191316. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
191317. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
191318. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
191319. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
191320. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
191321. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
191322. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
191323. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
191324. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
191325. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
191326. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
191327. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
191328. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
191329. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
191330. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
191331. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
191332. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
191333. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
191334. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
191335. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
191336. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
191337. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
191338. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
191339. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
191340. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
191341. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
191342. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
191343. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
191344. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
191345. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
191346. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
191347. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
191348. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
191349. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
191350. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
191351. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
191352. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
191353. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
191354. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
191355. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
191356. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
191357. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
191358. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
191359. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
191360. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
191361. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
191362. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
191363. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
191364. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
191365. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
191366. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
191367. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
191368. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
191369. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
191370. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
191371. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
191372. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
191373. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
191374. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
191375. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
191376. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
191377. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
191378. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
191379. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
191380. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
191381. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
191382. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
191383. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
191384. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
191385. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
191386. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
191387. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
191388. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
191389. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
191390. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
191391. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
191392. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
191393. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
191394. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
191395. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
191396. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
191397. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
191398. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
191399. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
191400. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
191401. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
191402. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
191403. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
191404. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
191405. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
191406. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
191407. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
191408. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
191409. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
191410. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
191411. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
191412. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
191413. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
191414. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
191415. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
191416. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
191417. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
191418. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
191419. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
191420. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
191421. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
191422. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
191423. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
191424. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK
191425. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT
191426. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK
191427. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT
191428. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK
191429. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT
191430. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK
191431. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT
191432. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK
191433. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT
191434. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK
191435. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT
191436. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK
191437. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT
191438. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK
191439. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT
191440. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
191441. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
191442. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
191443. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
191444. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
191445. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
191446. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
191447. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
191448. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
191449. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
191450. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
191451. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
191452. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
191453. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
191454. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
191455. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
191456. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
191457. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
191458. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
191459. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
191460. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
191461. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
191462. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
191463. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
191464. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
191465. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
191466. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
191467. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
191468. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
191469. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
191470. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
191471. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
191472. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
191473. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
191474. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
191475. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
191476. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
191477. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
191478. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
191479. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
191480. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
191481. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
191482. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
191483. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
191484. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
191485. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
191486. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
191487. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
191488. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
191489. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
191490. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
191491. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
191492. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
191493. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
191494. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
191495. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
191496. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
191497. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
191498. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
191499. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
191500. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
191501. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
191502. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
191503. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
191504. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
191505. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
191506. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
191507. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
191508. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
191509. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
191510. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
191511. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
191512. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
191513. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
191514. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
191515. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
191516. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
191517. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
191518. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
191519. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
191520. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
191521. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
191522. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
191523. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
191524. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
191525. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
191526. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
191527. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
191528. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
191529. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
191530. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
191531. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
191532. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
191533. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
191534. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
191535. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
191536. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
191537. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
191538. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
191539. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
191540. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
191541. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
191542. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
191543. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
191544. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
191545. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
191546. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
191547. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
191548. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
191549. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
191550. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
191551. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
191552. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
191553. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
191554. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
191555. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
191556. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
191557. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
191558. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
191559. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
191560. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
191561. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
191562. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
191563. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
191564. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
191565. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
191566. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
191567. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
191568. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
191569. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
191570. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
191571. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
191572. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
191573. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
191574. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
191575. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
191576. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
191577. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
191578. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
191579. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
191580. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
191581. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
191582. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
191583. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
191584. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
191585. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
191586. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
191587. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
191588. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
191589. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
191590. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
191591. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
191592. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
191593. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
191594. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
191595. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
191596. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
191597. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
191598. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
191599. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
191600. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
191601. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
191602. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
191603. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
191604. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
191605. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
191606. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
191607. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
191608. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
191609. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
191610. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
191611. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
191612. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
191613. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
191614. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
191615. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
191616. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
191617. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
191618. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
191619. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
191620. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
191621. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
191622. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
191623. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
191624. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
191625. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
191626. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
191627. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
191628. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
191629. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
191630. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
191631. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
191632. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
191633. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
191634. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
191635. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
191636. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
191637. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
191638. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
191639. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
191640. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
191641. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
191642. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
191643. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
191644. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
191645. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
191646. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
191647. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
191648. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
191649. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
191650. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
191651. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
191652. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
191653. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
191654. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
191655. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
191656. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
191657. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
191658. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
191659. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
191660. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
191661. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
191662. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
191663. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
191664. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
191665. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
191666. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
191667. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
191668. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
191669. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
191670. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
191671. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
191672. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
191673. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
191674. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
191675. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
191676. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
191677. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
191678. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
191679. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
191680. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
191681. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
191682. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK
191683. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
191684. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
191685. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
191686. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
191687. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
191688. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
191689. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
191690. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
191691. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
191692. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
191693. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
191694. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
191695. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
191696. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
191697. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
191698. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
191699. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
191700. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
191701. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
191702. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
191703. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
191704. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
191705. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
191706. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
191707. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
191708. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
191709. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
191710. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK
191711. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
191712. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
191713. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
191714. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
191715. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
191716. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK
191717. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT
191718. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
191719. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
191720. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
191721. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
191722. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
191723. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
191724. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
191725. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
191726. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
191727. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
191728. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
191729. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
191730. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
191731. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
191732. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
191733. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
191734. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
191735. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
191736. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
191737. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
191738. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
191739. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
191740. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
191741. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
191742. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
191743. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
191744. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
191745. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
191746. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
191747. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
191748. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
191749. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
191750. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
191751. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
191752. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
191753. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
191754. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
191755. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
191756. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
191757. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
191758. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
191759. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
191760. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
191761. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
191762. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
191763. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
191764. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
191765. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
191766. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
191767. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
191768. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
191769. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
191770. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
191771. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
191772. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
191773. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
191774. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
191775. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
191776. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
191777. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
191778. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
191779. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
191780. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
191781. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
191782. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
191783. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
191784. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
191785. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
191786. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
191787. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
191788. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
191789. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
191790. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
191791. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
191792. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
191793. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
191794. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
191795. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
191796. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
191797. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
191798. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
191799. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
191800. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
191801. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
191802. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
191803. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
191804. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
191805. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
191806. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
191807. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
191808. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
191809. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
191810. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
191811. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
191812. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
191813. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
191814. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
191815. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
191816. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
191817. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
191818. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
191819. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
191820. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
191821. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
191822. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
191823. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
191824. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
191825. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
191826. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
191827. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
191828. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
191829. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
191830. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
191831. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
191832. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
191833. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
191834. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
191835. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
191836. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
191837. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
191838. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
191839. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
191840. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
191841. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
191842. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
191843. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
191844. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
191845. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
191846. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
191847. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
191848. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
191849. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
191850. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
191851. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
191852. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
191853. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
191854. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
191855. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
191856. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
191857. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
191858. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
191859. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
191860. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
191861. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
191862. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
191863. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
191864. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
191865. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
191866. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
191867. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
191868. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
191869. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
191870. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
191871. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
191872. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
191873. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
191874. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
191875. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
191876. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
191877. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
191878. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
191879. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
191880. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
191881. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
191882. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
191883. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
191884. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
191885. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
191886. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
191887. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
191888. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
191889. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
191890. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
191891. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
191892. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
191893. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
191894. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
191895. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
191896. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
191897. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
191898. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
191899. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
191900. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
191901. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
191902. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
191903. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
191904. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
191905. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
191906. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
191907. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
191908. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
191909. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
191910. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
191911. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
191912. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
191913. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
191914. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
191915. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
191916. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
191917. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
191918. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
191919. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
191920. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
191921. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
191922. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
191923. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
191924. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
191925. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
191926. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
191927. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
191928. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
191929. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
191930. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
191931. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
191932. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
191933. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
191934. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
191935. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
191936. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
191937. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
191938. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
191939. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
191940. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
191941. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
191942. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
191943. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
191944. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
191945. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
191946. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
191947. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
191948. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
191949. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
191950. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
191951. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
191952. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
191953. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
191954. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
191955. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
191956. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
191957. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
191958. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
191959. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
191960. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
191961. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
191962. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
191963. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
191964. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
191965. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
191966. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
191967. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
191968. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
191969. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
191970. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
191971. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
191972. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
191973. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
191974. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
191975. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
191976. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
191977. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
191978. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
191979. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
191980. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
191981. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
191982. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
191983. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
191984. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
191985. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
191986. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
191987. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
191988. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
191989. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
191990. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
191991. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
191992. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
191993. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
191994. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
191995. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
191996. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
191997. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
191998. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
191999. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
192000. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
192001. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
192002. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
192003. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
192004. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
192005. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
192006. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
192007. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
192008. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
192009. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
192010. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
192011. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
192012. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
192013. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
192014. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
192015. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
192016. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
192017. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
192018. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
192019. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
192020. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
192021. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
192022. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
192023. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
192024. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
192025. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
192026. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
192027. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
192028. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
192029. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
192030. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
192031. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
192032. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
192033. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
192034. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
192035. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
192036. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
192037. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
192038. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
192039. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
192040. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
192041. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
192042. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
192043. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
192044. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
192045. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
192046. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
192047. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
192048. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
192049. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
192050. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
192051. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
192052. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
192053. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
192054. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
192055. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
192056. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
192057. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
192058. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
192059. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
192060. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
192061. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
192062. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
192063. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
192064. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
192065. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
192066. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
192067. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
192068. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
192069. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
192070. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
192071. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
192072. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
192073. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
192074. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
192075. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
192076. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
192077. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
192078. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
192079. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
192080. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
192081. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
192082. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
192083. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
192084. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
192085. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
192086. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
192087. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
192088. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
192089. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
192090. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
192091. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
192092. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
192093. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
192094. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
192095. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
192096. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
192097. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
192098. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
192099. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
192100. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
192101. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
192102. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
192103. DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
192104. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__NC74_MASK
192105. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__NC74__SHIFT
192106. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__RESERVED_15_8_MASK
192107. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__RESERVED_15_8__SHIFT
192108. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__bypass_bg_MASK
192109. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__bypass_bg__SHIFT
192110. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__chop_en_MASK
192111. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__chop_en__SHIFT
192112. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__vref_sel_fastreg_MASK
192113. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__vref_sel_fastreg__SHIFT
192114. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
192115. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
192116. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK
192117. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
192118. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK
192119. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
192120. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
192121. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
192122. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK
192123. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
192124. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK
192125. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
192126. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK
192127. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
192128. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK
192129. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
192130. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK
192131. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
192132. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
192133. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
192134. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
192135. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
192136. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK
192137. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT
192138. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
192139. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
192140. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK
192141. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
192142. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK
192143. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT
192144. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
192145. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
192146. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK
192147. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
192148. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
192149. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
192150. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__NC76_MASK
192151. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT
192152. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
192153. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
192154. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__atb_select_MASK
192155. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT
192156. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK
192157. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT
192158. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK
192159. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT
192160. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK
192161. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
192162. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK
192163. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT
192164. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK
192165. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT
192166. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC40_MASK
192167. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC40__SHIFT
192168. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC76_MASK
192169. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC76__SHIFT
192170. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK
192171. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
192172. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK
192173. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT
192174. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
192175. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
192176. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK
192177. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT
192178. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK
192179. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT
192180. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
192181. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
192182. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK
192183. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
192184. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK
192185. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
192186. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
192187. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
192188. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK
192189. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
192190. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK
192191. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT
192192. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
192193. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
192194. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK
192195. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
192196. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK
192197. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
192198. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
192199. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
192200. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK
192201. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
192202. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK
192203. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
192204. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK
192205. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
192206. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK
192207. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
192208. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK
192209. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
192210. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
192211. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
192212. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
192213. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
192214. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK
192215. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT
192216. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
192217. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
192218. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK
192219. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
192220. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK
192221. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT
192222. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
192223. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
192224. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK
192225. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
192226. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
192227. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
192228. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__NC76_MASK
192229. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT
192230. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
192231. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
192232. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__atb_select_MASK
192233. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT
192234. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK
192235. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT
192236. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK
192237. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT
192238. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK
192239. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
192240. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK
192241. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT
192242. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK
192243. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT
192244. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC40_MASK
192245. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC40__SHIFT
192246. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC76_MASK
192247. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC76__SHIFT
192248. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK
192249. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
192250. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK
192251. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT
192252. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
192253. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
192254. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK
192255. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT
192256. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK
192257. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT
192258. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
192259. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
192260. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK
192261. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
192262. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK
192263. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
192264. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
192265. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
192266. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK
192267. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
192268. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK
192269. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT
192270. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
192271. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
192272. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK
192273. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT
192274. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK
192275. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
192276. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK
192277. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
192278. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK
192279. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
192280. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
192281. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
192282. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
192283. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
192284. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
192285. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
192286. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK
192287. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
192288. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
192289. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
192290. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
192291. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
192292. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
192293. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
192294. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
192295. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
192296. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK
192297. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
192298. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
192299. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
192300. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
192301. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
192302. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
192303. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
192304. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
192305. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
192306. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
192307. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
192308. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
192309. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
192310. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
192311. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
192312. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
192313. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
192314. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
192315. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
192316. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
192317. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
192318. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
192319. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
192320. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
192321. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
192322. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
192323. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
192324. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
192325. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
192326. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
192327. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
192328. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
192329. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
192330. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
192331. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
192332. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
192333. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
192334. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
192335. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
192336. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
192337. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
192338. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
192339. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
192340. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
192341. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
192342. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
192343. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
192344. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
192345. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
192346. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
192347. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
192348. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
192349. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
192350. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
192351. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
192352. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
192353. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
192354. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
192355. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
192356. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
192357. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
192358. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
192359. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
192360. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
192361. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
192362. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
192363. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
192364. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
192365. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
192366. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
192367. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
192368. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
192369. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
192370. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
192371. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
192372. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
192373. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
192374. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
192375. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
192376. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
192377. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
192378. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
192379. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
192380. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
192381. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
192382. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
192383. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
192384. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK
192385. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT
192386. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
192387. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
192388. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__BG_EN_MASK
192389. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__BG_EN__SHIFT
192390. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK
192391. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT
192392. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK
192393. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT
192394. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK
192395. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT
192396. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
192397. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
192398. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK
192399. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT
192400. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
192401. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
192402. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK
192403. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT
192404. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK
192405. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT
192406. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK
192407. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
192408. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK
192409. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT
192410. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK
192411. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
192412. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK
192413. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT
192414. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK
192415. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT
192416. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK
192417. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT
192418. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK
192419. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
192420. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI__data_MASK
192421. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI__data__SHIFT
192422. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO__data_MASK
192423. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO__data__SHIFT
192424. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
192425. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
192426. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
192427. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
192428. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
192429. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
192430. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
192431. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
192432. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
192433. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
192434. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
192435. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
192436. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
192437. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
192438. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
192439. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
192440. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
192441. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
192442. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
192443. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
192444. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
192445. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
192446. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
192447. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
192448. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
192449. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
192450. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
192451. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
192452. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
192453. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
192454. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
192455. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
192456. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
192457. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
192458. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
192459. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
192460. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
192461. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
192462. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
192463. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
192464. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
192465. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
192466. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
192467. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
192468. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
192469. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
192470. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
192471. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
192472. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
192473. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
192474. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
192475. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
192476. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
192477. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
192478. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
192479. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
192480. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
192481. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
192482. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
192483. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
192484. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
192485. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
192486. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
192487. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
192488. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
192489. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
192490. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
192491. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
192492. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
192493. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
192494. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
192495. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
192496. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
192497. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
192498. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
192499. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
192500. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
192501. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
192502. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
192503. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
192504. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
192505. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
192506. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
192507. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
192508. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
192509. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
192510. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
192511. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
192512. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
192513. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
192514. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
192515. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
192516. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
192517. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
192518. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
192519. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
192520. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
192521. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
192522. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
192523. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
192524. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
192525. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
192526. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
192527. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
192528. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
192529. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
192530. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
192531. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
192532. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
192533. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
192534. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
192535. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
192536. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
192537. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
192538. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
192539. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
192540. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
192541. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
192542. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
192543. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
192544. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
192545. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
192546. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
192547. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
192548. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
192549. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
192550. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
192551. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
192552. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
192553. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
192554. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
192555. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
192556. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
192557. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
192558. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
192559. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
192560. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
192561. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
192562. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
192563. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
192564. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
192565. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
192566. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
192567. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
192568. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
192569. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
192570. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
192571. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
192572. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
192573. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
192574. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
192575. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
192576. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
192577. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
192578. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
192579. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
192580. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
192581. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
192582. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
192583. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
192584. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
192585. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
192586. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
192587. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
192588. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
192589. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
192590. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
192591. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
192592. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
192593. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
192594. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
192595. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
192596. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
192597. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
192598. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
192599. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
192600. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
192601. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
192602. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
192603. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
192604. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
192605. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
192606. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
192607. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
192608. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
192609. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
192610. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
192611. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
192612. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
192613. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
192614. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
192615. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
192616. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
192617. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
192618. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
192619. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
192620. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
192621. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
192622. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
192623. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
192624. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
192625. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
192626. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
192627. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
192628. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
192629. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
192630. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
192631. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
192632. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
192633. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
192634. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
192635. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
192636. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
192637. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
192638. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
192639. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
192640. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
192641. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
192642. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
192643. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
192644. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
192645. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
192646. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
192647. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
192648. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
192649. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
192650. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
192651. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
192652. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
192653. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
192654. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
192655. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
192656. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
192657. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
192658. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
192659. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
192660. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
192661. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
192662. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
192663. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
192664. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
192665. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
192666. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
192667. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
192668. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
192669. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
192670. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
192671. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
192672. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
192673. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
192674. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
192675. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
192676. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
192677. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
192678. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
192679. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
192680. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
192681. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
192682. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
192683. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
192684. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
192685. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
192686. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
192687. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
192688. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
192689. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
192690. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
192691. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
192692. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
192693. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
192694. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
192695. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
192696. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
192697. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
192698. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
192699. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
192700. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
192701. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
192702. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
192703. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
192704. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
192705. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
192706. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
192707. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
192708. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
192709. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
192710. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
192711. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
192712. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
192713. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
192714. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
192715. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
192716. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
192717. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
192718. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
192719. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
192720. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
192721. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
192722. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
192723. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
192724. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
192725. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
192726. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
192727. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
192728. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
192729. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
192730. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
192731. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
192732. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
192733. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
192734. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
192735. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
192736. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
192737. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
192738. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
192739. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
192740. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
192741. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
192742. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
192743. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
192744. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
192745. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
192746. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
192747. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
192748. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
192749. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
192750. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
192751. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
192752. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
192753. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
192754. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
192755. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
192756. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
192757. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
192758. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
192759. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
192760. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
192761. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
192762. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
192763. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
192764. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
192765. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
192766. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
192767. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
192768. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK
192769. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
192770. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
192771. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
192772. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
192773. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
192774. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
192775. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
192776. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
192777. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
192778. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
192779. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
192780. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
192781. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
192782. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
192783. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
192784. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
192785. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
192786. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
192787. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
192788. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
192789. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
192790. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
192791. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
192792. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
192793. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
192794. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
192795. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
192796. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK
192797. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
192798. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK
192799. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
192800. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK
192801. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
192802. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__STAT_MASK
192803. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT
192804. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
192805. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
192806. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
192807. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
192808. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
192809. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
192810. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
192811. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
192812. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
192813. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
192814. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
192815. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
192816. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
192817. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
192818. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
192819. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
192820. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
192821. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
192822. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
192823. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
192824. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
192825. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
192826. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
192827. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
192828. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
192829. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
192830. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
192831. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
192832. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
192833. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
192834. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
192835. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
192836. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
192837. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
192838. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
192839. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
192840. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
192841. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
192842. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
192843. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
192844. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
192845. DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
192846. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__NC74_MASK
192847. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__NC74__SHIFT
192848. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__RESERVED_15_8_MASK
192849. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__RESERVED_15_8__SHIFT
192850. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__bypass_bg_MASK
192851. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__bypass_bg__SHIFT
192852. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__chop_en_MASK
192853. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__chop_en__SHIFT
192854. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__vref_sel_fastreg_MASK
192855. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__vref_sel_fastreg__SHIFT
192856. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
192857. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
192858. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK
192859. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
192860. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK
192861. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
192862. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
192863. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
192864. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK
192865. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
192866. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK
192867. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
192868. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK
192869. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
192870. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK
192871. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
192872. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK
192873. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
192874. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
192875. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
192876. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
192877. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
192878. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_gd_MASK
192879. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT
192880. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
192881. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
192882. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK
192883. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
192884. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vp_MASK
192885. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT
192886. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
192887. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
192888. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK
192889. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
192890. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
192891. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
192892. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__NC76_MASK
192893. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__NC76__SHIFT
192894. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
192895. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
192896. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__atb_select_MASK
192897. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT
192898. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK
192899. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT
192900. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK
192901. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT
192902. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK
192903. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
192904. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK
192905. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT
192906. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK
192907. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT
192908. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC40_MASK
192909. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC40__SHIFT
192910. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC76_MASK
192911. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC76__SHIFT
192912. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK
192913. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
192914. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK
192915. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT
192916. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
192917. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
192918. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__cal_reg_MASK
192919. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT
192920. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__enable_reg_MASK
192921. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT
192922. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
192923. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
192924. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK
192925. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
192926. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK
192927. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
192928. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
192929. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
192930. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK
192931. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
192932. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__reset_reg_MASK
192933. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT
192934. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
192935. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
192936. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK
192937. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
192938. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK
192939. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
192940. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
192941. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
192942. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK
192943. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
192944. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK
192945. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
192946. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK
192947. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
192948. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK
192949. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
192950. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK
192951. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
192952. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
192953. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
192954. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
192955. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
192956. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_gd_MASK
192957. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT
192958. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
192959. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
192960. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK
192961. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
192962. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vp_MASK
192963. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT
192964. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
192965. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
192966. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK
192967. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
192968. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
192969. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
192970. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__NC76_MASK
192971. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__NC76__SHIFT
192972. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
192973. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
192974. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__atb_select_MASK
192975. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT
192976. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK
192977. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT
192978. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK
192979. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT
192980. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK
192981. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
192982. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK
192983. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT
192984. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK
192985. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT
192986. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC40_MASK
192987. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC40__SHIFT
192988. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC76_MASK
192989. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC76__SHIFT
192990. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK
192991. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
192992. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK
192993. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT
192994. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
192995. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
192996. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__cal_reg_MASK
192997. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT
192998. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__enable_reg_MASK
192999. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT
193000. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
193001. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
193002. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK
193003. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
193004. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK
193005. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
193006. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
193007. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
193008. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK
193009. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
193010. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__reset_reg_MASK
193011. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT
193012. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
193013. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
193014. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_atb_MASK
193015. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT
193016. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK
193017. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
193018. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK
193019. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
193020. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK
193021. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
193022. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
193023. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
193024. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
193025. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
193026. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
193027. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
193028. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK
193029. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
193030. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
193031. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
193032. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
193033. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
193034. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
193035. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
193036. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
193037. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
193038. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK
193039. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
193040. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
193041. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
193042. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
193043. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
193044. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
193045. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
193046. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
193047. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
193048. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
193049. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
193050. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
193051. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
193052. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
193053. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
193054. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
193055. DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
193056. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
193057. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
193058. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
193059. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
193060. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
193061. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
193062. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
193063. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
193064. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
193065. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
193066. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
193067. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
193068. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
193069. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
193070. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
193071. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
193072. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
193073. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
193074. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
193075. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
193076. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
193077. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
193078. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
193079. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
193080. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
193081. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
193082. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
193083. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
193084. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
193085. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
193086. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
193087. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
193088. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
193089. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
193090. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
193091. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
193092. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
193093. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
193094. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
193095. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
193096. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
193097. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
193098. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
193099. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
193100. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
193101. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
193102. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
193103. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
193104. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
193105. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
193106. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
193107. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
193108. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
193109. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
193110. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
193111. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
193112. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
193113. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
193114. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
193115. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
193116. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
193117. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
193118. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
193119. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
193120. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
193121. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
193122. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
193123. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
193124. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
193125. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
193126. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK
193127. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT
193128. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
193129. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
193130. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__BG_EN_MASK
193131. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__BG_EN__SHIFT
193132. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK
193133. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT
193134. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK
193135. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT
193136. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__PHY_RESET_MASK
193137. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT
193138. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
193139. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
193140. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK
193141. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT
193142. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
193143. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
193144. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK
193145. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT
193146. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK
193147. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT
193148. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK
193149. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
193150. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK
193151. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT
193152. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK
193153. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
193154. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK
193155. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT
193156. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK
193157. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT
193158. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK
193159. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT
193160. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK
193161. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
193162. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI__data_MASK
193163. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI__data__SHIFT
193164. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO__data_MASK
193165. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO__data__SHIFT
193166. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
193167. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
193168. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
193169. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
193170. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
193171. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
193172. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
193173. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
193174. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
193175. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
193176. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
193177. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
193178. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
193179. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
193180. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
193181. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
193182. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
193183. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
193184. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
193185. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
193186. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
193187. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
193188. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
193189. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
193190. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
193191. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
193192. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
193193. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
193194. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
193195. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
193196. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
193197. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
193198. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
193199. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
193200. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
193201. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
193202. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
193203. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
193204. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
193205. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
193206. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
193207. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
193208. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
193209. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
193210. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
193211. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
193212. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
193213. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
193214. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
193215. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
193216. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
193217. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
193218. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
193219. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
193220. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
193221. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
193222. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
193223. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
193224. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
193225. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
193226. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
193227. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
193228. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
193229. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
193230. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
193231. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
193232. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
193233. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
193234. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
193235. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
193236. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
193237. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
193238. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
193239. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
193240. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
193241. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
193242. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
193243. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
193244. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
193245. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
193246. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
193247. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
193248. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
193249. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
193250. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
193251. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
193252. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
193253. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
193254. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
193255. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
193256. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
193257. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
193258. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
193259. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
193260. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
193261. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
193262. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
193263. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
193264. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
193265. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
193266. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
193267. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
193268. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
193269. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
193270. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
193271. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
193272. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
193273. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
193274. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
193275. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
193276. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
193277. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
193278. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
193279. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
193280. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
193281. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
193282. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
193283. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
193284. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
193285. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
193286. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
193287. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
193288. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
193289. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
193290. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
193291. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
193292. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
193293. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
193294. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
193295. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
193296. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
193297. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
193298. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
193299. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
193300. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
193301. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
193302. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
193303. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
193304. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
193305. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
193306. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
193307. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
193308. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
193309. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
193310. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
193311. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
193312. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
193313. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
193314. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
193315. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
193316. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
193317. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
193318. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
193319. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
193320. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
193321. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
193322. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
193323. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
193324. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
193325. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
193326. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
193327. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
193328. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
193329. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
193330. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
193331. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
193332. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
193333. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
193334. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
193335. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
193336. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
193337. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
193338. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
193339. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
193340. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
193341. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
193342. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
193343. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
193344. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
193345. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
193346. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
193347. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
193348. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
193349. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
193350. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
193351. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
193352. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
193353. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
193354. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
193355. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
193356. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
193357. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
193358. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
193359. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
193360. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
193361. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
193362. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
193363. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
193364. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
193365. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
193366. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
193367. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
193368. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
193369. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
193370. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
193371. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
193372. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
193373. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
193374. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
193375. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
193376. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
193377. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
193378. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
193379. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
193380. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
193381. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
193382. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
193383. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
193384. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
193385. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
193386. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
193387. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
193388. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
193389. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
193390. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
193391. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
193392. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
193393. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
193394. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
193395. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
193396. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
193397. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
193398. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
193399. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
193400. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
193401. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
193402. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
193403. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
193404. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
193405. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
193406. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
193407. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
193408. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
193409. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
193410. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
193411. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
193412. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
193413. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
193414. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
193415. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
193416. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
193417. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
193418. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
193419. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
193420. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
193421. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
193422. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
193423. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
193424. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
193425. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
193426. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
193427. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
193428. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
193429. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
193430. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
193431. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
193432. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
193433. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
193434. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
193435. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
193436. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
193437. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
193438. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
193439. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
193440. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
193441. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
193442. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
193443. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
193444. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
193445. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
193446. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
193447. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
193448. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
193449. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
193450. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
193451. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
193452. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
193453. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
193454. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
193455. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
193456. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
193457. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
193458. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
193459. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
193460. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
193461. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
193462. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
193463. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
193464. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
193465. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
193466. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
193467. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
193468. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
193469. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
193470. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
193471. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
193472. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
193473. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
193474. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
193475. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
193476. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
193477. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
193478. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
193479. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
193480. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
193481. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
193482. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
193483. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
193484. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
193485. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
193486. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
193487. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
193488. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
193489. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
193490. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
193491. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
193492. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
193493. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
193494. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
193495. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
193496. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
193497. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
193498. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
193499. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
193500. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
193501. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
193502. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
193503. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
193504. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
193505. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
193506. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
193507. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
193508. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
193509. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
193510. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK
193511. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
193512. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
193513. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
193514. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
193515. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
193516. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
193517. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
193518. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
193519. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
193520. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
193521. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
193522. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
193523. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
193524. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
193525. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
193526. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
193527. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
193528. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
193529. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
193530. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
193531. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
193532. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
193533. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
193534. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
193535. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
193536. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
193537. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
193538. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK
193539. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
193540. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK
193541. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
193542. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK
193543. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
193544. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__STAT_MASK
193545. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__STAT__SHIFT
193546. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
193547. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
193548. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
193549. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
193550. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
193551. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
193552. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
193553. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
193554. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
193555. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
193556. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
193557. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
193558. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
193559. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
193560. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
193561. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
193562. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
193563. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
193564. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
193565. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
193566. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
193567. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
193568. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
193569. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
193570. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
193571. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
193572. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
193573. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
193574. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
193575. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
193576. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
193577. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
193578. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
193579. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
193580. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
193581. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
193582. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
193583. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
193584. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
193585. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
193586. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
193587. DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
193588. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
193589. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
193590. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
193591. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
193592. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
193593. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
193594. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
193595. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
193596. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
193597. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
193598. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK
193599. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT
193600. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
193601. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
193602. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
193603. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
193604. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
193605. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
193606. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
193607. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
193608. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
193609. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
193610. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
193611. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
193612. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
193613. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
193614. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
193615. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
193616. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
193617. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
193618. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
193619. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
193620. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
193621. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
193622. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
193623. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
193624. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
193625. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
193626. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
193627. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
193628. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
193629. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
193630. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK
193631. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
193632. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK
193633. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
193634. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK
193635. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
193636. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
193637. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
193638. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
193639. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
193640. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
193641. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
193642. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
193643. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
193644. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
193645. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
193646. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
193647. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
193648. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
193649. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
193650. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
193651. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
193652. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
193653. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
193654. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
193655. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
193656. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
193657. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
193658. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
193659. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
193660. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
193661. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
193662. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
193663. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
193664. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
193665. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
193666. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
193667. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
193668. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
193669. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
193670. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
193671. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
193672. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
193673. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
193674. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
193675. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
193676. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK
193677. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
193678. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK
193679. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
193680. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
193681. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
193682. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
193683. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
193684. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
193685. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
193686. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
193687. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
193688. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK
193689. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
193690. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
193691. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
193692. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
193693. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
193694. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
193695. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
193696. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
193697. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
193698. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
193699. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
193700. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__NC32_MASK
193701. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT
193702. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
193703. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
193704. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
193705. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
193706. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
193707. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
193708. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
193709. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
193710. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
193711. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
193712. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK
193713. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
193714. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
193715. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
193716. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
193717. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
193718. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
193719. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
193720. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
193721. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
193722. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
193723. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
193724. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK
193725. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
193726. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
193727. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
193728. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
193729. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
193730. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
193731. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
193732. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
193733. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
193734. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK
193735. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT
193736. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
193737. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
193738. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
193739. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
193740. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
193741. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
193742. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
193743. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
193744. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
193745. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
193746. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
193747. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
193748. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
193749. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
193750. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
193751. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
193752. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
193753. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
193754. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
193755. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
193756. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__NC20_MASK
193757. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__NC20__SHIFT
193758. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK
193759. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT
193760. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
193761. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
193762. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
193763. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
193764. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
193765. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
193766. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK
193767. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
193768. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK
193769. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
193770. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
193771. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
193772. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK
193773. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
193774. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK
193775. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
193776. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK
193777. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT
193778. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
193779. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
193780. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK
193781. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT
193782. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK
193783. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT
193784. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
193785. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
193786. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK
193787. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT
193788. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_gd_MASK
193789. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_gd__SHIFT
193790. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccm_MASK
193791. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT
193792. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccp_MASK
193793. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT
193794. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vptx_MASK
193795. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT
193796. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg0_MASK
193797. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT
193798. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg1_MASK
193799. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT
193800. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK
193801. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT
193802. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__override_regref_0_MASK
193803. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT
193804. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK
193805. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT
193806. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_nbias_MASK
193807. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT
193808. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_pbias_MASK
193809. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT
193810. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK
193811. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT
193812. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfm_MASK
193813. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT
193814. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfp_MASK
193815. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT
193816. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsm_MASK
193817. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT
193818. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsp_MASK
193819. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT
193820. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_vcm_MASK
193821. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT
193822. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
193823. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
193824. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK
193825. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
193826. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
193827. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
193828. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
193829. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
193830. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
193831. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
193832. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
193833. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
193834. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK
193835. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT
193836. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK
193837. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
193838. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__nc_MASK
193839. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__nc__SHIFT
193840. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_nmos_MASK
193841. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_nmos__SHIFT
193842. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_pmos_MASK
193843. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_pmos__SHIFT
193844. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__override_rxdetref_MASK
193845. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT
193846. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
193847. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
193848. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
193849. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
193850. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
193851. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
193852. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
193853. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
193854. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK
193855. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
193856. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
193857. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
193858. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
193859. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
193860. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
193861. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
193862. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
193863. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
193864. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
193865. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
193866. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
193867. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
193868. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
193869. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
193870. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
193871. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
193872. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
193873. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
193874. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
193875. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
193876. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
193877. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
193878. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
193879. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
193880. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
193881. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
193882. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
193883. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
193884. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
193885. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
193886. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK
193887. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
193888. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK
193889. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
193890. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
193891. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
193892. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK
193893. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
193894. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
193895. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
193896. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
193897. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
193898. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK
193899. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
193900. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
193901. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
193902. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
193903. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
193904. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
193905. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
193906. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
193907. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
193908. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
193909. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
193910. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
193911. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
193912. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK
193913. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
193914. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK
193915. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT
193916. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_MASK
193917. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT
193918. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK
193919. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
193920. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
193921. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
193922. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK
193923. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
193924. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK
193925. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
193926. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK
193927. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
193928. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK
193929. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT
193930. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
193931. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
193932. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
193933. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
193934. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
193935. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
193936. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
193937. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
193938. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
193939. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
193940. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
193941. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
193942. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
193943. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
193944. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
193945. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
193946. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
193947. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
193948. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
193949. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
193950. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
193951. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
193952. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
193953. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
193954. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
193955. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
193956. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
193957. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
193958. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
193959. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
193960. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
193961. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
193962. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
193963. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
193964. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
193965. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
193966. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
193967. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
193968. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
193969. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
193970. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
193971. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
193972. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
193973. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
193974. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
193975. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
193976. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
193977. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
193978. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
193979. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
193980. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
193981. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
193982. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
193983. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
193984. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
193985. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
193986. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
193987. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
193988. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
193989. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
193990. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
193991. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
193992. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
193993. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
193994. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
193995. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
193996. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
193997. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
193998. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
193999. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
194000. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
194001. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
194002. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
194003. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
194004. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
194005. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
194006. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
194007. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
194008. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
194009. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
194010. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
194011. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
194012. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
194013. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
194014. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
194015. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
194016. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
194017. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
194018. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
194019. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
194020. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
194021. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
194022. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
194023. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
194024. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
194025. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
194026. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
194027. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
194028. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
194029. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
194030. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
194031. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
194032. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
194033. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
194034. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
194035. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
194036. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
194037. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
194038. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
194039. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
194040. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
194041. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
194042. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
194043. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
194044. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
194045. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
194046. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
194047. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
194048. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
194049. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
194050. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
194051. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
194052. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
194053. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
194054. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
194055. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
194056. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
194057. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
194058. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
194059. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
194060. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
194061. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
194062. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
194063. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
194064. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
194065. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
194066. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
194067. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
194068. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
194069. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
194070. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
194071. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
194072. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
194073. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
194074. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
194075. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
194076. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
194077. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
194078. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
194079. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
194080. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
194081. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
194082. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
194083. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
194084. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
194085. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
194086. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
194087. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
194088. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
194089. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
194090. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
194091. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
194092. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
194093. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
194094. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
194095. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
194096. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
194097. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
194098. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
194099. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
194100. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
194101. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
194102. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
194103. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
194104. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
194105. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
194106. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
194107. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
194108. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
194109. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
194110. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
194111. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
194112. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
194113. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
194114. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
194115. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
194116. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
194117. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
194118. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
194119. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
194120. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
194121. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
194122. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
194123. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
194124. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
194125. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
194126. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
194127. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
194128. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
194129. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
194130. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
194131. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
194132. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
194133. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
194134. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
194135. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
194136. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
194137. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
194138. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
194139. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
194140. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
194141. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
194142. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
194143. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
194144. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
194145. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
194146. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
194147. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
194148. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
194149. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
194150. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
194151. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
194152. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
194153. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
194154. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
194155. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
194156. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
194157. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
194158. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
194159. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
194160. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
194161. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
194162. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
194163. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
194164. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
194165. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
194166. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
194167. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
194168. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
194169. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
194170. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
194171. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
194172. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
194173. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
194174. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK
194175. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
194176. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
194177. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
194178. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
194179. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
194180. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
194181. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
194182. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
194183. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
194184. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
194185. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
194186. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
194187. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
194188. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
194189. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
194190. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
194191. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
194192. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
194193. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
194194. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
194195. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
194196. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
194197. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
194198. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
194199. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
194200. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
194201. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
194202. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
194203. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
194204. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
194205. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
194206. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
194207. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
194208. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
194209. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
194210. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
194211. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
194212. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
194213. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
194214. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
194215. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
194216. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
194217. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
194218. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
194219. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
194220. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
194221. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
194222. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
194223. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
194224. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
194225. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
194226. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
194227. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
194228. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
194229. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
194230. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
194231. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
194232. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
194233. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
194234. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
194235. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
194236. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
194237. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
194238. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
194239. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
194240. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
194241. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
194242. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
194243. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
194244. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
194245. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
194246. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
194247. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
194248. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
194249. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
194250. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
194251. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
194252. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
194253. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
194254. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
194255. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
194256. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
194257. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
194258. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
194259. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
194260. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
194261. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
194262. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
194263. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
194264. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
194265. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
194266. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
194267. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
194268. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
194269. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
194270. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
194271. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
194272. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
194273. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
194274. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
194275. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
194276. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
194277. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
194278. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
194279. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
194280. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
194281. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
194282. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
194283. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
194284. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
194285. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
194286. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
194287. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
194288. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
194289. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
194290. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
194291. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
194292. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
194293. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
194294. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
194295. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
194296. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
194297. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
194298. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
194299. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
194300. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
194301. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
194302. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
194303. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
194304. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
194305. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
194306. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
194307. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
194308. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
194309. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
194310. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
194311. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
194312. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
194313. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
194314. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
194315. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
194316. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
194317. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
194318. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
194319. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
194320. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
194321. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
194322. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
194323. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
194324. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
194325. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
194326. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
194327. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
194328. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
194329. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
194330. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
194331. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
194332. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
194333. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
194334. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
194335. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
194336. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
194337. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
194338. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
194339. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
194340. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
194341. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
194342. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
194343. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
194344. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
194345. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
194346. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
194347. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
194348. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
194349. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
194350. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
194351. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
194352. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
194353. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
194354. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
194355. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
194356. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
194357. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
194358. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
194359. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
194360. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
194361. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
194362. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
194363. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
194364. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
194365. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
194366. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
194367. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
194368. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
194369. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
194370. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
194371. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
194372. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
194373. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
194374. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
194375. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
194376. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
194377. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
194378. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
194379. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
194380. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
194381. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
194382. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
194383. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
194384. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
194385. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
194386. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
194387. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
194388. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
194389. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
194390. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
194391. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
194392. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
194393. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
194394. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
194395. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
194396. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
194397. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
194398. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
194399. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
194400. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
194401. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
194402. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
194403. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
194404. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
194405. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
194406. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
194407. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
194408. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
194409. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
194410. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
194411. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
194412. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
194413. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
194414. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
194415. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
194416. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
194417. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
194418. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
194419. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
194420. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
194421. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
194422. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
194423. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
194424. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
194425. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
194426. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
194427. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
194428. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
194429. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
194430. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
194431. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
194432. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
194433. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
194434. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
194435. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
194436. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
194437. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
194438. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
194439. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
194440. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
194441. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
194442. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
194443. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
194444. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
194445. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
194446. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
194447. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
194448. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
194449. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
194450. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
194451. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
194452. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
194453. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
194454. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
194455. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
194456. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
194457. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
194458. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
194459. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
194460. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
194461. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
194462. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
194463. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
194464. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
194465. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
194466. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
194467. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
194468. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
194469. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
194470. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
194471. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
194472. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
194473. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
194474. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
194475. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
194476. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
194477. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
194478. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
194479. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
194480. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
194481. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
194482. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
194483. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
194484. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
194485. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
194486. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
194487. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
194488. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
194489. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
194490. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
194491. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
194492. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
194493. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
194494. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
194495. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
194496. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
194497. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
194498. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
194499. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
194500. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
194501. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
194502. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
194503. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
194504. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
194505. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
194506. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
194507. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
194508. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
194509. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
194510. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
194511. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
194512. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
194513. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
194514. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
194515. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
194516. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
194517. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
194518. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
194519. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
194520. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
194521. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
194522. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
194523. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
194524. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
194525. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
194526. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
194527. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
194528. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
194529. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
194530. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
194531. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
194532. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
194533. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
194534. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
194535. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
194536. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
194537. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
194538. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
194539. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
194540. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
194541. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
194542. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
194543. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
194544. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
194545. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
194546. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
194547. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
194548. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
194549. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
194550. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
194551. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
194552. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
194553. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
194554. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
194555. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
194556. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
194557. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
194558. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
194559. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
194560. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
194561. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
194562. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
194563. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
194564. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
194565. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
194566. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
194567. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
194568. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
194569. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
194570. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
194571. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
194572. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
194573. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
194574. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
194575. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
194576. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
194577. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
194578. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
194579. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
194580. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
194581. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
194582. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
194583. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
194584. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
194585. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
194586. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
194587. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
194588. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
194589. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
194590. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
194591. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
194592. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
194593. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
194594. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
194595. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
194596. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
194597. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
194598. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
194599. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
194600. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
194601. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
194602. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
194603. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
194604. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
194605. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
194606. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
194607. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
194608. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
194609. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
194610. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
194611. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
194612. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
194613. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
194614. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
194615. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
194616. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
194617. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
194618. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
194619. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
194620. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
194621. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
194622. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
194623. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
194624. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
194625. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
194626. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
194627. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
194628. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
194629. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
194630. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
194631. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
194632. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
194633. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
194634. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
194635. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
194636. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
194637. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
194638. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
194639. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
194640. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
194641. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
194642. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
194643. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
194644. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
194645. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
194646. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
194647. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
194648. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
194649. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
194650. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
194651. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
194652. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
194653. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
194654. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
194655. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
194656. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
194657. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
194658. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
194659. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
194660. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
194661. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
194662. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
194663. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
194664. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
194665. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
194666. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
194667. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
194668. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
194669. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
194670. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
194671. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
194672. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
194673. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
194674. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
194675. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
194676. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
194677. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
194678. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
194679. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
194680. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
194681. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
194682. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
194683. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
194684. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
194685. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
194686. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
194687. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
194688. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
194689. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
194690. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
194691. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
194692. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
194693. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
194694. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
194695. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
194696. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
194697. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
194698. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
194699. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
194700. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
194701. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
194702. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
194703. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
194704. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
194705. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
194706. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
194707. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
194708. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
194709. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
194710. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
194711. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
194712. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
194713. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
194714. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
194715. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
194716. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
194717. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
194718. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
194719. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
194720. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
194721. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
194722. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
194723. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
194724. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
194725. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
194726. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
194727. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
194728. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
194729. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
194730. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK
194731. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT
194732. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__MODE_MASK
194733. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT
194734. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
194735. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
194736. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK
194737. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT
194738. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK
194739. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT
194740. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__OV14_MASK
194741. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT
194742. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
194743. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
194744. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
194745. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
194746. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
194747. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
194748. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
194749. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
194750. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
194751. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
194752. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
194753. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
194754. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
194755. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
194756. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
194757. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
194758. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
194759. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
194760. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
194761. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
194762. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
194763. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
194764. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
194765. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
194766. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
194767. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
194768. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
194769. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
194770. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
194771. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
194772. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
194773. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
194774. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
194775. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
194776. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
194777. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
194778. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
194779. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
194780. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
194781. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
194782. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
194783. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
194784. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
194785. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
194786. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
194787. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
194788. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
194789. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
194790. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
194791. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
194792. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
194793. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
194794. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
194795. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
194796. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
194797. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
194798. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
194799. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
194800. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
194801. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
194802. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
194803. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
194804. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
194805. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
194806. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
194807. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
194808. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
194809. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
194810. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
194811. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
194812. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
194813. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
194814. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
194815. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
194816. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
194817. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
194818. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
194819. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
194820. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
194821. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
194822. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
194823. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
194824. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
194825. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
194826. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
194827. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
194828. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
194829. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
194830. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
194831. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
194832. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
194833. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
194834. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
194835. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
194836. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
194837. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
194838. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
194839. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
194840. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
194841. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
194842. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
194843. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
194844. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
194845. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
194846. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
194847. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
194848. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
194849. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
194850. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
194851. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
194852. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
194853. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
194854. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
194855. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
194856. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
194857. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
194858. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
194859. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
194860. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
194861. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
194862. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
194863. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
194864. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
194865. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
194866. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
194867. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
194868. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
194869. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
194870. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
194871. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
194872. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
194873. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
194874. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
194875. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
194876. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
194877. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
194878. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
194879. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
194880. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
194881. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
194882. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
194883. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
194884. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
194885. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
194886. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
194887. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
194888. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
194889. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
194890. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
194891. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
194892. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
194893. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
194894. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
194895. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
194896. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
194897. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
194898. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
194899. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
194900. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
194901. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
194902. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
194903. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
194904. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
194905. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
194906. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
194907. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
194908. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
194909. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
194910. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
194911. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
194912. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
194913. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
194914. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
194915. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
194916. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
194917. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
194918. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
194919. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
194920. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
194921. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
194922. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
194923. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
194924. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
194925. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
194926. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
194927. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
194928. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
194929. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
194930. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
194931. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
194932. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
194933. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
194934. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
194935. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
194936. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
194937. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
194938. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
194939. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
194940. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
194941. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
194942. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
194943. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
194944. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
194945. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
194946. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
194947. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
194948. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
194949. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
194950. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
194951. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
194952. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
194953. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
194954. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
194955. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
194956. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
194957. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
194958. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
194959. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
194960. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
194961. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
194962. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
194963. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
194964. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
194965. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
194966. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
194967. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
194968. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
194969. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
194970. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
194971. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
194972. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
194973. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
194974. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
194975. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
194976. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
194977. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
194978. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
194979. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
194980. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
194981. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
194982. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
194983. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
194984. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
194985. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
194986. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
194987. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
194988. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
194989. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
194990. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
194991. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
194992. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
194993. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
194994. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
194995. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
194996. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
194997. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
194998. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
194999. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
195000. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
195001. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
195002. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
195003. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
195004. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
195005. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
195006. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
195007. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
195008. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
195009. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
195010. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
195011. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
195012. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
195013. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
195014. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
195015. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
195016. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
195017. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
195018. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
195019. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
195020. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
195021. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
195022. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
195023. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
195024. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
195025. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
195026. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
195027. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
195028. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
195029. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
195030. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
195031. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
195032. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
195033. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
195034. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
195035. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
195036. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
195037. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
195038. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
195039. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
195040. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
195041. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
195042. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
195043. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
195044. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
195045. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
195046. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
195047. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
195048. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
195049. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
195050. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
195051. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
195052. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
195053. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
195054. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
195055. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
195056. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
195057. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
195058. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
195059. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
195060. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
195061. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
195062. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
195063. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
195064. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
195065. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
195066. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
195067. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
195068. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
195069. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
195070. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
195071. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
195072. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
195073. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
195074. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
195075. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
195076. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
195077. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
195078. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
195079. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
195080. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
195081. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
195082. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
195083. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
195084. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK
195085. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT
195086. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK
195087. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT
195088. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
195089. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
195090. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
195091. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
195092. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
195093. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
195094. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
195095. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
195096. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
195097. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
195098. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
195099. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
195100. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
195101. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
195102. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
195103. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
195104. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
195105. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
195106. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
195107. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
195108. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
195109. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
195110. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
195111. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
195112. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
195113. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
195114. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
195115. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
195116. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
195117. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
195118. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
195119. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
195120. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
195121. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
195122. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
195123. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
195124. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
195125. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
195126. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
195127. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
195128. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
195129. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
195130. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
195131. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
195132. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
195133. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
195134. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
195135. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
195136. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
195137. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
195138. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
195139. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
195140. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
195141. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
195142. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
195143. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
195144. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
195145. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
195146. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
195147. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
195148. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
195149. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
195150. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
195151. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
195152. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
195153. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
195154. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
195155. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
195156. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
195157. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
195158. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
195159. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
195160. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
195161. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
195162. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
195163. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
195164. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
195165. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
195166. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
195167. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
195168. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
195169. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
195170. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
195171. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
195172. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
195173. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
195174. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
195175. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
195176. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
195177. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
195178. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
195179. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
195180. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
195181. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
195182. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
195183. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
195184. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
195185. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
195186. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
195187. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
195188. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
195189. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
195190. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
195191. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
195192. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
195193. DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
195194. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
195195. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
195196. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
195197. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
195198. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
195199. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
195200. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
195201. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
195202. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
195203. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
195204. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK
195205. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT
195206. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
195207. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
195208. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
195209. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
195210. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
195211. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
195212. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
195213. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
195214. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
195215. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
195216. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
195217. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
195218. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
195219. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
195220. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
195221. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
195222. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
195223. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
195224. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
195225. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
195226. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
195227. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
195228. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
195229. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
195230. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
195231. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
195232. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
195233. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
195234. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
195235. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
195236. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK
195237. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
195238. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK
195239. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
195240. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK
195241. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
195242. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
195243. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
195244. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
195245. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
195246. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
195247. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
195248. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
195249. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
195250. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
195251. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
195252. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
195253. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
195254. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
195255. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
195256. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
195257. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
195258. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
195259. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
195260. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
195261. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
195262. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
195263. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
195264. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
195265. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
195266. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
195267. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
195268. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
195269. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
195270. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
195271. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
195272. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
195273. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
195274. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
195275. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
195276. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
195277. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
195278. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
195279. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
195280. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
195281. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
195282. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK
195283. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
195284. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK
195285. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
195286. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
195287. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
195288. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
195289. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
195290. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
195291. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
195292. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
195293. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
195294. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK
195295. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
195296. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
195297. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
195298. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
195299. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
195300. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
195301. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
195302. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
195303. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
195304. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
195305. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
195306. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__NC32_MASK
195307. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT
195308. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
195309. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
195310. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
195311. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
195312. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
195313. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
195314. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
195315. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
195316. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
195317. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
195318. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK
195319. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
195320. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
195321. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
195322. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
195323. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
195324. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
195325. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
195326. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
195327. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
195328. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
195329. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
195330. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK
195331. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
195332. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
195333. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
195334. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
195335. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
195336. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
195337. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
195338. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
195339. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
195340. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK
195341. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT
195342. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
195343. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
195344. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
195345. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
195346. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
195347. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
195348. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
195349. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
195350. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
195351. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
195352. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
195353. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
195354. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
195355. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
195356. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
195357. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
195358. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
195359. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
195360. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
195361. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
195362. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__NC20_MASK
195363. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__NC20__SHIFT
195364. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK
195365. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT
195366. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
195367. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
195368. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
195369. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
195370. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
195371. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
195372. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK
195373. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
195374. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK
195375. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
195376. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
195377. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
195378. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK
195379. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
195380. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK
195381. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
195382. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK
195383. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT
195384. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
195385. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
195386. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK
195387. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT
195388. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK
195389. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT
195390. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
195391. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
195392. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK
195393. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT
195394. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_gd_MASK
195395. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_gd__SHIFT
195396. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccm_MASK
195397. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT
195398. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccp_MASK
195399. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT
195400. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vptx_MASK
195401. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT
195402. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg0_MASK
195403. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT
195404. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg1_MASK
195405. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT
195406. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK
195407. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT
195408. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__override_regref_0_MASK
195409. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT
195410. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK
195411. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT
195412. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_nbias_MASK
195413. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT
195414. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_pbias_MASK
195415. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT
195416. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK
195417. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT
195418. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfm_MASK
195419. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT
195420. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfp_MASK
195421. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT
195422. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsm_MASK
195423. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT
195424. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsp_MASK
195425. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT
195426. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_vcm_MASK
195427. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT
195428. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
195429. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
195430. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK
195431. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
195432. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
195433. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
195434. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
195435. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
195436. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
195437. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
195438. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
195439. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
195440. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK
195441. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT
195442. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK
195443. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
195444. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__nc_MASK
195445. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__nc__SHIFT
195446. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_nmos_MASK
195447. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_nmos__SHIFT
195448. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_pmos_MASK
195449. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_pmos__SHIFT
195450. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__override_rxdetref_MASK
195451. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT
195452. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
195453. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
195454. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
195455. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
195456. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
195457. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
195458. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
195459. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
195460. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK
195461. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
195462. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
195463. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
195464. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
195465. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
195466. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
195467. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
195468. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
195469. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
195470. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
195471. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
195472. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
195473. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
195474. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
195475. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
195476. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
195477. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
195478. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
195479. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
195480. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
195481. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
195482. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
195483. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
195484. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
195485. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
195486. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
195487. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
195488. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
195489. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
195490. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
195491. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
195492. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK
195493. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
195494. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK
195495. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
195496. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
195497. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
195498. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK
195499. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
195500. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
195501. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
195502. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
195503. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
195504. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK
195505. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
195506. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
195507. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
195508. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
195509. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
195510. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
195511. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
195512. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
195513. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
195514. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
195515. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
195516. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
195517. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
195518. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK
195519. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
195520. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK
195521. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT
195522. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_MASK
195523. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT
195524. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK
195525. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
195526. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
195527. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
195528. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK
195529. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
195530. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK
195531. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
195532. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK
195533. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
195534. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK
195535. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT
195536. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
195537. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
195538. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
195539. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
195540. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
195541. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
195542. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
195543. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
195544. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
195545. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
195546. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
195547. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
195548. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
195549. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
195550. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
195551. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
195552. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
195553. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
195554. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
195555. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
195556. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
195557. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
195558. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
195559. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
195560. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
195561. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
195562. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
195563. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
195564. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
195565. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
195566. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
195567. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
195568. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
195569. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
195570. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
195571. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
195572. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
195573. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
195574. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
195575. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
195576. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
195577. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
195578. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
195579. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
195580. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
195581. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
195582. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
195583. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
195584. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
195585. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
195586. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
195587. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
195588. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
195589. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
195590. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
195591. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
195592. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
195593. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
195594. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
195595. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
195596. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
195597. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
195598. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
195599. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
195600. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
195601. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
195602. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
195603. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
195604. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
195605. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
195606. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
195607. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
195608. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
195609. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
195610. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
195611. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
195612. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
195613. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
195614. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
195615. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
195616. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
195617. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
195618. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
195619. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
195620. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
195621. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
195622. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
195623. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
195624. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
195625. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
195626. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
195627. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
195628. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
195629. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
195630. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
195631. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
195632. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
195633. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
195634. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
195635. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
195636. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
195637. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
195638. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
195639. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
195640. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
195641. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
195642. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
195643. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
195644. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
195645. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
195646. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
195647. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
195648. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
195649. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
195650. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
195651. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
195652. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
195653. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
195654. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
195655. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
195656. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
195657. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
195658. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
195659. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
195660. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
195661. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
195662. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
195663. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
195664. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
195665. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
195666. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
195667. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
195668. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
195669. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
195670. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
195671. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
195672. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
195673. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
195674. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
195675. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
195676. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
195677. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
195678. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
195679. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
195680. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
195681. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
195682. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
195683. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
195684. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
195685. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
195686. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
195687. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
195688. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
195689. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
195690. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
195691. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
195692. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
195693. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
195694. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
195695. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
195696. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
195697. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
195698. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
195699. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
195700. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
195701. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
195702. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
195703. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
195704. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
195705. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
195706. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
195707. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
195708. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
195709. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
195710. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
195711. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
195712. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
195713. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
195714. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
195715. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
195716. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
195717. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
195718. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
195719. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
195720. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
195721. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
195722. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
195723. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
195724. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
195725. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
195726. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
195727. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
195728. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
195729. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
195730. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
195731. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
195732. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
195733. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
195734. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
195735. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
195736. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
195737. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
195738. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
195739. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
195740. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
195741. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
195742. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
195743. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
195744. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
195745. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
195746. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
195747. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
195748. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
195749. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
195750. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
195751. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
195752. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
195753. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
195754. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
195755. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
195756. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
195757. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
195758. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
195759. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
195760. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
195761. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
195762. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
195763. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
195764. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
195765. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
195766. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
195767. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
195768. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
195769. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
195770. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
195771. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
195772. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
195773. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
195774. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
195775. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
195776. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
195777. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
195778. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
195779. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
195780. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK
195781. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
195782. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
195783. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
195784. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
195785. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
195786. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
195787. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
195788. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
195789. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
195790. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
195791. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
195792. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
195793. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
195794. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
195795. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
195796. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
195797. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
195798. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
195799. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
195800. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
195801. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
195802. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
195803. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
195804. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
195805. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
195806. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
195807. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
195808. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
195809. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
195810. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
195811. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
195812. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
195813. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
195814. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
195815. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
195816. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
195817. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
195818. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
195819. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
195820. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
195821. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
195822. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
195823. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
195824. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
195825. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
195826. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
195827. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
195828. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
195829. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
195830. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
195831. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
195832. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
195833. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
195834. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
195835. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
195836. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
195837. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
195838. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
195839. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
195840. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
195841. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
195842. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
195843. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
195844. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
195845. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
195846. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
195847. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
195848. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
195849. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
195850. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
195851. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
195852. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
195853. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
195854. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
195855. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
195856. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
195857. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
195858. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
195859. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
195860. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
195861. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
195862. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
195863. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
195864. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
195865. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
195866. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
195867. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
195868. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
195869. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
195870. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
195871. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
195872. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
195873. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
195874. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
195875. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
195876. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
195877. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
195878. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
195879. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
195880. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
195881. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
195882. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
195883. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
195884. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
195885. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
195886. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
195887. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
195888. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
195889. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
195890. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
195891. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
195892. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
195893. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
195894. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
195895. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
195896. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
195897. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
195898. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
195899. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
195900. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
195901. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
195902. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
195903. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
195904. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
195905. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
195906. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
195907. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
195908. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
195909. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
195910. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
195911. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
195912. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
195913. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
195914. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
195915. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
195916. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
195917. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
195918. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
195919. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
195920. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
195921. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
195922. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
195923. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
195924. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
195925. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
195926. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
195927. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
195928. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
195929. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
195930. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
195931. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
195932. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
195933. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
195934. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
195935. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
195936. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
195937. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
195938. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
195939. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
195940. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
195941. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
195942. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
195943. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
195944. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
195945. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
195946. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
195947. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
195948. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
195949. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
195950. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
195951. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
195952. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
195953. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
195954. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
195955. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
195956. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
195957. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
195958. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
195959. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
195960. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
195961. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
195962. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
195963. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
195964. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
195965. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
195966. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
195967. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
195968. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
195969. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
195970. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
195971. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
195972. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
195973. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
195974. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
195975. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
195976. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
195977. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
195978. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
195979. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
195980. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
195981. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
195982. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
195983. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
195984. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
195985. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
195986. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
195987. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
195988. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
195989. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
195990. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
195991. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
195992. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
195993. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
195994. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
195995. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
195996. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
195997. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
195998. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
195999. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
196000. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
196001. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
196002. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
196003. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
196004. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
196005. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
196006. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
196007. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
196008. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
196009. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
196010. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
196011. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
196012. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
196013. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
196014. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
196015. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
196016. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
196017. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
196018. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
196019. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
196020. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
196021. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
196022. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
196023. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
196024. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
196025. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
196026. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
196027. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
196028. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
196029. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
196030. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
196031. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
196032. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
196033. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
196034. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
196035. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
196036. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
196037. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
196038. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
196039. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
196040. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
196041. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
196042. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
196043. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
196044. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
196045. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
196046. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
196047. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
196048. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
196049. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
196050. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
196051. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
196052. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
196053. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
196054. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
196055. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
196056. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
196057. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
196058. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
196059. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
196060. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
196061. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
196062. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
196063. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
196064. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
196065. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
196066. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
196067. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
196068. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
196069. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
196070. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
196071. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
196072. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
196073. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
196074. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
196075. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
196076. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
196077. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
196078. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
196079. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
196080. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
196081. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
196082. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
196083. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
196084. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
196085. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
196086. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
196087. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
196088. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
196089. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
196090. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
196091. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
196092. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
196093. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
196094. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
196095. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
196096. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
196097. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
196098. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
196099. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
196100. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
196101. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
196102. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
196103. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
196104. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
196105. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
196106. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
196107. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
196108. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
196109. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
196110. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
196111. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
196112. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
196113. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
196114. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
196115. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
196116. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
196117. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
196118. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
196119. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
196120. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
196121. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
196122. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
196123. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
196124. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
196125. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
196126. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
196127. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
196128. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
196129. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
196130. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
196131. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
196132. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
196133. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
196134. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
196135. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
196136. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
196137. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
196138. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
196139. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
196140. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
196141. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
196142. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
196143. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
196144. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
196145. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
196146. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
196147. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
196148. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
196149. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
196150. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
196151. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
196152. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
196153. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
196154. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
196155. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
196156. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
196157. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
196158. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
196159. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
196160. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
196161. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
196162. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
196163. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
196164. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
196165. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
196166. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
196167. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
196168. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
196169. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
196170. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
196171. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
196172. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
196173. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
196174. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
196175. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
196176. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
196177. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
196178. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
196179. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
196180. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
196181. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
196182. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
196183. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
196184. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
196185. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
196186. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
196187. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
196188. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
196189. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
196190. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
196191. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
196192. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
196193. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
196194. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
196195. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
196196. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
196197. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
196198. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
196199. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
196200. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
196201. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
196202. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
196203. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
196204. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
196205. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
196206. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
196207. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
196208. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
196209. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
196210. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
196211. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
196212. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
196213. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
196214. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
196215. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
196216. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
196217. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
196218. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
196219. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
196220. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
196221. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
196222. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
196223. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
196224. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
196225. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
196226. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
196227. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
196228. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
196229. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
196230. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
196231. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
196232. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
196233. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
196234. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
196235. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
196236. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
196237. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
196238. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
196239. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
196240. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
196241. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
196242. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
196243. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
196244. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
196245. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
196246. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
196247. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
196248. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
196249. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
196250. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
196251. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
196252. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
196253. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
196254. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
196255. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
196256. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
196257. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
196258. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
196259. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
196260. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
196261. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
196262. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
196263. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
196264. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
196265. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
196266. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
196267. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
196268. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
196269. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
196270. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
196271. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
196272. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
196273. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
196274. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
196275. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
196276. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
196277. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
196278. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
196279. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
196280. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
196281. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
196282. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
196283. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
196284. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
196285. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
196286. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
196287. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
196288. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
196289. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
196290. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
196291. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
196292. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
196293. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
196294. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
196295. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
196296. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
196297. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
196298. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
196299. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
196300. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
196301. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
196302. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
196303. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
196304. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
196305. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
196306. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
196307. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
196308. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
196309. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
196310. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
196311. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
196312. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
196313. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
196314. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
196315. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
196316. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
196317. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
196318. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
196319. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
196320. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
196321. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
196322. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
196323. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
196324. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
196325. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
196326. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
196327. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
196328. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
196329. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
196330. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
196331. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
196332. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
196333. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
196334. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
196335. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
196336. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK
196337. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT
196338. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK
196339. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT
196340. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
196341. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
196342. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK
196343. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT
196344. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK
196345. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT
196346. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK
196347. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT
196348. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
196349. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
196350. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
196351. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
196352. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
196353. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
196354. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
196355. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
196356. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
196357. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
196358. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
196359. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
196360. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
196361. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
196362. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
196363. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
196364. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
196365. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
196366. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
196367. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
196368. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
196369. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
196370. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
196371. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
196372. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
196373. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
196374. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
196375. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
196376. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
196377. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
196378. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
196379. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
196380. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
196381. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
196382. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
196383. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
196384. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
196385. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
196386. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
196387. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
196388. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
196389. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
196390. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
196391. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
196392. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
196393. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
196394. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
196395. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
196396. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
196397. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
196398. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
196399. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
196400. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
196401. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
196402. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
196403. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
196404. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
196405. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
196406. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
196407. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
196408. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
196409. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
196410. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
196411. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
196412. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
196413. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
196414. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
196415. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
196416. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
196417. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
196418. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
196419. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
196420. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
196421. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
196422. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
196423. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
196424. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
196425. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
196426. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
196427. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
196428. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
196429. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
196430. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
196431. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
196432. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
196433. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
196434. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
196435. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
196436. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
196437. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
196438. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
196439. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
196440. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
196441. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
196442. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
196443. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
196444. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
196445. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
196446. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
196447. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
196448. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
196449. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
196450. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
196451. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
196452. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
196453. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
196454. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
196455. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
196456. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
196457. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
196458. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
196459. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
196460. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
196461. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
196462. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
196463. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
196464. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
196465. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
196466. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
196467. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
196468. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
196469. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
196470. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
196471. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
196472. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
196473. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
196474. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
196475. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
196476. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
196477. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
196478. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
196479. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
196480. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
196481. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
196482. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
196483. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
196484. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
196485. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
196486. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
196487. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
196488. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
196489. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
196490. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
196491. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
196492. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
196493. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
196494. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
196495. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
196496. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
196497. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
196498. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
196499. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
196500. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
196501. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
196502. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
196503. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
196504. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
196505. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
196506. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
196507. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
196508. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
196509. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
196510. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
196511. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
196512. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
196513. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
196514. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
196515. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
196516. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
196517. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
196518. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
196519. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
196520. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
196521. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
196522. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
196523. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
196524. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
196525. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
196526. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
196527. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
196528. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
196529. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
196530. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
196531. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
196532. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
196533. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
196534. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
196535. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
196536. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
196537. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
196538. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
196539. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
196540. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
196541. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
196542. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
196543. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
196544. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
196545. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
196546. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
196547. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
196548. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
196549. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
196550. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
196551. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
196552. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
196553. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
196554. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
196555. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
196556. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
196557. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
196558. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
196559. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
196560. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
196561. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
196562. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
196563. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
196564. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
196565. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
196566. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
196567. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
196568. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
196569. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
196570. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
196571. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
196572. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
196573. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
196574. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
196575. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
196576. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
196577. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
196578. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
196579. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
196580. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
196581. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
196582. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
196583. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
196584. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
196585. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
196586. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
196587. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
196588. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
196589. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
196590. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
196591. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
196592. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
196593. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
196594. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
196595. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
196596. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
196597. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
196598. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
196599. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
196600. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
196601. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
196602. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
196603. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
196604. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
196605. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
196606. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
196607. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
196608. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
196609. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
196610. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
196611. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
196612. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
196613. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
196614. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
196615. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
196616. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
196617. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
196618. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
196619. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
196620. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
196621. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
196622. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
196623. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
196624. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
196625. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
196626. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
196627. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
196628. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
196629. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
196630. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
196631. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
196632. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
196633. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
196634. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
196635. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
196636. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
196637. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
196638. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
196639. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
196640. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
196641. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
196642. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
196643. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
196644. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
196645. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
196646. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
196647. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
196648. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
196649. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
196650. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
196651. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
196652. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
196653. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
196654. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
196655. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
196656. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
196657. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
196658. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
196659. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
196660. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
196661. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
196662. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
196663. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
196664. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
196665. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
196666. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
196667. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
196668. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
196669. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
196670. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
196671. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
196672. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
196673. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
196674. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
196675. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
196676. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
196677. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
196678. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
196679. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
196680. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
196681. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
196682. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
196683. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
196684. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
196685. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
196686. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
196687. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
196688. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
196689. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
196690. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK
196691. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT
196692. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK
196693. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT
196694. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
196695. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
196696. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
196697. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
196698. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
196699. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
196700. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
196701. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
196702. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
196703. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
196704. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
196705. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
196706. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
196707. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
196708. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
196709. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
196710. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
196711. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
196712. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
196713. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
196714. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
196715. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
196716. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
196717. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
196718. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
196719. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
196720. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
196721. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
196722. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
196723. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
196724. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
196725. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
196726. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
196727. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
196728. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
196729. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
196730. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
196731. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
196732. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
196733. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
196734. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
196735. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
196736. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
196737. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
196738. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
196739. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
196740. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
196741. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
196742. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
196743. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
196744. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
196745. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
196746. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
196747. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
196748. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
196749. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
196750. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
196751. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
196752. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
196753. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
196754. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
196755. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
196756. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
196757. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
196758. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
196759. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
196760. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
196761. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
196762. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
196763. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
196764. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
196765. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
196766. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
196767. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
196768. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
196769. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
196770. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
196771. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
196772. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
196773. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
196774. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
196775. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
196776. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
196777. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
196778. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
196779. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
196780. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
196781. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
196782. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
196783. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
196784. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
196785. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
196786. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
196787. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
196788. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
196789. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
196790. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
196791. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
196792. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
196793. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
196794. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
196795. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
196796. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
196797. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
196798. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
196799. DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
196800. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
196801. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
196802. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
196803. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
196804. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
196805. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
196806. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
196807. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
196808. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
196809. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
196810. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK
196811. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT
196812. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
196813. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
196814. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
196815. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
196816. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
196817. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
196818. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
196819. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
196820. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
196821. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
196822. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
196823. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
196824. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
196825. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
196826. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
196827. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
196828. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
196829. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
196830. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
196831. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
196832. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
196833. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
196834. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
196835. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
196836. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
196837. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
196838. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
196839. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
196840. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
196841. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
196842. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK
196843. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
196844. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK
196845. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
196846. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK
196847. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
196848. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
196849. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
196850. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
196851. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
196852. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
196853. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
196854. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
196855. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
196856. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
196857. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
196858. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
196859. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
196860. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
196861. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
196862. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
196863. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
196864. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
196865. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
196866. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
196867. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
196868. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
196869. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
196870. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
196871. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
196872. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
196873. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
196874. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
196875. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
196876. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
196877. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
196878. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
196879. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
196880. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
196881. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
196882. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
196883. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
196884. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
196885. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
196886. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
196887. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
196888. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK
196889. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
196890. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK
196891. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
196892. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
196893. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
196894. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
196895. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
196896. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
196897. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
196898. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
196899. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
196900. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK
196901. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
196902. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
196903. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
196904. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
196905. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
196906. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
196907. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
196908. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
196909. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
196910. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
196911. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
196912. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__NC32_MASK
196913. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT
196914. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
196915. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
196916. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
196917. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
196918. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
196919. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
196920. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
196921. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
196922. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
196923. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
196924. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK
196925. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
196926. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
196927. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
196928. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
196929. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
196930. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
196931. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
196932. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
196933. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
196934. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
196935. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
196936. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK
196937. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
196938. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
196939. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
196940. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
196941. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
196942. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
196943. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
196944. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
196945. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
196946. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK
196947. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT
196948. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
196949. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
196950. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
196951. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
196952. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
196953. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
196954. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
196955. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
196956. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
196957. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
196958. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
196959. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
196960. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
196961. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
196962. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
196963. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
196964. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
196965. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
196966. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
196967. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
196968. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__NC20_MASK
196969. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__NC20__SHIFT
196970. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK
196971. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT
196972. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
196973. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
196974. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
196975. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
196976. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
196977. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
196978. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK
196979. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
196980. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK
196981. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
196982. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
196983. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
196984. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK
196985. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
196986. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK
196987. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
196988. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK
196989. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT
196990. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
196991. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
196992. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK
196993. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT
196994. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK
196995. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT
196996. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
196997. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
196998. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK
196999. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT
197000. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_gd_MASK
197001. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_gd__SHIFT
197002. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccm_MASK
197003. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT
197004. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccp_MASK
197005. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT
197006. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vptx_MASK
197007. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT
197008. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg0_MASK
197009. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT
197010. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg1_MASK
197011. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT
197012. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK
197013. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT
197014. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__override_regref_0_MASK
197015. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT
197016. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK
197017. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT
197018. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_nbias_MASK
197019. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT
197020. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_pbias_MASK
197021. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT
197022. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK
197023. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT
197024. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfm_MASK
197025. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT
197026. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfp_MASK
197027. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT
197028. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsm_MASK
197029. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT
197030. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsp_MASK
197031. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT
197032. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_vcm_MASK
197033. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT
197034. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
197035. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
197036. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK
197037. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
197038. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
197039. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
197040. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
197041. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
197042. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
197043. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
197044. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
197045. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
197046. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK
197047. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT
197048. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK
197049. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
197050. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__nc_MASK
197051. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__nc__SHIFT
197052. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_nmos_MASK
197053. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_nmos__SHIFT
197054. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_pmos_MASK
197055. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_pmos__SHIFT
197056. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__override_rxdetref_MASK
197057. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT
197058. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
197059. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
197060. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
197061. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
197062. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
197063. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
197064. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
197065. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
197066. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK
197067. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
197068. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
197069. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
197070. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
197071. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
197072. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
197073. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
197074. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
197075. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
197076. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
197077. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
197078. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
197079. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
197080. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
197081. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
197082. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
197083. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
197084. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
197085. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
197086. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
197087. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
197088. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
197089. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
197090. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
197091. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
197092. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
197093. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
197094. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
197095. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
197096. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
197097. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
197098. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK
197099. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
197100. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK
197101. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
197102. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
197103. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
197104. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK
197105. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
197106. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
197107. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
197108. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
197109. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
197110. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK
197111. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
197112. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
197113. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
197114. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
197115. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
197116. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
197117. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
197118. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
197119. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
197120. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
197121. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
197122. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
197123. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
197124. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK
197125. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
197126. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK
197127. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT
197128. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_MASK
197129. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT
197130. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK
197131. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
197132. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
197133. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
197134. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK
197135. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
197136. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK
197137. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
197138. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK
197139. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
197140. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK
197141. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT
197142. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
197143. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
197144. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
197145. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
197146. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
197147. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
197148. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
197149. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
197150. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
197151. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
197152. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
197153. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
197154. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
197155. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
197156. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
197157. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
197158. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
197159. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
197160. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
197161. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
197162. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
197163. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
197164. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
197165. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
197166. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
197167. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
197168. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
197169. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
197170. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
197171. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
197172. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
197173. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
197174. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
197175. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
197176. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
197177. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
197178. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
197179. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
197180. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
197181. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
197182. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
197183. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
197184. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
197185. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
197186. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
197187. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
197188. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
197189. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
197190. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
197191. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
197192. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
197193. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
197194. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
197195. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
197196. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
197197. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
197198. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
197199. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
197200. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
197201. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
197202. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
197203. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
197204. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
197205. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
197206. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
197207. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
197208. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
197209. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
197210. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
197211. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
197212. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
197213. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
197214. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
197215. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
197216. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
197217. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
197218. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
197219. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
197220. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
197221. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
197222. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
197223. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
197224. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
197225. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
197226. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
197227. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
197228. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
197229. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
197230. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
197231. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
197232. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
197233. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
197234. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
197235. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
197236. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
197237. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
197238. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
197239. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
197240. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
197241. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
197242. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
197243. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
197244. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
197245. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
197246. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
197247. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
197248. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
197249. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
197250. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
197251. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
197252. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
197253. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
197254. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
197255. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
197256. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
197257. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
197258. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
197259. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
197260. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
197261. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
197262. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
197263. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
197264. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
197265. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
197266. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
197267. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
197268. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
197269. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
197270. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
197271. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
197272. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
197273. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
197274. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
197275. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
197276. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
197277. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
197278. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
197279. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
197280. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
197281. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
197282. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
197283. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
197284. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
197285. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
197286. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
197287. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
197288. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
197289. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
197290. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
197291. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
197292. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
197293. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
197294. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
197295. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
197296. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
197297. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
197298. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
197299. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
197300. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
197301. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
197302. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
197303. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
197304. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
197305. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
197306. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
197307. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
197308. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
197309. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
197310. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
197311. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
197312. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
197313. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
197314. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
197315. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
197316. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
197317. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
197318. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
197319. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
197320. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
197321. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
197322. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
197323. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
197324. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
197325. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
197326. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
197327. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
197328. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
197329. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
197330. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
197331. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
197332. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
197333. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
197334. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
197335. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
197336. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
197337. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
197338. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
197339. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
197340. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
197341. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
197342. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
197343. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
197344. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
197345. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
197346. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
197347. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
197348. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
197349. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
197350. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
197351. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
197352. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
197353. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
197354. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
197355. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
197356. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
197357. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
197358. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
197359. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
197360. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
197361. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
197362. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
197363. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
197364. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
197365. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
197366. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
197367. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
197368. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
197369. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
197370. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
197371. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
197372. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
197373. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
197374. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
197375. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
197376. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
197377. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
197378. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
197379. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
197380. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
197381. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
197382. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
197383. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
197384. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
197385. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
197386. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK
197387. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
197388. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
197389. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
197390. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
197391. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
197392. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
197393. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
197394. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
197395. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
197396. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
197397. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
197398. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
197399. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
197400. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
197401. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
197402. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
197403. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
197404. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
197405. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
197406. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
197407. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
197408. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
197409. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
197410. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
197411. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
197412. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
197413. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
197414. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
197415. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
197416. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
197417. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
197418. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
197419. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
197420. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
197421. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
197422. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
197423. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
197424. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
197425. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
197426. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
197427. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
197428. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
197429. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
197430. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
197431. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
197432. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
197433. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
197434. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
197435. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
197436. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
197437. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
197438. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
197439. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
197440. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
197441. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
197442. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
197443. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
197444. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
197445. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
197446. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
197447. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
197448. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
197449. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
197450. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
197451. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
197452. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
197453. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
197454. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
197455. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
197456. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
197457. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
197458. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
197459. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
197460. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
197461. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
197462. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
197463. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
197464. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
197465. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
197466. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
197467. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
197468. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
197469. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
197470. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
197471. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
197472. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
197473. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
197474. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
197475. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
197476. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
197477. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
197478. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
197479. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
197480. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
197481. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
197482. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
197483. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
197484. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
197485. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
197486. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
197487. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
197488. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
197489. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
197490. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
197491. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
197492. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
197493. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
197494. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
197495. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
197496. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
197497. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
197498. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
197499. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
197500. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
197501. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
197502. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
197503. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
197504. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
197505. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
197506. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
197507. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
197508. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
197509. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
197510. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
197511. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
197512. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
197513. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
197514. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
197515. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
197516. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
197517. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
197518. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
197519. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
197520. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
197521. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
197522. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
197523. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
197524. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
197525. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
197526. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
197527. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
197528. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
197529. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
197530. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
197531. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
197532. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
197533. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
197534. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
197535. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
197536. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
197537. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
197538. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
197539. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
197540. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
197541. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
197542. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
197543. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
197544. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
197545. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
197546. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
197547. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
197548. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
197549. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
197550. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
197551. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
197552. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
197553. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
197554. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
197555. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
197556. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
197557. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
197558. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
197559. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
197560. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
197561. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
197562. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
197563. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
197564. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
197565. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
197566. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
197567. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
197568. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
197569. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
197570. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
197571. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
197572. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
197573. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
197574. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
197575. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
197576. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
197577. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
197578. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
197579. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
197580. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
197581. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
197582. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
197583. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
197584. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
197585. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
197586. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
197587. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
197588. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
197589. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
197590. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
197591. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
197592. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
197593. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
197594. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
197595. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
197596. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
197597. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
197598. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
197599. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
197600. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
197601. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
197602. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
197603. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
197604. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
197605. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
197606. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
197607. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
197608. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
197609. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
197610. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
197611. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
197612. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
197613. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
197614. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
197615. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
197616. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
197617. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
197618. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
197619. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
197620. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
197621. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
197622. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
197623. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
197624. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
197625. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
197626. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
197627. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
197628. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
197629. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
197630. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
197631. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
197632. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
197633. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
197634. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
197635. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
197636. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
197637. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
197638. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
197639. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
197640. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
197641. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
197642. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
197643. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
197644. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
197645. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
197646. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
197647. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
197648. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
197649. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
197650. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
197651. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
197652. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
197653. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
197654. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
197655. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
197656. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
197657. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
197658. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
197659. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
197660. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
197661. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
197662. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
197663. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
197664. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
197665. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
197666. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
197667. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
197668. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
197669. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
197670. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
197671. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
197672. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
197673. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
197674. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
197675. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
197676. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
197677. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
197678. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
197679. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
197680. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
197681. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
197682. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
197683. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
197684. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
197685. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
197686. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
197687. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
197688. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
197689. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
197690. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
197691. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
197692. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
197693. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
197694. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
197695. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
197696. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
197697. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
197698. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
197699. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
197700. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
197701. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
197702. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
197703. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
197704. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
197705. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
197706. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
197707. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
197708. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
197709. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
197710. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
197711. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
197712. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
197713. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
197714. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
197715. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
197716. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
197717. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
197718. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
197719. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
197720. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
197721. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
197722. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
197723. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
197724. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
197725. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
197726. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
197727. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
197728. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
197729. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
197730. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
197731. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
197732. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
197733. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
197734. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
197735. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
197736. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
197737. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
197738. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
197739. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
197740. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
197741. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
197742. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
197743. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
197744. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
197745. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
197746. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
197747. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
197748. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
197749. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
197750. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
197751. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
197752. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
197753. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
197754. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
197755. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
197756. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
197757. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
197758. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
197759. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
197760. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
197761. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
197762. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
197763. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
197764. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
197765. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
197766. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
197767. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
197768. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
197769. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
197770. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
197771. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
197772. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
197773. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
197774. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
197775. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
197776. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
197777. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
197778. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
197779. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
197780. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
197781. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
197782. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
197783. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
197784. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
197785. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
197786. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
197787. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
197788. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
197789. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
197790. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
197791. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
197792. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
197793. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
197794. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
197795. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
197796. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
197797. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
197798. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
197799. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
197800. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
197801. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
197802. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
197803. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
197804. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
197805. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
197806. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
197807. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
197808. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
197809. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
197810. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
197811. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
197812. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
197813. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
197814. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
197815. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
197816. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
197817. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
197818. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
197819. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
197820. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
197821. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
197822. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
197823. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
197824. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
197825. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
197826. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
197827. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
197828. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
197829. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
197830. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
197831. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
197832. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
197833. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
197834. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
197835. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
197836. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
197837. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
197838. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
197839. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
197840. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
197841. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
197842. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
197843. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
197844. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
197845. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
197846. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
197847. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
197848. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
197849. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
197850. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
197851. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
197852. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
197853. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
197854. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
197855. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
197856. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
197857. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
197858. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
197859. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
197860. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
197861. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
197862. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
197863. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
197864. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
197865. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
197866. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
197867. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
197868. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
197869. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
197870. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
197871. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
197872. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
197873. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
197874. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
197875. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
197876. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
197877. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
197878. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
197879. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
197880. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
197881. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
197882. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
197883. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
197884. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
197885. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
197886. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
197887. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
197888. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
197889. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
197890. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
197891. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
197892. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
197893. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
197894. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
197895. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
197896. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
197897. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
197898. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
197899. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
197900. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
197901. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
197902. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
197903. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
197904. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
197905. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
197906. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
197907. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
197908. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
197909. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
197910. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
197911. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
197912. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
197913. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
197914. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
197915. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
197916. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
197917. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
197918. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
197919. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
197920. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
197921. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
197922. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
197923. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
197924. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
197925. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
197926. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
197927. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
197928. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
197929. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
197930. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
197931. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
197932. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
197933. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
197934. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
197935. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
197936. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
197937. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
197938. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
197939. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
197940. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
197941. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
197942. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK
197943. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT
197944. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK
197945. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT
197946. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
197947. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
197948. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK
197949. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT
197950. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK
197951. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT
197952. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK
197953. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT
197954. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
197955. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
197956. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
197957. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
197958. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
197959. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
197960. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
197961. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
197962. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
197963. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
197964. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
197965. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
197966. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
197967. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
197968. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
197969. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
197970. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
197971. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
197972. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
197973. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
197974. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
197975. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
197976. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
197977. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
197978. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
197979. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
197980. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
197981. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
197982. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
197983. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
197984. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
197985. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
197986. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
197987. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
197988. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
197989. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
197990. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
197991. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
197992. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
197993. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
197994. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
197995. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
197996. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
197997. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
197998. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
197999. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
198000. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
198001. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
198002. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
198003. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
198004. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
198005. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
198006. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
198007. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
198008. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
198009. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
198010. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
198011. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
198012. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
198013. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
198014. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
198015. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
198016. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
198017. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
198018. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
198019. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
198020. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
198021. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
198022. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
198023. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
198024. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
198025. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
198026. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
198027. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
198028. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
198029. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
198030. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
198031. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
198032. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
198033. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
198034. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
198035. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
198036. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
198037. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
198038. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
198039. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
198040. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
198041. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
198042. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
198043. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
198044. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
198045. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
198046. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
198047. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
198048. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
198049. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
198050. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
198051. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
198052. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
198053. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
198054. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
198055. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
198056. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
198057. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
198058. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
198059. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
198060. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
198061. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
198062. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
198063. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
198064. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
198065. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
198066. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
198067. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
198068. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
198069. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
198070. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
198071. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
198072. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
198073. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
198074. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
198075. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
198076. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
198077. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
198078. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
198079. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
198080. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
198081. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
198082. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
198083. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
198084. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
198085. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
198086. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
198087. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
198088. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
198089. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
198090. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
198091. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
198092. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
198093. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
198094. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
198095. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
198096. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
198097. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
198098. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
198099. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
198100. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
198101. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
198102. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
198103. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
198104. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
198105. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
198106. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
198107. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
198108. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
198109. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
198110. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
198111. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
198112. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
198113. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
198114. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
198115. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
198116. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
198117. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
198118. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
198119. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
198120. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
198121. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
198122. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
198123. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
198124. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
198125. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
198126. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
198127. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
198128. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
198129. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
198130. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
198131. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
198132. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
198133. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
198134. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
198135. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
198136. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
198137. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
198138. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
198139. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
198140. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
198141. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
198142. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
198143. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
198144. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
198145. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
198146. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
198147. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
198148. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
198149. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
198150. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
198151. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
198152. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
198153. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
198154. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
198155. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
198156. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
198157. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
198158. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
198159. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
198160. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
198161. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
198162. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
198163. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
198164. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
198165. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
198166. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
198167. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
198168. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
198169. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
198170. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
198171. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
198172. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
198173. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
198174. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
198175. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
198176. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
198177. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
198178. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
198179. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
198180. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
198181. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
198182. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
198183. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
198184. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
198185. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
198186. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
198187. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
198188. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
198189. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
198190. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
198191. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
198192. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
198193. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
198194. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
198195. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
198196. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
198197. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
198198. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
198199. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
198200. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
198201. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
198202. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
198203. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
198204. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
198205. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
198206. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
198207. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
198208. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
198209. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
198210. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
198211. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
198212. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
198213. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
198214. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
198215. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
198216. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
198217. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
198218. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
198219. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
198220. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
198221. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
198222. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
198223. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
198224. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
198225. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
198226. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
198227. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
198228. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
198229. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
198230. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
198231. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
198232. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
198233. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
198234. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
198235. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
198236. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
198237. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
198238. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
198239. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
198240. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
198241. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
198242. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
198243. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
198244. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
198245. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
198246. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
198247. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
198248. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
198249. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
198250. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
198251. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
198252. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
198253. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
198254. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
198255. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
198256. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
198257. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
198258. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
198259. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
198260. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
198261. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
198262. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
198263. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
198264. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
198265. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
198266. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
198267. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
198268. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
198269. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
198270. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
198271. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
198272. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
198273. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
198274. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
198275. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
198276. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
198277. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
198278. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
198279. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
198280. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
198281. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
198282. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
198283. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
198284. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
198285. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
198286. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
198287. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
198288. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
198289. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
198290. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
198291. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
198292. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
198293. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
198294. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
198295. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
198296. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK
198297. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT
198298. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK
198299. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT
198300. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
198301. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
198302. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
198303. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
198304. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
198305. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
198306. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
198307. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
198308. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
198309. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
198310. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
198311. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
198312. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
198313. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
198314. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
198315. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
198316. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
198317. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
198318. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
198319. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
198320. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
198321. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
198322. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
198323. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
198324. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
198325. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
198326. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
198327. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
198328. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
198329. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
198330. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
198331. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
198332. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
198333. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
198334. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
198335. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
198336. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
198337. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
198338. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
198339. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
198340. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
198341. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
198342. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
198343. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
198344. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
198345. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
198346. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
198347. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
198348. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
198349. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
198350. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
198351. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
198352. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
198353. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
198354. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
198355. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
198356. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
198357. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
198358. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
198359. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
198360. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
198361. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
198362. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
198363. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
198364. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
198365. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
198366. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
198367. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
198368. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
198369. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
198370. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
198371. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
198372. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
198373. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
198374. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
198375. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
198376. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
198377. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
198378. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
198379. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
198380. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
198381. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
198382. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
198383. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
198384. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
198385. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
198386. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
198387. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
198388. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
198389. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
198390. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
198391. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
198392. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
198393. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
198394. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
198395. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
198396. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
198397. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
198398. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
198399. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
198400. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
198401. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
198402. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
198403. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
198404. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
198405. DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
198406. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
198407. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
198408. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
198409. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
198410. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
198411. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
198412. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
198413. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
198414. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
198415. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
198416. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK
198417. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT
198418. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
198419. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
198420. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
198421. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
198422. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
198423. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
198424. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
198425. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
198426. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
198427. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
198428. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
198429. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
198430. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
198431. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
198432. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
198433. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
198434. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
198435. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
198436. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
198437. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
198438. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
198439. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
198440. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
198441. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
198442. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
198443. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
198444. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
198445. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
198446. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
198447. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
198448. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK
198449. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
198450. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK
198451. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
198452. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK
198453. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
198454. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
198455. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
198456. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
198457. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
198458. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
198459. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
198460. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
198461. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
198462. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
198463. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
198464. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
198465. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
198466. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
198467. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
198468. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
198469. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
198470. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
198471. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
198472. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
198473. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
198474. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
198475. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
198476. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
198477. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
198478. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
198479. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
198480. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
198481. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
198482. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
198483. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
198484. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
198485. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
198486. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
198487. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
198488. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
198489. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
198490. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
198491. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
198492. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
198493. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
198494. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK
198495. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
198496. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK
198497. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
198498. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
198499. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
198500. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
198501. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
198502. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
198503. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
198504. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
198505. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
198506. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK
198507. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
198508. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
198509. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
198510. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
198511. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
198512. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
198513. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
198514. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
198515. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
198516. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
198517. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
198518. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__NC32_MASK
198519. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT
198520. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
198521. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
198522. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
198523. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
198524. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
198525. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
198526. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
198527. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
198528. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
198529. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
198530. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK
198531. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
198532. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
198533. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
198534. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
198535. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
198536. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
198537. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
198538. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
198539. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
198540. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
198541. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
198542. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK
198543. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
198544. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
198545. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
198546. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
198547. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
198548. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
198549. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
198550. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
198551. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
198552. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK
198553. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT
198554. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
198555. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
198556. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
198557. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
198558. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
198559. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
198560. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
198561. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
198562. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
198563. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
198564. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
198565. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
198566. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
198567. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
198568. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
198569. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
198570. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
198571. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
198572. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
198573. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
198574. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__NC20_MASK
198575. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__NC20__SHIFT
198576. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK
198577. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT
198578. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
198579. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
198580. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
198581. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
198582. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
198583. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
198584. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK
198585. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
198586. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK
198587. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
198588. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
198589. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
198590. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK
198591. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
198592. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK
198593. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
198594. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK
198595. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT
198596. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
198597. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
198598. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK
198599. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT
198600. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK
198601. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT
198602. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
198603. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
198604. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK
198605. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT
198606. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_gd_MASK
198607. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_gd__SHIFT
198608. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccm_MASK
198609. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT
198610. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccp_MASK
198611. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT
198612. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vptx_MASK
198613. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT
198614. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg0_MASK
198615. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT
198616. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg1_MASK
198617. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT
198618. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK
198619. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT
198620. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__override_regref_0_MASK
198621. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT
198622. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK
198623. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT
198624. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_nbias_MASK
198625. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT
198626. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_pbias_MASK
198627. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT
198628. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK
198629. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT
198630. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfm_MASK
198631. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT
198632. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfp_MASK
198633. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT
198634. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsm_MASK
198635. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT
198636. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsp_MASK
198637. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT
198638. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_vcm_MASK
198639. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT
198640. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
198641. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
198642. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK
198643. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
198644. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
198645. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
198646. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
198647. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
198648. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
198649. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
198650. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
198651. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
198652. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK
198653. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT
198654. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK
198655. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
198656. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__nc_MASK
198657. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__nc__SHIFT
198658. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_nmos_MASK
198659. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_nmos__SHIFT
198660. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_pmos_MASK
198661. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_pmos__SHIFT
198662. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__override_rxdetref_MASK
198663. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT
198664. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
198665. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
198666. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
198667. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
198668. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
198669. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
198670. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
198671. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
198672. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK
198673. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
198674. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
198675. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
198676. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
198677. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
198678. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
198679. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
198680. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
198681. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
198682. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
198683. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
198684. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
198685. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
198686. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
198687. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
198688. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
198689. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
198690. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
198691. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
198692. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
198693. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
198694. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
198695. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
198696. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
198697. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
198698. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
198699. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
198700. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
198701. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
198702. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
198703. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
198704. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK
198705. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
198706. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK
198707. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
198708. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
198709. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
198710. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK
198711. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
198712. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
198713. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
198714. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
198715. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
198716. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK
198717. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
198718. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
198719. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
198720. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
198721. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
198722. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
198723. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
198724. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
198725. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
198726. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
198727. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
198728. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
198729. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
198730. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK
198731. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
198732. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK
198733. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT
198734. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_MASK
198735. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT
198736. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK
198737. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
198738. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
198739. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
198740. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK
198741. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
198742. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK
198743. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
198744. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK
198745. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
198746. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK
198747. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT
198748. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
198749. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
198750. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
198751. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
198752. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
198753. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
198754. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
198755. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
198756. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
198757. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
198758. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
198759. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
198760. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
198761. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
198762. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
198763. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
198764. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
198765. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
198766. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
198767. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
198768. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
198769. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
198770. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
198771. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
198772. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
198773. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
198774. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
198775. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
198776. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
198777. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
198778. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
198779. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
198780. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
198781. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
198782. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
198783. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
198784. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
198785. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
198786. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
198787. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
198788. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
198789. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
198790. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
198791. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
198792. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
198793. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
198794. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
198795. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
198796. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
198797. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
198798. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
198799. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
198800. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
198801. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
198802. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
198803. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
198804. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
198805. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
198806. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
198807. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
198808. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
198809. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
198810. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
198811. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
198812. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
198813. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
198814. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
198815. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
198816. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
198817. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
198818. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
198819. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
198820. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
198821. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
198822. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
198823. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
198824. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
198825. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
198826. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
198827. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
198828. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
198829. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
198830. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
198831. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
198832. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
198833. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
198834. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
198835. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
198836. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
198837. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
198838. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
198839. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
198840. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
198841. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
198842. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
198843. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
198844. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
198845. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
198846. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
198847. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
198848. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
198849. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
198850. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
198851. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
198852. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
198853. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
198854. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
198855. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
198856. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
198857. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
198858. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
198859. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
198860. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
198861. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
198862. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
198863. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
198864. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
198865. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
198866. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
198867. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
198868. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
198869. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
198870. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
198871. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
198872. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
198873. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
198874. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
198875. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
198876. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
198877. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
198878. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
198879. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
198880. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
198881. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
198882. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
198883. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
198884. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
198885. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
198886. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
198887. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
198888. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
198889. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
198890. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
198891. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
198892. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
198893. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
198894. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
198895. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
198896. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
198897. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
198898. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
198899. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
198900. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
198901. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
198902. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
198903. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
198904. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
198905. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
198906. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
198907. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
198908. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
198909. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
198910. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
198911. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
198912. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
198913. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
198914. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
198915. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
198916. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
198917. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
198918. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
198919. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
198920. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
198921. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
198922. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
198923. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
198924. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
198925. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
198926. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
198927. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
198928. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
198929. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
198930. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
198931. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
198932. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
198933. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
198934. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
198935. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
198936. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
198937. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
198938. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
198939. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
198940. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
198941. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
198942. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
198943. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
198944. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
198945. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
198946. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
198947. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
198948. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
198949. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
198950. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
198951. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
198952. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
198953. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
198954. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
198955. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
198956. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
198957. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
198958. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
198959. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
198960. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
198961. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
198962. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
198963. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
198964. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
198965. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
198966. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
198967. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
198968. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
198969. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
198970. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
198971. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
198972. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
198973. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
198974. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
198975. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
198976. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
198977. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
198978. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
198979. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
198980. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
198981. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
198982. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
198983. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
198984. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
198985. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
198986. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
198987. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
198988. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
198989. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
198990. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
198991. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
198992. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK
198993. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
198994. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
198995. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
198996. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
198997. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
198998. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
198999. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
199000. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
199001. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
199002. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
199003. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
199004. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
199005. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
199006. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
199007. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
199008. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
199009. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
199010. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
199011. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
199012. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
199013. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
199014. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
199015. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
199016. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
199017. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
199018. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
199019. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
199020. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
199021. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
199022. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
199023. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
199024. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
199025. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
199026. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
199027. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
199028. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
199029. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
199030. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
199031. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
199032. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
199033. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
199034. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
199035. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
199036. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
199037. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
199038. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
199039. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
199040. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
199041. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
199042. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
199043. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
199044. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
199045. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
199046. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
199047. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
199048. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
199049. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
199050. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
199051. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
199052. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
199053. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
199054. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
199055. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
199056. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
199057. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
199058. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
199059. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
199060. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
199061. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
199062. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
199063. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
199064. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
199065. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
199066. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
199067. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
199068. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
199069. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
199070. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
199071. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
199072. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
199073. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
199074. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
199075. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
199076. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
199077. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
199078. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
199079. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
199080. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
199081. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
199082. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
199083. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
199084. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
199085. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
199086. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
199087. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
199088. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
199089. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
199090. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
199091. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
199092. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
199093. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
199094. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
199095. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
199096. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
199097. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
199098. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
199099. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
199100. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
199101. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
199102. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
199103. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
199104. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
199105. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
199106. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
199107. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
199108. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
199109. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
199110. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
199111. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
199112. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
199113. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
199114. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
199115. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
199116. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
199117. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
199118. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
199119. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
199120. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
199121. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
199122. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
199123. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
199124. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
199125. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
199126. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
199127. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
199128. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
199129. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
199130. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
199131. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
199132. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
199133. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
199134. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
199135. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
199136. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
199137. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
199138. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
199139. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
199140. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
199141. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
199142. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
199143. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
199144. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
199145. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
199146. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
199147. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
199148. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
199149. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
199150. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
199151. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
199152. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
199153. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
199154. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
199155. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
199156. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
199157. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
199158. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
199159. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
199160. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
199161. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
199162. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
199163. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
199164. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
199165. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
199166. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
199167. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
199168. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
199169. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
199170. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
199171. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
199172. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
199173. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
199174. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
199175. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
199176. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
199177. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
199178. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
199179. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
199180. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
199181. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
199182. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
199183. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
199184. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
199185. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
199186. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
199187. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
199188. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
199189. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
199190. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
199191. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
199192. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
199193. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
199194. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
199195. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
199196. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
199197. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
199198. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
199199. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
199200. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
199201. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
199202. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
199203. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
199204. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
199205. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
199206. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
199207. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
199208. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
199209. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
199210. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
199211. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
199212. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
199213. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
199214. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
199215. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
199216. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
199217. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
199218. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
199219. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
199220. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
199221. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
199222. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
199223. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
199224. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
199225. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
199226. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
199227. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
199228. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
199229. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
199230. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
199231. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
199232. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
199233. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
199234. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
199235. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
199236. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
199237. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
199238. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
199239. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
199240. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
199241. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
199242. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
199243. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
199244. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
199245. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
199246. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
199247. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
199248. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
199249. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
199250. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
199251. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
199252. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
199253. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
199254. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
199255. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
199256. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
199257. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
199258. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
199259. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
199260. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
199261. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
199262. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
199263. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
199264. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
199265. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
199266. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
199267. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
199268. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
199269. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
199270. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
199271. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
199272. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
199273. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
199274. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
199275. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
199276. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
199277. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
199278. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
199279. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
199280. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
199281. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
199282. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
199283. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
199284. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
199285. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
199286. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
199287. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
199288. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
199289. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
199290. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
199291. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
199292. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
199293. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
199294. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
199295. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
199296. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
199297. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
199298. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
199299. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
199300. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
199301. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
199302. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
199303. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
199304. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
199305. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
199306. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
199307. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
199308. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
199309. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
199310. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
199311. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
199312. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
199313. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
199314. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
199315. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
199316. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
199317. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
199318. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
199319. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
199320. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
199321. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
199322. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
199323. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
199324. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
199325. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
199326. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
199327. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
199328. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
199329. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
199330. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
199331. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
199332. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
199333. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
199334. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
199335. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
199336. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
199337. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
199338. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
199339. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
199340. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
199341. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
199342. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
199343. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
199344. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
199345. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
199346. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
199347. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
199348. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
199349. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
199350. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
199351. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
199352. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
199353. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
199354. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
199355. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
199356. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
199357. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
199358. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
199359. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
199360. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
199361. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
199362. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
199363. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
199364. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
199365. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
199366. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
199367. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
199368. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
199369. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
199370. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
199371. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
199372. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
199373. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
199374. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
199375. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
199376. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
199377. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
199378. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
199379. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
199380. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
199381. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
199382. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
199383. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
199384. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
199385. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
199386. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
199387. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
199388. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
199389. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
199390. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
199391. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
199392. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
199393. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
199394. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
199395. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
199396. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
199397. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
199398. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
199399. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
199400. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
199401. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
199402. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
199403. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
199404. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
199405. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
199406. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
199407. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
199408. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
199409. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
199410. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
199411. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
199412. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
199413. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
199414. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
199415. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
199416. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
199417. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
199418. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
199419. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
199420. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
199421. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
199422. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
199423. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
199424. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
199425. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
199426. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
199427. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
199428. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
199429. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
199430. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
199431. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
199432. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
199433. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
199434. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
199435. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
199436. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
199437. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
199438. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
199439. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
199440. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
199441. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
199442. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
199443. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
199444. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
199445. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
199446. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
199447. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
199448. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
199449. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
199450. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
199451. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
199452. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
199453. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
199454. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
199455. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
199456. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
199457. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
199458. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
199459. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
199460. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
199461. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
199462. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
199463. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
199464. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
199465. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
199466. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
199467. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
199468. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
199469. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
199470. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
199471. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
199472. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
199473. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
199474. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
199475. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
199476. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
199477. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
199478. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
199479. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
199480. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
199481. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
199482. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
199483. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
199484. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
199485. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
199486. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
199487. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
199488. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
199489. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
199490. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
199491. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
199492. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
199493. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
199494. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
199495. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
199496. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
199497. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
199498. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
199499. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
199500. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
199501. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
199502. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
199503. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
199504. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
199505. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
199506. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
199507. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
199508. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
199509. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
199510. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
199511. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
199512. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
199513. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
199514. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
199515. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
199516. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
199517. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
199518. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
199519. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
199520. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
199521. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
199522. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
199523. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
199524. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
199525. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
199526. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
199527. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
199528. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
199529. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
199530. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
199531. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
199532. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
199533. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
199534. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
199535. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
199536. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
199537. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
199538. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
199539. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
199540. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
199541. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
199542. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
199543. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
199544. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
199545. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
199546. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
199547. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
199548. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK
199549. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT
199550. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__MODE_MASK
199551. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT
199552. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
199553. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
199554. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK
199555. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT
199556. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK
199557. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT
199558. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__OV14_MASK
199559. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT
199560. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
199561. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
199562. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
199563. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
199564. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
199565. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
199566. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
199567. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
199568. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
199569. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
199570. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
199571. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
199572. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
199573. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
199574. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
199575. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
199576. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
199577. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
199578. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
199579. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
199580. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
199581. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
199582. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
199583. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
199584. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
199585. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
199586. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
199587. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
199588. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
199589. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
199590. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
199591. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
199592. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
199593. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
199594. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
199595. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
199596. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
199597. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
199598. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
199599. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
199600. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
199601. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
199602. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
199603. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
199604. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
199605. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
199606. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
199607. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
199608. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
199609. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
199610. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
199611. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
199612. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
199613. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
199614. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
199615. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
199616. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
199617. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
199618. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
199619. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
199620. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
199621. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
199622. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
199623. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
199624. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
199625. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
199626. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
199627. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
199628. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
199629. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
199630. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
199631. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
199632. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
199633. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
199634. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
199635. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
199636. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
199637. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
199638. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
199639. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
199640. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
199641. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
199642. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
199643. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
199644. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
199645. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
199646. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
199647. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
199648. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
199649. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
199650. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
199651. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
199652. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
199653. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
199654. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
199655. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
199656. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
199657. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
199658. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
199659. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
199660. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
199661. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
199662. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
199663. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
199664. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
199665. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
199666. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
199667. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
199668. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
199669. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
199670. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
199671. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
199672. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
199673. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
199674. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
199675. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
199676. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
199677. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
199678. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
199679. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
199680. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
199681. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
199682. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
199683. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
199684. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
199685. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
199686. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
199687. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
199688. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
199689. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
199690. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
199691. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
199692. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
199693. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
199694. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
199695. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
199696. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
199697. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
199698. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
199699. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
199700. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
199701. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
199702. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
199703. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
199704. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
199705. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
199706. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
199707. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
199708. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
199709. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
199710. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
199711. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
199712. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
199713. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
199714. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
199715. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
199716. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
199717. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
199718. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
199719. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
199720. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
199721. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
199722. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
199723. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
199724. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
199725. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
199726. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
199727. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
199728. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
199729. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
199730. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
199731. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
199732. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
199733. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
199734. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
199735. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
199736. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
199737. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
199738. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
199739. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
199740. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
199741. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
199742. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
199743. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
199744. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
199745. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
199746. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
199747. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
199748. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
199749. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
199750. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
199751. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
199752. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
199753. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
199754. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
199755. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
199756. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
199757. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
199758. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
199759. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
199760. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
199761. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
199762. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
199763. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
199764. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
199765. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
199766. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
199767. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
199768. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
199769. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
199770. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
199771. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
199772. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
199773. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
199774. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
199775. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
199776. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
199777. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
199778. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
199779. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
199780. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
199781. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
199782. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
199783. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
199784. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
199785. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
199786. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
199787. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
199788. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
199789. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
199790. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
199791. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
199792. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
199793. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
199794. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
199795. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
199796. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
199797. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
199798. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
199799. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
199800. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
199801. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
199802. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
199803. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
199804. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
199805. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
199806. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
199807. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
199808. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
199809. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
199810. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
199811. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
199812. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
199813. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
199814. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
199815. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
199816. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
199817. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
199818. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
199819. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
199820. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
199821. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
199822. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
199823. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
199824. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
199825. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
199826. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
199827. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
199828. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
199829. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
199830. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
199831. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
199832. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
199833. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
199834. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
199835. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
199836. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
199837. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
199838. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
199839. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
199840. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
199841. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
199842. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
199843. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
199844. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
199845. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
199846. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
199847. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
199848. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
199849. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
199850. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
199851. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
199852. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
199853. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
199854. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
199855. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
199856. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
199857. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
199858. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
199859. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
199860. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
199861. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
199862. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
199863. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
199864. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
199865. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
199866. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
199867. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
199868. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
199869. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
199870. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
199871. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
199872. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
199873. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
199874. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
199875. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
199876. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
199877. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
199878. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
199879. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
199880. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
199881. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
199882. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
199883. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
199884. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
199885. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
199886. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
199887. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
199888. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
199889. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
199890. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
199891. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
199892. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
199893. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
199894. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
199895. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
199896. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
199897. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
199898. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
199899. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
199900. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
199901. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
199902. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK
199903. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT
199904. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK
199905. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT
199906. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
199907. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
199908. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
199909. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
199910. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
199911. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
199912. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
199913. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
199914. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
199915. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
199916. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
199917. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
199918. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
199919. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
199920. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
199921. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
199922. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
199923. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
199924. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
199925. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
199926. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
199927. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
199928. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
199929. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
199930. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
199931. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
199932. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
199933. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
199934. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
199935. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
199936. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
199937. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
199938. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
199939. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
199940. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
199941. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
199942. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
199943. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
199944. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
199945. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
199946. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
199947. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
199948. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
199949. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
199950. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
199951. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
199952. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
199953. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
199954. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
199955. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
199956. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
199957. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
199958. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
199959. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
199960. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
199961. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
199962. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
199963. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
199964. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
199965. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
199966. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
199967. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
199968. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
199969. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
199970. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
199971. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
199972. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
199973. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
199974. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
199975. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
199976. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
199977. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
199978. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
199979. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
199980. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
199981. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
199982. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
199983. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
199984. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
199985. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
199986. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
199987. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
199988. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
199989. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
199990. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
199991. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
199992. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
199993. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
199994. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
199995. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
199996. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
199997. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
199998. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
199999. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
200000. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
200001. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
200002. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
200003. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
200004. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
200005. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
200006. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
200007. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
200008. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
200009. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
200010. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
200011. DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
200012. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
200013. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
200014. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
200015. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
200016. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
200017. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
200018. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
200019. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
200020. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
200021. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
200022. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK
200023. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT
200024. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
200025. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
200026. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
200027. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
200028. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
200029. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
200030. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
200031. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
200032. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
200033. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
200034. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
200035. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
200036. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
200037. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
200038. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
200039. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
200040. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
200041. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
200042. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
200043. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
200044. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
200045. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
200046. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
200047. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
200048. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
200049. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
200050. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
200051. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
200052. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
200053. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
200054. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK
200055. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
200056. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK
200057. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
200058. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK
200059. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
200060. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
200061. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
200062. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
200063. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
200064. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
200065. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
200066. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
200067. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
200068. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
200069. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
200070. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
200071. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
200072. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
200073. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
200074. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
200075. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
200076. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
200077. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
200078. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
200079. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
200080. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
200081. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
200082. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
200083. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
200084. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
200085. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
200086. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
200087. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
200088. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
200089. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
200090. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
200091. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
200092. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
200093. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
200094. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
200095. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
200096. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
200097. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
200098. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
200099. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
200100. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK
200101. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
200102. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK
200103. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
200104. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
200105. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
200106. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
200107. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
200108. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
200109. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
200110. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
200111. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
200112. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK
200113. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
200114. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
200115. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
200116. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
200117. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
200118. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
200119. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
200120. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
200121. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
200122. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
200123. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
200124. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__NC32_MASK
200125. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT
200126. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
200127. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
200128. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
200129. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
200130. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
200131. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
200132. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
200133. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
200134. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
200135. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
200136. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK
200137. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
200138. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
200139. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
200140. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
200141. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
200142. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
200143. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
200144. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
200145. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
200146. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
200147. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
200148. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK
200149. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
200150. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
200151. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
200152. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
200153. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
200154. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
200155. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
200156. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
200157. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
200158. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK
200159. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT
200160. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
200161. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
200162. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
200163. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
200164. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
200165. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
200166. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
200167. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
200168. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
200169. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
200170. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
200171. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
200172. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
200173. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
200174. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
200175. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
200176. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
200177. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
200178. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
200179. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
200180. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__NC20_MASK
200181. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__NC20__SHIFT
200182. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK
200183. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT
200184. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
200185. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
200186. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
200187. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
200188. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
200189. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
200190. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK
200191. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
200192. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK
200193. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
200194. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
200195. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
200196. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK
200197. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
200198. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK
200199. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
200200. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK
200201. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT
200202. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
200203. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
200204. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK
200205. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT
200206. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK
200207. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT
200208. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
200209. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
200210. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK
200211. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT
200212. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_gd_MASK
200213. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_gd__SHIFT
200214. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccm_MASK
200215. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT
200216. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccp_MASK
200217. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT
200218. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vptx_MASK
200219. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT
200220. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg0_MASK
200221. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT
200222. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg1_MASK
200223. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT
200224. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK
200225. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT
200226. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__override_regref_0_MASK
200227. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT
200228. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK
200229. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT
200230. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_nbias_MASK
200231. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT
200232. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_pbias_MASK
200233. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT
200234. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK
200235. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT
200236. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfm_MASK
200237. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT
200238. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfp_MASK
200239. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT
200240. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsm_MASK
200241. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT
200242. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsp_MASK
200243. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT
200244. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_vcm_MASK
200245. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT
200246. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
200247. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
200248. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK
200249. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
200250. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
200251. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
200252. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
200253. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
200254. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
200255. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
200256. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
200257. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
200258. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK
200259. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT
200260. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK
200261. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
200262. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__nc_MASK
200263. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__nc__SHIFT
200264. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_nmos_MASK
200265. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_nmos__SHIFT
200266. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_pmos_MASK
200267. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_pmos__SHIFT
200268. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__override_rxdetref_MASK
200269. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT
200270. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
200271. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
200272. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
200273. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
200274. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
200275. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
200276. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
200277. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
200278. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK
200279. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
200280. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
200281. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
200282. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
200283. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
200284. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
200285. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
200286. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
200287. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
200288. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
200289. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
200290. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
200291. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
200292. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
200293. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
200294. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
200295. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
200296. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
200297. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
200298. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
200299. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
200300. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
200301. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
200302. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
200303. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
200304. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
200305. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
200306. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
200307. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
200308. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
200309. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
200310. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK
200311. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
200312. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK
200313. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
200314. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
200315. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
200316. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK
200317. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
200318. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
200319. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
200320. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
200321. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
200322. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK
200323. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
200324. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
200325. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
200326. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
200327. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
200328. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
200329. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
200330. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
200331. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
200332. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
200333. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
200334. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
200335. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
200336. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK
200337. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
200338. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK
200339. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT
200340. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_MASK
200341. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT
200342. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK
200343. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
200344. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
200345. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
200346. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK
200347. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
200348. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK
200349. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
200350. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK
200351. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
200352. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK
200353. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT
200354. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
200355. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
200356. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
200357. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
200358. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
200359. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
200360. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
200361. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
200362. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
200363. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
200364. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
200365. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
200366. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
200367. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
200368. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
200369. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
200370. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
200371. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
200372. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
200373. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
200374. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
200375. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
200376. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
200377. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
200378. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
200379. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
200380. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
200381. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
200382. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
200383. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
200384. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
200385. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
200386. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
200387. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
200388. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
200389. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
200390. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
200391. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
200392. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
200393. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
200394. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
200395. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
200396. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
200397. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
200398. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
200399. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
200400. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
200401. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
200402. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
200403. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
200404. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
200405. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
200406. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
200407. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
200408. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
200409. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
200410. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
200411. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
200412. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
200413. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
200414. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
200415. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
200416. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
200417. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
200418. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
200419. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
200420. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
200421. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
200422. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
200423. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
200424. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
200425. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
200426. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
200427. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
200428. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
200429. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
200430. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
200431. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
200432. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
200433. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
200434. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
200435. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
200436. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
200437. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
200438. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
200439. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
200440. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
200441. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
200442. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
200443. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
200444. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
200445. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
200446. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
200447. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
200448. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
200449. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
200450. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
200451. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
200452. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
200453. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
200454. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
200455. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
200456. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
200457. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
200458. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
200459. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
200460. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
200461. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
200462. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
200463. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
200464. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
200465. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
200466. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
200467. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
200468. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
200469. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
200470. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
200471. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
200472. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
200473. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
200474. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
200475. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
200476. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
200477. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
200478. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
200479. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
200480. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
200481. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
200482. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
200483. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
200484. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
200485. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
200486. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
200487. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
200488. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
200489. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
200490. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
200491. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
200492. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
200493. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
200494. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
200495. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
200496. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
200497. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
200498. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
200499. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
200500. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
200501. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
200502. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
200503. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
200504. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
200505. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
200506. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
200507. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
200508. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
200509. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
200510. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
200511. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
200512. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
200513. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
200514. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
200515. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
200516. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
200517. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
200518. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
200519. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
200520. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
200521. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
200522. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
200523. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
200524. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
200525. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
200526. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
200527. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
200528. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
200529. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
200530. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
200531. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
200532. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
200533. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
200534. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
200535. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
200536. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
200537. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
200538. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
200539. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
200540. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
200541. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
200542. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
200543. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
200544. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
200545. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
200546. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
200547. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
200548. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
200549. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
200550. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
200551. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
200552. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
200553. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
200554. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
200555. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
200556. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
200557. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
200558. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
200559. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
200560. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
200561. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
200562. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
200563. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
200564. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
200565. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
200566. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
200567. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
200568. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
200569. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
200570. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
200571. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
200572. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
200573. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
200574. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
200575. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
200576. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
200577. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
200578. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
200579. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
200580. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
200581. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
200582. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
200583. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
200584. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
200585. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
200586. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
200587. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
200588. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
200589. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
200590. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
200591. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
200592. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
200593. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
200594. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
200595. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
200596. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
200597. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
200598. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK
200599. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
200600. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
200601. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
200602. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
200603. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
200604. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
200605. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
200606. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
200607. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
200608. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
200609. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
200610. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
200611. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
200612. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
200613. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
200614. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
200615. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
200616. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
200617. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
200618. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
200619. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
200620. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
200621. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
200622. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
200623. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
200624. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
200625. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
200626. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
200627. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
200628. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
200629. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
200630. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
200631. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
200632. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
200633. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
200634. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
200635. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
200636. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
200637. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
200638. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
200639. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
200640. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
200641. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
200642. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
200643. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
200644. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
200645. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
200646. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
200647. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
200648. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
200649. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
200650. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
200651. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
200652. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
200653. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
200654. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
200655. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
200656. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
200657. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
200658. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
200659. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
200660. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
200661. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
200662. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
200663. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
200664. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
200665. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
200666. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
200667. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
200668. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
200669. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
200670. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
200671. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
200672. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
200673. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
200674. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
200675. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
200676. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
200677. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
200678. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
200679. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
200680. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
200681. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
200682. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
200683. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
200684. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
200685. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
200686. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
200687. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
200688. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
200689. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
200690. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
200691. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
200692. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
200693. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
200694. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
200695. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
200696. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
200697. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
200698. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
200699. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
200700. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
200701. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
200702. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
200703. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
200704. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
200705. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
200706. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
200707. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
200708. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
200709. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
200710. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
200711. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
200712. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
200713. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
200714. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
200715. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
200716. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
200717. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
200718. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
200719. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
200720. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
200721. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
200722. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
200723. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
200724. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
200725. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
200726. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
200727. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
200728. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
200729. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
200730. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
200731. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
200732. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
200733. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
200734. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
200735. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
200736. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
200737. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
200738. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
200739. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
200740. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
200741. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
200742. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
200743. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
200744. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
200745. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
200746. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
200747. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
200748. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
200749. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
200750. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
200751. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
200752. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
200753. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
200754. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
200755. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
200756. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
200757. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
200758. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
200759. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
200760. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
200761. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
200762. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
200763. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
200764. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
200765. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
200766. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
200767. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
200768. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
200769. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
200770. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
200771. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
200772. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
200773. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
200774. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
200775. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
200776. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
200777. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
200778. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
200779. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
200780. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
200781. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
200782. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
200783. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
200784. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
200785. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
200786. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
200787. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
200788. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
200789. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
200790. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
200791. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
200792. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
200793. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
200794. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
200795. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
200796. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
200797. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
200798. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
200799. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
200800. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
200801. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
200802. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
200803. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
200804. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
200805. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
200806. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
200807. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
200808. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
200809. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
200810. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
200811. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
200812. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
200813. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
200814. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
200815. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
200816. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
200817. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
200818. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
200819. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
200820. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
200821. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
200822. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
200823. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
200824. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
200825. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
200826. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
200827. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
200828. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
200829. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
200830. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
200831. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
200832. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
200833. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
200834. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
200835. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
200836. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
200837. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
200838. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
200839. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
200840. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
200841. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
200842. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
200843. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
200844. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
200845. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
200846. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
200847. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
200848. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
200849. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
200850. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
200851. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
200852. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
200853. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
200854. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
200855. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
200856. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
200857. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
200858. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
200859. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
200860. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
200861. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
200862. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
200863. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
200864. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
200865. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
200866. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
200867. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
200868. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
200869. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
200870. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
200871. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
200872. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
200873. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
200874. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
200875. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
200876. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
200877. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
200878. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
200879. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
200880. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
200881. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
200882. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
200883. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
200884. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
200885. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
200886. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
200887. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
200888. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
200889. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
200890. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
200891. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
200892. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
200893. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
200894. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
200895. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
200896. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
200897. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
200898. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
200899. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
200900. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
200901. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
200902. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
200903. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
200904. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
200905. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
200906. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
200907. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
200908. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
200909. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
200910. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
200911. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
200912. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
200913. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
200914. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
200915. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
200916. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
200917. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
200918. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
200919. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
200920. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
200921. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
200922. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
200923. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
200924. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
200925. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
200926. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
200927. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
200928. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
200929. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
200930. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
200931. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
200932. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
200933. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
200934. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
200935. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
200936. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
200937. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
200938. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
200939. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
200940. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
200941. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
200942. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
200943. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
200944. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
200945. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
200946. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
200947. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
200948. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
200949. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
200950. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
200951. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
200952. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
200953. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
200954. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
200955. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
200956. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
200957. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
200958. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
200959. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
200960. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
200961. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
200962. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
200963. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
200964. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
200965. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
200966. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
200967. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
200968. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
200969. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
200970. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
200971. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
200972. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
200973. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
200974. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
200975. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
200976. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
200977. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
200978. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
200979. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
200980. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
200981. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
200982. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
200983. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
200984. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
200985. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
200986. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
200987. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
200988. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
200989. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
200990. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
200991. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
200992. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
200993. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
200994. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
200995. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
200996. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
200997. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
200998. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
200999. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
201000. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
201001. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
201002. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
201003. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
201004. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
201005. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
201006. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
201007. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
201008. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
201009. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
201010. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
201011. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
201012. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
201013. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
201014. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
201015. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
201016. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
201017. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
201018. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
201019. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
201020. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
201021. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
201022. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
201023. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
201024. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
201025. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
201026. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
201027. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
201028. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
201029. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
201030. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
201031. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
201032. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
201033. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
201034. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
201035. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
201036. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
201037. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
201038. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
201039. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
201040. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
201041. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
201042. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
201043. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
201044. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
201045. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
201046. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
201047. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
201048. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
201049. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
201050. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
201051. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
201052. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
201053. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
201054. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
201055. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
201056. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
201057. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
201058. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
201059. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
201060. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
201061. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
201062. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
201063. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
201064. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
201065. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
201066. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
201067. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
201068. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
201069. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
201070. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
201071. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
201072. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
201073. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
201074. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
201075. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
201076. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
201077. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
201078. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
201079. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
201080. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
201081. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
201082. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
201083. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
201084. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
201085. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
201086. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
201087. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
201088. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
201089. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
201090. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
201091. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
201092. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
201093. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
201094. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
201095. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
201096. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
201097. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
201098. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
201099. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
201100. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
201101. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
201102. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
201103. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
201104. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
201105. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
201106. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
201107. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
201108. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
201109. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
201110. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
201111. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
201112. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
201113. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
201114. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
201115. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
201116. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
201117. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
201118. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
201119. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
201120. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
201121. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
201122. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
201123. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
201124. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
201125. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
201126. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
201127. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
201128. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
201129. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
201130. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
201131. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
201132. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
201133. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
201134. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
201135. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
201136. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
201137. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
201138. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
201139. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
201140. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
201141. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
201142. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
201143. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
201144. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
201145. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
201146. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
201147. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
201148. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
201149. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
201150. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
201151. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
201152. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
201153. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
201154. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK
201155. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT
201156. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK
201157. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT
201158. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
201159. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
201160. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK
201161. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT
201162. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK
201163. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT
201164. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK
201165. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT
201166. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
201167. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
201168. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
201169. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
201170. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
201171. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
201172. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
201173. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
201174. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
201175. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
201176. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
201177. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
201178. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
201179. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
201180. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
201181. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
201182. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
201183. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
201184. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
201185. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
201186. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
201187. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
201188. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
201189. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
201190. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
201191. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
201192. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
201193. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
201194. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
201195. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
201196. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
201197. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
201198. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
201199. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
201200. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
201201. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
201202. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
201203. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
201204. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
201205. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
201206. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
201207. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
201208. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
201209. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
201210. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
201211. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
201212. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
201213. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
201214. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
201215. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
201216. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
201217. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
201218. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
201219. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
201220. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
201221. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
201222. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
201223. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
201224. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
201225. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
201226. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
201227. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
201228. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
201229. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
201230. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
201231. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
201232. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
201233. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
201234. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
201235. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
201236. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
201237. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
201238. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
201239. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
201240. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
201241. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
201242. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
201243. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
201244. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
201245. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
201246. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
201247. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
201248. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
201249. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
201250. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
201251. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
201252. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
201253. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
201254. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
201255. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
201256. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
201257. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
201258. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
201259. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
201260. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
201261. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
201262. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
201263. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
201264. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
201265. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
201266. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
201267. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
201268. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
201269. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
201270. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
201271. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
201272. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
201273. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
201274. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
201275. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
201276. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
201277. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
201278. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
201279. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
201280. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
201281. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
201282. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
201283. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
201284. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
201285. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
201286. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
201287. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
201288. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
201289. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
201290. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
201291. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
201292. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
201293. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
201294. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
201295. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
201296. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
201297. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
201298. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
201299. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
201300. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
201301. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
201302. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
201303. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
201304. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
201305. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
201306. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
201307. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
201308. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
201309. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
201310. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
201311. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
201312. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
201313. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
201314. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
201315. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
201316. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
201317. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
201318. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
201319. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
201320. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
201321. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
201322. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
201323. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
201324. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
201325. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
201326. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
201327. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
201328. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
201329. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
201330. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
201331. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
201332. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
201333. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
201334. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
201335. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
201336. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
201337. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
201338. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
201339. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
201340. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
201341. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
201342. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
201343. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
201344. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
201345. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
201346. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
201347. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
201348. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
201349. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
201350. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
201351. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
201352. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
201353. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
201354. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
201355. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
201356. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
201357. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
201358. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
201359. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
201360. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
201361. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
201362. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
201363. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
201364. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
201365. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
201366. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
201367. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
201368. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
201369. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
201370. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
201371. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
201372. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
201373. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
201374. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
201375. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
201376. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
201377. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
201378. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
201379. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
201380. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
201381. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
201382. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
201383. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
201384. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
201385. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
201386. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
201387. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
201388. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
201389. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
201390. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
201391. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
201392. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
201393. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
201394. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
201395. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
201396. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
201397. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
201398. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
201399. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
201400. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
201401. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
201402. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
201403. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
201404. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
201405. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
201406. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
201407. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
201408. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
201409. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
201410. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
201411. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
201412. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
201413. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
201414. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
201415. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
201416. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
201417. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
201418. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
201419. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
201420. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
201421. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
201422. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
201423. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
201424. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
201425. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
201426. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
201427. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
201428. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
201429. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
201430. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
201431. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
201432. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
201433. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
201434. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
201435. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
201436. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
201437. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
201438. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
201439. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
201440. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
201441. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
201442. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
201443. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
201444. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
201445. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
201446. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
201447. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
201448. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
201449. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
201450. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
201451. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
201452. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
201453. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
201454. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
201455. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
201456. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
201457. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
201458. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
201459. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
201460. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
201461. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
201462. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
201463. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
201464. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
201465. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
201466. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
201467. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
201468. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
201469. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
201470. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
201471. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
201472. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
201473. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
201474. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
201475. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
201476. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
201477. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
201478. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
201479. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
201480. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
201481. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
201482. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
201483. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
201484. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
201485. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
201486. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
201487. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
201488. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
201489. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
201490. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
201491. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
201492. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
201493. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
201494. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
201495. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
201496. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
201497. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
201498. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
201499. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
201500. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
201501. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
201502. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
201503. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
201504. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
201505. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
201506. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
201507. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
201508. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK
201509. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT
201510. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK
201511. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT
201512. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
201513. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
201514. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
201515. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
201516. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
201517. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
201518. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
201519. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
201520. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
201521. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
201522. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
201523. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
201524. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
201525. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
201526. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
201527. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
201528. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
201529. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
201530. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
201531. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
201532. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
201533. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
201534. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
201535. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
201536. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
201537. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
201538. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
201539. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
201540. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
201541. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
201542. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
201543. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
201544. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
201545. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
201546. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
201547. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
201548. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
201549. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
201550. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
201551. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
201552. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
201553. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
201554. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
201555. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
201556. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
201557. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
201558. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
201559. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
201560. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
201561. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
201562. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
201563. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
201564. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
201565. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
201566. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
201567. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
201568. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
201569. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
201570. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
201571. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
201572. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
201573. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
201574. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
201575. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
201576. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
201577. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
201578. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
201579. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
201580. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
201581. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
201582. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
201583. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
201584. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
201585. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
201586. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
201587. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
201588. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
201589. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
201590. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
201591. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
201592. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
201593. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
201594. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
201595. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
201596. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
201597. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
201598. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
201599. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
201600. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
201601. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
201602. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
201603. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
201604. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
201605. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
201606. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
201607. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
201608. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
201609. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
201610. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
201611. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
201612. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
201613. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
201614. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
201615. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
201616. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
201617. DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
201618. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK
201619. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
201620. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK
201621. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT
201622. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK
201623. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
201624. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK
201625. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
201626. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK
201627. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
201628. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK
201629. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
201630. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK
201631. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
201632. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK
201633. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
201634. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK
201635. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
201636. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK
201637. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
201638. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK
201639. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
201640. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK
201641. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
201642. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK
201643. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
201644. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK
201645. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
201646. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK
201647. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
201648. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK
201649. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
201650. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK
201651. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
201652. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK
201653. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
201654. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK
201655. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
201656. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK
201657. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
201658. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK
201659. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
201660. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK
201661. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
201662. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK
201663. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
201664. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK
201665. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
201666. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK
201667. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
201668. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK
201669. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
201670. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK
201671. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
201672. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK
201673. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
201674. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK
201675. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
201676. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK
201677. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
201678. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK
201679. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
201680. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK
201681. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
201682. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK
201683. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
201684. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK
201685. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
201686. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK
201687. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
201688. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK
201689. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
201690. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK
201691. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
201692. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK
201693. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
201694. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK
201695. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
201696. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK
201697. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
201698. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK
201699. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
201700. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK
201701. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
201702. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK
201703. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
201704. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK
201705. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
201706. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK
201707. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
201708. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK
201709. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
201710. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK
201711. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
201712. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK
201713. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
201714. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK
201715. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
201716. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK
201717. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
201718. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK
201719. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
201720. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK
201721. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
201722. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK
201723. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
201724. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK
201725. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
201726. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK
201727. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
201728. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK
201729. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
201730. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK
201731. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
201732. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK
201733. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
201734. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK
201735. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
201736. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK
201737. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
201738. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK
201739. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
201740. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK
201741. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
201742. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK
201743. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
201744. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK
201745. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
201746. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK
201747. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
201748. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK
201749. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
201750. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK
201751. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
201752. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK
201753. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
201754. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK
201755. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
201756. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK
201757. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
201758. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK
201759. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
201760. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK
201761. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
201762. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK
201763. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
201764. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK
201765. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
201766. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK
201767. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
201768. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK
201769. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
201770. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK
201771. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
201772. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK
201773. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
201774. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK
201775. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
201776. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK
201777. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
201778. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK
201779. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
201780. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK
201781. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
201782. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK
201783. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
201784. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK
201785. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
201786. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK
201787. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
201788. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK
201789. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
201790. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK
201791. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
201792. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK
201793. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
201794. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK
201795. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
201796. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK
201797. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
201798. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK
201799. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
201800. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK
201801. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
201802. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK
201803. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
201804. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK
201805. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
201806. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK
201807. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
201808. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK
201809. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
201810. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK
201811. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
201812. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK
201813. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
201814. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK
201815. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
201816. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK
201817. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
201818. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK
201819. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
201820. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK
201821. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
201822. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK
201823. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
201824. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK
201825. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
201826. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK
201827. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
201828. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK
201829. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
201830. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK
201831. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
201832. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK
201833. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
201834. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK
201835. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
201836. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK
201837. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
201838. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK
201839. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
201840. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK
201841. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
201842. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK
201843. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
201844. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK
201845. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
201846. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK
201847. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
201848. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK
201849. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
201850. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK
201851. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
201852. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK
201853. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
201854. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK
201855. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
201856. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK
201857. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
201858. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK
201859. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
201860. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK
201861. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
201862. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK
201863. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
201864. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK
201865. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
201866. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK
201867. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
201868. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK
201869. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
201870. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK
201871. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
201872. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK
201873. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
201874. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK
201875. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
201876. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK
201877. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
201878. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK
201879. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
201880. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK
201881. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
201882. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK
201883. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
201884. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK
201885. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
201886. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK
201887. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
201888. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK
201889. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
201890. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK
201891. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
201892. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK
201893. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
201894. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK
201895. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
201896. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK
201897. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
201898. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK
201899. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
201900. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK
201901. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
201902. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK
201903. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
201904. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK
201905. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
201906. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK
201907. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
201908. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK
201909. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
201910. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK
201911. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
201912. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK
201913. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
201914. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK
201915. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
201916. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK
201917. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
201918. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK
201919. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
201920. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK
201921. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
201922. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK
201923. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
201924. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK
201925. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
201926. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK
201927. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
201928. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK
201929. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
201930. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK
201931. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
201932. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK
201933. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
201934. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK
201935. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
201936. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK
201937. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
201938. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK
201939. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
201940. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK
201941. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
201942. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK
201943. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
201944. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK
201945. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
201946. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK
201947. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
201948. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK
201949. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
201950. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK
201951. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
201952. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK
201953. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
201954. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK
201955. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
201956. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK
201957. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
201958. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK
201959. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
201960. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK
201961. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
201962. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK
201963. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
201964. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK
201965. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
201966. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK
201967. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
201968. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK
201969. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
201970. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK
201971. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
201972. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK
201973. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
201974. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK
201975. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
201976. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK
201977. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
201978. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK
201979. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
201980. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK
201981. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
201982. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK
201983. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
201984. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK
201985. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
201986. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK
201987. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
201988. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK
201989. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
201990. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK
201991. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
201992. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK
201993. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
201994. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK
201995. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
201996. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK
201997. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
201998. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK
201999. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
202000. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK
202001. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
202002. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK
202003. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
202004. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK
202005. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
202006. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK
202007. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
202008. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK
202009. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
202010. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK
202011. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
202012. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK
202013. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
202014. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK
202015. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
202016. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK
202017. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
202018. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK
202019. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
202020. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK
202021. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
202022. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK
202023. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
202024. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK
202025. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
202026. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK
202027. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
202028. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK
202029. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
202030. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK
202031. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
202032. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK
202033. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
202034. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK
202035. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
202036. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK
202037. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
202038. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK
202039. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
202040. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK
202041. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
202042. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK
202043. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
202044. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK
202045. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
202046. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK
202047. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
202048. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK
202049. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
202050. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK
202051. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
202052. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK
202053. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
202054. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK
202055. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
202056. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK
202057. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
202058. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK
202059. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
202060. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK
202061. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
202062. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK
202063. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
202064. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK
202065. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
202066. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK
202067. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
202068. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK
202069. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
202070. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK
202071. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
202072. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK
202073. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
202074. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK
202075. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
202076. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK
202077. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
202078. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK
202079. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
202080. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK
202081. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
202082. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK
202083. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
202084. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK
202085. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
202086. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK
202087. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
202088. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK
202089. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
202090. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK
202091. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
202092. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK
202093. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
202094. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK
202095. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
202096. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK
202097. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
202098. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK
202099. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
202100. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK
202101. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
202102. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK
202103. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
202104. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK
202105. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
202106. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK
202107. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
202108. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK
202109. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
202110. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK
202111. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
202112. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK
202113. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
202114. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK
202115. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
202116. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK
202117. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
202118. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK
202119. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
202120. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK
202121. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
202122. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK
202123. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
202124. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK
202125. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
202126. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK
202127. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
202128. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK
202129. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
202130. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK
202131. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
202132. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK
202133. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
202134. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK
202135. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
202136. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK
202137. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
202138. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK
202139. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
202140. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK
202141. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
202142. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK
202143. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
202144. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK
202145. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
202146. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK
202147. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
202148. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK
202149. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
202150. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK
202151. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
202152. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK
202153. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
202154. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK
202155. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
202156. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK
202157. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
202158. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK
202159. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
202160. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK
202161. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
202162. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK
202163. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
202164. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK
202165. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
202166. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK
202167. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
202168. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK
202169. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
202170. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK
202171. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
202172. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK
202173. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
202174. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK
202175. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
202176. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK
202177. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
202178. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK
202179. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
202180. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK
202181. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
202182. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK
202183. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
202184. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK
202185. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
202186. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK
202187. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
202188. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK
202189. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
202190. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK
202191. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
202192. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK
202193. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
202194. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK
202195. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
202196. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK
202197. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
202198. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK
202199. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
202200. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK
202201. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
202202. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK
202203. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
202204. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK
202205. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
202206. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK
202207. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
202208. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK
202209. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
202210. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK
202211. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
202212. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK
202213. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
202214. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK
202215. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
202216. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK
202217. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
202218. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK
202219. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
202220. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK
202221. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
202222. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK
202223. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
202224. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK
202225. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
202226. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK
202227. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
202228. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK
202229. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
202230. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK
202231. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
202232. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK
202233. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
202234. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK
202235. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
202236. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK
202237. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
202238. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK
202239. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
202240. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK
202241. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
202242. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK
202243. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
202244. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK
202245. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
202246. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK
202247. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
202248. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK
202249. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
202250. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK
202251. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
202252. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK
202253. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
202254. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK
202255. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
202256. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK
202257. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
202258. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK
202259. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
202260. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK
202261. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
202262. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK
202263. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
202264. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK
202265. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
202266. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK
202267. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
202268. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK
202269. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
202270. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK
202271. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
202272. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK
202273. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
202274. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK
202275. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
202276. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK
202277. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
202278. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK
202279. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
202280. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK
202281. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
202282. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK
202283. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
202284. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK
202285. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
202286. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK
202287. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
202288. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK
202289. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
202290. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK
202291. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
202292. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK
202293. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
202294. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK
202295. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
202296. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK
202297. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
202298. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK
202299. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
202300. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK
202301. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
202302. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK
202303. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
202304. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK
202305. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
202306. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK
202307. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
202308. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK
202309. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
202310. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK
202311. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
202312. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK
202313. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
202314. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK
202315. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
202316. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK
202317. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
202318. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK
202319. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
202320. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK
202321. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
202322. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK
202323. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
202324. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK
202325. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
202326. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK
202327. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
202328. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK
202329. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
202330. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK
202331. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
202332. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK
202333. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
202334. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK
202335. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
202336. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK
202337. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
202338. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK
202339. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
202340. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK
202341. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
202342. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK
202343. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
202344. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK
202345. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
202346. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK
202347. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
202348. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK
202349. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
202350. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK
202351. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
202352. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK
202353. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
202354. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK
202355. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
202356. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK
202357. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
202358. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK
202359. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
202360. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK
202361. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
202362. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK
202363. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
202364. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK
202365. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
202366. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK
202367. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
202368. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK
202369. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
202370. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK
202371. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
202372. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK
202373. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
202374. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK
202375. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
202376. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK
202377. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
202378. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK
202379. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
202380. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK
202381. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
202382. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK
202383. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
202384. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK
202385. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
202386. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK
202387. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
202388. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK
202389. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
202390. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK
202391. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
202392. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK
202393. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
202394. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK
202395. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
202396. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK
202397. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
202398. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK
202399. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
202400. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK
202401. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
202402. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK
202403. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
202404. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK
202405. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
202406. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK
202407. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
202408. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK
202409. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
202410. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK
202411. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
202412. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK
202413. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
202414. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK
202415. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
202416. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK
202417. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
202418. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK
202419. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
202420. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK
202421. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
202422. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK
202423. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
202424. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK
202425. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
202426. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK
202427. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
202428. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK
202429. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
202430. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK
202431. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
202432. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK
202433. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
202434. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK
202435. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
202436. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK
202437. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
202438. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK
202439. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
202440. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK
202441. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
202442. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK
202443. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
202444. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK
202445. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
202446. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK
202447. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
202448. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK
202449. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
202450. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK
202451. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
202452. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK
202453. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
202454. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK
202455. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
202456. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK
202457. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
202458. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK
202459. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
202460. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK
202461. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
202462. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK
202463. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
202464. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK
202465. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
202466. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK
202467. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
202468. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK
202469. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
202470. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK
202471. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
202472. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK
202473. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
202474. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK
202475. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
202476. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK
202477. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
202478. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK
202479. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
202480. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK
202481. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
202482. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK
202483. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
202484. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK
202485. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
202486. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK
202487. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
202488. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK
202489. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
202490. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK
202491. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
202492. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK
202493. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
202494. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK
202495. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
202496. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK
202497. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
202498. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK
202499. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
202500. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK
202501. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
202502. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK
202503. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
202504. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK
202505. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
202506. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK
202507. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
202508. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK
202509. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
202510. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK
202511. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
202512. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK
202513. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
202514. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK
202515. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
202516. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK
202517. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
202518. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK
202519. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
202520. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK
202521. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
202522. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK
202523. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
202524. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK
202525. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
202526. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK
202527. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
202528. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK
202529. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
202530. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK
202531. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
202532. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK
202533. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
202534. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK
202535. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
202536. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK
202537. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
202538. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK
202539. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
202540. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK
202541. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
202542. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK
202543. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
202544. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK
202545. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
202546. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK
202547. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
202548. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK
202549. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
202550. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK
202551. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
202552. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK
202553. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
202554. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK
202555. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
202556. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK
202557. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
202558. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK
202559. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
202560. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK
202561. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
202562. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK
202563. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
202564. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK
202565. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
202566. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK
202567. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
202568. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK
202569. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
202570. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK
202571. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
202572. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK
202573. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
202574. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK
202575. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
202576. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK
202577. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
202578. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK
202579. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
202580. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK
202581. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
202582. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK
202583. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
202584. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK
202585. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
202586. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK
202587. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
202588. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK
202589. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
202590. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK
202591. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
202592. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK
202593. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
202594. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK
202595. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
202596. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK
202597. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
202598. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK
202599. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
202600. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK
202601. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
202602. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK
202603. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
202604. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK
202605. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
202606. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK
202607. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
202608. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK
202609. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
202610. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK
202611. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
202612. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK
202613. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
202614. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK
202615. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
202616. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK
202617. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
202618. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK
202619. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
202620. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK
202621. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
202622. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK
202623. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
202624. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK
202625. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
202626. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK
202627. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
202628. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK
202629. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
202630. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK
202631. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
202632. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK
202633. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
202634. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK
202635. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
202636. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK
202637. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
202638. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK
202639. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
202640. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK
202641. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
202642. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK
202643. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
202644. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK
202645. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
202646. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK
202647. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
202648. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK
202649. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
202650. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK
202651. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
202652. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK
202653. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
202654. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK
202655. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
202656. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK
202657. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
202658. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK
202659. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
202660. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK
202661. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
202662. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK
202663. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
202664. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK
202665. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
202666. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK
202667. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
202668. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK
202669. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
202670. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK
202671. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
202672. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK
202673. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
202674. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK
202675. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
202676. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK
202677. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
202678. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK
202679. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
202680. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK
202681. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
202682. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK
202683. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
202684. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK
202685. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
202686. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK
202687. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
202688. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK
202689. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
202690. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK
202691. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
202692. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK
202693. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
202694. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK
202695. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
202696. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK
202697. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
202698. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK
202699. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
202700. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK
202701. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
202702. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK
202703. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
202704. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK
202705. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
202706. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK
202707. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
202708. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK
202709. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
202710. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK
202711. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
202712. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK
202713. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
202714. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK
202715. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
202716. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK
202717. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
202718. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK
202719. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
202720. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK
202721. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
202722. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK
202723. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
202724. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK
202725. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
202726. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK
202727. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
202728. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK
202729. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
202730. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK
202731. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
202732. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK
202733. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
202734. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK
202735. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
202736. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK
202737. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
202738. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK
202739. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
202740. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK
202741. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
202742. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK
202743. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
202744. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK
202745. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
202746. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK
202747. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
202748. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK
202749. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
202750. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK
202751. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
202752. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK
202753. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
202754. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK
202755. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
202756. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK
202757. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
202758. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK
202759. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
202760. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK
202761. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
202762. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK
202763. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
202764. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK
202765. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
202766. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK
202767. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
202768. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK
202769. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
202770. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK
202771. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
202772. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK
202773. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
202774. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK
202775. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
202776. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK
202777. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
202778. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK
202779. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
202780. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK
202781. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
202782. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK
202783. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
202784. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK
202785. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
202786. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK
202787. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
202788. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK
202789. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
202790. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK
202791. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
202792. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK
202793. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
202794. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK
202795. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
202796. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK
202797. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
202798. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK
202799. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
202800. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK
202801. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
202802. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK
202803. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
202804. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK
202805. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
202806. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK
202807. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
202808. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK
202809. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
202810. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK
202811. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
202812. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK
202813. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
202814. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK
202815. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
202816. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK
202817. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
202818. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK
202819. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
202820. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK
202821. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
202822. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK
202823. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
202824. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK
202825. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
202826. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK
202827. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
202828. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK
202829. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
202830. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK
202831. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
202832. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK
202833. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
202834. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK
202835. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
202836. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK
202837. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
202838. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK
202839. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
202840. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK
202841. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
202842. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK
202843. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
202844. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK
202845. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
202846. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK
202847. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
202848. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK
202849. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
202850. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK
202851. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
202852. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK
202853. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
202854. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK
202855. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
202856. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK
202857. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
202858. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK
202859. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
202860. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK
202861. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
202862. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK
202863. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
202864. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK
202865. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
202866. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK
202867. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
202868. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK
202869. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
202870. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK
202871. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
202872. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK
202873. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
202874. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK
202875. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
202876. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK
202877. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
202878. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK
202879. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
202880. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK
202881. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
202882. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK
202883. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
202884. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK
202885. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
202886. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK
202887. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
202888. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK
202889. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
202890. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK
202891. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
202892. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK
202893. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
202894. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK
202895. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
202896. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK
202897. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
202898. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK
202899. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
202900. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK
202901. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
202902. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK
202903. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
202904. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK
202905. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
202906. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK
202907. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
202908. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK
202909. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
202910. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK
202911. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
202912. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK
202913. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
202914. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK
202915. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
202916. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK
202917. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
202918. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK
202919. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
202920. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK
202921. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
202922. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK
202923. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
202924. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK
202925. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
202926. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK
202927. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
202928. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK
202929. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
202930. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK
202931. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
202932. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK
202933. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
202934. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK
202935. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
202936. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK
202937. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
202938. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK
202939. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
202940. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK
202941. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
202942. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK
202943. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
202944. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK
202945. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
202946. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK
202947. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
202948. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK
202949. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
202950. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK
202951. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
202952. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK
202953. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
202954. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK
202955. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
202956. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK
202957. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
202958. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK
202959. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
202960. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK
202961. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
202962. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK
202963. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
202964. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK
202965. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
202966. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK
202967. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
202968. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK
202969. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
202970. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK
202971. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
202972. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK
202973. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
202974. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK
202975. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
202976. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK
202977. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
202978. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK
202979. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
202980. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK
202981. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
202982. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK
202983. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
202984. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK
202985. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
202986. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK
202987. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
202988. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK
202989. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
202990. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK
202991. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
202992. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK
202993. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
202994. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK
202995. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
202996. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK
202997. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
202998. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK
202999. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
203000. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK
203001. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
203002. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK
203003. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
203004. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK
203005. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
203006. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK
203007. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
203008. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK
203009. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
203010. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK
203011. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
203012. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK
203013. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
203014. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK
203015. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
203016. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK
203017. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
203018. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK
203019. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
203020. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK
203021. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
203022. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK
203023. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
203024. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK
203025. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
203026. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK
203027. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
203028. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK
203029. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
203030. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK
203031. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
203032. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK
203033. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
203034. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK
203035. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
203036. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK
203037. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
203038. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK
203039. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
203040. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK
203041. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
203042. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK
203043. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
203044. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK
203045. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
203046. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK
203047. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
203048. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK
203049. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
203050. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK
203051. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
203052. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK
203053. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
203054. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK
203055. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
203056. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK
203057. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
203058. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK
203059. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
203060. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK
203061. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
203062. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK
203063. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
203064. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK
203065. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
203066. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK
203067. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
203068. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK
203069. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
203070. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK
203071. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
203072. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK
203073. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
203074. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK
203075. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
203076. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK
203077. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
203078. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK
203079. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
203080. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK
203081. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
203082. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK
203083. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
203084. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK
203085. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
203086. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK
203087. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
203088. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK
203089. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
203090. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK
203091. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
203092. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK
203093. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
203094. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK
203095. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
203096. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK
203097. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
203098. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK
203099. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
203100. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK
203101. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
203102. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK
203103. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
203104. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK
203105. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
203106. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK
203107. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
203108. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK
203109. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
203110. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK
203111. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
203112. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK
203113. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
203114. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK
203115. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
203116. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK
203117. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
203118. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK
203119. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
203120. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK
203121. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
203122. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK
203123. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
203124. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK
203125. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
203126. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK
203127. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
203128. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK
203129. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
203130. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK
203131. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
203132. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK
203133. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
203134. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK
203135. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
203136. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK
203137. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
203138. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK
203139. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
203140. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK
203141. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
203142. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK
203143. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
203144. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK
203145. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
203146. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK
203147. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
203148. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK
203149. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
203150. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK
203151. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
203152. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK
203153. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
203154. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK
203155. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
203156. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK
203157. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
203158. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK
203159. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
203160. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK
203161. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
203162. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK
203163. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
203164. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK
203165. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
203166. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK
203167. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
203168. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK
203169. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
203170. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK
203171. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
203172. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK
203173. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
203174. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK
203175. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
203176. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK
203177. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
203178. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK
203179. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
203180. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK
203181. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
203182. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK
203183. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
203184. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK
203185. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
203186. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK
203187. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
203188. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK
203189. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
203190. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK
203191. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
203192. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK
203193. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
203194. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK
203195. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
203196. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK
203197. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
203198. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK
203199. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
203200. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK
203201. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
203202. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK
203203. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
203204. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK
203205. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
203206. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK
203207. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
203208. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK
203209. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
203210. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK
203211. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
203212. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK
203213. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
203214. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK
203215. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
203216. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK
203217. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
203218. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK
203219. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
203220. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK
203221. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
203222. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK
203223. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
203224. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK
203225. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
203226. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK
203227. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
203228. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK
203229. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
203230. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK
203231. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
203232. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK
203233. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
203234. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK
203235. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
203236. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK
203237. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
203238. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK
203239. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
203240. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK
203241. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
203242. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK
203243. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
203244. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK
203245. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
203246. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK
203247. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
203248. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK
203249. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
203250. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK
203251. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
203252. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK
203253. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
203254. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK
203255. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
203256. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK
203257. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
203258. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK
203259. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
203260. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK
203261. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
203262. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK
203263. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
203264. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK
203265. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
203266. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK
203267. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
203268. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK
203269. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
203270. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK
203271. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
203272. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK
203273. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
203274. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK
203275. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
203276. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK
203277. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
203278. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK
203279. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
203280. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK
203281. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
203282. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK
203283. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
203284. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK
203285. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
203286. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK
203287. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
203288. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK
203289. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
203290. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK
203291. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
203292. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK
203293. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
203294. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK
203295. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
203296. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK
203297. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
203298. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK
203299. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
203300. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK
203301. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
203302. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK
203303. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
203304. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK
203305. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
203306. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK
203307. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
203308. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK
203309. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
203310. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK
203311. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
203312. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK
203313. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
203314. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK
203315. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
203316. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK
203317. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
203318. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK
203319. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
203320. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK
203321. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
203322. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK
203323. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
203324. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK
203325. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
203326. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK
203327. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
203328. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK
203329. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
203330. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK
203331. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
203332. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK
203333. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
203334. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK
203335. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
203336. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK
203337. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
203338. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK
203339. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
203340. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK
203341. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
203342. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK
203343. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
203344. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK
203345. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
203346. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK
203347. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
203348. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK
203349. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
203350. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK
203351. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
203352. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK
203353. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
203354. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK
203355. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
203356. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK
203357. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
203358. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK
203359. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
203360. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK
203361. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
203362. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK
203363. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
203364. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK
203365. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
203366. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK
203367. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
203368. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK
203369. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
203370. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK
203371. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
203372. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK
203373. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
203374. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK
203375. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
203376. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK
203377. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
203378. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK
203379. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
203380. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK
203381. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
203382. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK
203383. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
203384. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK
203385. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
203386. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK
203387. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
203388. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK
203389. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
203390. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK
203391. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
203392. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK
203393. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
203394. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK
203395. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
203396. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK
203397. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
203398. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK
203399. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
203400. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK
203401. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
203402. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK
203403. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
203404. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK
203405. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
203406. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK
203407. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
203408. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK
203409. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
203410. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK
203411. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
203412. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK
203413. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
203414. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK
203415. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
203416. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK
203417. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
203418. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK
203419. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
203420. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK
203421. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
203422. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK
203423. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
203424. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK
203425. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
203426. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK
203427. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
203428. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK
203429. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
203430. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK
203431. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
203432. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK
203433. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
203434. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK
203435. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
203436. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK
203437. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
203438. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK
203439. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
203440. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK
203441. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
203442. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK
203443. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
203444. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK
203445. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
203446. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK
203447. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
203448. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK
203449. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
203450. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK
203451. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
203452. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK
203453. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
203454. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK
203455. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
203456. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK
203457. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
203458. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK
203459. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
203460. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK
203461. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
203462. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK
203463. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
203464. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK
203465. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
203466. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK
203467. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
203468. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK
203469. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
203470. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK
203471. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
203472. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK
203473. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
203474. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK
203475. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
203476. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK
203477. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
203478. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK
203479. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
203480. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK
203481. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
203482. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK
203483. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
203484. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK
203485. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
203486. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK
203487. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
203488. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK
203489. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
203490. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK
203491. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
203492. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK
203493. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
203494. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK
203495. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
203496. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK
203497. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
203498. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK
203499. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
203500. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK
203501. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
203502. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK
203503. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
203504. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK
203505. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
203506. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK
203507. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
203508. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK
203509. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
203510. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK
203511. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
203512. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK
203513. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
203514. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK
203515. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
203516. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK
203517. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
203518. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK
203519. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
203520. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK
203521. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
203522. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK
203523. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
203524. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK
203525. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
203526. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK
203527. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
203528. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK
203529. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
203530. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK
203531. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
203532. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK
203533. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
203534. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK
203535. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
203536. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK
203537. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
203538. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK
203539. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
203540. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK
203541. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
203542. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK
203543. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
203544. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK
203545. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
203546. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK
203547. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
203548. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK
203549. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
203550. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK
203551. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
203552. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK
203553. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
203554. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK
203555. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
203556. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK
203557. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
203558. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK
203559. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
203560. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK
203561. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
203562. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK
203563. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
203564. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK
203565. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
203566. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK
203567. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
203568. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK
203569. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
203570. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK
203571. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
203572. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK
203573. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
203574. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK
203575. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
203576. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK
203577. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
203578. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK
203579. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
203580. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK
203581. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
203582. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK
203583. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
203584. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK
203585. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
203586. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK
203587. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
203588. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK
203589. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
203590. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK
203591. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
203592. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK
203593. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
203594. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK
203595. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
203596. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK
203597. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
203598. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK
203599. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
203600. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK
203601. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
203602. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK
203603. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
203604. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK
203605. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
203606. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK
203607. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
203608. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK
203609. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
203610. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK
203611. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
203612. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK
203613. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
203614. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK
203615. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
203616. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK
203617. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
203618. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK
203619. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
203620. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK
203621. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
203622. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK
203623. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
203624. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK
203625. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
203626. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK
203627. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
203628. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK
203629. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
203630. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK
203631. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
203632. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK
203633. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
203634. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK
203635. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
203636. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK
203637. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
203638. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK
203639. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
203640. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK
203641. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
203642. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK
203643. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
203644. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK
203645. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
203646. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK
203647. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
203648. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK
203649. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
203650. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK
203651. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
203652. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK
203653. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
203654. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK
203655. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
203656. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK
203657. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
203658. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK
203659. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
203660. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK
203661. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
203662. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK
203663. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
203664. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK
203665. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
203666. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK
203667. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
203668. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK
203669. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
203670. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK
203671. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
203672. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK
203673. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
203674. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK
203675. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
203676. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK
203677. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
203678. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK
203679. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
203680. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK
203681. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
203682. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK
203683. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
203684. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK
203685. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
203686. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK
203687. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
203688. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK
203689. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
203690. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK
203691. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
203692. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK
203693. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
203694. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK
203695. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
203696. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK
203697. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
203698. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK
203699. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
203700. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK
203701. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
203702. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK
203703. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
203704. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK
203705. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
203706. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK
203707. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
203708. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK
203709. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
203710. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK
203711. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
203712. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK
203713. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
203714. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK
203715. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
203716. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK
203717. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
203718. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK
203719. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
203720. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK
203721. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
203722. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK
203723. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
203724. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK
203725. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
203726. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK
203727. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
203728. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK
203729. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
203730. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK
203731. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
203732. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK
203733. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
203734. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK
203735. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
203736. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK
203737. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
203738. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK
203739. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
203740. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK
203741. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
203742. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK
203743. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
203744. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK
203745. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
203746. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK
203747. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
203748. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK
203749. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
203750. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK
203751. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
203752. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK
203753. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
203754. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK
203755. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
203756. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK
203757. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
203758. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK
203759. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
203760. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK
203761. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
203762. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK
203763. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
203764. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK
203765. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
203766. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK
203767. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
203768. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK
203769. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
203770. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK
203771. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
203772. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK
203773. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
203774. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK
203775. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
203776. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK
203777. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
203778. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK
203779. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
203780. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK
203781. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
203782. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK
203783. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
203784. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK
203785. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
203786. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK
203787. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
203788. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK
203789. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
203790. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK
203791. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
203792. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK
203793. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
203794. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK
203795. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
203796. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK
203797. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
203798. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK
203799. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
203800. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK
203801. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
203802. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK
203803. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
203804. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK
203805. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
203806. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK
203807. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
203808. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK
203809. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
203810. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK
203811. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
203812. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK
203813. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
203814. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK
203815. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
203816. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK
203817. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
203818. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK
203819. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
203820. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK
203821. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
203822. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK
203823. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
203824. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK
203825. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
203826. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK
203827. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
203828. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK
203829. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
203830. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK
203831. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
203832. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK
203833. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
203834. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK
203835. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
203836. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK
203837. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
203838. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK
203839. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
203840. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK
203841. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
203842. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK
203843. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
203844. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK
203845. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
203846. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK
203847. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
203848. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK
203849. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
203850. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK
203851. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
203852. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK
203853. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
203854. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK
203855. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
203856. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK
203857. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
203858. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK
203859. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
203860. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK
203861. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
203862. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK
203863. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
203864. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK
203865. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
203866. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK
203867. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
203868. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK
203869. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
203870. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK
203871. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
203872. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK
203873. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
203874. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK
203875. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
203876. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK
203877. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
203878. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK
203879. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
203880. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK
203881. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
203882. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK
203883. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
203884. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK
203885. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
203886. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK
203887. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
203888. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK
203889. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
203890. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK
203891. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
203892. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK
203893. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
203894. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK
203895. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
203896. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK
203897. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
203898. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK
203899. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
203900. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK
203901. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
203902. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK
203903. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
203904. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK
203905. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
203906. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK
203907. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
203908. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK
203909. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
203910. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK
203911. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
203912. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK
203913. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
203914. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK
203915. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
203916. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK
203917. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
203918. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK
203919. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
203920. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK
203921. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
203922. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK
203923. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
203924. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK
203925. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
203926. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK
203927. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
203928. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK
203929. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
203930. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK
203931. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
203932. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK
203933. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
203934. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK
203935. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
203936. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK
203937. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
203938. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK
203939. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
203940. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK
203941. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
203942. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK
203943. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
203944. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK
203945. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
203946. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK
203947. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
203948. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK
203949. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
203950. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK
203951. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
203952. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK
203953. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
203954. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK
203955. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
203956. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK
203957. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
203958. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK
203959. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
203960. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK
203961. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
203962. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK
203963. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
203964. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK
203965. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
203966. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK
203967. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
203968. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK
203969. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
203970. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK
203971. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
203972. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK
203973. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
203974. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK
203975. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
203976. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK
203977. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
203978. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK
203979. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
203980. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK
203981. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
203982. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK
203983. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
203984. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK
203985. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
203986. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK
203987. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
203988. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK
203989. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
203990. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK
203991. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
203992. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK
203993. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
203994. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK
203995. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
203996. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK
203997. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
203998. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK
203999. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
204000. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK
204001. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
204002. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK
204003. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
204004. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK
204005. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
204006. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK
204007. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
204008. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK
204009. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
204010. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK
204011. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
204012. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK
204013. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
204014. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK
204015. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
204016. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK
204017. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
204018. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK
204019. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
204020. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK
204021. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
204022. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK
204023. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
204024. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK
204025. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
204026. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK
204027. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
204028. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK
204029. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
204030. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK
204031. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
204032. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK
204033. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
204034. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK
204035. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
204036. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK
204037. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
204038. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK
204039. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
204040. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK
204041. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
204042. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK
204043. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
204044. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK
204045. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
204046. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK
204047. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
204048. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK
204049. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
204050. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK
204051. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
204052. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK
204053. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
204054. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK
204055. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
204056. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK
204057. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
204058. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK
204059. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
204060. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK
204061. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
204062. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK
204063. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
204064. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK
204065. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
204066. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK
204067. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
204068. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK
204069. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
204070. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK
204071. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
204072. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK
204073. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
204074. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK
204075. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
204076. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK
204077. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
204078. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK
204079. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
204080. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK
204081. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
204082. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK
204083. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
204084. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK
204085. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
204086. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK
204087. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
204088. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK
204089. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
204090. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK
204091. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
204092. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK
204093. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
204094. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK
204095. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
204096. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK
204097. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
204098. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK
204099. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
204100. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK
204101. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
204102. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK
204103. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
204104. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK
204105. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
204106. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK
204107. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
204108. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK
204109. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
204110. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK
204111. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
204112. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK
204113. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
204114. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK
204115. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
204116. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK
204117. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
204118. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
204119. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
204120. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
204121. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
204122. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
204123. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
204124. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
204125. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
204126. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
204127. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
204128. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
204129. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
204130. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
204131. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
204132. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
204133. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
204134. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
204135. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
204136. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
204137. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
204138. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
204139. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
204140. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
204141. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
204142. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
204143. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
204144. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
204145. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
204146. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
204147. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
204148. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
204149. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
204150. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
204151. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
204152. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
204153. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
204154. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
204155. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
204156. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
204157. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
204158. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK
204159. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
204160. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK
204161. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT
204162. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK
204163. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
204164. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK
204165. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
204166. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK
204167. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
204168. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK
204169. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
204170. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK
204171. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
204172. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK
204173. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
204174. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK
204175. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
204176. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK
204177. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
204178. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK
204179. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
204180. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK
204181. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
204182. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK
204183. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
204184. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK
204185. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
204186. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK
204187. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
204188. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK
204189. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
204190. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK
204191. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
204192. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK
204193. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
204194. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK
204195. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
204196. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK
204197. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
204198. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK
204199. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
204200. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK
204201. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
204202. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK
204203. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
204204. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK
204205. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
204206. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK
204207. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
204208. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK
204209. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
204210. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK
204211. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
204212. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK
204213. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
204214. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK
204215. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
204216. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK
204217. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
204218. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK
204219. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
204220. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK
204221. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
204222. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK
204223. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
204224. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK
204225. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
204226. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK
204227. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
204228. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK
204229. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
204230. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK
204231. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
204232. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK
204233. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
204234. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK
204235. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
204236. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK
204237. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
204238. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK
204239. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
204240. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK
204241. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
204242. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK
204243. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
204244. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK
204245. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
204246. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK
204247. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
204248. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK
204249. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
204250. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK
204251. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
204252. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK
204253. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
204254. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK
204255. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
204256. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK
204257. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
204258. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK
204259. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
204260. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK
204261. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
204262. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK
204263. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
204264. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK
204265. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
204266. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK
204267. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
204268. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK
204269. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
204270. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK
204271. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
204272. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK
204273. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
204274. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK
204275. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
204276. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK
204277. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
204278. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK
204279. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
204280. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK
204281. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
204282. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK
204283. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
204284. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK
204285. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
204286. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK
204287. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
204288. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK
204289. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
204290. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK
204291. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
204292. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK
204293. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
204294. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK
204295. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
204296. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK
204297. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
204298. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK
204299. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
204300. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK
204301. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
204302. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK
204303. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
204304. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK
204305. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
204306. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK
204307. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
204308. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK
204309. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
204310. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK
204311. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
204312. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK
204313. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
204314. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK
204315. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
204316. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK
204317. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
204318. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK
204319. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
204320. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK
204321. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
204322. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK
204323. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
204324. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK
204325. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
204326. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK
204327. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
204328. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK
204329. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
204330. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK
204331. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
204332. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK
204333. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
204334. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK
204335. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
204336. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK
204337. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
204338. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK
204339. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
204340. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK
204341. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
204342. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK
204343. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
204344. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK
204345. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
204346. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK
204347. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
204348. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK
204349. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
204350. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK
204351. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
204352. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK
204353. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
204354. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK
204355. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
204356. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK
204357. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
204358. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK
204359. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
204360. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK
204361. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
204362. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK
204363. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
204364. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK
204365. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
204366. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK
204367. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
204368. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK
204369. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
204370. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK
204371. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
204372. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK
204373. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
204374. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK
204375. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
204376. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK
204377. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
204378. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK
204379. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
204380. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK
204381. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
204382. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK
204383. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
204384. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK
204385. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
204386. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK
204387. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
204388. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK
204389. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
204390. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK
204391. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
204392. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK
204393. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
204394. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK
204395. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
204396. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK
204397. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
204398. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK
204399. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
204400. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK
204401. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
204402. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK
204403. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
204404. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK
204405. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
204406. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK
204407. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
204408. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK
204409. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
204410. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK
204411. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
204412. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK
204413. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
204414. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK
204415. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
204416. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK
204417. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
204418. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK
204419. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
204420. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK
204421. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
204422. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK
204423. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
204424. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK
204425. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
204426. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK
204427. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
204428. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK
204429. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
204430. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK
204431. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
204432. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK
204433. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
204434. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK
204435. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
204436. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK
204437. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
204438. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK
204439. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
204440. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK
204441. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
204442. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK
204443. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
204444. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK
204445. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
204446. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK
204447. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
204448. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK
204449. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
204450. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK
204451. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
204452. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK
204453. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
204454. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK
204455. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
204456. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK
204457. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
204458. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK
204459. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
204460. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK
204461. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
204462. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK
204463. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
204464. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK
204465. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
204466. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK
204467. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
204468. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK
204469. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
204470. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK
204471. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
204472. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK
204473. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
204474. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK
204475. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
204476. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK
204477. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
204478. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK
204479. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
204480. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK
204481. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
204482. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK
204483. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
204484. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK
204485. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
204486. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK
204487. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
204488. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK
204489. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
204490. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK
204491. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
204492. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK
204493. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
204494. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK
204495. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
204496. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK
204497. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
204498. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK
204499. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
204500. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK
204501. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
204502. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK
204503. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
204504. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK
204505. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
204506. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK
204507. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
204508. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK
204509. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
204510. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK
204511. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
204512. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK
204513. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
204514. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK
204515. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
204516. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK
204517. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
204518. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK
204519. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
204520. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK
204521. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
204522. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK
204523. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
204524. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK
204525. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
204526. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK
204527. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
204528. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK
204529. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
204530. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK
204531. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
204532. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK
204533. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
204534. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK
204535. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
204536. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK
204537. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
204538. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK
204539. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
204540. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK
204541. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
204542. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK
204543. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
204544. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK
204545. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
204546. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK
204547. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
204548. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK
204549. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
204550. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK
204551. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
204552. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK
204553. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
204554. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK
204555. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
204556. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK
204557. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
204558. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK
204559. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
204560. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK
204561. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
204562. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK
204563. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
204564. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK
204565. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
204566. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK
204567. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
204568. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK
204569. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
204570. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK
204571. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
204572. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK
204573. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
204574. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK
204575. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
204576. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK
204577. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
204578. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK
204579. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
204580. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK
204581. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
204582. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK
204583. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
204584. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK
204585. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
204586. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK
204587. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
204588. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK
204589. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
204590. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK
204591. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
204592. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK
204593. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
204594. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK
204595. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
204596. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK
204597. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
204598. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK
204599. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
204600. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK
204601. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
204602. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK
204603. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
204604. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK
204605. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
204606. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK
204607. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
204608. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK
204609. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
204610. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK
204611. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
204612. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK
204613. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
204614. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK
204615. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
204616. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK
204617. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
204618. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK
204619. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
204620. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK
204621. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
204622. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK
204623. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
204624. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK
204625. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
204626. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK
204627. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
204628. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK
204629. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
204630. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK
204631. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
204632. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK
204633. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
204634. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK
204635. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
204636. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK
204637. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
204638. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK
204639. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
204640. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK
204641. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
204642. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK
204643. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
204644. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK
204645. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
204646. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK
204647. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
204648. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK
204649. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
204650. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK
204651. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
204652. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK
204653. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
204654. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK
204655. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
204656. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK
204657. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
204658. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK
204659. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
204660. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK
204661. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
204662. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK
204663. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
204664. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK
204665. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
204666. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK
204667. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
204668. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK
204669. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
204670. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK
204671. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
204672. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK
204673. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
204674. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK
204675. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
204676. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK
204677. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
204678. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK
204679. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
204680. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK
204681. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
204682. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK
204683. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
204684. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK
204685. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
204686. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK
204687. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
204688. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK
204689. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
204690. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK
204691. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
204692. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK
204693. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
204694. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK
204695. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
204696. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK
204697. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
204698. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK
204699. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
204700. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK
204701. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
204702. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK
204703. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
204704. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK
204705. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
204706. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK
204707. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
204708. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK
204709. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
204710. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK
204711. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
204712. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK
204713. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
204714. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK
204715. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
204716. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK
204717. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
204718. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK
204719. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
204720. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK
204721. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
204722. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK
204723. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
204724. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK
204725. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
204726. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK
204727. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
204728. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK
204729. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
204730. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK
204731. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
204732. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK
204733. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
204734. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK
204735. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
204736. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK
204737. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
204738. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK
204739. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
204740. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK
204741. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
204742. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK
204743. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
204744. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK
204745. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
204746. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK
204747. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
204748. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK
204749. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
204750. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK
204751. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
204752. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK
204753. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
204754. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK
204755. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
204756. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK
204757. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
204758. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK
204759. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
204760. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK
204761. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
204762. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK
204763. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
204764. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK
204765. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
204766. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK
204767. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
204768. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK
204769. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
204770. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK
204771. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
204772. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK
204773. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
204774. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK
204775. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
204776. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK
204777. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
204778. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK
204779. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
204780. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK
204781. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
204782. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK
204783. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
204784. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK
204785. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
204786. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK
204787. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
204788. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK
204789. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
204790. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK
204791. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
204792. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK
204793. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
204794. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK
204795. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
204796. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK
204797. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
204798. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK
204799. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
204800. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK
204801. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
204802. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK
204803. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
204804. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK
204805. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
204806. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK
204807. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
204808. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK
204809. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
204810. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK
204811. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
204812. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK
204813. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
204814. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK
204815. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
204816. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK
204817. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
204818. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK
204819. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
204820. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK
204821. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
204822. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK
204823. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
204824. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK
204825. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
204826. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK
204827. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
204828. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK
204829. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
204830. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK
204831. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
204832. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK
204833. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
204834. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK
204835. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
204836. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK
204837. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
204838. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK
204839. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
204840. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK
204841. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
204842. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK
204843. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
204844. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK
204845. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
204846. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK
204847. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
204848. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK
204849. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
204850. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK
204851. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
204852. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK
204853. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
204854. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK
204855. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
204856. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK
204857. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
204858. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK
204859. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
204860. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK
204861. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
204862. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK
204863. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
204864. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK
204865. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
204866. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK
204867. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
204868. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK
204869. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
204870. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK
204871. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
204872. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK
204873. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
204874. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK
204875. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
204876. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK
204877. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
204878. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK
204879. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
204880. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK
204881. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
204882. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK
204883. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
204884. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK
204885. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
204886. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK
204887. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
204888. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK
204889. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
204890. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK
204891. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
204892. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK
204893. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
204894. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK
204895. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
204896. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK
204897. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
204898. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK
204899. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
204900. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK
204901. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
204902. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK
204903. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
204904. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK
204905. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
204906. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK
204907. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
204908. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK
204909. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
204910. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK
204911. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
204912. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK
204913. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
204914. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK
204915. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
204916. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK
204917. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
204918. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK
204919. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
204920. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK
204921. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
204922. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK
204923. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
204924. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK
204925. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
204926. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK
204927. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
204928. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK
204929. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
204930. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK
204931. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
204932. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK
204933. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
204934. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK
204935. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
204936. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK
204937. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
204938. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK
204939. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
204940. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK
204941. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
204942. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK
204943. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
204944. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK
204945. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
204946. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK
204947. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
204948. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK
204949. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
204950. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK
204951. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
204952. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK
204953. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
204954. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK
204955. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
204956. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK
204957. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
204958. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK
204959. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
204960. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK
204961. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
204962. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK
204963. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
204964. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK
204965. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
204966. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK
204967. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
204968. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK
204969. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
204970. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK
204971. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
204972. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK
204973. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
204974. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK
204975. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
204976. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK
204977. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
204978. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK
204979. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
204980. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK
204981. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
204982. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK
204983. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
204984. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK
204985. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
204986. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK
204987. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
204988. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK
204989. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
204990. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK
204991. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
204992. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK
204993. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
204994. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK
204995. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
204996. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK
204997. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
204998. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK
204999. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
205000. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK
205001. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
205002. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK
205003. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
205004. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK
205005. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
205006. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK
205007. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
205008. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK
205009. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
205010. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK
205011. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
205012. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK
205013. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
205014. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK
205015. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
205016. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK
205017. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
205018. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK
205019. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
205020. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK
205021. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
205022. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK
205023. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
205024. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK
205025. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
205026. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK
205027. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
205028. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK
205029. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
205030. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK
205031. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
205032. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK
205033. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
205034. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK
205035. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
205036. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK
205037. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
205038. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK
205039. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
205040. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK
205041. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
205042. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK
205043. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
205044. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK
205045. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
205046. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK
205047. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
205048. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK
205049. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
205050. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK
205051. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
205052. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK
205053. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
205054. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK
205055. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
205056. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK
205057. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
205058. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK
205059. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
205060. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK
205061. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
205062. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK
205063. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
205064. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK
205065. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
205066. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK
205067. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
205068. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK
205069. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
205070. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK
205071. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
205072. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK
205073. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
205074. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK
205075. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
205076. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK
205077. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
205078. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK
205079. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
205080. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK
205081. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
205082. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK
205083. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
205084. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK
205085. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
205086. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK
205087. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
205088. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK
205089. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
205090. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK
205091. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
205092. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK
205093. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
205094. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK
205095. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
205096. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK
205097. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
205098. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK
205099. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
205100. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK
205101. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
205102. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK
205103. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
205104. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK
205105. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
205106. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK
205107. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
205108. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK
205109. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
205110. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK
205111. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
205112. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK
205113. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
205114. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK
205115. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
205116. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK
205117. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
205118. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK
205119. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
205120. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK
205121. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
205122. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK
205123. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
205124. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK
205125. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
205126. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK
205127. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
205128. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK
205129. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
205130. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK
205131. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
205132. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK
205133. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
205134. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK
205135. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
205136. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK
205137. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
205138. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK
205139. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
205140. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK
205141. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
205142. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK
205143. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
205144. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK
205145. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
205146. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK
205147. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
205148. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK
205149. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
205150. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK
205151. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
205152. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK
205153. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
205154. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK
205155. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
205156. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK
205157. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
205158. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK
205159. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
205160. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK
205161. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
205162. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK
205163. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
205164. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK
205165. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
205166. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK
205167. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
205168. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK
205169. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
205170. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK
205171. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
205172. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK
205173. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
205174. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK
205175. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
205176. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK
205177. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
205178. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK
205179. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
205180. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK
205181. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
205182. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK
205183. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
205184. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK
205185. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
205186. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK
205187. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
205188. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK
205189. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
205190. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK
205191. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
205192. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK
205193. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
205194. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK
205195. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
205196. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK
205197. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
205198. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK
205199. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
205200. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK
205201. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
205202. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK
205203. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
205204. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK
205205. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
205206. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK
205207. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
205208. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK
205209. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
205210. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK
205211. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
205212. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK
205213. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
205214. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK
205215. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
205216. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK
205217. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
205218. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK
205219. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
205220. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK
205221. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
205222. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK
205223. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
205224. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK
205225. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
205226. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK
205227. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
205228. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK
205229. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
205230. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK
205231. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
205232. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK
205233. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
205234. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK
205235. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
205236. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK
205237. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
205238. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK
205239. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
205240. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK
205241. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
205242. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK
205243. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
205244. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK
205245. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
205246. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK
205247. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
205248. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK
205249. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
205250. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK
205251. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
205252. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK
205253. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
205254. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK
205255. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
205256. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK
205257. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
205258. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK
205259. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
205260. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK
205261. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
205262. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK
205263. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
205264. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK
205265. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
205266. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK
205267. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
205268. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK
205269. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
205270. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK
205271. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
205272. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK
205273. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
205274. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK
205275. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
205276. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK
205277. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
205278. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK
205279. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
205280. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK
205281. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
205282. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK
205283. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
205284. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK
205285. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
205286. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK
205287. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
205288. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK
205289. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
205290. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK
205291. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
205292. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK
205293. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
205294. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK
205295. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
205296. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK
205297. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
205298. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK
205299. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
205300. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK
205301. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
205302. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK
205303. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
205304. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK
205305. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
205306. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK
205307. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
205308. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK
205309. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
205310. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK
205311. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
205312. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK
205313. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
205314. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK
205315. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
205316. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK
205317. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
205318. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK
205319. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
205320. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK
205321. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
205322. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK
205323. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
205324. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK
205325. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
205326. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK
205327. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
205328. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK
205329. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
205330. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK
205331. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
205332. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK
205333. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
205334. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK
205335. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
205336. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK
205337. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
205338. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK
205339. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
205340. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK
205341. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
205342. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK
205343. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
205344. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK
205345. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
205346. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK
205347. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
205348. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK
205349. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
205350. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK
205351. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
205352. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK
205353. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
205354. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK
205355. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
205356. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK
205357. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
205358. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK
205359. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
205360. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK
205361. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
205362. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK
205363. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
205364. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK
205365. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
205366. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK
205367. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
205368. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK
205369. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
205370. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK
205371. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
205372. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK
205373. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
205374. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK
205375. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
205376. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK
205377. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
205378. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK
205379. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
205380. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK
205381. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
205382. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK
205383. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
205384. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK
205385. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
205386. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK
205387. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
205388. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK
205389. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
205390. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK
205391. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
205392. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK
205393. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
205394. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK
205395. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
205396. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK
205397. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
205398. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK
205399. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
205400. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK
205401. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
205402. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK
205403. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
205404. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK
205405. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
205406. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK
205407. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
205408. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK
205409. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
205410. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK
205411. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
205412. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK
205413. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
205414. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK
205415. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
205416. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK
205417. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
205418. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK
205419. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
205420. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK
205421. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
205422. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK
205423. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
205424. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK
205425. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
205426. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK
205427. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
205428. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK
205429. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
205430. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK
205431. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
205432. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK
205433. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
205434. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK
205435. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
205436. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK
205437. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
205438. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK
205439. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
205440. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK
205441. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
205442. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK
205443. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
205444. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK
205445. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
205446. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK
205447. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
205448. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK
205449. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
205450. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK
205451. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
205452. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK
205453. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
205454. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK
205455. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
205456. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK
205457. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
205458. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK
205459. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
205460. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK
205461. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
205462. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK
205463. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
205464. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK
205465. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
205466. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK
205467. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
205468. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK
205469. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
205470. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK
205471. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
205472. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK
205473. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
205474. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK
205475. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
205476. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK
205477. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
205478. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK
205479. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
205480. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK
205481. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
205482. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK
205483. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
205484. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK
205485. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
205486. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK
205487. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
205488. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK
205489. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
205490. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK
205491. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
205492. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK
205493. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
205494. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK
205495. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
205496. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK
205497. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
205498. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK
205499. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
205500. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK
205501. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
205502. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK
205503. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
205504. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK
205505. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
205506. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK
205507. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
205508. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK
205509. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
205510. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK
205511. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
205512. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK
205513. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
205514. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK
205515. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
205516. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK
205517. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
205518. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK
205519. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
205520. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK
205521. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
205522. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK
205523. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
205524. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK
205525. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
205526. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK
205527. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
205528. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK
205529. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
205530. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK
205531. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
205532. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK
205533. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
205534. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK
205535. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
205536. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK
205537. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
205538. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK
205539. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
205540. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK
205541. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
205542. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK
205543. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
205544. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK
205545. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
205546. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK
205547. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
205548. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK
205549. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
205550. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK
205551. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
205552. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK
205553. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
205554. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK
205555. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
205556. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK
205557. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
205558. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK
205559. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
205560. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK
205561. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
205562. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK
205563. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
205564. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK
205565. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
205566. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK
205567. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
205568. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK
205569. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
205570. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK
205571. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
205572. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK
205573. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
205574. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK
205575. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
205576. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK
205577. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
205578. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK
205579. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
205580. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK
205581. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
205582. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK
205583. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
205584. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK
205585. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
205586. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK
205587. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
205588. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK
205589. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
205590. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK
205591. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
205592. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK
205593. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
205594. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK
205595. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
205596. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK
205597. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
205598. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK
205599. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
205600. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK
205601. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
205602. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK
205603. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
205604. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK
205605. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
205606. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK
205607. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
205608. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK
205609. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
205610. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK
205611. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
205612. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK
205613. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
205614. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK
205615. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
205616. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK
205617. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
205618. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK
205619. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
205620. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK
205621. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
205622. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK
205623. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
205624. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK
205625. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
205626. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK
205627. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
205628. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK
205629. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
205630. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK
205631. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
205632. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK
205633. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
205634. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK
205635. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
205636. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK
205637. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
205638. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK
205639. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
205640. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK
205641. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
205642. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK
205643. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
205644. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK
205645. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
205646. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK
205647. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
205648. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK
205649. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
205650. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK
205651. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
205652. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK
205653. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
205654. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK
205655. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
205656. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK
205657. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
205658. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK
205659. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
205660. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK
205661. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
205662. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK
205663. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
205664. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK
205665. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
205666. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK
205667. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
205668. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK
205669. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
205670. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK
205671. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
205672. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK
205673. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
205674. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK
205675. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
205676. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK
205677. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
205678. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK
205679. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
205680. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK
205681. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
205682. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK
205683. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
205684. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK
205685. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
205686. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK
205687. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
205688. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK
205689. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
205690. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK
205691. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
205692. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK
205693. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
205694. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK
205695. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
205696. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK
205697. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
205698. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK
205699. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
205700. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK
205701. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
205702. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK
205703. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
205704. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK
205705. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
205706. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK
205707. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
205708. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK
205709. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
205710. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK
205711. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
205712. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK
205713. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
205714. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK
205715. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
205716. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK
205717. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
205718. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK
205719. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
205720. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK
205721. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
205722. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK
205723. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
205724. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK
205725. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
205726. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK
205727. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
205728. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK
205729. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
205730. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK
205731. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
205732. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK
205733. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
205734. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK
205735. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
205736. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK
205737. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
205738. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK
205739. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
205740. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK
205741. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
205742. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK
205743. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
205744. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK
205745. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
205746. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK
205747. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
205748. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK
205749. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
205750. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK
205751. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
205752. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK
205753. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
205754. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK
205755. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
205756. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK
205757. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
205758. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK
205759. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
205760. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK
205761. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
205762. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK
205763. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
205764. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK
205765. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
205766. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK
205767. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
205768. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK
205769. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
205770. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK
205771. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
205772. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK
205773. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
205774. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK
205775. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
205776. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK
205777. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
205778. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK
205779. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
205780. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK
205781. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
205782. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK
205783. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
205784. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK
205785. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
205786. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK
205787. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
205788. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK
205789. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
205790. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK
205791. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
205792. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK
205793. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
205794. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK
205795. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
205796. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK
205797. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
205798. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK
205799. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
205800. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK
205801. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
205802. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK
205803. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
205804. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK
205805. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
205806. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK
205807. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
205808. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK
205809. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
205810. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK
205811. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
205812. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK
205813. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
205814. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK
205815. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
205816. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK
205817. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
205818. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK
205819. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
205820. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK
205821. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
205822. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK
205823. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
205824. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK
205825. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
205826. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK
205827. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
205828. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK
205829. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
205830. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK
205831. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
205832. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK
205833. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
205834. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK
205835. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
205836. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK
205837. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
205838. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK
205839. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
205840. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK
205841. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
205842. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK
205843. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
205844. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK
205845. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
205846. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK
205847. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
205848. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK
205849. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
205850. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK
205851. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
205852. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK
205853. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
205854. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK
205855. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
205856. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK
205857. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
205858. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK
205859. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
205860. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK
205861. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
205862. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK
205863. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
205864. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK
205865. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
205866. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK
205867. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
205868. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK
205869. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
205870. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK
205871. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
205872. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK
205873. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
205874. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK
205875. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
205876. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK
205877. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
205878. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK
205879. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
205880. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK
205881. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
205882. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK
205883. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
205884. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK
205885. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
205886. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK
205887. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
205888. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK
205889. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
205890. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK
205891. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
205892. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK
205893. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
205894. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK
205895. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
205896. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK
205897. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
205898. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK
205899. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
205900. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK
205901. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
205902. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK
205903. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
205904. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK
205905. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
205906. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK
205907. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
205908. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK
205909. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
205910. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK
205911. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
205912. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK
205913. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
205914. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK
205915. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
205916. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK
205917. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
205918. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK
205919. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
205920. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK
205921. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
205922. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK
205923. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
205924. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK
205925. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
205926. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK
205927. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
205928. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK
205929. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
205930. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK
205931. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
205932. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK
205933. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
205934. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK
205935. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
205936. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK
205937. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
205938. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK
205939. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
205940. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK
205941. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
205942. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK
205943. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
205944. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK
205945. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
205946. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK
205947. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
205948. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK
205949. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
205950. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK
205951. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
205952. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK
205953. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
205954. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK
205955. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
205956. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK
205957. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
205958. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK
205959. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
205960. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK
205961. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
205962. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK
205963. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
205964. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK
205965. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
205966. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK
205967. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
205968. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK
205969. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
205970. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK
205971. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
205972. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK
205973. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
205974. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK
205975. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
205976. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK
205977. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
205978. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK
205979. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
205980. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK
205981. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
205982. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK
205983. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
205984. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK
205985. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
205986. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK
205987. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
205988. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK
205989. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
205990. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK
205991. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
205992. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK
205993. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
205994. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK
205995. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
205996. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK
205997. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
205998. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK
205999. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
206000. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK
206001. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
206002. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK
206003. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
206004. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK
206005. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
206006. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK
206007. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
206008. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK
206009. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
206010. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK
206011. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
206012. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK
206013. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
206014. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK
206015. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
206016. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK
206017. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
206018. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK
206019. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
206020. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK
206021. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
206022. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK
206023. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
206024. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK
206025. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
206026. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK
206027. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
206028. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK
206029. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
206030. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK
206031. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
206032. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK
206033. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
206034. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK
206035. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
206036. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK
206037. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
206038. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK
206039. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
206040. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK
206041. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
206042. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK
206043. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
206044. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK
206045. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
206046. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK
206047. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
206048. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK
206049. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
206050. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK
206051. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
206052. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK
206053. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
206054. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK
206055. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
206056. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK
206057. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
206058. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK
206059. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
206060. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK
206061. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
206062. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK
206063. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
206064. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK
206065. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
206066. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK
206067. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
206068. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK
206069. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
206070. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK
206071. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
206072. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK
206073. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
206074. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK
206075. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
206076. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK
206077. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
206078. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK
206079. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
206080. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK
206081. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
206082. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK
206083. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
206084. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK
206085. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
206086. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK
206087. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
206088. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK
206089. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
206090. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK
206091. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
206092. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK
206093. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
206094. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK
206095. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
206096. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK
206097. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
206098. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK
206099. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
206100. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK
206101. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
206102. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK
206103. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
206104. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK
206105. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
206106. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK
206107. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
206108. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK
206109. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
206110. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK
206111. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
206112. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK
206113. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
206114. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK
206115. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
206116. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK
206117. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
206118. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK
206119. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
206120. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK
206121. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
206122. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK
206123. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
206124. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK
206125. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
206126. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK
206127. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
206128. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK
206129. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
206130. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK
206131. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
206132. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK
206133. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
206134. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK
206135. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
206136. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK
206137. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
206138. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK
206139. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
206140. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK
206141. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
206142. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK
206143. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
206144. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK
206145. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
206146. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK
206147. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
206148. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK
206149. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
206150. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK
206151. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
206152. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK
206153. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
206154. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK
206155. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
206156. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK
206157. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
206158. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK
206159. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
206160. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK
206161. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
206162. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK
206163. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
206164. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK
206165. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
206166. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK
206167. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
206168. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK
206169. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
206170. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK
206171. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
206172. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK
206173. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
206174. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK
206175. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
206176. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK
206177. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
206178. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK
206179. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
206180. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK
206181. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
206182. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK
206183. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
206184. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK
206185. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
206186. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK
206187. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
206188. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK
206189. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
206190. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK
206191. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
206192. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK
206193. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
206194. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK
206195. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
206196. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK
206197. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
206198. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK
206199. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
206200. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK
206201. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
206202. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK
206203. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
206204. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK
206205. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
206206. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK
206207. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
206208. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK
206209. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
206210. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK
206211. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
206212. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK
206213. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
206214. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK
206215. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
206216. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK
206217. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
206218. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK
206219. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
206220. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK
206221. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
206222. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK
206223. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
206224. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK
206225. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
206226. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK
206227. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
206228. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK
206229. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
206230. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK
206231. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
206232. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK
206233. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
206234. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK
206235. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
206236. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK
206237. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
206238. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK
206239. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
206240. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK
206241. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
206242. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK
206243. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
206244. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK
206245. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
206246. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK
206247. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
206248. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK
206249. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
206250. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK
206251. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
206252. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK
206253. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
206254. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK
206255. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
206256. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK
206257. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
206258. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK
206259. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
206260. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK
206261. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
206262. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK
206263. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
206264. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK
206265. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
206266. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK
206267. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
206268. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK
206269. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
206270. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK
206271. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
206272. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK
206273. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
206274. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK
206275. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
206276. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK
206277. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
206278. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK
206279. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
206280. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK
206281. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
206282. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK
206283. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
206284. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK
206285. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
206286. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK
206287. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
206288. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK
206289. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
206290. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK
206291. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
206292. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK
206293. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
206294. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK
206295. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
206296. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK
206297. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
206298. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK
206299. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
206300. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK
206301. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
206302. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK
206303. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
206304. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK
206305. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
206306. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK
206307. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
206308. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK
206309. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
206310. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK
206311. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
206312. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK
206313. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
206314. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK
206315. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
206316. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK
206317. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
206318. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK
206319. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
206320. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK
206321. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
206322. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK
206323. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
206324. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK
206325. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
206326. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK
206327. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
206328. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK
206329. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
206330. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK
206331. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
206332. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK
206333. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
206334. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK
206335. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
206336. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK
206337. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
206338. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK
206339. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
206340. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK
206341. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
206342. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK
206343. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
206344. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK
206345. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
206346. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK
206347. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
206348. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK
206349. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
206350. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK
206351. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
206352. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK
206353. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
206354. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK
206355. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
206356. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK
206357. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
206358. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK
206359. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
206360. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK
206361. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
206362. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK
206363. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
206364. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK
206365. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
206366. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK
206367. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
206368. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK
206369. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
206370. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK
206371. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
206372. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK
206373. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
206374. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK
206375. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
206376. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK
206377. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
206378. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK
206379. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
206380. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK
206381. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
206382. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK
206383. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
206384. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK
206385. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
206386. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK
206387. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
206388. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK
206389. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
206390. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK
206391. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
206392. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK
206393. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
206394. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK
206395. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
206396. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK
206397. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
206398. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK
206399. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
206400. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK
206401. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
206402. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK
206403. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
206404. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK
206405. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
206406. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK
206407. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
206408. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK
206409. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
206410. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK
206411. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
206412. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK
206413. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
206414. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK
206415. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
206416. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK
206417. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
206418. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK
206419. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
206420. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK
206421. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
206422. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK
206423. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
206424. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK
206425. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
206426. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK
206427. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
206428. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK
206429. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
206430. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK
206431. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
206432. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK
206433. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
206434. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK
206435. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
206436. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK
206437. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
206438. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK
206439. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
206440. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK
206441. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
206442. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK
206443. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
206444. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK
206445. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
206446. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK
206447. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
206448. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK
206449. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
206450. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK
206451. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
206452. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK
206453. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
206454. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK
206455. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
206456. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK
206457. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
206458. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK
206459. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
206460. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK
206461. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
206462. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK
206463. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
206464. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK
206465. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
206466. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK
206467. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
206468. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK
206469. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
206470. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK
206471. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
206472. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK
206473. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
206474. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK
206475. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
206476. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK
206477. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
206478. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK
206479. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
206480. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK
206481. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
206482. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK
206483. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
206484. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK
206485. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
206486. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK
206487. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
206488. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK
206489. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
206490. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK
206491. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
206492. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK
206493. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
206494. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK
206495. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
206496. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK
206497. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
206498. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK
206499. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
206500. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK
206501. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
206502. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK
206503. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
206504. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK
206505. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
206506. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK
206507. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
206508. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK
206509. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
206510. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK
206511. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
206512. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK
206513. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
206514. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK
206515. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
206516. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK
206517. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
206518. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK
206519. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
206520. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK
206521. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
206522. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK
206523. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
206524. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK
206525. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
206526. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK
206527. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
206528. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK
206529. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
206530. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK
206531. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
206532. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK
206533. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
206534. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK
206535. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
206536. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK
206537. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
206538. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK
206539. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
206540. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK
206541. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
206542. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK
206543. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
206544. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK
206545. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
206546. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK
206547. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
206548. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK
206549. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
206550. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK
206551. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
206552. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK
206553. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
206554. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK
206555. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
206556. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK
206557. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
206558. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK
206559. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
206560. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK
206561. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
206562. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK
206563. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
206564. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK
206565. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
206566. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK
206567. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
206568. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK
206569. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
206570. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK
206571. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
206572. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK
206573. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
206574. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK
206575. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
206576. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK
206577. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
206578. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK
206579. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
206580. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK
206581. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
206582. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK
206583. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
206584. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK
206585. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
206586. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK
206587. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
206588. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK
206589. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
206590. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK
206591. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
206592. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK
206593. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
206594. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK
206595. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
206596. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK
206597. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
206598. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK
206599. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
206600. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK
206601. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
206602. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK
206603. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
206604. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK
206605. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
206606. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK
206607. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
206608. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK
206609. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
206610. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK
206611. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
206612. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK
206613. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
206614. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK
206615. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
206616. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK
206617. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
206618. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK
206619. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
206620. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK
206621. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
206622. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK
206623. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
206624. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK
206625. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
206626. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK
206627. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
206628. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK
206629. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
206630. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK
206631. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
206632. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK
206633. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
206634. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK
206635. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
206636. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK
206637. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
206638. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK
206639. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
206640. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK
206641. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
206642. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK
206643. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
206644. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK
206645. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
206646. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK
206647. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
206648. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK
206649. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
206650. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK
206651. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
206652. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK
206653. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
206654. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK
206655. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
206656. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK
206657. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
206658. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
206659. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
206660. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
206661. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
206662. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
206663. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
206664. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
206665. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
206666. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
206667. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
206668. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
206669. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
206670. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
206671. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
206672. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
206673. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
206674. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
206675. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
206676. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
206677. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
206678. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
206679. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
206680. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
206681. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
206682. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
206683. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
206684. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
206685. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
206686. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
206687. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
206688. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
206689. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
206690. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
206691. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
206692. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
206693. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
206694. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
206695. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
206696. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
206697. DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
206698. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK
206699. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT
206700. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK
206701. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT
206702. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK
206703. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT
206704. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK
206705. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT
206706. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK
206707. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT
206708. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK
206709. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT
206710. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK
206711. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT
206712. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK
206713. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT
206714. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
206715. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
206716. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
206717. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
206718. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
206719. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
206720. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
206721. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
206722. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
206723. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
206724. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
206725. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
206726. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
206727. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
206728. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
206729. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
206730. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
206731. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
206732. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
206733. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
206734. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
206735. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
206736. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
206737. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
206738. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
206739. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
206740. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
206741. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
206742. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
206743. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
206744. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
206745. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
206746. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
206747. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
206748. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
206749. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
206750. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
206751. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
206752. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
206753. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
206754. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
206755. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
206756. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
206757. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
206758. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
206759. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
206760. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
206761. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
206762. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
206763. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
206764. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
206765. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
206766. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
206767. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
206768. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
206769. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
206770. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
206771. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
206772. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
206773. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
206774. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
206775. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
206776. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
206777. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
206778. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
206779. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
206780. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
206781. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
206782. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
206783. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
206784. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
206785. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
206786. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
206787. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
206788. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
206789. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
206790. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
206791. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
206792. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
206793. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
206794. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
206795. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
206796. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
206797. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
206798. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
206799. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
206800. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
206801. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
206802. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
206803. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
206804. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
206805. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
206806. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
206807. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
206808. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
206809. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
206810. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
206811. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
206812. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
206813. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
206814. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
206815. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
206816. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
206817. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
206818. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
206819. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
206820. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
206821. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
206822. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
206823. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
206824. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
206825. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
206826. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
206827. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
206828. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
206829. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
206830. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
206831. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
206832. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
206833. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
206834. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
206835. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
206836. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
206837. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
206838. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
206839. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
206840. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
206841. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
206842. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
206843. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
206844. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
206845. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
206846. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
206847. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
206848. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
206849. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
206850. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
206851. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
206852. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
206853. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
206854. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
206855. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
206856. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
206857. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
206858. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
206859. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
206860. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
206861. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
206862. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
206863. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
206864. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
206865. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
206866. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
206867. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
206868. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
206869. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
206870. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
206871. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
206872. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
206873. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
206874. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
206875. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
206876. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
206877. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
206878. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
206879. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
206880. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
206881. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
206882. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
206883. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
206884. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
206885. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
206886. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
206887. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
206888. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
206889. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
206890. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
206891. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
206892. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
206893. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
206894. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
206895. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
206896. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
206897. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
206898. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
206899. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
206900. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
206901. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
206902. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
206903. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
206904. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
206905. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
206906. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
206907. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
206908. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
206909. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
206910. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
206911. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
206912. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
206913. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
206914. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
206915. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
206916. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
206917. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
206918. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
206919. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
206920. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
206921. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
206922. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
206923. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
206924. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
206925. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
206926. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
206927. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
206928. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
206929. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
206930. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
206931. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
206932. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
206933. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
206934. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
206935. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
206936. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
206937. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
206938. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
206939. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
206940. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
206941. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
206942. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
206943. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
206944. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
206945. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
206946. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
206947. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
206948. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
206949. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
206950. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
206951. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
206952. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
206953. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
206954. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
206955. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
206956. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK
206957. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
206958. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
206959. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
206960. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
206961. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
206962. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
206963. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
206964. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
206965. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
206966. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
206967. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
206968. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
206969. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
206970. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
206971. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
206972. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
206973. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
206974. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
206975. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
206976. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
206977. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
206978. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
206979. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
206980. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
206981. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
206982. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
206983. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
206984. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK
206985. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
206986. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
206987. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
206988. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
206989. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
206990. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK
206991. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT
206992. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
206993. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
206994. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
206995. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
206996. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
206997. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
206998. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
206999. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
207000. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
207001. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
207002. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
207003. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
207004. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
207005. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
207006. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
207007. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
207008. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
207009. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
207010. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
207011. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
207012. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
207013. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
207014. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
207015. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
207016. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
207017. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
207018. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
207019. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
207020. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
207021. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
207022. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
207023. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
207024. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
207025. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
207026. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
207027. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
207028. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
207029. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
207030. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
207031. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
207032. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
207033. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
207034. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
207035. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
207036. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
207037. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
207038. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
207039. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
207040. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
207041. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
207042. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
207043. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
207044. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
207045. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
207046. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
207047. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
207048. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
207049. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
207050. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
207051. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
207052. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
207053. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
207054. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
207055. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
207056. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
207057. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
207058. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
207059. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
207060. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
207061. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
207062. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
207063. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
207064. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
207065. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
207066. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
207067. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
207068. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
207069. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
207070. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
207071. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
207072. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
207073. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
207074. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
207075. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
207076. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
207077. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
207078. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
207079. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
207080. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
207081. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
207082. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
207083. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
207084. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
207085. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
207086. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
207087. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
207088. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
207089. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
207090. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
207091. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
207092. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
207093. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
207094. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
207095. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
207096. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
207097. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
207098. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
207099. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
207100. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
207101. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
207102. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
207103. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
207104. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
207105. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
207106. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
207107. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
207108. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
207109. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
207110. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
207111. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
207112. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
207113. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
207114. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
207115. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
207116. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
207117. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
207118. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
207119. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
207120. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
207121. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
207122. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
207123. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
207124. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
207125. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
207126. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
207127. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
207128. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
207129. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
207130. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
207131. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
207132. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
207133. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
207134. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
207135. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
207136. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
207137. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
207138. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
207139. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
207140. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
207141. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
207142. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
207143. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
207144. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
207145. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
207146. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
207147. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
207148. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
207149. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
207150. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
207151. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
207152. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
207153. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
207154. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
207155. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
207156. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
207157. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
207158. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
207159. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
207160. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
207161. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
207162. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
207163. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
207164. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
207165. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
207166. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
207167. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
207168. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
207169. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
207170. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
207171. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
207172. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
207173. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
207174. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
207175. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
207176. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
207177. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
207178. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
207179. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
207180. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
207181. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
207182. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
207183. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
207184. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
207185. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
207186. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
207187. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
207188. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
207189. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
207190. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
207191. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
207192. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
207193. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
207194. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
207195. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
207196. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
207197. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
207198. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
207199. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
207200. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
207201. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
207202. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
207203. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
207204. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
207205. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
207206. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
207207. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
207208. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
207209. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
207210. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
207211. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
207212. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
207213. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
207214. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
207215. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
207216. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
207217. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
207218. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
207219. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
207220. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
207221. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
207222. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
207223. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
207224. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
207225. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
207226. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
207227. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
207228. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
207229. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
207230. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
207231. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
207232. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
207233. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
207234. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
207235. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
207236. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
207237. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
207238. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
207239. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
207240. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
207241. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
207242. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
207243. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
207244. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
207245. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
207246. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
207247. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
207248. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
207249. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
207250. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
207251. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
207252. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
207253. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
207254. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
207255. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
207256. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
207257. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
207258. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
207259. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
207260. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
207261. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
207262. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
207263. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
207264. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
207265. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
207266. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
207267. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
207268. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
207269. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
207270. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
207271. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
207272. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
207273. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
207274. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
207275. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
207276. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
207277. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
207278. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
207279. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
207280. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
207281. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
207282. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
207283. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
207284. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
207285. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
207286. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
207287. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
207288. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
207289. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
207290. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
207291. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
207292. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
207293. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
207294. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
207295. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
207296. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
207297. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
207298. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
207299. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
207300. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
207301. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
207302. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
207303. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
207304. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
207305. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
207306. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
207307. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
207308. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
207309. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
207310. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
207311. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
207312. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
207313. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
207314. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
207315. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
207316. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
207317. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
207318. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
207319. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
207320. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
207321. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
207322. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
207323. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
207324. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
207325. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
207326. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
207327. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
207328. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
207329. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
207330. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
207331. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
207332. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
207333. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
207334. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
207335. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
207336. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
207337. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
207338. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
207339. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
207340. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
207341. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
207342. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
207343. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
207344. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
207345. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
207346. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
207347. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
207348. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
207349. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
207350. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
207351. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
207352. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
207353. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
207354. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
207355. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
207356. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
207357. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
207358. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
207359. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
207360. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
207361. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
207362. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
207363. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
207364. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
207365. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
207366. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
207367. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
207368. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
207369. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
207370. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
207371. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
207372. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
207373. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
207374. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
207375. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
207376. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
207377. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
207378. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK
207379. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT
207380. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK
207381. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT
207382. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK
207383. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT
207384. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK
207385. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT
207386. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK
207387. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT
207388. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK
207389. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT
207390. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK
207391. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT
207392. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK
207393. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT
207394. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
207395. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
207396. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
207397. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
207398. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
207399. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
207400. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
207401. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
207402. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
207403. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
207404. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
207405. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
207406. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
207407. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
207408. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
207409. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
207410. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
207411. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
207412. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
207413. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
207414. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
207415. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
207416. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
207417. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
207418. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
207419. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
207420. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
207421. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
207422. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
207423. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
207424. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
207425. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
207426. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
207427. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
207428. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
207429. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
207430. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
207431. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
207432. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
207433. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
207434. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
207435. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
207436. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
207437. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
207438. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
207439. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
207440. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
207441. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
207442. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
207443. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
207444. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
207445. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
207446. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
207447. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
207448. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
207449. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
207450. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
207451. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
207452. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
207453. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
207454. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
207455. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
207456. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
207457. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
207458. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
207459. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
207460. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
207461. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
207462. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
207463. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
207464. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
207465. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
207466. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
207467. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
207468. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
207469. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
207470. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
207471. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
207472. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
207473. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
207474. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
207475. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
207476. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
207477. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
207478. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
207479. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
207480. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
207481. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
207482. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
207483. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
207484. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
207485. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
207486. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
207487. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
207488. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
207489. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
207490. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
207491. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
207492. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
207493. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
207494. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
207495. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
207496. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
207497. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
207498. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
207499. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
207500. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
207501. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
207502. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
207503. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
207504. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
207505. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
207506. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
207507. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
207508. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
207509. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
207510. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
207511. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
207512. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
207513. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
207514. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
207515. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
207516. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
207517. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
207518. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
207519. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
207520. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
207521. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
207522. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
207523. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
207524. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
207525. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
207526. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
207527. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
207528. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
207529. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
207530. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
207531. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
207532. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
207533. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
207534. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
207535. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
207536. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
207537. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
207538. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
207539. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
207540. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
207541. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
207542. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
207543. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
207544. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
207545. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
207546. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
207547. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
207548. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
207549. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
207550. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
207551. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
207552. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
207553. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
207554. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
207555. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
207556. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
207557. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
207558. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
207559. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
207560. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
207561. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
207562. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
207563. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
207564. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
207565. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
207566. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
207567. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
207568. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
207569. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
207570. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
207571. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
207572. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
207573. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
207574. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
207575. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
207576. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
207577. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
207578. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
207579. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
207580. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
207581. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
207582. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
207583. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
207584. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
207585. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
207586. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
207587. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
207588. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
207589. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
207590. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
207591. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
207592. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
207593. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
207594. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
207595. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
207596. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
207597. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
207598. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
207599. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
207600. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
207601. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
207602. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
207603. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
207604. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
207605. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
207606. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
207607. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
207608. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
207609. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
207610. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
207611. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
207612. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
207613. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
207614. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
207615. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
207616. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
207617. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
207618. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
207619. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
207620. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
207621. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
207622. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
207623. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
207624. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
207625. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
207626. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
207627. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
207628. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
207629. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
207630. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
207631. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
207632. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
207633. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
207634. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
207635. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
207636. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK
207637. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
207638. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
207639. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
207640. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
207641. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
207642. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
207643. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
207644. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
207645. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
207646. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
207647. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
207648. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
207649. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
207650. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
207651. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
207652. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
207653. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
207654. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
207655. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
207656. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
207657. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
207658. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
207659. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
207660. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
207661. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
207662. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
207663. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
207664. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK
207665. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
207666. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
207667. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
207668. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
207669. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
207670. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK
207671. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT
207672. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
207673. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
207674. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
207675. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
207676. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
207677. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
207678. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
207679. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
207680. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
207681. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
207682. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
207683. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
207684. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
207685. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
207686. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
207687. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
207688. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
207689. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
207690. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
207691. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
207692. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
207693. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
207694. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
207695. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
207696. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
207697. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
207698. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
207699. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
207700. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
207701. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
207702. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
207703. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
207704. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
207705. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
207706. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
207707. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
207708. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
207709. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
207710. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
207711. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
207712. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
207713. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
207714. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
207715. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
207716. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
207717. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
207718. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
207719. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
207720. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
207721. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
207722. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
207723. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
207724. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
207725. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
207726. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
207727. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
207728. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
207729. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
207730. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
207731. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
207732. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
207733. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
207734. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
207735. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
207736. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
207737. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
207738. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
207739. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
207740. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
207741. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
207742. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
207743. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
207744. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
207745. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
207746. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
207747. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
207748. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
207749. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
207750. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
207751. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
207752. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
207753. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
207754. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
207755. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
207756. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
207757. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
207758. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
207759. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
207760. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
207761. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
207762. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
207763. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
207764. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
207765. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
207766. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
207767. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
207768. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
207769. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
207770. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
207771. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
207772. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
207773. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
207774. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
207775. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
207776. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
207777. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
207778. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
207779. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
207780. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
207781. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
207782. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
207783. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
207784. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
207785. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
207786. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
207787. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
207788. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
207789. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
207790. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
207791. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
207792. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
207793. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
207794. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
207795. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
207796. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
207797. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
207798. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
207799. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
207800. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
207801. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
207802. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
207803. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
207804. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
207805. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
207806. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
207807. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
207808. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
207809. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
207810. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
207811. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
207812. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
207813. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
207814. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
207815. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
207816. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
207817. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
207818. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
207819. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
207820. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
207821. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
207822. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
207823. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
207824. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
207825. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
207826. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
207827. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
207828. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
207829. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
207830. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
207831. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
207832. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
207833. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
207834. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
207835. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
207836. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
207837. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
207838. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
207839. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
207840. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
207841. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
207842. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
207843. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
207844. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
207845. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
207846. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
207847. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
207848. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
207849. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
207850. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
207851. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
207852. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
207853. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
207854. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
207855. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
207856. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
207857. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
207858. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
207859. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
207860. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
207861. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
207862. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
207863. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
207864. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
207865. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
207866. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
207867. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
207868. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
207869. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
207870. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
207871. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
207872. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
207873. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
207874. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
207875. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
207876. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
207877. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
207878. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
207879. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
207880. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
207881. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
207882. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
207883. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
207884. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
207885. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
207886. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
207887. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
207888. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
207889. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
207890. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
207891. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
207892. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
207893. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
207894. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
207895. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
207896. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
207897. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
207898. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
207899. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
207900. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
207901. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
207902. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
207903. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
207904. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
207905. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
207906. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
207907. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
207908. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
207909. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
207910. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
207911. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
207912. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
207913. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
207914. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
207915. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
207916. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
207917. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
207918. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
207919. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
207920. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
207921. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
207922. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
207923. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
207924. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
207925. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
207926. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
207927. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
207928. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
207929. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
207930. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
207931. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
207932. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
207933. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
207934. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
207935. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
207936. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
207937. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
207938. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
207939. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
207940. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
207941. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
207942. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
207943. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
207944. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
207945. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
207946. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
207947. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
207948. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
207949. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
207950. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
207951. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
207952. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
207953. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
207954. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
207955. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
207956. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
207957. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
207958. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
207959. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
207960. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
207961. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
207962. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
207963. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
207964. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
207965. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
207966. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
207967. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
207968. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
207969. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
207970. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
207971. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
207972. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
207973. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
207974. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
207975. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
207976. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
207977. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
207978. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
207979. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
207980. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
207981. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
207982. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
207983. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
207984. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
207985. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
207986. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
207987. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
207988. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
207989. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
207990. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
207991. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
207992. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
207993. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
207994. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
207995. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
207996. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
207997. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
207998. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
207999. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
208000. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
208001. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
208002. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
208003. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
208004. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
208005. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
208006. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
208007. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
208008. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
208009. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
208010. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
208011. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
208012. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
208013. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
208014. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
208015. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
208016. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
208017. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
208018. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
208019. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
208020. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
208021. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
208022. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
208023. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
208024. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
208025. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
208026. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
208027. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
208028. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
208029. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
208030. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
208031. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
208032. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
208033. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
208034. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
208035. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
208036. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
208037. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
208038. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
208039. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
208040. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
208041. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
208042. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
208043. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
208044. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
208045. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
208046. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
208047. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
208048. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
208049. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
208050. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
208051. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
208052. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
208053. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
208054. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
208055. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
208056. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
208057. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
208058. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK
208059. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT
208060. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK
208061. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT
208062. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK
208063. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT
208064. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK
208065. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT
208066. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK
208067. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT
208068. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK
208069. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT
208070. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK
208071. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT
208072. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK
208073. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT
208074. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
208075. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
208076. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
208077. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
208078. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
208079. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
208080. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
208081. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
208082. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
208083. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
208084. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
208085. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
208086. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
208087. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
208088. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
208089. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
208090. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
208091. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
208092. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
208093. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
208094. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
208095. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
208096. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
208097. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
208098. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
208099. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
208100. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
208101. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208102. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
208103. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
208104. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
208105. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
208106. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
208107. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
208108. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
208109. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208110. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
208111. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
208112. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
208113. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
208114. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
208115. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
208116. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
208117. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
208118. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
208119. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
208120. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
208121. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208122. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
208123. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
208124. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
208125. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
208126. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
208127. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
208128. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
208129. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208130. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
208131. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
208132. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
208133. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
208134. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
208135. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
208136. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
208137. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
208138. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
208139. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
208140. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
208141. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
208142. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
208143. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
208144. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
208145. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
208146. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
208147. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
208148. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
208149. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
208150. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
208151. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
208152. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
208153. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
208154. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
208155. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
208156. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
208157. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
208158. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
208159. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
208160. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
208161. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
208162. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
208163. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
208164. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
208165. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
208166. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
208167. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
208168. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
208169. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
208170. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
208171. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
208172. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
208173. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
208174. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
208175. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
208176. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
208177. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
208178. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
208179. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
208180. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
208181. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
208182. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
208183. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
208184. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
208185. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
208186. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
208187. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
208188. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
208189. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
208190. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
208191. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
208192. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
208193. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
208194. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
208195. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
208196. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
208197. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
208198. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
208199. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
208200. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
208201. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
208202. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
208203. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
208204. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
208205. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
208206. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
208207. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
208208. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
208209. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
208210. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
208211. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
208212. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
208213. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
208214. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
208215. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
208216. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
208217. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
208218. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
208219. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
208220. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
208221. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
208222. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
208223. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
208224. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
208225. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
208226. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
208227. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
208228. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
208229. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
208230. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
208231. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
208232. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
208233. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
208234. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
208235. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
208236. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
208237. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
208238. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
208239. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
208240. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
208241. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
208242. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
208243. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
208244. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
208245. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
208246. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
208247. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
208248. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
208249. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
208250. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
208251. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
208252. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
208253. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
208254. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
208255. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
208256. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
208257. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
208258. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
208259. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
208260. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
208261. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
208262. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
208263. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
208264. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
208265. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
208266. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
208267. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
208268. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
208269. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
208270. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
208271. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
208272. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
208273. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
208274. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
208275. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
208276. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
208277. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
208278. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
208279. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
208280. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
208281. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
208282. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
208283. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
208284. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
208285. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
208286. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
208287. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
208288. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
208289. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
208290. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
208291. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
208292. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
208293. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
208294. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
208295. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
208296. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
208297. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
208298. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
208299. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
208300. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
208301. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
208302. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
208303. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
208304. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
208305. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
208306. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
208307. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
208308. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
208309. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
208310. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
208311. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
208312. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
208313. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
208314. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
208315. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
208316. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK
208317. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
208318. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
208319. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
208320. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
208321. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
208322. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
208323. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
208324. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
208325. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
208326. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
208327. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
208328. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
208329. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
208330. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
208331. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
208332. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
208333. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
208334. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
208335. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
208336. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
208337. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
208338. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
208339. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
208340. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
208341. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
208342. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
208343. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
208344. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK
208345. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
208346. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
208347. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
208348. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
208349. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
208350. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK
208351. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT
208352. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
208353. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
208354. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
208355. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
208356. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
208357. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
208358. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
208359. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
208360. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
208361. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
208362. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
208363. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
208364. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
208365. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
208366. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
208367. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
208368. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
208369. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
208370. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
208371. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
208372. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
208373. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
208374. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
208375. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
208376. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
208377. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
208378. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
208379. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
208380. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
208381. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
208382. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
208383. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
208384. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
208385. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
208386. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
208387. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
208388. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
208389. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
208390. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
208391. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
208392. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
208393. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
208394. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
208395. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
208396. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
208397. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
208398. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
208399. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
208400. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
208401. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
208402. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
208403. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
208404. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
208405. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
208406. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
208407. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
208408. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
208409. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
208410. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
208411. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
208412. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
208413. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
208414. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
208415. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
208416. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
208417. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
208418. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
208419. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
208420. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
208421. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
208422. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
208423. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
208424. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
208425. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
208426. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
208427. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
208428. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
208429. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
208430. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
208431. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
208432. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
208433. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
208434. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
208435. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
208436. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
208437. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
208438. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
208439. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
208440. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
208441. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
208442. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
208443. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
208444. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
208445. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
208446. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
208447. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
208448. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
208449. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
208450. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
208451. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
208452. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
208453. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
208454. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
208455. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
208456. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
208457. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
208458. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
208459. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
208460. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
208461. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
208462. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
208463. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
208464. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
208465. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
208466. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
208467. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
208468. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
208469. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
208470. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
208471. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
208472. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
208473. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
208474. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
208475. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
208476. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
208477. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
208478. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
208479. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
208480. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
208481. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
208482. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
208483. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
208484. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
208485. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
208486. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
208487. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
208488. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
208489. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
208490. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
208491. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
208492. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
208493. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
208494. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
208495. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
208496. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
208497. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
208498. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
208499. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
208500. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
208501. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
208502. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
208503. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
208504. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
208505. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
208506. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
208507. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
208508. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
208509. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
208510. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
208511. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
208512. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
208513. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
208514. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
208515. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
208516. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
208517. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
208518. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
208519. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
208520. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
208521. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
208522. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
208523. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
208524. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
208525. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
208526. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
208527. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
208528. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
208529. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
208530. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
208531. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
208532. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
208533. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
208534. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
208535. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
208536. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
208537. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
208538. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
208539. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
208540. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
208541. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
208542. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
208543. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
208544. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
208545. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
208546. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
208547. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
208548. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
208549. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
208550. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
208551. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
208552. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
208553. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
208554. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
208555. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
208556. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
208557. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
208558. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
208559. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
208560. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
208561. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
208562. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
208563. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
208564. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
208565. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
208566. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
208567. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
208568. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
208569. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
208570. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
208571. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
208572. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
208573. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
208574. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
208575. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
208576. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
208577. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
208578. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
208579. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
208580. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
208581. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
208582. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
208583. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
208584. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
208585. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
208586. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
208587. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
208588. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
208589. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
208590. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
208591. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
208592. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
208593. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
208594. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
208595. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
208596. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
208597. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
208598. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
208599. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
208600. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
208601. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
208602. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
208603. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
208604. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
208605. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
208606. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
208607. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
208608. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
208609. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
208610. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
208611. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
208612. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
208613. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
208614. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
208615. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
208616. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
208617. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
208618. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
208619. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
208620. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
208621. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
208622. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
208623. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
208624. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
208625. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
208626. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
208627. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
208628. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
208629. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
208630. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
208631. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
208632. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
208633. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
208634. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
208635. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
208636. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
208637. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
208638. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
208639. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
208640. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
208641. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
208642. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
208643. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
208644. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
208645. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
208646. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
208647. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
208648. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
208649. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
208650. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
208651. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
208652. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
208653. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
208654. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
208655. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
208656. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
208657. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
208658. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
208659. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
208660. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
208661. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
208662. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
208663. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
208664. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
208665. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
208666. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
208667. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
208668. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
208669. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
208670. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
208671. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
208672. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
208673. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
208674. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
208675. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
208676. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
208677. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
208678. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
208679. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
208680. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
208681. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
208682. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
208683. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
208684. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
208685. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
208686. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
208687. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
208688. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
208689. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
208690. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
208691. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
208692. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
208693. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
208694. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
208695. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
208696. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
208697. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
208698. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
208699. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
208700. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
208701. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
208702. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
208703. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
208704. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
208705. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
208706. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
208707. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
208708. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
208709. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
208710. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
208711. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
208712. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
208713. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
208714. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
208715. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
208716. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
208717. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
208718. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
208719. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
208720. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
208721. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
208722. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
208723. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
208724. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
208725. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
208726. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
208727. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
208728. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
208729. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
208730. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
208731. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
208732. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
208733. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
208734. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
208735. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
208736. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
208737. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
208738. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK
208739. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT
208740. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK
208741. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT
208742. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK
208743. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT
208744. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK
208745. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT
208746. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK
208747. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT
208748. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK
208749. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT
208750. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK
208751. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT
208752. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK
208753. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT
208754. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
208755. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
208756. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
208757. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
208758. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
208759. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
208760. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
208761. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
208762. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
208763. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
208764. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
208765. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
208766. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
208767. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
208768. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
208769. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
208770. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
208771. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
208772. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
208773. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
208774. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
208775. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
208776. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
208777. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
208778. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
208779. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
208780. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
208781. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208782. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
208783. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
208784. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
208785. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
208786. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
208787. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
208788. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
208789. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208790. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
208791. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
208792. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
208793. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
208794. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
208795. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
208796. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
208797. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
208798. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
208799. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
208800. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
208801. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208802. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
208803. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
208804. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
208805. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
208806. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
208807. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
208808. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
208809. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
208810. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
208811. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
208812. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
208813. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
208814. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
208815. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
208816. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
208817. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
208818. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
208819. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
208820. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
208821. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
208822. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
208823. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
208824. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
208825. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
208826. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
208827. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
208828. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
208829. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
208830. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
208831. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
208832. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
208833. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
208834. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
208835. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
208836. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
208837. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
208838. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
208839. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
208840. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
208841. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
208842. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
208843. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
208844. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
208845. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
208846. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
208847. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
208848. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
208849. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
208850. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
208851. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
208852. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
208853. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
208854. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
208855. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
208856. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
208857. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
208858. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
208859. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
208860. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
208861. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
208862. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
208863. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
208864. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
208865. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
208866. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
208867. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
208868. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
208869. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
208870. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
208871. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
208872. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
208873. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
208874. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
208875. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
208876. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
208877. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
208878. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
208879. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
208880. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
208881. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
208882. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
208883. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
208884. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
208885. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
208886. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
208887. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
208888. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
208889. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
208890. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
208891. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
208892. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
208893. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
208894. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
208895. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
208896. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
208897. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
208898. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
208899. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
208900. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
208901. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
208902. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
208903. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
208904. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
208905. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
208906. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
208907. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
208908. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
208909. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
208910. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
208911. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
208912. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
208913. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
208914. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
208915. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
208916. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
208917. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
208918. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
208919. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
208920. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
208921. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
208922. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
208923. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
208924. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
208925. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
208926. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
208927. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
208928. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
208929. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
208930. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
208931. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
208932. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
208933. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
208934. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
208935. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
208936. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
208937. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
208938. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
208939. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
208940. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
208941. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
208942. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
208943. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
208944. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
208945. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
208946. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
208947. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
208948. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
208949. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
208950. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
208951. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
208952. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
208953. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
208954. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
208955. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
208956. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
208957. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
208958. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
208959. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
208960. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
208961. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
208962. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
208963. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
208964. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
208965. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
208966. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
208967. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
208968. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
208969. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
208970. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
208971. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
208972. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
208973. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
208974. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
208975. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
208976. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
208977. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
208978. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
208979. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
208980. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
208981. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
208982. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
208983. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
208984. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
208985. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
208986. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
208987. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
208988. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
208989. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
208990. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
208991. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
208992. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
208993. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
208994. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
208995. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
208996. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK
208997. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
208998. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
208999. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
209000. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
209001. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
209002. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
209003. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
209004. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
209005. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
209006. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
209007. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
209008. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
209009. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
209010. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
209011. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
209012. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
209013. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
209014. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
209015. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
209016. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
209017. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
209018. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
209019. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
209020. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
209021. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
209022. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
209023. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
209024. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK
209025. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
209026. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
209027. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
209028. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
209029. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
209030. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK
209031. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT
209032. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
209033. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
209034. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
209035. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
209036. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
209037. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
209038. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
209039. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
209040. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
209041. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
209042. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
209043. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
209044. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
209045. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
209046. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
209047. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
209048. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
209049. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
209050. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
209051. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
209052. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
209053. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
209054. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
209055. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
209056. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
209057. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
209058. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
209059. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
209060. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
209061. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
209062. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
209063. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
209064. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
209065. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
209066. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
209067. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
209068. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
209069. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
209070. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
209071. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
209072. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
209073. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
209074. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
209075. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
209076. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
209077. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
209078. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
209079. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
209080. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
209081. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
209082. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
209083. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
209084. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
209085. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
209086. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
209087. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
209088. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
209089. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
209090. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
209091. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
209092. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
209093. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
209094. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
209095. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
209096. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
209097. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
209098. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
209099. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
209100. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
209101. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
209102. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
209103. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
209104. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
209105. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
209106. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
209107. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
209108. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
209109. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
209110. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
209111. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
209112. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
209113. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
209114. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
209115. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
209116. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
209117. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
209118. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
209119. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
209120. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
209121. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
209122. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
209123. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
209124. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
209125. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
209126. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
209127. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
209128. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
209129. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
209130. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
209131. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
209132. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
209133. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
209134. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
209135. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
209136. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
209137. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
209138. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
209139. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
209140. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
209141. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
209142. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
209143. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
209144. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
209145. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
209146. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
209147. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
209148. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
209149. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
209150. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
209151. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
209152. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
209153. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
209154. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
209155. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
209156. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
209157. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
209158. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
209159. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
209160. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
209161. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
209162. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
209163. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
209164. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
209165. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
209166. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
209167. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
209168. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
209169. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
209170. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
209171. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
209172. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
209173. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
209174. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
209175. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
209176. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
209177. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
209178. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
209179. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
209180. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
209181. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
209182. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
209183. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
209184. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
209185. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
209186. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
209187. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
209188. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
209189. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
209190. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
209191. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
209192. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
209193. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
209194. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
209195. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
209196. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
209197. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
209198. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
209199. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
209200. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
209201. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
209202. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
209203. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
209204. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
209205. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
209206. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
209207. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
209208. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
209209. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
209210. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
209211. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
209212. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
209213. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
209214. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
209215. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
209216. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
209217. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
209218. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
209219. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
209220. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
209221. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
209222. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
209223. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
209224. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
209225. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
209226. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
209227. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
209228. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
209229. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
209230. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
209231. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
209232. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
209233. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
209234. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
209235. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
209236. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
209237. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
209238. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
209239. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
209240. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
209241. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
209242. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
209243. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
209244. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
209245. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
209246. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
209247. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
209248. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
209249. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
209250. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
209251. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
209252. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
209253. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
209254. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
209255. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
209256. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
209257. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
209258. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
209259. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
209260. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
209261. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
209262. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
209263. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
209264. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
209265. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
209266. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
209267. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
209268. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
209269. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
209270. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
209271. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
209272. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
209273. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
209274. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
209275. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
209276. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
209277. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
209278. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
209279. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
209280. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
209281. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
209282. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
209283. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
209284. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
209285. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
209286. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
209287. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
209288. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
209289. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
209290. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
209291. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
209292. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
209293. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
209294. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
209295. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
209296. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
209297. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
209298. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
209299. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
209300. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
209301. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
209302. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
209303. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
209304. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
209305. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
209306. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
209307. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
209308. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
209309. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
209310. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
209311. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
209312. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
209313. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
209314. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
209315. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
209316. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
209317. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
209318. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
209319. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
209320. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
209321. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
209322. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
209323. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
209324. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
209325. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
209326. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
209327. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
209328. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
209329. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
209330. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
209331. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
209332. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
209333. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
209334. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
209335. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
209336. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
209337. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
209338. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
209339. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
209340. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
209341. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
209342. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
209343. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
209344. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
209345. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
209346. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
209347. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
209348. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
209349. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
209350. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
209351. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
209352. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
209353. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
209354. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
209355. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
209356. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
209357. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
209358. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
209359. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
209360. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
209361. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
209362. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
209363. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
209364. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
209365. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
209366. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
209367. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
209368. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
209369. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
209370. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
209371. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
209372. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
209373. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
209374. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
209375. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
209376. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
209377. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
209378. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
209379. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
209380. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
209381. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
209382. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
209383. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
209384. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
209385. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
209386. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
209387. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
209388. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
209389. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
209390. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
209391. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
209392. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
209393. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
209394. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
209395. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
209396. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
209397. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
209398. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
209399. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
209400. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
209401. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
209402. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
209403. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
209404. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
209405. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
209406. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
209407. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
209408. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
209409. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
209410. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
209411. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
209412. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
209413. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
209414. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
209415. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
209416. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
209417. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
209418. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK
209419. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT
209420. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK
209421. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT
209422. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK
209423. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT
209424. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK
209425. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT
209426. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK
209427. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT
209428. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK
209429. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT
209430. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK
209431. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT
209432. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK
209433. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT
209434. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
209435. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
209436. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
209437. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
209438. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
209439. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
209440. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
209441. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
209442. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
209443. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
209444. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
209445. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
209446. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
209447. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
209448. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
209449. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
209450. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
209451. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
209452. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
209453. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
209454. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
209455. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
209456. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
209457. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
209458. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
209459. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
209460. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
209461. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
209462. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
209463. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
209464. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
209465. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
209466. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
209467. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
209468. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
209469. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
209470. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
209471. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
209472. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
209473. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
209474. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
209475. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
209476. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
209477. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
209478. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
209479. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
209480. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
209481. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
209482. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
209483. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
209484. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
209485. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
209486. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
209487. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
209488. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
209489. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
209490. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
209491. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
209492. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
209493. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
209494. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
209495. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
209496. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
209497. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
209498. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
209499. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
209500. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
209501. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
209502. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
209503. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
209504. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
209505. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
209506. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
209507. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
209508. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
209509. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
209510. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
209511. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
209512. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
209513. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
209514. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
209515. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
209516. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
209517. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
209518. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
209519. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
209520. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
209521. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
209522. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
209523. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
209524. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
209525. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
209526. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
209527. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
209528. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
209529. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
209530. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
209531. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
209532. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
209533. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
209534. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
209535. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
209536. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
209537. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
209538. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
209539. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
209540. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
209541. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
209542. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
209543. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
209544. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
209545. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
209546. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
209547. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
209548. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
209549. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
209550. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
209551. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
209552. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
209553. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
209554. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
209555. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
209556. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
209557. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
209558. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
209559. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
209560. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
209561. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
209562. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
209563. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
209564. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
209565. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
209566. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
209567. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
209568. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
209569. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
209570. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
209571. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
209572. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
209573. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
209574. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
209575. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
209576. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
209577. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
209578. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
209579. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
209580. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
209581. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
209582. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
209583. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
209584. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
209585. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
209586. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
209587. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
209588. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
209589. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
209590. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
209591. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
209592. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
209593. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
209594. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
209595. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
209596. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
209597. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
209598. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
209599. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
209600. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
209601. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
209602. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
209603. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
209604. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
209605. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
209606. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
209607. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
209608. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
209609. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
209610. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
209611. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
209612. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
209613. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
209614. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
209615. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
209616. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
209617. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
209618. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
209619. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
209620. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
209621. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
209622. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
209623. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
209624. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
209625. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
209626. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
209627. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
209628. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
209629. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
209630. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
209631. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
209632. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
209633. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
209634. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
209635. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
209636. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
209637. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
209638. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
209639. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
209640. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
209641. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
209642. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
209643. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
209644. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
209645. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
209646. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
209647. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
209648. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
209649. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
209650. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
209651. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
209652. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
209653. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
209654. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
209655. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
209656. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
209657. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
209658. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
209659. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
209660. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
209661. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
209662. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
209663. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
209664. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
209665. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
209666. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
209667. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
209668. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
209669. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
209670. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
209671. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
209672. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
209673. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
209674. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
209675. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
209676. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK
209677. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
209678. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
209679. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
209680. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
209681. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
209682. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
209683. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
209684. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
209685. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
209686. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
209687. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
209688. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
209689. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
209690. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
209691. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
209692. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
209693. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
209694. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
209695. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
209696. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
209697. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
209698. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
209699. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
209700. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
209701. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
209702. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
209703. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
209704. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK
209705. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
209706. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
209707. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
209708. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
209709. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
209710. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK
209711. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT
209712. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
209713. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
209714. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
209715. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
209716. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
209717. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
209718. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
209719. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
209720. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
209721. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
209722. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
209723. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
209724. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
209725. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
209726. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
209727. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
209728. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
209729. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
209730. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
209731. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
209732. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
209733. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
209734. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
209735. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
209736. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
209737. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
209738. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
209739. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
209740. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
209741. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
209742. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
209743. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
209744. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
209745. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
209746. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
209747. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
209748. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
209749. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
209750. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
209751. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
209752. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
209753. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
209754. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
209755. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
209756. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
209757. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
209758. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
209759. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
209760. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
209761. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
209762. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
209763. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
209764. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
209765. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
209766. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
209767. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
209768. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
209769. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
209770. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
209771. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
209772. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
209773. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
209774. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
209775. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
209776. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
209777. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
209778. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
209779. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
209780. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
209781. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
209782. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
209783. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
209784. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
209785. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
209786. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
209787. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
209788. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
209789. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
209790. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
209791. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
209792. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
209793. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
209794. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
209795. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
209796. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
209797. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
209798. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
209799. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
209800. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
209801. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
209802. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
209803. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
209804. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
209805. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
209806. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
209807. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
209808. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
209809. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
209810. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
209811. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
209812. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
209813. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
209814. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
209815. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
209816. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
209817. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
209818. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
209819. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
209820. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
209821. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
209822. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
209823. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
209824. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
209825. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
209826. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
209827. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
209828. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
209829. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
209830. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
209831. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
209832. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
209833. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
209834. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
209835. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
209836. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
209837. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
209838. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
209839. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
209840. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
209841. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
209842. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
209843. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
209844. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
209845. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
209846. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
209847. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
209848. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
209849. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
209850. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
209851. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
209852. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
209853. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
209854. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
209855. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
209856. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
209857. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
209858. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
209859. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
209860. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
209861. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
209862. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
209863. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
209864. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
209865. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
209866. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
209867. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
209868. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
209869. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
209870. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
209871. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
209872. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
209873. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
209874. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
209875. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
209876. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
209877. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
209878. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
209879. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
209880. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
209881. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
209882. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
209883. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
209884. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
209885. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
209886. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
209887. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
209888. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
209889. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
209890. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
209891. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
209892. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
209893. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
209894. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
209895. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
209896. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
209897. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
209898. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
209899. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
209900. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
209901. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
209902. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
209903. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
209904. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
209905. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
209906. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
209907. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
209908. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
209909. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
209910. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
209911. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
209912. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
209913. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
209914. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
209915. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
209916. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
209917. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
209918. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
209919. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
209920. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
209921. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
209922. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
209923. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
209924. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
209925. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
209926. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
209927. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
209928. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
209929. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
209930. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
209931. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
209932. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
209933. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
209934. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
209935. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
209936. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
209937. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
209938. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
209939. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
209940. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
209941. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
209942. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
209943. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
209944. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
209945. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
209946. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
209947. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
209948. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
209949. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
209950. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
209951. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
209952. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
209953. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
209954. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
209955. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
209956. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
209957. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
209958. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
209959. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
209960. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
209961. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
209962. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
209963. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
209964. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
209965. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
209966. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
209967. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
209968. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
209969. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
209970. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
209971. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
209972. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
209973. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
209974. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
209975. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
209976. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
209977. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
209978. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
209979. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
209980. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
209981. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
209982. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
209983. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
209984. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
209985. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
209986. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
209987. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
209988. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
209989. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
209990. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
209991. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
209992. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
209993. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
209994. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
209995. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
209996. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
209997. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
209998. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
209999. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
210000. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
210001. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
210002. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
210003. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
210004. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
210005. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
210006. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
210007. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
210008. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
210009. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
210010. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
210011. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
210012. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
210013. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
210014. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
210015. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
210016. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
210017. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
210018. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
210019. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
210020. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
210021. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
210022. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
210023. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
210024. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
210025. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
210026. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
210027. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
210028. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
210029. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
210030. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
210031. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
210032. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
210033. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
210034. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
210035. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
210036. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
210037. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
210038. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
210039. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
210040. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
210041. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
210042. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
210043. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
210044. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
210045. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
210046. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
210047. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
210048. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
210049. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
210050. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
210051. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
210052. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
210053. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
210054. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
210055. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
210056. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
210057. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
210058. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
210059. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
210060. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
210061. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
210062. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
210063. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
210064. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
210065. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
210066. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
210067. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
210068. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
210069. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
210070. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
210071. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
210072. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
210073. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
210074. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
210075. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
210076. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
210077. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
210078. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
210079. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
210080. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
210081. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
210082. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
210083. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
210084. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
210085. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
210086. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
210087. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
210088. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
210089. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
210090. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
210091. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
210092. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
210093. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
210094. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
210095. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
210096. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
210097. DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
210098. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__NC74_MASK
210099. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__NC74__SHIFT
210100. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__RESERVED_15_8_MASK
210101. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__RESERVED_15_8__SHIFT
210102. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__bypass_bg_MASK
210103. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__bypass_bg__SHIFT
210104. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__chop_en_MASK
210105. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__chop_en__SHIFT
210106. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__vref_sel_fastreg_MASK
210107. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__vref_sel_fastreg__SHIFT
210108. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
210109. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
210110. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK
210111. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
210112. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK
210113. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
210114. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
210115. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
210116. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK
210117. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
210118. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK
210119. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
210120. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK
210121. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
210122. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK
210123. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
210124. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK
210125. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
210126. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
210127. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
210128. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
210129. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
210130. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK
210131. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT
210132. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
210133. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
210134. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK
210135. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
210136. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK
210137. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT
210138. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
210139. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
210140. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK
210141. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
210142. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
210143. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
210144. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__NC76_MASK
210145. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT
210146. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
210147. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
210148. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__atb_select_MASK
210149. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT
210150. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK
210151. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT
210152. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK
210153. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT
210154. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK
210155. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
210156. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK
210157. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT
210158. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK
210159. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT
210160. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC40_MASK
210161. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC40__SHIFT
210162. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC76_MASK
210163. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC76__SHIFT
210164. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK
210165. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
210166. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK
210167. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT
210168. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
210169. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
210170. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK
210171. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT
210172. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK
210173. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT
210174. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
210175. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
210176. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK
210177. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
210178. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK
210179. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
210180. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
210181. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
210182. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK
210183. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
210184. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK
210185. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT
210186. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
210187. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
210188. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK
210189. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
210190. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK
210191. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
210192. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
210193. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
210194. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK
210195. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
210196. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK
210197. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
210198. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK
210199. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
210200. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK
210201. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
210202. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK
210203. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
210204. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
210205. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
210206. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
210207. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
210208. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK
210209. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT
210210. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
210211. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
210212. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK
210213. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
210214. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK
210215. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT
210216. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
210217. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
210218. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK
210219. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
210220. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
210221. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
210222. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__NC76_MASK
210223. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT
210224. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
210225. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
210226. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__atb_select_MASK
210227. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT
210228. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK
210229. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT
210230. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK
210231. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT
210232. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK
210233. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
210234. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK
210235. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT
210236. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK
210237. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT
210238. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC40_MASK
210239. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC40__SHIFT
210240. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC76_MASK
210241. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC76__SHIFT
210242. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK
210243. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
210244. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK
210245. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT
210246. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
210247. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
210248. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK
210249. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT
210250. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK
210251. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT
210252. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
210253. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
210254. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK
210255. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
210256. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK
210257. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
210258. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
210259. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
210260. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK
210261. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
210262. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK
210263. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT
210264. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
210265. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
210266. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK
210267. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT
210268. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK
210269. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
210270. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK
210271. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
210272. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK
210273. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
210274. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
210275. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
210276. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
210277. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
210278. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
210279. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
210280. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK
210281. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
210282. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
210283. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
210284. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
210285. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
210286. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
210287. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
210288. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
210289. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
210290. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK
210291. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
210292. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
210293. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
210294. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
210295. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
210296. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
210297. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
210298. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
210299. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
210300. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
210301. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
210302. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
210303. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
210304. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
210305. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
210306. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
210307. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
210308. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
210309. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
210310. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
210311. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
210312. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
210313. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
210314. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
210315. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
210316. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
210317. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
210318. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
210319. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
210320. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
210321. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
210322. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
210323. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
210324. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
210325. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
210326. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
210327. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
210328. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
210329. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
210330. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
210331. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
210332. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
210333. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
210334. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
210335. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
210336. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
210337. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
210338. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
210339. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
210340. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
210341. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
210342. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
210343. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
210344. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
210345. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
210346. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
210347. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
210348. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
210349. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
210350. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
210351. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
210352. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
210353. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
210354. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
210355. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
210356. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
210357. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
210358. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
210359. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
210360. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
210361. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
210362. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
210363. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
210364. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
210365. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
210366. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
210367. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
210368. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
210369. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
210370. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
210371. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
210372. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
210373. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
210374. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
210375. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
210376. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
210377. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
210378. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK
210379. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT
210380. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
210381. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
210382. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__BG_EN_MASK
210383. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__BG_EN__SHIFT
210384. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK
210385. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT
210386. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK
210387. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT
210388. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK
210389. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT
210390. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
210391. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
210392. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK
210393. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT
210394. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
210395. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
210396. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK
210397. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT
210398. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK
210399. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT
210400. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK
210401. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
210402. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK
210403. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT
210404. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK
210405. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
210406. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK
210407. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT
210408. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK
210409. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT
210410. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK
210411. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT
210412. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK
210413. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
210414. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI__data_MASK
210415. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI__data__SHIFT
210416. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO__data_MASK
210417. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO__data__SHIFT
210418. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
210419. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
210420. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
210421. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
210422. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
210423. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
210424. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
210425. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
210426. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
210427. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
210428. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
210429. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
210430. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
210431. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
210432. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
210433. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
210434. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
210435. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
210436. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
210437. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
210438. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
210439. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
210440. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
210441. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
210442. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
210443. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
210444. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
210445. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
210446. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
210447. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
210448. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
210449. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
210450. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
210451. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
210452. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
210453. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
210454. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
210455. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
210456. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
210457. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
210458. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
210459. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
210460. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
210461. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
210462. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
210463. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
210464. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
210465. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
210466. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
210467. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
210468. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
210469. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
210470. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
210471. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
210472. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
210473. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
210474. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
210475. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
210476. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
210477. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
210478. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
210479. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
210480. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
210481. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
210482. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
210483. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
210484. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
210485. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
210486. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
210487. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
210488. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
210489. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
210490. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
210491. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
210492. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
210493. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
210494. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
210495. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
210496. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
210497. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
210498. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
210499. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
210500. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
210501. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
210502. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
210503. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
210504. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
210505. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
210506. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
210507. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
210508. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
210509. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
210510. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
210511. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
210512. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
210513. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
210514. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
210515. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
210516. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
210517. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
210518. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
210519. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
210520. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
210521. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
210522. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
210523. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
210524. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
210525. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
210526. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
210527. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
210528. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
210529. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
210530. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
210531. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
210532. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
210533. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
210534. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
210535. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
210536. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
210537. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
210538. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
210539. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
210540. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
210541. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
210542. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
210543. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
210544. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
210545. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
210546. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
210547. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
210548. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
210549. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
210550. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
210551. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
210552. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
210553. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
210554. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
210555. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
210556. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
210557. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
210558. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
210559. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
210560. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
210561. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
210562. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
210563. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
210564. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
210565. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
210566. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
210567. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
210568. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
210569. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
210570. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
210571. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
210572. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
210573. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
210574. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
210575. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
210576. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
210577. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
210578. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
210579. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
210580. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
210581. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
210582. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
210583. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
210584. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
210585. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
210586. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
210587. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
210588. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
210589. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
210590. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
210591. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
210592. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
210593. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
210594. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
210595. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
210596. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
210597. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
210598. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
210599. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
210600. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
210601. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
210602. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
210603. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
210604. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
210605. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
210606. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
210607. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
210608. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
210609. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
210610. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
210611. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
210612. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
210613. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
210614. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
210615. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
210616. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
210617. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
210618. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
210619. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
210620. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
210621. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
210622. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
210623. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
210624. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
210625. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
210626. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
210627. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
210628. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
210629. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
210630. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
210631. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
210632. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
210633. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
210634. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
210635. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
210636. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
210637. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
210638. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
210639. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
210640. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
210641. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
210642. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
210643. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
210644. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
210645. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
210646. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
210647. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
210648. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
210649. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
210650. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
210651. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
210652. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
210653. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
210654. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
210655. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
210656. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
210657. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
210658. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
210659. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
210660. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
210661. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
210662. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
210663. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
210664. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
210665. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
210666. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
210667. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
210668. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
210669. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
210670. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
210671. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
210672. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
210673. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
210674. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
210675. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
210676. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
210677. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
210678. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
210679. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
210680. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
210681. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
210682. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
210683. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
210684. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
210685. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
210686. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
210687. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
210688. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
210689. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
210690. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
210691. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
210692. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
210693. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
210694. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
210695. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
210696. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
210697. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
210698. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
210699. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
210700. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
210701. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
210702. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
210703. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
210704. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
210705. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
210706. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
210707. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
210708. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
210709. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
210710. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
210711. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
210712. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
210713. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
210714. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
210715. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
210716. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
210717. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
210718. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
210719. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
210720. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
210721. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
210722. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
210723. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
210724. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
210725. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
210726. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
210727. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
210728. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
210729. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
210730. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
210731. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
210732. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
210733. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
210734. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
210735. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
210736. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
210737. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
210738. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
210739. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
210740. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
210741. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
210742. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
210743. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
210744. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
210745. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
210746. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
210747. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
210748. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
210749. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
210750. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
210751. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
210752. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
210753. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
210754. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
210755. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
210756. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
210757. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
210758. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
210759. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
210760. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
210761. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
210762. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK
210763. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
210764. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
210765. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
210766. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
210767. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
210768. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
210769. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
210770. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
210771. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
210772. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
210773. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
210774. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
210775. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
210776. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
210777. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
210778. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
210779. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
210780. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
210781. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
210782. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
210783. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
210784. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
210785. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
210786. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
210787. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
210788. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
210789. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
210790. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK
210791. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
210792. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK
210793. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
210794. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK
210795. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
210796. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__STAT_MASK
210797. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT
210798. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
210799. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
210800. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
210801. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
210802. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
210803. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
210804. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
210805. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
210806. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
210807. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
210808. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
210809. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
210810. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
210811. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
210812. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
210813. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
210814. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
210815. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
210816. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
210817. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
210818. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
210819. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
210820. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
210821. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
210822. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
210823. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
210824. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
210825. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
210826. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
210827. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
210828. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
210829. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
210830. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
210831. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
210832. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
210833. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
210834. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
210835. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
210836. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
210837. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
210838. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
210839. DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
210840. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__NC74_MASK
210841. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__NC74__SHIFT
210842. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__RESERVED_15_8_MASK
210843. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__RESERVED_15_8__SHIFT
210844. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__bypass_bg_MASK
210845. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__bypass_bg__SHIFT
210846. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__chop_en_MASK
210847. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__chop_en__SHIFT
210848. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__vref_sel_fastreg_MASK
210849. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__vref_sel_fastreg__SHIFT
210850. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
210851. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
210852. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK
210853. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
210854. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK
210855. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
210856. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
210857. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
210858. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK
210859. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
210860. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK
210861. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
210862. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK
210863. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
210864. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK
210865. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
210866. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK
210867. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
210868. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
210869. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
210870. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
210871. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
210872. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_gd_MASK
210873. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT
210874. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
210875. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
210876. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK
210877. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
210878. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vp_MASK
210879. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT
210880. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
210881. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
210882. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK
210883. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
210884. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
210885. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
210886. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__NC76_MASK
210887. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__NC76__SHIFT
210888. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
210889. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
210890. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__atb_select_MASK
210891. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT
210892. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK
210893. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT
210894. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK
210895. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT
210896. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK
210897. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
210898. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK
210899. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT
210900. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK
210901. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT
210902. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC40_MASK
210903. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC40__SHIFT
210904. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC76_MASK
210905. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC76__SHIFT
210906. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK
210907. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
210908. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK
210909. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT
210910. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
210911. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
210912. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__cal_reg_MASK
210913. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT
210914. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__enable_reg_MASK
210915. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT
210916. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
210917. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
210918. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK
210919. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
210920. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK
210921. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
210922. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
210923. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
210924. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK
210925. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
210926. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__reset_reg_MASK
210927. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT
210928. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
210929. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
210930. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK
210931. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
210932. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK
210933. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
210934. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
210935. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
210936. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK
210937. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
210938. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK
210939. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
210940. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK
210941. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
210942. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK
210943. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
210944. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK
210945. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
210946. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
210947. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
210948. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
210949. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
210950. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_gd_MASK
210951. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT
210952. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
210953. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
210954. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK
210955. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
210956. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vp_MASK
210957. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT
210958. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
210959. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
210960. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK
210961. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
210962. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
210963. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
210964. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__NC76_MASK
210965. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__NC76__SHIFT
210966. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
210967. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
210968. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__atb_select_MASK
210969. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT
210970. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK
210971. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT
210972. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK
210973. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT
210974. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK
210975. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
210976. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK
210977. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT
210978. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK
210979. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT
210980. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC40_MASK
210981. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC40__SHIFT
210982. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC76_MASK
210983. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC76__SHIFT
210984. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK
210985. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
210986. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK
210987. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT
210988. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
210989. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
210990. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__cal_reg_MASK
210991. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT
210992. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__enable_reg_MASK
210993. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT
210994. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
210995. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
210996. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK
210997. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
210998. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK
210999. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
211000. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
211001. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
211002. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK
211003. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
211004. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__reset_reg_MASK
211005. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT
211006. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
211007. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
211008. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_atb_MASK
211009. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT
211010. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK
211011. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
211012. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK
211013. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
211014. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK
211015. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
211016. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
211017. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
211018. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
211019. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
211020. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
211021. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
211022. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK
211023. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
211024. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
211025. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
211026. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
211027. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
211028. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
211029. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
211030. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
211031. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
211032. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK
211033. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
211034. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
211035. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
211036. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
211037. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
211038. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
211039. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
211040. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
211041. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
211042. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
211043. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
211044. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
211045. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
211046. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
211047. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
211048. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
211049. DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
211050. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
211051. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
211052. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
211053. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
211054. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
211055. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
211056. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
211057. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
211058. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
211059. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
211060. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
211061. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
211062. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
211063. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
211064. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
211065. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
211066. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
211067. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
211068. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
211069. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
211070. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
211071. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
211072. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
211073. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
211074. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
211075. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
211076. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
211077. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
211078. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
211079. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
211080. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
211081. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
211082. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
211083. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
211084. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
211085. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
211086. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
211087. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
211088. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
211089. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
211090. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
211091. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
211092. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
211093. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
211094. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
211095. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
211096. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
211097. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
211098. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
211099. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
211100. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
211101. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
211102. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
211103. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
211104. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
211105. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
211106. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
211107. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
211108. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
211109. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
211110. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
211111. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
211112. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
211113. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
211114. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
211115. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
211116. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
211117. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
211118. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
211119. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
211120. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK
211121. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT
211122. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
211123. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
211124. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__BG_EN_MASK
211125. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__BG_EN__SHIFT
211126. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK
211127. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT
211128. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK
211129. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT
211130. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__PHY_RESET_MASK
211131. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT
211132. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
211133. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
211134. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK
211135. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT
211136. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
211137. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
211138. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK
211139. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT
211140. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK
211141. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT
211142. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK
211143. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
211144. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK
211145. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT
211146. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK
211147. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
211148. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK
211149. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT
211150. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK
211151. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT
211152. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK
211153. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT
211154. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK
211155. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
211156. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI__data_MASK
211157. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI__data__SHIFT
211158. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO__data_MASK
211159. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO__data__SHIFT
211160. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
211161. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
211162. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
211163. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
211164. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
211165. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
211166. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
211167. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
211168. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
211169. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
211170. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
211171. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
211172. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
211173. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
211174. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
211175. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
211176. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
211177. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
211178. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
211179. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
211180. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
211181. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
211182. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
211183. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
211184. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
211185. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
211186. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
211187. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
211188. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
211189. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
211190. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
211191. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
211192. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
211193. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
211194. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
211195. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
211196. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
211197. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
211198. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
211199. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
211200. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
211201. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
211202. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
211203. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
211204. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
211205. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
211206. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
211207. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
211208. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
211209. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
211210. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
211211. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
211212. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
211213. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
211214. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
211215. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
211216. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
211217. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
211218. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
211219. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
211220. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
211221. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
211222. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
211223. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
211224. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
211225. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
211226. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
211227. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
211228. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
211229. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
211230. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
211231. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
211232. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
211233. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
211234. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
211235. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
211236. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
211237. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
211238. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
211239. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
211240. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
211241. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
211242. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
211243. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
211244. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
211245. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
211246. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
211247. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
211248. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
211249. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
211250. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
211251. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
211252. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
211253. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
211254. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
211255. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
211256. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
211257. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
211258. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
211259. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
211260. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
211261. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
211262. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
211263. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
211264. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
211265. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
211266. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
211267. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
211268. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
211269. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
211270. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
211271. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
211272. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
211273. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
211274. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
211275. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
211276. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
211277. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
211278. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
211279. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
211280. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
211281. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
211282. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
211283. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
211284. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
211285. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
211286. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
211287. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
211288. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
211289. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
211290. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
211291. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
211292. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
211293. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
211294. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
211295. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
211296. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
211297. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
211298. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
211299. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
211300. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
211301. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
211302. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
211303. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
211304. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
211305. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
211306. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
211307. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
211308. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
211309. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
211310. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
211311. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
211312. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
211313. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
211314. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
211315. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
211316. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
211317. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
211318. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
211319. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
211320. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
211321. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
211322. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
211323. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
211324. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
211325. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
211326. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
211327. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
211328. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
211329. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
211330. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
211331. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
211332. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
211333. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
211334. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
211335. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
211336. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
211337. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
211338. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
211339. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
211340. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
211341. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
211342. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
211343. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
211344. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
211345. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
211346. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
211347. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
211348. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
211349. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
211350. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
211351. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
211352. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
211353. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
211354. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
211355. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
211356. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
211357. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
211358. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
211359. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
211360. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
211361. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
211362. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
211363. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
211364. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
211365. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
211366. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
211367. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
211368. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
211369. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
211370. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
211371. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
211372. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
211373. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
211374. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
211375. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
211376. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
211377. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
211378. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
211379. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
211380. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
211381. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
211382. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
211383. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
211384. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
211385. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
211386. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
211387. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
211388. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
211389. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
211390. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
211391. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
211392. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
211393. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
211394. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
211395. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
211396. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
211397. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
211398. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
211399. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
211400. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
211401. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
211402. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
211403. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
211404. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
211405. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
211406. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
211407. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
211408. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
211409. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
211410. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
211411. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
211412. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
211413. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
211414. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
211415. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
211416. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
211417. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
211418. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
211419. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
211420. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
211421. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
211422. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
211423. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
211424. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
211425. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
211426. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
211427. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
211428. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
211429. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
211430. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
211431. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
211432. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
211433. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
211434. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
211435. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
211436. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
211437. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
211438. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
211439. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
211440. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
211441. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
211442. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
211443. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
211444. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
211445. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
211446. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
211447. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
211448. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
211449. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
211450. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
211451. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
211452. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
211453. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
211454. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
211455. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
211456. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
211457. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
211458. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
211459. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
211460. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
211461. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
211462. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
211463. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
211464. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
211465. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
211466. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
211467. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
211468. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
211469. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
211470. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
211471. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
211472. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
211473. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
211474. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
211475. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
211476. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
211477. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
211478. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
211479. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
211480. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
211481. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
211482. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
211483. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
211484. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
211485. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
211486. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
211487. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
211488. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
211489. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
211490. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
211491. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
211492. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
211493. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
211494. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
211495. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
211496. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
211497. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
211498. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
211499. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
211500. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
211501. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
211502. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
211503. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
211504. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK
211505. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
211506. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
211507. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
211508. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
211509. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
211510. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
211511. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
211512. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
211513. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
211514. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
211515. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
211516. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
211517. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
211518. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
211519. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
211520. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
211521. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
211522. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
211523. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
211524. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
211525. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
211526. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
211527. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
211528. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
211529. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
211530. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
211531. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
211532. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK
211533. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
211534. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK
211535. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
211536. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK
211537. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
211538. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__STAT_MASK
211539. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__STAT__SHIFT
211540. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
211541. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
211542. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
211543. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
211544. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
211545. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
211546. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
211547. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
211548. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
211549. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
211550. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
211551. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
211552. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
211553. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
211554. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
211555. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
211556. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
211557. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
211558. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
211559. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
211560. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
211561. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
211562. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
211563. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
211564. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
211565. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
211566. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
211567. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
211568. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
211569. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
211570. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
211571. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
211572. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
211573. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
211574. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
211575. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
211576. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
211577. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
211578. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
211579. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
211580. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
211581. DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
211582. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
211583. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
211584. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
211585. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
211586. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
211587. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
211588. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
211589. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
211590. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
211591. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
211592. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK
211593. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT
211594. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
211595. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
211596. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
211597. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
211598. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
211599. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
211600. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
211601. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
211602. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
211603. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
211604. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
211605. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
211606. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
211607. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
211608. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
211609. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
211610. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
211611. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
211612. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
211613. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
211614. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
211615. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
211616. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
211617. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
211618. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
211619. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
211620. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
211621. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
211622. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
211623. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
211624. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK
211625. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
211626. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK
211627. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
211628. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK
211629. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
211630. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
211631. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
211632. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
211633. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
211634. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
211635. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
211636. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
211637. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
211638. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
211639. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
211640. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
211641. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
211642. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
211643. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
211644. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
211645. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
211646. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
211647. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
211648. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
211649. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
211650. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
211651. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
211652. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
211653. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
211654. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
211655. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
211656. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
211657. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
211658. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
211659. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
211660. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
211661. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
211662. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
211663. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
211664. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
211665. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
211666. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
211667. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
211668. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
211669. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
211670. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK
211671. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
211672. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK
211673. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
211674. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
211675. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
211676. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
211677. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
211678. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
211679. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
211680. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
211681. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
211682. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK
211683. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
211684. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
211685. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
211686. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
211687. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
211688. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
211689. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
211690. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
211691. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
211692. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
211693. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
211694. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__NC32_MASK
211695. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT
211696. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
211697. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
211698. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
211699. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
211700. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
211701. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
211702. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
211703. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
211704. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
211705. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
211706. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK
211707. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
211708. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
211709. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
211710. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
211711. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
211712. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
211713. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
211714. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
211715. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
211716. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
211717. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
211718. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK
211719. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
211720. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
211721. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
211722. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
211723. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
211724. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
211725. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
211726. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
211727. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
211728. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK
211729. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT
211730. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
211731. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
211732. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
211733. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
211734. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
211735. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
211736. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
211737. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
211738. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
211739. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
211740. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
211741. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
211742. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
211743. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
211744. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
211745. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
211746. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
211747. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
211748. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
211749. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
211750. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__NC20_MASK
211751. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__NC20__SHIFT
211752. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK
211753. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT
211754. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
211755. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
211756. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
211757. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
211758. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
211759. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
211760. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK
211761. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
211762. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK
211763. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
211764. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
211765. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
211766. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK
211767. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
211768. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK
211769. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
211770. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK
211771. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT
211772. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
211773. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
211774. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK
211775. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT
211776. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK
211777. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT
211778. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
211779. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
211780. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK
211781. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT
211782. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_gd_MASK
211783. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_gd__SHIFT
211784. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccm_MASK
211785. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT
211786. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccp_MASK
211787. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT
211788. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vptx_MASK
211789. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT
211790. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg0_MASK
211791. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT
211792. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg1_MASK
211793. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT
211794. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK
211795. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT
211796. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__override_regref_0_MASK
211797. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT
211798. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK
211799. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT
211800. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_nbias_MASK
211801. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT
211802. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_pbias_MASK
211803. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT
211804. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK
211805. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT
211806. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfm_MASK
211807. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT
211808. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfp_MASK
211809. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT
211810. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsm_MASK
211811. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT
211812. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsp_MASK
211813. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT
211814. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_vcm_MASK
211815. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT
211816. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
211817. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
211818. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK
211819. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
211820. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
211821. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
211822. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
211823. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
211824. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
211825. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
211826. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
211827. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
211828. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK
211829. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT
211830. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK
211831. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
211832. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__nc_MASK
211833. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__nc__SHIFT
211834. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_nmos_MASK
211835. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_nmos__SHIFT
211836. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_pmos_MASK
211837. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_pmos__SHIFT
211838. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__override_rxdetref_MASK
211839. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT
211840. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
211841. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
211842. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
211843. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
211844. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
211845. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
211846. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
211847. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
211848. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK
211849. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
211850. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
211851. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
211852. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
211853. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
211854. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
211855. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
211856. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
211857. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
211858. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
211859. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
211860. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
211861. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
211862. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
211863. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
211864. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
211865. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
211866. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
211867. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
211868. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
211869. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
211870. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
211871. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
211872. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
211873. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
211874. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
211875. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
211876. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
211877. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
211878. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
211879. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
211880. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK
211881. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
211882. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK
211883. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
211884. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
211885. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
211886. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK
211887. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
211888. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
211889. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
211890. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
211891. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
211892. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK
211893. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
211894. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
211895. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
211896. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
211897. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
211898. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
211899. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
211900. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
211901. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
211902. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
211903. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
211904. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
211905. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
211906. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK
211907. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
211908. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK
211909. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT
211910. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_MASK
211911. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT
211912. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK
211913. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
211914. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
211915. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
211916. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK
211917. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
211918. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK
211919. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
211920. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK
211921. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
211922. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK
211923. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT
211924. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
211925. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
211926. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
211927. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
211928. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
211929. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
211930. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
211931. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
211932. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
211933. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
211934. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
211935. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
211936. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
211937. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
211938. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
211939. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
211940. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
211941. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
211942. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
211943. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
211944. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
211945. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
211946. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
211947. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
211948. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
211949. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
211950. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
211951. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
211952. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
211953. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
211954. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
211955. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
211956. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
211957. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
211958. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
211959. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
211960. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
211961. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
211962. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
211963. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
211964. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
211965. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
211966. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
211967. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
211968. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
211969. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
211970. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
211971. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
211972. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
211973. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
211974. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
211975. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
211976. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
211977. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
211978. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
211979. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
211980. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
211981. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
211982. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
211983. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
211984. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
211985. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
211986. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
211987. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
211988. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
211989. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
211990. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
211991. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
211992. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
211993. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
211994. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
211995. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
211996. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
211997. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
211998. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
211999. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
212000. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
212001. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
212002. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
212003. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
212004. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
212005. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
212006. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
212007. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
212008. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
212009. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
212010. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
212011. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
212012. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
212013. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
212014. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
212015. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
212016. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
212017. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
212018. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
212019. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
212020. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
212021. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
212022. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
212023. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
212024. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
212025. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
212026. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
212027. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
212028. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
212029. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
212030. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
212031. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
212032. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
212033. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
212034. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
212035. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
212036. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
212037. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
212038. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
212039. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
212040. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
212041. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
212042. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
212043. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
212044. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
212045. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
212046. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
212047. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
212048. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
212049. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
212050. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
212051. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
212052. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
212053. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
212054. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
212055. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
212056. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
212057. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
212058. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
212059. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
212060. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
212061. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
212062. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
212063. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
212064. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
212065. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
212066. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
212067. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
212068. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
212069. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
212070. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
212071. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
212072. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
212073. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
212074. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
212075. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
212076. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
212077. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
212078. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
212079. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
212080. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
212081. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
212082. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
212083. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
212084. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
212085. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
212086. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
212087. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
212088. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
212089. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
212090. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
212091. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
212092. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
212093. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
212094. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
212095. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
212096. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
212097. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
212098. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
212099. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
212100. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
212101. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
212102. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
212103. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
212104. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
212105. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
212106. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
212107. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
212108. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
212109. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
212110. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
212111. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
212112. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
212113. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
212114. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
212115. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
212116. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
212117. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
212118. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
212119. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
212120. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
212121. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
212122. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
212123. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
212124. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
212125. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
212126. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
212127. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
212128. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
212129. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
212130. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
212131. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
212132. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
212133. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
212134. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
212135. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
212136. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
212137. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
212138. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
212139. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
212140. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
212141. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
212142. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
212143. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
212144. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
212145. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
212146. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
212147. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
212148. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
212149. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
212150. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
212151. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
212152. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
212153. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
212154. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
212155. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
212156. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
212157. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
212158. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
212159. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
212160. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
212161. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
212162. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
212163. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
212164. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
212165. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
212166. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
212167. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
212168. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK
212169. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
212170. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
212171. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
212172. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
212173. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
212174. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
212175. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
212176. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
212177. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
212178. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
212179. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
212180. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
212181. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
212182. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
212183. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
212184. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
212185. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
212186. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
212187. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
212188. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
212189. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
212190. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
212191. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
212192. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
212193. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
212194. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
212195. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
212196. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
212197. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
212198. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
212199. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
212200. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
212201. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
212202. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
212203. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
212204. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
212205. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
212206. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
212207. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
212208. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
212209. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
212210. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
212211. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
212212. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
212213. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
212214. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
212215. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
212216. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
212217. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
212218. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
212219. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
212220. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
212221. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
212222. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
212223. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
212224. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
212225. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
212226. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
212227. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
212228. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
212229. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
212230. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
212231. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
212232. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
212233. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
212234. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
212235. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
212236. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
212237. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
212238. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
212239. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
212240. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
212241. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
212242. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
212243. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
212244. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
212245. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
212246. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
212247. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
212248. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
212249. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
212250. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
212251. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
212252. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
212253. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
212254. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
212255. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
212256. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
212257. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
212258. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
212259. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
212260. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
212261. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
212262. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
212263. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
212264. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
212265. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
212266. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
212267. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
212268. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
212269. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
212270. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
212271. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
212272. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
212273. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
212274. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
212275. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
212276. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
212277. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
212278. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
212279. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
212280. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
212281. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
212282. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
212283. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
212284. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
212285. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
212286. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
212287. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
212288. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
212289. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
212290. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
212291. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
212292. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
212293. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
212294. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
212295. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
212296. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
212297. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
212298. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
212299. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
212300. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
212301. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
212302. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
212303. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
212304. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
212305. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
212306. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
212307. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
212308. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
212309. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
212310. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
212311. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
212312. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
212313. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
212314. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
212315. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
212316. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
212317. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
212318. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
212319. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
212320. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
212321. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
212322. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
212323. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
212324. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
212325. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
212326. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
212327. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
212328. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
212329. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
212330. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
212331. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
212332. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
212333. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
212334. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
212335. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
212336. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
212337. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
212338. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
212339. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
212340. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
212341. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
212342. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
212343. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
212344. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
212345. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
212346. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
212347. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
212348. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
212349. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
212350. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
212351. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
212352. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
212353. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
212354. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
212355. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
212356. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
212357. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
212358. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
212359. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
212360. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
212361. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
212362. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
212363. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
212364. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
212365. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
212366. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
212367. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
212368. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
212369. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
212370. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
212371. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
212372. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
212373. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
212374. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
212375. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
212376. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
212377. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
212378. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
212379. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
212380. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
212381. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
212382. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
212383. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
212384. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
212385. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
212386. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
212387. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
212388. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
212389. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
212390. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
212391. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
212392. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
212393. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
212394. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
212395. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
212396. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
212397. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
212398. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
212399. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
212400. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
212401. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
212402. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
212403. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
212404. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
212405. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
212406. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
212407. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
212408. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
212409. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
212410. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
212411. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
212412. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
212413. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
212414. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
212415. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
212416. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
212417. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
212418. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
212419. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
212420. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
212421. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
212422. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
212423. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
212424. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
212425. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
212426. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
212427. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
212428. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
212429. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
212430. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
212431. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
212432. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
212433. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
212434. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
212435. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
212436. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
212437. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
212438. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
212439. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
212440. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
212441. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
212442. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
212443. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
212444. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
212445. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
212446. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
212447. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
212448. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
212449. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
212450. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
212451. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
212452. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
212453. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
212454. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
212455. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
212456. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
212457. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
212458. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
212459. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
212460. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
212461. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
212462. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
212463. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
212464. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
212465. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
212466. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
212467. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
212468. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
212469. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
212470. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
212471. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
212472. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
212473. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
212474. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
212475. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
212476. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
212477. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
212478. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
212479. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
212480. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
212481. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
212482. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
212483. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
212484. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
212485. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
212486. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
212487. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
212488. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
212489. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
212490. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
212491. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
212492. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
212493. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
212494. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
212495. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
212496. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
212497. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
212498. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
212499. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
212500. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
212501. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
212502. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
212503. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
212504. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
212505. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
212506. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
212507. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
212508. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
212509. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
212510. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
212511. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
212512. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
212513. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
212514. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
212515. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
212516. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
212517. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
212518. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
212519. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
212520. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
212521. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
212522. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
212523. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
212524. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
212525. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
212526. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
212527. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
212528. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
212529. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
212530. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
212531. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
212532. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
212533. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
212534. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
212535. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
212536. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
212537. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
212538. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
212539. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
212540. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
212541. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
212542. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
212543. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
212544. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
212545. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
212546. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
212547. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
212548. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
212549. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
212550. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
212551. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
212552. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
212553. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
212554. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
212555. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
212556. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
212557. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
212558. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
212559. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
212560. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
212561. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
212562. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
212563. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
212564. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
212565. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
212566. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
212567. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
212568. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
212569. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
212570. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
212571. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
212572. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
212573. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
212574. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
212575. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
212576. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
212577. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
212578. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
212579. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
212580. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
212581. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
212582. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
212583. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
212584. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
212585. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
212586. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
212587. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
212588. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
212589. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
212590. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
212591. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
212592. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
212593. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
212594. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
212595. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
212596. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
212597. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
212598. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
212599. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
212600. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
212601. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
212602. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
212603. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
212604. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
212605. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
212606. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
212607. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
212608. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
212609. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
212610. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
212611. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
212612. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
212613. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
212614. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
212615. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
212616. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
212617. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
212618. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
212619. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
212620. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
212621. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
212622. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
212623. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
212624. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
212625. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
212626. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
212627. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
212628. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
212629. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
212630. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
212631. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
212632. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
212633. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
212634. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
212635. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
212636. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
212637. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
212638. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
212639. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
212640. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
212641. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
212642. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
212643. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
212644. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
212645. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
212646. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
212647. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
212648. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
212649. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
212650. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
212651. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
212652. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
212653. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
212654. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
212655. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
212656. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
212657. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
212658. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
212659. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
212660. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
212661. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
212662. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
212663. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
212664. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
212665. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
212666. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
212667. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
212668. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
212669. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
212670. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
212671. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
212672. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
212673. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
212674. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
212675. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
212676. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
212677. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
212678. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
212679. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
212680. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
212681. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
212682. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
212683. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
212684. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
212685. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
212686. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
212687. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
212688. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
212689. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
212690. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
212691. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
212692. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
212693. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
212694. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
212695. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
212696. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
212697. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
212698. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
212699. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
212700. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
212701. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
212702. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
212703. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
212704. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
212705. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
212706. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
212707. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
212708. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
212709. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
212710. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
212711. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
212712. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
212713. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
212714. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
212715. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
212716. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
212717. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
212718. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
212719. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
212720. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
212721. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
212722. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
212723. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
212724. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK
212725. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT
212726. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__MODE_MASK
212727. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT
212728. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
212729. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
212730. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK
212731. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT
212732. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK
212733. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT
212734. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__OV14_MASK
212735. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT
212736. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
212737. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
212738. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
212739. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
212740. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
212741. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
212742. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
212743. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
212744. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
212745. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
212746. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
212747. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
212748. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
212749. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
212750. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
212751. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
212752. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
212753. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
212754. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
212755. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
212756. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
212757. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
212758. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
212759. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
212760. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
212761. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
212762. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
212763. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
212764. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
212765. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
212766. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
212767. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
212768. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
212769. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
212770. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
212771. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
212772. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
212773. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
212774. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
212775. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
212776. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
212777. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
212778. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
212779. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
212780. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
212781. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
212782. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
212783. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
212784. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
212785. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
212786. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
212787. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
212788. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
212789. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
212790. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
212791. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
212792. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
212793. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
212794. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
212795. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
212796. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
212797. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
212798. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
212799. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
212800. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
212801. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
212802. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
212803. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
212804. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
212805. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
212806. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
212807. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
212808. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
212809. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
212810. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
212811. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
212812. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
212813. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
212814. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
212815. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
212816. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
212817. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
212818. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
212819. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
212820. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
212821. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
212822. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
212823. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
212824. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
212825. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
212826. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
212827. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
212828. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
212829. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
212830. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
212831. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
212832. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
212833. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
212834. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
212835. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
212836. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
212837. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
212838. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
212839. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
212840. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
212841. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
212842. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
212843. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
212844. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
212845. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
212846. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
212847. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
212848. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
212849. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
212850. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
212851. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
212852. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
212853. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
212854. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
212855. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
212856. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
212857. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
212858. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
212859. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
212860. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
212861. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
212862. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
212863. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
212864. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
212865. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
212866. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
212867. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
212868. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
212869. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
212870. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
212871. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
212872. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
212873. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
212874. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
212875. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
212876. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
212877. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
212878. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
212879. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
212880. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
212881. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
212882. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
212883. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
212884. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
212885. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
212886. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
212887. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
212888. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
212889. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
212890. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
212891. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
212892. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
212893. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
212894. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
212895. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
212896. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
212897. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
212898. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
212899. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
212900. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
212901. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
212902. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
212903. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
212904. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
212905. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
212906. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
212907. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
212908. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
212909. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
212910. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
212911. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
212912. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
212913. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
212914. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
212915. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
212916. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
212917. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
212918. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
212919. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
212920. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
212921. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
212922. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
212923. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
212924. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
212925. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
212926. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
212927. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
212928. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
212929. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
212930. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
212931. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
212932. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
212933. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
212934. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
212935. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
212936. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
212937. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
212938. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
212939. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
212940. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
212941. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
212942. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
212943. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
212944. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
212945. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
212946. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
212947. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
212948. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
212949. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
212950. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
212951. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
212952. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
212953. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
212954. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
212955. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
212956. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
212957. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
212958. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
212959. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
212960. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
212961. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
212962. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
212963. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
212964. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
212965. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
212966. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
212967. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
212968. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
212969. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
212970. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
212971. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
212972. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
212973. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
212974. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
212975. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
212976. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
212977. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
212978. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
212979. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
212980. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
212981. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
212982. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
212983. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
212984. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
212985. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
212986. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
212987. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
212988. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
212989. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
212990. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
212991. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
212992. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
212993. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
212994. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
212995. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
212996. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
212997. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
212998. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
212999. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
213000. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
213001. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
213002. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
213003. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
213004. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
213005. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
213006. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
213007. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
213008. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
213009. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
213010. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
213011. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
213012. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
213013. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
213014. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
213015. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
213016. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
213017. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
213018. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
213019. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
213020. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
213021. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
213022. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
213023. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
213024. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
213025. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
213026. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
213027. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
213028. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
213029. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
213030. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
213031. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
213032. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
213033. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
213034. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
213035. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
213036. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
213037. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
213038. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
213039. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
213040. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
213041. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
213042. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
213043. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
213044. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
213045. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
213046. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
213047. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
213048. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
213049. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
213050. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
213051. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
213052. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
213053. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
213054. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
213055. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
213056. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
213057. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
213058. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
213059. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
213060. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
213061. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
213062. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
213063. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
213064. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
213065. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
213066. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
213067. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
213068. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
213069. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
213070. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
213071. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
213072. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
213073. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
213074. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
213075. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
213076. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
213077. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
213078. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK
213079. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT
213080. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK
213081. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT
213082. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
213083. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
213084. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
213085. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
213086. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
213087. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
213088. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
213089. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
213090. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
213091. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
213092. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
213093. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
213094. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
213095. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
213096. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
213097. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
213098. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
213099. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
213100. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
213101. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
213102. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
213103. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
213104. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
213105. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
213106. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
213107. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
213108. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
213109. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
213110. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
213111. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
213112. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
213113. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
213114. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
213115. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
213116. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
213117. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
213118. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
213119. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
213120. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
213121. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
213122. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
213123. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
213124. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
213125. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
213126. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
213127. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
213128. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
213129. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
213130. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
213131. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
213132. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
213133. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
213134. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
213135. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
213136. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
213137. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
213138. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
213139. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
213140. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
213141. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
213142. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
213143. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
213144. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
213145. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
213146. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
213147. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
213148. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
213149. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
213150. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
213151. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
213152. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
213153. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
213154. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
213155. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
213156. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
213157. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
213158. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
213159. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
213160. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
213161. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
213162. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
213163. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
213164. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
213165. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
213166. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
213167. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
213168. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
213169. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
213170. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
213171. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
213172. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
213173. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
213174. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
213175. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
213176. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
213177. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
213178. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
213179. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
213180. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
213181. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
213182. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
213183. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
213184. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
213185. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
213186. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
213187. DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
213188. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
213189. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
213190. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
213191. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
213192. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
213193. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
213194. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
213195. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
213196. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
213197. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
213198. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK
213199. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT
213200. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
213201. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
213202. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
213203. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
213204. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
213205. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
213206. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
213207. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
213208. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
213209. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
213210. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
213211. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
213212. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
213213. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
213214. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
213215. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
213216. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
213217. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
213218. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
213219. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
213220. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
213221. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
213222. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
213223. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
213224. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
213225. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
213226. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
213227. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
213228. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
213229. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
213230. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK
213231. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
213232. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK
213233. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
213234. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK
213235. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
213236. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
213237. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
213238. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
213239. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
213240. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
213241. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
213242. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
213243. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
213244. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
213245. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
213246. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
213247. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
213248. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
213249. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
213250. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
213251. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
213252. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
213253. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
213254. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
213255. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
213256. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
213257. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
213258. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
213259. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
213260. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
213261. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
213262. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
213263. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
213264. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
213265. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
213266. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
213267. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
213268. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
213269. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
213270. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
213271. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
213272. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
213273. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
213274. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
213275. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
213276. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK
213277. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
213278. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK
213279. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
213280. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
213281. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
213282. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
213283. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
213284. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
213285. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
213286. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
213287. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
213288. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK
213289. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
213290. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
213291. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
213292. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
213293. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
213294. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
213295. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
213296. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
213297. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
213298. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
213299. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
213300. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__NC32_MASK
213301. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT
213302. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
213303. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
213304. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
213305. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
213306. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
213307. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
213308. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
213309. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
213310. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
213311. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
213312. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK
213313. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
213314. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
213315. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
213316. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
213317. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
213318. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
213319. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
213320. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
213321. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
213322. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
213323. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
213324. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK
213325. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
213326. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
213327. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
213328. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
213329. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
213330. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
213331. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
213332. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
213333. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
213334. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK
213335. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT
213336. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
213337. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
213338. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
213339. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
213340. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
213341. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
213342. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
213343. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
213344. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
213345. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
213346. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
213347. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
213348. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
213349. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
213350. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
213351. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
213352. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
213353. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
213354. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
213355. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
213356. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__NC20_MASK
213357. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__NC20__SHIFT
213358. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK
213359. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT
213360. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
213361. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
213362. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
213363. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
213364. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
213365. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
213366. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK
213367. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
213368. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK
213369. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
213370. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
213371. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
213372. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK
213373. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
213374. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK
213375. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
213376. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK
213377. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT
213378. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
213379. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
213380. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK
213381. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT
213382. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK
213383. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT
213384. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
213385. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
213386. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK
213387. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT
213388. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_gd_MASK
213389. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_gd__SHIFT
213390. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccm_MASK
213391. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT
213392. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccp_MASK
213393. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT
213394. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vptx_MASK
213395. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT
213396. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg0_MASK
213397. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT
213398. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg1_MASK
213399. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT
213400. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK
213401. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT
213402. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__override_regref_0_MASK
213403. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT
213404. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK
213405. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT
213406. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_nbias_MASK
213407. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT
213408. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_pbias_MASK
213409. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT
213410. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK
213411. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT
213412. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfm_MASK
213413. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT
213414. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfp_MASK
213415. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT
213416. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsm_MASK
213417. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT
213418. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsp_MASK
213419. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT
213420. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_vcm_MASK
213421. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT
213422. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
213423. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
213424. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK
213425. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
213426. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
213427. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
213428. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
213429. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
213430. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
213431. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
213432. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
213433. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
213434. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK
213435. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT
213436. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK
213437. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
213438. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__nc_MASK
213439. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__nc__SHIFT
213440. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_nmos_MASK
213441. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_nmos__SHIFT
213442. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_pmos_MASK
213443. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_pmos__SHIFT
213444. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__override_rxdetref_MASK
213445. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT
213446. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
213447. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
213448. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
213449. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
213450. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
213451. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
213452. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
213453. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
213454. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK
213455. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
213456. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
213457. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
213458. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
213459. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
213460. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
213461. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
213462. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
213463. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
213464. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
213465. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
213466. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
213467. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
213468. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
213469. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
213470. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
213471. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
213472. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
213473. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
213474. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
213475. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
213476. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
213477. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
213478. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
213479. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
213480. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
213481. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
213482. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
213483. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
213484. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
213485. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
213486. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK
213487. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
213488. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK
213489. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
213490. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
213491. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
213492. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK
213493. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
213494. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
213495. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
213496. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
213497. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
213498. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK
213499. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
213500. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
213501. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
213502. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
213503. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
213504. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
213505. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
213506. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
213507. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
213508. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
213509. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
213510. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
213511. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
213512. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK
213513. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
213514. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK
213515. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT
213516. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_MASK
213517. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT
213518. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK
213519. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
213520. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
213521. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
213522. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK
213523. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
213524. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK
213525. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
213526. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK
213527. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
213528. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK
213529. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT
213530. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
213531. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
213532. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
213533. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
213534. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
213535. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
213536. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
213537. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
213538. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
213539. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
213540. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
213541. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
213542. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
213543. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
213544. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
213545. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
213546. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
213547. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
213548. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
213549. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
213550. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
213551. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
213552. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
213553. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
213554. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
213555. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
213556. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
213557. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
213558. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
213559. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
213560. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
213561. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
213562. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
213563. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
213564. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
213565. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
213566. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
213567. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
213568. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
213569. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
213570. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
213571. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
213572. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
213573. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
213574. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
213575. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
213576. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
213577. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
213578. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
213579. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
213580. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
213581. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
213582. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
213583. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
213584. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
213585. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
213586. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
213587. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
213588. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
213589. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
213590. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
213591. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
213592. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
213593. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
213594. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
213595. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
213596. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
213597. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
213598. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
213599. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
213600. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
213601. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
213602. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
213603. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
213604. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
213605. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
213606. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
213607. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
213608. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
213609. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
213610. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
213611. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
213612. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
213613. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
213614. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
213615. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
213616. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
213617. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
213618. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
213619. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
213620. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
213621. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
213622. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
213623. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
213624. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
213625. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
213626. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
213627. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
213628. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
213629. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
213630. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
213631. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
213632. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
213633. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
213634. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
213635. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
213636. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
213637. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
213638. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
213639. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
213640. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
213641. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
213642. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
213643. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
213644. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
213645. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
213646. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
213647. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
213648. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
213649. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
213650. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
213651. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
213652. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
213653. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
213654. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
213655. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
213656. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
213657. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
213658. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
213659. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
213660. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
213661. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
213662. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
213663. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
213664. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
213665. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
213666. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
213667. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
213668. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
213669. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
213670. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
213671. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
213672. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
213673. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
213674. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
213675. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
213676. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
213677. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
213678. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
213679. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
213680. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
213681. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
213682. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
213683. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
213684. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
213685. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
213686. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
213687. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
213688. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
213689. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
213690. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
213691. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
213692. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
213693. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
213694. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
213695. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
213696. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
213697. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
213698. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
213699. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
213700. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
213701. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
213702. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
213703. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
213704. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
213705. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
213706. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
213707. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
213708. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
213709. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
213710. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
213711. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
213712. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
213713. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
213714. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
213715. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
213716. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
213717. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
213718. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
213719. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
213720. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
213721. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
213722. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
213723. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
213724. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
213725. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
213726. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
213727. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
213728. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
213729. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
213730. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
213731. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
213732. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
213733. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
213734. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
213735. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
213736. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
213737. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
213738. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
213739. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
213740. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
213741. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
213742. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
213743. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
213744. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
213745. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
213746. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
213747. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
213748. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
213749. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
213750. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
213751. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
213752. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
213753. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
213754. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
213755. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
213756. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
213757. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
213758. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
213759. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
213760. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
213761. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
213762. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
213763. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
213764. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
213765. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
213766. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
213767. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
213768. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
213769. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
213770. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
213771. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
213772. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
213773. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
213774. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK
213775. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
213776. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
213777. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
213778. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
213779. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
213780. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
213781. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
213782. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
213783. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
213784. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
213785. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
213786. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
213787. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
213788. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
213789. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
213790. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
213791. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
213792. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
213793. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
213794. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
213795. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
213796. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
213797. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
213798. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
213799. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
213800. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
213801. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
213802. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
213803. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
213804. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
213805. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
213806. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
213807. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
213808. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
213809. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
213810. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
213811. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
213812. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
213813. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
213814. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
213815. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
213816. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
213817. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
213818. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
213819. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
213820. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
213821. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
213822. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
213823. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
213824. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
213825. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
213826. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
213827. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
213828. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
213829. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
213830. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
213831. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
213832. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
213833. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
213834. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
213835. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
213836. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
213837. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
213838. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
213839. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
213840. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
213841. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
213842. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
213843. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
213844. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
213845. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
213846. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
213847. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
213848. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
213849. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
213850. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
213851. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
213852. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
213853. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
213854. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
213855. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
213856. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
213857. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
213858. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
213859. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
213860. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
213861. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
213862. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
213863. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
213864. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
213865. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
213866. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
213867. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
213868. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
213869. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
213870. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
213871. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
213872. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
213873. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
213874. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
213875. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
213876. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
213877. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
213878. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
213879. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
213880. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
213881. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
213882. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
213883. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
213884. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
213885. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
213886. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
213887. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
213888. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
213889. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
213890. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
213891. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
213892. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
213893. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
213894. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
213895. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
213896. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
213897. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
213898. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
213899. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
213900. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
213901. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
213902. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
213903. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
213904. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
213905. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
213906. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
213907. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
213908. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
213909. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
213910. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
213911. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
213912. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
213913. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
213914. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
213915. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
213916. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
213917. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
213918. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
213919. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
213920. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
213921. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
213922. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
213923. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
213924. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
213925. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
213926. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
213927. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
213928. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
213929. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
213930. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
213931. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
213932. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
213933. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
213934. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
213935. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
213936. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
213937. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
213938. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
213939. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
213940. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
213941. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
213942. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
213943. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
213944. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
213945. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
213946. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
213947. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
213948. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
213949. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
213950. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
213951. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
213952. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
213953. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
213954. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
213955. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
213956. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
213957. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
213958. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
213959. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
213960. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
213961. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
213962. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
213963. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
213964. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
213965. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
213966. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
213967. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
213968. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
213969. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
213970. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
213971. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
213972. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
213973. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
213974. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
213975. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
213976. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
213977. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
213978. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
213979. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
213980. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
213981. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
213982. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
213983. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
213984. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
213985. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
213986. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
213987. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
213988. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
213989. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
213990. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
213991. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
213992. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
213993. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
213994. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
213995. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
213996. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
213997. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
213998. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
213999. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
214000. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
214001. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
214002. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
214003. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
214004. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
214005. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
214006. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
214007. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
214008. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
214009. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
214010. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
214011. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
214012. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
214013. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
214014. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
214015. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
214016. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
214017. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
214018. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
214019. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
214020. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
214021. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
214022. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
214023. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
214024. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
214025. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
214026. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
214027. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
214028. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
214029. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
214030. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
214031. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
214032. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
214033. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
214034. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
214035. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
214036. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
214037. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
214038. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
214039. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
214040. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
214041. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
214042. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
214043. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
214044. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
214045. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
214046. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
214047. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
214048. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
214049. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
214050. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
214051. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
214052. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
214053. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
214054. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
214055. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
214056. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
214057. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
214058. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
214059. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
214060. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
214061. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
214062. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
214063. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
214064. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
214065. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
214066. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
214067. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
214068. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
214069. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
214070. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
214071. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
214072. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
214073. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
214074. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
214075. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
214076. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
214077. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
214078. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
214079. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
214080. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
214081. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
214082. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
214083. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
214084. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
214085. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
214086. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
214087. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
214088. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
214089. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
214090. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
214091. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
214092. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
214093. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
214094. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
214095. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
214096. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
214097. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
214098. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
214099. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
214100. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
214101. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
214102. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
214103. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
214104. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
214105. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
214106. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
214107. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
214108. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
214109. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
214110. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
214111. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
214112. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
214113. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
214114. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
214115. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
214116. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
214117. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
214118. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
214119. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
214120. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
214121. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
214122. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
214123. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
214124. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
214125. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
214126. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
214127. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
214128. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
214129. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
214130. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
214131. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
214132. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
214133. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
214134. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
214135. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
214136. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
214137. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
214138. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
214139. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
214140. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
214141. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
214142. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
214143. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
214144. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
214145. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
214146. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
214147. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
214148. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
214149. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
214150. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
214151. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
214152. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
214153. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
214154. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
214155. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
214156. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
214157. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
214158. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
214159. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
214160. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
214161. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
214162. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
214163. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
214164. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
214165. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
214166. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
214167. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
214168. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
214169. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
214170. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
214171. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
214172. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
214173. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
214174. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
214175. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
214176. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
214177. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
214178. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
214179. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
214180. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
214181. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
214182. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
214183. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
214184. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
214185. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
214186. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
214187. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
214188. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
214189. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
214190. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
214191. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
214192. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
214193. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
214194. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
214195. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
214196. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
214197. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
214198. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
214199. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
214200. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
214201. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
214202. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
214203. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
214204. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
214205. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
214206. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
214207. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
214208. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
214209. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
214210. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
214211. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
214212. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
214213. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
214214. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
214215. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
214216. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
214217. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
214218. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
214219. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
214220. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
214221. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
214222. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
214223. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
214224. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
214225. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
214226. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
214227. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
214228. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
214229. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
214230. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
214231. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
214232. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
214233. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
214234. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
214235. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
214236. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
214237. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
214238. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
214239. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
214240. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
214241. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
214242. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
214243. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
214244. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
214245. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
214246. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
214247. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
214248. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
214249. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
214250. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
214251. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
214252. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
214253. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
214254. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
214255. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
214256. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
214257. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
214258. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
214259. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
214260. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
214261. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
214262. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
214263. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
214264. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
214265. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
214266. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
214267. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
214268. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
214269. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
214270. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
214271. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
214272. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
214273. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
214274. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
214275. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
214276. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
214277. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
214278. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
214279. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
214280. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
214281. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
214282. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
214283. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
214284. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
214285. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
214286. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
214287. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
214288. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
214289. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
214290. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
214291. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
214292. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
214293. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
214294. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
214295. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
214296. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
214297. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
214298. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
214299. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
214300. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
214301. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
214302. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
214303. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
214304. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
214305. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
214306. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
214307. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
214308. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
214309. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
214310. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
214311. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
214312. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
214313. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
214314. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
214315. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
214316. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
214317. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
214318. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
214319. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
214320. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
214321. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
214322. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
214323. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
214324. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
214325. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
214326. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
214327. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
214328. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
214329. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
214330. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK
214331. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT
214332. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK
214333. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT
214334. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
214335. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
214336. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK
214337. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT
214338. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK
214339. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT
214340. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK
214341. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT
214342. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
214343. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
214344. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
214345. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
214346. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
214347. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
214348. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
214349. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
214350. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
214351. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
214352. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
214353. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
214354. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
214355. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
214356. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
214357. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
214358. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
214359. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
214360. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
214361. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
214362. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
214363. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
214364. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
214365. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
214366. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
214367. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
214368. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
214369. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
214370. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
214371. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
214372. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
214373. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
214374. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
214375. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
214376. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
214377. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
214378. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
214379. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
214380. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
214381. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
214382. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
214383. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
214384. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
214385. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
214386. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
214387. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
214388. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
214389. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
214390. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
214391. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
214392. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
214393. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
214394. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
214395. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
214396. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
214397. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
214398. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
214399. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
214400. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
214401. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
214402. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
214403. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
214404. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
214405. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
214406. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
214407. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
214408. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
214409. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
214410. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
214411. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
214412. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
214413. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
214414. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
214415. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
214416. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
214417. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
214418. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
214419. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
214420. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
214421. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
214422. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
214423. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
214424. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
214425. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
214426. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
214427. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
214428. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
214429. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
214430. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
214431. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
214432. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
214433. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
214434. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
214435. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
214436. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
214437. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
214438. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
214439. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
214440. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
214441. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
214442. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
214443. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
214444. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
214445. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
214446. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
214447. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
214448. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
214449. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
214450. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
214451. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
214452. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
214453. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
214454. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
214455. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
214456. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
214457. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
214458. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
214459. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
214460. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
214461. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
214462. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
214463. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
214464. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
214465. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
214466. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
214467. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
214468. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
214469. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
214470. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
214471. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
214472. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
214473. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
214474. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
214475. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
214476. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
214477. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
214478. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
214479. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
214480. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
214481. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
214482. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
214483. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
214484. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
214485. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
214486. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
214487. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
214488. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
214489. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
214490. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
214491. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
214492. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
214493. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
214494. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
214495. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
214496. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
214497. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
214498. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
214499. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
214500. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
214501. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
214502. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
214503. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
214504. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
214505. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
214506. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
214507. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
214508. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
214509. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
214510. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
214511. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
214512. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
214513. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
214514. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
214515. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
214516. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
214517. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
214518. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
214519. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
214520. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
214521. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
214522. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
214523. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
214524. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
214525. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
214526. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
214527. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
214528. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
214529. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
214530. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
214531. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
214532. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
214533. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
214534. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
214535. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
214536. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
214537. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
214538. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
214539. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
214540. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
214541. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
214542. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
214543. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
214544. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
214545. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
214546. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
214547. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
214548. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
214549. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
214550. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
214551. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
214552. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
214553. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
214554. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
214555. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
214556. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
214557. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
214558. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
214559. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
214560. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
214561. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
214562. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
214563. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
214564. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
214565. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
214566. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
214567. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
214568. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
214569. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
214570. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
214571. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
214572. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
214573. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
214574. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
214575. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
214576. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
214577. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
214578. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
214579. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
214580. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
214581. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
214582. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
214583. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
214584. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
214585. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
214586. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
214587. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
214588. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
214589. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
214590. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
214591. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
214592. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
214593. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
214594. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
214595. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
214596. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
214597. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
214598. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
214599. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
214600. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
214601. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
214602. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
214603. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
214604. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
214605. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
214606. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
214607. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
214608. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
214609. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
214610. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
214611. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
214612. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
214613. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
214614. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
214615. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
214616. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
214617. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
214618. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
214619. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
214620. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
214621. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
214622. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
214623. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
214624. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
214625. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
214626. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
214627. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
214628. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
214629. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
214630. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
214631. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
214632. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
214633. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
214634. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
214635. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
214636. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
214637. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
214638. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
214639. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
214640. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
214641. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
214642. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
214643. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
214644. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
214645. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
214646. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
214647. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
214648. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
214649. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
214650. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
214651. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
214652. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
214653. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
214654. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
214655. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
214656. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
214657. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
214658. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
214659. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
214660. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
214661. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
214662. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
214663. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
214664. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
214665. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
214666. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
214667. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
214668. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
214669. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
214670. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
214671. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
214672. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
214673. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
214674. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
214675. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
214676. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
214677. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
214678. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
214679. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
214680. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
214681. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
214682. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
214683. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
214684. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK
214685. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT
214686. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK
214687. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT
214688. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
214689. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
214690. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
214691. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
214692. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
214693. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
214694. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
214695. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
214696. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
214697. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
214698. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
214699. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
214700. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
214701. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
214702. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
214703. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
214704. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
214705. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
214706. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
214707. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
214708. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
214709. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
214710. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
214711. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
214712. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
214713. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
214714. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
214715. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
214716. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
214717. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
214718. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
214719. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
214720. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
214721. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
214722. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
214723. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
214724. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
214725. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
214726. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
214727. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
214728. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
214729. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
214730. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
214731. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
214732. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
214733. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
214734. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
214735. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
214736. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
214737. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
214738. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
214739. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
214740. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
214741. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
214742. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
214743. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
214744. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
214745. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
214746. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
214747. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
214748. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
214749. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
214750. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
214751. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
214752. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
214753. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
214754. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
214755. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
214756. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
214757. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
214758. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
214759. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
214760. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
214761. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
214762. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
214763. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
214764. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
214765. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
214766. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
214767. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
214768. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
214769. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
214770. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
214771. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
214772. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
214773. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
214774. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
214775. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
214776. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
214777. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
214778. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
214779. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
214780. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
214781. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
214782. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
214783. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
214784. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
214785. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
214786. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
214787. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
214788. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
214789. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
214790. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
214791. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
214792. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
214793. DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
214794. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
214795. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
214796. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
214797. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
214798. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
214799. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
214800. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
214801. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
214802. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
214803. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
214804. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK
214805. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT
214806. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
214807. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
214808. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
214809. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
214810. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
214811. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
214812. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
214813. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
214814. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
214815. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
214816. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
214817. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
214818. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
214819. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
214820. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
214821. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
214822. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
214823. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
214824. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
214825. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
214826. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
214827. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
214828. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
214829. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
214830. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
214831. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
214832. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
214833. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
214834. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
214835. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
214836. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK
214837. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
214838. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK
214839. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
214840. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK
214841. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
214842. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
214843. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
214844. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
214845. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
214846. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
214847. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
214848. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
214849. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
214850. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
214851. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
214852. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
214853. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
214854. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
214855. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
214856. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
214857. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
214858. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
214859. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
214860. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
214861. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
214862. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
214863. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
214864. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
214865. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
214866. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
214867. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
214868. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
214869. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
214870. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
214871. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
214872. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
214873. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
214874. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
214875. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
214876. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
214877. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
214878. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
214879. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
214880. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
214881. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
214882. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK
214883. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
214884. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK
214885. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
214886. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
214887. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
214888. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
214889. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
214890. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
214891. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
214892. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
214893. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
214894. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK
214895. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
214896. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
214897. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
214898. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
214899. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
214900. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
214901. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
214902. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
214903. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
214904. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
214905. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
214906. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__NC32_MASK
214907. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT
214908. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
214909. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
214910. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
214911. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
214912. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
214913. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
214914. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
214915. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
214916. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
214917. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
214918. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK
214919. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
214920. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
214921. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
214922. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
214923. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
214924. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
214925. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
214926. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
214927. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
214928. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
214929. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
214930. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK
214931. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
214932. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
214933. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
214934. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
214935. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
214936. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
214937. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
214938. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
214939. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
214940. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK
214941. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT
214942. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
214943. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
214944. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
214945. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
214946. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
214947. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
214948. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
214949. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
214950. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
214951. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
214952. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
214953. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
214954. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
214955. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
214956. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
214957. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
214958. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
214959. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
214960. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
214961. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
214962. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__NC20_MASK
214963. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__NC20__SHIFT
214964. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK
214965. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT
214966. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
214967. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
214968. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
214969. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
214970. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
214971. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
214972. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK
214973. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
214974. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK
214975. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
214976. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
214977. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
214978. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK
214979. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
214980. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK
214981. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
214982. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK
214983. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT
214984. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
214985. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
214986. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK
214987. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT
214988. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK
214989. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT
214990. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
214991. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
214992. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK
214993. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT
214994. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_gd_MASK
214995. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_gd__SHIFT
214996. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccm_MASK
214997. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT
214998. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccp_MASK
214999. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT
215000. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vptx_MASK
215001. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT
215002. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg0_MASK
215003. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT
215004. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg1_MASK
215005. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT
215006. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK
215007. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT
215008. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__override_regref_0_MASK
215009. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT
215010. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK
215011. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT
215012. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_nbias_MASK
215013. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT
215014. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_pbias_MASK
215015. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT
215016. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK
215017. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT
215018. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfm_MASK
215019. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT
215020. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfp_MASK
215021. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT
215022. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsm_MASK
215023. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT
215024. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsp_MASK
215025. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT
215026. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_vcm_MASK
215027. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT
215028. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
215029. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
215030. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK
215031. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
215032. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
215033. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
215034. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
215035. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
215036. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
215037. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
215038. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
215039. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
215040. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK
215041. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT
215042. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK
215043. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
215044. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__nc_MASK
215045. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__nc__SHIFT
215046. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_nmos_MASK
215047. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_nmos__SHIFT
215048. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_pmos_MASK
215049. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_pmos__SHIFT
215050. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__override_rxdetref_MASK
215051. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT
215052. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
215053. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
215054. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
215055. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
215056. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
215057. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
215058. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
215059. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
215060. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK
215061. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
215062. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
215063. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
215064. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
215065. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
215066. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
215067. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
215068. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
215069. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
215070. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
215071. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
215072. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
215073. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
215074. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
215075. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
215076. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
215077. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
215078. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
215079. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
215080. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
215081. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
215082. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
215083. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
215084. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
215085. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
215086. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
215087. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
215088. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
215089. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
215090. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
215091. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
215092. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK
215093. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
215094. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK
215095. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
215096. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
215097. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
215098. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK
215099. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
215100. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
215101. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
215102. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
215103. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
215104. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK
215105. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
215106. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
215107. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
215108. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
215109. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
215110. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
215111. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
215112. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
215113. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
215114. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
215115. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
215116. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
215117. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
215118. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK
215119. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
215120. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK
215121. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT
215122. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_MASK
215123. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT
215124. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK
215125. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
215126. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
215127. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
215128. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK
215129. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
215130. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK
215131. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
215132. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK
215133. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
215134. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK
215135. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT
215136. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
215137. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
215138. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
215139. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
215140. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
215141. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
215142. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
215143. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
215144. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
215145. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
215146. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
215147. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
215148. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
215149. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
215150. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
215151. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
215152. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
215153. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
215154. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
215155. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
215156. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
215157. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
215158. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
215159. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
215160. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
215161. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
215162. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
215163. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
215164. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
215165. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
215166. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
215167. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
215168. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
215169. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
215170. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
215171. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
215172. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
215173. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
215174. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
215175. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
215176. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
215177. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
215178. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
215179. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
215180. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
215181. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
215182. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
215183. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
215184. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
215185. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
215186. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
215187. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
215188. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
215189. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
215190. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
215191. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
215192. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
215193. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
215194. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
215195. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
215196. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
215197. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
215198. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
215199. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
215200. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
215201. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
215202. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
215203. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
215204. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
215205. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
215206. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
215207. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
215208. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
215209. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
215210. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
215211. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
215212. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
215213. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
215214. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
215215. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
215216. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
215217. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
215218. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
215219. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
215220. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
215221. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
215222. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
215223. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
215224. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
215225. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
215226. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
215227. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
215228. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
215229. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
215230. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
215231. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
215232. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
215233. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
215234. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
215235. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
215236. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
215237. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
215238. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
215239. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
215240. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
215241. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
215242. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
215243. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
215244. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
215245. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
215246. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
215247. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
215248. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
215249. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
215250. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
215251. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
215252. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
215253. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
215254. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
215255. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
215256. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
215257. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
215258. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
215259. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
215260. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
215261. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
215262. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
215263. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
215264. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
215265. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
215266. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
215267. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
215268. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
215269. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
215270. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
215271. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
215272. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
215273. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
215274. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
215275. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
215276. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
215277. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
215278. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
215279. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
215280. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
215281. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
215282. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
215283. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
215284. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
215285. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
215286. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
215287. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
215288. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
215289. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
215290. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
215291. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
215292. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
215293. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
215294. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
215295. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
215296. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
215297. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
215298. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
215299. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
215300. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
215301. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
215302. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
215303. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
215304. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
215305. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
215306. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
215307. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
215308. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
215309. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
215310. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
215311. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
215312. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
215313. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
215314. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
215315. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
215316. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
215317. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
215318. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
215319. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
215320. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
215321. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
215322. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
215323. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
215324. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
215325. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
215326. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
215327. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
215328. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
215329. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
215330. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
215331. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
215332. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
215333. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
215334. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
215335. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
215336. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
215337. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
215338. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
215339. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
215340. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
215341. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
215342. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
215343. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
215344. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
215345. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
215346. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
215347. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
215348. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
215349. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
215350. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
215351. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
215352. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
215353. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
215354. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
215355. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
215356. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
215357. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
215358. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
215359. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
215360. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
215361. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
215362. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
215363. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
215364. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
215365. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
215366. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
215367. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
215368. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
215369. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
215370. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
215371. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
215372. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
215373. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
215374. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
215375. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
215376. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
215377. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
215378. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
215379. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
215380. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK
215381. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
215382. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
215383. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
215384. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
215385. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
215386. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
215387. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
215388. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
215389. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
215390. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
215391. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
215392. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
215393. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
215394. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
215395. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
215396. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
215397. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
215398. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
215399. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
215400. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
215401. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
215402. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
215403. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
215404. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
215405. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
215406. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
215407. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
215408. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
215409. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
215410. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
215411. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
215412. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
215413. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
215414. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
215415. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
215416. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
215417. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
215418. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
215419. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
215420. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
215421. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
215422. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
215423. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
215424. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
215425. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
215426. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
215427. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
215428. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
215429. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
215430. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
215431. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
215432. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
215433. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
215434. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
215435. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
215436. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
215437. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
215438. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
215439. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
215440. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
215441. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
215442. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
215443. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
215444. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
215445. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
215446. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
215447. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
215448. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
215449. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
215450. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
215451. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
215452. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
215453. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
215454. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
215455. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
215456. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
215457. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
215458. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
215459. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
215460. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
215461. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
215462. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
215463. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
215464. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
215465. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
215466. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
215467. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
215468. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
215469. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
215470. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
215471. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
215472. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
215473. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
215474. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
215475. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
215476. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
215477. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
215478. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
215479. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
215480. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
215481. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
215482. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
215483. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
215484. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
215485. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
215486. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
215487. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
215488. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
215489. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
215490. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
215491. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
215492. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
215493. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
215494. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
215495. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
215496. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
215497. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
215498. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
215499. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
215500. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
215501. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
215502. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
215503. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
215504. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
215505. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
215506. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
215507. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
215508. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
215509. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
215510. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
215511. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
215512. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
215513. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
215514. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
215515. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
215516. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
215517. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
215518. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
215519. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
215520. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
215521. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
215522. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
215523. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
215524. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
215525. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
215526. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
215527. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
215528. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
215529. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
215530. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
215531. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
215532. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
215533. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
215534. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
215535. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
215536. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
215537. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
215538. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
215539. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
215540. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
215541. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
215542. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
215543. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
215544. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
215545. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
215546. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
215547. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
215548. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
215549. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
215550. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
215551. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
215552. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
215553. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
215554. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
215555. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
215556. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
215557. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
215558. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
215559. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
215560. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
215561. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
215562. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
215563. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
215564. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
215565. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
215566. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
215567. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
215568. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
215569. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
215570. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
215571. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
215572. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
215573. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
215574. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
215575. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
215576. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
215577. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
215578. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
215579. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
215580. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
215581. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
215582. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
215583. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
215584. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
215585. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
215586. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
215587. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
215588. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
215589. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
215590. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
215591. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
215592. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
215593. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
215594. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
215595. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
215596. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
215597. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
215598. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
215599. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
215600. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
215601. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
215602. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
215603. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
215604. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
215605. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
215606. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
215607. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
215608. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
215609. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
215610. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
215611. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
215612. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
215613. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
215614. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
215615. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
215616. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
215617. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
215618. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
215619. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
215620. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
215621. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
215622. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
215623. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
215624. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
215625. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
215626. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
215627. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
215628. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
215629. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
215630. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
215631. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
215632. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
215633. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
215634. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
215635. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
215636. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
215637. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
215638. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
215639. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
215640. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
215641. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
215642. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
215643. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
215644. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
215645. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
215646. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
215647. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
215648. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
215649. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
215650. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
215651. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
215652. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
215653. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
215654. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
215655. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
215656. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
215657. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
215658. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
215659. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
215660. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
215661. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
215662. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
215663. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
215664. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
215665. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
215666. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
215667. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
215668. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
215669. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
215670. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
215671. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
215672. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
215673. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
215674. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
215675. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
215676. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
215677. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
215678. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
215679. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
215680. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
215681. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
215682. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
215683. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
215684. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
215685. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
215686. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
215687. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
215688. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
215689. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
215690. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
215691. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
215692. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
215693. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
215694. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
215695. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
215696. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
215697. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
215698. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
215699. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
215700. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
215701. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
215702. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
215703. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
215704. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
215705. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
215706. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
215707. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
215708. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
215709. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
215710. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
215711. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
215712. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
215713. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
215714. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
215715. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
215716. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
215717. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
215718. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
215719. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
215720. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
215721. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
215722. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
215723. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
215724. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
215725. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
215726. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
215727. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
215728. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
215729. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
215730. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
215731. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
215732. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
215733. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
215734. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
215735. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
215736. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
215737. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
215738. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
215739. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
215740. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
215741. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
215742. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
215743. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
215744. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
215745. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
215746. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
215747. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
215748. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
215749. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
215750. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
215751. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
215752. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
215753. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
215754. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
215755. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
215756. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
215757. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
215758. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
215759. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
215760. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
215761. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
215762. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
215763. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
215764. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
215765. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
215766. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
215767. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
215768. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
215769. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
215770. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
215771. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
215772. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
215773. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
215774. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
215775. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
215776. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
215777. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
215778. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
215779. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
215780. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
215781. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
215782. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
215783. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
215784. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
215785. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
215786. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
215787. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
215788. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
215789. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
215790. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
215791. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
215792. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
215793. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
215794. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
215795. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
215796. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
215797. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
215798. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
215799. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
215800. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
215801. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
215802. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
215803. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
215804. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
215805. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
215806. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
215807. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
215808. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
215809. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
215810. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
215811. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
215812. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
215813. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
215814. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
215815. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
215816. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
215817. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
215818. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
215819. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
215820. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
215821. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
215822. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
215823. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
215824. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
215825. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
215826. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
215827. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
215828. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
215829. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
215830. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
215831. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
215832. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
215833. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
215834. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
215835. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
215836. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
215837. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
215838. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
215839. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
215840. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
215841. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
215842. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
215843. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
215844. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
215845. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
215846. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
215847. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
215848. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
215849. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
215850. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
215851. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
215852. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
215853. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
215854. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
215855. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
215856. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
215857. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
215858. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
215859. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
215860. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
215861. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
215862. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
215863. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
215864. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
215865. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
215866. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
215867. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
215868. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
215869. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
215870. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
215871. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
215872. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
215873. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
215874. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
215875. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
215876. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
215877. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
215878. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
215879. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
215880. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
215881. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
215882. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
215883. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
215884. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
215885. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
215886. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
215887. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
215888. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
215889. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
215890. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
215891. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
215892. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
215893. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
215894. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
215895. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
215896. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
215897. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
215898. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
215899. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
215900. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
215901. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
215902. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
215903. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
215904. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
215905. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
215906. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
215907. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
215908. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
215909. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
215910. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
215911. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
215912. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
215913. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
215914. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
215915. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
215916. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
215917. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
215918. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
215919. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
215920. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
215921. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
215922. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
215923. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
215924. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
215925. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
215926. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
215927. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
215928. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
215929. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
215930. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
215931. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
215932. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
215933. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
215934. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
215935. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
215936. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK
215937. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT
215938. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK
215939. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT
215940. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
215941. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
215942. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK
215943. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT
215944. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK
215945. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT
215946. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK
215947. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT
215948. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
215949. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
215950. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
215951. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
215952. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
215953. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
215954. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
215955. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
215956. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
215957. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
215958. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
215959. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
215960. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
215961. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
215962. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
215963. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
215964. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
215965. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
215966. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
215967. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
215968. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
215969. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
215970. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
215971. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
215972. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
215973. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
215974. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
215975. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
215976. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
215977. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
215978. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
215979. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
215980. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
215981. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
215982. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
215983. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
215984. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
215985. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
215986. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
215987. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
215988. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
215989. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
215990. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
215991. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
215992. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
215993. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
215994. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
215995. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
215996. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
215997. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
215998. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
215999. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
216000. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
216001. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
216002. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
216003. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
216004. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
216005. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
216006. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
216007. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
216008. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
216009. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
216010. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
216011. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
216012. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
216013. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
216014. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
216015. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
216016. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
216017. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
216018. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
216019. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
216020. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
216021. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
216022. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
216023. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
216024. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
216025. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
216026. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
216027. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
216028. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
216029. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
216030. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
216031. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
216032. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
216033. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
216034. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
216035. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
216036. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
216037. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
216038. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
216039. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
216040. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
216041. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
216042. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
216043. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
216044. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
216045. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
216046. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
216047. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
216048. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
216049. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
216050. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
216051. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
216052. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
216053. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
216054. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
216055. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
216056. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
216057. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
216058. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
216059. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
216060. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
216061. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
216062. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
216063. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
216064. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
216065. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
216066. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
216067. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
216068. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
216069. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
216070. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
216071. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
216072. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
216073. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
216074. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
216075. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
216076. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
216077. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
216078. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
216079. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
216080. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
216081. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
216082. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
216083. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
216084. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
216085. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
216086. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
216087. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
216088. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
216089. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
216090. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
216091. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
216092. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
216093. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
216094. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
216095. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
216096. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
216097. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
216098. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
216099. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
216100. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
216101. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
216102. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
216103. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
216104. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
216105. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
216106. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
216107. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
216108. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
216109. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
216110. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
216111. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
216112. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
216113. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
216114. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
216115. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
216116. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
216117. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
216118. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
216119. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
216120. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
216121. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
216122. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
216123. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
216124. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
216125. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
216126. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
216127. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
216128. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
216129. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
216130. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
216131. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
216132. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
216133. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
216134. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
216135. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
216136. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
216137. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
216138. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
216139. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
216140. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
216141. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
216142. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
216143. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
216144. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
216145. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
216146. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
216147. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
216148. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
216149. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
216150. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
216151. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
216152. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
216153. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
216154. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
216155. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
216156. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
216157. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
216158. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
216159. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
216160. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
216161. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
216162. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
216163. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
216164. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
216165. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
216166. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
216167. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
216168. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
216169. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
216170. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
216171. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
216172. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
216173. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
216174. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
216175. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
216176. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
216177. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
216178. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
216179. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
216180. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
216181. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
216182. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
216183. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
216184. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
216185. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
216186. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
216187. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
216188. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
216189. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
216190. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
216191. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
216192. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
216193. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
216194. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
216195. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
216196. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
216197. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
216198. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
216199. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
216200. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
216201. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
216202. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
216203. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
216204. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
216205. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
216206. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
216207. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
216208. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
216209. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
216210. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
216211. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
216212. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
216213. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
216214. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
216215. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
216216. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
216217. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
216218. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
216219. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
216220. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
216221. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
216222. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
216223. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
216224. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
216225. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
216226. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
216227. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
216228. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
216229. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
216230. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
216231. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
216232. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
216233. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
216234. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
216235. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
216236. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
216237. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
216238. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
216239. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
216240. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
216241. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
216242. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
216243. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
216244. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
216245. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
216246. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
216247. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
216248. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
216249. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
216250. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
216251. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
216252. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
216253. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
216254. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
216255. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
216256. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
216257. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
216258. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
216259. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
216260. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
216261. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
216262. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
216263. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
216264. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
216265. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
216266. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
216267. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
216268. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
216269. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
216270. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
216271. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
216272. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
216273. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
216274. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
216275. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
216276. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
216277. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
216278. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
216279. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
216280. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
216281. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
216282. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
216283. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
216284. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
216285. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
216286. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
216287. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
216288. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
216289. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
216290. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK
216291. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT
216292. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK
216293. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT
216294. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
216295. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
216296. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
216297. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
216298. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
216299. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
216300. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
216301. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
216302. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
216303. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
216304. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
216305. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
216306. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
216307. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
216308. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
216309. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
216310. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
216311. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
216312. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
216313. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
216314. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
216315. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
216316. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
216317. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
216318. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
216319. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
216320. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
216321. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
216322. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
216323. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
216324. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
216325. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
216326. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
216327. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
216328. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
216329. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
216330. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
216331. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
216332. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
216333. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
216334. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
216335. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
216336. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
216337. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
216338. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
216339. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
216340. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
216341. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
216342. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
216343. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
216344. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
216345. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
216346. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
216347. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
216348. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
216349. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
216350. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
216351. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
216352. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
216353. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
216354. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
216355. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
216356. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
216357. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
216358. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
216359. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
216360. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
216361. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
216362. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
216363. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
216364. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
216365. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
216366. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
216367. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
216368. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
216369. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
216370. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
216371. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
216372. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
216373. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
216374. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
216375. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
216376. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
216377. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
216378. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
216379. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
216380. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
216381. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
216382. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
216383. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
216384. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
216385. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
216386. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
216387. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
216388. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
216389. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
216390. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
216391. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
216392. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
216393. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
216394. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
216395. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
216396. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
216397. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
216398. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
216399. DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
216400. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
216401. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
216402. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
216403. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
216404. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
216405. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
216406. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
216407. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
216408. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
216409. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
216410. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK
216411. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT
216412. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
216413. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
216414. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
216415. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
216416. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
216417. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
216418. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
216419. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
216420. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
216421. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
216422. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
216423. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
216424. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
216425. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
216426. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
216427. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
216428. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
216429. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
216430. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
216431. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
216432. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
216433. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
216434. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
216435. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
216436. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
216437. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
216438. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
216439. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
216440. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
216441. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
216442. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK
216443. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
216444. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK
216445. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
216446. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK
216447. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
216448. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
216449. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
216450. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
216451. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
216452. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
216453. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
216454. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
216455. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
216456. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
216457. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
216458. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
216459. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
216460. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
216461. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
216462. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
216463. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
216464. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
216465. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
216466. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
216467. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
216468. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
216469. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
216470. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
216471. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
216472. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
216473. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
216474. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
216475. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
216476. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
216477. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
216478. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
216479. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
216480. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
216481. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
216482. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
216483. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
216484. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
216485. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
216486. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
216487. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
216488. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK
216489. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
216490. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK
216491. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
216492. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
216493. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
216494. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
216495. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
216496. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
216497. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
216498. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
216499. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
216500. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK
216501. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
216502. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
216503. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
216504. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
216505. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
216506. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
216507. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
216508. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
216509. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
216510. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
216511. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
216512. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__NC32_MASK
216513. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT
216514. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
216515. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
216516. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
216517. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
216518. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
216519. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
216520. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
216521. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
216522. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
216523. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
216524. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK
216525. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
216526. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
216527. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
216528. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
216529. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
216530. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
216531. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
216532. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
216533. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
216534. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
216535. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
216536. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK
216537. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
216538. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
216539. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
216540. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
216541. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
216542. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
216543. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
216544. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
216545. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
216546. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK
216547. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT
216548. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
216549. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
216550. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
216551. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
216552. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
216553. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
216554. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
216555. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
216556. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
216557. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
216558. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
216559. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
216560. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
216561. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
216562. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
216563. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
216564. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
216565. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
216566. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
216567. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
216568. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__NC20_MASK
216569. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__NC20__SHIFT
216570. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK
216571. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT
216572. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
216573. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
216574. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
216575. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
216576. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
216577. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
216578. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK
216579. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
216580. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK
216581. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
216582. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
216583. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
216584. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK
216585. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
216586. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK
216587. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
216588. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK
216589. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT
216590. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
216591. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
216592. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK
216593. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT
216594. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK
216595. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT
216596. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
216597. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
216598. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK
216599. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT
216600. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_gd_MASK
216601. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_gd__SHIFT
216602. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccm_MASK
216603. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT
216604. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccp_MASK
216605. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT
216606. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vptx_MASK
216607. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT
216608. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg0_MASK
216609. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT
216610. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg1_MASK
216611. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT
216612. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK
216613. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT
216614. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__override_regref_0_MASK
216615. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT
216616. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK
216617. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT
216618. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_nbias_MASK
216619. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT
216620. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_pbias_MASK
216621. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT
216622. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK
216623. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT
216624. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfm_MASK
216625. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT
216626. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfp_MASK
216627. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT
216628. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsm_MASK
216629. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT
216630. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsp_MASK
216631. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT
216632. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_vcm_MASK
216633. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT
216634. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
216635. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
216636. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK
216637. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
216638. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
216639. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
216640. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
216641. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
216642. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
216643. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
216644. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
216645. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
216646. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK
216647. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT
216648. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK
216649. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
216650. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__nc_MASK
216651. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__nc__SHIFT
216652. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_nmos_MASK
216653. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_nmos__SHIFT
216654. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_pmos_MASK
216655. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_pmos__SHIFT
216656. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__override_rxdetref_MASK
216657. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT
216658. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
216659. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
216660. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
216661. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
216662. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
216663. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
216664. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
216665. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
216666. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK
216667. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
216668. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
216669. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
216670. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
216671. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
216672. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
216673. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
216674. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
216675. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
216676. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
216677. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
216678. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
216679. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
216680. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
216681. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
216682. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
216683. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
216684. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
216685. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
216686. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
216687. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
216688. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
216689. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
216690. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
216691. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
216692. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
216693. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
216694. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
216695. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
216696. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
216697. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
216698. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK
216699. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
216700. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK
216701. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
216702. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
216703. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
216704. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK
216705. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
216706. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
216707. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
216708. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
216709. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
216710. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK
216711. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
216712. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
216713. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
216714. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
216715. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
216716. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
216717. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
216718. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
216719. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
216720. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
216721. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
216722. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
216723. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
216724. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK
216725. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
216726. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK
216727. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT
216728. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_MASK
216729. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT
216730. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK
216731. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
216732. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
216733. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
216734. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK
216735. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
216736. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK
216737. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
216738. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK
216739. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
216740. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK
216741. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT
216742. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
216743. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
216744. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
216745. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
216746. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
216747. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
216748. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
216749. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
216750. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
216751. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
216752. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
216753. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
216754. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
216755. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
216756. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
216757. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
216758. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
216759. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
216760. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
216761. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
216762. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
216763. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
216764. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
216765. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
216766. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
216767. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
216768. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
216769. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
216770. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
216771. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
216772. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
216773. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
216774. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
216775. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
216776. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
216777. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
216778. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
216779. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
216780. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
216781. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
216782. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
216783. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
216784. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
216785. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
216786. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
216787. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
216788. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
216789. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
216790. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
216791. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
216792. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
216793. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
216794. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
216795. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
216796. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
216797. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
216798. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
216799. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
216800. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
216801. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
216802. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
216803. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
216804. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
216805. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
216806. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
216807. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
216808. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
216809. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
216810. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
216811. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
216812. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
216813. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
216814. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
216815. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
216816. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
216817. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
216818. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
216819. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
216820. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
216821. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
216822. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
216823. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
216824. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
216825. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
216826. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
216827. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
216828. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
216829. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
216830. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
216831. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
216832. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
216833. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
216834. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
216835. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
216836. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
216837. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
216838. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
216839. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
216840. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
216841. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
216842. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
216843. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
216844. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
216845. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
216846. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
216847. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
216848. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
216849. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
216850. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
216851. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
216852. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
216853. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
216854. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
216855. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
216856. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
216857. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
216858. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
216859. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
216860. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
216861. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
216862. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
216863. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
216864. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
216865. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
216866. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
216867. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
216868. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
216869. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
216870. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
216871. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
216872. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
216873. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
216874. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
216875. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
216876. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
216877. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
216878. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
216879. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
216880. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
216881. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
216882. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
216883. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
216884. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
216885. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
216886. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
216887. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
216888. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
216889. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
216890. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
216891. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
216892. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
216893. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
216894. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
216895. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
216896. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
216897. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
216898. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
216899. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
216900. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
216901. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
216902. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
216903. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
216904. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
216905. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
216906. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
216907. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
216908. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
216909. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
216910. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
216911. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
216912. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
216913. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
216914. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
216915. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
216916. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
216917. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
216918. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
216919. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
216920. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
216921. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
216922. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
216923. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
216924. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
216925. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
216926. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
216927. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
216928. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
216929. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
216930. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
216931. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
216932. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
216933. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
216934. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
216935. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
216936. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
216937. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
216938. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
216939. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
216940. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
216941. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
216942. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
216943. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
216944. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
216945. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
216946. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
216947. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
216948. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
216949. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
216950. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
216951. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
216952. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
216953. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
216954. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
216955. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
216956. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
216957. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
216958. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
216959. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
216960. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
216961. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
216962. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
216963. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
216964. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
216965. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
216966. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
216967. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
216968. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
216969. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
216970. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
216971. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
216972. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
216973. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
216974. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
216975. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
216976. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
216977. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
216978. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
216979. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
216980. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
216981. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
216982. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
216983. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
216984. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
216985. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
216986. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK
216987. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
216988. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
216989. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
216990. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
216991. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
216992. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
216993. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
216994. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
216995. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
216996. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
216997. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
216998. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
216999. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
217000. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
217001. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
217002. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
217003. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
217004. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
217005. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
217006. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
217007. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
217008. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
217009. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
217010. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
217011. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
217012. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
217013. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
217014. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
217015. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
217016. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
217017. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
217018. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
217019. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
217020. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
217021. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
217022. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
217023. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
217024. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
217025. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
217026. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
217027. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
217028. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
217029. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
217030. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
217031. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
217032. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
217033. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
217034. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
217035. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
217036. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
217037. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
217038. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
217039. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
217040. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
217041. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
217042. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
217043. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
217044. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
217045. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
217046. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
217047. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
217048. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
217049. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
217050. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
217051. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
217052. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
217053. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
217054. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
217055. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
217056. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
217057. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
217058. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
217059. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
217060. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
217061. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
217062. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
217063. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
217064. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
217065. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
217066. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
217067. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
217068. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
217069. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
217070. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
217071. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
217072. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
217073. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
217074. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
217075. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
217076. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
217077. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
217078. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
217079. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
217080. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
217081. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
217082. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
217083. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
217084. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
217085. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
217086. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
217087. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
217088. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
217089. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
217090. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
217091. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
217092. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
217093. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
217094. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
217095. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
217096. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
217097. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
217098. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
217099. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
217100. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
217101. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
217102. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
217103. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
217104. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
217105. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
217106. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
217107. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
217108. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
217109. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
217110. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
217111. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
217112. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
217113. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
217114. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
217115. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
217116. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
217117. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
217118. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
217119. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
217120. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
217121. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
217122. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
217123. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
217124. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
217125. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
217126. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
217127. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
217128. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
217129. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
217130. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
217131. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
217132. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
217133. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
217134. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
217135. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
217136. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
217137. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
217138. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
217139. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
217140. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
217141. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
217142. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
217143. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
217144. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
217145. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
217146. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
217147. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
217148. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
217149. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
217150. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
217151. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
217152. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
217153. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
217154. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
217155. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
217156. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
217157. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
217158. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
217159. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
217160. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
217161. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
217162. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
217163. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
217164. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
217165. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
217166. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
217167. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
217168. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
217169. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
217170. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
217171. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
217172. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
217173. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
217174. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
217175. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
217176. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
217177. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
217178. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
217179. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
217180. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
217181. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
217182. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
217183. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
217184. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
217185. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
217186. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
217187. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
217188. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
217189. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
217190. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
217191. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
217192. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
217193. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
217194. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
217195. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
217196. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
217197. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
217198. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
217199. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
217200. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
217201. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
217202. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
217203. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
217204. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
217205. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
217206. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
217207. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
217208. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
217209. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
217210. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
217211. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
217212. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
217213. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
217214. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
217215. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
217216. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
217217. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
217218. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
217219. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
217220. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
217221. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
217222. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
217223. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
217224. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
217225. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
217226. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
217227. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
217228. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
217229. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
217230. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
217231. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
217232. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
217233. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
217234. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
217235. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
217236. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
217237. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
217238. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
217239. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
217240. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
217241. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
217242. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
217243. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
217244. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
217245. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
217246. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
217247. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
217248. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
217249. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
217250. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
217251. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
217252. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
217253. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
217254. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
217255. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
217256. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
217257. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
217258. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
217259. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
217260. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
217261. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
217262. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
217263. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
217264. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
217265. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
217266. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
217267. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
217268. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
217269. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
217270. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
217271. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
217272. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
217273. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
217274. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
217275. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
217276. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
217277. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
217278. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
217279. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
217280. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
217281. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
217282. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
217283. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
217284. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
217285. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
217286. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
217287. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
217288. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
217289. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
217290. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
217291. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
217292. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
217293. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
217294. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
217295. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
217296. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
217297. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
217298. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
217299. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
217300. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
217301. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
217302. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
217303. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
217304. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
217305. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
217306. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
217307. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
217308. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
217309. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
217310. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
217311. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
217312. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
217313. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
217314. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
217315. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
217316. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
217317. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
217318. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
217319. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
217320. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
217321. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
217322. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
217323. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
217324. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
217325. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
217326. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
217327. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
217328. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
217329. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
217330. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
217331. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
217332. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
217333. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
217334. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
217335. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
217336. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
217337. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
217338. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
217339. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
217340. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
217341. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
217342. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
217343. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
217344. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
217345. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
217346. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
217347. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
217348. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
217349. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
217350. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
217351. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
217352. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
217353. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
217354. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
217355. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
217356. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
217357. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
217358. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
217359. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
217360. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
217361. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
217362. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
217363. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
217364. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
217365. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
217366. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
217367. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
217368. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
217369. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
217370. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
217371. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
217372. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
217373. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
217374. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
217375. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
217376. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
217377. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
217378. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
217379. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
217380. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
217381. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
217382. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
217383. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
217384. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
217385. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
217386. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
217387. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
217388. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
217389. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
217390. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
217391. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
217392. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
217393. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
217394. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
217395. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
217396. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
217397. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
217398. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
217399. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
217400. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
217401. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
217402. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
217403. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
217404. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
217405. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
217406. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
217407. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
217408. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
217409. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
217410. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
217411. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
217412. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
217413. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
217414. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
217415. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
217416. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
217417. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
217418. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
217419. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
217420. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
217421. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
217422. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
217423. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
217424. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
217425. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
217426. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
217427. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
217428. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
217429. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
217430. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
217431. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
217432. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
217433. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
217434. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
217435. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
217436. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
217437. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
217438. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
217439. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
217440. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
217441. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
217442. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
217443. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
217444. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
217445. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
217446. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
217447. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
217448. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
217449. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
217450. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
217451. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
217452. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
217453. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
217454. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
217455. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
217456. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
217457. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
217458. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
217459. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
217460. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
217461. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
217462. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
217463. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
217464. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
217465. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
217466. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
217467. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
217468. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
217469. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
217470. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
217471. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
217472. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
217473. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
217474. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
217475. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
217476. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
217477. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
217478. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
217479. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
217480. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
217481. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
217482. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
217483. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
217484. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
217485. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
217486. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
217487. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
217488. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
217489. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
217490. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
217491. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
217492. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
217493. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
217494. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
217495. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
217496. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
217497. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
217498. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
217499. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
217500. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
217501. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
217502. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
217503. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
217504. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
217505. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
217506. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
217507. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
217508. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
217509. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
217510. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
217511. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
217512. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
217513. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
217514. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
217515. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
217516. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
217517. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
217518. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
217519. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
217520. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
217521. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
217522. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
217523. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
217524. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
217525. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
217526. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
217527. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
217528. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
217529. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
217530. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
217531. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
217532. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
217533. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
217534. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
217535. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
217536. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
217537. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
217538. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
217539. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
217540. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
217541. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
217542. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK
217543. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT
217544. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__MODE_MASK
217545. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT
217546. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
217547. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
217548. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK
217549. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT
217550. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK
217551. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT
217552. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__OV14_MASK
217553. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT
217554. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
217555. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
217556. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
217557. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
217558. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
217559. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
217560. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
217561. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
217562. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
217563. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
217564. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
217565. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
217566. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
217567. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
217568. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
217569. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
217570. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
217571. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
217572. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
217573. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
217574. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
217575. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
217576. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
217577. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
217578. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
217579. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
217580. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
217581. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
217582. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
217583. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
217584. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
217585. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
217586. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
217587. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
217588. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
217589. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
217590. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
217591. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
217592. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
217593. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
217594. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
217595. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
217596. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
217597. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
217598. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
217599. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
217600. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
217601. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
217602. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
217603. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
217604. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
217605. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
217606. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
217607. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
217608. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
217609. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
217610. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
217611. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
217612. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
217613. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
217614. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
217615. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
217616. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
217617. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
217618. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
217619. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
217620. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
217621. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
217622. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
217623. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
217624. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
217625. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
217626. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
217627. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
217628. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
217629. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
217630. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
217631. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
217632. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
217633. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
217634. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
217635. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
217636. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
217637. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
217638. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
217639. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
217640. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
217641. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
217642. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
217643. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
217644. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
217645. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
217646. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
217647. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
217648. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
217649. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
217650. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
217651. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
217652. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
217653. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
217654. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
217655. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
217656. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
217657. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
217658. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
217659. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
217660. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
217661. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
217662. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
217663. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
217664. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
217665. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
217666. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
217667. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
217668. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
217669. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
217670. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
217671. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
217672. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
217673. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
217674. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
217675. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
217676. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
217677. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
217678. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
217679. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
217680. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
217681. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
217682. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
217683. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
217684. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
217685. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
217686. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
217687. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
217688. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
217689. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
217690. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
217691. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
217692. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
217693. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
217694. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
217695. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
217696. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
217697. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
217698. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
217699. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
217700. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
217701. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
217702. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
217703. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
217704. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
217705. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
217706. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
217707. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
217708. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
217709. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
217710. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
217711. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
217712. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
217713. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
217714. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
217715. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
217716. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
217717. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
217718. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
217719. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
217720. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
217721. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
217722. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
217723. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
217724. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
217725. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
217726. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
217727. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
217728. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
217729. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
217730. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
217731. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
217732. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
217733. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
217734. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
217735. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
217736. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
217737. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
217738. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
217739. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
217740. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
217741. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
217742. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
217743. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
217744. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
217745. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
217746. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
217747. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
217748. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
217749. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
217750. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
217751. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
217752. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
217753. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
217754. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
217755. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
217756. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
217757. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
217758. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
217759. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
217760. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
217761. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
217762. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
217763. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
217764. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
217765. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
217766. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
217767. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
217768. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
217769. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
217770. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
217771. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
217772. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
217773. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
217774. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
217775. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
217776. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
217777. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
217778. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
217779. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
217780. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
217781. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
217782. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
217783. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
217784. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
217785. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
217786. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
217787. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
217788. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
217789. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
217790. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
217791. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
217792. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
217793. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
217794. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
217795. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
217796. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
217797. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
217798. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
217799. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
217800. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
217801. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
217802. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
217803. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
217804. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
217805. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
217806. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
217807. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
217808. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
217809. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
217810. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
217811. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
217812. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
217813. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
217814. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
217815. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
217816. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
217817. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
217818. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
217819. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
217820. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
217821. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
217822. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
217823. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
217824. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
217825. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
217826. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
217827. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
217828. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
217829. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
217830. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
217831. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
217832. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
217833. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
217834. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
217835. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
217836. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
217837. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
217838. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
217839. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
217840. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
217841. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
217842. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
217843. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
217844. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
217845. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
217846. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
217847. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
217848. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
217849. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
217850. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
217851. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
217852. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
217853. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
217854. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
217855. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
217856. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
217857. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
217858. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
217859. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
217860. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
217861. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
217862. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
217863. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
217864. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
217865. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
217866. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
217867. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
217868. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
217869. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
217870. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
217871. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
217872. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
217873. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
217874. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
217875. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
217876. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
217877. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
217878. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
217879. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
217880. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
217881. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
217882. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
217883. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
217884. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
217885. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
217886. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
217887. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
217888. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
217889. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
217890. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
217891. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
217892. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
217893. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
217894. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
217895. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
217896. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK
217897. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT
217898. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK
217899. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT
217900. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
217901. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
217902. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
217903. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
217904. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
217905. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
217906. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
217907. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
217908. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
217909. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
217910. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
217911. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
217912. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
217913. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
217914. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
217915. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
217916. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
217917. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
217918. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
217919. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
217920. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
217921. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
217922. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
217923. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
217924. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
217925. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
217926. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
217927. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
217928. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
217929. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
217930. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
217931. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
217932. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
217933. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
217934. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
217935. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
217936. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
217937. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
217938. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
217939. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
217940. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
217941. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
217942. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
217943. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
217944. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
217945. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
217946. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
217947. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
217948. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
217949. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
217950. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
217951. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
217952. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
217953. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
217954. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
217955. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
217956. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
217957. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
217958. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
217959. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
217960. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
217961. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
217962. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
217963. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
217964. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
217965. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
217966. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
217967. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
217968. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
217969. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
217970. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
217971. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
217972. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
217973. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
217974. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
217975. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
217976. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
217977. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
217978. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
217979. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
217980. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
217981. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
217982. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
217983. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
217984. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
217985. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
217986. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
217987. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
217988. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
217989. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
217990. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
217991. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
217992. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
217993. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
217994. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
217995. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
217996. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
217997. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
217998. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
217999. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
218000. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
218001. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
218002. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
218003. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
218004. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
218005. DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
218006. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK
218007. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT
218008. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK
218009. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT
218010. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK
218011. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT
218012. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK
218013. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT
218014. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK
218015. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT
218016. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK
218017. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT
218018. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK
218019. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT
218020. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK
218021. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT
218022. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK
218023. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT
218024. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK
218025. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT
218026. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK
218027. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT
218028. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK
218029. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT
218030. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK
218031. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT
218032. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK
218033. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT
218034. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK
218035. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT
218036. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK
218037. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT
218038. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK
218039. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT
218040. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK
218041. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT
218042. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK
218043. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT
218044. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK
218045. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT
218046. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK
218047. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT
218048. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK
218049. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT
218050. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK
218051. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT
218052. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK
218053. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT
218054. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK
218055. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT
218056. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK
218057. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT
218058. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK
218059. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT
218060. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK
218061. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT
218062. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK
218063. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT
218064. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK
218065. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT
218066. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK
218067. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT
218068. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK
218069. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT
218070. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK
218071. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT
218072. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK
218073. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT
218074. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK
218075. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT
218076. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK
218077. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT
218078. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK
218079. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT
218080. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK
218081. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT
218082. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK
218083. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT
218084. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK
218085. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT
218086. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK
218087. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT
218088. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK
218089. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT
218090. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK
218091. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT
218092. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK
218093. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT
218094. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK
218095. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT
218096. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK
218097. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT
218098. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK
218099. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT
218100. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK
218101. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT
218102. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK
218103. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT
218104. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK
218105. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT
218106. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK
218107. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT
218108. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK
218109. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT
218110. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK
218111. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT
218112. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK
218113. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT
218114. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK
218115. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT
218116. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK
218117. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT
218118. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__NC32_MASK
218119. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT
218120. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK
218121. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT
218122. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK
218123. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT
218124. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK
218125. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT
218126. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK
218127. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT
218128. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK
218129. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT
218130. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK
218131. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT
218132. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK
218133. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT
218134. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK
218135. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT
218136. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK
218137. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT
218138. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK
218139. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT
218140. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK
218141. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT
218142. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK
218143. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT
218144. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK
218145. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT
218146. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK
218147. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT
218148. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK
218149. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT
218150. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK
218151. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT
218152. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK
218153. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT
218154. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK
218155. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT
218156. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK
218157. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT
218158. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK
218159. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT
218160. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK
218161. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT
218162. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK
218163. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT
218164. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK
218165. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT
218166. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK
218167. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT
218168. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK
218169. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT
218170. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK
218171. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT
218172. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK
218173. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT
218174. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__NC20_MASK
218175. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__NC20__SHIFT
218176. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK
218177. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT
218178. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK
218179. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT
218180. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK
218181. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT
218182. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK
218183. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT
218184. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK
218185. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT
218186. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK
218187. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT
218188. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK
218189. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT
218190. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK
218191. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT
218192. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK
218193. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT
218194. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK
218195. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT
218196. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK
218197. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT
218198. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK
218199. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT
218200. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK
218201. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT
218202. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK
218203. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT
218204. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK
218205. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT
218206. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_gd_MASK
218207. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_gd__SHIFT
218208. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccm_MASK
218209. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT
218210. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccp_MASK
218211. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT
218212. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vptx_MASK
218213. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT
218214. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg0_MASK
218215. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT
218216. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg1_MASK
218217. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT
218218. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK
218219. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT
218220. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__override_regref_0_MASK
218221. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT
218222. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK
218223. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT
218224. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_nbias_MASK
218225. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT
218226. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_pbias_MASK
218227. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT
218228. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK
218229. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT
218230. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfm_MASK
218231. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT
218232. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfp_MASK
218233. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT
218234. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsm_MASK
218235. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT
218236. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsp_MASK
218237. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT
218238. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_vcm_MASK
218239. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT
218240. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK
218241. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT
218242. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK
218243. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT
218244. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK
218245. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT
218246. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK
218247. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT
218248. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK
218249. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT
218250. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK
218251. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT
218252. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK
218253. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT
218254. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK
218255. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT
218256. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__nc_MASK
218257. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__nc__SHIFT
218258. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_nmos_MASK
218259. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_nmos__SHIFT
218260. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_pmos_MASK
218261. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_pmos__SHIFT
218262. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__override_rxdetref_MASK
218263. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT
218264. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK
218265. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT
218266. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK
218267. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT
218268. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK
218269. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT
218270. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK
218271. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT
218272. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK
218273. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT
218274. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK
218275. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT
218276. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK
218277. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT
218278. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK
218279. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT
218280. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK
218281. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT
218282. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK
218283. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT
218284. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK
218285. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT
218286. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK
218287. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT
218288. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK
218289. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT
218290. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK
218291. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT
218292. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK
218293. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT
218294. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK
218295. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT
218296. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK
218297. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT
218298. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK
218299. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT
218300. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK
218301. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT
218302. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK
218303. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT
218304. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK
218305. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT
218306. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK
218307. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT
218308. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK
218309. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT
218310. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK
218311. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT
218312. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK
218313. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT
218314. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK
218315. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT
218316. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK
218317. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT
218318. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK
218319. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT
218320. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK
218321. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT
218322. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK
218323. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT
218324. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK
218325. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT
218326. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK
218327. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT
218328. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK
218329. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT
218330. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK
218331. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT
218332. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK
218333. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT
218334. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_MASK
218335. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT
218336. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK
218337. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT
218338. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK
218339. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT
218340. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK
218341. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT
218342. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK
218343. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT
218344. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK
218345. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT
218346. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK
218347. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT
218348. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK
218349. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT
218350. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK
218351. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT
218352. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK
218353. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT
218354. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK
218355. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT
218356. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK
218357. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT
218358. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK
218359. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT
218360. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK
218361. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT
218362. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK
218363. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT
218364. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK
218365. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT
218366. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK
218367. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT
218368. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK
218369. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT
218370. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
218371. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
218372. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK
218373. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT
218374. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK
218375. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT
218376. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK
218377. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT
218378. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK
218379. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT
218380. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK
218381. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT
218382. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK
218383. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT
218384. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK
218385. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT
218386. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK
218387. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT
218388. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK
218389. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT
218390. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK
218391. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT
218392. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK
218393. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT
218394. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK
218395. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT
218396. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK
218397. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT
218398. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK
218399. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT
218400. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK
218401. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT
218402. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK
218403. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT
218404. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK
218405. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT
218406. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK
218407. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT
218408. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK
218409. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT
218410. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK
218411. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT
218412. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK
218413. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT
218414. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK
218415. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT
218416. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK
218417. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT
218418. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK
218419. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT
218420. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK
218421. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT
218422. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK
218423. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT
218424. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK
218425. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT
218426. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK
218427. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT
218428. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK
218429. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT
218430. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK
218431. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT
218432. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK
218433. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT
218434. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK
218435. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT
218436. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK
218437. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT
218438. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK
218439. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT
218440. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK
218441. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT
218442. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK
218443. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT
218444. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK
218445. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT
218446. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK
218447. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT
218448. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK
218449. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT
218450. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK
218451. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT
218452. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK
218453. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT
218454. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK
218455. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT
218456. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK
218457. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT
218458. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK
218459. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT
218460. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK
218461. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT
218462. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK
218463. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT
218464. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK
218465. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT
218466. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK
218467. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT
218468. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK
218469. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT
218470. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK
218471. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT
218472. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK
218473. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
218474. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK
218475. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT
218476. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK
218477. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT
218478. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK
218479. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT
218480. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK
218481. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT
218482. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK
218483. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT
218484. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK
218485. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT
218486. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK
218487. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT
218488. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK
218489. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT
218490. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK
218491. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT
218492. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK
218493. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT
218494. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK
218495. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT
218496. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK
218497. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT
218498. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK
218499. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT
218500. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK
218501. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT
218502. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK
218503. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT
218504. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK
218505. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT
218506. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK
218507. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT
218508. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK
218509. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT
218510. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK
218511. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT
218512. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK
218513. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT
218514. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK
218515. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT
218516. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK
218517. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT
218518. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK
218519. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT
218520. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK
218521. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT
218522. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK
218523. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT
218524. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK
218525. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT
218526. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK
218527. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT
218528. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK
218529. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT
218530. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK
218531. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT
218532. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK
218533. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT
218534. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK
218535. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT
218536. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK
218537. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT
218538. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK
218539. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT
218540. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK
218541. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT
218542. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK
218543. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT
218544. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK
218545. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT
218546. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK
218547. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT
218548. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK
218549. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT
218550. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK
218551. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT
218552. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK
218553. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT
218554. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK
218555. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT
218556. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK
218557. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT
218558. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK
218559. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT
218560. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK
218561. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT
218562. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK
218563. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT
218564. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK
218565. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT
218566. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK
218567. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT
218568. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK
218569. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT
218570. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK
218571. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT
218572. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK
218573. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT
218574. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK
218575. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT
218576. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK
218577. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT
218578. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK
218579. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT
218580. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK
218581. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT
218582. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK
218583. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT
218584. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK
218585. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT
218586. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK
218587. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT
218588. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK
218589. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT
218590. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK
218591. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT
218592. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK
218593. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT
218594. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK
218595. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT
218596. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK
218597. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT
218598. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK
218599. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT
218600. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK
218601. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT
218602. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK
218603. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT
218604. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK
218605. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT
218606. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK
218607. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT
218608. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK
218609. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT
218610. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK
218611. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT
218612. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK
218613. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT
218614. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK
218615. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT
218616. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK
218617. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT
218618. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK
218619. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT
218620. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK
218621. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT
218622. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK
218623. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT
218624. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK
218625. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT
218626. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK
218627. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT
218628. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK
218629. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT
218630. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK
218631. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT
218632. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK
218633. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT
218634. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK
218635. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT
218636. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK
218637. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT
218638. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK
218639. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT
218640. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK
218641. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT
218642. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK
218643. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT
218644. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK
218645. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT
218646. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK
218647. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT
218648. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK
218649. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT
218650. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK
218651. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT
218652. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK
218653. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT
218654. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK
218655. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT
218656. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK
218657. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT
218658. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK
218659. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT
218660. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK
218661. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT
218662. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK
218663. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT
218664. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK
218665. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT
218666. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK
218667. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT
218668. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK
218669. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT
218670. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK
218671. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT
218672. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK
218673. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT
218674. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK
218675. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT
218676. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK
218677. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT
218678. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK
218679. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT
218680. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK
218681. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT
218682. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK
218683. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT
218684. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK
218685. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT
218686. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK
218687. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT
218688. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK
218689. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT
218690. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK
218691. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT
218692. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK
218693. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT
218694. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK
218695. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT
218696. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK
218697. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT
218698. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK
218699. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT
218700. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK
218701. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT
218702. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK
218703. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT
218704. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK
218705. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT
218706. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK
218707. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT
218708. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK
218709. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT
218710. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK
218711. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT
218712. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK
218713. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT
218714. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK
218715. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT
218716. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK
218717. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT
218718. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK
218719. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT
218720. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK
218721. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT
218722. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK
218723. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT
218724. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK
218725. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT
218726. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK
218727. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT
218728. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK
218729. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT
218730. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK
218731. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT
218732. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK
218733. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT
218734. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK
218735. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT
218736. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK
218737. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT
218738. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK
218739. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT
218740. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK
218741. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT
218742. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK
218743. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT
218744. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK
218745. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT
218746. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK
218747. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT
218748. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK
218749. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT
218750. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK
218751. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT
218752. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK
218753. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT
218754. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK
218755. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT
218756. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK
218757. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT
218758. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK
218759. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT
218760. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK
218761. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT
218762. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK
218763. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT
218764. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK
218765. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT
218766. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK
218767. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT
218768. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK
218769. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT
218770. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK
218771. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT
218772. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK
218773. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT
218774. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK
218775. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT
218776. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK
218777. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT
218778. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK
218779. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT
218780. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK
218781. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT
218782. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK
218783. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT
218784. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK
218785. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT
218786. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK
218787. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT
218788. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK
218789. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT
218790. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK
218791. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT
218792. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK
218793. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT
218794. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK
218795. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT
218796. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK
218797. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT
218798. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK
218799. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT
218800. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK
218801. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT
218802. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK
218803. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT
218804. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK
218805. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT
218806. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK
218807. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT
218808. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK
218809. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT
218810. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK
218811. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT
218812. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK
218813. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT
218814. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK
218815. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT
218816. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK
218817. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT
218818. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK
218819. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT
218820. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK
218821. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT
218822. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK
218823. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT
218824. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK
218825. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT
218826. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK
218827. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT
218828. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK
218829. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT
218830. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK
218831. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT
218832. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK
218833. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT
218834. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK
218835. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT
218836. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK
218837. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT
218838. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK
218839. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT
218840. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK
218841. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT
218842. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK
218843. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT
218844. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK
218845. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT
218846. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK
218847. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT
218848. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK
218849. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT
218850. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK
218851. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT
218852. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK
218853. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT
218854. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK
218855. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT
218856. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK
218857. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT
218858. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK
218859. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT
218860. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK
218861. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT
218862. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK
218863. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT
218864. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK
218865. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT
218866. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK
218867. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT
218868. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK
218869. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT
218870. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK
218871. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT
218872. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK
218873. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT
218874. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK
218875. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT
218876. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK
218877. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT
218878. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK
218879. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT
218880. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK
218881. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT
218882. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK
218883. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT
218884. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK
218885. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT
218886. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK
218887. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT
218888. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK
218889. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT
218890. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK
218891. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT
218892. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK
218893. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT
218894. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK
218895. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT
218896. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK
218897. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT
218898. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK
218899. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT
218900. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK
218901. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT
218902. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK
218903. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT
218904. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK
218905. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT
218906. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK
218907. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT
218908. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK
218909. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT
218910. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK
218911. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT
218912. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK
218913. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT
218914. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK
218915. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT
218916. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK
218917. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT
218918. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK
218919. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT
218920. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK
218921. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT
218922. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK
218923. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT
218924. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK
218925. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT
218926. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK
218927. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT
218928. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK
218929. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT
218930. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK
218931. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT
218932. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK
218933. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT
218934. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK
218935. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT
218936. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK
218937. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT
218938. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK
218939. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT
218940. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK
218941. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT
218942. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK
218943. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT
218944. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK
218945. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT
218946. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK
218947. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT
218948. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK
218949. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT
218950. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK
218951. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK
218952. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT
218953. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT
218954. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK
218955. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT
218956. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK
218957. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT
218958. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK
218959. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT
218960. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK
218961. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT
218962. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK
218963. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT
218964. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK
218965. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT
218966. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK
218967. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT
218968. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK
218969. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT
218970. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK
218971. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT
218972. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK
218973. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT
218974. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK
218975. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT
218976. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK
218977. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT
218978. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK
218979. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT
218980. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK
218981. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT
218982. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK
218983. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT
218984. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK
218985. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT
218986. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK
218987. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT
218988. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK
218989. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT
218990. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK
218991. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT
218992. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
218993. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
218994. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
218995. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
218996. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
218997. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
218998. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
218999. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
219000. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
219001. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
219002. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
219003. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
219004. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
219005. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
219006. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
219007. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
219008. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
219009. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
219010. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
219011. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
219012. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
219013. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
219014. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
219015. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
219016. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
219017. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
219018. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
219019. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
219020. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
219021. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
219022. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
219023. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
219024. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK
219025. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT
219026. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK
219027. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT
219028. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK
219029. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT
219030. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK
219031. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT
219032. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK
219033. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT
219034. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK
219035. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT
219036. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK
219037. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT
219038. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK
219039. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT
219040. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK
219041. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT
219042. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK
219043. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT
219044. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK
219045. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT
219046. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK
219047. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT
219048. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK
219049. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT
219050. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK
219051. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT
219052. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK
219053. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT
219054. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK
219055. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT
219056. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK
219057. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT
219058. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK
219059. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT
219060. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK
219061. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT
219062. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK
219063. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT
219064. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK
219065. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT
219066. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK
219067. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT
219068. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK
219069. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT
219070. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
219071. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
219072. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
219073. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
219074. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
219075. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
219076. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
219077. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
219078. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK
219079. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT
219080. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK
219081. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT
219082. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK
219083. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT
219084. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK
219085. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT
219086. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK
219087. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT
219088. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK
219089. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT
219090. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK
219091. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK
219092. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT
219093. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT
219094. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK
219095. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT
219096. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK
219097. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT
219098. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK
219099. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT
219100. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK
219101. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT
219102. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK
219103. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT
219104. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK
219105. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT
219106. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK
219107. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT
219108. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK
219109. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT
219110. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK
219111. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT
219112. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK
219113. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT
219114. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK
219115. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT
219116. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK
219117. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT
219118. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK
219119. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT
219120. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK
219121. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT
219122. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK
219123. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT
219124. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK
219125. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT
219126. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK
219127. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT
219128. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK
219129. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT
219130. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK
219131. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT
219132. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK
219133. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT
219134. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK
219135. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT
219136. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK
219137. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT
219138. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK
219139. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT
219140. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK
219141. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT
219142. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK
219143. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT
219144. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK
219145. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT
219146. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK
219147. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT
219148. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK
219149. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT
219150. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK
219151. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT
219152. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK
219153. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT
219154. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK
219155. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT
219156. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK
219157. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT
219158. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK
219159. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT
219160. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK
219161. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT
219162. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK
219163. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT
219164. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK
219165. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT
219166. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK
219167. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT
219168. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK
219169. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT
219170. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK
219171. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT
219172. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK
219173. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT
219174. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK
219175. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT
219176. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK
219177. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT
219178. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK
219179. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT
219180. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK
219181. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT
219182. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK
219183. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT
219184. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK
219185. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT
219186. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK
219187. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT
219188. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK
219189. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT
219190. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK
219191. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT
219192. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK
219193. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT
219194. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK
219195. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT
219196. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK
219197. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT
219198. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK
219199. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT
219200. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK
219201. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT
219202. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK
219203. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT
219204. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK
219205. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT
219206. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK
219207. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT
219208. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK
219209. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT
219210. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK
219211. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT
219212. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK
219213. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT
219214. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK
219215. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT
219216. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK
219217. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT
219218. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK
219219. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT
219220. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK
219221. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT
219222. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK
219223. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT
219224. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK
219225. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT
219226. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK
219227. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT
219228. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK
219229. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT
219230. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK
219231. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT
219232. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK
219233. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT
219234. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK
219235. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT
219236. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK
219237. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT
219238. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK
219239. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT
219240. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK
219241. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT
219242. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK
219243. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT
219244. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK
219245. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT
219246. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK
219247. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT
219248. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK
219249. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT
219250. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK
219251. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT
219252. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK
219253. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT
219254. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK
219255. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT
219256. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK
219257. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT
219258. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK
219259. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT
219260. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK
219261. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT
219262. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK
219263. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT
219264. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK
219265. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT
219266. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK
219267. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT
219268. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK
219269. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT
219270. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK
219271. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT
219272. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK
219273. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT
219274. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK
219275. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT
219276. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK
219277. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT
219278. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK
219279. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT
219280. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK
219281. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT
219282. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK
219283. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT
219284. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK
219285. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT
219286. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK
219287. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT
219288. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK
219289. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT
219290. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK
219291. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT
219292. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK
219293. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT
219294. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK
219295. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT
219296. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK
219297. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT
219298. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK
219299. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT
219300. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK
219301. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT
219302. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK
219303. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT
219304. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK
219305. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT
219306. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK
219307. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT
219308. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK
219309. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT
219310. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK
219311. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT
219312. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK
219313. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT
219314. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK
219315. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT
219316. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK
219317. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT
219318. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK
219319. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT
219320. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK
219321. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT
219322. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK
219323. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT
219324. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK
219325. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT
219326. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK
219327. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT
219328. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK
219329. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT
219330. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK
219331. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT
219332. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK
219333. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT
219334. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK
219335. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT
219336. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK
219337. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT
219338. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK
219339. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT
219340. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK
219341. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT
219342. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK
219343. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT
219344. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK
219345. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT
219346. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK
219347. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT
219348. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK
219349. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT
219350. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK
219351. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT
219352. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK
219353. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT
219354. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK
219355. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT
219356. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK
219357. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT
219358. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK
219359. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT
219360. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK
219361. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT
219362. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK
219363. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT
219364. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK
219365. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT
219366. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK
219367. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT
219368. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK
219369. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT
219370. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK
219371. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT
219372. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK
219373. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT
219374. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK
219375. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT
219376. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK
219377. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT
219378. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK
219379. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK
219380. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT
219381. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT
219382. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK
219383. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT
219384. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK
219385. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT
219386. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK
219387. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT
219388. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK
219389. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT
219390. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK
219391. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT
219392. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK
219393. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT
219394. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK
219395. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT
219396. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK
219397. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT
219398. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK
219399. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT
219400. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK
219401. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT
219402. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK
219403. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT
219404. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK
219405. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT
219406. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK
219407. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT
219408. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK
219409. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT
219410. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK
219411. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT
219412. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK
219413. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT
219414. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK
219415. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT
219416. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK
219417. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT
219418. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK
219419. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT
219420. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK
219421. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT
219422. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK
219423. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT
219424. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK
219425. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT
219426. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK
219427. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT
219428. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK
219429. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT
219430. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK
219431. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT
219432. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK
219433. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT
219434. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK
219435. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT
219436. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK
219437. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
219438. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK
219439. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT
219440. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK
219441. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT
219442. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK
219443. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT
219444. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK
219445. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT
219446. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK
219447. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT
219448. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK
219449. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT
219450. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK
219451. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT
219452. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK
219453. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT
219454. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK
219455. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT
219456. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK
219457. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT
219458. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK
219459. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT
219460. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK
219461. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT
219462. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK
219463. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT
219464. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK
219465. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT
219466. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK
219467. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT
219468. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK
219469. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT
219470. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK
219471. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT
219472. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK
219473. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT
219474. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK
219475. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT
219476. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK
219477. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT
219478. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK
219479. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT
219480. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK
219481. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT
219482. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK
219483. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT
219484. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK
219485. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT
219486. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK
219487. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT
219488. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK
219489. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT
219490. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK
219491. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT
219492. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK
219493. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT
219494. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK
219495. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT
219496. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK
219497. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT
219498. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK
219499. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT
219500. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK
219501. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT
219502. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK
219503. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT
219504. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK
219505. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT
219506. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK
219507. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT
219508. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK
219509. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT
219510. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK
219511. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT
219512. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK
219513. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT
219514. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK
219515. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT
219516. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK
219517. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT
219518. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK
219519. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT
219520. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK
219521. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT
219522. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK
219523. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT
219524. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK
219525. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT
219526. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK
219527. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT
219528. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK
219529. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT
219530. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK
219531. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT
219532. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK
219533. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT
219534. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK
219535. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT
219536. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK
219537. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT
219538. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK
219539. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT
219540. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK
219541. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT
219542. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK
219543. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT
219544. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK
219545. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT
219546. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK
219547. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT
219548. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK
219549. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT
219550. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK
219551. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT
219552. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK
219553. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT
219554. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK
219555. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT
219556. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK
219557. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT
219558. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK
219559. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT
219560. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK
219561. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT
219562. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK
219563. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT
219564. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK
219565. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT
219566. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK
219567. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT
219568. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK
219569. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT
219570. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK
219571. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT
219572. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK
219573. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT
219574. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK
219575. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT
219576. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK
219577. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT
219578. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK
219579. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT
219580. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK
219581. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT
219582. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK
219583. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT
219584. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK
219585. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT
219586. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK
219587. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT
219588. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK
219589. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT
219590. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK
219591. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT
219592. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK
219593. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT
219594. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK
219595. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT
219596. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK
219597. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT
219598. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK
219599. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT
219600. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK
219601. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT
219602. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK
219603. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT
219604. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK
219605. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT
219606. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK
219607. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT
219608. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK
219609. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT
219610. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK
219611. DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT
219612. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK
219613. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
219614. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK
219615. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT
219616. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK
219617. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
219618. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK
219619. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
219620. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK
219621. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
219622. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK
219623. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
219624. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK
219625. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
219626. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK
219627. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
219628. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK
219629. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
219630. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK
219631. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
219632. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK
219633. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
219634. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK
219635. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
219636. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK
219637. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
219638. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK
219639. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
219640. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK
219641. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
219642. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK
219643. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
219644. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK
219645. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
219646. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK
219647. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
219648. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK
219649. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
219650. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK
219651. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
219652. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK
219653. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
219654. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK
219655. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
219656. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK
219657. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
219658. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK
219659. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
219660. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK
219661. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
219662. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK
219663. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
219664. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK
219665. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
219666. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK
219667. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
219668. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK
219669. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
219670. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK
219671. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
219672. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK
219673. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
219674. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK
219675. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
219676. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK
219677. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
219678. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK
219679. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
219680. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK
219681. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
219682. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK
219683. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
219684. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK
219685. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
219686. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK
219687. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
219688. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK
219689. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
219690. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK
219691. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
219692. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK
219693. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
219694. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK
219695. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
219696. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK
219697. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
219698. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK
219699. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
219700. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK
219701. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
219702. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK
219703. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
219704. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK
219705. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
219706. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK
219707. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
219708. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK
219709. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
219710. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK
219711. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
219712. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK
219713. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
219714. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK
219715. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
219716. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK
219717. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
219718. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK
219719. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
219720. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK
219721. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
219722. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK
219723. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
219724. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK
219725. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
219726. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK
219727. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
219728. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK
219729. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
219730. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK
219731. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
219732. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK
219733. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
219734. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK
219735. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
219736. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK
219737. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
219738. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK
219739. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
219740. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK
219741. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
219742. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK
219743. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
219744. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK
219745. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
219746. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK
219747. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
219748. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK
219749. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
219750. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK
219751. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
219752. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK
219753. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
219754. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK
219755. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
219756. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK
219757. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
219758. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK
219759. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
219760. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK
219761. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
219762. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK
219763. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
219764. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK
219765. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
219766. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK
219767. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
219768. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK
219769. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
219770. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK
219771. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
219772. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK
219773. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
219774. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK
219775. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
219776. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK
219777. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
219778. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK
219779. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
219780. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK
219781. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
219782. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK
219783. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
219784. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK
219785. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
219786. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK
219787. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
219788. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK
219789. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
219790. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK
219791. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
219792. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK
219793. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
219794. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK
219795. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
219796. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK
219797. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
219798. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK
219799. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
219800. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK
219801. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
219802. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK
219803. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
219804. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK
219805. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
219806. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK
219807. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
219808. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK
219809. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
219810. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK
219811. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
219812. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK
219813. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
219814. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK
219815. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
219816. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK
219817. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
219818. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK
219819. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
219820. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK
219821. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
219822. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK
219823. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
219824. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK
219825. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
219826. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK
219827. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
219828. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK
219829. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
219830. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK
219831. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
219832. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK
219833. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
219834. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK
219835. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
219836. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK
219837. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
219838. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK
219839. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
219840. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK
219841. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
219842. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK
219843. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
219844. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK
219845. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
219846. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK
219847. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
219848. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK
219849. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
219850. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK
219851. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
219852. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK
219853. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
219854. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK
219855. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
219856. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK
219857. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
219858. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK
219859. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
219860. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK
219861. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
219862. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK
219863. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
219864. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK
219865. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
219866. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK
219867. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
219868. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK
219869. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
219870. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK
219871. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
219872. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK
219873. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
219874. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK
219875. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
219876. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK
219877. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
219878. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK
219879. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
219880. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK
219881. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
219882. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK
219883. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
219884. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK
219885. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
219886. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK
219887. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
219888. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK
219889. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
219890. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK
219891. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
219892. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK
219893. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
219894. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK
219895. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
219896. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK
219897. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
219898. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK
219899. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
219900. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK
219901. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
219902. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK
219903. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
219904. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK
219905. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
219906. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK
219907. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
219908. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK
219909. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
219910. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK
219911. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
219912. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK
219913. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
219914. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK
219915. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
219916. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK
219917. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
219918. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK
219919. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
219920. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK
219921. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
219922. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK
219923. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
219924. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK
219925. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
219926. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK
219927. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
219928. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK
219929. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
219930. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK
219931. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
219932. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK
219933. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
219934. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK
219935. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
219936. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK
219937. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
219938. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK
219939. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
219940. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK
219941. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
219942. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK
219943. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
219944. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK
219945. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
219946. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK
219947. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
219948. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK
219949. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
219950. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK
219951. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
219952. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK
219953. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
219954. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK
219955. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
219956. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK
219957. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
219958. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK
219959. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
219960. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK
219961. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
219962. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK
219963. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
219964. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK
219965. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
219966. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK
219967. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
219968. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK
219969. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
219970. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK
219971. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
219972. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK
219973. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
219974. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK
219975. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
219976. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK
219977. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
219978. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK
219979. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
219980. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK
219981. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
219982. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK
219983. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
219984. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK
219985. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
219986. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK
219987. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
219988. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK
219989. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
219990. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK
219991. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
219992. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK
219993. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
219994. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK
219995. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
219996. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK
219997. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
219998. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK
219999. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
220000. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK
220001. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
220002. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK
220003. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
220004. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK
220005. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
220006. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK
220007. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
220008. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK
220009. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
220010. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK
220011. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
220012. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK
220013. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
220014. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK
220015. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
220016. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK
220017. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
220018. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK
220019. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
220020. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK
220021. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
220022. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK
220023. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
220024. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK
220025. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
220026. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK
220027. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
220028. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK
220029. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
220030. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK
220031. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
220032. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK
220033. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
220034. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK
220035. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
220036. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK
220037. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
220038. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK
220039. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
220040. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK
220041. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
220042. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK
220043. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
220044. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK
220045. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
220046. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK
220047. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
220048. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK
220049. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
220050. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK
220051. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
220052. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK
220053. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
220054. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK
220055. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
220056. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK
220057. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
220058. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK
220059. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
220060. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK
220061. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
220062. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK
220063. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
220064. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK
220065. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
220066. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK
220067. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
220068. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK
220069. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
220070. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK
220071. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
220072. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK
220073. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
220074. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK
220075. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
220076. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK
220077. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
220078. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK
220079. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
220080. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK
220081. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
220082. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK
220083. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
220084. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK
220085. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
220086. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK
220087. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
220088. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK
220089. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
220090. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK
220091. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
220092. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK
220093. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
220094. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK
220095. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
220096. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK
220097. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
220098. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK
220099. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
220100. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK
220101. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
220102. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK
220103. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
220104. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK
220105. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
220106. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK
220107. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
220108. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK
220109. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
220110. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK
220111. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
220112. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK
220113. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
220114. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK
220115. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
220116. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK
220117. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
220118. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK
220119. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
220120. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK
220121. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
220122. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK
220123. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
220124. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK
220125. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
220126. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK
220127. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
220128. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK
220129. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
220130. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK
220131. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
220132. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK
220133. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
220134. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK
220135. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
220136. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK
220137. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
220138. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK
220139. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
220140. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK
220141. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
220142. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK
220143. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
220144. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK
220145. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
220146. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK
220147. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
220148. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK
220149. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
220150. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK
220151. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
220152. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK
220153. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
220154. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK
220155. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
220156. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK
220157. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
220158. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK
220159. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
220160. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK
220161. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
220162. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK
220163. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
220164. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK
220165. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
220166. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK
220167. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
220168. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK
220169. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
220170. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK
220171. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
220172. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK
220173. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
220174. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK
220175. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
220176. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK
220177. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
220178. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK
220179. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
220180. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK
220181. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
220182. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK
220183. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
220184. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK
220185. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
220186. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK
220187. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
220188. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK
220189. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
220190. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK
220191. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
220192. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK
220193. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
220194. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK
220195. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
220196. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK
220197. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
220198. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK
220199. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
220200. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK
220201. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
220202. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK
220203. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
220204. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK
220205. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
220206. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK
220207. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
220208. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK
220209. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
220210. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK
220211. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
220212. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK
220213. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
220214. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK
220215. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
220216. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK
220217. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
220218. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK
220219. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
220220. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK
220221. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
220222. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK
220223. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
220224. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK
220225. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
220226. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK
220227. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
220228. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK
220229. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
220230. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK
220231. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
220232. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK
220233. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
220234. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK
220235. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
220236. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK
220237. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
220238. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK
220239. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
220240. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK
220241. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
220242. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK
220243. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
220244. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK
220245. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
220246. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK
220247. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
220248. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK
220249. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
220250. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK
220251. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
220252. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK
220253. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
220254. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK
220255. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
220256. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK
220257. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
220258. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK
220259. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
220260. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK
220261. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
220262. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK
220263. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
220264. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK
220265. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
220266. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK
220267. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
220268. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK
220269. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
220270. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK
220271. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
220272. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK
220273. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
220274. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK
220275. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
220276. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK
220277. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
220278. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK
220279. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
220280. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK
220281. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
220282. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK
220283. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
220284. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK
220285. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
220286. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK
220287. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
220288. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK
220289. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
220290. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK
220291. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
220292. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK
220293. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
220294. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK
220295. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
220296. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK
220297. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
220298. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK
220299. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
220300. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK
220301. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
220302. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK
220303. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
220304. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK
220305. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
220306. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK
220307. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
220308. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK
220309. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
220310. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK
220311. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
220312. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK
220313. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
220314. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK
220315. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
220316. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK
220317. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
220318. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK
220319. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
220320. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK
220321. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
220322. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK
220323. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
220324. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK
220325. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
220326. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK
220327. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
220328. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK
220329. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
220330. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK
220331. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
220332. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK
220333. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
220334. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK
220335. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
220336. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK
220337. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
220338. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK
220339. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
220340. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK
220341. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
220342. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK
220343. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
220344. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK
220345. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
220346. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK
220347. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
220348. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK
220349. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
220350. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK
220351. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
220352. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK
220353. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
220354. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK
220355. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
220356. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK
220357. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
220358. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK
220359. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
220360. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK
220361. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
220362. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK
220363. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
220364. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK
220365. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
220366. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK
220367. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
220368. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK
220369. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
220370. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK
220371. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
220372. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK
220373. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
220374. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK
220375. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
220376. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK
220377. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
220378. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK
220379. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
220380. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK
220381. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
220382. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK
220383. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
220384. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK
220385. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
220386. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK
220387. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
220388. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK
220389. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
220390. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK
220391. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
220392. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK
220393. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
220394. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK
220395. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
220396. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK
220397. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
220398. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK
220399. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
220400. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK
220401. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
220402. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK
220403. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
220404. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK
220405. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
220406. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK
220407. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
220408. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK
220409. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
220410. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK
220411. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
220412. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK
220413. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
220414. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK
220415. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
220416. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK
220417. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
220418. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK
220419. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
220420. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK
220421. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
220422. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK
220423. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
220424. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK
220425. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
220426. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK
220427. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
220428. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK
220429. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
220430. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK
220431. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
220432. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK
220433. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
220434. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK
220435. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
220436. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK
220437. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
220438. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK
220439. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
220440. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK
220441. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
220442. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK
220443. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
220444. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK
220445. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
220446. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK
220447. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
220448. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK
220449. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
220450. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK
220451. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
220452. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK
220453. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
220454. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK
220455. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
220456. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK
220457. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
220458. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK
220459. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
220460. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK
220461. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
220462. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK
220463. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
220464. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK
220465. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
220466. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK
220467. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
220468. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK
220469. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
220470. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK
220471. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
220472. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK
220473. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
220474. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK
220475. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
220476. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK
220477. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
220478. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK
220479. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
220480. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK
220481. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
220482. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK
220483. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
220484. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK
220485. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
220486. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK
220487. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
220488. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK
220489. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
220490. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK
220491. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
220492. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK
220493. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
220494. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK
220495. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
220496. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK
220497. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
220498. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK
220499. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
220500. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK
220501. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
220502. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK
220503. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
220504. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK
220505. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
220506. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK
220507. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
220508. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK
220509. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
220510. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK
220511. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
220512. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK
220513. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
220514. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK
220515. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
220516. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK
220517. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
220518. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK
220519. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
220520. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK
220521. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
220522. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK
220523. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
220524. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK
220525. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
220526. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK
220527. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
220528. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK
220529. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
220530. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK
220531. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
220532. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK
220533. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
220534. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK
220535. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
220536. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK
220537. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
220538. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK
220539. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
220540. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK
220541. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
220542. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK
220543. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
220544. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK
220545. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
220546. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK
220547. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
220548. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK
220549. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
220550. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK
220551. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
220552. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK
220553. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
220554. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK
220555. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
220556. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK
220557. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
220558. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK
220559. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
220560. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK
220561. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
220562. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK
220563. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
220564. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK
220565. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
220566. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK
220567. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
220568. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK
220569. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
220570. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK
220571. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
220572. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK
220573. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
220574. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK
220575. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
220576. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK
220577. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
220578. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK
220579. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
220580. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK
220581. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
220582. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK
220583. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
220584. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK
220585. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
220586. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK
220587. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
220588. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK
220589. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
220590. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK
220591. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
220592. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK
220593. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
220594. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK
220595. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
220596. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK
220597. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
220598. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK
220599. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
220600. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK
220601. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
220602. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK
220603. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
220604. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK
220605. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
220606. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK
220607. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
220608. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK
220609. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
220610. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK
220611. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
220612. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK
220613. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
220614. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK
220615. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
220616. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK
220617. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
220618. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK
220619. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
220620. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK
220621. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
220622. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK
220623. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
220624. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK
220625. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
220626. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK
220627. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
220628. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK
220629. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
220630. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK
220631. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
220632. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK
220633. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
220634. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK
220635. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
220636. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK
220637. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
220638. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK
220639. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
220640. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK
220641. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
220642. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK
220643. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
220644. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK
220645. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
220646. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK
220647. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
220648. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK
220649. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
220650. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK
220651. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
220652. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK
220653. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
220654. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK
220655. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
220656. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK
220657. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
220658. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK
220659. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
220660. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK
220661. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
220662. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK
220663. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
220664. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK
220665. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
220666. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK
220667. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
220668. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK
220669. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
220670. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK
220671. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
220672. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK
220673. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
220674. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK
220675. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
220676. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK
220677. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
220678. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK
220679. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
220680. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK
220681. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
220682. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK
220683. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
220684. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK
220685. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
220686. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK
220687. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
220688. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK
220689. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
220690. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK
220691. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
220692. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK
220693. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
220694. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK
220695. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
220696. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK
220697. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
220698. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK
220699. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
220700. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK
220701. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
220702. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK
220703. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
220704. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK
220705. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
220706. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK
220707. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
220708. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK
220709. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
220710. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK
220711. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
220712. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK
220713. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
220714. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK
220715. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
220716. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK
220717. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
220718. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK
220719. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
220720. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK
220721. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
220722. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK
220723. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
220724. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK
220725. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
220726. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK
220727. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
220728. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK
220729. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
220730. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK
220731. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
220732. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK
220733. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
220734. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK
220735. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
220736. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK
220737. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
220738. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK
220739. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
220740. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK
220741. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
220742. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK
220743. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
220744. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK
220745. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
220746. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK
220747. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
220748. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK
220749. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
220750. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK
220751. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
220752. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK
220753. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
220754. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK
220755. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
220756. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK
220757. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
220758. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK
220759. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
220760. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK
220761. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
220762. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK
220763. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
220764. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK
220765. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
220766. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK
220767. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
220768. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK
220769. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
220770. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK
220771. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
220772. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK
220773. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
220774. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK
220775. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
220776. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK
220777. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
220778. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK
220779. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
220780. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK
220781. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
220782. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK
220783. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
220784. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK
220785. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
220786. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK
220787. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
220788. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK
220789. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
220790. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK
220791. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
220792. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK
220793. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
220794. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK
220795. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
220796. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK
220797. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
220798. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK
220799. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
220800. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK
220801. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
220802. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK
220803. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
220804. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK
220805. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
220806. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK
220807. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
220808. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK
220809. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
220810. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK
220811. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
220812. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK
220813. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
220814. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK
220815. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
220816. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK
220817. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
220818. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK
220819. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
220820. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK
220821. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
220822. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK
220823. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
220824. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK
220825. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
220826. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK
220827. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
220828. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK
220829. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
220830. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK
220831. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
220832. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK
220833. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
220834. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK
220835. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
220836. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK
220837. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
220838. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK
220839. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
220840. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK
220841. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
220842. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK
220843. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
220844. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK
220845. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
220846. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK
220847. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
220848. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK
220849. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
220850. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK
220851. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
220852. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK
220853. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
220854. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK
220855. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
220856. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK
220857. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
220858. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK
220859. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
220860. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK
220861. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
220862. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK
220863. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
220864. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK
220865. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
220866. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK
220867. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
220868. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK
220869. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
220870. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK
220871. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
220872. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK
220873. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
220874. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK
220875. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
220876. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK
220877. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
220878. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK
220879. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
220880. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK
220881. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
220882. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK
220883. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
220884. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK
220885. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
220886. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK
220887. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
220888. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK
220889. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
220890. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK
220891. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
220892. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK
220893. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
220894. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK
220895. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
220896. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK
220897. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
220898. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK
220899. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
220900. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK
220901. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
220902. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK
220903. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
220904. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK
220905. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
220906. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK
220907. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
220908. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK
220909. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
220910. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK
220911. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
220912. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK
220913. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
220914. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK
220915. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
220916. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK
220917. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
220918. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK
220919. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
220920. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK
220921. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
220922. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK
220923. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
220924. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK
220925. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
220926. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK
220927. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
220928. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK
220929. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
220930. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK
220931. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
220932. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK
220933. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
220934. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK
220935. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
220936. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK
220937. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
220938. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK
220939. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
220940. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK
220941. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
220942. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK
220943. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
220944. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK
220945. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
220946. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK
220947. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
220948. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK
220949. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
220950. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK
220951. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
220952. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK
220953. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
220954. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK
220955. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
220956. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK
220957. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
220958. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK
220959. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
220960. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK
220961. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
220962. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK
220963. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
220964. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK
220965. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
220966. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK
220967. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
220968. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK
220969. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
220970. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK
220971. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
220972. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK
220973. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
220974. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK
220975. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
220976. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK
220977. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
220978. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK
220979. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
220980. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK
220981. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
220982. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK
220983. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
220984. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK
220985. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
220986. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK
220987. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
220988. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK
220989. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
220990. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK
220991. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
220992. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK
220993. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
220994. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK
220995. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
220996. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK
220997. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
220998. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK
220999. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
221000. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK
221001. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
221002. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK
221003. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
221004. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK
221005. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
221006. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK
221007. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
221008. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK
221009. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
221010. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK
221011. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
221012. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK
221013. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
221014. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK
221015. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
221016. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK
221017. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
221018. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK
221019. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
221020. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK
221021. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
221022. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK
221023. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
221024. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK
221025. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
221026. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK
221027. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
221028. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK
221029. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
221030. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK
221031. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
221032. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK
221033. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
221034. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK
221035. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
221036. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK
221037. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
221038. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK
221039. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
221040. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK
221041. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
221042. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK
221043. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
221044. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK
221045. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
221046. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK
221047. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
221048. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK
221049. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
221050. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK
221051. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
221052. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK
221053. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
221054. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK
221055. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
221056. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK
221057. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
221058. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK
221059. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
221060. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK
221061. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
221062. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK
221063. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
221064. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK
221065. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
221066. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK
221067. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
221068. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK
221069. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
221070. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK
221071. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
221072. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK
221073. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
221074. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK
221075. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
221076. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK
221077. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
221078. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK
221079. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
221080. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK
221081. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
221082. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK
221083. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
221084. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK
221085. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
221086. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK
221087. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
221088. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK
221089. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
221090. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK
221091. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
221092. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK
221093. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
221094. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK
221095. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
221096. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK
221097. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
221098. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK
221099. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
221100. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK
221101. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
221102. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK
221103. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
221104. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK
221105. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
221106. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK
221107. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
221108. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK
221109. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
221110. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK
221111. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
221112. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK
221113. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
221114. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK
221115. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
221116. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK
221117. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
221118. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK
221119. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
221120. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK
221121. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
221122. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK
221123. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
221124. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK
221125. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
221126. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK
221127. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
221128. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK
221129. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
221130. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK
221131. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
221132. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK
221133. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
221134. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK
221135. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
221136. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK
221137. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
221138. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK
221139. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
221140. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK
221141. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
221142. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK
221143. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
221144. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK
221145. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
221146. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK
221147. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
221148. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK
221149. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
221150. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK
221151. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
221152. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK
221153. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
221154. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK
221155. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
221156. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK
221157. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
221158. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK
221159. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
221160. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK
221161. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
221162. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK
221163. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
221164. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK
221165. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
221166. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK
221167. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
221168. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK
221169. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
221170. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK
221171. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
221172. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK
221173. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
221174. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK
221175. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
221176. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK
221177. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
221178. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK
221179. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
221180. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK
221181. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
221182. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK
221183. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
221184. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK
221185. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
221186. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK
221187. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
221188. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK
221189. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
221190. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK
221191. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
221192. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK
221193. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
221194. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK
221195. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
221196. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK
221197. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
221198. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK
221199. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
221200. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK
221201. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
221202. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK
221203. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
221204. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK
221205. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
221206. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK
221207. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
221208. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK
221209. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
221210. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK
221211. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
221212. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK
221213. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
221214. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK
221215. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
221216. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK
221217. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
221218. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK
221219. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
221220. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK
221221. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
221222. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK
221223. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
221224. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK
221225. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
221226. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK
221227. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
221228. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK
221229. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
221230. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK
221231. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
221232. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK
221233. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
221234. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK
221235. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
221236. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK
221237. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
221238. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK
221239. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
221240. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK
221241. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
221242. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK
221243. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
221244. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK
221245. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
221246. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK
221247. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
221248. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK
221249. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
221250. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK
221251. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
221252. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK
221253. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
221254. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK
221255. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
221256. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK
221257. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
221258. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK
221259. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
221260. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK
221261. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
221262. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK
221263. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
221264. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK
221265. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
221266. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK
221267. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
221268. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK
221269. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
221270. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK
221271. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
221272. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK
221273. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
221274. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK
221275. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
221276. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK
221277. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
221278. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK
221279. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
221280. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK
221281. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
221282. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK
221283. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
221284. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK
221285. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
221286. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK
221287. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
221288. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK
221289. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
221290. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK
221291. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
221292. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK
221293. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
221294. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK
221295. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
221296. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK
221297. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
221298. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK
221299. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
221300. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK
221301. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
221302. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK
221303. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
221304. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK
221305. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
221306. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK
221307. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
221308. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK
221309. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
221310. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK
221311. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
221312. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK
221313. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
221314. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK
221315. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
221316. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK
221317. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
221318. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK
221319. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
221320. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK
221321. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
221322. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK
221323. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
221324. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK
221325. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
221326. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK
221327. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
221328. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK
221329. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
221330. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK
221331. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
221332. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK
221333. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
221334. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK
221335. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
221336. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK
221337. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
221338. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK
221339. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
221340. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK
221341. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
221342. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK
221343. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
221344. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK
221345. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
221346. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK
221347. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
221348. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK
221349. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
221350. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK
221351. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
221352. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK
221353. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
221354. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK
221355. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
221356. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK
221357. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
221358. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK
221359. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
221360. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK
221361. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
221362. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK
221363. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
221364. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK
221365. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
221366. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK
221367. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
221368. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK
221369. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
221370. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK
221371. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
221372. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK
221373. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
221374. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK
221375. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
221376. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK
221377. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
221378. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK
221379. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
221380. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK
221381. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
221382. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK
221383. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
221384. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK
221385. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
221386. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK
221387. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
221388. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK
221389. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
221390. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK
221391. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
221392. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK
221393. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
221394. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK
221395. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
221396. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK
221397. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
221398. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK
221399. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
221400. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK
221401. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
221402. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK
221403. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
221404. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK
221405. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
221406. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK
221407. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
221408. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK
221409. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
221410. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK
221411. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
221412. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK
221413. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
221414. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK
221415. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
221416. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK
221417. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
221418. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK
221419. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
221420. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK
221421. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
221422. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK
221423. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
221424. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK
221425. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
221426. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK
221427. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
221428. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK
221429. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
221430. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK
221431. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
221432. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK
221433. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
221434. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK
221435. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
221436. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK
221437. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
221438. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK
221439. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
221440. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK
221441. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
221442. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK
221443. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
221444. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK
221445. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
221446. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK
221447. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
221448. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK
221449. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
221450. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK
221451. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
221452. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK
221453. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
221454. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK
221455. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
221456. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK
221457. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
221458. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK
221459. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
221460. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK
221461. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
221462. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK
221463. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
221464. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK
221465. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
221466. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK
221467. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
221468. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK
221469. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
221470. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK
221471. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
221472. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK
221473. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
221474. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK
221475. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
221476. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK
221477. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
221478. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK
221479. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
221480. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK
221481. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
221482. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK
221483. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
221484. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK
221485. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
221486. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK
221487. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
221488. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK
221489. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
221490. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK
221491. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
221492. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK
221493. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
221494. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK
221495. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
221496. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK
221497. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
221498. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK
221499. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
221500. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK
221501. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
221502. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK
221503. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
221504. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK
221505. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
221506. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK
221507. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
221508. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK
221509. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
221510. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK
221511. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
221512. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK
221513. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
221514. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK
221515. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
221516. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK
221517. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
221518. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK
221519. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
221520. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK
221521. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
221522. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK
221523. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
221524. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK
221525. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
221526. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK
221527. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
221528. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK
221529. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
221530. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK
221531. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
221532. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK
221533. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
221534. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK
221535. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
221536. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK
221537. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
221538. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK
221539. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
221540. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK
221541. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
221542. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK
221543. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
221544. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK
221545. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
221546. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK
221547. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
221548. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK
221549. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
221550. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK
221551. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
221552. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK
221553. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
221554. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK
221555. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
221556. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK
221557. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
221558. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK
221559. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
221560. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK
221561. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
221562. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK
221563. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
221564. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK
221565. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
221566. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK
221567. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
221568. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK
221569. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
221570. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK
221571. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
221572. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK
221573. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
221574. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK
221575. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
221576. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK
221577. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
221578. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK
221579. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
221580. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK
221581. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
221582. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK
221583. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
221584. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK
221585. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
221586. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK
221587. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
221588. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK
221589. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
221590. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK
221591. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
221592. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK
221593. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
221594. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK
221595. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
221596. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK
221597. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
221598. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK
221599. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
221600. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK
221601. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
221602. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK
221603. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
221604. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK
221605. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
221606. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK
221607. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
221608. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK
221609. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
221610. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK
221611. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
221612. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK
221613. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
221614. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK
221615. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
221616. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK
221617. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
221618. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK
221619. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
221620. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK
221621. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
221622. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK
221623. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
221624. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK
221625. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
221626. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK
221627. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
221628. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK
221629. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
221630. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK
221631. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
221632. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK
221633. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
221634. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK
221635. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
221636. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK
221637. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
221638. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK
221639. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
221640. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK
221641. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
221642. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK
221643. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
221644. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK
221645. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
221646. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK
221647. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
221648. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK
221649. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
221650. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK
221651. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
221652. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK
221653. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
221654. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK
221655. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
221656. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK
221657. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
221658. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK
221659. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
221660. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK
221661. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
221662. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK
221663. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
221664. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK
221665. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
221666. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK
221667. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
221668. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK
221669. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
221670. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK
221671. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
221672. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK
221673. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
221674. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK
221675. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
221676. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK
221677. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
221678. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK
221679. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
221680. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK
221681. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
221682. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK
221683. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
221684. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK
221685. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
221686. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK
221687. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
221688. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK
221689. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
221690. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK
221691. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
221692. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK
221693. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
221694. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK
221695. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
221696. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK
221697. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
221698. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK
221699. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
221700. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK
221701. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
221702. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK
221703. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
221704. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK
221705. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
221706. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK
221707. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
221708. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK
221709. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
221710. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK
221711. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
221712. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK
221713. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
221714. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK
221715. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
221716. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK
221717. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
221718. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK
221719. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
221720. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK
221721. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
221722. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK
221723. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
221724. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK
221725. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
221726. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK
221727. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
221728. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK
221729. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
221730. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK
221731. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
221732. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK
221733. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
221734. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK
221735. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
221736. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK
221737. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
221738. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK
221739. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
221740. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK
221741. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
221742. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK
221743. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
221744. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK
221745. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
221746. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK
221747. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
221748. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK
221749. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
221750. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK
221751. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
221752. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK
221753. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
221754. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK
221755. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
221756. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK
221757. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
221758. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK
221759. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
221760. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK
221761. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
221762. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK
221763. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
221764. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK
221765. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
221766. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK
221767. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
221768. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK
221769. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
221770. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK
221771. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
221772. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK
221773. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
221774. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK
221775. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
221776. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK
221777. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
221778. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK
221779. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
221780. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK
221781. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
221782. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK
221783. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
221784. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK
221785. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
221786. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK
221787. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
221788. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK
221789. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
221790. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK
221791. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
221792. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK
221793. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
221794. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK
221795. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
221796. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK
221797. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
221798. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK
221799. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
221800. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK
221801. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
221802. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK
221803. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
221804. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK
221805. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
221806. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK
221807. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
221808. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK
221809. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
221810. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK
221811. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
221812. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK
221813. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
221814. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK
221815. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
221816. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK
221817. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
221818. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK
221819. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
221820. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK
221821. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
221822. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK
221823. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
221824. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK
221825. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
221826. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK
221827. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
221828. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK
221829. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
221830. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK
221831. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
221832. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK
221833. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
221834. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK
221835. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
221836. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK
221837. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
221838. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK
221839. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
221840. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK
221841. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
221842. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK
221843. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
221844. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK
221845. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
221846. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK
221847. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
221848. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK
221849. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
221850. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK
221851. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
221852. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK
221853. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
221854. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK
221855. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
221856. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK
221857. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
221858. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK
221859. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
221860. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK
221861. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
221862. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK
221863. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
221864. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK
221865. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
221866. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK
221867. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
221868. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK
221869. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
221870. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK
221871. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
221872. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK
221873. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
221874. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK
221875. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
221876. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK
221877. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
221878. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK
221879. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
221880. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK
221881. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
221882. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK
221883. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
221884. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK
221885. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
221886. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK
221887. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
221888. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK
221889. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
221890. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK
221891. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
221892. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK
221893. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
221894. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK
221895. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
221896. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK
221897. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
221898. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK
221899. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
221900. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK
221901. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
221902. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK
221903. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
221904. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK
221905. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
221906. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK
221907. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
221908. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK
221909. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
221910. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK
221911. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
221912. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK
221913. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
221914. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK
221915. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
221916. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK
221917. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
221918. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK
221919. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
221920. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK
221921. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
221922. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK
221923. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
221924. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK
221925. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
221926. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK
221927. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
221928. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK
221929. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
221930. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK
221931. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
221932. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK
221933. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
221934. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK
221935. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
221936. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK
221937. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
221938. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK
221939. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
221940. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK
221941. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
221942. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK
221943. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
221944. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK
221945. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
221946. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK
221947. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
221948. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK
221949. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
221950. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK
221951. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
221952. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK
221953. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
221954. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK
221955. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
221956. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK
221957. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
221958. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK
221959. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
221960. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK
221961. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
221962. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK
221963. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
221964. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK
221965. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
221966. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK
221967. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
221968. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK
221969. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
221970. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK
221971. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
221972. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK
221973. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
221974. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK
221975. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
221976. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK
221977. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
221978. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK
221979. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
221980. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK
221981. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
221982. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK
221983. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
221984. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK
221985. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
221986. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK
221987. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
221988. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK
221989. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
221990. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK
221991. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
221992. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK
221993. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
221994. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK
221995. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
221996. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK
221997. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
221998. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK
221999. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
222000. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK
222001. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
222002. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK
222003. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
222004. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK
222005. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
222006. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK
222007. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
222008. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK
222009. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
222010. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK
222011. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
222012. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK
222013. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
222014. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK
222015. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
222016. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK
222017. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
222018. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK
222019. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
222020. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK
222021. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
222022. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK
222023. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
222024. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK
222025. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
222026. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK
222027. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
222028. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK
222029. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
222030. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK
222031. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
222032. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK
222033. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
222034. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK
222035. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
222036. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK
222037. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
222038. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK
222039. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
222040. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK
222041. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
222042. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK
222043. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
222044. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK
222045. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
222046. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK
222047. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
222048. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK
222049. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
222050. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK
222051. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
222052. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK
222053. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
222054. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK
222055. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
222056. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK
222057. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
222058. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK
222059. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
222060. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK
222061. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
222062. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK
222063. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
222064. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK
222065. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
222066. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK
222067. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
222068. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK
222069. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
222070. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK
222071. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
222072. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK
222073. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
222074. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK
222075. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
222076. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK
222077. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
222078. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK
222079. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
222080. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK
222081. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
222082. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK
222083. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
222084. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK
222085. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
222086. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK
222087. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
222088. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK
222089. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
222090. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK
222091. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
222092. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK
222093. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
222094. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK
222095. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
222096. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK
222097. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
222098. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK
222099. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
222100. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK
222101. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
222102. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK
222103. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
222104. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK
222105. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
222106. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK
222107. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
222108. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK
222109. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
222110. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK
222111. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
222112. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
222113. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
222114. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
222115. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
222116. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
222117. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
222118. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
222119. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
222120. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
222121. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
222122. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
222123. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
222124. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
222125. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
222126. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
222127. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
222128. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
222129. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
222130. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
222131. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
222132. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
222133. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
222134. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
222135. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
222136. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
222137. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
222138. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
222139. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
222140. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
222141. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
222142. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
222143. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
222144. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
222145. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
222146. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
222147. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
222148. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
222149. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
222150. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
222151. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
222152. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK
222153. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT
222154. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK
222155. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT
222156. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK
222157. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT
222158. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK
222159. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT
222160. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK
222161. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT
222162. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK
222163. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT
222164. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK
222165. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT
222166. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK
222167. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT
222168. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK
222169. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT
222170. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK
222171. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT
222172. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK
222173. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT
222174. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK
222175. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT
222176. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK
222177. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT
222178. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK
222179. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT
222180. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK
222181. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT
222182. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK
222183. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT
222184. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK
222185. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT
222186. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK
222187. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT
222188. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK
222189. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT
222190. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK
222191. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT
222192. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK
222193. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT
222194. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK
222195. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT
222196. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK
222197. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT
222198. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK
222199. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT
222200. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK
222201. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT
222202. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK
222203. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT
222204. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK
222205. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT
222206. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK
222207. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT
222208. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK
222209. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT
222210. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK
222211. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT
222212. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK
222213. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT
222214. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK
222215. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT
222216. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK
222217. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT
222218. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK
222219. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT
222220. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK
222221. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT
222222. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK
222223. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT
222224. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK
222225. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT
222226. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK
222227. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT
222228. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK
222229. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT
222230. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK
222231. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT
222232. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK
222233. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT
222234. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK
222235. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT
222236. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK
222237. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT
222238. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK
222239. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT
222240. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK
222241. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT
222242. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK
222243. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT
222244. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK
222245. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT
222246. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK
222247. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT
222248. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK
222249. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT
222250. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK
222251. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT
222252. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK
222253. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT
222254. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK
222255. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT
222256. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK
222257. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT
222258. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK
222259. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT
222260. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK
222261. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT
222262. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK
222263. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT
222264. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK
222265. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT
222266. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK
222267. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT
222268. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK
222269. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT
222270. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK
222271. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT
222272. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK
222273. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT
222274. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK
222275. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT
222276. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK
222277. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT
222278. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK
222279. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT
222280. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK
222281. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT
222282. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK
222283. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT
222284. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK
222285. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT
222286. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK
222287. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT
222288. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK
222289. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT
222290. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK
222291. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT
222292. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK
222293. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT
222294. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK
222295. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT
222296. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK
222297. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT
222298. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK
222299. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT
222300. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK
222301. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT
222302. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK
222303. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT
222304. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK
222305. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT
222306. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK
222307. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT
222308. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK
222309. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT
222310. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK
222311. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT
222312. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK
222313. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT
222314. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK
222315. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT
222316. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK
222317. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT
222318. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK
222319. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT
222320. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK
222321. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT
222322. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK
222323. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT
222324. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK
222325. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT
222326. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK
222327. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT
222328. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK
222329. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT
222330. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK
222331. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT
222332. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK
222333. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT
222334. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK
222335. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT
222336. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK
222337. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT
222338. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK
222339. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT
222340. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK
222341. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT
222342. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK
222343. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT
222344. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK
222345. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT
222346. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK
222347. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT
222348. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK
222349. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT
222350. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK
222351. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT
222352. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK
222353. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT
222354. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK
222355. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT
222356. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK
222357. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT
222358. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK
222359. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT
222360. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK
222361. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT
222362. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK
222363. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT
222364. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK
222365. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT
222366. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK
222367. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT
222368. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK
222369. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT
222370. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK
222371. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT
222372. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK
222373. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT
222374. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK
222375. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT
222376. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK
222377. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT
222378. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK
222379. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT
222380. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK
222381. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT
222382. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK
222383. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT
222384. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK
222385. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT
222386. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK
222387. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT
222388. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK
222389. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT
222390. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK
222391. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT
222392. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK
222393. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT
222394. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK
222395. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT
222396. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK
222397. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT
222398. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK
222399. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT
222400. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK
222401. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT
222402. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK
222403. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT
222404. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK
222405. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT
222406. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK
222407. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT
222408. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK
222409. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT
222410. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK
222411. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT
222412. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK
222413. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT
222414. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK
222415. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT
222416. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK
222417. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT
222418. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK
222419. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT
222420. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK
222421. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT
222422. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK
222423. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT
222424. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK
222425. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT
222426. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK
222427. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT
222428. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK
222429. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT
222430. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK
222431. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT
222432. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK
222433. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT
222434. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK
222435. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT
222436. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK
222437. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT
222438. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK
222439. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT
222440. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK
222441. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT
222442. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK
222443. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT
222444. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK
222445. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT
222446. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK
222447. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT
222448. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK
222449. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT
222450. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK
222451. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT
222452. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK
222453. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT
222454. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK
222455. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT
222456. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK
222457. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT
222458. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK
222459. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT
222460. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK
222461. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT
222462. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK
222463. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT
222464. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK
222465. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT
222466. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK
222467. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT
222468. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK
222469. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT
222470. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK
222471. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT
222472. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK
222473. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT
222474. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK
222475. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT
222476. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK
222477. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT
222478. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK
222479. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT
222480. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK
222481. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT
222482. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK
222483. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT
222484. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK
222485. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT
222486. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK
222487. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT
222488. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK
222489. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT
222490. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK
222491. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT
222492. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK
222493. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT
222494. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK
222495. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT
222496. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK
222497. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT
222498. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK
222499. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT
222500. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK
222501. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT
222502. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK
222503. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT
222504. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK
222505. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT
222506. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK
222507. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT
222508. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK
222509. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT
222510. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK
222511. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT
222512. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK
222513. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT
222514. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK
222515. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT
222516. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK
222517. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT
222518. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK
222519. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT
222520. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK
222521. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT
222522. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK
222523. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT
222524. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK
222525. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT
222526. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK
222527. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT
222528. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK
222529. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT
222530. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK
222531. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT
222532. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK
222533. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT
222534. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK
222535. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT
222536. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK
222537. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT
222538. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK
222539. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT
222540. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK
222541. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT
222542. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK
222543. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT
222544. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK
222545. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT
222546. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK
222547. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT
222548. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK
222549. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT
222550. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK
222551. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT
222552. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK
222553. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT
222554. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK
222555. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT
222556. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK
222557. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT
222558. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK
222559. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT
222560. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK
222561. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT
222562. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK
222563. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT
222564. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK
222565. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT
222566. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK
222567. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT
222568. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK
222569. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT
222570. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK
222571. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT
222572. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK
222573. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT
222574. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK
222575. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT
222576. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK
222577. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT
222578. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK
222579. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT
222580. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK
222581. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT
222582. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK
222583. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT
222584. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK
222585. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT
222586. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK
222587. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT
222588. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK
222589. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT
222590. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK
222591. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT
222592. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK
222593. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT
222594. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK
222595. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT
222596. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK
222597. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT
222598. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK
222599. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT
222600. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK
222601. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT
222602. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK
222603. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT
222604. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK
222605. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT
222606. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK
222607. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT
222608. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK
222609. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT
222610. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK
222611. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT
222612. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK
222613. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT
222614. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK
222615. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT
222616. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK
222617. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT
222618. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK
222619. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT
222620. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK
222621. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT
222622. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK
222623. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT
222624. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK
222625. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT
222626. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK
222627. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT
222628. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK
222629. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT
222630. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK
222631. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT
222632. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK
222633. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT
222634. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK
222635. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT
222636. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK
222637. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT
222638. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK
222639. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT
222640. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK
222641. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT
222642. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK
222643. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT
222644. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK
222645. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT
222646. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK
222647. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT
222648. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK
222649. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT
222650. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK
222651. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT
222652. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK
222653. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT
222654. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK
222655. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT
222656. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK
222657. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT
222658. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK
222659. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT
222660. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK
222661. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT
222662. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK
222663. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT
222664. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK
222665. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT
222666. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK
222667. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT
222668. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK
222669. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT
222670. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK
222671. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT
222672. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK
222673. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT
222674. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK
222675. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT
222676. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK
222677. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT
222678. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK
222679. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT
222680. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK
222681. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT
222682. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK
222683. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT
222684. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK
222685. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT
222686. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK
222687. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT
222688. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK
222689. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT
222690. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK
222691. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT
222692. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK
222693. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT
222694. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK
222695. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT
222696. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK
222697. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT
222698. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK
222699. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT
222700. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK
222701. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT
222702. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK
222703. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT
222704. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK
222705. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT
222706. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK
222707. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT
222708. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK
222709. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT
222710. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK
222711. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT
222712. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK
222713. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT
222714. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK
222715. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT
222716. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK
222717. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT
222718. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK
222719. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT
222720. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK
222721. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT
222722. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK
222723. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT
222724. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK
222725. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT
222726. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK
222727. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT
222728. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK
222729. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT
222730. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK
222731. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT
222732. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK
222733. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT
222734. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK
222735. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT
222736. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK
222737. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT
222738. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK
222739. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT
222740. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK
222741. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT
222742. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK
222743. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT
222744. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK
222745. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT
222746. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK
222747. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT
222748. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK
222749. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT
222750. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK
222751. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT
222752. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK
222753. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT
222754. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK
222755. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT
222756. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK
222757. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT
222758. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK
222759. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT
222760. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK
222761. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT
222762. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK
222763. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT
222764. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK
222765. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT
222766. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK
222767. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT
222768. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK
222769. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT
222770. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK
222771. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT
222772. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK
222773. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT
222774. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK
222775. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT
222776. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK
222777. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT
222778. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK
222779. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT
222780. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK
222781. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT
222782. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK
222783. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT
222784. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK
222785. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT
222786. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK
222787. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT
222788. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK
222789. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT
222790. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK
222791. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT
222792. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK
222793. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT
222794. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK
222795. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT
222796. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK
222797. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT
222798. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK
222799. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT
222800. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK
222801. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT
222802. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK
222803. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT
222804. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK
222805. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT
222806. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK
222807. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT
222808. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK
222809. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT
222810. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK
222811. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT
222812. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK
222813. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT
222814. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK
222815. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT
222816. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK
222817. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT
222818. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK
222819. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT
222820. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK
222821. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT
222822. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK
222823. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT
222824. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK
222825. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT
222826. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK
222827. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT
222828. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK
222829. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT
222830. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK
222831. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT
222832. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK
222833. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT
222834. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK
222835. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT
222836. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK
222837. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT
222838. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK
222839. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT
222840. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK
222841. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT
222842. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK
222843. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT
222844. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK
222845. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT
222846. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK
222847. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT
222848. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK
222849. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT
222850. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK
222851. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT
222852. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK
222853. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT
222854. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK
222855. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT
222856. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK
222857. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT
222858. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK
222859. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT
222860. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK
222861. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT
222862. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK
222863. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT
222864. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK
222865. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT
222866. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK
222867. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT
222868. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK
222869. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT
222870. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK
222871. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT
222872. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK
222873. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT
222874. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK
222875. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT
222876. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK
222877. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT
222878. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK
222879. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT
222880. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK
222881. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT
222882. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK
222883. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT
222884. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK
222885. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT
222886. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK
222887. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT
222888. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK
222889. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT
222890. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK
222891. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT
222892. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK
222893. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT
222894. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK
222895. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT
222896. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK
222897. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT
222898. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK
222899. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT
222900. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK
222901. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT
222902. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK
222903. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT
222904. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK
222905. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT
222906. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK
222907. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT
222908. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK
222909. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT
222910. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK
222911. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT
222912. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK
222913. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT
222914. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK
222915. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT
222916. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK
222917. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT
222918. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK
222919. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT
222920. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK
222921. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT
222922. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK
222923. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT
222924. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK
222925. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT
222926. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK
222927. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT
222928. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK
222929. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT
222930. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK
222931. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT
222932. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK
222933. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT
222934. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK
222935. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT
222936. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK
222937. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT
222938. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK
222939. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT
222940. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK
222941. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT
222942. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK
222943. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT
222944. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK
222945. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT
222946. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK
222947. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT
222948. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK
222949. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT
222950. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK
222951. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT
222952. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK
222953. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT
222954. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK
222955. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT
222956. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK
222957. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT
222958. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK
222959. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT
222960. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK
222961. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT
222962. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK
222963. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT
222964. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK
222965. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT
222966. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK
222967. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT
222968. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK
222969. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT
222970. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK
222971. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT
222972. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK
222973. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT
222974. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK
222975. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT
222976. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK
222977. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT
222978. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK
222979. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT
222980. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK
222981. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT
222982. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK
222983. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT
222984. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK
222985. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT
222986. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK
222987. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT
222988. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK
222989. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT
222990. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK
222991. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT
222992. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK
222993. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT
222994. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK
222995. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT
222996. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK
222997. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT
222998. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK
222999. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT
223000. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK
223001. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT
223002. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK
223003. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT
223004. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK
223005. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT
223006. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK
223007. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT
223008. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK
223009. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT
223010. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK
223011. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT
223012. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK
223013. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT
223014. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK
223015. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT
223016. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK
223017. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT
223018. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK
223019. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT
223020. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK
223021. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT
223022. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK
223023. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT
223024. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK
223025. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT
223026. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK
223027. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT
223028. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK
223029. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT
223030. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK
223031. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT
223032. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK
223033. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT
223034. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK
223035. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT
223036. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK
223037. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT
223038. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK
223039. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT
223040. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK
223041. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT
223042. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK
223043. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT
223044. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK
223045. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT
223046. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK
223047. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT
223048. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK
223049. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT
223050. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK
223051. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT
223052. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK
223053. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT
223054. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK
223055. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT
223056. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK
223057. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT
223058. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK
223059. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT
223060. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK
223061. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT
223062. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK
223063. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT
223064. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK
223065. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT
223066. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK
223067. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT
223068. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK
223069. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT
223070. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK
223071. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT
223072. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK
223073. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT
223074. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK
223075. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT
223076. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK
223077. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT
223078. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK
223079. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT
223080. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK
223081. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT
223082. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK
223083. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT
223084. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK
223085. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT
223086. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK
223087. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT
223088. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK
223089. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT
223090. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK
223091. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT
223092. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK
223093. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT
223094. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK
223095. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT
223096. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK
223097. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT
223098. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK
223099. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT
223100. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK
223101. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT
223102. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK
223103. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT
223104. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK
223105. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT
223106. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK
223107. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT
223108. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK
223109. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT
223110. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK
223111. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT
223112. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK
223113. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT
223114. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK
223115. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT
223116. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK
223117. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT
223118. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK
223119. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT
223120. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK
223121. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT
223122. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK
223123. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT
223124. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK
223125. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT
223126. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK
223127. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT
223128. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK
223129. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT
223130. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK
223131. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT
223132. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK
223133. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT
223134. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK
223135. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT
223136. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK
223137. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT
223138. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK
223139. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT
223140. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK
223141. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT
223142. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK
223143. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT
223144. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK
223145. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT
223146. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK
223147. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT
223148. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK
223149. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT
223150. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK
223151. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT
223152. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK
223153. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT
223154. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK
223155. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT
223156. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK
223157. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT
223158. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK
223159. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT
223160. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK
223161. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT
223162. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK
223163. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT
223164. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK
223165. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT
223166. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK
223167. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT
223168. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK
223169. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT
223170. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK
223171. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT
223172. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK
223173. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT
223174. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK
223175. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT
223176. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK
223177. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT
223178. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK
223179. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT
223180. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK
223181. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT
223182. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK
223183. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT
223184. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK
223185. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT
223186. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK
223187. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT
223188. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK
223189. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT
223190. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK
223191. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT
223192. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK
223193. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT
223194. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK
223195. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT
223196. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK
223197. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT
223198. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK
223199. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT
223200. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK
223201. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT
223202. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK
223203. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT
223204. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK
223205. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT
223206. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK
223207. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT
223208. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK
223209. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT
223210. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK
223211. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT
223212. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK
223213. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT
223214. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK
223215. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT
223216. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK
223217. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT
223218. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK
223219. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT
223220. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK
223221. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT
223222. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK
223223. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT
223224. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK
223225. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT
223226. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK
223227. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT
223228. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK
223229. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT
223230. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK
223231. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT
223232. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK
223233. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT
223234. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK
223235. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT
223236. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK
223237. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT
223238. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK
223239. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT
223240. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK
223241. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT
223242. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK
223243. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT
223244. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK
223245. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT
223246. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK
223247. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT
223248. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK
223249. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT
223250. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK
223251. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT
223252. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK
223253. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT
223254. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK
223255. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT
223256. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK
223257. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT
223258. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK
223259. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT
223260. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK
223261. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT
223262. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK
223263. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT
223264. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK
223265. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT
223266. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK
223267. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT
223268. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK
223269. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT
223270. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK
223271. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT
223272. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK
223273. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT
223274. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK
223275. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT
223276. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK
223277. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT
223278. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK
223279. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT
223280. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK
223281. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT
223282. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK
223283. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT
223284. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK
223285. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT
223286. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK
223287. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT
223288. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK
223289. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT
223290. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK
223291. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT
223292. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK
223293. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT
223294. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK
223295. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT
223296. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK
223297. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT
223298. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK
223299. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT
223300. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK
223301. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT
223302. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK
223303. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT
223304. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK
223305. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT
223306. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK
223307. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT
223308. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK
223309. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT
223310. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK
223311. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT
223312. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK
223313. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT
223314. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK
223315. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT
223316. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK
223317. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT
223318. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK
223319. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT
223320. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK
223321. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT
223322. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK
223323. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT
223324. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK
223325. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT
223326. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK
223327. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT
223328. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK
223329. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT
223330. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK
223331. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT
223332. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK
223333. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT
223334. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK
223335. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT
223336. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK
223337. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT
223338. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK
223339. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT
223340. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK
223341. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT
223342. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK
223343. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT
223344. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK
223345. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT
223346. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK
223347. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT
223348. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK
223349. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT
223350. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK
223351. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT
223352. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK
223353. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT
223354. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK
223355. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT
223356. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK
223357. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT
223358. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK
223359. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT
223360. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK
223361. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT
223362. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK
223363. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT
223364. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK
223365. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT
223366. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK
223367. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT
223368. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK
223369. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT
223370. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK
223371. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT
223372. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK
223373. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT
223374. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK
223375. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT
223376. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK
223377. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT
223378. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK
223379. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT
223380. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK
223381. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT
223382. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK
223383. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT
223384. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK
223385. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT
223386. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK
223387. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT
223388. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK
223389. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT
223390. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK
223391. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT
223392. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK
223393. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT
223394. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK
223395. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT
223396. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK
223397. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT
223398. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK
223399. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT
223400. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK
223401. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT
223402. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK
223403. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT
223404. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK
223405. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT
223406. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK
223407. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT
223408. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK
223409. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT
223410. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK
223411. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT
223412. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK
223413. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT
223414. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK
223415. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT
223416. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK
223417. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT
223418. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK
223419. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT
223420. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK
223421. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT
223422. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK
223423. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT
223424. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK
223425. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT
223426. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK
223427. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT
223428. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK
223429. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT
223430. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK
223431. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT
223432. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK
223433. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT
223434. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK
223435. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT
223436. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK
223437. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT
223438. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK
223439. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT
223440. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK
223441. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT
223442. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK
223443. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT
223444. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK
223445. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT
223446. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK
223447. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT
223448. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK
223449. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT
223450. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK
223451. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT
223452. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK
223453. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT
223454. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK
223455. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT
223456. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK
223457. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT
223458. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK
223459. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT
223460. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK
223461. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT
223462. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK
223463. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT
223464. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK
223465. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT
223466. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK
223467. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT
223468. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK
223469. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT
223470. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK
223471. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT
223472. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK
223473. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT
223474. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK
223475. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT
223476. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK
223477. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT
223478. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK
223479. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT
223480. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK
223481. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT
223482. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK
223483. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT
223484. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK
223485. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT
223486. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK
223487. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT
223488. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK
223489. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT
223490. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK
223491. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT
223492. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK
223493. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT
223494. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK
223495. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT
223496. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK
223497. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT
223498. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK
223499. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT
223500. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK
223501. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT
223502. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK
223503. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT
223504. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK
223505. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT
223506. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK
223507. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT
223508. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK
223509. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT
223510. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK
223511. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT
223512. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK
223513. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT
223514. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK
223515. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT
223516. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK
223517. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT
223518. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK
223519. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT
223520. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK
223521. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT
223522. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK
223523. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT
223524. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK
223525. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT
223526. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK
223527. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT
223528. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK
223529. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT
223530. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK
223531. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT
223532. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK
223533. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT
223534. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK
223535. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT
223536. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK
223537. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT
223538. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK
223539. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT
223540. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK
223541. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT
223542. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK
223543. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT
223544. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK
223545. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT
223546. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK
223547. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT
223548. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK
223549. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT
223550. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK
223551. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT
223552. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK
223553. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT
223554. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK
223555. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT
223556. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK
223557. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT
223558. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK
223559. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT
223560. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK
223561. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT
223562. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK
223563. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT
223564. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK
223565. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT
223566. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK
223567. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT
223568. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK
223569. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT
223570. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK
223571. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT
223572. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK
223573. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT
223574. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK
223575. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT
223576. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK
223577. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT
223578. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK
223579. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT
223580. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK
223581. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT
223582. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK
223583. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT
223584. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK
223585. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT
223586. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK
223587. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT
223588. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK
223589. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT
223590. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK
223591. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT
223592. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK
223593. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT
223594. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK
223595. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT
223596. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK
223597. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT
223598. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK
223599. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT
223600. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK
223601. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT
223602. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK
223603. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT
223604. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK
223605. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT
223606. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK
223607. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT
223608. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK
223609. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT
223610. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK
223611. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT
223612. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK
223613. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT
223614. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK
223615. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT
223616. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK
223617. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT
223618. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK
223619. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT
223620. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK
223621. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT
223622. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK
223623. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT
223624. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK
223625. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT
223626. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK
223627. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT
223628. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK
223629. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT
223630. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK
223631. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT
223632. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK
223633. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT
223634. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK
223635. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT
223636. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK
223637. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT
223638. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK
223639. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT
223640. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK
223641. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT
223642. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK
223643. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT
223644. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK
223645. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT
223646. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK
223647. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT
223648. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK
223649. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT
223650. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK
223651. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT
223652. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK
223653. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT
223654. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK
223655. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT
223656. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK
223657. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT
223658. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK
223659. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT
223660. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK
223661. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT
223662. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK
223663. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT
223664. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK
223665. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT
223666. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK
223667. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT
223668. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK
223669. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT
223670. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK
223671. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT
223672. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK
223673. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT
223674. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK
223675. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT
223676. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK
223677. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT
223678. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK
223679. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT
223680. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK
223681. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT
223682. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK
223683. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT
223684. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK
223685. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT
223686. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK
223687. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT
223688. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK
223689. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT
223690. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK
223691. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT
223692. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK
223693. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT
223694. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK
223695. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT
223696. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK
223697. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT
223698. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK
223699. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT
223700. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK
223701. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT
223702. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK
223703. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT
223704. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK
223705. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT
223706. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK
223707. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT
223708. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK
223709. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT
223710. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK
223711. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT
223712. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK
223713. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT
223714. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK
223715. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT
223716. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK
223717. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT
223718. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK
223719. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT
223720. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK
223721. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT
223722. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK
223723. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT
223724. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK
223725. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT
223726. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK
223727. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT
223728. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK
223729. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT
223730. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK
223731. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT
223732. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK
223733. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT
223734. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK
223735. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT
223736. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK
223737. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT
223738. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK
223739. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT
223740. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK
223741. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT
223742. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK
223743. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT
223744. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK
223745. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT
223746. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK
223747. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT
223748. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK
223749. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT
223750. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK
223751. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT
223752. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK
223753. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT
223754. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK
223755. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT
223756. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK
223757. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT
223758. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK
223759. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT
223760. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK
223761. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT
223762. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK
223763. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT
223764. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK
223765. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT
223766. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK
223767. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT
223768. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK
223769. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT
223770. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK
223771. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT
223772. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK
223773. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT
223774. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK
223775. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT
223776. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK
223777. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT
223778. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK
223779. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT
223780. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK
223781. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT
223782. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK
223783. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT
223784. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK
223785. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT
223786. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK
223787. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT
223788. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK
223789. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT
223790. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK
223791. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT
223792. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK
223793. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT
223794. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK
223795. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT
223796. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK
223797. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT
223798. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK
223799. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT
223800. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK
223801. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT
223802. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK
223803. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT
223804. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK
223805. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT
223806. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK
223807. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT
223808. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK
223809. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT
223810. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK
223811. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT
223812. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK
223813. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT
223814. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK
223815. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT
223816. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK
223817. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT
223818. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK
223819. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT
223820. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK
223821. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT
223822. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK
223823. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT
223824. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK
223825. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT
223826. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK
223827. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT
223828. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK
223829. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT
223830. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK
223831. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT
223832. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK
223833. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT
223834. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK
223835. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT
223836. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK
223837. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT
223838. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK
223839. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT
223840. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK
223841. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT
223842. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK
223843. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT
223844. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK
223845. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT
223846. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK
223847. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT
223848. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK
223849. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT
223850. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK
223851. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT
223852. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK
223853. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT
223854. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK
223855. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT
223856. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK
223857. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT
223858. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK
223859. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT
223860. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK
223861. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT
223862. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK
223863. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT
223864. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK
223865. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT
223866. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK
223867. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT
223868. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK
223869. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT
223870. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK
223871. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT
223872. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK
223873. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT
223874. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK
223875. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT
223876. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK
223877. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT
223878. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK
223879. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT
223880. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK
223881. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT
223882. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK
223883. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT
223884. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK
223885. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT
223886. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK
223887. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT
223888. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK
223889. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT
223890. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK
223891. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT
223892. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK
223893. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT
223894. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK
223895. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT
223896. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK
223897. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT
223898. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK
223899. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT
223900. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK
223901. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT
223902. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK
223903. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT
223904. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK
223905. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT
223906. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK
223907. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT
223908. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK
223909. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT
223910. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK
223911. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT
223912. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK
223913. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT
223914. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK
223915. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT
223916. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK
223917. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT
223918. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK
223919. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT
223920. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK
223921. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT
223922. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK
223923. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT
223924. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK
223925. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT
223926. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK
223927. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT
223928. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK
223929. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT
223930. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK
223931. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT
223932. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK
223933. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT
223934. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK
223935. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT
223936. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK
223937. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT
223938. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK
223939. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT
223940. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK
223941. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT
223942. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK
223943. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT
223944. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK
223945. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT
223946. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK
223947. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT
223948. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK
223949. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT
223950. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK
223951. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT
223952. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK
223953. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT
223954. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK
223955. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT
223956. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK
223957. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT
223958. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK
223959. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT
223960. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK
223961. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT
223962. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK
223963. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT
223964. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK
223965. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT
223966. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK
223967. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT
223968. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK
223969. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT
223970. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK
223971. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT
223972. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK
223973. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT
223974. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK
223975. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT
223976. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK
223977. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT
223978. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK
223979. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT
223980. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK
223981. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT
223982. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK
223983. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT
223984. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK
223985. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT
223986. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK
223987. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT
223988. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK
223989. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT
223990. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK
223991. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT
223992. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK
223993. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT
223994. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK
223995. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT
223996. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK
223997. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT
223998. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK
223999. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT
224000. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK
224001. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT
224002. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK
224003. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT
224004. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK
224005. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT
224006. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK
224007. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT
224008. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK
224009. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT
224010. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK
224011. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT
224012. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK
224013. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT
224014. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK
224015. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT
224016. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK
224017. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT
224018. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK
224019. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT
224020. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK
224021. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT
224022. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK
224023. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT
224024. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK
224025. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT
224026. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK
224027. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT
224028. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK
224029. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT
224030. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK
224031. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT
224032. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK
224033. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT
224034. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK
224035. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT
224036. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK
224037. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT
224038. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK
224039. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT
224040. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK
224041. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT
224042. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK
224043. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT
224044. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK
224045. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT
224046. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK
224047. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT
224048. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK
224049. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT
224050. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK
224051. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT
224052. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK
224053. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT
224054. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK
224055. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT
224056. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK
224057. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT
224058. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK
224059. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT
224060. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK
224061. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT
224062. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK
224063. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT
224064. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK
224065. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT
224066. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK
224067. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT
224068. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK
224069. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT
224070. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK
224071. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT
224072. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK
224073. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT
224074. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK
224075. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT
224076. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK
224077. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT
224078. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK
224079. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT
224080. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK
224081. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT
224082. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK
224083. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT
224084. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK
224085. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT
224086. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK
224087. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT
224088. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK
224089. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT
224090. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK
224091. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT
224092. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK
224093. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT
224094. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK
224095. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT
224096. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK
224097. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT
224098. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK
224099. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT
224100. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK
224101. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT
224102. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK
224103. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT
224104. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK
224105. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT
224106. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK
224107. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT
224108. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK
224109. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT
224110. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK
224111. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT
224112. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK
224113. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT
224114. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK
224115. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT
224116. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK
224117. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT
224118. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK
224119. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT
224120. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK
224121. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT
224122. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK
224123. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT
224124. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK
224125. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT
224126. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK
224127. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT
224128. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK
224129. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT
224130. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK
224131. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT
224132. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK
224133. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT
224134. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK
224135. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT
224136. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK
224137. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT
224138. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK
224139. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT
224140. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK
224141. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT
224142. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK
224143. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT
224144. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK
224145. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT
224146. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK
224147. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT
224148. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK
224149. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT
224150. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK
224151. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT
224152. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK
224153. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT
224154. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK
224155. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT
224156. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK
224157. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT
224158. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK
224159. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT
224160. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK
224161. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT
224162. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK
224163. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT
224164. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK
224165. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT
224166. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK
224167. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT
224168. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK
224169. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT
224170. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK
224171. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT
224172. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK
224173. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT
224174. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK
224175. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT
224176. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK
224177. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT
224178. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK
224179. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT
224180. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK
224181. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT
224182. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK
224183. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT
224184. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK
224185. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT
224186. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK
224187. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT
224188. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK
224189. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT
224190. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK
224191. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT
224192. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK
224193. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT
224194. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK
224195. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT
224196. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK
224197. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT
224198. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK
224199. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT
224200. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK
224201. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT
224202. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK
224203. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT
224204. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK
224205. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT
224206. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK
224207. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT
224208. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK
224209. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT
224210. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK
224211. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT
224212. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK
224213. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT
224214. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK
224215. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT
224216. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK
224217. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT
224218. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK
224219. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT
224220. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK
224221. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT
224222. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK
224223. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT
224224. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK
224225. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT
224226. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK
224227. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT
224228. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK
224229. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT
224230. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK
224231. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT
224232. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK
224233. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT
224234. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK
224235. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT
224236. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK
224237. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT
224238. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK
224239. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT
224240. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK
224241. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT
224242. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK
224243. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT
224244. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK
224245. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT
224246. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK
224247. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT
224248. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK
224249. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT
224250. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK
224251. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT
224252. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK
224253. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT
224254. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK
224255. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT
224256. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK
224257. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT
224258. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK
224259. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT
224260. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK
224261. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT
224262. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK
224263. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT
224264. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK
224265. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT
224266. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK
224267. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT
224268. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK
224269. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT
224270. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK
224271. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT
224272. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK
224273. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT
224274. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK
224275. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT
224276. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK
224277. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT
224278. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK
224279. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT
224280. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK
224281. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT
224282. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK
224283. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT
224284. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK
224285. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT
224286. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK
224287. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT
224288. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK
224289. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT
224290. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK
224291. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT
224292. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK
224293. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT
224294. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK
224295. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT
224296. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK
224297. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT
224298. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK
224299. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT
224300. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK
224301. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT
224302. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK
224303. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT
224304. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK
224305. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT
224306. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK
224307. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT
224308. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK
224309. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT
224310. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK
224311. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT
224312. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK
224313. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT
224314. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK
224315. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT
224316. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK
224317. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT
224318. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK
224319. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT
224320. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK
224321. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT
224322. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK
224323. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT
224324. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK
224325. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT
224326. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK
224327. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT
224328. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK
224329. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT
224330. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK
224331. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT
224332. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK
224333. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT
224334. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK
224335. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT
224336. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK
224337. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT
224338. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK
224339. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT
224340. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK
224341. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT
224342. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK
224343. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT
224344. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK
224345. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT
224346. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK
224347. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT
224348. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK
224349. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT
224350. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK
224351. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT
224352. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK
224353. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT
224354. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK
224355. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT
224356. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK
224357. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT
224358. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK
224359. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT
224360. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK
224361. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT
224362. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK
224363. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT
224364. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK
224365. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT
224366. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK
224367. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT
224368. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK
224369. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT
224370. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK
224371. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT
224372. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK
224373. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT
224374. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK
224375. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT
224376. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK
224377. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT
224378. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK
224379. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT
224380. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK
224381. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT
224382. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK
224383. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT
224384. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK
224385. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT
224386. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK
224387. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT
224388. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK
224389. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT
224390. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK
224391. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT
224392. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK
224393. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT
224394. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK
224395. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT
224396. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK
224397. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT
224398. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK
224399. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT
224400. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK
224401. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT
224402. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK
224403. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT
224404. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK
224405. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT
224406. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK
224407. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT
224408. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK
224409. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT
224410. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK
224411. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT
224412. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK
224413. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT
224414. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK
224415. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT
224416. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK
224417. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT
224418. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK
224419. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT
224420. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK
224421. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT
224422. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK
224423. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT
224424. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK
224425. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT
224426. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK
224427. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT
224428. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK
224429. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT
224430. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK
224431. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT
224432. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK
224433. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT
224434. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK
224435. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT
224436. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK
224437. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT
224438. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK
224439. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT
224440. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK
224441. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT
224442. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK
224443. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT
224444. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK
224445. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT
224446. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK
224447. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT
224448. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK
224449. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT
224450. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK
224451. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT
224452. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK
224453. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT
224454. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK
224455. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT
224456. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK
224457. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT
224458. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK
224459. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT
224460. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK
224461. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT
224462. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK
224463. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT
224464. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK
224465. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT
224466. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK
224467. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT
224468. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK
224469. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT
224470. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK
224471. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT
224472. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK
224473. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT
224474. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK
224475. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT
224476. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK
224477. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT
224478. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK
224479. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT
224480. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK
224481. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT
224482. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK
224483. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT
224484. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK
224485. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT
224486. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK
224487. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT
224488. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK
224489. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT
224490. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK
224491. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT
224492. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK
224493. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT
224494. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK
224495. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT
224496. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK
224497. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT
224498. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK
224499. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT
224500. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK
224501. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT
224502. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK
224503. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT
224504. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK
224505. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT
224506. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK
224507. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT
224508. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK
224509. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT
224510. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK
224511. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT
224512. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK
224513. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT
224514. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK
224515. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT
224516. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK
224517. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT
224518. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK
224519. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT
224520. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK
224521. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT
224522. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK
224523. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT
224524. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK
224525. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT
224526. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK
224527. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT
224528. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK
224529. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT
224530. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK
224531. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT
224532. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK
224533. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT
224534. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK
224535. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT
224536. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK
224537. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT
224538. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK
224539. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT
224540. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK
224541. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT
224542. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK
224543. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT
224544. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK
224545. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT
224546. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK
224547. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT
224548. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK
224549. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT
224550. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK
224551. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT
224552. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK
224553. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT
224554. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK
224555. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT
224556. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK
224557. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT
224558. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK
224559. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT
224560. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK
224561. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT
224562. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK
224563. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT
224564. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK
224565. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT
224566. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK
224567. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT
224568. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK
224569. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT
224570. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK
224571. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT
224572. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK
224573. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT
224574. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK
224575. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT
224576. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK
224577. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT
224578. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK
224579. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT
224580. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK
224581. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT
224582. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK
224583. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT
224584. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK
224585. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT
224586. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK
224587. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT
224588. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK
224589. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT
224590. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK
224591. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT
224592. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK
224593. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT
224594. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK
224595. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT
224596. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK
224597. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT
224598. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK
224599. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT
224600. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK
224601. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT
224602. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK
224603. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT
224604. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK
224605. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT
224606. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK
224607. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT
224608. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK
224609. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT
224610. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK
224611. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT
224612. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK
224613. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT
224614. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK
224615. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT
224616. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK
224617. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT
224618. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK
224619. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT
224620. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK
224621. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT
224622. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK
224623. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT
224624. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK
224625. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT
224626. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK
224627. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT
224628. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK
224629. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT
224630. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK
224631. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT
224632. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK
224633. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT
224634. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK
224635. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT
224636. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK
224637. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT
224638. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK
224639. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT
224640. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK
224641. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT
224642. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK
224643. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT
224644. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK
224645. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT
224646. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK
224647. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT
224648. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK
224649. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT
224650. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK
224651. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT
224652. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK
224653. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT
224654. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK
224655. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT
224656. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK
224657. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT
224658. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK
224659. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT
224660. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK
224661. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT
224662. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK
224663. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT
224664. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK
224665. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT
224666. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK
224667. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT
224668. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK
224669. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT
224670. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
224671. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
224672. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK
224673. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT
224674. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK
224675. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT
224676. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK
224677. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT
224678. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK
224679. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT
224680. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK
224681. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT
224682. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK
224683. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT
224684. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK
224685. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT
224686. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK
224687. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT
224688. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK
224689. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT
224690. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK
224691. DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT
224692. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK
224693. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT
224694. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK
224695. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT
224696. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK
224697. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT
224698. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK
224699. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT
224700. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK
224701. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT
224702. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK
224703. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT
224704. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK
224705. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT
224706. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK
224707. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT
224708. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
224709. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
224710. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
224711. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
224712. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
224713. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
224714. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
224715. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
224716. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
224717. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
224718. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
224719. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
224720. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
224721. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
224722. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
224723. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
224724. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
224725. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
224726. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
224727. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
224728. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
224729. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
224730. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
224731. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
224732. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
224733. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
224734. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
224735. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
224736. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
224737. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
224738. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
224739. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
224740. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
224741. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
224742. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
224743. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
224744. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
224745. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
224746. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
224747. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
224748. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
224749. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
224750. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
224751. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
224752. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
224753. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
224754. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
224755. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
224756. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
224757. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
224758. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
224759. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
224760. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
224761. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
224762. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
224763. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
224764. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
224765. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
224766. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
224767. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
224768. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
224769. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
224770. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
224771. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
224772. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
224773. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
224774. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
224775. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
224776. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
224777. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
224778. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
224779. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
224780. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
224781. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
224782. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
224783. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
224784. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
224785. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
224786. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
224787. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
224788. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
224789. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
224790. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
224791. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
224792. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
224793. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
224794. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
224795. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
224796. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
224797. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
224798. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
224799. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
224800. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
224801. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
224802. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
224803. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
224804. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
224805. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
224806. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
224807. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
224808. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
224809. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
224810. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
224811. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
224812. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
224813. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
224814. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
224815. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
224816. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
224817. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
224818. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
224819. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
224820. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
224821. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
224822. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
224823. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
224824. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
224825. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
224826. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
224827. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
224828. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
224829. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
224830. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
224831. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
224832. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
224833. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
224834. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
224835. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
224836. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
224837. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
224838. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
224839. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
224840. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
224841. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
224842. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
224843. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
224844. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
224845. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
224846. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
224847. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
224848. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
224849. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
224850. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
224851. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
224852. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
224853. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
224854. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
224855. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
224856. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
224857. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
224858. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
224859. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
224860. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
224861. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
224862. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
224863. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
224864. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
224865. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
224866. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
224867. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
224868. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
224869. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
224870. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
224871. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
224872. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
224873. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
224874. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
224875. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
224876. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
224877. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
224878. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
224879. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
224880. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
224881. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
224882. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
224883. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
224884. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
224885. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
224886. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
224887. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
224888. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
224889. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
224890. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
224891. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
224892. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
224893. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
224894. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
224895. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
224896. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
224897. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
224898. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
224899. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
224900. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
224901. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
224902. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
224903. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
224904. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
224905. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
224906. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
224907. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
224908. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
224909. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
224910. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
224911. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
224912. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
224913. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
224914. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
224915. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
224916. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
224917. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
224918. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
224919. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
224920. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
224921. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
224922. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
224923. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
224924. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
224925. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
224926. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
224927. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
224928. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
224929. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
224930. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
224931. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
224932. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
224933. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
224934. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
224935. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
224936. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
224937. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
224938. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
224939. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
224940. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
224941. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
224942. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
224943. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
224944. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
224945. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
224946. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
224947. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
224948. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
224949. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
224950. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK
224951. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
224952. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
224953. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
224954. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
224955. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
224956. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
224957. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
224958. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
224959. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
224960. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
224961. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
224962. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
224963. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
224964. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
224965. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
224966. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
224967. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
224968. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
224969. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
224970. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
224971. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
224972. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
224973. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
224974. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
224975. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
224976. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
224977. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
224978. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK
224979. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
224980. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
224981. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
224982. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
224983. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
224984. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK
224985. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT
224986. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
224987. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
224988. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
224989. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
224990. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
224991. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
224992. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
224993. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
224994. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
224995. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
224996. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
224997. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
224998. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
224999. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
225000. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
225001. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
225002. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
225003. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
225004. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
225005. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
225006. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
225007. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
225008. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
225009. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
225010. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
225011. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
225012. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
225013. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
225014. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
225015. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
225016. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
225017. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
225018. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
225019. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
225020. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
225021. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
225022. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
225023. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
225024. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
225025. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
225026. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
225027. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
225028. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
225029. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
225030. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
225031. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
225032. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
225033. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
225034. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
225035. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
225036. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
225037. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
225038. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
225039. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
225040. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
225041. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
225042. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
225043. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
225044. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
225045. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
225046. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
225047. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
225048. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
225049. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
225050. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
225051. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
225052. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
225053. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
225054. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
225055. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
225056. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
225057. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
225058. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
225059. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
225060. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
225061. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
225062. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
225063. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
225064. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
225065. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
225066. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
225067. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
225068. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
225069. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
225070. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
225071. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
225072. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
225073. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
225074. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
225075. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
225076. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
225077. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
225078. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
225079. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
225080. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
225081. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
225082. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
225083. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
225084. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
225085. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
225086. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
225087. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
225088. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
225089. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
225090. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
225091. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
225092. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
225093. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
225094. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
225095. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
225096. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
225097. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
225098. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
225099. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
225100. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
225101. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
225102. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
225103. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
225104. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
225105. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
225106. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
225107. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
225108. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
225109. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
225110. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
225111. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
225112. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
225113. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
225114. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
225115. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
225116. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
225117. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
225118. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
225119. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
225120. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
225121. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
225122. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
225123. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
225124. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
225125. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
225126. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
225127. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
225128. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
225129. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
225130. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
225131. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
225132. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
225133. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
225134. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
225135. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
225136. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
225137. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
225138. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
225139. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
225140. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
225141. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
225142. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
225143. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
225144. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
225145. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
225146. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
225147. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
225148. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
225149. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
225150. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
225151. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
225152. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
225153. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
225154. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
225155. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
225156. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
225157. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
225158. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
225159. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
225160. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
225161. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
225162. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
225163. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
225164. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
225165. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
225166. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
225167. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
225168. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
225169. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
225170. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
225171. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
225172. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
225173. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
225174. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
225175. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
225176. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
225177. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
225178. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
225179. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
225180. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
225181. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
225182. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
225183. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
225184. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
225185. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
225186. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
225187. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
225188. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
225189. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
225190. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
225191. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
225192. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
225193. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
225194. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
225195. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
225196. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
225197. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
225198. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
225199. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
225200. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
225201. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
225202. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
225203. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
225204. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
225205. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
225206. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
225207. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
225208. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
225209. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
225210. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
225211. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
225212. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
225213. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
225214. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
225215. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
225216. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
225217. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
225218. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
225219. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
225220. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
225221. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
225222. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
225223. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
225224. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
225225. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
225226. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
225227. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
225228. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
225229. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
225230. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
225231. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
225232. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
225233. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
225234. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
225235. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
225236. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
225237. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
225238. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
225239. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
225240. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
225241. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
225242. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
225243. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
225244. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
225245. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
225246. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
225247. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
225248. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
225249. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
225250. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
225251. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
225252. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
225253. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
225254. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
225255. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
225256. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
225257. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
225258. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
225259. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
225260. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
225261. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
225262. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
225263. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
225264. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
225265. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
225266. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
225267. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
225268. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
225269. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
225270. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
225271. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
225272. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
225273. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
225274. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
225275. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
225276. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
225277. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
225278. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
225279. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
225280. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
225281. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
225282. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
225283. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
225284. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
225285. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
225286. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
225287. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
225288. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
225289. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
225290. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
225291. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
225292. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
225293. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
225294. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
225295. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
225296. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
225297. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
225298. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
225299. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
225300. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
225301. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
225302. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
225303. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
225304. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
225305. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
225306. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
225307. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
225308. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
225309. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
225310. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
225311. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
225312. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
225313. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
225314. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
225315. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
225316. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
225317. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
225318. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
225319. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
225320. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
225321. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
225322. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
225323. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
225324. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
225325. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
225326. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
225327. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
225328. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
225329. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
225330. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
225331. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
225332. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
225333. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
225334. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
225335. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
225336. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
225337. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
225338. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
225339. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
225340. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
225341. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
225342. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
225343. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
225344. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
225345. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
225346. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
225347. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
225348. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
225349. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
225350. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
225351. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
225352. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
225353. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
225354. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
225355. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
225356. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
225357. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
225358. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
225359. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
225360. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
225361. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
225362. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
225363. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
225364. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
225365. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
225366. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
225367. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
225368. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
225369. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
225370. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
225371. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
225372. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK
225373. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT
225374. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK
225375. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT
225376. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK
225377. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT
225378. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK
225379. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT
225380. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK
225381. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT
225382. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK
225383. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT
225384. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK
225385. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT
225386. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK
225387. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT
225388. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
225389. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
225390. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
225391. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
225392. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
225393. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
225394. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
225395. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
225396. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
225397. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
225398. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
225399. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
225400. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
225401. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
225402. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
225403. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
225404. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
225405. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
225406. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
225407. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
225408. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
225409. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
225410. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
225411. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
225412. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
225413. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
225414. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
225415. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
225416. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
225417. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
225418. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
225419. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
225420. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
225421. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
225422. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
225423. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
225424. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
225425. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
225426. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
225427. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
225428. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
225429. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
225430. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
225431. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
225432. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
225433. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
225434. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
225435. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
225436. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
225437. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
225438. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
225439. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
225440. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
225441. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
225442. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
225443. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
225444. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
225445. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
225446. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
225447. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
225448. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
225449. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
225450. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
225451. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
225452. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
225453. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
225454. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
225455. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
225456. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
225457. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
225458. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
225459. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
225460. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
225461. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
225462. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
225463. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
225464. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
225465. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
225466. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
225467. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
225468. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
225469. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
225470. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
225471. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
225472. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
225473. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
225474. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
225475. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
225476. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
225477. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
225478. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
225479. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
225480. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
225481. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
225482. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
225483. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
225484. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
225485. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
225486. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
225487. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
225488. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
225489. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
225490. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
225491. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
225492. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
225493. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
225494. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
225495. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
225496. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
225497. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
225498. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
225499. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
225500. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
225501. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
225502. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
225503. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
225504. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
225505. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
225506. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
225507. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
225508. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
225509. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
225510. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
225511. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
225512. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
225513. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
225514. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
225515. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
225516. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
225517. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
225518. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
225519. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
225520. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
225521. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
225522. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
225523. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
225524. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
225525. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
225526. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
225527. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
225528. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
225529. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
225530. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
225531. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
225532. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
225533. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
225534. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
225535. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
225536. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
225537. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
225538. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
225539. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
225540. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
225541. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
225542. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
225543. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
225544. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
225545. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
225546. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
225547. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
225548. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
225549. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
225550. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
225551. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
225552. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
225553. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
225554. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
225555. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
225556. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
225557. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
225558. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
225559. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
225560. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
225561. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
225562. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
225563. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
225564. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
225565. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
225566. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
225567. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
225568. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
225569. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
225570. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
225571. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
225572. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
225573. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
225574. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
225575. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
225576. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
225577. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
225578. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
225579. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
225580. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
225581. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
225582. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
225583. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
225584. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
225585. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
225586. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
225587. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
225588. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
225589. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
225590. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
225591. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
225592. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
225593. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
225594. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
225595. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
225596. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
225597. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
225598. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
225599. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
225600. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
225601. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
225602. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
225603. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
225604. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
225605. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
225606. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
225607. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
225608. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
225609. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
225610. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
225611. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
225612. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
225613. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
225614. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
225615. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
225616. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
225617. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
225618. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
225619. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
225620. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
225621. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
225622. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
225623. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
225624. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
225625. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
225626. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
225627. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
225628. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
225629. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
225630. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK
225631. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
225632. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
225633. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
225634. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
225635. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
225636. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
225637. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
225638. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
225639. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
225640. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
225641. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
225642. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
225643. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
225644. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
225645. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
225646. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
225647. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
225648. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
225649. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
225650. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
225651. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
225652. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
225653. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
225654. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
225655. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
225656. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
225657. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
225658. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK
225659. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
225660. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
225661. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
225662. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
225663. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
225664. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK
225665. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT
225666. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
225667. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
225668. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
225669. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
225670. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
225671. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
225672. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
225673. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
225674. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
225675. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
225676. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
225677. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
225678. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
225679. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
225680. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
225681. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
225682. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
225683. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
225684. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
225685. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
225686. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
225687. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
225688. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
225689. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
225690. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
225691. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
225692. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
225693. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
225694. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
225695. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
225696. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
225697. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
225698. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
225699. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
225700. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
225701. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
225702. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
225703. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
225704. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
225705. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
225706. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
225707. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
225708. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
225709. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
225710. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
225711. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
225712. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
225713. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
225714. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
225715. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
225716. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
225717. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
225718. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
225719. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
225720. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
225721. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
225722. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
225723. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
225724. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
225725. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
225726. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
225727. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
225728. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
225729. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
225730. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
225731. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
225732. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
225733. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
225734. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
225735. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
225736. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
225737. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
225738. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
225739. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
225740. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
225741. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
225742. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
225743. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
225744. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
225745. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
225746. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
225747. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
225748. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
225749. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
225750. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
225751. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
225752. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
225753. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
225754. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
225755. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
225756. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
225757. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
225758. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
225759. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
225760. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
225761. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
225762. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
225763. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
225764. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
225765. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
225766. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
225767. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
225768. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
225769. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
225770. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
225771. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
225772. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
225773. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
225774. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
225775. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
225776. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
225777. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
225778. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
225779. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
225780. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
225781. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
225782. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
225783. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
225784. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
225785. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
225786. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
225787. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
225788. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
225789. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
225790. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
225791. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
225792. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
225793. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
225794. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
225795. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
225796. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
225797. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
225798. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
225799. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
225800. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
225801. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
225802. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
225803. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
225804. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
225805. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
225806. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
225807. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
225808. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
225809. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
225810. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
225811. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
225812. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
225813. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
225814. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
225815. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
225816. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
225817. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
225818. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
225819. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
225820. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
225821. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
225822. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
225823. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
225824. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
225825. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
225826. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
225827. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
225828. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
225829. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
225830. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
225831. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
225832. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
225833. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
225834. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
225835. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
225836. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
225837. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
225838. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
225839. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
225840. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
225841. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
225842. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
225843. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
225844. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
225845. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
225846. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
225847. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
225848. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
225849. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
225850. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
225851. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
225852. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
225853. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
225854. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
225855. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
225856. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
225857. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
225858. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
225859. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
225860. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
225861. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
225862. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
225863. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
225864. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
225865. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
225866. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
225867. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
225868. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
225869. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
225870. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
225871. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
225872. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
225873. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
225874. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
225875. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
225876. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
225877. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
225878. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
225879. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
225880. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
225881. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
225882. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
225883. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
225884. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
225885. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
225886. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
225887. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
225888. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
225889. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
225890. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
225891. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
225892. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
225893. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
225894. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
225895. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
225896. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
225897. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
225898. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
225899. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
225900. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
225901. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
225902. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
225903. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
225904. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
225905. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
225906. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
225907. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
225908. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
225909. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
225910. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
225911. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
225912. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
225913. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
225914. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
225915. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
225916. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
225917. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
225918. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
225919. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
225920. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
225921. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
225922. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
225923. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
225924. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
225925. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
225926. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
225927. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
225928. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
225929. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
225930. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
225931. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
225932. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
225933. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
225934. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
225935. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
225936. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
225937. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
225938. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
225939. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
225940. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
225941. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
225942. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
225943. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
225944. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
225945. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
225946. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
225947. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
225948. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
225949. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
225950. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
225951. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
225952. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
225953. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
225954. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
225955. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
225956. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
225957. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
225958. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
225959. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
225960. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
225961. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
225962. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
225963. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
225964. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
225965. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
225966. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
225967. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
225968. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
225969. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
225970. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
225971. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
225972. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
225973. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
225974. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
225975. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
225976. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
225977. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
225978. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
225979. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
225980. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
225981. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
225982. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
225983. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
225984. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
225985. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
225986. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
225987. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
225988. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
225989. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
225990. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
225991. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
225992. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
225993. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
225994. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
225995. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
225996. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
225997. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
225998. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
225999. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
226000. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
226001. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
226002. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
226003. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
226004. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
226005. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
226006. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
226007. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
226008. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
226009. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
226010. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
226011. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
226012. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
226013. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
226014. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
226015. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
226016. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
226017. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
226018. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
226019. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
226020. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
226021. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
226022. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
226023. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
226024. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
226025. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
226026. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
226027. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
226028. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
226029. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
226030. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
226031. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
226032. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
226033. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
226034. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
226035. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
226036. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
226037. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
226038. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
226039. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
226040. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
226041. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
226042. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
226043. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
226044. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
226045. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
226046. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
226047. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
226048. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
226049. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
226050. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
226051. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
226052. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK
226053. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT
226054. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK
226055. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT
226056. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK
226057. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT
226058. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK
226059. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT
226060. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK
226061. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT
226062. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK
226063. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT
226064. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK
226065. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT
226066. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK
226067. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT
226068. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
226069. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
226070. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
226071. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
226072. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
226073. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
226074. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
226075. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
226076. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
226077. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
226078. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
226079. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
226080. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
226081. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
226082. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
226083. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
226084. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
226085. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
226086. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
226087. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
226088. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
226089. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
226090. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
226091. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
226092. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
226093. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
226094. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
226095. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226096. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
226097. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
226098. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
226099. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
226100. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
226101. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
226102. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
226103. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226104. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
226105. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
226106. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
226107. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
226108. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
226109. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
226110. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
226111. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
226112. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
226113. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
226114. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
226115. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226116. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
226117. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
226118. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
226119. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
226120. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
226121. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
226122. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
226123. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226124. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
226125. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
226126. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
226127. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
226128. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
226129. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
226130. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
226131. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
226132. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
226133. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
226134. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
226135. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
226136. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
226137. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
226138. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
226139. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
226140. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
226141. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
226142. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
226143. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
226144. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
226145. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
226146. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
226147. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
226148. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
226149. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
226150. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
226151. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
226152. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
226153. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
226154. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
226155. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
226156. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
226157. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
226158. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
226159. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
226160. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
226161. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
226162. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
226163. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
226164. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
226165. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
226166. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
226167. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
226168. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
226169. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
226170. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
226171. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
226172. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
226173. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
226174. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
226175. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
226176. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
226177. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
226178. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
226179. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
226180. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
226181. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
226182. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
226183. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
226184. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
226185. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
226186. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
226187. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
226188. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
226189. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
226190. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
226191. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
226192. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
226193. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
226194. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
226195. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
226196. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
226197. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
226198. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
226199. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
226200. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
226201. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
226202. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
226203. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
226204. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
226205. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
226206. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
226207. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
226208. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
226209. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
226210. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
226211. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
226212. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
226213. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
226214. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
226215. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
226216. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
226217. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
226218. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
226219. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
226220. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
226221. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
226222. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
226223. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
226224. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
226225. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
226226. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
226227. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
226228. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
226229. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
226230. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
226231. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
226232. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
226233. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
226234. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
226235. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
226236. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
226237. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
226238. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
226239. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
226240. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
226241. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
226242. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
226243. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
226244. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
226245. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
226246. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
226247. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
226248. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
226249. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
226250. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
226251. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
226252. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
226253. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
226254. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
226255. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
226256. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
226257. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
226258. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
226259. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
226260. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
226261. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
226262. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
226263. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
226264. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
226265. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
226266. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
226267. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
226268. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
226269. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
226270. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
226271. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
226272. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
226273. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
226274. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
226275. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
226276. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
226277. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
226278. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
226279. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
226280. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
226281. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
226282. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
226283. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
226284. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
226285. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
226286. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
226287. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
226288. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
226289. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
226290. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
226291. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
226292. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
226293. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
226294. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
226295. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
226296. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
226297. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
226298. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
226299. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
226300. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
226301. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
226302. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
226303. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
226304. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
226305. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
226306. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
226307. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
226308. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
226309. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
226310. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK
226311. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
226312. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
226313. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
226314. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
226315. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
226316. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
226317. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
226318. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
226319. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
226320. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
226321. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
226322. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
226323. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
226324. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
226325. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
226326. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
226327. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
226328. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
226329. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
226330. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
226331. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
226332. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
226333. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
226334. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
226335. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
226336. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
226337. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
226338. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK
226339. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
226340. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
226341. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
226342. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
226343. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
226344. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK
226345. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT
226346. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
226347. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
226348. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
226349. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
226350. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
226351. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
226352. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
226353. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
226354. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
226355. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
226356. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
226357. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
226358. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
226359. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
226360. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
226361. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
226362. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
226363. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
226364. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
226365. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
226366. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
226367. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
226368. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
226369. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
226370. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
226371. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
226372. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
226373. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
226374. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
226375. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
226376. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
226377. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
226378. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
226379. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
226380. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
226381. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
226382. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
226383. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
226384. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
226385. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
226386. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
226387. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
226388. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
226389. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
226390. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
226391. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
226392. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
226393. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
226394. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
226395. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
226396. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
226397. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
226398. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
226399. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
226400. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
226401. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
226402. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
226403. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
226404. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
226405. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
226406. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
226407. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
226408. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
226409. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
226410. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
226411. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
226412. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
226413. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
226414. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
226415. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
226416. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
226417. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
226418. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
226419. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
226420. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
226421. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
226422. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
226423. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
226424. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
226425. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
226426. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
226427. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
226428. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
226429. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
226430. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
226431. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
226432. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
226433. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
226434. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
226435. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
226436. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
226437. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
226438. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
226439. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
226440. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
226441. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
226442. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
226443. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
226444. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
226445. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
226446. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
226447. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
226448. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
226449. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
226450. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
226451. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
226452. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
226453. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
226454. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
226455. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
226456. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
226457. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
226458. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
226459. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
226460. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
226461. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
226462. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
226463. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
226464. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
226465. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
226466. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
226467. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
226468. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
226469. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
226470. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
226471. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
226472. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
226473. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
226474. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
226475. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
226476. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
226477. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
226478. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
226479. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
226480. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
226481. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
226482. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
226483. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
226484. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
226485. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
226486. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
226487. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
226488. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
226489. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
226490. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
226491. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
226492. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
226493. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
226494. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
226495. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
226496. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
226497. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
226498. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
226499. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
226500. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
226501. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
226502. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
226503. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
226504. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
226505. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
226506. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
226507. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
226508. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
226509. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
226510. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
226511. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
226512. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
226513. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
226514. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
226515. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
226516. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
226517. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
226518. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
226519. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
226520. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
226521. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
226522. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
226523. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
226524. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
226525. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
226526. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
226527. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
226528. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
226529. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
226530. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
226531. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
226532. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
226533. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
226534. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
226535. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
226536. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
226537. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
226538. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
226539. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
226540. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
226541. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
226542. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
226543. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
226544. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
226545. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
226546. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
226547. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
226548. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
226549. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
226550. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
226551. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
226552. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
226553. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
226554. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
226555. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
226556. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
226557. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
226558. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
226559. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
226560. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
226561. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
226562. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
226563. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
226564. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
226565. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
226566. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
226567. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
226568. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
226569. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
226570. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
226571. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
226572. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
226573. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
226574. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
226575. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
226576. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
226577. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
226578. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
226579. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
226580. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
226581. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
226582. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
226583. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
226584. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
226585. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
226586. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
226587. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
226588. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
226589. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
226590. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
226591. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
226592. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
226593. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
226594. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
226595. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
226596. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
226597. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
226598. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
226599. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
226600. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
226601. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
226602. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
226603. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
226604. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
226605. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
226606. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
226607. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
226608. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
226609. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
226610. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
226611. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
226612. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
226613. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
226614. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
226615. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
226616. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
226617. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
226618. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
226619. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
226620. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
226621. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
226622. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
226623. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
226624. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
226625. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
226626. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
226627. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
226628. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
226629. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
226630. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
226631. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
226632. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
226633. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
226634. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
226635. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
226636. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
226637. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
226638. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
226639. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
226640. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
226641. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
226642. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
226643. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
226644. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
226645. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
226646. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
226647. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
226648. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
226649. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
226650. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
226651. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
226652. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
226653. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
226654. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
226655. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
226656. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
226657. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
226658. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
226659. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
226660. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
226661. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
226662. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
226663. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
226664. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
226665. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
226666. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
226667. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
226668. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
226669. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
226670. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
226671. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
226672. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
226673. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
226674. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
226675. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
226676. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
226677. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
226678. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
226679. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
226680. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
226681. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
226682. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
226683. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
226684. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
226685. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
226686. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
226687. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
226688. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
226689. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
226690. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
226691. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
226692. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
226693. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
226694. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
226695. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
226696. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
226697. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
226698. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
226699. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
226700. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
226701. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
226702. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
226703. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
226704. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
226705. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
226706. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
226707. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
226708. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
226709. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
226710. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
226711. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
226712. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
226713. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
226714. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
226715. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
226716. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
226717. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
226718. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
226719. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
226720. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
226721. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
226722. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
226723. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
226724. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
226725. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
226726. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
226727. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
226728. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
226729. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
226730. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
226731. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
226732. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK
226733. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT
226734. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK
226735. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT
226736. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK
226737. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT
226738. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK
226739. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT
226740. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK
226741. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT
226742. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK
226743. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT
226744. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK
226745. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT
226746. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK
226747. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT
226748. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
226749. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
226750. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
226751. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
226752. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
226753. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
226754. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
226755. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
226756. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
226757. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
226758. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
226759. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
226760. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
226761. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
226762. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
226763. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
226764. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
226765. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
226766. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
226767. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
226768. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
226769. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
226770. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
226771. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
226772. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
226773. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
226774. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
226775. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226776. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
226777. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
226778. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
226779. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
226780. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
226781. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
226782. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
226783. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226784. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
226785. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
226786. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
226787. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
226788. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
226789. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
226790. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
226791. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
226792. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
226793. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
226794. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
226795. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226796. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
226797. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
226798. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
226799. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
226800. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
226801. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
226802. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
226803. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
226804. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
226805. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
226806. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
226807. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
226808. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
226809. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
226810. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
226811. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
226812. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
226813. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
226814. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
226815. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
226816. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
226817. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
226818. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
226819. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
226820. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
226821. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
226822. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
226823. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
226824. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
226825. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
226826. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
226827. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
226828. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
226829. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
226830. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
226831. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
226832. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
226833. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
226834. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
226835. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
226836. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
226837. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
226838. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
226839. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
226840. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
226841. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
226842. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
226843. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
226844. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
226845. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
226846. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
226847. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
226848. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
226849. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
226850. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
226851. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
226852. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
226853. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
226854. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
226855. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
226856. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
226857. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
226858. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
226859. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
226860. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
226861. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
226862. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
226863. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
226864. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
226865. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
226866. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
226867. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
226868. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
226869. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
226870. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
226871. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
226872. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
226873. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
226874. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
226875. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
226876. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
226877. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
226878. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
226879. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
226880. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
226881. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
226882. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
226883. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
226884. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
226885. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
226886. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
226887. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
226888. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
226889. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
226890. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
226891. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
226892. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
226893. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
226894. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
226895. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
226896. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
226897. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
226898. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
226899. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
226900. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
226901. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
226902. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
226903. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
226904. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
226905. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
226906. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
226907. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
226908. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
226909. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
226910. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
226911. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
226912. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
226913. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
226914. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
226915. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
226916. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
226917. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
226918. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
226919. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
226920. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
226921. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
226922. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
226923. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
226924. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
226925. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
226926. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
226927. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
226928. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
226929. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
226930. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
226931. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
226932. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
226933. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
226934. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
226935. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
226936. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
226937. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
226938. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
226939. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
226940. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
226941. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
226942. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
226943. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
226944. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
226945. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
226946. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
226947. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
226948. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
226949. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
226950. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
226951. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
226952. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
226953. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
226954. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
226955. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
226956. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
226957. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
226958. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
226959. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
226960. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
226961. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
226962. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
226963. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
226964. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
226965. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
226966. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
226967. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
226968. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
226969. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
226970. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
226971. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
226972. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
226973. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
226974. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
226975. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
226976. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
226977. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
226978. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
226979. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
226980. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
226981. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
226982. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
226983. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
226984. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
226985. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
226986. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
226987. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
226988. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
226989. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
226990. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK
226991. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
226992. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
226993. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
226994. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
226995. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
226996. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
226997. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
226998. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
226999. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
227000. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
227001. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
227002. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
227003. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
227004. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
227005. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
227006. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
227007. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
227008. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
227009. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
227010. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
227011. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
227012. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
227013. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
227014. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
227015. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
227016. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
227017. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
227018. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK
227019. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
227020. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
227021. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
227022. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
227023. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
227024. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK
227025. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT
227026. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
227027. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
227028. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
227029. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
227030. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
227031. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
227032. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
227033. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
227034. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
227035. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
227036. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
227037. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
227038. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
227039. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
227040. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
227041. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
227042. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
227043. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
227044. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
227045. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
227046. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
227047. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
227048. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
227049. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
227050. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
227051. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
227052. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
227053. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
227054. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
227055. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
227056. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
227057. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
227058. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
227059. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
227060. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
227061. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
227062. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
227063. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
227064. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
227065. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
227066. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
227067. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
227068. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
227069. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
227070. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
227071. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
227072. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
227073. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
227074. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
227075. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
227076. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
227077. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
227078. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
227079. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
227080. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
227081. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
227082. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
227083. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
227084. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
227085. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
227086. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
227087. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
227088. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
227089. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
227090. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
227091. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
227092. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
227093. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
227094. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
227095. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
227096. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
227097. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
227098. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
227099. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
227100. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
227101. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
227102. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
227103. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
227104. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
227105. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
227106. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
227107. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
227108. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
227109. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
227110. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
227111. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
227112. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
227113. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
227114. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
227115. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
227116. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
227117. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
227118. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
227119. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
227120. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
227121. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
227122. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
227123. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
227124. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
227125. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
227126. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
227127. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
227128. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
227129. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
227130. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
227131. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
227132. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
227133. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
227134. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
227135. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
227136. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
227137. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
227138. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
227139. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
227140. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
227141. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
227142. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
227143. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
227144. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
227145. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
227146. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
227147. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
227148. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
227149. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
227150. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
227151. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
227152. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
227153. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
227154. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
227155. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
227156. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
227157. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
227158. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
227159. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
227160. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
227161. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
227162. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
227163. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
227164. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
227165. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
227166. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
227167. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
227168. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
227169. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
227170. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
227171. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
227172. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
227173. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
227174. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
227175. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
227176. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
227177. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
227178. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
227179. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
227180. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
227181. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
227182. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
227183. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
227184. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
227185. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
227186. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
227187. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
227188. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
227189. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
227190. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
227191. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
227192. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
227193. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
227194. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
227195. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
227196. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
227197. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
227198. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
227199. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
227200. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
227201. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
227202. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
227203. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
227204. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
227205. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
227206. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
227207. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
227208. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
227209. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
227210. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
227211. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
227212. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
227213. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
227214. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
227215. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
227216. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
227217. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
227218. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
227219. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
227220. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
227221. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
227222. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
227223. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
227224. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
227225. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
227226. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
227227. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
227228. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
227229. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
227230. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
227231. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
227232. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
227233. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
227234. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
227235. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
227236. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
227237. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
227238. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
227239. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
227240. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
227241. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
227242. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
227243. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
227244. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
227245. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
227246. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
227247. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
227248. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
227249. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
227250. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
227251. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
227252. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
227253. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
227254. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
227255. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
227256. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
227257. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
227258. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
227259. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
227260. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
227261. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
227262. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
227263. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
227264. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
227265. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
227266. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
227267. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
227268. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
227269. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
227270. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
227271. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
227272. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
227273. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
227274. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
227275. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
227276. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
227277. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
227278. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
227279. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
227280. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
227281. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
227282. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
227283. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
227284. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
227285. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
227286. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
227287. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
227288. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
227289. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
227290. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
227291. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
227292. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
227293. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
227294. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
227295. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
227296. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
227297. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
227298. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
227299. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
227300. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
227301. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
227302. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
227303. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
227304. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
227305. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
227306. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
227307. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
227308. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
227309. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
227310. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
227311. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
227312. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
227313. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
227314. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
227315. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
227316. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
227317. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
227318. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
227319. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
227320. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
227321. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
227322. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
227323. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
227324. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
227325. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
227326. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
227327. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
227328. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
227329. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
227330. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
227331. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
227332. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
227333. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
227334. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
227335. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
227336. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
227337. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
227338. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
227339. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
227340. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
227341. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
227342. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
227343. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
227344. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
227345. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
227346. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
227347. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
227348. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
227349. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
227350. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
227351. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
227352. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
227353. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
227354. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
227355. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
227356. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
227357. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
227358. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
227359. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
227360. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
227361. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
227362. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
227363. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
227364. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
227365. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
227366. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
227367. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
227368. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
227369. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
227370. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
227371. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
227372. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
227373. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
227374. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
227375. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
227376. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
227377. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
227378. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
227379. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
227380. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
227381. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
227382. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
227383. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
227384. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
227385. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
227386. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
227387. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
227388. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
227389. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
227390. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
227391. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
227392. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
227393. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
227394. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
227395. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
227396. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
227397. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
227398. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
227399. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
227400. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
227401. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
227402. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
227403. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
227404. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
227405. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
227406. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
227407. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
227408. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
227409. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
227410. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
227411. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
227412. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK
227413. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT
227414. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK
227415. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT
227416. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK
227417. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT
227418. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK
227419. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT
227420. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK
227421. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT
227422. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK
227423. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT
227424. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK
227425. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT
227426. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK
227427. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT
227428. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK
227429. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT
227430. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK
227431. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT
227432. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK
227433. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT
227434. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK
227435. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT
227436. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK
227437. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT
227438. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK
227439. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT
227440. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK
227441. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT
227442. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK
227443. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
227444. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK
227445. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT
227446. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK
227447. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
227448. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK
227449. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT
227450. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK
227451. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
227452. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK
227453. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT
227454. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
227455. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
227456. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK
227457. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT
227458. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK
227459. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT
227460. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK
227461. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT
227462. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
227463. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
227464. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK
227465. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT
227466. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK
227467. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
227468. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK
227469. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT
227470. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK
227471. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
227472. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK
227473. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT
227474. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK
227475. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
227476. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK
227477. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT
227478. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK
227479. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT
227480. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK
227481. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT
227482. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK
227483. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT
227484. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK
227485. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT
227486. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK
227487. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT
227488. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK
227489. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT
227490. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK
227491. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT
227492. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK
227493. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT
227494. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK
227495. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT
227496. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK
227497. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT
227498. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK
227499. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT
227500. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK
227501. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT
227502. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK
227503. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT
227504. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK
227505. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT
227506. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK
227507. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT
227508. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK
227509. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT
227510. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK
227511. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT
227512. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK
227513. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT
227514. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK
227515. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT
227516. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK
227517. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT
227518. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK
227519. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT
227520. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK
227521. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT
227522. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK
227523. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT
227524. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK
227525. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT
227526. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK
227527. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT
227528. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK
227529. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT
227530. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK
227531. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT
227532. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK
227533. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT
227534. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK
227535. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT
227536. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK
227537. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT
227538. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK
227539. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT
227540. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK
227541. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT
227542. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK
227543. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT
227544. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK
227545. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT
227546. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK
227547. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT
227548. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK
227549. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT
227550. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK
227551. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT
227552. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK
227553. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT
227554. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK
227555. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT
227556. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK
227557. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT
227558. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK
227559. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT
227560. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK
227561. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT
227562. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK
227563. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT
227564. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK
227565. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT
227566. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK
227567. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT
227568. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK
227569. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT
227570. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK
227571. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT
227572. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK
227573. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT
227574. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK
227575. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT
227576. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK
227577. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT
227578. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK
227579. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT
227580. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK
227581. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT
227582. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK
227583. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT
227584. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK
227585. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT
227586. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK
227587. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT
227588. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK
227589. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT
227590. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK
227591. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT
227592. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK
227593. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT
227594. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK
227595. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT
227596. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK
227597. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT
227598. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK
227599. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT
227600. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK
227601. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT
227602. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK
227603. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT
227604. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK
227605. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT
227606. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK
227607. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT
227608. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK
227609. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT
227610. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK
227611. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT
227612. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK
227613. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT
227614. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK
227615. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT
227616. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK
227617. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT
227618. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK
227619. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT
227620. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK
227621. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT
227622. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK
227623. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT
227624. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK
227625. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT
227626. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK
227627. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT
227628. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK
227629. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT
227630. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK
227631. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT
227632. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK
227633. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT
227634. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK
227635. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT
227636. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK
227637. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT
227638. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK
227639. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT
227640. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK
227641. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT
227642. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK
227643. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT
227644. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK
227645. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT
227646. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK
227647. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT
227648. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK
227649. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT
227650. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK
227651. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT
227652. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK
227653. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT
227654. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK
227655. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT
227656. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK
227657. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT
227658. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK
227659. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT
227660. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK
227661. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT
227662. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK
227663. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT
227664. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK
227665. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT
227666. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK
227667. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT
227668. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK
227669. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT
227670. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK
227671. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT
227672. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK
227673. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT
227674. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK
227675. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT
227676. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK
227677. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT
227678. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK
227679. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT
227680. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK
227681. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT
227682. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK
227683. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT
227684. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK
227685. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT
227686. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK
227687. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT
227688. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK
227689. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT
227690. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK
227691. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT
227692. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK
227693. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT
227694. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK
227695. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT
227696. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK
227697. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT
227698. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK
227699. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT
227700. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK
227701. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT
227702. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK
227703. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT
227704. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK
227705. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT
227706. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK
227707. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT
227708. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK
227709. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT
227710. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK
227711. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT
227712. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK
227713. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT
227714. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK
227715. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT
227716. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK
227717. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT
227718. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK
227719. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT
227720. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK
227721. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT
227722. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK
227723. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT
227724. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK
227725. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT
227726. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK
227727. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT
227728. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK
227729. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT
227730. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK
227731. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT
227732. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK
227733. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT
227734. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK
227735. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT
227736. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK
227737. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
227738. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK
227739. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT
227740. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK
227741. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT
227742. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK
227743. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT
227744. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK
227745. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT
227746. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK
227747. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT
227748. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK
227749. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT
227750. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK
227751. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT
227752. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK
227753. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT
227754. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK
227755. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT
227756. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK
227757. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT
227758. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK
227759. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT
227760. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK
227761. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT
227762. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK
227763. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT
227764. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK
227765. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT
227766. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK
227767. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT
227768. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK
227769. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT
227770. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK
227771. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT
227772. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK
227773. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT
227774. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK
227775. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT
227776. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK
227777. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT
227778. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK
227779. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT
227780. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK
227781. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT
227782. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK
227783. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT
227784. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK
227785. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT
227786. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK
227787. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT
227788. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK
227789. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
227790. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK
227791. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
227792. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK
227793. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT
227794. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK
227795. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
227796. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK
227797. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
227798. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK
227799. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT
227800. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK
227801. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT
227802. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK
227803. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT
227804. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK
227805. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT
227806. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK
227807. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT
227808. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK
227809. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK
227810. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT
227811. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT
227812. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK
227813. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT
227814. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK
227815. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT
227816. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK
227817. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT
227818. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK
227819. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT
227820. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK
227821. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT
227822. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK
227823. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT
227824. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK
227825. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT
227826. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK
227827. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT
227828. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK
227829. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT
227830. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK
227831. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT
227832. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK
227833. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT
227834. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK
227835. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT
227836. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK
227837. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT
227838. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK
227839. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT
227840. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK
227841. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT
227842. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK
227843. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT
227844. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK
227845. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT
227846. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK
227847. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT
227848. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK
227849. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT
227850. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK
227851. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT
227852. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK
227853. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT
227854. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK
227855. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT
227856. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK
227857. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT
227858. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK
227859. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT
227860. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK
227861. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT
227862. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK
227863. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT
227864. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK
227865. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT
227866. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK
227867. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT
227868. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK
227869. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT
227870. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK
227871. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT
227872. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK
227873. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT
227874. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK
227875. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT
227876. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK
227877. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT
227878. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK
227879. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT
227880. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK
227881. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT
227882. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK
227883. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT
227884. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK
227885. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT
227886. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK
227887. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT
227888. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK
227889. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT
227890. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK
227891. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT
227892. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK
227893. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT
227894. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK
227895. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT
227896. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK
227897. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT
227898. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK
227899. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT
227900. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK
227901. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT
227902. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK
227903. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT
227904. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK
227905. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT
227906. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK
227907. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT
227908. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK
227909. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT
227910. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK
227911. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT
227912. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK
227913. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT
227914. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK
227915. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT
227916. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK
227917. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT
227918. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK
227919. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT
227920. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK
227921. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT
227922. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK
227923. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT
227924. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK
227925. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT
227926. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK
227927. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT
227928. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK
227929. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT
227930. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK
227931. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT
227932. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK
227933. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT
227934. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK
227935. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT
227936. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK
227937. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT
227938. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK
227939. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT
227940. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK
227941. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT
227942. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK
227943. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT
227944. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK
227945. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT
227946. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK
227947. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT
227948. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK
227949. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT
227950. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK
227951. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT
227952. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK
227953. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT
227954. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK
227955. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT
227956. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK
227957. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT
227958. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK
227959. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT
227960. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK
227961. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT
227962. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK
227963. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT
227964. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK
227965. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT
227966. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK
227967. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT
227968. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK
227969. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT
227970. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK
227971. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT
227972. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK
227973. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT
227974. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK
227975. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT
227976. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK
227977. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT
227978. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK
227979. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT
227980. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK
227981. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT
227982. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK
227983. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT
227984. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK
227985. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT
227986. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK
227987. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT
227988. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK
227989. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT
227990. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK
227991. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT
227992. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK
227993. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT
227994. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK
227995. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT
227996. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK
227997. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT
227998. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK
227999. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT
228000. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK
228001. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT
228002. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK
228003. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT
228004. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK
228005. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT
228006. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK
228007. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT
228008. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK
228009. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT
228010. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK
228011. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT
228012. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK
228013. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT
228014. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK
228015. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT
228016. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK
228017. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT
228018. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK
228019. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT
228020. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK
228021. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT
228022. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK
228023. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT
228024. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK
228025. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT
228026. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK
228027. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT
228028. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK
228029. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT
228030. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK
228031. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT
228032. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK
228033. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT
228034. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK
228035. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT
228036. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK
228037. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT
228038. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK
228039. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT
228040. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK
228041. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT
228042. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK
228043. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT
228044. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK
228045. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT
228046. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK
228047. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT
228048. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK
228049. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT
228050. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK
228051. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT
228052. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK
228053. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT
228054. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK
228055. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT
228056. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK
228057. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT
228058. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK
228059. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT
228060. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK
228061. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT
228062. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK
228063. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT
228064. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK
228065. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT
228066. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK
228067. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT
228068. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK
228069. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT
228070. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK
228071. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT
228072. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK
228073. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT
228074. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK
228075. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT
228076. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK
228077. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT
228078. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK
228079. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT
228080. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK
228081. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT
228082. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK
228083. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT
228084. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK
228085. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT
228086. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK
228087. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT
228088. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK
228089. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT
228090. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK
228091. DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT
228092. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__NC74_MASK
228093. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__NC74__SHIFT
228094. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__RESERVED_15_8_MASK
228095. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__RESERVED_15_8__SHIFT
228096. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__bypass_bg_MASK
228097. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__bypass_bg__SHIFT
228098. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__chop_en_MASK
228099. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__chop_en__SHIFT
228100. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__vref_sel_fastreg_MASK
228101. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__vref_sel_fastreg__SHIFT
228102. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
228103. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
228104. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK
228105. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
228106. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK
228107. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
228108. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
228109. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
228110. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK
228111. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
228112. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK
228113. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
228114. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK
228115. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
228116. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK
228117. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
228118. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK
228119. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
228120. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
228121. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
228122. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
228123. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
228124. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK
228125. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT
228126. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
228127. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
228128. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK
228129. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
228130. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK
228131. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT
228132. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
228133. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
228134. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK
228135. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
228136. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
228137. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
228138. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__NC76_MASK
228139. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT
228140. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
228141. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
228142. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__atb_select_MASK
228143. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT
228144. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK
228145. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT
228146. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK
228147. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT
228148. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK
228149. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
228150. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK
228151. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT
228152. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK
228153. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT
228154. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC40_MASK
228155. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC40__SHIFT
228156. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC76_MASK
228157. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC76__SHIFT
228158. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK
228159. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
228160. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK
228161. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT
228162. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
228163. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
228164. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK
228165. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT
228166. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK
228167. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT
228168. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
228169. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
228170. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK
228171. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
228172. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK
228173. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
228174. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
228175. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
228176. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK
228177. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
228178. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK
228179. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT
228180. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
228181. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
228182. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK
228183. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
228184. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK
228185. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
228186. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
228187. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
228188. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK
228189. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
228190. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK
228191. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
228192. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK
228193. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
228194. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK
228195. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
228196. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK
228197. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
228198. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
228199. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
228200. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
228201. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
228202. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK
228203. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT
228204. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
228205. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
228206. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK
228207. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
228208. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK
228209. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT
228210. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
228211. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
228212. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK
228213. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
228214. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
228215. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
228216. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__NC76_MASK
228217. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT
228218. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
228219. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
228220. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__atb_select_MASK
228221. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT
228222. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK
228223. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT
228224. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK
228225. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT
228226. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK
228227. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
228228. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK
228229. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT
228230. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK
228231. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT
228232. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC40_MASK
228233. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC40__SHIFT
228234. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC76_MASK
228235. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC76__SHIFT
228236. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK
228237. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
228238. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK
228239. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT
228240. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
228241. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
228242. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK
228243. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT
228244. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK
228245. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT
228246. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
228247. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
228248. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK
228249. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
228250. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK
228251. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
228252. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
228253. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
228254. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK
228255. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
228256. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK
228257. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT
228258. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
228259. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
228260. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK
228261. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT
228262. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK
228263. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
228264. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK
228265. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
228266. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK
228267. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
228268. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
228269. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
228270. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
228271. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
228272. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
228273. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
228274. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK
228275. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
228276. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
228277. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
228278. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
228279. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
228280. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
228281. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
228282. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
228283. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
228284. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK
228285. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
228286. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
228287. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
228288. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
228289. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
228290. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
228291. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
228292. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
228293. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
228294. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
228295. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
228296. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
228297. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
228298. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
228299. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
228300. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
228301. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
228302. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
228303. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
228304. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
228305. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
228306. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
228307. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
228308. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
228309. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
228310. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
228311. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
228312. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
228313. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
228314. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
228315. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
228316. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
228317. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
228318. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
228319. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
228320. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
228321. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
228322. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
228323. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
228324. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
228325. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
228326. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
228327. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
228328. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
228329. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
228330. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
228331. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
228332. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
228333. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
228334. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
228335. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
228336. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
228337. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
228338. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
228339. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
228340. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
228341. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
228342. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
228343. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
228344. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
228345. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
228346. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
228347. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
228348. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
228349. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
228350. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
228351. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
228352. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
228353. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
228354. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
228355. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
228356. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
228357. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
228358. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
228359. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
228360. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
228361. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
228362. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
228363. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
228364. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
228365. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
228366. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
228367. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
228368. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
228369. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
228370. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
228371. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
228372. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK
228373. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT
228374. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
228375. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
228376. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__BG_EN_MASK
228377. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__BG_EN__SHIFT
228378. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK
228379. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT
228380. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK
228381. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT
228382. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK
228383. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT
228384. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
228385. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
228386. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK
228387. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT
228388. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
228389. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
228390. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK
228391. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT
228392. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK
228393. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT
228394. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK
228395. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
228396. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK
228397. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT
228398. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK
228399. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
228400. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK
228401. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT
228402. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK
228403. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT
228404. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK
228405. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT
228406. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK
228407. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
228408. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI__data_MASK
228409. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI__data__SHIFT
228410. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO__data_MASK
228411. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO__data__SHIFT
228412. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
228413. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
228414. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
228415. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
228416. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
228417. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
228418. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
228419. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
228420. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
228421. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
228422. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
228423. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
228424. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
228425. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
228426. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
228427. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
228428. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
228429. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
228430. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
228431. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
228432. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
228433. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
228434. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
228435. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
228436. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
228437. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
228438. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
228439. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
228440. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
228441. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
228442. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
228443. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
228444. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
228445. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
228446. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
228447. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
228448. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
228449. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
228450. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
228451. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
228452. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
228453. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
228454. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
228455. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
228456. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
228457. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
228458. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
228459. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
228460. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
228461. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
228462. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
228463. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
228464. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
228465. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
228466. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
228467. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
228468. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
228469. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
228470. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
228471. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
228472. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
228473. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
228474. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
228475. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
228476. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
228477. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
228478. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
228479. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
228480. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
228481. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
228482. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
228483. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
228484. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
228485. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
228486. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
228487. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
228488. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
228489. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
228490. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
228491. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
228492. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
228493. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
228494. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
228495. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
228496. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
228497. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
228498. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
228499. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
228500. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
228501. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
228502. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
228503. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
228504. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
228505. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
228506. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
228507. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
228508. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
228509. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
228510. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
228511. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
228512. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
228513. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
228514. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
228515. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
228516. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
228517. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
228518. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
228519. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
228520. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
228521. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
228522. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
228523. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
228524. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
228525. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
228526. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
228527. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
228528. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
228529. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
228530. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
228531. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
228532. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
228533. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
228534. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
228535. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
228536. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
228537. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
228538. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
228539. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
228540. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
228541. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
228542. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
228543. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
228544. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
228545. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
228546. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
228547. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
228548. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
228549. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
228550. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
228551. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
228552. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
228553. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
228554. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
228555. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
228556. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
228557. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
228558. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
228559. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
228560. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
228561. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
228562. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
228563. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
228564. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
228565. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
228566. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
228567. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
228568. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
228569. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
228570. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
228571. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
228572. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
228573. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
228574. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
228575. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
228576. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
228577. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
228578. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
228579. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
228580. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
228581. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
228582. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
228583. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
228584. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
228585. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
228586. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
228587. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
228588. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
228589. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
228590. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
228591. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
228592. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
228593. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
228594. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
228595. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
228596. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
228597. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
228598. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
228599. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
228600. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
228601. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
228602. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
228603. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
228604. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
228605. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
228606. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
228607. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
228608. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
228609. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
228610. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
228611. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
228612. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
228613. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
228614. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
228615. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
228616. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
228617. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
228618. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
228619. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
228620. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
228621. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
228622. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
228623. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
228624. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
228625. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
228626. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
228627. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
228628. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
228629. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
228630. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
228631. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
228632. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
228633. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
228634. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
228635. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
228636. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
228637. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
228638. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
228639. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
228640. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
228641. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
228642. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
228643. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
228644. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
228645. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
228646. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
228647. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
228648. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
228649. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
228650. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
228651. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
228652. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
228653. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
228654. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
228655. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
228656. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
228657. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
228658. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
228659. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
228660. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
228661. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
228662. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
228663. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
228664. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
228665. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
228666. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
228667. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
228668. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
228669. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
228670. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
228671. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
228672. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
228673. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
228674. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
228675. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
228676. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
228677. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
228678. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
228679. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
228680. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
228681. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
228682. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
228683. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
228684. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
228685. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
228686. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
228687. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
228688. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
228689. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
228690. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
228691. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
228692. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
228693. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
228694. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
228695. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
228696. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
228697. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
228698. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
228699. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
228700. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
228701. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
228702. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
228703. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
228704. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
228705. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
228706. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
228707. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
228708. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
228709. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
228710. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
228711. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
228712. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
228713. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
228714. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
228715. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
228716. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
228717. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
228718. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
228719. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
228720. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
228721. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
228722. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
228723. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
228724. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
228725. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
228726. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
228727. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
228728. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
228729. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
228730. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
228731. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
228732. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
228733. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
228734. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
228735. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
228736. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
228737. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
228738. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
228739. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
228740. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
228741. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
228742. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
228743. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
228744. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
228745. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
228746. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
228747. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
228748. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
228749. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
228750. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
228751. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
228752. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
228753. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
228754. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
228755. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
228756. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK
228757. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
228758. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
228759. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
228760. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
228761. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
228762. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
228763. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
228764. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
228765. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
228766. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
228767. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
228768. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
228769. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
228770. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
228771. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
228772. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
228773. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
228774. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
228775. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
228776. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
228777. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
228778. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
228779. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
228780. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
228781. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
228782. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
228783. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
228784. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK
228785. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
228786. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK
228787. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
228788. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK
228789. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
228790. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__STAT_MASK
228791. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT
228792. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
228793. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
228794. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
228795. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
228796. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
228797. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
228798. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
228799. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
228800. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
228801. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
228802. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
228803. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
228804. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
228805. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
228806. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
228807. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
228808. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
228809. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
228810. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
228811. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
228812. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
228813. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
228814. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
228815. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
228816. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
228817. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
228818. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
228819. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
228820. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
228821. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
228822. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
228823. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
228824. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
228825. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
228826. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
228827. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
228828. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
228829. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
228830. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
228831. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
228832. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
228833. DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
228834. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__NC74_MASK
228835. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__NC74__SHIFT
228836. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__RESERVED_15_8_MASK
228837. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__RESERVED_15_8__SHIFT
228838. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__bypass_bg_MASK
228839. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__bypass_bg__SHIFT
228840. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__chop_en_MASK
228841. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__chop_en__SHIFT
228842. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__vref_sel_fastreg_MASK
228843. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__vref_sel_fastreg__SHIFT
228844. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK
228845. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT
228846. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK
228847. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT
228848. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK
228849. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT
228850. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK
228851. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT
228852. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK
228853. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT
228854. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK
228855. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT
228856. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK
228857. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT
228858. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK
228859. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT
228860. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK
228861. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT
228862. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK
228863. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT
228864. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK
228865. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT
228866. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_gd_MASK
228867. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT
228868. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK
228869. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT
228870. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK
228871. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT
228872. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vp_MASK
228873. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT
228874. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK
228875. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT
228876. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK
228877. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT
228878. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK
228879. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT
228880. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__NC76_MASK
228881. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__NC76__SHIFT
228882. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK
228883. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT
228884. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__atb_select_MASK
228885. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT
228886. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK
228887. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT
228888. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK
228889. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT
228890. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK
228891. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT
228892. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK
228893. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT
228894. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK
228895. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT
228896. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC40_MASK
228897. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC40__SHIFT
228898. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC76_MASK
228899. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC76__SHIFT
228900. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK
228901. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT
228902. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK
228903. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT
228904. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK
228905. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT
228906. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__cal_reg_MASK
228907. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT
228908. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__enable_reg_MASK
228909. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT
228910. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK
228911. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT
228912. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK
228913. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT
228914. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK
228915. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT
228916. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK
228917. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT
228918. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK
228919. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT
228920. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__reset_reg_MASK
228921. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT
228922. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK
228923. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT
228924. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK
228925. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT
228926. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK
228927. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT
228928. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK
228929. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT
228930. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK
228931. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT
228932. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK
228933. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT
228934. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK
228935. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT
228936. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK
228937. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT
228938. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK
228939. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT
228940. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK
228941. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT
228942. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK
228943. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT
228944. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_gd_MASK
228945. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT
228946. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK
228947. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT
228948. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK
228949. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT
228950. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vp_MASK
228951. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT
228952. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK
228953. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT
228954. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK
228955. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT
228956. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK
228957. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT
228958. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__NC76_MASK
228959. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__NC76__SHIFT
228960. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK
228961. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT
228962. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__atb_select_MASK
228963. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT
228964. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK
228965. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT
228966. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK
228967. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT
228968. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK
228969. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT
228970. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK
228971. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT
228972. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK
228973. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT
228974. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC40_MASK
228975. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC40__SHIFT
228976. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC76_MASK
228977. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC76__SHIFT
228978. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK
228979. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT
228980. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK
228981. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT
228982. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK
228983. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT
228984. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__cal_reg_MASK
228985. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT
228986. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__enable_reg_MASK
228987. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT
228988. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK
228989. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT
228990. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK
228991. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT
228992. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK
228993. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT
228994. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK
228995. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT
228996. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK
228997. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT
228998. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__reset_reg_MASK
228999. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT
229000. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK
229001. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT
229002. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_atb_MASK
229003. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT
229004. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK
229005. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT
229006. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK
229007. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT
229008. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK
229009. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT
229010. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK
229011. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT
229012. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK
229013. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT
229014. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK
229015. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT
229016. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK
229017. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT
229018. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK
229019. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT
229020. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK
229021. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT
229022. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK
229023. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT
229024. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK
229025. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT
229026. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK
229027. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT
229028. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK
229029. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT
229030. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK
229031. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT
229032. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK
229033. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT
229034. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK
229035. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT
229036. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK
229037. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT
229038. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK
229039. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT
229040. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK
229041. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT
229042. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK
229043. DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT
229044. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK
229045. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT
229046. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK
229047. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT
229048. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK
229049. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT
229050. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK
229051. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT
229052. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK
229053. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT
229054. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK
229055. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT
229056. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK
229057. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT
229058. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK
229059. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT
229060. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK
229061. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT
229062. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK
229063. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT
229064. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK
229065. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT
229066. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK
229067. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT
229068. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK
229069. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT
229070. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK
229071. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT
229072. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK
229073. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT
229074. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK
229075. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT
229076. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK
229077. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT
229078. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK
229079. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT
229080. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK
229081. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT
229082. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK
229083. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT
229084. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK
229085. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT
229086. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK
229087. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT
229088. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK
229089. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT
229090. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK
229091. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT
229092. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK
229093. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT
229094. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK
229095. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT
229096. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK
229097. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT
229098. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK
229099. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT
229100. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK
229101. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT
229102. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK
229103. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT
229104. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK
229105. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT
229106. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK
229107. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT
229108. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK
229109. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT
229110. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK
229111. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT
229112. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK
229113. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT
229114. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK
229115. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT
229116. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK
229117. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT
229118. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__BG_EN_MASK
229119. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__BG_EN__SHIFT
229120. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK
229121. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT
229122. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK
229123. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT
229124. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__PHY_RESET_MASK
229125. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT
229126. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK
229127. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT
229128. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK
229129. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT
229130. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK
229131. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT
229132. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK
229133. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT
229134. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK
229135. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT
229136. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK
229137. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT
229138. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK
229139. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT
229140. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK
229141. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT
229142. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK
229143. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT
229144. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK
229145. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT
229146. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK
229147. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT
229148. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK
229149. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT
229150. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI__data_MASK
229151. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI__data__SHIFT
229152. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO__data_MASK
229153. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO__data__SHIFT
229154. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK
229155. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT
229156. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK
229157. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT
229158. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK
229159. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT
229160. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK
229161. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT
229162. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK
229163. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT
229164. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK
229165. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT
229166. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK
229167. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT
229168. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK
229169. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT
229170. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK
229171. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
229172. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
229173. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
229174. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK
229175. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
229176. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK
229177. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT
229178. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK
229179. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT
229180. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
229181. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
229182. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK
229183. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT
229184. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK
229185. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT
229186. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK
229187. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
229188. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK
229189. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT
229190. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK
229191. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT
229192. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK
229193. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT
229194. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK
229195. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT
229196. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK
229197. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT
229198. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK
229199. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT
229200. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK
229201. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT
229202. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK
229203. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT
229204. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK
229205. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT
229206. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK
229207. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT
229208. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK
229209. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT
229210. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK
229211. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT
229212. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
229213. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
229214. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
229215. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
229216. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
229217. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
229218. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
229219. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
229220. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
229221. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
229222. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
229223. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
229224. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
229225. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
229226. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
229227. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
229228. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
229229. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
229230. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
229231. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
229232. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
229233. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
229234. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
229235. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
229236. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
229237. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
229238. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
229239. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
229240. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
229241. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
229242. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
229243. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
229244. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
229245. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
229246. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
229247. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
229248. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
229249. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
229250. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
229251. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
229252. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
229253. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
229254. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
229255. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
229256. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
229257. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
229258. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
229259. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
229260. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
229261. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
229262. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
229263. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
229264. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
229265. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
229266. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
229267. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
229268. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
229269. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
229270. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
229271. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
229272. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
229273. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
229274. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
229275. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
229276. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
229277. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
229278. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
229279. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
229280. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
229281. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
229282. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
229283. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
229284. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
229285. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
229286. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
229287. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
229288. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
229289. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
229290. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
229291. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
229292. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
229293. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
229294. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK
229295. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT
229296. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK
229297. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT
229298. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK
229299. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT
229300. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK
229301. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT
229302. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK
229303. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT
229304. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK
229305. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT
229306. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK
229307. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT
229308. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK
229309. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT
229310. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK
229311. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT
229312. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK
229313. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT
229314. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK
229315. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT
229316. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK
229317. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT
229318. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK
229319. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT
229320. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK
229321. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT
229322. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
229323. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
229324. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
229325. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
229326. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK
229327. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
229328. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
229329. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
229330. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK
229331. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT
229332. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK
229333. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
229334. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK
229335. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT
229336. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
229337. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
229338. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK
229339. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT
229340. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK
229341. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT
229342. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK
229343. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT
229344. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK
229345. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
229346. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK
229347. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
229348. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK
229349. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT
229350. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK
229351. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT
229352. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
229353. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
229354. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK
229355. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT
229356. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK
229357. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT
229358. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK
229359. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
229360. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK
229361. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT
229362. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK
229363. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT
229364. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK
229365. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT
229366. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK
229367. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT
229368. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK
229369. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT
229370. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK
229371. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT
229372. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK
229373. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT
229374. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK
229375. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT
229376. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK
229377. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT
229378. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK
229379. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT
229380. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK
229381. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT
229382. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK
229383. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT
229384. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK
229385. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT
229386. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK
229387. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT
229388. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK
229389. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT
229390. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK
229391. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT
229392. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK
229393. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT
229394. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK
229395. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT
229396. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK
229397. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT
229398. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK
229399. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT
229400. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK
229401. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT
229402. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK
229403. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT
229404. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK
229405. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT
229406. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK
229407. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT
229408. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK
229409. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT
229410. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK
229411. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT
229412. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK
229413. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT
229414. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK
229415. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT
229416. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK
229417. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT
229418. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK
229419. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT
229420. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK
229421. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT
229422. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK
229423. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT
229424. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK
229425. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT
229426. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK
229427. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT
229428. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK
229429. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT
229430. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK
229431. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK
229432. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT
229433. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT
229434. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK
229435. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT
229436. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK
229437. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT
229438. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK
229439. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT
229440. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK
229441. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT
229442. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK
229443. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT
229444. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK
229445. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT
229446. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK
229447. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT
229448. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK
229449. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT
229450. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK
229451. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT
229452. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK
229453. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT
229454. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK
229455. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT
229456. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK
229457. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT
229458. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK
229459. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT
229460. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK
229461. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT
229462. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK
229463. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT
229464. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK
229465. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT
229466. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK
229467. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT
229468. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK
229469. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT
229470. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK
229471. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT
229472. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK
229473. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT
229474. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK
229475. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT
229476. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK
229477. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT
229478. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK
229479. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT
229480. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK
229481. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT
229482. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK
229483. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT
229484. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK
229485. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT
229486. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK
229487. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT
229488. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK
229489. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT
229490. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK
229491. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT
229492. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK
229493. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT
229494. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK
229495. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT
229496. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK
229497. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT
229498. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK
229499. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT
229500. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK
229501. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT
229502. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK
229503. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT
229504. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK
229505. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT
229506. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK
229507. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT
229508. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK
229509. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT
229510. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK
229511. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT
229512. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK
229513. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT
229514. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK
229515. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT
229516. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK
229517. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT
229518. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK
229519. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT
229520. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK
229521. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT
229522. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK
229523. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT
229524. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK
229525. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT
229526. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK
229527. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT
229528. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK
229529. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT
229530. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK
229531. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT
229532. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__STAT_MASK
229533. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__STAT__SHIFT
229534. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK
229535. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT
229536. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK
229537. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT
229538. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK
229539. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT
229540. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK
229541. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT
229542. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK
229543. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT
229544. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK
229545. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT
229546. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK
229547. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT
229548. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK
229549. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT
229550. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK
229551. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT
229552. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK
229553. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT
229554. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK
229555. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT
229556. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK
229557. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT
229558. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK
229559. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT
229560. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK
229561. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT
229562. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK
229563. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT
229564. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK
229565. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT
229566. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK
229567. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT
229568. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK
229569. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT
229570. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK
229571. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT
229572. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK
229573. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT
229574. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK
229575. DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT
229576. DWC_I2S_PLAY
229577. DWC_I2S_RECORD
229578. DWC_LLP_LMS
229579. DWC_LLP_LOC
229580. DWC_PARAMS_MBLK_EN
229581. DWC_SGR_SGC
229582. DWC_SGR_SGI
229583. DWC_UFS_REG_HCLKDIV
229584. DWC_UFS_REG_HCLKDIV_DIV_125
229585. DWC_UFS_REG_HCLKDIV_DIV_200
229586. DWC_UFS_REG_HCLKDIV_DIV_62_5
229587. DWFILL
229588. DWGREG0
229589. DWGREG0_END
229590. DWGREG1
229591. DWGREG1_END
229592. DWINPOS
229593. DWINSZ
229594. DWL_16
229595. DWL_18
229596. DWL_20
229597. DWL_22
229598. DWL_24
229599. DWL_32
229600. DWL_8
229601. DWL_MASK
229602. DWMAC_125MHZ
229603. DWMAC_25MHZ
229604. DWMAC_2_5MHZ
229605. DWMAC_50MHZ
229606. DWMAC_AUTO_TX_SOURCE
229607. DWMAC_CKEN_GTX
229608. DWMAC_CKEN_RXN_OUT
229609. DWMAC_CKEN_RX_IN
229610. DWMAC_CKEN_RX_OUT
229611. DWMAC_CKEN_TXN_OUT
229612. DWMAC_CKEN_TX_IN
229613. DWMAC_CKEN_TX_OUT
229614. DWMAC_CORE_3_40
229615. DWMAC_CORE_3_50
229616. DWMAC_CORE_4_00
229617. DWMAC_CORE_4_10
229618. DWMAC_CORE_5_00
229619. DWMAC_CORE_5_10
229620. DWMAC_LOW_TX_SOURCE
229621. DWMAC_RGMII
229622. DWMAC_RXN_VARDELAY
229623. DWMAC_RXN_VARDELAY_SHIFT
229624. DWMAC_RX_SOURCE
229625. DWMAC_RX_VARDELAY
229626. DWMAC_RX_VARDELAY_SHIFT
229627. DWMAC_SIMPLE_MUX
229628. DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID
229629. DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID
229630. DWMAC_TXN_VARDELAY
229631. DWMAC_TXN_VARDELAY_SHIFT
229632. DWMAC_TX_SOURCE
229633. DWMAC_TX_VARDELAY
229634. DWMAC_TX_VARDELAY_SHIFT
229635. DWMMC_SDIO_ID
229636. DWORD
229637. DWORDS_TO_BYTES
229638. DWORD_BYTE_SWAP_BOTH_SWAP
229639. DWORD_BYTE_SWAP_BYTE_SWAP
229640. DWORD_BYTE_SWAP_NO_SWAP
229641. DWORD_BYTE_SWAP_WORD_SWAP
229642. DWORD_DATA
229643. DWORD_FIELD
229644. DWORD_MASK
229645. DWORD_REG_BITS_IS_ON
229646. DWORD_REG_BITS_OFF
229647. DWORD_REG_BITS_ON
229648. DWORD_REG_BITS_SET
229649. DWORD_SELECT
229650. DWR_ABPCK_2_BIT_PER_CLK
229651. DWR_ABPCK_4_BIT_PER_CLK
229652. DWR_ABPCK_BIT_PER_CLK
229653. DWR_DBPCK_2_BIT_PER_CLK
229654. DWR_DBPCK_4_BIT_PER_CLK
229655. DWR_DBPCK_BIT_PER_CLK
229656. DWXGMAC_CORE_2_10
229657. DW_CFA_GNU_args_size
229658. DW_CFA_GNU_negative_offset_extended
229659. DW_CFA_GNU_window_save
229660. DW_CFA_advance_loc
229661. DW_CFA_advance_loc1
229662. DW_CFA_advance_loc2
229663. DW_CFA_advance_loc4
229664. DW_CFA_def_cfa
229665. DW_CFA_def_cfa_expression
229666. DW_CFA_def_cfa_offset
229667. DW_CFA_def_cfa_offset_sf
229668. DW_CFA_def_cfa_register
229669. DW_CFA_def_cfa_sf
229670. DW_CFA_expression
229671. DW_CFA_hi_user
229672. DW_CFA_lo_user
229673. DW_CFA_nop
229674. DW_CFA_offset
229675. DW_CFA_offset_extended
229676. DW_CFA_offset_extended_sf
229677. DW_CFA_opcode
229678. DW_CFA_operand
229679. DW_CFA_register
229680. DW_CFA_remember_state
229681. DW_CFA_restore
229682. DW_CFA_restore_extended
229683. DW_CFA_restore_state
229684. DW_CFA_same_value
229685. DW_CFA_set_loc
229686. DW_CFA_undefined
229687. DW_CFA_val_expression
229688. DW_CFA_val_offset
229689. DW_CFA_val_offset_sf
229690. DW_CFG_DMA_EN
229691. DW_CIE_ID
229692. DW_DMAC_HPROT1_PRIVILEGED_MODE
229693. DW_DMAC_HPROT2_BUFFERABLE
229694. DW_DMAC_HPROT3_CACHEABLE
229695. DW_DMA_BUSWIDTHS
229696. DW_DMA_FC_DP_P2P
229697. DW_DMA_FC_D_M2M
229698. DW_DMA_FC_D_M2P
229699. DW_DMA_FC_D_P2M
229700. DW_DMA_FC_D_P2P
229701. DW_DMA_FC_P_M2P
229702. DW_DMA_FC_P_P2M
229703. DW_DMA_FC_SP_P2P
229704. DW_DMA_IS_CYCLIC
229705. DW_DMA_IS_INITIALIZED
229706. DW_DMA_IS_PAUSED
229707. DW_DMA_IS_SOFT_LLP
229708. DW_DMA_MAX_NR_CHANNELS
229709. DW_DMA_MAX_NR_MASTERS
229710. DW_DMA_MAX_NR_REQUESTS
229711. DW_DMA_MSIZE_1
229712. DW_DMA_MSIZE_128
229713. DW_DMA_MSIZE_16
229714. DW_DMA_MSIZE_256
229715. DW_DMA_MSIZE_32
229716. DW_DMA_MSIZE_4
229717. DW_DMA_MSIZE_64
229718. DW_DMA_MSIZE_8
229719. DW_EDMA_V0_CB
229720. DW_EDMA_V0_CCS
229721. DW_EDMA_V0_LIE
229722. DW_EDMA_V0_LLE
229723. DW_EDMA_V0_LLP
229724. DW_EDMA_V0_RIE
229725. DW_EDMA_V0_TCB
229726. DW_EH_FRAME_CIE
229727. DW_EH_PE_ADJUST
229728. DW_EH_PE_APPL_MASK
229729. DW_EH_PE_FORM
229730. DW_EH_PE_FORMAT_MASK
229731. DW_EH_PE_abs
229732. DW_EH_PE_absptr
229733. DW_EH_PE_aligned
229734. DW_EH_PE_data2
229735. DW_EH_PE_data4
229736. DW_EH_PE_data8
229737. DW_EH_PE_datarel
229738. DW_EH_PE_funcrel
229739. DW_EH_PE_indirect
229740. DW_EH_PE_leb128
229741. DW_EH_PE_native
229742. DW_EH_PE_omit
229743. DW_EH_PE_pcrel
229744. DW_EH_PE_ptr
229745. DW_EH_PE_sdata2
229746. DW_EH_PE_sdata4
229747. DW_EH_PE_sdata8
229748. DW_EH_PE_signed
229749. DW_EH_PE_sleb128
229750. DW_EH_PE_textrel
229751. DW_EH_PE_udata2
229752. DW_EH_PE_udata4
229753. DW_EH_PE_udata8
229754. DW_EH_PE_uleb128
229755. DW_EXT_DWARF64
229756. DW_EXT_HI
229757. DW_EXT_LO
229758. DW_HDMI_AUDIO_H
229759. DW_HDMI_CEC_H
229760. DW_HDMI_PHY_DWC_HDMI20_TX_PHY
229761. DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY
229762. DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC
229763. DW_HDMI_PHY_DWC_HDMI_TX_PHY
229764. DW_HDMI_PHY_DWC_MHL_PHY
229765. DW_HDMI_PHY_DWC_MHL_PHY_HEAC
229766. DW_HDMI_PHY_VENDOR_PHY
229767. DW_HDMI_RES_10
229768. DW_HDMI_RES_12
229769. DW_HDMI_RES_8
229770. DW_HDMI_RES_MAX
229771. DW_I2C_DEV_PMOPS
229772. DW_I2S_MASTER
229773. DW_I2S_QUIRK_16BIT_IDX_OVERRIDE
229774. DW_I2S_QUIRK_COMP_PARAM1
229775. DW_I2S_QUIRK_COMP_REG_OFFSET
229776. DW_I2S_SLAVE
229777. DW_IC_CLR_ACTIVITY
229778. DW_IC_CLR_GEN_CALL
229779. DW_IC_CLR_INTR
229780. DW_IC_CLR_RD_REQ
229781. DW_IC_CLR_RESTART_DET
229782. DW_IC_CLR_RX_DONE
229783. DW_IC_CLR_RX_OVER
229784. DW_IC_CLR_RX_UNDER
229785. DW_IC_CLR_START_DET
229786. DW_IC_CLR_STOP_DET
229787. DW_IC_CLR_TX_ABRT
229788. DW_IC_CLR_TX_OVER
229789. DW_IC_COMP_PARAM_1
229790. DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH
229791. DW_IC_COMP_PARAM_1_SPEED_MODE_MASK
229792. DW_IC_COMP_TYPE
229793. DW_IC_COMP_TYPE_VALUE
229794. DW_IC_COMP_VERSION
229795. DW_IC_CON
229796. DW_IC_CON_10BITADDR_MASTER
229797. DW_IC_CON_10BITADDR_SLAVE
229798. DW_IC_CON_MASTER
229799. DW_IC_CON_RESTART_EN
229800. DW_IC_CON_RX_FIFO_FULL_HLD_CTRL
229801. DW_IC_CON_SLAVE_DISABLE
229802. DW_IC_CON_SPEED_FAST
229803. DW_IC_CON_SPEED_HIGH
229804. DW_IC_CON_SPEED_MASK
229805. DW_IC_CON_SPEED_STD
229806. DW_IC_CON_STOP_DET_IFADDRESSED
229807. DW_IC_CON_TX_EMPTY_CTRL
229808. DW_IC_DATA_CMD
229809. DW_IC_DEFAULT_FUNCTIONALITY
229810. DW_IC_ENABLE
229811. DW_IC_ENABLE_STATUS
229812. DW_IC_ERR_TX_ABRT
229813. DW_IC_FS_SCL_HCNT
229814. DW_IC_FS_SCL_LCNT
229815. DW_IC_HS_SCL_HCNT
229816. DW_IC_HS_SCL_LCNT
229817. DW_IC_INTR_ACTIVITY
229818. DW_IC_INTR_DEFAULT_MASK
229819. DW_IC_INTR_GEN_CALL
229820. DW_IC_INTR_MASK
229821. DW_IC_INTR_MASTER_MASK
229822. DW_IC_INTR_RD_REQ
229823. DW_IC_INTR_RESTART_DET
229824. DW_IC_INTR_RX_DONE
229825. DW_IC_INTR_RX_FULL
229826. DW_IC_INTR_RX_OVER
229827. DW_IC_INTR_RX_UNDER
229828. DW_IC_INTR_SLAVE_MASK
229829. DW_IC_INTR_START_DET
229830. DW_IC_INTR_STAT
229831. DW_IC_INTR_STOP_DET
229832. DW_IC_INTR_TX_ABRT
229833. DW_IC_INTR_TX_EMPTY
229834. DW_IC_INTR_TX_OVER
229835. DW_IC_MASTER
229836. DW_IC_RAW_INTR_STAT
229837. DW_IC_RXFLR
229838. DW_IC_RX_ABRT_SLAVE_ARBLOST
229839. DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO
229840. DW_IC_RX_ABRT_SLAVE_RD_INTX
229841. DW_IC_RX_TL
229842. DW_IC_SAR
229843. DW_IC_SDA_HOLD
229844. DW_IC_SDA_HOLD_MIN_VERS
229845. DW_IC_SDA_HOLD_RX_MASK
229846. DW_IC_SDA_HOLD_RX_SHIFT
229847. DW_IC_SLAVE
229848. DW_IC_SS_SCL_HCNT
229849. DW_IC_SS_SCL_LCNT
229850. DW_IC_STATUS
229851. DW_IC_STATUS_ACTIVITY
229852. DW_IC_STATUS_MASTER_ACTIVITY
229853. DW_IC_STATUS_SLAVE_ACTIVITY
229854. DW_IC_STATUS_TFE
229855. DW_IC_TAR
229856. DW_IC_TAR_10BITADDR_MASTER
229857. DW_IC_TXFLR
229858. DW_IC_TX_ABRT_10ADDR1_NOACK
229859. DW_IC_TX_ABRT_10ADDR2_NOACK
229860. DW_IC_TX_ABRT_10B_RD_NORSTRT
229861. DW_IC_TX_ABRT_7B_ADDR_NOACK
229862. DW_IC_TX_ABRT_GCALL_NOACK
229863. DW_IC_TX_ABRT_GCALL_READ
229864. DW_IC_TX_ABRT_MASTER_DIS
229865. DW_IC_TX_ABRT_NOACK
229866. DW_IC_TX_ABRT_SBYTE_ACKDET
229867. DW_IC_TX_ABRT_SBYTE_NORSTRT
229868. DW_IC_TX_ABRT_SOURCE
229869. DW_IC_TX_ABRT_TXDATA_NOACK
229870. DW_IC_TX_ARB_LOST
229871. DW_IC_TX_TL
229872. DW_LENGTH_MASK
229873. DW_LNS_num_opcode
229874. DW_MCI_CAPABILITIES
229875. DW_MCI_CMD_ERROR_FLAGS
229876. DW_MCI_DATA_ERROR_FLAGS
229877. DW_MCI_DESC_DATA_LENGTH
229878. DW_MCI_DMA_THRESHOLD
229879. DW_MCI_ERROR_FLAGS
229880. DW_MCI_FREQ_MAX
229881. DW_MCI_FREQ_MIN
229882. DW_MCI_RECV_STATUS
229883. DW_MCI_SEND_STATUS
229884. DW_MCI_TYPE_EXYNOS4210
229885. DW_MCI_TYPE_EXYNOS4412
229886. DW_MCI_TYPE_EXYNOS5250
229887. DW_MCI_TYPE_EXYNOS5420
229888. DW_MCI_TYPE_EXYNOS5420_SMU
229889. DW_MCI_TYPE_EXYNOS7
229890. DW_MCI_TYPE_EXYNOS7_SMU
229891. DW_MIPI_NEEDS_GRF_CLK
229892. DW_MIPI_NEEDS_PHY_CFG_CLK
229893. DW_MMC_240A
229894. DW_MMC_280A
229895. DW_MMC_CARD_NEEDS_POLL
229896. DW_MMC_CARD_NEED_INIT
229897. DW_MMC_CARD_NO_LOW_PWR
229898. DW_MMC_CARD_NO_USE_HOLD
229899. DW_MMC_CARD_PRESENT
229900. DW_OP_abs
229901. DW_OP_addr
229902. DW_OP_and
229903. DW_OP_bit_piece
229904. DW_OP_bra
229905. DW_OP_breg0
229906. DW_OP_breg1
229907. DW_OP_breg10
229908. DW_OP_breg11
229909. DW_OP_breg12
229910. DW_OP_breg13
229911. DW_OP_breg14
229912. DW_OP_breg15
229913. DW_OP_breg16
229914. DW_OP_breg17
229915. DW_OP_breg18
229916. DW_OP_breg19
229917. DW_OP_breg2
229918. DW_OP_breg20
229919. DW_OP_breg21
229920. DW_OP_breg22
229921. DW_OP_breg23
229922. DW_OP_breg24
229923. DW_OP_breg25
229924. DW_OP_breg26
229925. DW_OP_breg27
229926. DW_OP_breg28
229927. DW_OP_breg29
229928. DW_OP_breg3
229929. DW_OP_breg30
229930. DW_OP_breg31
229931. DW_OP_breg4
229932. DW_OP_breg5
229933. DW_OP_breg6
229934. DW_OP_breg7
229935. DW_OP_breg8
229936. DW_OP_breg9
229937. DW_OP_bregx
229938. DW_OP_call2
229939. DW_OP_call4
229940. DW_OP_call_frame_cfa
229941. DW_OP_call_ref
229942. DW_OP_const1s
229943. DW_OP_const1u
229944. DW_OP_const2s
229945. DW_OP_const2u
229946. DW_OP_const4s
229947. DW_OP_const4u
229948. DW_OP_const8s
229949. DW_OP_const8u
229950. DW_OP_consts
229951. DW_OP_constu
229952. DW_OP_deref
229953. DW_OP_deref_size
229954. DW_OP_div
229955. DW_OP_drop
229956. DW_OP_dup
229957. DW_OP_eq
229958. DW_OP_fbreg
229959. DW_OP_form_tls_address
229960. DW_OP_ge
229961. DW_OP_gt
229962. DW_OP_hi_user
229963. DW_OP_le
229964. DW_OP_lit0
229965. DW_OP_lit1
229966. DW_OP_lit10
229967. DW_OP_lit11
229968. DW_OP_lit12
229969. DW_OP_lit13
229970. DW_OP_lit14
229971. DW_OP_lit15
229972. DW_OP_lit16
229973. DW_OP_lit17
229974. DW_OP_lit18
229975. DW_OP_lit19
229976. DW_OP_lit2
229977. DW_OP_lit20
229978. DW_OP_lit21
229979. DW_OP_lit22
229980. DW_OP_lit23
229981. DW_OP_lit24
229982. DW_OP_lit25
229983. DW_OP_lit26
229984. DW_OP_lit27
229985. DW_OP_lit28
229986. DW_OP_lit29
229987. DW_OP_lit3
229988. DW_OP_lit30
229989. DW_OP_lit31
229990. DW_OP_lit4
229991. DW_OP_lit5
229992. DW_OP_lit6
229993. DW_OP_lit7
229994. DW_OP_lit8
229995. DW_OP_lit9
229996. DW_OP_lo_user
229997. DW_OP_lt
229998. DW_OP_minus
229999. DW_OP_mod
230000. DW_OP_mul
230001. DW_OP_ne
230002. DW_OP_neg
230003. DW_OP_nop
230004. DW_OP_not
230005. DW_OP_or
230006. DW_OP_over
230007. DW_OP_pick
230008. DW_OP_piece
230009. DW_OP_plus
230010. DW_OP_plus_uconst
230011. DW_OP_push_object_address
230012. DW_OP_reg0
230013. DW_OP_reg1
230014. DW_OP_reg10
230015. DW_OP_reg11
230016. DW_OP_reg12
230017. DW_OP_reg13
230018. DW_OP_reg14
230019. DW_OP_reg15
230020. DW_OP_reg16
230021. DW_OP_reg17
230022. DW_OP_reg18
230023. DW_OP_reg19
230024. DW_OP_reg2
230025. DW_OP_reg20
230026. DW_OP_reg21
230027. DW_OP_reg22
230028. DW_OP_reg23
230029. DW_OP_reg24
230030. DW_OP_reg25
230031. DW_OP_reg26
230032. DW_OP_reg27
230033. DW_OP_reg28
230034. DW_OP_reg29
230035. DW_OP_reg3
230036. DW_OP_reg30
230037. DW_OP_reg31
230038. DW_OP_reg4
230039. DW_OP_reg5
230040. DW_OP_reg6
230041. DW_OP_reg7
230042. DW_OP_reg8
230043. DW_OP_reg9
230044. DW_OP_regx
230045. DW_OP_rot
230046. DW_OP_shl
230047. DW_OP_shr
230048. DW_OP_shra
230049. DW_OP_skip
230050. DW_OP_swap
230051. DW_OP_xderef
230052. DW_OP_xderef_size
230053. DW_OP_xor
230054. DW_PARAMS_DATA_WIDTH
230055. DW_PARAMS_DATA_WIDTH1
230056. DW_PARAMS_DATA_WIDTH2
230057. DW_PARAMS_DATA_WIDTH3
230058. DW_PARAMS_DATA_WIDTH4
230059. DW_PARAMS_EN
230060. DW_PARAMS_NR_CHAN
230061. DW_PARAMS_NR_MASTER
230062. DW_PCIE_AS_IO
230063. DW_PCIE_AS_MEM
230064. DW_PCIE_AS_UNKNOWN
230065. DW_PCIE_EP_TYPE
230066. DW_PCIE_LEG_EP_TYPE
230067. DW_PCIE_RC_TYPE
230068. DW_PCIE_REGION_INBOUND
230069. DW_PCIE_REGION_OUTBOUND
230070. DW_PCIE_REGION_UNKNOWN
230071. DW_PCIE_UNKNOWN_TYPE
230072. DW_PER_PAGE
230073. DW_REG
230074. DW_SPI_BAUDR
230075. DW_SPI_CS_OVERRIDE
230076. DW_SPI_CTRL0
230077. DW_SPI_CTRL1
230078. DW_SPI_DMACR
230079. DW_SPI_DMARDLR
230080. DW_SPI_DMATDLR
230081. DW_SPI_DR
230082. DW_SPI_HEADER_H
230083. DW_SPI_ICR
230084. DW_SPI_IDR
230085. DW_SPI_IMR
230086. DW_SPI_ISR
230087. DW_SPI_MSTICR
230088. DW_SPI_MWCR
230089. DW_SPI_RISR
230090. DW_SPI_RXFLR
230091. DW_SPI_RXFLTR
230092. DW_SPI_RXOICR
230093. DW_SPI_RXUICR
230094. DW_SPI_SER
230095. DW_SPI_SR
230096. DW_SPI_SSIENR
230097. DW_SPI_TXFLR
230098. DW_SPI_TXFLTR
230099. DW_SPI_TXOICR
230100. DW_SPI_VERSION
230101. DW_UART_CPR
230102. DW_UART_CPR_ABP_DATA_WIDTH
230103. DW_UART_CPR_ADDITIONAL_FEATURES
230104. DW_UART_CPR_AFCE_MODE
230105. DW_UART_CPR_DMA_EXTRA
230106. DW_UART_CPR_ENCODED_PARMS
230107. DW_UART_CPR_FIFO_ACCESS
230108. DW_UART_CPR_FIFO_MODE
230109. DW_UART_CPR_FIFO_SIZE
230110. DW_UART_CPR_FIFO_STAT
230111. DW_UART_CPR_SHADOW
230112. DW_UART_CPR_SIR_LP_MODE
230113. DW_UART_CPR_SIR_MODE
230114. DW_UART_CPR_THRE_MODE
230115. DW_UART_DLF
230116. DW_UART_MCR_SIRE
230117. DW_UART_UCV
230118. DW_UART_USR
230119. DW_WDT_DEFAULT_SECONDS
230120. DW_WDT_MAX_TOP
230121. DWordIO_t
230122. DWstruct
230123. DWtype
230124. DWunion
230125. DX
230126. DX10_CLAMP
230127. DX9_CONSTS
230128. DXCLIP_DIRECTX
230129. DXCLIP_OPENGL
230130. DXD
230131. DXD_CORRUPT
230132. DXD_EXTENT
230133. DXD_FILE
230134. DXD_INDEX
230135. DXD_INLINE
230136. DXDaddress
230137. DXDlength
230138. DXDsize
230139. DXENA
230140. DXENDLY
230141. DXEPCTL_CNAK
230142. DXEPCTL_DPID
230143. DXEPCTL_EOFRNUM
230144. DXEPCTL_EPDIS
230145. DXEPCTL_EPENA
230146. DXEPCTL_EPTYPE_BULK
230147. DXEPCTL_EPTYPE_CONTROL
230148. DXEPCTL_EPTYPE_INTERRUPT
230149. DXEPCTL_EPTYPE_ISO
230150. DXEPCTL_EPTYPE_MASK
230151. DXEPCTL_MPS
230152. DXEPCTL_MPS_LIMIT
230153. DXEPCTL_MPS_MASK
230154. DXEPCTL_MPS_SHIFT
230155. DXEPCTL_NAKSTS
230156. DXEPCTL_NEXTEP
230157. DXEPCTL_NEXTEP_LIMIT
230158. DXEPCTL_NEXTEP_MASK
230159. DXEPCTL_NEXTEP_SHIFT
230160. DXEPCTL_SETD0PID
230161. DXEPCTL_SETD1PID
230162. DXEPCTL_SETEVENFR
230163. DXEPCTL_SETODDFR
230164. DXEPCTL_SNAK
230165. DXEPCTL_SNP
230166. DXEPCTL_STALL
230167. DXEPCTL_TXFNUM
230168. DXEPCTL_TXFNUM_LIMIT
230169. DXEPCTL_TXFNUM_MASK
230170. DXEPCTL_TXFNUM_SHIFT
230171. DXEPCTL_USBACTEP
230172. DXEPINT_AHBERR
230173. DXEPINT_BACK2BACKSETUP
230174. DXEPINT_BBLEERRINTRPT
230175. DXEPINT_BNAINTR
230176. DXEPINT_EPDISBLD
230177. DXEPINT_INEPNAKEFF
230178. DXEPINT_INTKNEPMIS
230179. DXEPINT_INTKNTXFEMP
230180. DXEPINT_NAKINTRPT
230181. DXEPINT_NYETINTRPT
230182. DXEPINT_OUTPKTERR
230183. DXEPINT_OUTTKNEPDIS
230184. DXEPINT_PKTDRPSTS
230185. DXEPINT_SETUP
230186. DXEPINT_SETUP_RCVD
230187. DXEPINT_STSPHSERCVD
230188. DXEPINT_TIMEOUT
230189. DXEPINT_TXFEMP
230190. DXEPINT_TXFIFOUNDRN
230191. DXEPINT_XFERCOMPL
230192. DXEPTSIZ_MC
230193. DXEPTSIZ_MC_LIMIT
230194. DXEPTSIZ_MC_MASK
230195. DXEPTSIZ_MC_SHIFT
230196. DXEPTSIZ_PKTCNT
230197. DXEPTSIZ_PKTCNT_GET
230198. DXEPTSIZ_PKTCNT_LIMIT
230199. DXEPTSIZ_PKTCNT_MASK
230200. DXEPTSIZ_PKTCNT_SHIFT
230201. DXEPTSIZ_XFERSIZE
230202. DXEPTSIZ_XFERSIZE_GET
230203. DXEPTSIZ_XFERSIZE_LIMIT
230204. DXEPTSIZ_XFERSIZE_MASK
230205. DXEPTSIZ_XFERSIZE_SHIFT
230206. DXIO_CFG_SOFT_RESET__shadow_debug_reset0_MASK
230207. DXIO_CFG_SOFT_RESET__shadow_debug_reset0__SHIFT
230208. DXIO_CFG_SOFT_RESET__shadow_debug_reset1_MASK
230209. DXIO_CFG_SOFT_RESET__shadow_debug_reset1__SHIFT
230210. DXIO_CFG_SOFT_RESET__shadow_debug_reset2_MASK
230211. DXIO_CFG_SOFT_RESET__shadow_debug_reset2__SHIFT
230212. DXIO_CFG_SOFT_RESET__shadow_debug_reset3_MASK
230213. DXIO_CFG_SOFT_RESET__shadow_debug_reset3__SHIFT
230214. DXIO_CFG_SOFT_RESET__shadow_debug_reset4_MASK
230215. DXIO_CFG_SOFT_RESET__shadow_debug_reset4__SHIFT
230216. DXIO_CFG_SOFT_RESET__shadow_debug_reset5_MASK
230217. DXIO_CFG_SOFT_RESET__shadow_debug_reset5__SHIFT
230218. DXIO_CFG_SOFT_RESET__shadow_debug_reset6_MASK
230219. DXIO_CFG_SOFT_RESET__shadow_debug_reset6__SHIFT
230220. DXIO_CFG_SOFT_RESET__shadow_debug_reset7_MASK
230221. DXIO_CFG_SOFT_RESET__shadow_debug_reset7__SHIFT
230222. DXIO_HWDID__Hardware_Major_Version_Number_MASK
230223. DXIO_HWDID__Hardware_Major_Version_Number__SHIFT
230224. DXIO_HWDID__Hardware_Minor_Version_Number_MASK
230225. DXIO_HWDID__Hardware_Minor_Version_Number__SHIFT
230226. DXIO_HWDID__Hardware_Revision_MASK
230227. DXIO_HWDID__Hardware_Revision__SHIFT
230228. DXIO_HWDID__PCS_Vendor_ID_MASK
230229. DXIO_HWDID__PCS_Vendor_ID__SHIFT
230230. DXIO_HWDID__Protocol_PCS_MASK
230231. DXIO_HWDID__Protocol_PCS__SHIFT
230232. DXIO_LINKAGE_KPDMX__Base_Offset_MASK
230233. DXIO_LINKAGE_KPDMX__Base_Offset__SHIFT
230234. DXIO_LINKAGE_KPDMX__Overlay_MASK
230235. DXIO_LINKAGE_KPDMX__Overlay__SHIFT
230236. DXIO_LINKAGE_KPDMX__Presence_MASK
230237. DXIO_LINKAGE_KPDMX__Presence__SHIFT
230238. DXIO_LINKAGE_KPFIFO__Base_Offset_MASK
230239. DXIO_LINKAGE_KPFIFO__Base_Offset__SHIFT
230240. DXIO_LINKAGE_KPFIFO__Frame_Size_MASK
230241. DXIO_LINKAGE_KPFIFO__Frame_Size__SHIFT
230242. DXIO_LINKAGE_KPFIFO__Overlay_MASK
230243. DXIO_LINKAGE_KPFIFO__Overlay__SHIFT
230244. DXIO_LINKAGE_KPMX__Base_Offset_MASK
230245. DXIO_LINKAGE_KPMX__Base_Offset__SHIFT
230246. DXIO_LINKAGE_KPMX__Frame_Size_MASK
230247. DXIO_LINKAGE_KPMX__Frame_Size__SHIFT
230248. DXIO_LINKAGE_KPMX__Overlay_MASK
230249. DXIO_LINKAGE_KPMX__Overlay__SHIFT
230250. DXIO_LINKAGE_KPNP__Base_Offset_MASK
230251. DXIO_LINKAGE_KPNP__Base_Offset__SHIFT
230252. DXIO_LINKAGE_KPNP__Frame_Size_MASK
230253. DXIO_LINKAGE_KPNP__Frame_Size__SHIFT
230254. DXIO_LINKAGE_KPNP__Overlay_MASK
230255. DXIO_LINKAGE_KPNP__Overlay__SHIFT
230256. DXIO_LINKAGE_LANEGRP__Index_Offset_MASK
230257. DXIO_LINKAGE_LANEGRP__Index_Offset__SHIFT
230258. DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size_MASK
230259. DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size__SHIFT
230260. DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses_MASK
230261. DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses__SHIFT
230262. DXIO_LINKAGE_LANEGRP__Presence_MASK
230263. DXIO_LINKAGE_LANEGRP__Presence__SHIFT
230264. DXInfo
230265. DXMT2PD
230266. DXMTFCS
230267. DX_AC97_BUSY_READ
230268. DX_AC97_BUSY_WRITE
230269. DX_AC97_PLAYBACK
230270. DX_AC97_READY
230271. DX_AC97_RECORD
230272. DX_ACR0_AC97_W
230273. DX_ACR1_AC97_R
230274. DX_ACR2_AC97_COM_STAT
230275. DX_HASH_HALF_MD4
230276. DX_HASH_HALF_MD4_UNSIGNED
230277. DX_HASH_LEGACY
230278. DX_HASH_LEGACY_UNSIGNED
230279. DX_HASH_TEA
230280. DX_HASH_TEA_UNSIGNED
230281. DX_MASK
230282. DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE
230283. DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0
230284. DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1
230285. DX_REG_M
230286. DX_REG_N
230287. DX_STAT
230288. DYING
230289. DYING_NULLS_VAL
230290. DYNACK_H
230291. DYNAMIC
230292. DYNAMICE_ENGINE_SETTINGS_PARAMETER
230293. DYNAMICE_MC_DPM_SETTINGS_PARAMETER
230294. DYNAMICE_MEMORY_SETTINGS_PARAMETER
230295. DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1
230296. DYNAMIC_ALL_FUNC_ENABLE
230297. DYNAMIC_BB_ADAPTIVITY
230298. DYNAMIC_BB_ANT_DIV
230299. DYNAMIC_BB_BB_FA_CNT
230300. DYNAMIC_BB_CCK_PD
230301. DYNAMIC_BB_DIG
230302. DYNAMIC_BB_DYNAMIC_ATC
230303. DYNAMIC_BB_DYNAMIC_TXPWR
230304. DYNAMIC_BB_PATH_DIV
230305. DYNAMIC_BB_PSD
230306. DYNAMIC_BB_PWR_SAVE
230307. DYNAMIC_BB_PWR_TRA
230308. DYNAMIC_BB_PWR_TRAIN
230309. DYNAMIC_BB_RATE_ADAPTIVE
230310. DYNAMIC_BB_RA_MASK
230311. DYNAMIC_BB_RSSI_MONITOR
230312. DYNAMIC_BB_RXHP
230313. DYNAMIC_BUFFERS
230314. DYNAMIC_BURST
230315. DYNAMIC_CAMID_ALLOC
230316. DYNAMIC_CHK_WK_CID
230317. DYNAMIC_CLOCK_GATING_PARAMETERS
230318. DYNAMIC_CLOCK_GATING_PS_ALLOCATION
230319. DYNAMIC_DEBUG_BRANCH
230320. DYNAMIC_DEEP_SLEEP_EN
230321. DYNAMIC_DEEP_SLEEP_ENABLE
230322. DYNAMIC_FUNC_ANT_DIV
230323. DYNAMIC_FUNC_BT
230324. DYNAMIC_FUNC_DIG
230325. DYNAMIC_FUNC_DISABLE
230326. DYNAMIC_FUNC_HP
230327. DYNAMIC_FUNC_SS
230328. DYNAMIC_GFX_ISLAND_PWR_DOWN
230329. DYNAMIC_GFX_ISLAND_PWR_LP
230330. DYNAMIC_LIGHT_SLEEP_EN
230331. DYNAMIC_LIGHT_SLEEP_ENABLE
230332. DYNAMIC_MAC_EARLY_MODE
230333. DYNAMIC_MAC_EDCA_TURBO
230334. DYNAMIC_MAC_ENTRIES_H_S
230335. DYNAMIC_MAC_ENTRIES_H_SHIFT
230336. DYNAMIC_MAC_ENTRIES_S
230337. DYNAMIC_MAC_ENTRIES_SHIFT
230338. DYNAMIC_MAC_FID_S
230339. DYNAMIC_MAC_FID_SHIFT
230340. DYNAMIC_MAC_SRC_PORT_S
230341. DYNAMIC_MAC_SRC_PORT_SHIFT
230342. DYNAMIC_MAC_TABLE_ADDR
230343. DYNAMIC_MAC_TABLE_ENTRIES
230344. DYNAMIC_MAC_TABLE_ENTRIES_H
230345. DYNAMIC_MAC_TABLE_FID
230346. DYNAMIC_MAC_TABLE_MAC_EMPTY
230347. DYNAMIC_MAC_TABLE_NOT_READY
230348. DYNAMIC_MAC_TABLE_RESERVED
230349. DYNAMIC_MAC_TABLE_SRC_PORT
230350. DYNAMIC_MAC_TABLE_TIMESTAMP
230351. DYNAMIC_MAC_TIMESTAMP_S
230352. DYNAMIC_MAC_TIMESTAMP_SHIFT
230353. DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE
230354. DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE
230355. DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE
230356. DYNAMIC_MINORS
230357. DYNAMIC_NOISE_CONTROL_FORMATTER
230358. DYNAMIC_PIXEL_DEPTH_30BPP
230359. DYNAMIC_PIXEL_DEPTH_36BPP
230360. DYNAMIC_PM_EN
230361. DYNAMIC_PORT_MAX
230362. DYNAMIC_PORT_MIN
230363. DYNAMIC_POWER
230364. DYNAMIC_RF_CALIBRATION
230365. DYNAMIC_RF_RX_GAIN_TRACK
230366. DYNAMIC_RF_TX_PWR_TRACK
230367. DYNAMIC_SHUT_DOWN_ENABLE
230368. DYNAMIC_STOP_EXCESS
230369. DYNAMIC_TABLE_DIR
230370. DYNAMIC_VOLTAGE_SCALAR
230371. DYNAMIC_WMM_PS
230372. DYNAPRO_FORMAT_LENGTH
230373. DYNAPRO_FORMAT_TOUCH_BIT
230374. DYNAPRO_GET_TOUCHED
230375. DYNAPRO_GET_XC
230376. DYNAPRO_GET_YC
230377. DYNAPRO_MAX_XC
230378. DYNAPRO_MAX_YC
230379. DYNAPRO_MIN_XC
230380. DYNAPRO_MIN_YC
230381. DYNAPRO_RESPONSE_BEGIN_BYTE
230382. DYNMEM_MAJOR_VERSION
230383. DYNMEM_MAKE_VERSION
230384. DYNMEM_MINOR_VERSION
230385. DYNMEM_PROTOCOL_VERSION_1
230386. DYNMEM_PROTOCOL_VERSION_2
230387. DYNMEM_PROTOCOL_VERSION_3
230388. DYNMEM_PROTOCOL_VERSION_CURRENT
230389. DYNMEM_PROTOCOL_VERSION_WIN10
230390. DYNMEM_PROTOCOL_VERSION_WIN7
230391. DYNMEM_PROTOCOL_VERSION_WIN8
230392. DYNPM_ACTION_DEFAULT
230393. DYNPM_ACTION_DOWNCLOCK
230394. DYNPM_ACTION_MINIMUM
230395. DYNPM_ACTION_NONE
230396. DYNPM_ACTION_UPCLOCK
230397. DYNPM_STATE_ACTIVE
230398. DYNPM_STATE_DISABLED
230399. DYNPM_STATE_MINIMUM
230400. DYNPM_STATE_PAUSED
230401. DYNPM_STATE_SUSPENDED
230402. DYNTICK_IRQ_NONIDLE
230403. DYN_BACKBIAS_CNTL
230404. DYN_COLOR_DIS
230405. DYN_COLOR_EN
230406. DYN_DEPTH
230407. DYN_DEPTH_16BPP
230408. DYN_DEPTH_24BPP
230409. DYN_DEPTH_32BPP
230410. DYN_DEPTH_8BPP
230411. DYN_DEPTH_ENABLE
230412. DYN_FTRACE_TEST_NAME
230413. DYN_FTRACE_TEST_NAME2
230414. DYN_GFX_CLK_OFF_EN
230415. DYN_GFX_CLK_OFF_MC_EN
230416. DYN_GPR_ENABLE
230417. DYN_LIGHT_SLEEP_EN
230418. DYN_ODT_MASK
230419. DYN_ODT_SHIFT
230420. DYN_OR_EN
230421. DYN_PER_CU_PG_ENABLE
230422. DYN_PER_SIMD_PG_ENABLE
230423. DYN_PWRMGT_SCLK_LENGTH
230424. DYN_PWR_DOWN_EN
230425. DYN_PWR_ENTER_INDEX
230426. DYN_PWR_ENTER_INDEX_MASK
230427. DYN_PWR_ENTER_INDEX_SHIFT
230428. DYN_RR_EN
230429. DYN_SCLK_VOL_CNTL
230430. DYN_SPREAD_SPECTRUM_EN
230431. DYN_STOP_LAT_MASK
230432. DYN_TREES
230433. DZE_STAT
230434. DZ_B110
230435. DZ_B1200
230436. DZ_B134
230437. DZ_B150
230438. DZ_B1800
230439. DZ_B2000
230440. DZ_B2400
230441. DZ_B300
230442. DZ_B3600
230443. DZ_B4800
230444. DZ_B50
230445. DZ_B600
230446. DZ_B7200
230447. DZ_B75
230448. DZ_B9600
230449. DZ_BREAK
230450. DZ_BRK0
230451. DZ_BRK1
230452. DZ_BRK2
230453. DZ_BRK3
230454. DZ_CBAUD
230455. DZ_CLR
230456. DZ_CS5
230457. DZ_CS6
230458. DZ_CS7
230459. DZ_CS8
230460. DZ_CSIZE
230461. DZ_CSR
230462. DZ_CSTOPB
230463. DZ_DVAL
230464. DZ_FERR
230465. DZ_HASHMASK
230466. DZ_KEYBOARD
230467. DZ_LINE_KEYBOARD
230468. DZ_LINE_MASK
230469. DZ_LINE_MODEM
230470. DZ_LINE_MOUSE
230471. DZ_LINE_PRINTER
230472. DZ_LNENB
230473. DZ_LPR
230474. DZ_MAINT
230475. DZ_MASK
230476. DZ_MODEM
230477. DZ_MODEM_CD
230478. DZ_MODEM_CTS
230479. DZ_MODEM_DSR
230480. DZ_MODEM_DTR
230481. DZ_MODEM_RI
230482. DZ_MODEM_RTS
230483. DZ_MOUSE
230484. DZ_MSE
230485. DZ_MSR
230486. DZ_NB_PORT
230487. DZ_OERR
230488. DZ_PARENB
230489. DZ_PARODD
230490. DZ_PERR
230491. DZ_PRINTER
230492. DZ_PRINT_CD
230493. DZ_PRINT_CTS
230494. DZ_PRINT_DSR
230495. DZ_PRINT_DTR
230496. DZ_PRINT_RI
230497. DZ_PRINT_RTS
230498. DZ_RBUF
230499. DZ_RBUF_MASK
230500. DZ_RDONE
230501. DZ_RIE
230502. DZ_RXENAB
230503. DZ_SERIAL_H
230504. DZ_TCR
230505. DZ_TDR
230506. DZ_TIE
230507. DZ_TLINE
230508. DZ_TRDY
230509. DZ_WAKEUP_CHARS
230510. DZ_XMIT_SIZE
230511. D_11A_ONLY_MODE
230512. D_11BG_COMPATIBLE_MODE
230513. D_11B_ONLY_MODE
230514. D_11G_ONLY_MODE
230515. D_11H
230516. D_20
230517. D_36
230518. D_ALL
230519. D_AP
230520. D_AR0
230521. D_AR1
230522. D_ASSERT
230523. D_ASSOC
230524. D_ATTACHING
230525. D_BDW
230526. D_BDW_PLUS
230527. D_BIG_END
230528. D_BITS
230529. D_BUCKET
230530. D_BXT
230531. D_C
230532. D_CACHE_LINE_SIZE
230533. D_CALIB
230534. D_CDEC
230535. D_CDEC_CK
230536. D_CDEC_FED
230537. D_CDEC_RED
230538. D_CDM
230539. D_CDM_RCE
230540. D_CDM_REN
230541. D_CDM_RHI
230542. D_CDM_THI
230543. D_CDM_XCE
230544. D_CDM_XEN
230545. D_CDP
230546. D_CFL
230547. D_CHI
230548. D_CHI_BPF
230549. D_CHI_CHICM
230550. D_CHI_EN
230551. D_CHI_FD
230552. D_CHI_FE
230553. D_CHI_IR
230554. D_CHI_OD
230555. D_CMD
230556. D_CODES
230557. D_COMP_BDW
230558. D_COMP_COMP_DISABLE
230559. D_COMP_COMP_FORCE
230560. D_COMP_HSW
230561. D_COMP_RCOMP_IN_PROGRESS
230562. D_CONF
230563. D_CONSISTENT
230564. D_CUT_VERSION
230565. D_D
230566. D_DEBUG
230567. D_DESC
230568. D_DISKLESS
230569. D_DIV
230570. D_DLY
230571. D_DMA_OFF
230572. D_DMA_RUNNING
230573. D_DONE
230574. D_DROP
230575. D_DTS
230576. D_DTS_DEL
230577. D_DTS_INS
230578. D_DTS_PRVIN
230579. D_DTS_PRVOUT
230580. D_DTS_VI
230581. D_DTS_VO
230582. D_DURING
230583. D_E
230584. D_EEPROM
230585. D_ENPIO
230586. D_ENPIO0
230587. D_ENPIO1
230588. D_ENPIO2
230589. D_ENPIO3
230590. D_EXTRA
230591. D_F
230592. D_FAILED
230593. D_FFC
230594. D_FIFO_SIZE
230595. D_FLAG_VERIFY
230596. D_FRAM
230597. D_FREG_MASK
230598. D_FS_RAM_SIZE_BULK
230599. D_FW
230600. D_G
230601. D_GATE
230602. D_GEN
230603. D_GEN8PLUS
230604. D_GEN9PLUS
230605. D_GEO
230606. D_H
230607. D_HC
230608. D_HC_DUMP
230609. D_HIGH
230610. D_HS_RAM_SIZE_BULK
230611. D_HT
230612. D_ID
230613. D_IDX
230614. D_IIQ
230615. D_INCONSISTENT
230616. D_INFO
230617. D_INIT
230618. D_INIT_REASONS
230619. D_INT
230620. D_INTR_BRDY
230621. D_INTR_CHI
230622. D_INTR_CHIL
230623. D_INTR_CMD
230624. D_INTR_CMDI
230625. D_INTR_COLL
230626. D_INTR_DBYT
230627. D_INTR_EOL
230628. D_INTR_FXDT
230629. D_INTR_GETCHAN
230630. D_INTR_GETCMD
230631. D_INTR_GETCODE
230632. D_INTR_GETRVAL
230633. D_INTR_GETVAL
230634. D_INTR_IBEG
230635. D_INTR_IEND
230636. D_INTR_LINT
230637. D_INTR_MINT
230638. D_INTR_NT
230639. D_INTR_RBYT
230640. D_INTR_SBRI
230641. D_INTR_TE
230642. D_INTR_UNDR
230643. D_INTR_XCMP
230644. D_IR
230645. D_ISR
230646. D_JUMP
230647. D_KBL
230648. D_LBG
230649. D_LED
230650. D_LEN
230651. D_LEVEL
230652. D_LEVEL_SIZE
230653. D_LINK_V100
230654. D_LITTLE_END
230655. D_LLUE
230656. D_LUN
230657. D_MAC80211
230658. D_MACDUMP
230659. D_MASK
230660. D_MASTER
230661. D_MBE
230662. D_MLE
230663. D_MM
230664. D_MOD
230665. D_MODULE
230666. D_MODULENAME
230667. D_MRR
230668. D_N
230669. D_NEGOTIATING
230670. D_NORMAL
230671. D_NOTIF
230672. D_NT
230673. D_NT_ABV
230674. D_NT_ACT
230675. D_NT_EZ
230676. D_NT_FACT
230677. D_NT_FBIT
230678. D_NT_FT
230679. D_NT_IFA
230680. D_NT_IRM_EN
230681. D_NT_IRM_IMM
230682. D_NT_ISNT
230683. D_NT_LLB
230684. D_NT_MFE
230685. D_NT_NBF
230686. D_NT_RLB
230687. D_OUTDATED
230688. D_P
230689. D_PACK
230690. D_PARTIAL
230691. D_PAUSE
230692. D_PIO0
230693. D_PIO1
230694. D_PIO2
230695. D_PIO3
230696. D_PIPE
230697. D_POS
230698. D_POWER
230699. D_PREP
230700. D_PRE_SKL
230701. D_PRO
230702. D_PROBE
230703. D_PROTO
230704. D_PRT
230705. D_P_0
230706. D_P_1
230707. D_P_10
230708. D_P_11
230709. D_P_12
230710. D_P_13
230711. D_P_14
230712. D_P_15
230713. D_P_16
230714. D_P_17
230715. D_P_18
230716. D_P_19
230717. D_P_2
230718. D_P_20
230719. D_P_21
230720. D_P_22
230721. D_P_23
230722. D_P_24
230723. D_P_25
230724. D_P_26
230725. D_P_27
230726. D_P_28
230727. D_P_29
230728. D_P_3
230729. D_P_30
230730. D_P_31
230731. D_P_4
230732. D_P_5
230733. D_P_6
230734. D_P_7
230735. D_P_8
230736. D_P_9
230737. D_QOS
230738. D_R
230739. D_RADIO
230740. D_RAM_SIZE_CTRL
230741. D_RATE
230742. D_RECON
230743. D_REG
230744. D_REG_M
230745. D_REG_N
230746. D_REX
230747. D_RF_KILL
230748. D_ROOT
230749. D_RX
230750. D_RX_INTR
230751. D_S
230752. D_SBY
230753. D_SCAN
230754. D_SDP
230755. D_SDP_2SAME
230756. D_SDP_A
230757. D_SDP_C
230758. D_SDP_CHANGE
230759. D_SDP_EOL
230760. D_SDP_EVERY
230761. D_SDP_FIXED
230762. D_SDP_FROM_SER
230763. D_SDP_HDLC
230764. D_SDP_HDLC_D
230765. D_SDP_IDLE
230766. D_SDP_LSB
230767. D_SDP_MEM
230768. D_SDP_MODE
230769. D_SDP_MSB
230770. D_SDP_P
230771. D_SDP_SER
230772. D_SDP_TO_SER
230773. D_SHIFT_LEFT
230774. D_SHIFT_RIGHT
230775. D_SIZE
230776. D_SKB
230777. D_SKB_SIZE
230778. D_SKL
230779. D_SKL_PLUS
230780. D_SLV
230781. D_SSP
230782. D_STATE
230783. D_STATS
230784. D_STREAM
230785. D_SUBMIT
230786. D_SUBMODULE
230787. D_SUBMODULE_DECLARE
230788. D_SUBMODULE_DEFINE
230789. D_SYNC_FORM
230790. D_T
230791. D_TE
230792. D_TEMP
230793. D_TEST
230794. D_TEST_DUMP
230795. D_TEST_MCBIST
230796. D_TEST_PROC
230797. D_TEST_RAM
230798. D_TEST_RAMBIST
230799. D_TEST_RAMREAD
230800. D_TEST_RAMWRITE
230801. D_TEST_ROMONOFF
230802. D_TEST_SER
230803. D_TEST_SIZE
230804. D_TIMING
230805. D_TRINE
230806. D_TS_1CHANNEL
230807. D_TS_ANCHOR
230808. D_TS_CYCLE
230809. D_TS_DI
230810. D_TS_LEN
230811. D_TS_MON
230812. D_TS_MONITOR
230813. D_TS_NEXT
230814. D_TS_NONCONTIG
230815. D_TX
230816. D_TXPOWER
230817. D_TX_INTR
230818. D_TX_MODE
230819. D_TX_REPLY
230820. D_UGATE
230821. D_UNI
230822. D_UNKNOWN
230823. D_UP_TO_DATE
230824. D_USBI
230825. D_USBO
230826. D_USR
230827. D_WAIT
230828. D_WALK_CONTINUE
230829. D_WALK_NORETRY
230830. D_WALK_QUIT
230831. D_WALK_SKIP
230832. D_WEP
230833. D_X
230834. Dad
230835. Dallp1
230836. Dallp2
230837. DataApplicationCapability
230838. DataApplicationCapability_application
230839. DataDynamic
230840. DataInOff
230841. DataInOn
230842. DataProtocolCapability
230843. DataType
230844. Data_error
230845. DbMemArbWatermarks
230846. DbPRTFaultBehavior
230847. DbPSLControl
230848. Dbcol_Bordcol
230849. DbgAntHunt
230850. DbgPrint
230851. Dbit21p2
230852. Dbit28p2
230853. Dbit29p2
230854. Dbit2p2
230855. Dbit30p2
230856. Dbit31p2
230857. Dbit3p1
230858. Dbit3p2
230859. Dbl_addition
230860. Dbl_allp1
230861. Dbl_allp2
230862. Dbl_and_signs
230863. Dbl_arithrightshiftby1
230864. Dbl_clear_exponent_set_hidden
230865. Dbl_clear_sign
230866. Dbl_clear_signexponent
230867. Dbl_clear_signexponent_set_hidden
230868. Dbl_copyfromptr
230869. Dbl_copyto_dblext
230870. Dbl_copytoint_exponentmantissap1
230871. Dbl_copytoptr
230872. Dbl_decrement
230873. Dbl_denormalize
230874. Dbl_exponent
230875. Dbl_exponentmantissap1
230876. Dbl_firstword
230877. Dbl_fix_overshift
230878. Dbl_fourthword
230879. Dbl_hidden
230880. Dbl_hiddenhigh3mantissa
230881. Dbl_increment
230882. Dbl_increment_mantissa
230883. Dbl_invert_sign
230884. Dbl_is_signalingnan
230885. Dbl_isequal
230886. Dbl_isgreaterthan
230887. Dbl_isinexact_to_fix
230888. Dbl_isinexact_to_unsigned
230889. Dbl_isinfinity
230890. Dbl_isinfinity_exponent
230891. Dbl_islessthan
230892. Dbl_ismagnitudeless
230893. Dbl_isnan
230894. Dbl_isnotgreaterthan
230895. Dbl_isnotinfinity_exponent
230896. Dbl_isnotlessthan
230897. Dbl_isnotnan
230898. Dbl_isnotzero
230899. Dbl_isnotzero_exponent
230900. Dbl_isnotzero_exponentmantissa
230901. Dbl_isnotzero_hiddenhigh7mantissa
230902. Dbl_isnotzero_low4p2
230903. Dbl_isnotzero_mantissa
230904. Dbl_isnotzero_mantissap1
230905. Dbl_isnotzero_mantissap2
230906. Dbl_isone_hidden
230907. Dbl_isone_hiddenoverflow
230908. Dbl_isone_lowmantissap1
230909. Dbl_isone_lowmantissap2
230910. Dbl_isone_roundbit
230911. Dbl_isone_sign
230912. Dbl_isone_signaling
230913. Dbl_isone_stickybit
230914. Dbl_isoverflow_to_int
230915. Dbl_iszero
230916. Dbl_iszero_allp1
230917. Dbl_iszero_allp2
230918. Dbl_iszero_exponent
230919. Dbl_iszero_exponentmantissa
230920. Dbl_iszero_hidden
230921. Dbl_iszero_hiddenhigh3mantissa
230922. Dbl_iszero_hiddenhigh7mantissa
230923. Dbl_iszero_hiddenoverflow
230924. Dbl_iszero_mantissa
230925. Dbl_iszero_sign
230926. Dbl_leftshift
230927. Dbl_leftshiftby1
230928. Dbl_leftshiftby1_withextent
230929. Dbl_leftshiftby2
230930. Dbl_leftshiftby3
230931. Dbl_leftshiftby4
230932. Dbl_leftshiftby7
230933. Dbl_leftshiftby8
230934. Dbl_lowmantissap2
230935. Dbl_makequietnan
230936. Dbl_makesignalingnan
230937. Dbl_mantissap1
230938. Dbl_mantissap2
230939. Dbl_normalize
230940. Dbl_or_signs
230941. Dbl_right_align
230942. Dbl_rightshift
230943. Dbl_rightshift_exponentmantissa
230944. Dbl_rightshiftby1
230945. Dbl_rightshiftby1_withextent
230946. Dbl_rightshiftby2
230947. Dbl_rightshiftby4
230948. Dbl_rightshiftby8
230949. Dbl_roundnearest_from_dint
230950. Dbl_roundnearest_from_duint
230951. Dbl_secondword
230952. Dbl_set_exponent
230953. Dbl_set_exponentmantissa
230954. Dbl_set_exponentmantissap1
230955. Dbl_set_mantissa
230956. Dbl_set_mantissap1
230957. Dbl_set_mantissap2
230958. Dbl_set_quiet
230959. Dbl_set_sign
230960. Dbl_sethigh4bits
230961. Dbl_setinfinity
230962. Dbl_setinfinity_exponent
230963. Dbl_setinfinity_exponentmantissa
230964. Dbl_setinfinitynegative
230965. Dbl_setinfinitypositive
230966. Dbl_setlargest
230967. Dbl_setlargest_exponentmantissa
230968. Dbl_setlargestnegative
230969. Dbl_setlargestpositive
230970. Dbl_setnegativeinfinity
230971. Dbl_setnegativezero
230972. Dbl_setnegativezerop1
230973. Dbl_setone_lowmantissap2
230974. Dbl_setone_sign
230975. Dbl_setoverflow
230976. Dbl_setwrapped_exponent
230977. Dbl_setzero
230978. Dbl_setzero_exponent
230979. Dbl_setzero_exponentmantissa
230980. Dbl_setzero_exponentmantissap1
230981. Dbl_setzero_mantissa
230982. Dbl_setzero_mantissap1
230983. Dbl_setzero_mantissap2
230984. Dbl_setzero_sign
230985. Dbl_setzerop1
230986. Dbl_setzerop2
230987. Dbl_sign
230988. Dbl_signexponent
230989. Dbl_signextendedsign
230990. Dbl_subtract
230991. Dbl_subtract_withextension
230992. Dbl_swap_lower
230993. Dbl_thirdword
230994. Dbl_to_sgl_denormalized
230995. Dbl_to_sgl_exponent
230996. Dbl_to_sgl_mantissa
230997. Dbl_xorfromintp1
230998. Dbl_xortointp1
230999. Dblext_addition
231000. Dblext_arithrightshiftby1
231001. Dblext_clear_sign
231002. Dblext_clear_signexponent
231003. Dblext_clear_signexponent_set_hidden
231004. Dblext_copy
231005. Dblext_copytoint_exponentmantissap1
231006. Dblext_denormalize
231007. Dblext_ismagnitudeless
231008. Dblext_isnotzero_low31p3
231009. Dblext_isnotzero_mantissap3
231010. Dblext_isnotzero_mantissap4
231011. Dblext_isone_hidden
231012. Dblext_isone_highp3
231013. Dblext_isone_lowp2
231014. Dblext_iszero
231015. Dblext_leftshiftby1
231016. Dblext_leftshiftby2
231017. Dblext_leftshiftby3
231018. Dblext_leftshiftby4
231019. Dblext_leftshiftby8
231020. Dblext_right_align
231021. Dblext_rightshiftby1
231022. Dblext_rightshiftby4
231023. Dblext_set_sign
231024. Dblext_setone_lowmantissap4
231025. Dblext_setzero
231026. Dblext_subtract
231027. Dblext_swap_lower
231028. Dblext_xorfromintp1
231029. Dblext_xortointp1
231030. Ddr2FbdimmMemType
231031. Ddr2MemType
231032. Ddr3MemType
231033. Ddr4MemType
231034. DdrMemType
231035. DeActivateBAEntry
231036. DeInitLed871x
231037. Debounce_DIS1
231038. Debounce_DIS2
231039. Debounce_DIS3
231040. DebugBlockId
231041. DebugBlockId_BY16
231042. DebugBlockId_BY2
231043. DebugBlockId_BY4
231044. DebugBlockId_BY8
231045. DebugBlockId_OLD
231046. DebugCtrl
231047. DebugCtrl0
231048. DebugCtrl1
231049. DebugException
231050. DecodeH323_UserInformation
231051. DecodeMultimediaSystemControlMessage
231052. DecodeQ931
231053. DecodeRasMessage
231054. DecompressBand23
231055. DecryptBuf
231056. DefaultLogPageSize
231057. Default_BI
231058. Default_Fsync
231059. DelPIDFilter
231060. DelayValue
231061. DeleteMidQEntry
231062. Delif
231063. DeliverQ
231064. Delse
231065. Dendif
231066. Deposit_dexponent
231067. Deposit_dexponentmantissap1
231068. Deposit_dextlowp4
231069. Deposit_dhigh2mantissa
231070. Deposit_dhigh4p1
231071. Deposit_dlowp1
231072. Deposit_dlowp2
231073. Deposit_dmantissap1
231074. Deposit_dsign
231075. Deposit_dsignexponent
231076. Deposit_sexponent
231077. Deposit_sexponentmantissa
231078. Deposit_shigh2mantissa
231079. Deposit_shigh4
231080. Deposit_slow
231081. Deposit_smantissa
231082. Deposit_ssign
231083. Deposit_ssignexponent
231084. DepthArray
231085. DepthFormat
231086. DesRxColl
231087. DescEndPacket
231088. DescEndPkt
231089. DescEndRing
231090. DescIntr
231091. DescIntrOnDMADone
231092. DescIntrOnTx
231093. DescMore
231094. DescNoCRC
231095. DescOwn
231096. DescOwned
231097. DescPktOK
231098. DescRxAbort
231099. DescRxAlign
231100. DescRxCRC
231101. DescRxDest
231102. DescRxInvalid
231103. DescRxLong
231104. DescRxLoop
231105. DescRxOver
231106. DescRxRunt
231107. DescSizeMask
231108. DescSkipLen
231109. DescStartPkt
231110. DescTag
231111. DescTxAbort
231112. DescTxCarrier
231113. DescTxCollCount
231114. DescTxDefer
231115. DescTxExcColl
231116. DescTxExcDefer
231117. DescTxFIFO
231118. DescTxOOWCol
231119. DescUseLink
231120. DescWholePkt
231121. DestroyOSDWindow
231122. Dev_InRequest
231123. Dev_Request
231124. DeviceCtlBlk
231125. DeviceOutRequest
231126. DevicePresent
231127. DeviceRequest
231128. Dexponent
231129. Dexponentmantissap1
231130. Dextallp1
231131. Dextallp2
231132. Dextallp3
231133. Dextallp4
231134. Dexthiddenoverflow
231135. Dexthighp3
231136. Dextlow31p3
231137. Dextlowp2
231138. Dfalse
231139. Dhdet_Hdef
231140. Dhdet_Hdes
231141. Dhidden
231142. Dhiddenhigh3mantissa
231143. Dhiddenhigh7mantissa
231144. Dhiddenoverflow
231145. Dhigh2mantissa
231146. Dhigh31p1
231147. Dhigh31p2
231148. Dhigh4p1
231149. Dhighp1
231150. Dhighp2
231151. Dht01_Hbps
231152. Dht01_Ht
231153. Dht02_Has
231154. Dht02_Hlbs
231155. Dht03_Hfps
231156. Dht03_Hrbs
231157. DiS01
231158. DiS02
231159. DiS03
231160. DiS04
231161. DiS05
231162. DiS06
231163. DiS07
231164. DiS08
231165. DiS09
231166. DiS10
231167. DiS11
231168. DiagBufferPostReply_t
231169. DiagBufferPostRequest_t
231170. DiagDataUploadHeader_t
231171. DiagReleaseReply_t
231172. DiagReleaseRequest_t
231173. DiagStatus_AddressConflict
231174. DiagStatus_AddressFailure
231175. DiagStatus_CantAssignPciIoAddr
231176. DiagStatus_CantAssignPciIrq
231177. DiagStatus_CantAssignPciMemAddr
231178. DiagStatus_CantAssignPciResources
231179. DiagStatus_DmaConflict
231180. DiagStatus_DmaFailure
231181. DiagStatus_IrqConflict
231182. DiagStatus_IrqFailure
231183. DiagStatus_MemoryError
231184. DiagStatus_OK
231185. DiagStatus_PciAdapterNotFound
231186. DiagnosticReg
231187. Digiface
231188. Dint_copyfromptr
231189. Dint_copytoptr
231190. Dint_decrement
231191. Dint_from_dbl_mantissa
231192. Dint_from_sgl_mantissa
231193. Dint_increment
231194. Dint_isinexact_to_dbl
231195. Dint_isinexact_to_sgl
231196. Dint_isone_lowp2
231197. Dint_negate
231198. Dint_set_minint
231199. Dint_setone_sign
231200. Dint_setzero
231201. Dintp1
231202. Dintp2
231203. DisableAlign
231204. DisableAll
231205. DisableAutoTx
231206. DisableCRT2Display
231207. DisableInterrupt8723BSdio
231208. DisableLinkPulse
231209. DisablePolCor
231210. DisableRamdacOutput
231211. DisableRecv
231212. DisableVGA
231213. Disable_IRQ
231214. DisconnectCtrlEx_param
231215. Disconnected
231216. DiseqcSendBit
231217. DiseqcSendByte
231218. DiskController
231219. DiskOnChip
231220. DiskPeripheral
231221. DispDevicePriorityInfo
231222. DispOutInfo
231223. Disp_Pll_M
231224. Disp_Pll_N
231225. Disp_Pll_P
231226. DisplayClockTable_t
231227. DisplayConfig
231228. DisplayController
231229. DisplayPipeConfiguration
231230. Divide
231231. Divisionbyzeroflag
231232. Divisionbyzerotrap
231233. Dlink350c
231234. Dllctrl_Rld_Adrln
231235. Dlow31p1
231236. Dlow31p2
231237. Dlow4p2
231238. Dlowp1
231239. Dlowp2
231240. DmaCmd_AbortAllChannels
231241. DmaCmd_AbortRxChannel
231242. DmaCmd_AbortTxChannel
231243. DmaCmd_ContinueAllChannels
231244. DmaCmd_ContinueRxChannel
231245. DmaCmd_ContinueTxChannel
231246. DmaCmd_InitAllChannels
231247. DmaCmd_InitRxChannel
231248. DmaCmd_InitTxChannel
231249. DmaCmd_Null
231250. DmaCmd_PauseAllChannels
231251. DmaCmd_PauseRxChannel
231252. DmaCmd_PauseTxChannel
231253. DmaCmd_ResetAllChannels
231254. DmaCmd_ResetHighestDmaIus
231255. DmaCmd_ResetRxChannel
231256. DmaCmd_ResetTxChannel
231257. DmaCmd_StartAllChannels
231258. DmaCmd_StartRxChannel
231259. DmaCmd_StartTxChannel
231260. DmaCommandFib
231261. Dmantissap1
231262. Dmantissap2
231263. Dmctrl_Burstlen
231264. Dmctrl_D_Thrhld
231265. Dmctrl_Uv_Thrhld
231266. Dmctrl_V_Thrhld
231267. DoC_2k_CDSN_IO
231268. DoC_2k_ECCStatus
231269. DoC_AliasResolution
231270. DoC_CDSNControl
231271. DoC_CDSNDeviceSelect
231272. DoC_CDSNSlowIO
231273. DoC_ChipID
231274. DoC_ConfigInput
231275. DoC_DOCControl
231276. DoC_DOCStatus
231277. DoC_Delay
231278. DoC_ECCConf
231279. DoC_ECCSyndrome0
231280. DoC_ECCSyndrome1
231281. DoC_ECCSyndrome2
231282. DoC_ECCSyndrome3
231283. DoC_ECCSyndrome4
231284. DoC_ECCSyndrome5
231285. DoC_FloorSelect
231286. DoC_LastDataRead
231287. DoC_Mil_CDSN_IO
231288. DoC_Mplus_AccessStatus
231289. DoC_Mplus_AliasResolution
231290. DoC_Mplus_Configuration
231291. DoC_Mplus_CtrlConfirm
231292. DoC_Mplus_DOCControl
231293. DoC_Mplus_DeviceSelect
231294. DoC_Mplus_DownloadStatus
231295. DoC_Mplus_ECCConf
231296. DoC_Mplus_ECCSyndrome0
231297. DoC_Mplus_ECCSyndrome1
231298. DoC_Mplus_ECCSyndrome2
231299. DoC_Mplus_ECCSyndrome3
231300. DoC_Mplus_ECCSyndrome4
231301. DoC_Mplus_ECCSyndrome5
231302. DoC_Mplus_FlashAddress
231303. DoC_Mplus_FlashCmd
231304. DoC_Mplus_FlashControl
231305. DoC_Mplus_FlashData0
231306. DoC_Mplus_FlashData1
231307. DoC_Mplus_FlashSelect
231308. DoC_Mplus_LastDataRead
231309. DoC_Mplus_LastDataRead1
231310. DoC_Mplus_NOP
231311. DoC_Mplus_OutputControl
231312. DoC_Mplus_Power
231313. DoC_Mplus_ReadPipeInit
231314. DoC_Mplus_Toggle
231315. DoC_Mplus_WritePipeTerm
231316. DoC_NOP
231317. DoC_ReadPipeInit
231318. DoC_Sig1
231319. DoC_Sig2
231320. DoC_WaitReady
231321. DoC_WritePipeTerm
231322. DoC_is_2000
231323. DoC_is_Millennium
231324. DoC_is_MillenniumPlus
231325. DoIQK_8723B
231326. DoReserved
231327. Dodmsk_Mask_B
231328. Dodmsk_Mask_G
231329. Dodmsk_Mask_R
231330. DontExpandLCD
231331. DontExpandLCDShift
231332. DontUseEeprom
231333. DoorBellAdapterNormCmdNotFull
231334. DoorBellAdapterNormCmdReady
231335. DoorBellAdapterNormRespNotFull
231336. DoorBellAdapterNormRespReady
231337. DoorBellAifPending
231338. DoorBellPrintfDone
231339. DoorBellPrintfReady
231340. DoorBellSyncCmdAvailable
231341. DoorbellClrReg_p
231342. DoorbellReg_p
231343. DoorbellReg_s
231344. DoubleCPDO
231345. DoubleScanMode
231346. DownComplete
231347. DownCounter
231348. DownListPtr
231349. DownStall
231350. DownUnstall
231351. DownloadMicrocode
231352. Dpm0PgNbPsHi
231353. Dpm0PgNbPsHi_MASK
231354. Dpm0PgNbPsHi_SHIFT
231355. Dpm0PgNbPsLo
231356. Dpm0PgNbPsLo_MASK
231357. Dpm0PgNbPsLo_SHIFT
231358. DpmActivityMonitorCoeffExt_t
231359. DpmActivityMonitorCoeffInt_t
231360. DpmClock_t
231361. DpmClocks_t
231362. DpmDescriptor_t
231363. DpmXNbPsHi
231364. DpmXNbPsHi_MASK
231365. DpmXNbPsHi_SHIFT
231366. DpmXNbPsLo
231367. DpmXNbPsLo_MASK
231368. DpmXNbPsLo_SHIFT
231369. DpramBootSpooler_tag
231370. Dprintf
231371. Dprintk
231372. DramMemType
231373. DrawBlock
231374. DrawLine
231375. DriverInterface
231376. DriverLoaded
231377. DriverMode
231378. DriverSmuConfig_t
231379. DriverTune
231380. DriverVer_type
231381. DroopInt_t
231382. DrumkitFileID
231383. Dsctrl_Updwait
231384. Dsign
231385. Dsignaling
231386. Dsignalingnan
231387. Dsignedhigh31p1
231388. Dsignedsign
231389. Dsignexponent
231390. DspInterrupt
231391. DstAcc
231392. DstAccLo
231393. DstDI
231394. DstDX
231395. DstImmUByte
231396. DstMask
231397. DstMem
231398. DstMem16
231399. DstMem64
231400. DstReg
231401. DstShift
231402. DstXacc
231403. Duint_copyfromptr
231404. Duint_copytoptr
231405. Duint_from_dbl_mantissa
231406. Duint_from_sgl_mantissa
231407. Duint_increment
231408. Duint_isinexact_to_dbl
231409. Duint_isinexact_to_sgl
231410. Duint_isone_lowp2
231411. Duint_setzero
231412. Duintp1
231413. Duintp2
231414. DumpStats
231415. DuplexSelect
231416. DvbDmxFilterCallback
231417. DvcGetQinfo
231418. DvcPutScsiQ
231419. DvcV6
231420. Dvdet_Vdef
231421. Dvdet_Vdes
231422. Dvectrl_Vevent
231423. Dvectrl_Vfetch
231424. Dvlnum_Vline
231425. Dvt01_Vbps
231426. Dvt01_Vt
231427. Dvt02_Vas
231428. Dvt02_Vtbs
231429. Dvt03_Vbbs
231430. Dvt03_Vfps
231431. DwordAlign
231432. DxGRPH_PFLIP_INT_CLEAR
231433. DxGRPH_PFLIP_INT_MASK
231434. DxGRPH_PFLIP_INT_OCCURRED
231435. DxGRPH_PFLIP_INT_TYPE
231436. DxMODE_INT_MASK
231437. DxMODE_VBLANK_ACK
231438. DxMODE_VBLANK_INTERRUPT
231439. DxMODE_VBLANK_INTERRUPT_TYPE
231440. DxMODE_VBLANK_OCCURRED
231441. DxMODE_VBLANK_STAT
231442. DxMODE_VLINE_ACK
231443. DxMODE_VLINE_INTERRUPT
231444. DxMODE_VLINE_INTERRUPT_TYPE
231445. DxMODE_VLINE_OCCURRED
231446. DxMODE_VLINE_STAT
231447. DynPage_addr
231448. DynamicClockGating